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TOMOYO Linux Cross Reference
Linux/include/linux/mtd/spi-nor.h

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  1 /*
  2  * Copyright (C) 2014 Freescale Semiconductor, Inc.
  3  *
  4  * This program is free software; you can redistribute it and/or modify
  5  * it under the terms of the GNU General Public License as published by
  6  * the Free Software Foundation; either version 2 of the License, or
  7  * (at your option) any later version.
  8  */
  9 
 10 #ifndef __LINUX_MTD_SPI_NOR_H
 11 #define __LINUX_MTD_SPI_NOR_H
 12 
 13 #include <linux/bitops.h>
 14 #include <linux/mtd/cfi.h>
 15 #include <linux/mtd/mtd.h>
 16 
 17 /*
 18  * Manufacturer IDs
 19  *
 20  * The first byte returned from the flash after sending opcode SPINOR_OP_RDID.
 21  * Sometimes these are the same as CFI IDs, but sometimes they aren't.
 22  */
 23 #define SNOR_MFR_ATMEL          CFI_MFR_ATMEL
 24 #define SNOR_MFR_GIGADEVICE     0xc8
 25 #define SNOR_MFR_INTEL          CFI_MFR_INTEL
 26 #define SNOR_MFR_MICRON         CFI_MFR_ST /* ST Micro <--> Micron */
 27 #define SNOR_MFR_MACRONIX       CFI_MFR_MACRONIX
 28 #define SNOR_MFR_SPANSION       CFI_MFR_AMD
 29 #define SNOR_MFR_SST            CFI_MFR_SST
 30 #define SNOR_MFR_WINBOND        0xef /* Also used by some Spansion */
 31 
 32 /*
 33  * Note on opcode nomenclature: some opcodes have a format like
 34  * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
 35  * of I/O lines used for the opcode, address, and data (respectively). The
 36  * FUNCTION has an optional suffix of '4', to represent an opcode which
 37  * requires a 4-byte (32-bit) address.
 38  */
 39 
 40 /* Flash opcodes. */
 41 #define SPINOR_OP_WREN          0x06    /* Write enable */
 42 #define SPINOR_OP_RDSR          0x05    /* Read status register */
 43 #define SPINOR_OP_WRSR          0x01    /* Write status register 1 byte */
 44 #define SPINOR_OP_RDSR2         0x3f    /* Read status register 2 */
 45 #define SPINOR_OP_WRSR2         0x3e    /* Write status register 2 */
 46 #define SPINOR_OP_READ          0x03    /* Read data bytes (low frequency) */
 47 #define SPINOR_OP_READ_FAST     0x0b    /* Read data bytes (high frequency) */
 48 #define SPINOR_OP_READ_1_1_2    0x3b    /* Read data bytes (Dual Output SPI) */
 49 #define SPINOR_OP_READ_1_2_2    0xbb    /* Read data bytes (Dual I/O SPI) */
 50 #define SPINOR_OP_READ_1_1_4    0x6b    /* Read data bytes (Quad Output SPI) */
 51 #define SPINOR_OP_READ_1_4_4    0xeb    /* Read data bytes (Quad I/O SPI) */
 52 #define SPINOR_OP_PP            0x02    /* Page program (up to 256 bytes) */
 53 #define SPINOR_OP_PP_1_1_4      0x32    /* Quad page program */
 54 #define SPINOR_OP_PP_1_4_4      0x38    /* Quad page program */
 55 #define SPINOR_OP_BE_4K         0x20    /* Erase 4KiB block */
 56 #define SPINOR_OP_BE_4K_PMC     0xd7    /* Erase 4KiB block on PMC chips */
 57 #define SPINOR_OP_BE_32K        0x52    /* Erase 32KiB block */
 58 #define SPINOR_OP_CHIP_ERASE    0xc7    /* Erase whole flash chip */
 59 #define SPINOR_OP_SE            0xd8    /* Sector erase (usually 64KiB) */
 60 #define SPINOR_OP_RDID          0x9f    /* Read JEDEC ID */
 61 #define SPINOR_OP_RDSFDP        0x5a    /* Read SFDP */
 62 #define SPINOR_OP_RDCR          0x35    /* Read configuration register */
 63 #define SPINOR_OP_RDFSR         0x70    /* Read flag status register */
 64 
 65 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
 66 #define SPINOR_OP_READ_4B       0x13    /* Read data bytes (low frequency) */
 67 #define SPINOR_OP_READ_FAST_4B  0x0c    /* Read data bytes (high frequency) */
 68 #define SPINOR_OP_READ_1_1_2_4B 0x3c    /* Read data bytes (Dual Output SPI) */
 69 #define SPINOR_OP_READ_1_2_2_4B 0xbc    /* Read data bytes (Dual I/O SPI) */
 70 #define SPINOR_OP_READ_1_1_4_4B 0x6c    /* Read data bytes (Quad Output SPI) */
 71 #define SPINOR_OP_READ_1_4_4_4B 0xec    /* Read data bytes (Quad I/O SPI) */
 72 #define SPINOR_OP_PP_4B         0x12    /* Page program (up to 256 bytes) */
 73 #define SPINOR_OP_PP_1_1_4_4B   0x34    /* Quad page program */
 74 #define SPINOR_OP_PP_1_4_4_4B   0x3e    /* Quad page program */
 75 #define SPINOR_OP_BE_4K_4B      0x21    /* Erase 4KiB block */
 76 #define SPINOR_OP_BE_32K_4B     0x5c    /* Erase 32KiB block */
 77 #define SPINOR_OP_SE_4B         0xdc    /* Sector erase (usually 64KiB) */
 78 
 79 /* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */
 80 #define SPINOR_OP_READ_1_1_1_DTR        0x0d
 81 #define SPINOR_OP_READ_1_2_2_DTR        0xbd
 82 #define SPINOR_OP_READ_1_4_4_DTR        0xed
 83 
 84 #define SPINOR_OP_READ_1_1_1_DTR_4B     0x0e
 85 #define SPINOR_OP_READ_1_2_2_DTR_4B     0xbe
 86 #define SPINOR_OP_READ_1_4_4_DTR_4B     0xee
 87 
 88 /* Used for SST flashes only. */
 89 #define SPINOR_OP_BP            0x02    /* Byte program */
 90 #define SPINOR_OP_WRDI          0x04    /* Write disable */
 91 #define SPINOR_OP_AAI_WP        0xad    /* Auto address increment word program */
 92 
 93 /* Used for S3AN flashes only */
 94 #define SPINOR_OP_XSE           0x50    /* Sector erase */
 95 #define SPINOR_OP_XPP           0x82    /* Page program */
 96 #define SPINOR_OP_XRDSR         0xd7    /* Read status register */
 97 
 98 #define XSR_PAGESIZE            BIT(0)  /* Page size in Po2 or Linear */
 99 #define XSR_RDY                 BIT(7)  /* Ready */
100 
101 
102 /* Used for Macronix and Winbond flashes. */
103 #define SPINOR_OP_EN4B          0xb7    /* Enter 4-byte mode */
104 #define SPINOR_OP_EX4B          0xe9    /* Exit 4-byte mode */
105 
106 /* Used for Spansion flashes only. */
107 #define SPINOR_OP_BRWR          0x17    /* Bank register write */
108 #define SPINOR_OP_CLSR          0x30    /* Clear status register 1 */
109 
110 /* Used for Micron flashes only. */
111 #define SPINOR_OP_RD_EVCR      0x65    /* Read EVCR register */
112 #define SPINOR_OP_WD_EVCR      0x61    /* Write EVCR register */
113 
114 /* Status Register bits. */
115 #define SR_WIP                  BIT(0)  /* Write in progress */
116 #define SR_WEL                  BIT(1)  /* Write enable latch */
117 /* meaning of other SR_* bits may differ between vendors */
118 #define SR_BP0                  BIT(2)  /* Block protect 0 */
119 #define SR_BP1                  BIT(3)  /* Block protect 1 */
120 #define SR_BP2                  BIT(4)  /* Block protect 2 */
121 #define SR_TB                   BIT(5)  /* Top/Bottom protect */
122 #define SR_SRWD                 BIT(7)  /* SR write protect */
123 /* Spansion/Cypress specific status bits */
124 #define SR_E_ERR                BIT(5)
125 #define SR_P_ERR                BIT(6)
126 
127 #define SR_QUAD_EN_MX           BIT(6)  /* Macronix Quad I/O */
128 
129 /* Enhanced Volatile Configuration Register bits */
130 #define EVCR_QUAD_EN_MICRON     BIT(7)  /* Micron Quad I/O */
131 
132 /* Flag Status Register bits */
133 #define FSR_READY               BIT(7)
134 
135 /* Configuration Register bits. */
136 #define CR_QUAD_EN_SPAN         BIT(1)  /* Spansion Quad I/O */
137 
138 /* Status Register 2 bits. */
139 #define SR2_QUAD_EN_BIT7        BIT(7)
140 
141 /* Supported SPI protocols */
142 #define SNOR_PROTO_INST_MASK    GENMASK(23, 16)
143 #define SNOR_PROTO_INST_SHIFT   16
144 #define SNOR_PROTO_INST(_nbits) \
145         ((((unsigned long)(_nbits)) << SNOR_PROTO_INST_SHIFT) & \
146          SNOR_PROTO_INST_MASK)
147 
148 #define SNOR_PROTO_ADDR_MASK    GENMASK(15, 8)
149 #define SNOR_PROTO_ADDR_SHIFT   8
150 #define SNOR_PROTO_ADDR(_nbits) \
151         ((((unsigned long)(_nbits)) << SNOR_PROTO_ADDR_SHIFT) & \
152          SNOR_PROTO_ADDR_MASK)
153 
154 #define SNOR_PROTO_DATA_MASK    GENMASK(7, 0)
155 #define SNOR_PROTO_DATA_SHIFT   0
156 #define SNOR_PROTO_DATA(_nbits) \
157         ((((unsigned long)(_nbits)) << SNOR_PROTO_DATA_SHIFT) & \
158          SNOR_PROTO_DATA_MASK)
159 
160 #define SNOR_PROTO_IS_DTR       BIT(24) /* Double Transfer Rate */
161 
162 #define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits)   \
163         (SNOR_PROTO_INST(_inst_nbits) |                         \
164          SNOR_PROTO_ADDR(_addr_nbits) |                         \
165          SNOR_PROTO_DATA(_data_nbits))
166 #define SNOR_PROTO_DTR(_inst_nbits, _addr_nbits, _data_nbits)   \
167         (SNOR_PROTO_IS_DTR |                                    \
168          SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits))
169 
170 enum spi_nor_protocol {
171         SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1),
172         SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2),
173         SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4),
174         SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8),
175         SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2),
176         SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4),
177         SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8),
178         SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2, 2),
179         SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4),
180         SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8),
181 
182         SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1),
183         SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2),
184         SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4),
185         SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8),
186 };
187 
188 static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)
189 {
190         return !!(proto & SNOR_PROTO_IS_DTR);
191 }
192 
193 static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)
194 {
195         return ((unsigned long)(proto & SNOR_PROTO_INST_MASK)) >>
196                 SNOR_PROTO_INST_SHIFT;
197 }
198 
199 static inline u8 spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)
200 {
201         return ((unsigned long)(proto & SNOR_PROTO_ADDR_MASK)) >>
202                 SNOR_PROTO_ADDR_SHIFT;
203 }
204 
205 static inline u8 spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)
206 {
207         return ((unsigned long)(proto & SNOR_PROTO_DATA_MASK)) >>
208                 SNOR_PROTO_DATA_SHIFT;
209 }
210 
211 static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto)
212 {
213         return spi_nor_get_protocol_data_nbits(proto);
214 }
215 
216 #define SPI_NOR_MAX_CMD_SIZE    8
217 enum spi_nor_ops {
218         SPI_NOR_OPS_READ = 0,
219         SPI_NOR_OPS_WRITE,
220         SPI_NOR_OPS_ERASE,
221         SPI_NOR_OPS_LOCK,
222         SPI_NOR_OPS_UNLOCK,
223 };
224 
225 enum spi_nor_option_flags {
226         SNOR_F_USE_FSR          = BIT(0),
227         SNOR_F_HAS_SR_TB        = BIT(1),
228         SNOR_F_NO_OP_CHIP_ERASE = BIT(2),
229         SNOR_F_S3AN_ADDR_DEFAULT = BIT(3),
230         SNOR_F_READY_XSR_RDY    = BIT(4),
231         SNOR_F_USE_CLSR         = BIT(5),
232 };
233 
234 /**
235  * struct flash_info - Forward declaration of a structure used internally by
236  *                     spi_nor_scan()
237  */
238 struct flash_info;
239 
240 /**
241  * struct spi_nor - Structure for defining a the SPI NOR layer
242  * @mtd:                point to a mtd_info structure
243  * @lock:               the lock for the read/write/erase/lock/unlock operations
244  * @dev:                point to a spi device, or a spi nor controller device.
245  * @info:               spi-nor part JDEC MFR id and other info
246  * @page_size:          the page size of the SPI NOR
247  * @addr_width:         number of address bytes
248  * @erase_opcode:       the opcode for erasing a sector
249  * @read_opcode:        the read opcode
250  * @read_dummy:         the dummy needed by the read operation
251  * @program_opcode:     the program opcode
252  * @sst_write_second:   used by the SST write operation
253  * @flags:              flag options for the current SPI-NOR (SNOR_F_*)
254  * @read_proto:         the SPI protocol for read operations
255  * @write_proto:        the SPI protocol for write operations
256  * @reg_proto           the SPI protocol for read_reg/write_reg/erase operations
257  * @cmd_buf:            used by the write_reg
258  * @prepare:            [OPTIONAL] do some preparations for the
259  *                      read/write/erase/lock/unlock operations
260  * @unprepare:          [OPTIONAL] do some post work after the
261  *                      read/write/erase/lock/unlock operations
262  * @read_reg:           [DRIVER-SPECIFIC] read out the register
263  * @write_reg:          [DRIVER-SPECIFIC] write data to the register
264  * @read:               [DRIVER-SPECIFIC] read data from the SPI NOR
265  * @write:              [DRIVER-SPECIFIC] write data to the SPI NOR
266  * @erase:              [DRIVER-SPECIFIC] erase a sector of the SPI NOR
267  *                      at the offset @offs; if not provided by the driver,
268  *                      spi-nor will send the erase opcode via write_reg()
269  * @flash_lock:         [FLASH-SPECIFIC] lock a region of the SPI NOR
270  * @flash_unlock:       [FLASH-SPECIFIC] unlock a region of the SPI NOR
271  * @flash_is_locked:    [FLASH-SPECIFIC] check if a region of the SPI NOR is
272  * @quad_enable:        [FLASH-SPECIFIC] enables SPI NOR quad mode
273  *                      completely locked
274  * @priv:               the private data
275  */
276 struct spi_nor {
277         struct mtd_info         mtd;
278         struct mutex            lock;
279         struct device           *dev;
280         const struct flash_info *info;
281         u32                     page_size;
282         u8                      addr_width;
283         u8                      erase_opcode;
284         u8                      read_opcode;
285         u8                      read_dummy;
286         u8                      program_opcode;
287         enum spi_nor_protocol   read_proto;
288         enum spi_nor_protocol   write_proto;
289         enum spi_nor_protocol   reg_proto;
290         bool                    sst_write_second;
291         u32                     flags;
292         u8                      cmd_buf[SPI_NOR_MAX_CMD_SIZE];
293 
294         int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
295         void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
296         int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
297         int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
298 
299         ssize_t (*read)(struct spi_nor *nor, loff_t from,
300                         size_t len, u_char *read_buf);
301         ssize_t (*write)(struct spi_nor *nor, loff_t to,
302                         size_t len, const u_char *write_buf);
303         int (*erase)(struct spi_nor *nor, loff_t offs);
304 
305         int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
306         int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
307         int (*flash_is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len);
308         int (*quad_enable)(struct spi_nor *nor);
309 
310         void *priv;
311 };
312 
313 static inline void spi_nor_set_flash_node(struct spi_nor *nor,
314                                           struct device_node *np)
315 {
316         mtd_set_of_node(&nor->mtd, np);
317 }
318 
319 static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor)
320 {
321         return mtd_get_of_node(&nor->mtd);
322 }
323 
324 /**
325  * struct spi_nor_hwcaps - Structure for describing the hardware capabilies
326  * supported by the SPI controller (bus master).
327  * @mask:               the bitmask listing all the supported hw capabilies
328  */
329 struct spi_nor_hwcaps {
330         u32     mask;
331 };
332 
333 /*
334  *(Fast) Read capabilities.
335  * MUST be ordered by priority: the higher bit position, the higher priority.
336  * As a matter of performances, it is relevant to use Octo SPI protocols first,
337  * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly
338  * (Slow) Read.
339  */
340 #define SNOR_HWCAPS_READ_MASK           GENMASK(14, 0)
341 #define SNOR_HWCAPS_READ                BIT(0)
342 #define SNOR_HWCAPS_READ_FAST           BIT(1)
343 #define SNOR_HWCAPS_READ_1_1_1_DTR      BIT(2)
344 
345 #define SNOR_HWCAPS_READ_DUAL           GENMASK(6, 3)
346 #define SNOR_HWCAPS_READ_1_1_2          BIT(3)
347 #define SNOR_HWCAPS_READ_1_2_2          BIT(4)
348 #define SNOR_HWCAPS_READ_2_2_2          BIT(5)
349 #define SNOR_HWCAPS_READ_1_2_2_DTR      BIT(6)
350 
351 #define SNOR_HWCAPS_READ_QUAD           GENMASK(10, 7)
352 #define SNOR_HWCAPS_READ_1_1_4          BIT(7)
353 #define SNOR_HWCAPS_READ_1_4_4          BIT(8)
354 #define SNOR_HWCAPS_READ_4_4_4          BIT(9)
355 #define SNOR_HWCAPS_READ_1_4_4_DTR      BIT(10)
356 
357 #define SNOR_HWCPAS_READ_OCTO           GENMASK(14, 11)
358 #define SNOR_HWCAPS_READ_1_1_8          BIT(11)
359 #define SNOR_HWCAPS_READ_1_8_8          BIT(12)
360 #define SNOR_HWCAPS_READ_8_8_8          BIT(13)
361 #define SNOR_HWCAPS_READ_1_8_8_DTR      BIT(14)
362 
363 /*
364  * Page Program capabilities.
365  * MUST be ordered by priority: the higher bit position, the higher priority.
366  * Like (Fast) Read capabilities, Octo/Quad SPI protocols are preferred to the
367  * legacy SPI 1-1-1 protocol.
368  * Note that Dual Page Programs are not supported because there is no existing
369  * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory
370  * implements such commands.
371  */
372 #define SNOR_HWCAPS_PP_MASK     GENMASK(22, 16)
373 #define SNOR_HWCAPS_PP          BIT(16)
374 
375 #define SNOR_HWCAPS_PP_QUAD     GENMASK(19, 17)
376 #define SNOR_HWCAPS_PP_1_1_4    BIT(17)
377 #define SNOR_HWCAPS_PP_1_4_4    BIT(18)
378 #define SNOR_HWCAPS_PP_4_4_4    BIT(19)
379 
380 #define SNOR_HWCAPS_PP_OCTO     GENMASK(22, 20)
381 #define SNOR_HWCAPS_PP_1_1_8    BIT(20)
382 #define SNOR_HWCAPS_PP_1_8_8    BIT(21)
383 #define SNOR_HWCAPS_PP_8_8_8    BIT(22)
384 
385 /**
386  * spi_nor_scan() - scan the SPI NOR
387  * @nor:        the spi_nor structure
388  * @name:       the chip type name
389  * @hwcaps:     the hardware capabilities supported by the controller driver
390  *
391  * The drivers can use this fuction to scan the SPI NOR.
392  * In the scanning, it will try to get all the necessary information to
393  * fill the mtd_info{} and the spi_nor{}.
394  *
395  * The chip type name can be provided through the @name parameter.
396  *
397  * Return: 0 for success, others for failure.
398  */
399 int spi_nor_scan(struct spi_nor *nor, const char *name,
400                  const struct spi_nor_hwcaps *hwcaps);
401 
402 #endif
403 

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