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TOMOYO Linux Cross Reference
Linux/include/linux/pci.h

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  1 /* SPDX-License-Identifier: GPL-2.0 */
  2 /*
  3  *      pci.h
  4  *
  5  *      PCI defines and function prototypes
  6  *      Copyright 1994, Drew Eckhardt
  7  *      Copyright 1997--1999 Martin Mares <mj@ucw.cz>
  8  *
  9  *      For more information, please consult the following manuals (look at
 10  *      http://www.pcisig.com/ for how to get them):
 11  *
 12  *      PCI BIOS Specification
 13  *      PCI Local Bus Specification
 14  *      PCI to PCI Bridge Specification
 15  *      PCI System Design Guide
 16  */
 17 #ifndef LINUX_PCI_H
 18 #define LINUX_PCI_H
 19 
 20 
 21 #include <linux/mod_devicetable.h>
 22 
 23 #include <linux/types.h>
 24 #include <linux/init.h>
 25 #include <linux/ioport.h>
 26 #include <linux/list.h>
 27 #include <linux/compiler.h>
 28 #include <linux/errno.h>
 29 #include <linux/kobject.h>
 30 #include <linux/atomic.h>
 31 #include <linux/device.h>
 32 #include <linux/interrupt.h>
 33 #include <linux/io.h>
 34 #include <linux/resource_ext.h>
 35 #include <uapi/linux/pci.h>
 36 
 37 #include <linux/pci_ids.h>
 38 
 39 /*
 40  * The PCI interface treats multi-function devices as independent
 41  * devices.  The slot/function address of each device is encoded
 42  * in a single byte as follows:
 43  *
 44  *      7:3 = slot
 45  *      2:0 = function
 46  *
 47  * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
 48  * In the interest of not exposing interfaces to user-space unnecessarily,
 49  * the following kernel-only defines are being added here.
 50  */
 51 #define PCI_DEVID(bus, devfn)  ((((u16)(bus)) << 8) | (devfn))
 52 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
 53 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
 54 
 55 /* pci_slot represents a physical slot */
 56 struct pci_slot {
 57         struct pci_bus *bus;            /* The bus this slot is on */
 58         struct list_head list;          /* node in list of slots on this bus */
 59         struct hotplug_slot *hotplug;   /* Hotplug info (migrate over time) */
 60         unsigned char number;           /* PCI_SLOT(pci_dev->devfn) */
 61         struct kobject kobj;
 62 };
 63 
 64 static inline const char *pci_slot_name(const struct pci_slot *slot)
 65 {
 66         return kobject_name(&slot->kobj);
 67 }
 68 
 69 /* File state for mmap()s on /proc/bus/pci/X/Y */
 70 enum pci_mmap_state {
 71         pci_mmap_io,
 72         pci_mmap_mem
 73 };
 74 
 75 /*
 76  *  For PCI devices, the region numbers are assigned this way:
 77  */
 78 enum {
 79         /* #0-5: standard PCI resources */
 80         PCI_STD_RESOURCES,
 81         PCI_STD_RESOURCE_END = 5,
 82 
 83         /* #6: expansion ROM resource */
 84         PCI_ROM_RESOURCE,
 85 
 86         /* device specific resources */
 87 #ifdef CONFIG_PCI_IOV
 88         PCI_IOV_RESOURCES,
 89         PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
 90 #endif
 91 
 92         /* resources assigned to buses behind the bridge */
 93 #define PCI_BRIDGE_RESOURCE_NUM 4
 94 
 95         PCI_BRIDGE_RESOURCES,
 96         PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
 97                                   PCI_BRIDGE_RESOURCE_NUM - 1,
 98 
 99         /* total resources associated with a PCI device */
100         PCI_NUM_RESOURCES,
101 
102         /* preserve this for compatibility */
103         DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
104 };
105 
106 /**
107  * enum pci_interrupt_pin - PCI INTx interrupt values
108  * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
109  * @PCI_INTERRUPT_INTA: PCI INTA pin
110  * @PCI_INTERRUPT_INTB: PCI INTB pin
111  * @PCI_INTERRUPT_INTC: PCI INTC pin
112  * @PCI_INTERRUPT_INTD: PCI INTD pin
113  *
114  * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
115  * PCI_INTERRUPT_PIN register.
116  */
117 enum pci_interrupt_pin {
118         PCI_INTERRUPT_UNKNOWN,
119         PCI_INTERRUPT_INTA,
120         PCI_INTERRUPT_INTB,
121         PCI_INTERRUPT_INTC,
122         PCI_INTERRUPT_INTD,
123 };
124 
125 /* The number of legacy PCI INTx interrupts */
126 #define PCI_NUM_INTX    4
127 
128 /*
129  * pci_power_t values must match the bits in the Capabilities PME_Support
130  * and Control/Status PowerState fields in the Power Management capability.
131  */
132 typedef int __bitwise pci_power_t;
133 
134 #define PCI_D0          ((pci_power_t __force) 0)
135 #define PCI_D1          ((pci_power_t __force) 1)
136 #define PCI_D2          ((pci_power_t __force) 2)
137 #define PCI_D3hot       ((pci_power_t __force) 3)
138 #define PCI_D3cold      ((pci_power_t __force) 4)
139 #define PCI_UNKNOWN     ((pci_power_t __force) 5)
140 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
141 
142 /* Remember to update this when the list above changes! */
143 extern const char *pci_power_names[];
144 
145 static inline const char *pci_power_name(pci_power_t state)
146 {
147         return pci_power_names[1 + (__force int) state];
148 }
149 
150 #define PCI_PM_D2_DELAY         200
151 #define PCI_PM_D3_WAIT          10
152 #define PCI_PM_D3COLD_WAIT      100
153 #define PCI_PM_BUS_WAIT         50
154 
155 /** The pci_channel state describes connectivity between the CPU and
156  *  the pci device.  If some PCI bus between here and the pci device
157  *  has crashed or locked up, this info is reflected here.
158  */
159 typedef unsigned int __bitwise pci_channel_state_t;
160 
161 enum pci_channel_state {
162         /* I/O channel is in normal state */
163         pci_channel_io_normal = (__force pci_channel_state_t) 1,
164 
165         /* I/O to channel is blocked */
166         pci_channel_io_frozen = (__force pci_channel_state_t) 2,
167 
168         /* PCI card is dead */
169         pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
170 };
171 
172 typedef unsigned int __bitwise pcie_reset_state_t;
173 
174 enum pcie_reset_state {
175         /* Reset is NOT asserted (Use to deassert reset) */
176         pcie_deassert_reset = (__force pcie_reset_state_t) 1,
177 
178         /* Use #PERST to reset PCIe device */
179         pcie_warm_reset = (__force pcie_reset_state_t) 2,
180 
181         /* Use PCIe Hot Reset to reset device */
182         pcie_hot_reset = (__force pcie_reset_state_t) 3
183 };
184 
185 typedef unsigned short __bitwise pci_dev_flags_t;
186 enum pci_dev_flags {
187         /* INTX_DISABLE in PCI_COMMAND register disables MSI
188          * generation too.
189          */
190         PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
191         /* Device configuration is irrevocably lost if disabled into D3 */
192         PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
193         /* Provide indication device is assigned by a Virtual Machine Manager */
194         PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
195         /* Flag for quirk use to store if quirk-specific ACS is enabled */
196         PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
197         /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
198         PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
199         /* Do not use bus resets for device */
200         PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
201         /* Do not use PM reset even if device advertises NoSoftRst- */
202         PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
203         /* Get VPD from function 0 VPD */
204         PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
205         /* a non-root bridge where translation occurs, stop alias search here */
206         PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
207         /* Do not use FLR even if device advertises PCI_AF_CAP */
208         PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
209         /*
210          * Resume before calling the driver's system suspend hooks, disabling
211          * the direct_complete optimization.
212          */
213         PCI_DEV_FLAGS_NEEDS_RESUME = (__force pci_dev_flags_t) (1 << 11),
214         /* Don't use Relaxed Ordering for TLPs directed at this device */
215         PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 12),
216 };
217 
218 enum pci_irq_reroute_variant {
219         INTEL_IRQ_REROUTE_VARIANT = 1,
220         MAX_IRQ_REROUTE_VARIANTS = 3
221 };
222 
223 typedef unsigned short __bitwise pci_bus_flags_t;
224 enum pci_bus_flags {
225         PCI_BUS_FLAGS_NO_MSI    = (__force pci_bus_flags_t) 1,
226         PCI_BUS_FLAGS_NO_MMRBC  = (__force pci_bus_flags_t) 2,
227         PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
228 };
229 
230 /* These values come from the PCI Express Spec */
231 enum pcie_link_width {
232         PCIE_LNK_WIDTH_RESRV    = 0x00,
233         PCIE_LNK_X1             = 0x01,
234         PCIE_LNK_X2             = 0x02,
235         PCIE_LNK_X4             = 0x04,
236         PCIE_LNK_X8             = 0x08,
237         PCIE_LNK_X12            = 0x0C,
238         PCIE_LNK_X16            = 0x10,
239         PCIE_LNK_X32            = 0x20,
240         PCIE_LNK_WIDTH_UNKNOWN  = 0xFF,
241 };
242 
243 /* Based on the PCI Hotplug Spec, but some values are made up by us */
244 enum pci_bus_speed {
245         PCI_SPEED_33MHz                 = 0x00,
246         PCI_SPEED_66MHz                 = 0x01,
247         PCI_SPEED_66MHz_PCIX            = 0x02,
248         PCI_SPEED_100MHz_PCIX           = 0x03,
249         PCI_SPEED_133MHz_PCIX           = 0x04,
250         PCI_SPEED_66MHz_PCIX_ECC        = 0x05,
251         PCI_SPEED_100MHz_PCIX_ECC       = 0x06,
252         PCI_SPEED_133MHz_PCIX_ECC       = 0x07,
253         PCI_SPEED_66MHz_PCIX_266        = 0x09,
254         PCI_SPEED_100MHz_PCIX_266       = 0x0a,
255         PCI_SPEED_133MHz_PCIX_266       = 0x0b,
256         AGP_UNKNOWN                     = 0x0c,
257         AGP_1X                          = 0x0d,
258         AGP_2X                          = 0x0e,
259         AGP_4X                          = 0x0f,
260         AGP_8X                          = 0x10,
261         PCI_SPEED_66MHz_PCIX_533        = 0x11,
262         PCI_SPEED_100MHz_PCIX_533       = 0x12,
263         PCI_SPEED_133MHz_PCIX_533       = 0x13,
264         PCIE_SPEED_2_5GT                = 0x14,
265         PCIE_SPEED_5_0GT                = 0x15,
266         PCIE_SPEED_8_0GT                = 0x16,
267         PCI_SPEED_UNKNOWN               = 0xff,
268 };
269 
270 struct pci_cap_saved_data {
271         u16 cap_nr;
272         bool cap_extended;
273         unsigned int size;
274         u32 data[0];
275 };
276 
277 struct pci_cap_saved_state {
278         struct hlist_node next;
279         struct pci_cap_saved_data cap;
280 };
281 
282 struct irq_affinity;
283 struct pcie_link_state;
284 struct pci_vpd;
285 struct pci_sriov;
286 struct pci_ats;
287 
288 /*
289  * The pci_dev structure is used to describe PCI devices.
290  */
291 struct pci_dev {
292         struct list_head bus_list;      /* node in per-bus list */
293         struct pci_bus  *bus;           /* bus this device is on */
294         struct pci_bus  *subordinate;   /* bus this device bridges to */
295 
296         void            *sysdata;       /* hook for sys-specific extension */
297         struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
298         struct pci_slot *slot;          /* Physical slot this device is in */
299 
300         unsigned int    devfn;          /* encoded device & function index */
301         unsigned short  vendor;
302         unsigned short  device;
303         unsigned short  subsystem_vendor;
304         unsigned short  subsystem_device;
305         unsigned int    class;          /* 3 bytes: (base,sub,prog-if) */
306         u8              revision;       /* PCI revision, low byte of class word */
307         u8              hdr_type;       /* PCI header type (`multi' flag masked out) */
308 #ifdef CONFIG_PCIEAER
309         u16             aer_cap;        /* AER capability offset */
310 #endif
311         u8              pcie_cap;       /* PCIe capability offset */
312         u8              msi_cap;        /* MSI capability offset */
313         u8              msix_cap;       /* MSI-X capability offset */
314         u8              pcie_mpss:3;    /* PCIe Max Payload Size Supported */
315         u8              rom_base_reg;   /* which config register controls the ROM */
316         u8              pin;            /* which interrupt pin this device uses */
317         u16             pcie_flags_reg; /* cached PCIe Capabilities Register */
318         unsigned long   *dma_alias_mask;/* mask of enabled devfn aliases */
319 
320         struct pci_driver *driver;      /* which driver has allocated this device */
321         u64             dma_mask;       /* Mask of the bits of bus address this
322                                            device implements.  Normally this is
323                                            0xffffffff.  You only need to change
324                                            this if your device has broken DMA
325                                            or supports 64-bit transfers.  */
326 
327         struct device_dma_parameters dma_parms;
328 
329         pci_power_t     current_state;  /* Current operating state. In ACPI-speak,
330                                            this is D0-D3, D0 being fully functional,
331                                            and D3 being off. */
332         u8              pm_cap;         /* PM capability offset */
333         unsigned int    pme_support:5;  /* Bitmask of states from which PME#
334                                            can be generated */
335         unsigned int    pme_poll:1;     /* Poll device's PME status bit */
336         unsigned int    d1_support:1;   /* Low power state D1 is supported */
337         unsigned int    d2_support:1;   /* Low power state D2 is supported */
338         unsigned int    no_d1d2:1;      /* D1 and D2 are forbidden */
339         unsigned int    no_d3cold:1;    /* D3cold is forbidden */
340         unsigned int    bridge_d3:1;    /* Allow D3 for bridge */
341         unsigned int    d3cold_allowed:1;       /* D3cold is allowed by user */
342         unsigned int    mmio_always_on:1;       /* disallow turning off io/mem
343                                                    decoding during bar sizing */
344         unsigned int    wakeup_prepared:1;
345         unsigned int    runtime_d3cold:1;       /* whether go through runtime
346                                                    D3cold, not set for devices
347                                                    powered on/off by the
348                                                    corresponding bridge */
349         unsigned int    ignore_hotplug:1;       /* Ignore hotplug events */
350         unsigned int    hotplug_user_indicators:1; /* SlotCtl indicators
351                                                       controlled exclusively by
352                                                       user sysfs */
353         unsigned int    d3_delay;       /* D3->D0 transition time in ms */
354         unsigned int    d3cold_delay;   /* D3cold->D0 transition time in ms */
355 
356 #ifdef CONFIG_PCIEASPM
357         struct pcie_link_state  *link_state;    /* ASPM link state */
358 #endif
359 
360         pci_channel_state_t error_state;        /* current connectivity state */
361         struct  device  dev;            /* Generic device interface */
362 
363         int             cfg_size;       /* Size of configuration space */
364 
365         /*
366          * Instead of touching interrupt line and base address registers
367          * directly, use the values stored here. They might be different!
368          */
369         unsigned int    irq;
370         struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
371 
372         bool match_driver;              /* Skip attaching driver */
373         /* These fields are used by common fixups */
374         unsigned int    transparent:1;  /* Subtractive decode PCI bridge */
375         unsigned int    multifunction:1;/* Part of multi-function device */
376         /* keep track of device state */
377         unsigned int    is_added:1;
378         unsigned int    is_busmaster:1; /* device is busmaster */
379         unsigned int    no_msi:1;       /* device may not use msi */
380         unsigned int    no_64bit_msi:1; /* device may only use 32-bit MSIs */
381         unsigned int    block_cfg_access:1;     /* config space access is blocked */
382         unsigned int    broken_parity_status:1; /* Device generates false positive parity */
383         unsigned int    irq_reroute_variant:2;  /* device needs IRQ rerouting variant */
384         unsigned int    msi_enabled:1;
385         unsigned int    msix_enabled:1;
386         unsigned int    ari_enabled:1;  /* ARI forwarding */
387         unsigned int    ats_enabled:1;  /* Address Translation Service */
388         unsigned int    pasid_enabled:1;        /* Process Address Space ID */
389         unsigned int    pri_enabled:1;          /* Page Request Interface */
390         unsigned int    is_managed:1;
391         unsigned int    needs_freset:1; /* Dev requires fundamental reset */
392         unsigned int    state_saved:1;
393         unsigned int    is_physfn:1;
394         unsigned int    is_virtfn:1;
395         unsigned int    reset_fn:1;
396         unsigned int    is_hotplug_bridge:1;
397         unsigned int    is_thunderbolt:1; /* Thunderbolt controller */
398         unsigned int    __aer_firmware_first_valid:1;
399         unsigned int    __aer_firmware_first:1;
400         unsigned int    broken_intx_masking:1; /* INTx masking can't be used */
401         unsigned int    io_window_1k:1; /* Intel P2P bridge 1K I/O windows */
402         unsigned int    irq_managed:1;
403         unsigned int    has_secondary_link:1;
404         unsigned int    non_compliant_bars:1;   /* broken BARs; ignore them */
405         unsigned int    is_probed:1;            /* device probing in progress */
406         pci_dev_flags_t dev_flags;
407         atomic_t        enable_cnt;     /* pci_enable_device has been called */
408 
409         u32             saved_config_space[16]; /* config space saved at suspend time */
410         struct hlist_head saved_cap_space;
411         struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
412         int rom_attr_enabled;           /* has display of the rom attribute been enabled? */
413         struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
414         struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
415 
416 #ifdef CONFIG_PCIE_PTM
417         unsigned int    ptm_root:1;
418         unsigned int    ptm_enabled:1;
419         u8              ptm_granularity;
420 #endif
421 #ifdef CONFIG_PCI_MSI
422         const struct attribute_group **msi_irq_groups;
423 #endif
424         struct pci_vpd *vpd;
425 #ifdef CONFIG_PCI_ATS
426         union {
427                 struct pci_sriov *sriov;        /* SR-IOV capability related */
428                 struct pci_dev *physfn; /* the PF this VF is associated with */
429         };
430         u16             ats_cap;        /* ATS Capability offset */
431         u8              ats_stu;        /* ATS Smallest Translation Unit */
432         atomic_t        ats_ref_cnt;    /* number of VFs with ATS enabled */
433 #endif
434 #ifdef CONFIG_PCI_PRI
435         u32             pri_reqs_alloc; /* Number of PRI requests allocated */
436 #endif
437 #ifdef CONFIG_PCI_PASID
438         u16             pasid_features;
439 #endif
440         phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */
441         size_t romlen; /* Length of ROM if it's not from the BAR */
442         char *driver_override; /* Driver name to force a match */
443 
444         unsigned long priv_flags; /* Private flags for the pci driver */
445 };
446 
447 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
448 {
449 #ifdef CONFIG_PCI_IOV
450         if (dev->is_virtfn)
451                 dev = dev->physfn;
452 #endif
453         return dev;
454 }
455 
456 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
457 
458 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
459 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
460 
461 static inline int pci_channel_offline(struct pci_dev *pdev)
462 {
463         return (pdev->error_state != pci_channel_io_normal);
464 }
465 
466 struct pci_host_bridge {
467         struct device dev;
468         struct pci_bus *bus;            /* root bus */
469         struct pci_ops *ops;
470         void *sysdata;
471         int busnr;
472         struct list_head windows;       /* resource_entry */
473         u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* platform IRQ swizzler */
474         int (*map_irq)(const struct pci_dev *, u8, u8);
475         void (*release_fn)(struct pci_host_bridge *);
476         void *release_data;
477         struct msi_controller *msi;
478         unsigned int ignore_reset_delay:1;      /* for entire hierarchy */
479         unsigned int no_ext_tags:1;             /* no Extended Tags */
480         /* Resource alignment requirements */
481         resource_size_t (*align_resource)(struct pci_dev *dev,
482                         const struct resource *res,
483                         resource_size_t start,
484                         resource_size_t size,
485                         resource_size_t align);
486         unsigned long private[0] ____cacheline_aligned;
487 };
488 
489 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
490 
491 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
492 {
493         return (void *)bridge->private;
494 }
495 
496 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
497 {
498         return container_of(priv, struct pci_host_bridge, private);
499 }
500 
501 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
502 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
503                                                    size_t priv);
504 void pci_free_host_bridge(struct pci_host_bridge *bridge);
505 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
506 
507 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
508                      void (*release_fn)(struct pci_host_bridge *),
509                      void *release_data);
510 
511 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
512 
513 /*
514  * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
515  * to P2P or CardBus bridge windows) go in a table.  Additional ones (for
516  * buses below host bridges or subtractive decode bridges) go in the list.
517  * Use pci_bus_for_each_resource() to iterate through all the resources.
518  */
519 
520 /*
521  * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
522  * and there's no way to program the bridge with the details of the window.
523  * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
524  * decode bit set, because they are explicit and can be programmed with _SRS.
525  */
526 #define PCI_SUBTRACTIVE_DECODE  0x1
527 
528 struct pci_bus_resource {
529         struct list_head list;
530         struct resource *res;
531         unsigned int flags;
532 };
533 
534 #define PCI_REGION_FLAG_MASK    0x0fU   /* These bits of resource flags tell us the PCI region flags */
535 
536 struct pci_bus {
537         struct list_head node;          /* node in list of buses */
538         struct pci_bus  *parent;        /* parent bus this bridge is on */
539         struct list_head children;      /* list of child buses */
540         struct list_head devices;       /* list of devices on this bus */
541         struct pci_dev  *self;          /* bridge device as seen by parent */
542         struct list_head slots;         /* list of slots on this bus;
543                                            protected by pci_slot_mutex */
544         struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
545         struct list_head resources;     /* address space routed to this bus */
546         struct resource busn_res;       /* bus numbers routed to this bus */
547 
548         struct pci_ops  *ops;           /* configuration access functions */
549         struct msi_controller *msi;     /* MSI controller */
550         void            *sysdata;       /* hook for sys-specific extension */
551         struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
552 
553         unsigned char   number;         /* bus number */
554         unsigned char   primary;        /* number of primary bridge */
555         unsigned char   max_bus_speed;  /* enum pci_bus_speed */
556         unsigned char   cur_bus_speed;  /* enum pci_bus_speed */
557 #ifdef CONFIG_PCI_DOMAINS_GENERIC
558         int             domain_nr;
559 #endif
560 
561         char            name[48];
562 
563         unsigned short  bridge_ctl;     /* manage NO_ISA/FBB/et al behaviors */
564         pci_bus_flags_t bus_flags;      /* inherited by child buses */
565         struct device           *bridge;
566         struct device           dev;
567         struct bin_attribute    *legacy_io; /* legacy I/O for this bus */
568         struct bin_attribute    *legacy_mem; /* legacy mem */
569         unsigned int            is_added:1;
570 };
571 
572 #define to_pci_bus(n)   container_of(n, struct pci_bus, dev)
573 
574 /*
575  * Returns true if the PCI bus is root (behind host-PCI bridge),
576  * false otherwise
577  *
578  * Some code assumes that "bus->self == NULL" means that bus is a root bus.
579  * This is incorrect because "virtual" buses added for SR-IOV (via
580  * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
581  */
582 static inline bool pci_is_root_bus(struct pci_bus *pbus)
583 {
584         return !(pbus->parent);
585 }
586 
587 /**
588  * pci_is_bridge - check if the PCI device is a bridge
589  * @dev: PCI device
590  *
591  * Return true if the PCI device is bridge whether it has subordinate
592  * or not.
593  */
594 static inline bool pci_is_bridge(struct pci_dev *dev)
595 {
596         return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
597                 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
598 }
599 
600 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
601 {
602         dev = pci_physfn(dev);
603         if (pci_is_root_bus(dev->bus))
604                 return NULL;
605 
606         return dev->bus->self;
607 }
608 
609 struct device *pci_get_host_bridge_device(struct pci_dev *dev);
610 void pci_put_host_bridge_device(struct device *dev);
611 
612 #ifdef CONFIG_PCI_MSI
613 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
614 {
615         return pci_dev->msi_enabled || pci_dev->msix_enabled;
616 }
617 #else
618 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
619 #endif
620 
621 /*
622  * Error values that may be returned by PCI functions.
623  */
624 #define PCIBIOS_SUCCESSFUL              0x00
625 #define PCIBIOS_FUNC_NOT_SUPPORTED      0x81
626 #define PCIBIOS_BAD_VENDOR_ID           0x83
627 #define PCIBIOS_DEVICE_NOT_FOUND        0x86
628 #define PCIBIOS_BAD_REGISTER_NUMBER     0x87
629 #define PCIBIOS_SET_FAILED              0x88
630 #define PCIBIOS_BUFFER_TOO_SMALL        0x89
631 
632 /*
633  * Translate above to generic errno for passing back through non-PCI code.
634  */
635 static inline int pcibios_err_to_errno(int err)
636 {
637         if (err <= PCIBIOS_SUCCESSFUL)
638                 return err; /* Assume already errno */
639 
640         switch (err) {
641         case PCIBIOS_FUNC_NOT_SUPPORTED:
642                 return -ENOENT;
643         case PCIBIOS_BAD_VENDOR_ID:
644                 return -ENOTTY;
645         case PCIBIOS_DEVICE_NOT_FOUND:
646                 return -ENODEV;
647         case PCIBIOS_BAD_REGISTER_NUMBER:
648                 return -EFAULT;
649         case PCIBIOS_SET_FAILED:
650                 return -EIO;
651         case PCIBIOS_BUFFER_TOO_SMALL:
652                 return -ENOSPC;
653         }
654 
655         return -ERANGE;
656 }
657 
658 /* Low-level architecture-dependent routines */
659 
660 struct pci_ops {
661         int (*add_bus)(struct pci_bus *bus);
662         void (*remove_bus)(struct pci_bus *bus);
663         void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
664         int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
665         int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
666 };
667 
668 /*
669  * ACPI needs to be able to access PCI config space before we've done a
670  * PCI bus scan and created pci_bus structures.
671  */
672 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
673                  int reg, int len, u32 *val);
674 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
675                   int reg, int len, u32 val);
676 
677 #ifdef CONFIG_PCI_BUS_ADDR_T_64BIT
678 typedef u64 pci_bus_addr_t;
679 #else
680 typedef u32 pci_bus_addr_t;
681 #endif
682 
683 struct pci_bus_region {
684         pci_bus_addr_t start;
685         pci_bus_addr_t end;
686 };
687 
688 struct pci_dynids {
689         spinlock_t lock;            /* protects list, index */
690         struct list_head list;      /* for IDs added at runtime */
691 };
692 
693 
694 /*
695  * PCI Error Recovery System (PCI-ERS).  If a PCI device driver provides
696  * a set of callbacks in struct pci_error_handlers, that device driver
697  * will be notified of PCI bus errors, and will be driven to recovery
698  * when an error occurs.
699  */
700 
701 typedef unsigned int __bitwise pci_ers_result_t;
702 
703 enum pci_ers_result {
704         /* no result/none/not supported in device driver */
705         PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
706 
707         /* Device driver can recover without slot reset */
708         PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
709 
710         /* Device driver wants slot to be reset. */
711         PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
712 
713         /* Device has completely failed, is unrecoverable */
714         PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
715 
716         /* Device driver is fully recovered and operational */
717         PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
718 
719         /* No AER capabilities registered for the driver */
720         PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
721 };
722 
723 /* PCI bus error event callbacks */
724 struct pci_error_handlers {
725         /* PCI bus error detected on this device */
726         pci_ers_result_t (*error_detected)(struct pci_dev *dev,
727                                            enum pci_channel_state error);
728 
729         /* MMIO has been re-enabled, but not DMA */
730         pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
731 
732         /* PCI slot has been reset */
733         pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
734 
735         /* PCI function reset prepare or completed */
736         void (*reset_prepare)(struct pci_dev *dev);
737         void (*reset_done)(struct pci_dev *dev);
738 
739         /* Device driver may resume normal operations */
740         void (*resume)(struct pci_dev *dev);
741 };
742 
743 
744 struct module;
745 struct pci_driver {
746         struct list_head node;
747         const char *name;
748         const struct pci_device_id *id_table;   /* must be non-NULL for probe to be called */
749         int  (*probe)  (struct pci_dev *dev, const struct pci_device_id *id);   /* New device inserted */
750         void (*remove) (struct pci_dev *dev);   /* Device removed (NULL if not a hot-plug capable driver) */
751         int  (*suspend) (struct pci_dev *dev, pm_message_t state);      /* Device suspended */
752         int  (*suspend_late) (struct pci_dev *dev, pm_message_t state);
753         int  (*resume_early) (struct pci_dev *dev);
754         int  (*resume) (struct pci_dev *dev);                   /* Device woken up */
755         void (*shutdown) (struct pci_dev *dev);
756         int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */
757         const struct pci_error_handlers *err_handler;
758         const struct attribute_group **groups;
759         struct device_driver    driver;
760         struct pci_dynids dynids;
761 };
762 
763 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
764 
765 /**
766  * PCI_DEVICE - macro used to describe a specific pci device
767  * @vend: the 16 bit PCI Vendor ID
768  * @dev: the 16 bit PCI Device ID
769  *
770  * This macro is used to create a struct pci_device_id that matches a
771  * specific device.  The subvendor and subdevice fields will be set to
772  * PCI_ANY_ID.
773  */
774 #define PCI_DEVICE(vend,dev) \
775         .vendor = (vend), .device = (dev), \
776         .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
777 
778 /**
779  * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
780  * @vend: the 16 bit PCI Vendor ID
781  * @dev: the 16 bit PCI Device ID
782  * @subvend: the 16 bit PCI Subvendor ID
783  * @subdev: the 16 bit PCI Subdevice ID
784  *
785  * This macro is used to create a struct pci_device_id that matches a
786  * specific device with subsystem information.
787  */
788 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
789         .vendor = (vend), .device = (dev), \
790         .subvendor = (subvend), .subdevice = (subdev)
791 
792 /**
793  * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
794  * @dev_class: the class, subclass, prog-if triple for this device
795  * @dev_class_mask: the class mask for this device
796  *
797  * This macro is used to create a struct pci_device_id that matches a
798  * specific PCI class.  The vendor, device, subvendor, and subdevice
799  * fields will be set to PCI_ANY_ID.
800  */
801 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
802         .class = (dev_class), .class_mask = (dev_class_mask), \
803         .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
804         .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
805 
806 /**
807  * PCI_VDEVICE - macro used to describe a specific pci device in short form
808  * @vend: the vendor name
809  * @dev: the 16 bit PCI Device ID
810  *
811  * This macro is used to create a struct pci_device_id that matches a
812  * specific PCI device.  The subvendor, and subdevice fields will be set
813  * to PCI_ANY_ID. The macro allows the next field to follow as the device
814  * private data.
815  */
816 
817 #define PCI_VDEVICE(vend, dev) \
818         .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
819         .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
820 
821 enum {
822         PCI_REASSIGN_ALL_RSRC   = 0x00000001,   /* ignore firmware setup */
823         PCI_REASSIGN_ALL_BUS    = 0x00000002,   /* reassign all bus numbers */
824         PCI_PROBE_ONLY          = 0x00000004,   /* use existing setup */
825         PCI_CAN_SKIP_ISA_ALIGN  = 0x00000008,   /* don't do ISA alignment */
826         PCI_ENABLE_PROC_DOMAINS = 0x00000010,   /* enable domains in /proc */
827         PCI_COMPAT_DOMAIN_0     = 0x00000020,   /* ... except domain 0 */
828         PCI_SCAN_ALL_PCIE_DEVS  = 0x00000040,   /* scan all, not just dev 0 */
829 };
830 
831 /* these external functions are only available when PCI support is enabled */
832 #ifdef CONFIG_PCI
833 
834 extern unsigned int pci_flags;
835 
836 static inline void pci_set_flags(int flags) { pci_flags = flags; }
837 static inline void pci_add_flags(int flags) { pci_flags |= flags; }
838 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
839 static inline int pci_has_flag(int flag) { return pci_flags & flag; }
840 
841 void pcie_bus_configure_settings(struct pci_bus *bus);
842 
843 enum pcie_bus_config_types {
844         PCIE_BUS_TUNE_OFF,      /* don't touch MPS at all */
845         PCIE_BUS_DEFAULT,       /* ensure MPS matches upstream bridge */
846         PCIE_BUS_SAFE,          /* use largest MPS boot-time devices support */
847         PCIE_BUS_PERFORMANCE,   /* use MPS and MRRS for best performance */
848         PCIE_BUS_PEER2PEER,     /* set MPS = 128 for all devices */
849 };
850 
851 extern enum pcie_bus_config_types pcie_bus_config;
852 
853 extern struct bus_type pci_bus_type;
854 
855 /* Do NOT directly access these two variables, unless you are arch-specific PCI
856  * code, or PCI core code. */
857 extern struct list_head pci_root_buses; /* list of all known PCI buses */
858 /* Some device drivers need know if PCI is initiated */
859 int no_pci_devices(void);
860 
861 void pcibios_resource_survey_bus(struct pci_bus *bus);
862 void pcibios_bus_add_device(struct pci_dev *pdev);
863 void pcibios_add_bus(struct pci_bus *bus);
864 void pcibios_remove_bus(struct pci_bus *bus);
865 void pcibios_fixup_bus(struct pci_bus *);
866 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
867 /* Architecture-specific versions may override this (weak) */
868 char *pcibios_setup(char *str);
869 
870 /* Used only when drivers/pci/setup.c is used */
871 resource_size_t pcibios_align_resource(void *, const struct resource *,
872                                 resource_size_t,
873                                 resource_size_t);
874 
875 /* Weak but can be overriden by arch */
876 void pci_fixup_cardbus(struct pci_bus *);
877 
878 /* Generic PCI functions used internally */
879 
880 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
881                              struct resource *res);
882 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
883                              struct pci_bus_region *region);
884 void pcibios_scan_specific_bus(int busn);
885 struct pci_bus *pci_find_bus(int domain, int busnr);
886 void pci_bus_add_devices(const struct pci_bus *bus);
887 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
888 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
889                                     struct pci_ops *ops, void *sysdata,
890                                     struct list_head *resources);
891 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
892 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
893 void pci_bus_release_busn_res(struct pci_bus *b);
894 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
895                                              struct pci_ops *ops, void *sysdata,
896                                              struct list_head *resources);
897 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
898 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
899                                 int busnr);
900 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
901 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
902                                  const char *name,
903                                  struct hotplug_slot *hotplug);
904 void pci_destroy_slot(struct pci_slot *slot);
905 #ifdef CONFIG_SYSFS
906 void pci_dev_assign_slot(struct pci_dev *dev);
907 #else
908 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
909 #endif
910 int pci_scan_slot(struct pci_bus *bus, int devfn);
911 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
912 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
913 unsigned int pci_scan_child_bus(struct pci_bus *bus);
914 void pci_bus_add_device(struct pci_dev *dev);
915 void pci_read_bridge_bases(struct pci_bus *child);
916 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
917                                           struct resource *res);
918 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev);
919 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
920 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
921 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
922 struct pci_dev *pci_dev_get(struct pci_dev *dev);
923 void pci_dev_put(struct pci_dev *dev);
924 void pci_remove_bus(struct pci_bus *b);
925 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
926 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
927 void pci_stop_root_bus(struct pci_bus *bus);
928 void pci_remove_root_bus(struct pci_bus *bus);
929 void pci_setup_cardbus(struct pci_bus *bus);
930 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
931 void pci_sort_breadthfirst(void);
932 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
933 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
934 
935 /* Generic PCI functions exported to card drivers */
936 
937 enum pci_lost_interrupt_reason {
938         PCI_LOST_IRQ_NO_INFORMATION = 0,
939         PCI_LOST_IRQ_DISABLE_MSI,
940         PCI_LOST_IRQ_DISABLE_MSIX,
941         PCI_LOST_IRQ_DISABLE_ACPI,
942 };
943 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
944 int pci_find_capability(struct pci_dev *dev, int cap);
945 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
946 int pci_find_ext_capability(struct pci_dev *dev, int cap);
947 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
948 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
949 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
950 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
951 
952 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
953                                 struct pci_dev *from);
954 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
955                                 unsigned int ss_vendor, unsigned int ss_device,
956                                 struct pci_dev *from);
957 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
958 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
959                                             unsigned int devfn);
960 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
961                                                    unsigned int devfn)
962 {
963         return pci_get_domain_bus_and_slot(0, bus, devfn);
964 }
965 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
966 int pci_dev_present(const struct pci_device_id *ids);
967 
968 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
969                              int where, u8 *val);
970 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
971                              int where, u16 *val);
972 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
973                               int where, u32 *val);
974 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
975                               int where, u8 val);
976 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
977                               int where, u16 val);
978 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
979                                int where, u32 val);
980 
981 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
982                             int where, int size, u32 *val);
983 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
984                             int where, int size, u32 val);
985 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
986                               int where, int size, u32 *val);
987 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
988                                int where, int size, u32 val);
989 
990 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
991 
992 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
993 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
994 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
995 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
996 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
997 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
998 
999 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1000 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1001 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1002 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1003 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1004                                        u16 clear, u16 set);
1005 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1006                                         u32 clear, u32 set);
1007 
1008 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1009                                            u16 set)
1010 {
1011         return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1012 }
1013 
1014 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1015                                             u32 set)
1016 {
1017         return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1018 }
1019 
1020 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1021                                              u16 clear)
1022 {
1023         return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1024 }
1025 
1026 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1027                                               u32 clear)
1028 {
1029         return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1030 }
1031 
1032 /* user-space driven config access */
1033 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1034 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1035 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1036 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1037 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1038 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1039 
1040 int __must_check pci_enable_device(struct pci_dev *dev);
1041 int __must_check pci_enable_device_io(struct pci_dev *dev);
1042 int __must_check pci_enable_device_mem(struct pci_dev *dev);
1043 int __must_check pci_reenable_device(struct pci_dev *);
1044 int __must_check pcim_enable_device(struct pci_dev *pdev);
1045 void pcim_pin_device(struct pci_dev *pdev);
1046 
1047 static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1048 {
1049         /*
1050          * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1051          * writable and no quirk has marked the feature broken.
1052          */
1053         return !pdev->broken_intx_masking;
1054 }
1055 
1056 static inline int pci_is_enabled(struct pci_dev *pdev)
1057 {
1058         return (atomic_read(&pdev->enable_cnt) > 0);
1059 }
1060 
1061 static inline int pci_is_managed(struct pci_dev *pdev)
1062 {
1063         return pdev->is_managed;
1064 }
1065 
1066 void pci_disable_device(struct pci_dev *dev);
1067 
1068 extern unsigned int pcibios_max_latency;
1069 void pci_set_master(struct pci_dev *dev);
1070 void pci_clear_master(struct pci_dev *dev);
1071 
1072 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1073 int pci_set_cacheline_size(struct pci_dev *dev);
1074 #define HAVE_PCI_SET_MWI
1075 int __must_check pci_set_mwi(struct pci_dev *dev);
1076 int pci_try_set_mwi(struct pci_dev *dev);
1077 void pci_clear_mwi(struct pci_dev *dev);
1078 void pci_intx(struct pci_dev *dev, int enable);
1079 bool pci_check_and_mask_intx(struct pci_dev *dev);
1080 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1081 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1082 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1083 int pcix_get_max_mmrbc(struct pci_dev *dev);
1084 int pcix_get_mmrbc(struct pci_dev *dev);
1085 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1086 int pcie_get_readrq(struct pci_dev *dev);
1087 int pcie_set_readrq(struct pci_dev *dev, int rq);
1088 int pcie_get_mps(struct pci_dev *dev);
1089 int pcie_set_mps(struct pci_dev *dev, int mps);
1090 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
1091                           enum pcie_link_width *width);
1092 void pcie_flr(struct pci_dev *dev);
1093 int __pci_reset_function(struct pci_dev *dev);
1094 int __pci_reset_function_locked(struct pci_dev *dev);
1095 int pci_reset_function(struct pci_dev *dev);
1096 int pci_reset_function_locked(struct pci_dev *dev);
1097 int pci_try_reset_function(struct pci_dev *dev);
1098 int pci_probe_reset_slot(struct pci_slot *slot);
1099 int pci_reset_slot(struct pci_slot *slot);
1100 int pci_try_reset_slot(struct pci_slot *slot);
1101 int pci_probe_reset_bus(struct pci_bus *bus);
1102 int pci_reset_bus(struct pci_bus *bus);
1103 int pci_try_reset_bus(struct pci_bus *bus);
1104 void pci_reset_secondary_bus(struct pci_dev *dev);
1105 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1106 void pci_reset_bridge_secondary_bus(struct pci_dev *dev);
1107 void pci_update_resource(struct pci_dev *dev, int resno);
1108 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1109 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1110 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1111 bool pci_device_is_present(struct pci_dev *pdev);
1112 void pci_ignore_hotplug(struct pci_dev *dev);
1113 
1114 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1115                 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1116                 const char *fmt, ...);
1117 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1118 
1119 /* ROM control related routines */
1120 int pci_enable_rom(struct pci_dev *pdev);
1121 void pci_disable_rom(struct pci_dev *pdev);
1122 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1123 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1124 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
1125 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
1126 
1127 /* Power management related routines */
1128 int pci_save_state(struct pci_dev *dev);
1129 void pci_restore_state(struct pci_dev *dev);
1130 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1131 int pci_load_saved_state(struct pci_dev *dev,
1132                          struct pci_saved_state *state);
1133 int pci_load_and_free_saved_state(struct pci_dev *dev,
1134                                   struct pci_saved_state **state);
1135 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1136 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1137                                                    u16 cap);
1138 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1139 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1140                                 u16 cap, unsigned int size);
1141 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
1142 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1143 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1144 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1145 void pci_pme_active(struct pci_dev *dev, bool enable);
1146 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1147 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1148 int pci_prepare_to_sleep(struct pci_dev *dev);
1149 int pci_back_from_sleep(struct pci_dev *dev);
1150 bool pci_dev_run_wake(struct pci_dev *dev);
1151 bool pci_check_pme_status(struct pci_dev *dev);
1152 void pci_pme_wakeup_bus(struct pci_bus *bus);
1153 void pci_d3cold_enable(struct pci_dev *dev);
1154 void pci_d3cold_disable(struct pci_dev *dev);
1155 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1156 
1157 /* PCI Virtual Channel */
1158 int pci_save_vc_state(struct pci_dev *dev);
1159 void pci_restore_vc_state(struct pci_dev *dev);
1160 void pci_allocate_vc_save_buffers(struct pci_dev *dev);
1161 
1162 /* For use by arch with custom probe code */
1163 void set_pcie_port_type(struct pci_dev *pdev);
1164 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1165 
1166 /* Functions for PCI Hotplug drivers to use */
1167 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1168 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1169 unsigned int pci_rescan_bus(struct pci_bus *bus);
1170 void pci_lock_rescan_remove(void);
1171 void pci_unlock_rescan_remove(void);
1172 
1173 /* Vital product data routines */
1174 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1175 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1176 int pci_set_vpd_size(struct pci_dev *dev, size_t len);
1177 
1178 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1179 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1180 void pci_bus_assign_resources(const struct pci_bus *bus);
1181 void pci_bus_claim_resources(struct pci_bus *bus);
1182 void pci_bus_size_bridges(struct pci_bus *bus);
1183 int pci_claim_resource(struct pci_dev *, int);
1184 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1185 void pci_assign_unassigned_resources(void);
1186 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1187 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1188 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1189 void pdev_enable_device(struct pci_dev *);
1190 int pci_enable_resources(struct pci_dev *, int mask);
1191 void pci_assign_irq(struct pci_dev *dev);
1192 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1193 #define HAVE_PCI_REQ_REGIONS    2
1194 int __must_check pci_request_regions(struct pci_dev *, const char *);
1195 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1196 void pci_release_regions(struct pci_dev *);
1197 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1198 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1199 void pci_release_region(struct pci_dev *, int);
1200 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1201 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1202 void pci_release_selected_regions(struct pci_dev *, int);
1203 
1204 /* drivers/pci/bus.c */
1205 struct pci_bus *pci_bus_get(struct pci_bus *bus);
1206 void pci_bus_put(struct pci_bus *bus);
1207 void pci_add_resource(struct list_head *resources, struct resource *res);
1208 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1209                              resource_size_t offset);
1210 void pci_free_resource_list(struct list_head *resources);
1211 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1212                           unsigned int flags);
1213 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1214 void pci_bus_remove_resources(struct pci_bus *bus);
1215 int devm_request_pci_bus_resources(struct device *dev,
1216                                    struct list_head *resources);
1217 
1218 #define pci_bus_for_each_resource(bus, res, i)                          \
1219         for (i = 0;                                                     \
1220             (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1221              i++)
1222 
1223 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1224                         struct resource *res, resource_size_t size,
1225                         resource_size_t align, resource_size_t min,
1226                         unsigned long type_mask,
1227                         resource_size_t (*alignf)(void *,
1228                                                   const struct resource *,
1229                                                   resource_size_t,
1230                                                   resource_size_t),
1231                         void *alignf_data);
1232 
1233 
1234 int pci_register_io_range(phys_addr_t addr, resource_size_t size);
1235 unsigned long pci_address_to_pio(phys_addr_t addr);
1236 phys_addr_t pci_pio_to_address(unsigned long pio);
1237 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1238 void pci_unmap_iospace(struct resource *res);
1239 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1240                                       resource_size_t offset,
1241                                       resource_size_t size);
1242 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1243                                           struct resource *res);
1244 
1245 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1246 {
1247         struct pci_bus_region region;
1248 
1249         pcibios_resource_to_bus(pdev->bus, &region, &pdev->resource[bar]);
1250         return region.start;
1251 }
1252 
1253 /* Proper probing supporting hot-pluggable devices */
1254 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1255                                        const char *mod_name);
1256 
1257 /*
1258  * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
1259  */
1260 #define pci_register_driver(driver)             \
1261         __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1262 
1263 void pci_unregister_driver(struct pci_driver *dev);
1264 
1265 /**
1266  * module_pci_driver() - Helper macro for registering a PCI driver
1267  * @__pci_driver: pci_driver struct
1268  *
1269  * Helper macro for PCI drivers which do not do anything special in module
1270  * init/exit. This eliminates a lot of boilerplate. Each module may only
1271  * use this macro once, and calling it replaces module_init() and module_exit()
1272  */
1273 #define module_pci_driver(__pci_driver) \
1274         module_driver(__pci_driver, pci_register_driver, \
1275                        pci_unregister_driver)
1276 
1277 /**
1278  * builtin_pci_driver() - Helper macro for registering a PCI driver
1279  * @__pci_driver: pci_driver struct
1280  *
1281  * Helper macro for PCI drivers which do not do anything special in their
1282  * init code. This eliminates a lot of boilerplate. Each driver may only
1283  * use this macro once, and calling it replaces device_initcall(...)
1284  */
1285 #define builtin_pci_driver(__pci_driver) \
1286         builtin_driver(__pci_driver, pci_register_driver)
1287 
1288 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1289 int pci_add_dynid(struct pci_driver *drv,
1290                   unsigned int vendor, unsigned int device,
1291                   unsigned int subvendor, unsigned int subdevice,
1292                   unsigned int class, unsigned int class_mask,
1293                   unsigned long driver_data);
1294 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1295                                          struct pci_dev *dev);
1296 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1297                     int pass);
1298 
1299 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1300                   void *userdata);
1301 int pci_cfg_space_size(struct pci_dev *dev);
1302 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1303 void pci_setup_bridge(struct pci_bus *bus);
1304 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1305                                          unsigned long type);
1306 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
1307 
1308 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1309 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1310 
1311 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1312                       unsigned int command_bits, u32 flags);
1313 
1314 #define PCI_IRQ_LEGACY          (1 << 0) /* allow legacy interrupts */
1315 #define PCI_IRQ_MSI             (1 << 1) /* allow MSI interrupts */
1316 #define PCI_IRQ_MSIX            (1 << 2) /* allow MSI-X interrupts */
1317 #define PCI_IRQ_AFFINITY        (1 << 3) /* auto-assign affinity */
1318 #define PCI_IRQ_ALL_TYPES \
1319         (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1320 
1321 /* kmem_cache style wrapper around pci_alloc_consistent() */
1322 
1323 #include <linux/pci-dma.h>
1324 #include <linux/dmapool.h>
1325 
1326 #define pci_pool dma_pool
1327 #define pci_pool_create(name, pdev, size, align, allocation) \
1328                 dma_pool_create(name, &pdev->dev, size, align, allocation)
1329 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1330 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1331 #define pci_pool_zalloc(pool, flags, handle) \
1332                 dma_pool_zalloc(pool, flags, handle)
1333 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1334 
1335 struct msix_entry {
1336         u32     vector; /* kernel uses to write allocated vector */
1337         u16     entry;  /* driver uses to specify entry, OS writes */
1338 };
1339 
1340 #ifdef CONFIG_PCI_MSI
1341 int pci_msi_vec_count(struct pci_dev *dev);
1342 void pci_disable_msi(struct pci_dev *dev);
1343 int pci_msix_vec_count(struct pci_dev *dev);
1344 void pci_disable_msix(struct pci_dev *dev);
1345 void pci_restore_msi_state(struct pci_dev *dev);
1346 int pci_msi_enabled(void);
1347 int pci_enable_msi(struct pci_dev *dev);
1348 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1349                           int minvec, int maxvec);
1350 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1351                                         struct msix_entry *entries, int nvec)
1352 {
1353         int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1354         if (rc < 0)
1355                 return rc;
1356         return 0;
1357 }
1358 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1359                                    unsigned int max_vecs, unsigned int flags,
1360                                    const struct irq_affinity *affd);
1361 
1362 void pci_free_irq_vectors(struct pci_dev *dev);
1363 int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1364 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1365 int pci_irq_get_node(struct pci_dev *pdev, int vec);
1366 
1367 #else
1368 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1369 static inline void pci_disable_msi(struct pci_dev *dev) { }
1370 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1371 static inline void pci_disable_msix(struct pci_dev *dev) { }
1372 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1373 static inline int pci_msi_enabled(void) { return 0; }
1374 static inline int pci_enable_msi(struct pci_dev *dev)
1375 { return -ENOSYS; }
1376 static inline int pci_enable_msix_range(struct pci_dev *dev,
1377                       struct msix_entry *entries, int minvec, int maxvec)
1378 { return -ENOSYS; }
1379 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1380                       struct msix_entry *entries, int nvec)
1381 { return -ENOSYS; }
1382 
1383 static inline int
1384 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1385                                unsigned int max_vecs, unsigned int flags,
1386                                const struct irq_affinity *aff_desc)
1387 {
1388         if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1389                 return 1;
1390         return -ENOSPC;
1391 }
1392 
1393 static inline void pci_free_irq_vectors(struct pci_dev *dev)
1394 {
1395 }
1396 
1397 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1398 {
1399         if (WARN_ON_ONCE(nr > 0))
1400                 return -EINVAL;
1401         return dev->irq;
1402 }
1403 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1404                 int vec)
1405 {
1406         return cpu_possible_mask;
1407 }
1408 
1409 static inline int pci_irq_get_node(struct pci_dev *pdev, int vec)
1410 {
1411         return first_online_node;
1412 }
1413 #endif
1414 
1415 static inline int
1416 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1417                       unsigned int max_vecs, unsigned int flags)
1418 {
1419         return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1420                                               NULL);
1421 }
1422 
1423 /**
1424  * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1425  * @d: the INTx IRQ domain
1426  * @node: the DT node for the device whose interrupt we're translating
1427  * @intspec: the interrupt specifier data from the DT
1428  * @intsize: the number of entries in @intspec
1429  * @out_hwirq: pointer at which to write the hwirq number
1430  * @out_type: pointer at which to write the interrupt type
1431  *
1432  * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1433  * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1434  * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1435  * INTx value to obtain the hwirq number.
1436  *
1437  * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1438  */
1439 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1440                                       struct device_node *node,
1441                                       const u32 *intspec,
1442                                       unsigned int intsize,
1443                                       unsigned long *out_hwirq,
1444                                       unsigned int *out_type)
1445 {
1446         const u32 intx = intspec[0];
1447 
1448         if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1449                 return -EINVAL;
1450 
1451         *out_hwirq = intx - PCI_INTERRUPT_INTA;
1452         return 0;
1453 }
1454 
1455 #ifdef CONFIG_PCIEPORTBUS
1456 extern bool pcie_ports_disabled;
1457 extern bool pcie_ports_auto;
1458 #else
1459 #define pcie_ports_disabled     true
1460 #define pcie_ports_auto         false
1461 #endif
1462 
1463 #ifdef CONFIG_PCIEASPM
1464 bool pcie_aspm_support_enabled(void);
1465 #else
1466 static inline bool pcie_aspm_support_enabled(void) { return false; }
1467 #endif
1468 
1469 #ifdef CONFIG_PCIEAER
1470 void pci_no_aer(void);
1471 bool pci_aer_available(void);
1472 int pci_aer_init(struct pci_dev *dev);
1473 #else
1474 static inline void pci_no_aer(void) { }
1475 static inline bool pci_aer_available(void) { return false; }
1476 static inline int pci_aer_init(struct pci_dev *d) { return -ENODEV; }
1477 #endif
1478 
1479 #ifdef CONFIG_PCIE_ECRC
1480 void pcie_set_ecrc_checking(struct pci_dev *dev);
1481 void pcie_ecrc_get_policy(char *str);
1482 #else
1483 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
1484 static inline void pcie_ecrc_get_policy(char *str) { }
1485 #endif
1486 
1487 #ifdef CONFIG_HT_IRQ
1488 /* The functions a driver should call */
1489 int  ht_create_irq(struct pci_dev *dev, int idx);
1490 void ht_destroy_irq(unsigned int irq);
1491 #endif /* CONFIG_HT_IRQ */
1492 
1493 #ifdef CONFIG_PCI_ATS
1494 /* Address Translation Service */
1495 void pci_ats_init(struct pci_dev *dev);
1496 int pci_enable_ats(struct pci_dev *dev, int ps);
1497 void pci_disable_ats(struct pci_dev *dev);
1498 int pci_ats_queue_depth(struct pci_dev *dev);
1499 #else
1500 static inline void pci_ats_init(struct pci_dev *d) { }
1501 static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; }
1502 static inline void pci_disable_ats(struct pci_dev *d) { }
1503 static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; }
1504 #endif
1505 
1506 #ifdef CONFIG_PCIE_PTM
1507 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1508 #else
1509 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1510 { return -EINVAL; }
1511 #endif
1512 
1513 void pci_cfg_access_lock(struct pci_dev *dev);
1514 bool pci_cfg_access_trylock(struct pci_dev *dev);
1515 void pci_cfg_access_unlock(struct pci_dev *dev);
1516 
1517 /*
1518  * PCI domain support.  Sometimes called PCI segment (eg by ACPI),
1519  * a PCI domain is defined to be a set of PCI buses which share
1520  * configuration space.
1521  */
1522 #ifdef CONFIG_PCI_DOMAINS
1523 extern int pci_domains_supported;
1524 int pci_get_new_domain_nr(void);
1525 #else
1526 enum { pci_domains_supported = 0 };
1527 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1528 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1529 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1530 #endif /* CONFIG_PCI_DOMAINS */
1531 
1532 /*
1533  * Generic implementation for PCI domain support. If your
1534  * architecture does not need custom management of PCI
1535  * domains then this implementation will be used
1536  */
1537 #ifdef CONFIG_PCI_DOMAINS_GENERIC
1538 static inline int pci_domain_nr(struct pci_bus *bus)
1539 {
1540         return bus->domain_nr;
1541 }
1542 #ifdef CONFIG_ACPI
1543 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1544 #else
1545 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1546 { return 0; }
1547 #endif
1548 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1549 #endif
1550 
1551 /* some architectures require additional setup to direct VGA traffic */
1552 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1553                       unsigned int command_bits, u32 flags);
1554 void pci_register_set_vga_state(arch_set_vga_state_t func);
1555 
1556 static inline int
1557 pci_request_io_regions(struct pci_dev *pdev, const char *name)
1558 {
1559         return pci_request_selected_regions(pdev,
1560                             pci_select_bars(pdev, IORESOURCE_IO), name);
1561 }
1562 
1563 static inline void
1564 pci_release_io_regions(struct pci_dev *pdev)
1565 {
1566         return pci_release_selected_regions(pdev,
1567                             pci_select_bars(pdev, IORESOURCE_IO));
1568 }
1569 
1570 static inline int
1571 pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1572 {
1573         return pci_request_selected_regions(pdev,
1574                             pci_select_bars(pdev, IORESOURCE_MEM), name);
1575 }
1576 
1577 static inline void
1578 pci_release_mem_regions(struct pci_dev *pdev)
1579 {
1580         return pci_release_selected_regions(pdev,
1581                             pci_select_bars(pdev, IORESOURCE_MEM));
1582 }
1583 
1584 #else /* CONFIG_PCI is not enabled */
1585 
1586 static inline void pci_set_flags(int flags) { }
1587 static inline void pci_add_flags(int flags) { }
1588 static inline void pci_clear_flags(int flags) { }
1589 static inline int pci_has_flag(int flag) { return 0; }
1590 
1591 /*
1592  *  If the system does not have PCI, clearly these return errors.  Define
1593  *  these as simple inline functions to avoid hair in drivers.
1594  */
1595 
1596 #define _PCI_NOP(o, s, t) \
1597         static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1598                                                 int where, t val) \
1599                 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1600 
1601 #define _PCI_NOP_ALL(o, x)      _PCI_NOP(o, byte, u8 x) \
1602                                 _PCI_NOP(o, word, u16 x) \
1603                                 _PCI_NOP(o, dword, u32 x)
1604 _PCI_NOP_ALL(read, *)
1605 _PCI_NOP_ALL(write,)
1606 
1607 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1608                                              unsigned int device,
1609                                              struct pci_dev *from)
1610 { return NULL; }
1611 
1612 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1613                                              unsigned int device,
1614                                              unsigned int ss_vendor,
1615                                              unsigned int ss_device,
1616                                              struct pci_dev *from)
1617 { return NULL; }
1618 
1619 static inline struct pci_dev *pci_get_class(unsigned int class,
1620                                             struct pci_dev *from)
1621 { return NULL; }
1622 
1623 #define pci_dev_present(ids)    (0)
1624 #define no_pci_devices()        (1)
1625 #define pci_dev_put(dev)        do { } while (0)
1626 
1627 static inline void pci_set_master(struct pci_dev *dev) { }
1628 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1629 static inline void pci_disable_device(struct pci_dev *dev) { }
1630 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1631 { return -EBUSY; }
1632 static inline int __pci_register_driver(struct pci_driver *drv,
1633                                         struct module *owner)
1634 { return 0; }
1635 static inline int pci_register_driver(struct pci_driver *drv)
1636 { return 0; }
1637 static inline void pci_unregister_driver(struct pci_driver *drv) { }
1638 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1639 { return 0; }
1640 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1641                                            int cap)
1642 { return 0; }
1643 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1644 { return 0; }
1645 
1646 /* Power management related routines */
1647 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1648 static inline void pci_restore_state(struct pci_dev *dev) { }
1649 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1650 { return 0; }
1651 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1652 { return 0; }
1653 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1654                                            pm_message_t state)
1655 { return PCI_D0; }
1656 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1657                                   int enable)
1658 { return 0; }
1659 
1660 static inline struct resource *pci_find_resource(struct pci_dev *dev,
1661                                                  struct resource *res)
1662 { return NULL; }
1663 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1664 { return -EIO; }
1665 static inline void pci_release_regions(struct pci_dev *dev) { }
1666 
1667 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1668 
1669 static inline void pci_block_cfg_access(struct pci_dev *dev) { }
1670 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1671 { return 0; }
1672 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { }
1673 
1674 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1675 { return NULL; }
1676 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1677                                                 unsigned int devfn)
1678 { return NULL; }
1679 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1680                                                 unsigned int devfn)
1681 { return NULL; }
1682 
1683 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1684 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1685 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1686 
1687 #define dev_is_pci(d) (false)
1688 #define dev_is_pf(d) (false)
1689 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1690 { return false; }
1691 #endif /* CONFIG_PCI */
1692 
1693 /* Include architecture-dependent settings and functions */
1694 
1695 #include <asm/pci.h>
1696 
1697 /* These two functions provide almost identical functionality. Depennding
1698  * on the architecture, one will be implemented as a wrapper around the
1699  * other (in drivers/pci/mmap.c).
1700  *
1701  * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1702  * is expected to be an offset within that region.
1703  *
1704  * pci_mmap_page_range() is the legacy architecture-specific interface,
1705  * which accepts a "user visible" resource address converted by
1706  * pci_resource_to_user(), as used in the legacy mmap() interface in
1707  * /proc/bus/pci/.
1708  */
1709 int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1710                             struct vm_area_struct *vma,
1711                             enum pci_mmap_state mmap_state, int write_combine);
1712 int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1713                         struct vm_area_struct *vma,
1714                         enum pci_mmap_state mmap_state, int write_combine);
1715 
1716 #ifndef arch_can_pci_mmap_wc
1717 #define arch_can_pci_mmap_wc()          0
1718 #endif
1719 
1720 #ifndef arch_can_pci_mmap_io
1721 #define arch_can_pci_mmap_io()          0
1722 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1723 #else
1724 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1725 #endif
1726 
1727 #ifndef pci_root_bus_fwnode
1728 #define pci_root_bus_fwnode(bus)        NULL
1729 #endif
1730 
1731 /* these helpers provide future and backwards compatibility
1732  * for accessing popular PCI BAR info */
1733 #define pci_resource_start(dev, bar)    ((dev)->resource[(bar)].start)
1734 #define pci_resource_end(dev, bar)      ((dev)->resource[(bar)].end)
1735 #define pci_resource_flags(dev, bar)    ((dev)->resource[(bar)].flags)
1736 #define pci_resource_len(dev,bar) \
1737         ((pci_resource_start((dev), (bar)) == 0 &&      \
1738           pci_resource_end((dev), (bar)) ==             \
1739           pci_resource_start((dev), (bar))) ? 0 :       \
1740                                                         \
1741          (pci_resource_end((dev), (bar)) -              \
1742           pci_resource_start((dev), (bar)) + 1))
1743 
1744 /* Similar to the helpers above, these manipulate per-pci_dev
1745  * driver-specific data.  They are really just a wrapper around
1746  * the generic device structure functions of these calls.
1747  */
1748 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1749 {
1750         return dev_get_drvdata(&pdev->dev);
1751 }
1752 
1753 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1754 {
1755         dev_set_drvdata(&pdev->dev, data);
1756 }
1757 
1758 /* If you want to know what to call your pci_dev, ask this function.
1759  * Again, it's a wrapper around the generic device.
1760  */
1761 static inline const char *pci_name(const struct pci_dev *pdev)
1762 {
1763         return dev_name(&pdev->dev);
1764 }
1765 
1766 
1767 /* Some archs don't want to expose struct resource to userland as-is
1768  * in sysfs and /proc
1769  */
1770 #ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER
1771 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1772                           const struct resource *rsrc,
1773                           resource_size_t *start, resource_size_t *end);
1774 #else
1775 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1776                 const struct resource *rsrc, resource_size_t *start,
1777                 resource_size_t *end)
1778 {
1779         *start = rsrc->start;
1780         *end = rsrc->end;
1781 }
1782 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1783 
1784 
1785 /*
1786  *  The world is not perfect and supplies us with broken PCI devices.
1787  *  For at least a part of these bugs we need a work-around, so both
1788  *  generic (drivers/pci/quirks.c) and per-architecture code can define
1789  *  fixup hooks to be called for particular buggy devices.
1790  */
1791 
1792 struct pci_fixup {
1793         u16 vendor;             /* You can use PCI_ANY_ID here of course */
1794         u16 device;             /* You can use PCI_ANY_ID here of course */
1795         u32 class;              /* You can use PCI_ANY_ID here too */
1796         unsigned int class_shift;       /* should be 0, 8, 16 */
1797         void (*hook)(struct pci_dev *dev);
1798 };
1799 
1800 enum pci_fixup_pass {
1801         pci_fixup_early,        /* Before probing BARs */
1802         pci_fixup_header,       /* After reading configuration header */
1803         pci_fixup_final,        /* Final phase of device fixups */
1804         pci_fixup_enable,       /* pci_enable_device() time */
1805         pci_fixup_resume,       /* pci_device_resume() */
1806         pci_fixup_suspend,      /* pci_device_suspend() */
1807         pci_fixup_resume_early, /* pci_device_resume_early() */
1808         pci_fixup_suspend_late, /* pci_device_suspend_late() */
1809 };
1810 
1811 /* Anonymous variables would be nice... */
1812 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1813                                   class_shift, hook)                    \
1814         static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used       \
1815         __attribute__((__section__(#section), aligned((sizeof(void *)))))    \
1816                 = { vendor, device, class, class_shift, hook };
1817 
1818 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class,            \
1819                                          class_shift, hook)             \
1820         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early,                     \
1821                 hook, vendor, device, class, class_shift, hook)
1822 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class,           \
1823                                          class_shift, hook)             \
1824         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header,                    \
1825                 hook, vendor, device, class, class_shift, hook)
1826 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class,            \
1827                                          class_shift, hook)             \
1828         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final,                     \
1829                 hook, vendor, device, class, class_shift, hook)
1830 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class,           \
1831                                          class_shift, hook)             \
1832         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable,                    \
1833                 hook, vendor, device, class, class_shift, hook)
1834 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class,           \
1835                                          class_shift, hook)             \
1836         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume,                    \
1837                 resume##hook, vendor, device, class,    \
1838                 class_shift, hook)
1839 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class,     \
1840                                          class_shift, hook)             \
1841         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early,              \
1842                 resume_early##hook, vendor, device,     \
1843                 class, class_shift, hook)
1844 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class,          \
1845                                          class_shift, hook)             \
1846         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend,                   \
1847                 suspend##hook, vendor, device, class,   \
1848                 class_shift, hook)
1849 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class,     \
1850                                          class_shift, hook)             \
1851         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late,              \
1852                 suspend_late##hook, vendor, device,     \
1853                 class, class_shift, hook)
1854 
1855 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook)                   \
1856         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early,                     \
1857                 hook, vendor, device, PCI_ANY_ID, 0, hook)
1858 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook)                  \
1859         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header,                    \
1860                 hook, vendor, device, PCI_ANY_ID, 0, hook)
1861 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook)                   \
1862         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final,                     \
1863                 hook, vendor, device, PCI_ANY_ID, 0, hook)
1864 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook)                  \
1865         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable,                    \
1866                 hook, vendor, device, PCI_ANY_ID, 0, hook)
1867 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook)                  \
1868         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume,                    \
1869                 resume##hook, vendor, device,           \
1870                 PCI_ANY_ID, 0, hook)
1871 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook)            \
1872         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early,              \
1873                 resume_early##hook, vendor, device,     \
1874                 PCI_ANY_ID, 0, hook)
1875 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook)                 \
1876         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend,                   \
1877                 suspend##hook, vendor, device,          \
1878                 PCI_ANY_ID, 0, hook)
1879 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook)            \
1880         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late,              \
1881                 suspend_late##hook, vendor, device,     \
1882                 PCI_ANY_ID, 0, hook)
1883 
1884 #ifdef CONFIG_PCI_QUIRKS
1885 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1886 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
1887 int pci_dev_specific_enable_acs(struct pci_dev *dev);
1888 #else
1889 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1890                                     struct pci_dev *dev) { }
1891 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1892                                                u16 acs_flags)
1893 {
1894         return -ENOTTY;
1895 }
1896 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
1897 {
1898         return -ENOTTY;
1899 }
1900 #endif
1901 
1902 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1903 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1904 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1905 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1906 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1907                                    const char *name);
1908 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1909 
1910 extern int pci_pci_problems;
1911 #define PCIPCI_FAIL             1       /* No PCI PCI DMA */
1912 #define PCIPCI_TRITON           2
1913 #define PCIPCI_NATOMA           4
1914 #define PCIPCI_VIAETBF          8
1915 #define PCIPCI_VSFX             16
1916 #define PCIPCI_ALIMAGIK         32      /* Need low latency setting */
1917 #define PCIAGP_FAIL             64      /* No PCI to AGP DMA */
1918 
1919 extern unsigned long pci_cardbus_io_size;
1920 extern unsigned long pci_cardbus_mem_size;
1921 extern u8 pci_dfl_cache_line_size;
1922 extern u8 pci_cache_line_size;
1923 
1924 extern unsigned long pci_hotplug_io_size;
1925 extern unsigned long pci_hotplug_mem_size;
1926 extern unsigned long pci_hotplug_bus_size;
1927 
1928 /* Architecture-specific versions may override these (weak) */
1929 void pcibios_disable_device(struct pci_dev *dev);
1930 void pcibios_set_master(struct pci_dev *dev);
1931 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1932                                  enum pcie_reset_state state);
1933 int pcibios_add_device(struct pci_dev *dev);
1934 void pcibios_release_device(struct pci_dev *dev);
1935 void pcibios_penalize_isa_irq(int irq, int active);
1936 int pcibios_alloc_irq(struct pci_dev *dev);
1937 void pcibios_free_irq(struct pci_dev *dev);
1938 
1939 #ifdef CONFIG_HIBERNATE_CALLBACKS
1940 extern struct dev_pm_ops pcibios_pm_ops;
1941 #endif
1942 
1943 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
1944 void __init pci_mmcfg_early_init(void);
1945 void __init pci_mmcfg_late_init(void);
1946 #else
1947 static inline void pci_mmcfg_early_init(void) { }
1948 static inline void pci_mmcfg_late_init(void) { }
1949 #endif
1950 
1951 int pci_ext_cfg_avail(void);
1952 
1953 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1954 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
1955 
1956 #ifdef CONFIG_PCI_IOV
1957 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
1958 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
1959 
1960 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1961 void pci_disable_sriov(struct pci_dev *dev);
1962 int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset);
1963 void pci_iov_remove_virtfn(struct pci_dev *dev, int id, int reset);
1964 int pci_num_vf(struct pci_dev *dev);
1965 int pci_vfs_assigned(struct pci_dev *dev);
1966 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1967 int pci_sriov_get_totalvfs(struct pci_dev *dev);
1968 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
1969 #else
1970 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
1971 {
1972         return -ENOSYS;
1973 }
1974 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
1975 {
1976         return -ENOSYS;
1977 }
1978 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1979 { return -ENODEV; }
1980 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset)
1981 {
1982         return -ENOSYS;
1983 }
1984 static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
1985                                          int id, int reset) { }
1986 static inline void pci_disable_sriov(struct pci_dev *dev) { }
1987 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
1988 static inline int pci_vfs_assigned(struct pci_dev *dev)
1989 { return 0; }
1990 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
1991 { return 0; }
1992 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
1993 { return 0; }
1994 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
1995 { return 0; }
1996 #endif
1997 
1998 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1999 void pci_hp_create_module_link(struct pci_slot *pci_slot);
2000 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
2001 #endif
2002 
2003 /**
2004  * pci_pcie_cap - get the saved PCIe capability offset
2005  * @dev: PCI device
2006  *
2007  * PCIe capability offset is calculated at PCI device initialization
2008  * time and saved in the data structure. This function returns saved
2009  * PCIe capability offset. Using this instead of pci_find_capability()
2010  * reduces unnecessary search in the PCI configuration space. If you
2011  * need to calculate PCIe capability offset from raw device for some
2012  * reasons, please use pci_find_capability() instead.
2013  */
2014 static inline int pci_pcie_cap(struct pci_dev *dev)
2015 {
2016         return dev->pcie_cap;
2017 }
2018 
2019 /**
2020  * pci_is_pcie - check if the PCI device is PCI Express capable
2021  * @dev: PCI device
2022  *
2023  * Returns: true if the PCI device is PCI Express capable, false otherwise.
2024  */
2025 static inline bool pci_is_pcie(struct pci_dev *dev)
2026 {
2027         return pci_pcie_cap(dev);
2028 }
2029 
2030 /**
2031  * pcie_caps_reg - get the PCIe Capabilities Register
2032  * @dev: PCI device
2033  */
2034 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2035 {
2036         return dev->pcie_flags_reg;
2037 }
2038 
2039 /**
2040  * pci_pcie_type - get the PCIe device/port type
2041  * @dev: PCI device
2042  */
2043 static inline int pci_pcie_type(const struct pci_dev *dev)
2044 {
2045         return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2046 }
2047 
2048 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2049 {
2050         while (1) {
2051                 if (!pci_is_pcie(dev))
2052                         break;
2053                 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2054                         return dev;
2055                 if (!dev->bus->self)
2056                         break;
2057                 dev = dev->bus->self;
2058         }
2059         return NULL;
2060 }
2061 
2062 void pci_request_acs(void);
2063 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2064 bool pci_acs_path_enabled(struct pci_dev *start,
2065                           struct pci_dev *end, u16 acs_flags);
2066 
2067 #define PCI_VPD_LRDT                    0x80    /* Large Resource Data Type */
2068 #define PCI_VPD_LRDT_ID(x)              ((x) | PCI_VPD_LRDT)
2069 
2070 /* Large Resource Data Type Tag Item Names */
2071 #define PCI_VPD_LTIN_ID_STRING          0x02    /* Identifier String */
2072 #define PCI_VPD_LTIN_RO_DATA            0x10    /* Read-Only Data */
2073 #define PCI_VPD_LTIN_RW_DATA            0x11    /* Read-Write Data */
2074 
2075 #define PCI_VPD_LRDT_ID_STRING          PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2076 #define PCI_VPD_LRDT_RO_DATA            PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2077 #define PCI_VPD_LRDT_RW_DATA            PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2078 
2079 /* Small Resource Data Type Tag Item Names */
2080 #define PCI_VPD_STIN_END                0x0f    /* End */
2081 
2082 #define PCI_VPD_SRDT_END                (PCI_VPD_STIN_END << 3)
2083 
2084 #define PCI_VPD_SRDT_TIN_MASK           0x78
2085 #define PCI_VPD_SRDT_LEN_MASK           0x07
2086 #define PCI_VPD_LRDT_TIN_MASK           0x7f
2087 
2088 #define PCI_VPD_LRDT_TAG_SIZE           3
2089 #define PCI_VPD_SRDT_TAG_SIZE           1
2090 
2091 #define PCI_VPD_INFO_FLD_HDR_SIZE       3
2092 
2093 #define PCI_VPD_RO_KEYWORD_PARTNO       "PN"
2094 #define PCI_VPD_RO_KEYWORD_MFR_ID       "MN"
2095 #define PCI_VPD_RO_KEYWORD_VENDOR0      "V0"
2096 #define PCI_VPD_RO_KEYWORD_CHKSUM       "RV"
2097 
2098 /**
2099  * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
2100  * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2101  *
2102  * Returns the extracted Large Resource Data Type length.
2103  */
2104 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
2105 {
2106         return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
2107 }
2108 
2109 /**
2110  * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
2111  * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2112  *
2113  * Returns the extracted Large Resource Data Type Tag item.
2114  */
2115 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
2116 {
2117     return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
2118 }
2119 
2120 /**
2121  * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
2122  * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2123  *
2124  * Returns the extracted Small Resource Data Type length.
2125  */
2126 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
2127 {
2128         return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
2129 }
2130 
2131 /**
2132  * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
2133  * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2134  *
2135  * Returns the extracted Small Resource Data Type Tag Item.
2136  */
2137 static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
2138 {
2139         return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
2140 }
2141 
2142 /**
2143  * pci_vpd_info_field_size - Extracts the information field length
2144  * @lrdt: Pointer to the beginning of an information field header
2145  *
2146  * Returns the extracted information field length.
2147  */
2148 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
2149 {
2150         return info_field[2];
2151 }
2152 
2153 /**
2154  * pci_vpd_find_tag - Locates the Resource Data Type tag provided
2155  * @buf: Pointer to buffered vpd data
2156  * @off: The offset into the buffer at which to begin the search
2157  * @len: The length of the vpd buffer
2158  * @rdt: The Resource Data Type to search for
2159  *
2160  * Returns the index where the Resource Data Type was found or
2161  * -ENOENT otherwise.
2162  */
2163 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
2164 
2165 /**
2166  * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
2167  * @buf: Pointer to buffered vpd data
2168  * @off: The offset into the buffer at which to begin the search
2169  * @len: The length of the buffer area, relative to off, in which to search
2170  * @kw: The keyword to search for
2171  *
2172  * Returns the index where the information field keyword was found or
2173  * -ENOENT otherwise.
2174  */
2175 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2176                               unsigned int len, const char *kw);
2177 
2178 /* PCI <-> OF binding helpers */
2179 #ifdef CONFIG_OF
2180 struct device_node;
2181 struct irq_domain;
2182 void pci_set_of_node(struct pci_dev *dev);
2183 void pci_release_of_node(struct pci_dev *dev);
2184 void pci_set_bus_of_node(struct pci_bus *bus);
2185 void pci_release_bus_of_node(struct pci_bus *bus);
2186 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2187 
2188 /* Arch may override this (weak) */
2189 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2190 
2191 static inline struct device_node *
2192 pci_device_to_OF_node(const struct pci_dev *pdev)
2193 {
2194         return pdev ? pdev->dev.of_node : NULL;
2195 }
2196 
2197 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2198 {
2199         return bus ? bus->dev.of_node : NULL;
2200 }
2201 
2202 #else /* CONFIG_OF */
2203 static inline void pci_set_of_node(struct pci_dev *dev) { }
2204 static inline void pci_release_of_node(struct pci_dev *dev) { }
2205 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
2206 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
2207 static inline struct device_node *
2208 pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; }
2209 static inline struct irq_domain *
2210 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2211 #endif  /* CONFIG_OF */
2212 
2213 #ifdef CONFIG_ACPI
2214 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2215 
2216 void
2217 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2218 #else
2219 static inline struct irq_domain *
2220 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2221 #endif
2222 
2223 #ifdef CONFIG_EEH
2224 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2225 {
2226         return pdev->dev.archdata.edev;
2227 }
2228 #endif
2229 
2230 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn);
2231 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2232 int pci_for_each_dma_alias(struct pci_dev *pdev,
2233                            int (*fn)(struct pci_dev *pdev,
2234                                      u16 alias, void *data), void *data);
2235 
2236 /* helper functions for operation of device flag */
2237 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2238 {
2239         pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2240 }
2241 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2242 {
2243         pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2244 }
2245 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2246 {
2247         return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2248 }
2249 
2250 /**
2251  * pci_ari_enabled - query ARI forwarding status
2252  * @bus: the PCI bus
2253  *
2254  * Returns true if ARI forwarding is enabled.
2255  */
2256 static inline bool pci_ari_enabled(struct pci_bus *bus)
2257 {
2258         return bus->self && bus->self->ari_enabled;
2259 }
2260 
2261 /**
2262  * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2263  * @pdev: PCI device to check
2264  *
2265  * Walk upwards from @pdev and check for each encountered bridge if it's part
2266  * of a Thunderbolt controller.  Reaching the host bridge means @pdev is not
2267  * Thunderbolt-attached.  (But rather soldered to the mainboard usually.)
2268  */
2269 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2270 {
2271         struct pci_dev *parent = pdev;
2272 
2273         if (pdev->is_thunderbolt)
2274                 return true;
2275 
2276         while ((parent = pci_upstream_bridge(parent)))
2277                 if (parent->is_thunderbolt)
2278                         return true;
2279 
2280         return false;
2281 }
2282 
2283 /* provide the legacy pci_dma_* API */
2284 #include <linux/pci-dma-compat.h>
2285 
2286 #endif /* LINUX_PCI_H */
2287 

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