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TOMOYO Linux Cross Reference
Linux/include/linux/pci.h

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  1 /*
  2  *      pci.h
  3  *
  4  *      PCI defines and function prototypes
  5  *      Copyright 1994, Drew Eckhardt
  6  *      Copyright 1997--1999 Martin Mares <mj@ucw.cz>
  7  *
  8  *      For more information, please consult the following manuals (look at
  9  *      http://www.pcisig.com/ for how to get them):
 10  *
 11  *      PCI BIOS Specification
 12  *      PCI Local Bus Specification
 13  *      PCI to PCI Bridge Specification
 14  *      PCI System Design Guide
 15  */
 16 #ifndef LINUX_PCI_H
 17 #define LINUX_PCI_H
 18 
 19 
 20 #include <linux/mod_devicetable.h>
 21 
 22 #include <linux/types.h>
 23 #include <linux/init.h>
 24 #include <linux/ioport.h>
 25 #include <linux/list.h>
 26 #include <linux/compiler.h>
 27 #include <linux/errno.h>
 28 #include <linux/kobject.h>
 29 #include <linux/atomic.h>
 30 #include <linux/device.h>
 31 #include <linux/io.h>
 32 #include <linux/irqreturn.h>
 33 #include <uapi/linux/pci.h>
 34 
 35 /* Include the ID list */
 36 #include <linux/pci_ids.h>
 37 
 38 /*
 39  * The PCI interface treats multi-function devices as independent
 40  * devices.  The slot/function address of each device is encoded
 41  * in a single byte as follows:
 42  *
 43  *      7:3 = slot
 44  *      2:0 = function
 45  * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined uapi/linux/pci.h
 46  * In the interest of not exposing interfaces to user-space unnecessarily,
 47  * the following kernel only defines are being added here.
 48  */
 49 #define PCI_DEVID(bus, devfn)  ((((u16)bus) << 8) | devfn)
 50 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
 51 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
 52 
 53 /* pci_slot represents a physical slot */
 54 struct pci_slot {
 55         struct pci_bus *bus;            /* The bus this slot is on */
 56         struct list_head list;          /* node in list of slots on this bus */
 57         struct hotplug_slot *hotplug;   /* Hotplug info (migrate over time) */
 58         unsigned char number;           /* PCI_SLOT(pci_dev->devfn) */
 59         struct kobject kobj;
 60 };
 61 
 62 static inline const char *pci_slot_name(const struct pci_slot *slot)
 63 {
 64         return kobject_name(&slot->kobj);
 65 }
 66 
 67 /* File state for mmap()s on /proc/bus/pci/X/Y */
 68 enum pci_mmap_state {
 69         pci_mmap_io,
 70         pci_mmap_mem
 71 };
 72 
 73 /* This defines the direction arg to the DMA mapping routines. */
 74 #define PCI_DMA_BIDIRECTIONAL   0
 75 #define PCI_DMA_TODEVICE        1
 76 #define PCI_DMA_FROMDEVICE      2
 77 #define PCI_DMA_NONE            3
 78 
 79 /*
 80  *  For PCI devices, the region numbers are assigned this way:
 81  */
 82 enum {
 83         /* #0-5: standard PCI resources */
 84         PCI_STD_RESOURCES,
 85         PCI_STD_RESOURCE_END = 5,
 86 
 87         /* #6: expansion ROM resource */
 88         PCI_ROM_RESOURCE,
 89 
 90         /* device specific resources */
 91 #ifdef CONFIG_PCI_IOV
 92         PCI_IOV_RESOURCES,
 93         PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
 94 #endif
 95 
 96         /* resources assigned to buses behind the bridge */
 97 #define PCI_BRIDGE_RESOURCE_NUM 4
 98 
 99         PCI_BRIDGE_RESOURCES,
100         PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
101                                   PCI_BRIDGE_RESOURCE_NUM - 1,
102 
103         /* total resources associated with a PCI device */
104         PCI_NUM_RESOURCES,
105 
106         /* preserve this for compatibility */
107         DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
108 };
109 
110 typedef int __bitwise pci_power_t;
111 
112 #define PCI_D0          ((pci_power_t __force) 0)
113 #define PCI_D1          ((pci_power_t __force) 1)
114 #define PCI_D2          ((pci_power_t __force) 2)
115 #define PCI_D3hot       ((pci_power_t __force) 3)
116 #define PCI_D3cold      ((pci_power_t __force) 4)
117 #define PCI_UNKNOWN     ((pci_power_t __force) 5)
118 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
119 
120 /* Remember to update this when the list above changes! */
121 extern const char *pci_power_names[];
122 
123 static inline const char *pci_power_name(pci_power_t state)
124 {
125         return pci_power_names[1 + (int) state];
126 }
127 
128 #define PCI_PM_D2_DELAY         200
129 #define PCI_PM_D3_WAIT          10
130 #define PCI_PM_D3COLD_WAIT      100
131 #define PCI_PM_BUS_WAIT         50
132 
133 /** The pci_channel state describes connectivity between the CPU and
134  *  the pci device.  If some PCI bus between here and the pci device
135  *  has crashed or locked up, this info is reflected here.
136  */
137 typedef unsigned int __bitwise pci_channel_state_t;
138 
139 enum pci_channel_state {
140         /* I/O channel is in normal state */
141         pci_channel_io_normal = (__force pci_channel_state_t) 1,
142 
143         /* I/O to channel is blocked */
144         pci_channel_io_frozen = (__force pci_channel_state_t) 2,
145 
146         /* PCI card is dead */
147         pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
148 };
149 
150 typedef unsigned int __bitwise pcie_reset_state_t;
151 
152 enum pcie_reset_state {
153         /* Reset is NOT asserted (Use to deassert reset) */
154         pcie_deassert_reset = (__force pcie_reset_state_t) 1,
155 
156         /* Use #PERST to reset PCI-E device */
157         pcie_warm_reset = (__force pcie_reset_state_t) 2,
158 
159         /* Use PCI-E Hot Reset to reset device */
160         pcie_hot_reset = (__force pcie_reset_state_t) 3
161 };
162 
163 typedef unsigned short __bitwise pci_dev_flags_t;
164 enum pci_dev_flags {
165         /* INTX_DISABLE in PCI_COMMAND register disables MSI
166          * generation too.
167          */
168         PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1,
169         /* Device configuration is irrevocably lost if disabled into D3 */
170         PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
171         /* Provide indication device is assigned by a Virtual Machine Manager */
172         PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) 4,
173 };
174 
175 enum pci_irq_reroute_variant {
176         INTEL_IRQ_REROUTE_VARIANT = 1,
177         MAX_IRQ_REROUTE_VARIANTS = 3
178 };
179 
180 typedef unsigned short __bitwise pci_bus_flags_t;
181 enum pci_bus_flags {
182         PCI_BUS_FLAGS_NO_MSI   = (__force pci_bus_flags_t) 1,
183         PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
184 };
185 
186 /* Based on the PCI Hotplug Spec, but some values are made up by us */
187 enum pci_bus_speed {
188         PCI_SPEED_33MHz                 = 0x00,
189         PCI_SPEED_66MHz                 = 0x01,
190         PCI_SPEED_66MHz_PCIX            = 0x02,
191         PCI_SPEED_100MHz_PCIX           = 0x03,
192         PCI_SPEED_133MHz_PCIX           = 0x04,
193         PCI_SPEED_66MHz_PCIX_ECC        = 0x05,
194         PCI_SPEED_100MHz_PCIX_ECC       = 0x06,
195         PCI_SPEED_133MHz_PCIX_ECC       = 0x07,
196         PCI_SPEED_66MHz_PCIX_266        = 0x09,
197         PCI_SPEED_100MHz_PCIX_266       = 0x0a,
198         PCI_SPEED_133MHz_PCIX_266       = 0x0b,
199         AGP_UNKNOWN                     = 0x0c,
200         AGP_1X                          = 0x0d,
201         AGP_2X                          = 0x0e,
202         AGP_4X                          = 0x0f,
203         AGP_8X                          = 0x10,
204         PCI_SPEED_66MHz_PCIX_533        = 0x11,
205         PCI_SPEED_100MHz_PCIX_533       = 0x12,
206         PCI_SPEED_133MHz_PCIX_533       = 0x13,
207         PCIE_SPEED_2_5GT                = 0x14,
208         PCIE_SPEED_5_0GT                = 0x15,
209         PCIE_SPEED_8_0GT                = 0x16,
210         PCI_SPEED_UNKNOWN               = 0xff,
211 };
212 
213 struct pci_cap_saved_data {
214         char cap_nr;
215         unsigned int size;
216         u32 data[0];
217 };
218 
219 struct pci_cap_saved_state {
220         struct hlist_node next;
221         struct pci_cap_saved_data cap;
222 };
223 
224 struct pcie_link_state;
225 struct pci_vpd;
226 struct pci_sriov;
227 struct pci_ats;
228 
229 /*
230  * The pci_dev structure is used to describe PCI devices.
231  */
232 struct pci_dev {
233         struct list_head bus_list;      /* node in per-bus list */
234         struct pci_bus  *bus;           /* bus this device is on */
235         struct pci_bus  *subordinate;   /* bus this device bridges to */
236 
237         void            *sysdata;       /* hook for sys-specific extension */
238         struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
239         struct pci_slot *slot;          /* Physical slot this device is in */
240 
241         unsigned int    devfn;          /* encoded device & function index */
242         unsigned short  vendor;
243         unsigned short  device;
244         unsigned short  subsystem_vendor;
245         unsigned short  subsystem_device;
246         unsigned int    class;          /* 3 bytes: (base,sub,prog-if) */
247         u8              revision;       /* PCI revision, low byte of class word */
248         u8              hdr_type;       /* PCI header type (`multi' flag masked out) */
249         u8              pcie_cap;       /* PCI-E capability offset */
250         u8              msi_cap;        /* MSI capability offset */
251         u8              msix_cap;       /* MSI-X capability offset */
252         u8              pcie_mpss:3;    /* PCI-E Max Payload Size Supported */
253         u8              rom_base_reg;   /* which config register controls the ROM */
254         u8              pin;            /* which interrupt pin this device uses */
255         u16             pcie_flags_reg; /* cached PCI-E Capabilities Register */
256 
257         struct pci_driver *driver;      /* which driver has allocated this device */
258         u64             dma_mask;       /* Mask of the bits of bus address this
259                                            device implements.  Normally this is
260                                            0xffffffff.  You only need to change
261                                            this if your device has broken DMA
262                                            or supports 64-bit transfers.  */
263 
264         struct device_dma_parameters dma_parms;
265 
266         pci_power_t     current_state;  /* Current operating state. In ACPI-speak,
267                                            this is D0-D3, D0 being fully functional,
268                                            and D3 being off. */
269         u8              pm_cap;         /* PM capability offset */
270         unsigned int    pme_support:5;  /* Bitmask of states from which PME#
271                                            can be generated */
272         unsigned int    pme_interrupt:1;
273         unsigned int    pme_poll:1;     /* Poll device's PME status bit */
274         unsigned int    d1_support:1;   /* Low power state D1 is supported */
275         unsigned int    d2_support:1;   /* Low power state D2 is supported */
276         unsigned int    no_d1d2:1;      /* D1 and D2 are forbidden */
277         unsigned int    no_d3cold:1;    /* D3cold is forbidden */
278         unsigned int    d3cold_allowed:1;       /* D3cold is allowed by user */
279         unsigned int    mmio_always_on:1;       /* disallow turning off io/mem
280                                                    decoding during bar sizing */
281         unsigned int    wakeup_prepared:1;
282         unsigned int    runtime_d3cold:1;       /* whether go through runtime
283                                                    D3cold, not set for devices
284                                                    powered on/off by the
285                                                    corresponding bridge */
286         unsigned int    d3_delay;       /* D3->D0 transition time in ms */
287         unsigned int    d3cold_delay;   /* D3cold->D0 transition time in ms */
288 
289 #ifdef CONFIG_PCIEASPM
290         struct pcie_link_state  *link_state;    /* ASPM link state. */
291 #endif
292 
293         pci_channel_state_t error_state;        /* current connectivity state */
294         struct  device  dev;            /* Generic device interface */
295 
296         int             cfg_size;       /* Size of configuration space */
297 
298         /*
299          * Instead of touching interrupt line and base address registers
300          * directly, use the values stored here. They might be different!
301          */
302         unsigned int    irq;
303         struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
304 
305         bool match_driver;              /* Skip attaching driver */
306         /* These fields are used by common fixups */
307         unsigned int    transparent:1;  /* Transparent PCI bridge */
308         unsigned int    multifunction:1;/* Part of multi-function device */
309         /* keep track of device state */
310         unsigned int    is_added:1;
311         unsigned int    is_busmaster:1; /* device is busmaster */
312         unsigned int    no_msi:1;       /* device may not use msi */
313         unsigned int    no_64bit_msi:1; /* device may only use 32-bit MSIs */
314         unsigned int    block_cfg_access:1;     /* config space access is blocked */
315         unsigned int    broken_parity_status:1; /* Device generates false positive parity */
316         unsigned int    irq_reroute_variant:2;  /* device needs IRQ rerouting variant */
317         unsigned int    msi_enabled:1;
318         unsigned int    msix_enabled:1;
319         unsigned int    ari_enabled:1;  /* ARI forwarding */
320         unsigned int    is_managed:1;
321         unsigned int    is_pcie:1;      /* Obsolete. Will be removed.
322                                            Use pci_is_pcie() instead */
323         unsigned int    needs_freset:1; /* Dev requires fundamental reset */
324         unsigned int    state_saved:1;
325         unsigned int    is_physfn:1;
326         unsigned int    is_virtfn:1;
327         unsigned int    reset_fn:1;
328         unsigned int    is_hotplug_bridge:1;
329         unsigned int    __aer_firmware_first_valid:1;
330         unsigned int    __aer_firmware_first:1;
331         unsigned int    broken_intx_masking:1;
332         unsigned int    io_window_1k:1; /* Intel P2P bridge 1K I/O windows */
333         unsigned int    non_compliant_bars:1;   /* broken BARs; ignore them */
334         pci_dev_flags_t dev_flags;
335         atomic_t        enable_cnt;     /* pci_enable_device has been called */
336 
337         u32             saved_config_space[16]; /* config space saved at suspend time */
338         struct hlist_head saved_cap_space;
339         struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
340         int rom_attr_enabled;           /* has display of the rom attribute been enabled? */
341         struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
342         struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
343 #ifdef CONFIG_PCI_MSI
344         struct list_head msi_list;
345         struct kset *msi_kset;
346 #endif
347         struct pci_vpd *vpd;
348 #ifdef CONFIG_PCI_ATS
349         union {
350                 struct pci_sriov *sriov;        /* SR-IOV capability related */
351                 struct pci_dev *physfn; /* the PF this VF is associated with */
352         };
353         struct pci_ats  *ats;   /* Address Translation Service */
354 #endif
355         phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */
356         size_t romlen; /* Length of ROM if it's not from the BAR */
357 };
358 
359 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
360 {
361 #ifdef CONFIG_PCI_IOV
362         if (dev->is_virtfn)
363                 dev = dev->physfn;
364 #endif
365 
366         return dev;
367 }
368 
369 struct pci_dev *alloc_pci_dev(void);
370 
371 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
372 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
373 
374 static inline int pci_channel_offline(struct pci_dev *pdev)
375 {
376         return (pdev->error_state != pci_channel_io_normal);
377 }
378 
379 extern struct resource busn_resource;
380 
381 struct pci_host_bridge_window {
382         struct list_head list;
383         struct resource *res;           /* host bridge aperture (CPU address) */
384         resource_size_t offset;         /* bus address + offset = CPU address */
385 };
386 
387 struct pci_host_bridge {
388         struct device dev;
389         struct pci_bus *bus;            /* root bus */
390         struct list_head windows;       /* pci_host_bridge_windows */
391         void (*release_fn)(struct pci_host_bridge *);
392         void *release_data;
393 };
394 
395 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
396 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
397                      void (*release_fn)(struct pci_host_bridge *),
398                      void *release_data);
399 
400 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
401 
402 /*
403  * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
404  * to P2P or CardBus bridge windows) go in a table.  Additional ones (for
405  * buses below host bridges or subtractive decode bridges) go in the list.
406  * Use pci_bus_for_each_resource() to iterate through all the resources.
407  */
408 
409 /*
410  * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
411  * and there's no way to program the bridge with the details of the window.
412  * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
413  * decode bit set, because they are explicit and can be programmed with _SRS.
414  */
415 #define PCI_SUBTRACTIVE_DECODE  0x1
416 
417 struct pci_bus_resource {
418         struct list_head list;
419         struct resource *res;
420         unsigned int flags;
421 };
422 
423 #define PCI_REGION_FLAG_MASK    0x0fU   /* These bits of resource flags tell us the PCI region flags */
424 
425 struct pci_bus {
426         struct list_head node;          /* node in list of buses */
427         struct pci_bus  *parent;        /* parent bus this bridge is on */
428         struct list_head children;      /* list of child buses */
429         struct list_head devices;       /* list of devices on this bus */
430         struct pci_dev  *self;          /* bridge device as seen by parent */
431         struct list_head slots;         /* list of slots on this bus */
432         struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
433         struct list_head resources;     /* address space routed to this bus */
434         struct resource busn_res;       /* bus numbers routed to this bus */
435 
436         struct pci_ops  *ops;           /* configuration access functions */
437         void            *sysdata;       /* hook for sys-specific extension */
438         struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
439 
440         unsigned char   number;         /* bus number */
441         unsigned char   primary;        /* number of primary bridge */
442         unsigned char   max_bus_speed;  /* enum pci_bus_speed */
443         unsigned char   cur_bus_speed;  /* enum pci_bus_speed */
444 
445         char            name[48];
446 
447         unsigned short  bridge_ctl;     /* manage NO_ISA/FBB/et al behaviors */
448         pci_bus_flags_t bus_flags;      /* Inherited by child busses */
449         struct device           *bridge;
450         struct device           dev;
451         struct bin_attribute    *legacy_io; /* legacy I/O for this bus */
452         struct bin_attribute    *legacy_mem; /* legacy mem */
453         unsigned int            is_added:1;
454 };
455 
456 #define pci_bus_b(n)    list_entry(n, struct pci_bus, node)
457 #define to_pci_bus(n)   container_of(n, struct pci_bus, dev)
458 
459 /*
460  * Returns true if the pci bus is root (behind host-pci bridge),
461  * false otherwise
462  */
463 static inline bool pci_is_root_bus(struct pci_bus *pbus)
464 {
465         return !(pbus->parent);
466 }
467 
468 #ifdef CONFIG_PCI_MSI
469 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
470 {
471         return pci_dev->msi_enabled || pci_dev->msix_enabled;
472 }
473 #else
474 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
475 #endif
476 
477 /*
478  * Error values that may be returned by PCI functions.
479  */
480 #define PCIBIOS_SUCCESSFUL              0x00
481 #define PCIBIOS_FUNC_NOT_SUPPORTED      0x81
482 #define PCIBIOS_BAD_VENDOR_ID           0x83
483 #define PCIBIOS_DEVICE_NOT_FOUND        0x86
484 #define PCIBIOS_BAD_REGISTER_NUMBER     0x87
485 #define PCIBIOS_SET_FAILED              0x88
486 #define PCIBIOS_BUFFER_TOO_SMALL        0x89
487 
488 /*
489  * Translate above to generic errno for passing back through non-pci.
490  */
491 static inline int pcibios_err_to_errno(int err)
492 {
493         if (err <= PCIBIOS_SUCCESSFUL)
494                 return err; /* Assume already errno */
495 
496         switch (err) {
497         case PCIBIOS_FUNC_NOT_SUPPORTED:
498                 return -ENOENT;
499         case PCIBIOS_BAD_VENDOR_ID:
500                 return -EINVAL;
501         case PCIBIOS_DEVICE_NOT_FOUND:
502                 return -ENODEV;
503         case PCIBIOS_BAD_REGISTER_NUMBER:
504                 return -EFAULT;
505         case PCIBIOS_SET_FAILED:
506                 return -EIO;
507         case PCIBIOS_BUFFER_TOO_SMALL:
508                 return -ENOSPC;
509         }
510 
511         return -ENOTTY;
512 }
513 
514 /* Low-level architecture-dependent routines */
515 
516 struct pci_ops {
517         int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
518         int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
519 };
520 
521 /*
522  * ACPI needs to be able to access PCI config space before we've done a
523  * PCI bus scan and created pci_bus structures.
524  */
525 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
526                  int reg, int len, u32 *val);
527 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
528                   int reg, int len, u32 val);
529 
530 struct pci_bus_region {
531         resource_size_t start;
532         resource_size_t end;
533 };
534 
535 struct pci_dynids {
536         spinlock_t lock;            /* protects list, index */
537         struct list_head list;      /* for IDs added at runtime */
538 };
539 
540 /* ---------------------------------------------------------------- */
541 /** PCI Error Recovery System (PCI-ERS).  If a PCI device driver provides
542  *  a set of callbacks in struct pci_error_handlers, then that device driver
543  *  will be notified of PCI bus errors, and will be driven to recovery
544  *  when an error occurs.
545  */
546 
547 typedef unsigned int __bitwise pci_ers_result_t;
548 
549 enum pci_ers_result {
550         /* no result/none/not supported in device driver */
551         PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
552 
553         /* Device driver can recover without slot reset */
554         PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
555 
556         /* Device driver wants slot to be reset. */
557         PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
558 
559         /* Device has completely failed, is unrecoverable */
560         PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
561 
562         /* Device driver is fully recovered and operational */
563         PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
564 
565         /* No AER capabilities registered for the driver */
566         PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
567 };
568 
569 /* PCI bus error event callbacks */
570 struct pci_error_handlers {
571         /* PCI bus error detected on this device */
572         pci_ers_result_t (*error_detected)(struct pci_dev *dev,
573                                            enum pci_channel_state error);
574 
575         /* MMIO has been re-enabled, but not DMA */
576         pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
577 
578         /* PCI Express link has been reset */
579         pci_ers_result_t (*link_reset)(struct pci_dev *dev);
580 
581         /* PCI slot has been reset */
582         pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
583 
584         /* Device driver may resume normal operations */
585         void (*resume)(struct pci_dev *dev);
586 };
587 
588 /* ---------------------------------------------------------------- */
589 
590 struct module;
591 struct pci_driver {
592         struct list_head node;
593         const char *name;
594         const struct pci_device_id *id_table;   /* must be non-NULL for probe to be called */
595         int  (*probe)  (struct pci_dev *dev, const struct pci_device_id *id);   /* New device inserted */
596         void (*remove) (struct pci_dev *dev);   /* Device removed (NULL if not a hot-plug capable driver) */
597         int  (*suspend) (struct pci_dev *dev, pm_message_t state);      /* Device suspended */
598         int  (*suspend_late) (struct pci_dev *dev, pm_message_t state);
599         int  (*resume_early) (struct pci_dev *dev);
600         int  (*resume) (struct pci_dev *dev);                   /* Device woken up */
601         void (*shutdown) (struct pci_dev *dev);
602         int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */
603         const struct pci_error_handlers *err_handler;
604         struct device_driver    driver;
605         struct pci_dynids dynids;
606 };
607 
608 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
609 
610 /**
611  * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
612  * @_table: device table name
613  *
614  * This macro is used to create a struct pci_device_id array (a device table)
615  * in a generic manner.
616  */
617 #define DEFINE_PCI_DEVICE_TABLE(_table) \
618         const struct pci_device_id _table[]
619 
620 /**
621  * PCI_DEVICE - macro used to describe a specific pci device
622  * @vend: the 16 bit PCI Vendor ID
623  * @dev: the 16 bit PCI Device ID
624  *
625  * This macro is used to create a struct pci_device_id that matches a
626  * specific device.  The subvendor and subdevice fields will be set to
627  * PCI_ANY_ID.
628  */
629 #define PCI_DEVICE(vend,dev) \
630         .vendor = (vend), .device = (dev), \
631         .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
632 
633 /**
634  * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
635  * @vend: the 16 bit PCI Vendor ID
636  * @dev: the 16 bit PCI Device ID
637  * @subvend: the 16 bit PCI Subvendor ID
638  * @subdev: the 16 bit PCI Subdevice ID
639  *
640  * This macro is used to create a struct pci_device_id that matches a
641  * specific device with subsystem information.
642  */
643 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
644         .vendor = (vend), .device = (dev), \
645         .subvendor = (subvend), .subdevice = (subdev)
646 
647 /**
648  * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
649  * @dev_class: the class, subclass, prog-if triple for this device
650  * @dev_class_mask: the class mask for this device
651  *
652  * This macro is used to create a struct pci_device_id that matches a
653  * specific PCI class.  The vendor, device, subvendor, and subdevice
654  * fields will be set to PCI_ANY_ID.
655  */
656 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
657         .class = (dev_class), .class_mask = (dev_class_mask), \
658         .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
659         .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
660 
661 /**
662  * PCI_VDEVICE - macro used to describe a specific pci device in short form
663  * @vendor: the vendor name
664  * @device: the 16 bit PCI Device ID
665  *
666  * This macro is used to create a struct pci_device_id that matches a
667  * specific PCI device.  The subvendor, and subdevice fields will be set
668  * to PCI_ANY_ID. The macro allows the next field to follow as the device
669  * private data.
670  */
671 
672 #define PCI_VDEVICE(vendor, device)             \
673         PCI_VENDOR_ID_##vendor, (device),       \
674         PCI_ANY_ID, PCI_ANY_ID, 0, 0
675 
676 /* these external functions are only available when PCI support is enabled */
677 #ifdef CONFIG_PCI
678 
679 void pcie_bus_configure_settings(struct pci_bus *bus, u8 smpss);
680 
681 enum pcie_bus_config_types {
682         PCIE_BUS_TUNE_OFF,
683         PCIE_BUS_SAFE,
684         PCIE_BUS_PERFORMANCE,
685         PCIE_BUS_PEER2PEER,
686 };
687 
688 extern enum pcie_bus_config_types pcie_bus_config;
689 
690 extern struct bus_type pci_bus_type;
691 
692 /* Do NOT directly access these two variables, unless you are arch specific pci
693  * code, or pci core code. */
694 extern struct list_head pci_root_buses; /* list of all known PCI buses */
695 /* Some device drivers need know if pci is initiated */
696 int no_pci_devices(void);
697 
698 void pcibios_resource_survey_bus(struct pci_bus *bus);
699 void pcibios_add_bus(struct pci_bus *bus);
700 void pcibios_remove_bus(struct pci_bus *bus);
701 void pcibios_fixup_bus(struct pci_bus *);
702 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
703 /* Architecture specific versions may override this (weak) */
704 char *pcibios_setup(char *str);
705 
706 /* Used only when drivers/pci/setup.c is used */
707 resource_size_t pcibios_align_resource(void *, const struct resource *,
708                                 resource_size_t,
709                                 resource_size_t);
710 void pcibios_update_irq(struct pci_dev *, int irq);
711 
712 /* Weak but can be overriden by arch */
713 void pci_fixup_cardbus(struct pci_bus *);
714 
715 /* Generic PCI functions used internally */
716 
717 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
718                              struct resource *res);
719 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
720                              struct pci_bus_region *region);
721 void pcibios_scan_specific_bus(int busn);
722 struct pci_bus *pci_find_bus(int domain, int busnr);
723 void pci_bus_add_devices(const struct pci_bus *bus);
724 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
725                                       struct pci_ops *ops, void *sysdata);
726 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
727 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
728                                     struct pci_ops *ops, void *sysdata,
729                                     struct list_head *resources);
730 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
731 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
732 void pci_bus_release_busn_res(struct pci_bus *b);
733 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
734                                              struct pci_ops *ops, void *sysdata,
735                                              struct list_head *resources);
736 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
737                                 int busnr);
738 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
739 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
740                                  const char *name,
741                                  struct hotplug_slot *hotplug);
742 void pci_destroy_slot(struct pci_slot *slot);
743 void pci_renumber_slot(struct pci_slot *slot, int slot_nr);
744 int pci_scan_slot(struct pci_bus *bus, int devfn);
745 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
746 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
747 unsigned int pci_scan_child_bus(struct pci_bus *bus);
748 int __must_check pci_bus_add_device(struct pci_dev *dev);
749 void pci_read_bridge_bases(struct pci_bus *child);
750 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
751                                           struct resource *res);
752 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
753 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
754 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
755 struct pci_dev *pci_dev_get(struct pci_dev *dev);
756 void pci_dev_put(struct pci_dev *dev);
757 void pci_remove_bus(struct pci_bus *b);
758 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
759 void pci_stop_root_bus(struct pci_bus *bus);
760 void pci_remove_root_bus(struct pci_bus *bus);
761 void pci_setup_cardbus(struct pci_bus *bus);
762 void pci_sort_breadthfirst(void);
763 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
764 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
765 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
766 
767 /* Generic PCI functions exported to card drivers */
768 
769 enum pci_lost_interrupt_reason {
770         PCI_LOST_IRQ_NO_INFORMATION = 0,
771         PCI_LOST_IRQ_DISABLE_MSI,
772         PCI_LOST_IRQ_DISABLE_MSIX,
773         PCI_LOST_IRQ_DISABLE_ACPI,
774 };
775 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
776 int pci_find_capability(struct pci_dev *dev, int cap);
777 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
778 int pci_find_ext_capability(struct pci_dev *dev, int cap);
779 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
780 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
781 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
782 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
783 
784 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
785                                 struct pci_dev *from);
786 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
787                                 unsigned int ss_vendor, unsigned int ss_device,
788                                 struct pci_dev *from);
789 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
790 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
791                                             unsigned int devfn);
792 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
793                                                    unsigned int devfn)
794 {
795         return pci_get_domain_bus_and_slot(0, bus, devfn);
796 }
797 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
798 int pci_dev_present(const struct pci_device_id *ids);
799 
800 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
801                              int where, u8 *val);
802 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
803                              int where, u16 *val);
804 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
805                               int where, u32 *val);
806 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
807                               int where, u8 val);
808 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
809                               int where, u16 val);
810 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
811                                int where, u32 val);
812 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
813 
814 static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
815 {
816         return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
817 }
818 static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
819 {
820         return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
821 }
822 static inline int pci_read_config_dword(const struct pci_dev *dev, int where,
823                                         u32 *val)
824 {
825         return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
826 }
827 static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
828 {
829         return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
830 }
831 static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
832 {
833         return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
834 }
835 static inline int pci_write_config_dword(const struct pci_dev *dev, int where,
836                                          u32 val)
837 {
838         return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
839 }
840 
841 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
842 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
843 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
844 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
845 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
846                                        u16 clear, u16 set);
847 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
848                                         u32 clear, u32 set);
849 
850 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
851                                            u16 set)
852 {
853         return pcie_capability_clear_and_set_word(dev, pos, 0, set);
854 }
855 
856 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
857                                             u32 set)
858 {
859         return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
860 }
861 
862 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
863                                              u16 clear)
864 {
865         return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
866 }
867 
868 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
869                                               u32 clear)
870 {
871         return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
872 }
873 
874 /* user-space driven config access */
875 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
876 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
877 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
878 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
879 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
880 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
881 
882 int __must_check pci_enable_device(struct pci_dev *dev);
883 int __must_check pci_enable_device_io(struct pci_dev *dev);
884 int __must_check pci_enable_device_mem(struct pci_dev *dev);
885 int __must_check pci_reenable_device(struct pci_dev *);
886 int __must_check pcim_enable_device(struct pci_dev *pdev);
887 void pcim_pin_device(struct pci_dev *pdev);
888 
889 static inline int pci_is_enabled(struct pci_dev *pdev)
890 {
891         return (atomic_read(&pdev->enable_cnt) > 0);
892 }
893 
894 static inline int pci_is_managed(struct pci_dev *pdev)
895 {
896         return pdev->is_managed;
897 }
898 
899 void pci_disable_device(struct pci_dev *dev);
900 
901 extern unsigned int pcibios_max_latency;
902 void pci_set_master(struct pci_dev *dev);
903 void pci_clear_master(struct pci_dev *dev);
904 
905 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
906 int pci_set_cacheline_size(struct pci_dev *dev);
907 #define HAVE_PCI_SET_MWI
908 int __must_check pci_set_mwi(struct pci_dev *dev);
909 int pci_try_set_mwi(struct pci_dev *dev);
910 void pci_clear_mwi(struct pci_dev *dev);
911 void pci_intx(struct pci_dev *dev, int enable);
912 bool pci_intx_mask_supported(struct pci_dev *dev);
913 bool pci_check_and_mask_intx(struct pci_dev *dev);
914 bool pci_check_and_unmask_intx(struct pci_dev *dev);
915 void pci_msi_off(struct pci_dev *dev);
916 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
917 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
918 int pcix_get_max_mmrbc(struct pci_dev *dev);
919 int pcix_get_mmrbc(struct pci_dev *dev);
920 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
921 int pcie_get_readrq(struct pci_dev *dev);
922 int pcie_set_readrq(struct pci_dev *dev, int rq);
923 int pcie_get_mps(struct pci_dev *dev);
924 int pcie_set_mps(struct pci_dev *dev, int mps);
925 int __pci_reset_function(struct pci_dev *dev);
926 int __pci_reset_function_locked(struct pci_dev *dev);
927 int pci_reset_function(struct pci_dev *dev);
928 void pci_update_resource(struct pci_dev *dev, int resno);
929 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
930 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
931 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
932 
933 /* ROM control related routines */
934 int pci_enable_rom(struct pci_dev *pdev);
935 void pci_disable_rom(struct pci_dev *pdev);
936 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
937 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
938 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
939 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
940 
941 /* Power management related routines */
942 int pci_save_state(struct pci_dev *dev);
943 void pci_restore_state(struct pci_dev *dev);
944 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
945 int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state);
946 int pci_load_and_free_saved_state(struct pci_dev *dev,
947                                   struct pci_saved_state **state);
948 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
949 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
950 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
951 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
952 void pci_pme_active(struct pci_dev *dev, bool enable);
953 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
954                       bool runtime, bool enable);
955 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
956 pci_power_t pci_target_state(struct pci_dev *dev);
957 int pci_prepare_to_sleep(struct pci_dev *dev);
958 int pci_back_from_sleep(struct pci_dev *dev);
959 bool pci_dev_run_wake(struct pci_dev *dev);
960 bool pci_check_pme_status(struct pci_dev *dev);
961 void pci_pme_wakeup_bus(struct pci_bus *bus);
962 
963 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
964                                   bool enable)
965 {
966         return __pci_enable_wake(dev, state, false, enable);
967 }
968 
969 #define PCI_EXP_IDO_REQUEST     (1<<0)
970 #define PCI_EXP_IDO_COMPLETION  (1<<1)
971 void pci_enable_ido(struct pci_dev *dev, unsigned long type);
972 void pci_disable_ido(struct pci_dev *dev, unsigned long type);
973 
974 enum pci_obff_signal_type {
975         PCI_EXP_OBFF_SIGNAL_L0 = 0,
976         PCI_EXP_OBFF_SIGNAL_ALWAYS = 1,
977 };
978 int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type);
979 void pci_disable_obff(struct pci_dev *dev);
980 
981 int pci_enable_ltr(struct pci_dev *dev);
982 void pci_disable_ltr(struct pci_dev *dev);
983 int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns);
984 
985 /* For use by arch with custom probe code */
986 void set_pcie_port_type(struct pci_dev *pdev);
987 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
988 
989 /* Functions for PCI Hotplug drivers to use */
990 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
991 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
992 unsigned int pci_rescan_bus(struct pci_bus *bus);
993 
994 /* Vital product data routines */
995 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
996 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
997 int pci_vpd_truncate(struct pci_dev *dev, size_t size);
998 
999 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1000 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1001 void pci_bus_assign_resources(const struct pci_bus *bus);
1002 void pci_bus_size_bridges(struct pci_bus *bus);
1003 int pci_claim_resource(struct pci_dev *, int);
1004 void pci_assign_unassigned_resources(void);
1005 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1006 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1007 void pdev_enable_device(struct pci_dev *);
1008 int pci_enable_resources(struct pci_dev *, int mask);
1009 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
1010                     int (*)(const struct pci_dev *, u8, u8));
1011 #define HAVE_PCI_REQ_REGIONS    2
1012 int __must_check pci_request_regions(struct pci_dev *, const char *);
1013 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1014 void pci_release_regions(struct pci_dev *);
1015 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1016 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1017 void pci_release_region(struct pci_dev *, int);
1018 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1019 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1020 void pci_release_selected_regions(struct pci_dev *, int);
1021 
1022 /* drivers/pci/bus.c */
1023 void pci_add_resource(struct list_head *resources, struct resource *res);
1024 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1025                              resource_size_t offset);
1026 void pci_free_resource_list(struct list_head *resources);
1027 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags);
1028 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1029 void pci_bus_remove_resources(struct pci_bus *bus);
1030 
1031 #define pci_bus_for_each_resource(bus, res, i)                          \
1032         for (i = 0;                                                     \
1033             (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1034              i++)
1035 
1036 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1037                         struct resource *res, resource_size_t size,
1038                         resource_size_t align, resource_size_t min,
1039                         unsigned int type_mask,
1040                         resource_size_t (*alignf)(void *,
1041                                                   const struct resource *,
1042                                                   resource_size_t,
1043                                                   resource_size_t),
1044                         void *alignf_data);
1045 void pci_enable_bridges(struct pci_bus *bus);
1046 
1047 /* Proper probing supporting hot-pluggable devices */
1048 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1049                                        const char *mod_name);
1050 
1051 /*
1052  * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
1053  */
1054 #define pci_register_driver(driver)             \
1055         __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1056 
1057 void pci_unregister_driver(struct pci_driver *dev);
1058 
1059 /**
1060  * module_pci_driver() - Helper macro for registering a PCI driver
1061  * @__pci_driver: pci_driver struct
1062  *
1063  * Helper macro for PCI drivers which do not do anything special in module
1064  * init/exit. This eliminates a lot of boilerplate. Each module may only
1065  * use this macro once, and calling it replaces module_init() and module_exit()
1066  */
1067 #define module_pci_driver(__pci_driver) \
1068         module_driver(__pci_driver, pci_register_driver, \
1069                        pci_unregister_driver)
1070 
1071 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1072 int pci_add_dynid(struct pci_driver *drv,
1073                   unsigned int vendor, unsigned int device,
1074                   unsigned int subvendor, unsigned int subdevice,
1075                   unsigned int class, unsigned int class_mask,
1076                   unsigned long driver_data);
1077 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1078                                          struct pci_dev *dev);
1079 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1080                     int pass);
1081 
1082 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1083                   void *userdata);
1084 int pci_cfg_space_size_ext(struct pci_dev *dev);
1085 int pci_cfg_space_size(struct pci_dev *dev);
1086 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1087 void pci_setup_bridge(struct pci_bus *bus);
1088 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1089                                          unsigned long type);
1090 
1091 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1092 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1093 
1094 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1095                       unsigned int command_bits, u32 flags);
1096 /* kmem_cache style wrapper around pci_alloc_consistent() */
1097 
1098 #include <linux/pci-dma.h>
1099 #include <linux/dmapool.h>
1100 
1101 #define pci_pool dma_pool
1102 #define pci_pool_create(name, pdev, size, align, allocation) \
1103                 dma_pool_create(name, &pdev->dev, size, align, allocation)
1104 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1105 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1106 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1107 
1108 enum pci_dma_burst_strategy {
1109         PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
1110                                    strategy_parameter is N/A */
1111         PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
1112                                    byte boundaries */
1113         PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
1114                                    strategy_parameter byte boundaries */
1115 };
1116 
1117 struct msix_entry {
1118         u32     vector; /* kernel uses to write allocated vector */
1119         u16     entry;  /* driver uses to specify entry, OS writes */
1120 };
1121 
1122 
1123 #ifndef CONFIG_PCI_MSI
1124 static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
1125 {
1126         return -1;
1127 }
1128 
1129 static inline int
1130 pci_enable_msi_block_auto(struct pci_dev *dev, unsigned int *maxvec)
1131 {
1132         return -1;
1133 }
1134 
1135 static inline void pci_msi_shutdown(struct pci_dev *dev)
1136 { }
1137 static inline void pci_disable_msi(struct pci_dev *dev)
1138 { }
1139 
1140 static inline int pci_msix_table_size(struct pci_dev *dev)
1141 {
1142         return 0;
1143 }
1144 static inline int pci_enable_msix(struct pci_dev *dev,
1145                                   struct msix_entry *entries, int nvec)
1146 {
1147         return -1;
1148 }
1149 
1150 static inline void pci_msix_shutdown(struct pci_dev *dev)
1151 { }
1152 static inline void pci_disable_msix(struct pci_dev *dev)
1153 { }
1154 
1155 static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev)
1156 { }
1157 
1158 static inline void pci_restore_msi_state(struct pci_dev *dev)
1159 { }
1160 static inline int pci_msi_enabled(void)
1161 {
1162         return 0;
1163 }
1164 #else
1165 int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec);
1166 int pci_enable_msi_block_auto(struct pci_dev *dev, unsigned int *maxvec);
1167 void pci_msi_shutdown(struct pci_dev *dev);
1168 void pci_disable_msi(struct pci_dev *dev);
1169 int pci_msix_table_size(struct pci_dev *dev);
1170 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec);
1171 void pci_msix_shutdown(struct pci_dev *dev);
1172 void pci_disable_msix(struct pci_dev *dev);
1173 void msi_remove_pci_irq_vectors(struct pci_dev *dev);
1174 void pci_restore_msi_state(struct pci_dev *dev);
1175 int pci_msi_enabled(void);
1176 #endif
1177 
1178 #ifdef CONFIG_PCIEPORTBUS
1179 extern bool pcie_ports_disabled;
1180 extern bool pcie_ports_auto;
1181 #else
1182 #define pcie_ports_disabled     true
1183 #define pcie_ports_auto         false
1184 #endif
1185 
1186 #ifndef CONFIG_PCIEASPM
1187 static inline int pcie_aspm_enabled(void) { return 0; }
1188 static inline bool pcie_aspm_support_enabled(void) { return false; }
1189 #else
1190 int pcie_aspm_enabled(void);
1191 bool pcie_aspm_support_enabled(void);
1192 #endif
1193 
1194 #ifdef CONFIG_PCIEAER
1195 void pci_no_aer(void);
1196 bool pci_aer_available(void);
1197 #else
1198 static inline void pci_no_aer(void) { }
1199 static inline bool pci_aer_available(void) { return false; }
1200 #endif
1201 
1202 #ifndef CONFIG_PCIE_ECRC
1203 static inline void pcie_set_ecrc_checking(struct pci_dev *dev)
1204 {
1205         return;
1206 }
1207 static inline void pcie_ecrc_get_policy(char *str) {};
1208 #else
1209 void pcie_set_ecrc_checking(struct pci_dev *dev);
1210 void pcie_ecrc_get_policy(char *str);
1211 #endif
1212 
1213 #define pci_enable_msi(pdev)    pci_enable_msi_block(pdev, 1)
1214 
1215 #ifdef CONFIG_HT_IRQ
1216 /* The functions a driver should call */
1217 int  ht_create_irq(struct pci_dev *dev, int idx);
1218 void ht_destroy_irq(unsigned int irq);
1219 #endif /* CONFIG_HT_IRQ */
1220 
1221 void pci_cfg_access_lock(struct pci_dev *dev);
1222 bool pci_cfg_access_trylock(struct pci_dev *dev);
1223 void pci_cfg_access_unlock(struct pci_dev *dev);
1224 
1225 /*
1226  * PCI domain support.  Sometimes called PCI segment (eg by ACPI),
1227  * a PCI domain is defined to be a set of PCI busses which share
1228  * configuration space.
1229  */
1230 #ifdef CONFIG_PCI_DOMAINS
1231 extern int pci_domains_supported;
1232 #else
1233 enum { pci_domains_supported = 0 };
1234 static inline int pci_domain_nr(struct pci_bus *bus)
1235 {
1236         return 0;
1237 }
1238 
1239 static inline int pci_proc_domain(struct pci_bus *bus)
1240 {
1241         return 0;
1242 }
1243 #endif /* CONFIG_PCI_DOMAINS */
1244 
1245 /* some architectures require additional setup to direct VGA traffic */
1246 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1247                       unsigned int command_bits, u32 flags);
1248 void pci_register_set_vga_state(arch_set_vga_state_t func);
1249 
1250 #else /* CONFIG_PCI is not enabled */
1251 
1252 /*
1253  *  If the system does not have PCI, clearly these return errors.  Define
1254  *  these as simple inline functions to avoid hair in drivers.
1255  */
1256 
1257 #define _PCI_NOP(o, s, t) \
1258         static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1259                                                 int where, t val) \
1260                 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1261 
1262 #define _PCI_NOP_ALL(o, x)      _PCI_NOP(o, byte, u8 x) \
1263                                 _PCI_NOP(o, word, u16 x) \
1264                                 _PCI_NOP(o, dword, u32 x)
1265 _PCI_NOP_ALL(read, *)
1266 _PCI_NOP_ALL(write,)
1267 
1268 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1269                                              unsigned int device,
1270                                              struct pci_dev *from)
1271 {
1272         return NULL;
1273 }
1274 
1275 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1276                                              unsigned int device,
1277                                              unsigned int ss_vendor,
1278                                              unsigned int ss_device,
1279                                              struct pci_dev *from)
1280 {
1281         return NULL;
1282 }
1283 
1284 static inline struct pci_dev *pci_get_class(unsigned int class,
1285                                             struct pci_dev *from)
1286 {
1287         return NULL;
1288 }
1289 
1290 #define pci_dev_present(ids)    (0)
1291 #define no_pci_devices()        (1)
1292 #define pci_dev_put(dev)        do { } while (0)
1293 
1294 static inline void pci_set_master(struct pci_dev *dev)
1295 { }
1296 
1297 static inline int pci_enable_device(struct pci_dev *dev)
1298 {
1299         return -EIO;
1300 }
1301 
1302 static inline void pci_disable_device(struct pci_dev *dev)
1303 { }
1304 
1305 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1306 {
1307         return -EIO;
1308 }
1309 
1310 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1311 {
1312         return -EIO;
1313 }
1314 
1315 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
1316                                         unsigned int size)
1317 {
1318         return -EIO;
1319 }
1320 
1321 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
1322                                         unsigned long mask)
1323 {
1324         return -EIO;
1325 }
1326 
1327 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1328 {
1329         return -EBUSY;
1330 }
1331 
1332 static inline int __pci_register_driver(struct pci_driver *drv,
1333                                         struct module *owner)
1334 {
1335         return 0;
1336 }
1337 
1338 static inline int pci_register_driver(struct pci_driver *drv)
1339 {
1340         return 0;
1341 }
1342 
1343 static inline void pci_unregister_driver(struct pci_driver *drv)
1344 { }
1345 
1346 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1347 {
1348         return 0;
1349 }
1350 
1351 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1352                                            int cap)
1353 {
1354         return 0;
1355 }
1356 
1357 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1358 {
1359         return 0;
1360 }
1361 
1362 /* Power management related routines */
1363 static inline int pci_save_state(struct pci_dev *dev)
1364 {
1365         return 0;
1366 }
1367 
1368 static inline void pci_restore_state(struct pci_dev *dev)
1369 { }
1370 
1371 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1372 {
1373         return 0;
1374 }
1375 
1376 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1377 {
1378         return 0;
1379 }
1380 
1381 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1382                                            pm_message_t state)
1383 {
1384         return PCI_D0;
1385 }
1386 
1387 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1388                                   int enable)
1389 {
1390         return 0;
1391 }
1392 
1393 static inline void pci_enable_ido(struct pci_dev *dev, unsigned long type)
1394 {
1395 }
1396 
1397 static inline void pci_disable_ido(struct pci_dev *dev, unsigned long type)
1398 {
1399 }
1400 
1401 static inline int pci_enable_obff(struct pci_dev *dev, unsigned long type)
1402 {
1403         return 0;
1404 }
1405 
1406 static inline void pci_disable_obff(struct pci_dev *dev)
1407 {
1408 }
1409 
1410 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1411 {
1412         return -EIO;
1413 }
1414 
1415 static inline void pci_release_regions(struct pci_dev *dev)
1416 { }
1417 
1418 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1419 
1420 static inline void pci_block_cfg_access(struct pci_dev *dev)
1421 { }
1422 
1423 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1424 { return 0; }
1425 
1426 static inline void pci_unblock_cfg_access(struct pci_dev *dev)
1427 { }
1428 
1429 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1430 { return NULL; }
1431 
1432 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1433                                                 unsigned int devfn)
1434 { return NULL; }
1435 
1436 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1437                                                 unsigned int devfn)
1438 { return NULL; }
1439 
1440 static inline int pci_domain_nr(struct pci_bus *bus)
1441 { return 0; }
1442 
1443 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev)
1444 { return NULL; }
1445 
1446 #define dev_is_pci(d) (false)
1447 #define dev_is_pf(d) (false)
1448 #define dev_num_vf(d) (0)
1449 #endif /* CONFIG_PCI */
1450 
1451 /* Include architecture-dependent settings and functions */
1452 
1453 #include <asm/pci.h>
1454 
1455 #ifndef PCIBIOS_MAX_MEM_32
1456 #define PCIBIOS_MAX_MEM_32 (-1)
1457 #endif
1458 
1459 /* these helpers provide future and backwards compatibility
1460  * for accessing popular PCI BAR info */
1461 #define pci_resource_start(dev, bar)    ((dev)->resource[(bar)].start)
1462 #define pci_resource_end(dev, bar)      ((dev)->resource[(bar)].end)
1463 #define pci_resource_flags(dev, bar)    ((dev)->resource[(bar)].flags)
1464 #define pci_resource_len(dev,bar) \
1465         ((pci_resource_start((dev), (bar)) == 0 &&      \
1466           pci_resource_end((dev), (bar)) ==             \
1467           pci_resource_start((dev), (bar))) ? 0 :       \
1468                                                         \
1469          (pci_resource_end((dev), (bar)) -              \
1470           pci_resource_start((dev), (bar)) + 1))
1471 
1472 /* Similar to the helpers above, these manipulate per-pci_dev
1473  * driver-specific data.  They are really just a wrapper around
1474  * the generic device structure functions of these calls.
1475  */
1476 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1477 {
1478         return dev_get_drvdata(&pdev->dev);
1479 }
1480 
1481 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1482 {
1483         dev_set_drvdata(&pdev->dev, data);
1484 }
1485 
1486 /* If you want to know what to call your pci_dev, ask this function.
1487  * Again, it's a wrapper around the generic device.
1488  */
1489 static inline const char *pci_name(const struct pci_dev *pdev)
1490 {
1491         return dev_name(&pdev->dev);
1492 }
1493 
1494 
1495 /* Some archs don't want to expose struct resource to userland as-is
1496  * in sysfs and /proc
1497  */
1498 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1499 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1500                 const struct resource *rsrc, resource_size_t *start,
1501                 resource_size_t *end)
1502 {
1503         *start = rsrc->start;
1504         *end = rsrc->end;
1505 }
1506 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1507 
1508 
1509 /*
1510  *  The world is not perfect and supplies us with broken PCI devices.
1511  *  For at least a part of these bugs we need a work-around, so both
1512  *  generic (drivers/pci/quirks.c) and per-architecture code can define
1513  *  fixup hooks to be called for particular buggy devices.
1514  */
1515 
1516 struct pci_fixup {
1517         u16 vendor;             /* You can use PCI_ANY_ID here of course */
1518         u16 device;             /* You can use PCI_ANY_ID here of course */
1519         u32 class;              /* You can use PCI_ANY_ID here too */
1520         unsigned int class_shift;       /* should be 0, 8, 16 */
1521         void (*hook)(struct pci_dev *dev);
1522 };
1523 
1524 enum pci_fixup_pass {
1525         pci_fixup_early,        /* Before probing BARs */
1526         pci_fixup_header,       /* After reading configuration header */
1527         pci_fixup_final,        /* Final phase of device fixups */
1528         pci_fixup_enable,       /* pci_enable_device() time */
1529         pci_fixup_resume,       /* pci_device_resume() */
1530         pci_fixup_suspend,      /* pci_device_suspend */
1531         pci_fixup_resume_early, /* pci_device_resume_early() */
1532 };
1533 
1534 /* Anonymous variables would be nice... */
1535 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1536                                   class_shift, hook)                    \
1537         static const struct pci_fixup __pci_fixup_##name __used         \
1538         __attribute__((__section__(#section), aligned((sizeof(void *)))))    \
1539                 = { vendor, device, class, class_shift, hook };
1540 
1541 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class,            \
1542                                          class_shift, hook)             \
1543         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early,                     \
1544                 vendor##device##hook, vendor, device, class, class_shift, hook)
1545 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class,           \
1546                                          class_shift, hook)             \
1547         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header,                    \
1548                 vendor##device##hook, vendor, device, class, class_shift, hook)
1549 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class,            \
1550                                          class_shift, hook)             \
1551         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final,                     \
1552                 vendor##device##hook, vendor, device, class, class_shift, hook)
1553 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class,           \
1554                                          class_shift, hook)             \
1555         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable,                    \
1556                 vendor##device##hook, vendor, device, class, class_shift, hook)
1557 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class,           \
1558                                          class_shift, hook)             \
1559         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume,                    \
1560                 resume##vendor##device##hook, vendor, device, class,    \
1561                 class_shift, hook)
1562 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class,     \
1563                                          class_shift, hook)             \
1564         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early,              \
1565                 resume_early##vendor##device##hook, vendor, device,     \
1566                 class, class_shift, hook)
1567 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class,          \
1568                                          class_shift, hook)             \
1569         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend,                   \
1570                 suspend##vendor##device##hook, vendor, device, class,   \
1571                 class_shift, hook)
1572 
1573 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook)                   \
1574         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early,                     \
1575                 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1576 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook)                  \
1577         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header,                    \
1578                 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1579 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook)                   \
1580         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final,                     \
1581                 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1582 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook)                  \
1583         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable,                    \
1584                 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1585 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook)                  \
1586         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume,                    \
1587                 resume##vendor##device##hook, vendor, device,           \
1588                 PCI_ANY_ID, 0, hook)
1589 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook)            \
1590         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early,              \
1591                 resume_early##vendor##device##hook, vendor, device,     \
1592                 PCI_ANY_ID, 0, hook)
1593 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook)                 \
1594         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend,                   \
1595                 suspend##vendor##device##hook, vendor, device,          \
1596                 PCI_ANY_ID, 0, hook)
1597 
1598 #ifdef CONFIG_PCI_QUIRKS
1599 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1600 struct pci_dev *pci_get_dma_source(struct pci_dev *dev);
1601 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
1602 #else
1603 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1604                                     struct pci_dev *dev) {}
1605 static inline struct pci_dev *pci_get_dma_source(struct pci_dev *dev)
1606 {
1607         return pci_dev_get(dev);
1608 }
1609 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1610                                                u16 acs_flags)
1611 {
1612         return -ENOTTY;
1613 }
1614 #endif
1615 
1616 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1617 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1618 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1619 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1620 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1621                                    const char *name);
1622 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1623 
1624 extern int pci_pci_problems;
1625 #define PCIPCI_FAIL             1       /* No PCI PCI DMA */
1626 #define PCIPCI_TRITON           2
1627 #define PCIPCI_NATOMA           4
1628 #define PCIPCI_VIAETBF          8
1629 #define PCIPCI_VSFX             16
1630 #define PCIPCI_ALIMAGIK         32      /* Need low latency setting */
1631 #define PCIAGP_FAIL             64      /* No PCI to AGP DMA */
1632 
1633 extern unsigned long pci_cardbus_io_size;
1634 extern unsigned long pci_cardbus_mem_size;
1635 extern u8 pci_dfl_cache_line_size;
1636 extern u8 pci_cache_line_size;
1637 
1638 extern unsigned long pci_hotplug_io_size;
1639 extern unsigned long pci_hotplug_mem_size;
1640 
1641 /* Architecture specific versions may override these (weak) */
1642 int pcibios_add_platform_entries(struct pci_dev *dev);
1643 void pcibios_disable_device(struct pci_dev *dev);
1644 void pcibios_set_master(struct pci_dev *dev);
1645 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1646                                  enum pcie_reset_state state);
1647 int pcibios_add_device(struct pci_dev *dev);
1648 
1649 #ifdef CONFIG_PCI_MMCONFIG
1650 void __init pci_mmcfg_early_init(void);
1651 void __init pci_mmcfg_late_init(void);
1652 #else
1653 static inline void pci_mmcfg_early_init(void) { }
1654 static inline void pci_mmcfg_late_init(void) { }
1655 #endif
1656 
1657 int pci_ext_cfg_avail(void);
1658 
1659 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1660 
1661 #ifdef CONFIG_PCI_IOV
1662 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1663 void pci_disable_sriov(struct pci_dev *dev);
1664 irqreturn_t pci_sriov_migration(struct pci_dev *dev);
1665 int pci_num_vf(struct pci_dev *dev);
1666 int pci_vfs_assigned(struct pci_dev *dev);
1667 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1668 int pci_sriov_get_totalvfs(struct pci_dev *dev);
1669 #else
1670 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1671 {
1672         return -ENODEV;
1673 }
1674 static inline void pci_disable_sriov(struct pci_dev *dev)
1675 {
1676 }
1677 static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev)
1678 {
1679         return IRQ_NONE;
1680 }
1681 static inline int pci_num_vf(struct pci_dev *dev)
1682 {
1683         return 0;
1684 }
1685 static inline int pci_vfs_assigned(struct pci_dev *dev)
1686 {
1687         return 0;
1688 }
1689 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
1690 {
1691         return 0;
1692 }
1693 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
1694 {
1695         return 0;
1696 }
1697 #endif
1698 
1699 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1700 void pci_hp_create_module_link(struct pci_slot *pci_slot);
1701 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1702 #endif
1703 
1704 /**
1705  * pci_pcie_cap - get the saved PCIe capability offset
1706  * @dev: PCI device
1707  *
1708  * PCIe capability offset is calculated at PCI device initialization
1709  * time and saved in the data structure. This function returns saved
1710  * PCIe capability offset. Using this instead of pci_find_capability()
1711  * reduces unnecessary search in the PCI configuration space. If you
1712  * need to calculate PCIe capability offset from raw device for some
1713  * reasons, please use pci_find_capability() instead.
1714  */
1715 static inline int pci_pcie_cap(struct pci_dev *dev)
1716 {
1717         return dev->pcie_cap;
1718 }
1719 
1720 /**
1721  * pci_is_pcie - check if the PCI device is PCI Express capable
1722  * @dev: PCI device
1723  *
1724  * Retrun true if the PCI device is PCI Express capable, false otherwise.
1725  */
1726 static inline bool pci_is_pcie(struct pci_dev *dev)
1727 {
1728         return !!pci_pcie_cap(dev);
1729 }
1730 
1731 /**
1732  * pcie_caps_reg - get the PCIe Capabilities Register
1733  * @dev: PCI device
1734  */
1735 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
1736 {
1737         return dev->pcie_flags_reg;
1738 }
1739 
1740 /**
1741  * pci_pcie_type - get the PCIe device/port type
1742  * @dev: PCI device
1743  */
1744 static inline int pci_pcie_type(const struct pci_dev *dev)
1745 {
1746         return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
1747 }
1748 
1749 void pci_request_acs(void);
1750 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
1751 bool pci_acs_path_enabled(struct pci_dev *start,
1752                           struct pci_dev *end, u16 acs_flags);
1753 
1754 #define PCI_VPD_LRDT                    0x80    /* Large Resource Data Type */
1755 #define PCI_VPD_LRDT_ID(x)              (x | PCI_VPD_LRDT)
1756 
1757 /* Large Resource Data Type Tag Item Names */
1758 #define PCI_VPD_LTIN_ID_STRING          0x02    /* Identifier String */
1759 #define PCI_VPD_LTIN_RO_DATA            0x10    /* Read-Only Data */
1760 #define PCI_VPD_LTIN_RW_DATA            0x11    /* Read-Write Data */
1761 
1762 #define PCI_VPD_LRDT_ID_STRING          PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1763 #define PCI_VPD_LRDT_RO_DATA            PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1764 #define PCI_VPD_LRDT_RW_DATA            PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1765 
1766 /* Small Resource Data Type Tag Item Names */
1767 #define PCI_VPD_STIN_END                0x78    /* End */
1768 
1769 #define PCI_VPD_SRDT_END                PCI_VPD_STIN_END
1770 
1771 #define PCI_VPD_SRDT_TIN_MASK           0x78
1772 #define PCI_VPD_SRDT_LEN_MASK           0x07
1773 
1774 #define PCI_VPD_LRDT_TAG_SIZE           3
1775 #define PCI_VPD_SRDT_TAG_SIZE           1
1776 
1777 #define PCI_VPD_INFO_FLD_HDR_SIZE       3
1778 
1779 #define PCI_VPD_RO_KEYWORD_PARTNO       "PN"
1780 #define PCI_VPD_RO_KEYWORD_MFR_ID       "MN"
1781 #define PCI_VPD_RO_KEYWORD_VENDOR0      "V0"
1782 #define PCI_VPD_RO_KEYWORD_CHKSUM       "RV"
1783 
1784 /**
1785  * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1786  * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1787  *
1788  * Returns the extracted Large Resource Data Type length.
1789  */
1790 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1791 {
1792         return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1793 }
1794 
1795 /**
1796  * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
1797  * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1798  *
1799  * Returns the extracted Small Resource Data Type length.
1800  */
1801 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
1802 {
1803         return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
1804 }
1805 
1806 /**
1807  * pci_vpd_info_field_size - Extracts the information field length
1808  * @lrdt: Pointer to the beginning of an information field header
1809  *
1810  * Returns the extracted information field length.
1811  */
1812 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
1813 {
1814         return info_field[2];
1815 }
1816 
1817 /**
1818  * pci_vpd_find_tag - Locates the Resource Data Type tag provided
1819  * @buf: Pointer to buffered vpd data
1820  * @off: The offset into the buffer at which to begin the search
1821  * @len: The length of the vpd buffer
1822  * @rdt: The Resource Data Type to search for
1823  *
1824  * Returns the index where the Resource Data Type was found or
1825  * -ENOENT otherwise.
1826  */
1827 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
1828 
1829 /**
1830  * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
1831  * @buf: Pointer to buffered vpd data
1832  * @off: The offset into the buffer at which to begin the search
1833  * @len: The length of the buffer area, relative to off, in which to search
1834  * @kw: The keyword to search for
1835  *
1836  * Returns the index where the information field keyword was found or
1837  * -ENOENT otherwise.
1838  */
1839 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
1840                               unsigned int len, const char *kw);
1841 
1842 /* PCI <-> OF binding helpers */
1843 #ifdef CONFIG_OF
1844 struct device_node;
1845 void pci_set_of_node(struct pci_dev *dev);
1846 void pci_release_of_node(struct pci_dev *dev);
1847 void pci_set_bus_of_node(struct pci_bus *bus);
1848 void pci_release_bus_of_node(struct pci_bus *bus);
1849 
1850 /* Arch may override this (weak) */
1851 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
1852 
1853 static inline struct device_node *
1854 pci_device_to_OF_node(const struct pci_dev *pdev)
1855 {
1856         return pdev ? pdev->dev.of_node : NULL;
1857 }
1858 
1859 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
1860 {
1861         return bus ? bus->dev.of_node : NULL;
1862 }
1863 
1864 #else /* CONFIG_OF */
1865 static inline void pci_set_of_node(struct pci_dev *dev) { }
1866 static inline void pci_release_of_node(struct pci_dev *dev) { }
1867 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
1868 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
1869 #endif  /* CONFIG_OF */
1870 
1871 #ifdef CONFIG_EEH
1872 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
1873 {
1874         return pdev->dev.archdata.edev;
1875 }
1876 #endif
1877 
1878 /**
1879  * pci_find_upstream_pcie_bridge - find upstream PCIe-to-PCI bridge of a device
1880  * @pdev: the PCI device
1881  *
1882  * if the device is PCIE, return NULL
1883  * if the device isn't connected to a PCIe bridge (that is its parent is a
1884  * legacy PCI bridge and the bridge is directly connected to bus 0), return its
1885  * parent
1886  */
1887 struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev);
1888 
1889 #endif /* LINUX_PCI_H */
1890 

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