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TOMOYO Linux Cross Reference
Linux/include/linux/pci.h

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  1 /* SPDX-License-Identifier: GPL-2.0 */
  2 /*
  3  *      pci.h
  4  *
  5  *      PCI defines and function prototypes
  6  *      Copyright 1994, Drew Eckhardt
  7  *      Copyright 1997--1999 Martin Mares <mj@ucw.cz>
  8  *
  9  *      For more information, please consult the following manuals (look at
 10  *      http://www.pcisig.com/ for how to get them):
 11  *
 12  *      PCI BIOS Specification
 13  *      PCI Local Bus Specification
 14  *      PCI to PCI Bridge Specification
 15  *      PCI System Design Guide
 16  */
 17 #ifndef LINUX_PCI_H
 18 #define LINUX_PCI_H
 19 
 20 
 21 #include <linux/mod_devicetable.h>
 22 
 23 #include <linux/types.h>
 24 #include <linux/init.h>
 25 #include <linux/ioport.h>
 26 #include <linux/list.h>
 27 #include <linux/compiler.h>
 28 #include <linux/errno.h>
 29 #include <linux/kobject.h>
 30 #include <linux/atomic.h>
 31 #include <linux/device.h>
 32 #include <linux/interrupt.h>
 33 #include <linux/io.h>
 34 #include <linux/resource_ext.h>
 35 #include <uapi/linux/pci.h>
 36 
 37 #include <linux/pci_ids.h>
 38 
 39 /*
 40  * The PCI interface treats multi-function devices as independent
 41  * devices.  The slot/function address of each device is encoded
 42  * in a single byte as follows:
 43  *
 44  *      7:3 = slot
 45  *      2:0 = function
 46  *
 47  * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
 48  * In the interest of not exposing interfaces to user-space unnecessarily,
 49  * the following kernel-only defines are being added here.
 50  */
 51 #define PCI_DEVID(bus, devfn)   ((((u16)(bus)) << 8) | (devfn))
 52 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
 53 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
 54 
 55 /* pci_slot represents a physical slot */
 56 struct pci_slot {
 57         struct pci_bus          *bus;           /* Bus this slot is on */
 58         struct list_head        list;           /* Node in list of slots */
 59         struct hotplug_slot     *hotplug;       /* Hotplug info (move here) */
 60         unsigned char           number;         /* PCI_SLOT(pci_dev->devfn) */
 61         struct kobject          kobj;
 62 };
 63 
 64 static inline const char *pci_slot_name(const struct pci_slot *slot)
 65 {
 66         return kobject_name(&slot->kobj);
 67 }
 68 
 69 /* File state for mmap()s on /proc/bus/pci/X/Y */
 70 enum pci_mmap_state {
 71         pci_mmap_io,
 72         pci_mmap_mem
 73 };
 74 
 75 /* For PCI devices, the region numbers are assigned this way: */
 76 enum {
 77         /* #0-5: standard PCI resources */
 78         PCI_STD_RESOURCES,
 79         PCI_STD_RESOURCE_END = 5,
 80 
 81         /* #6: expansion ROM resource */
 82         PCI_ROM_RESOURCE,
 83 
 84         /* Device-specific resources */
 85 #ifdef CONFIG_PCI_IOV
 86         PCI_IOV_RESOURCES,
 87         PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
 88 #endif
 89 
 90         /* Resources assigned to buses behind the bridge */
 91 #define PCI_BRIDGE_RESOURCE_NUM 4
 92 
 93         PCI_BRIDGE_RESOURCES,
 94         PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
 95                                   PCI_BRIDGE_RESOURCE_NUM - 1,
 96 
 97         /* Total resources associated with a PCI device */
 98         PCI_NUM_RESOURCES,
 99 
100         /* Preserve this for compatibility */
101         DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
102 };
103 
104 /**
105  * enum pci_interrupt_pin - PCI INTx interrupt values
106  * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
107  * @PCI_INTERRUPT_INTA: PCI INTA pin
108  * @PCI_INTERRUPT_INTB: PCI INTB pin
109  * @PCI_INTERRUPT_INTC: PCI INTC pin
110  * @PCI_INTERRUPT_INTD: PCI INTD pin
111  *
112  * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
113  * PCI_INTERRUPT_PIN register.
114  */
115 enum pci_interrupt_pin {
116         PCI_INTERRUPT_UNKNOWN,
117         PCI_INTERRUPT_INTA,
118         PCI_INTERRUPT_INTB,
119         PCI_INTERRUPT_INTC,
120         PCI_INTERRUPT_INTD,
121 };
122 
123 /* The number of legacy PCI INTx interrupts */
124 #define PCI_NUM_INTX    4
125 
126 /*
127  * pci_power_t values must match the bits in the Capabilities PME_Support
128  * and Control/Status PowerState fields in the Power Management capability.
129  */
130 typedef int __bitwise pci_power_t;
131 
132 #define PCI_D0          ((pci_power_t __force) 0)
133 #define PCI_D1          ((pci_power_t __force) 1)
134 #define PCI_D2          ((pci_power_t __force) 2)
135 #define PCI_D3hot       ((pci_power_t __force) 3)
136 #define PCI_D3cold      ((pci_power_t __force) 4)
137 #define PCI_UNKNOWN     ((pci_power_t __force) 5)
138 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
139 
140 /* Remember to update this when the list above changes! */
141 extern const char *pci_power_names[];
142 
143 static inline const char *pci_power_name(pci_power_t state)
144 {
145         return pci_power_names[1 + (__force int) state];
146 }
147 
148 #define PCI_PM_D2_DELAY         200
149 #define PCI_PM_D3_WAIT          10
150 #define PCI_PM_D3COLD_WAIT      100
151 #define PCI_PM_BUS_WAIT         50
152 
153 /**
154  * The pci_channel state describes connectivity between the CPU and
155  * the PCI device.  If some PCI bus between here and the PCI device
156  * has crashed or locked up, this info is reflected here.
157  */
158 typedef unsigned int __bitwise pci_channel_state_t;
159 
160 enum pci_channel_state {
161         /* I/O channel is in normal state */
162         pci_channel_io_normal = (__force pci_channel_state_t) 1,
163 
164         /* I/O to channel is blocked */
165         pci_channel_io_frozen = (__force pci_channel_state_t) 2,
166 
167         /* PCI card is dead */
168         pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
169 };
170 
171 typedef unsigned int __bitwise pcie_reset_state_t;
172 
173 enum pcie_reset_state {
174         /* Reset is NOT asserted (Use to deassert reset) */
175         pcie_deassert_reset = (__force pcie_reset_state_t) 1,
176 
177         /* Use #PERST to reset PCIe device */
178         pcie_warm_reset = (__force pcie_reset_state_t) 2,
179 
180         /* Use PCIe Hot Reset to reset device */
181         pcie_hot_reset = (__force pcie_reset_state_t) 3
182 };
183 
184 typedef unsigned short __bitwise pci_dev_flags_t;
185 enum pci_dev_flags {
186         /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
187         PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
188         /* Device configuration is irrevocably lost if disabled into D3 */
189         PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
190         /* Provide indication device is assigned by a Virtual Machine Manager */
191         PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
192         /* Flag for quirk use to store if quirk-specific ACS is enabled */
193         PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
194         /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
195         PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
196         /* Do not use bus resets for device */
197         PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
198         /* Do not use PM reset even if device advertises NoSoftRst- */
199         PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
200         /* Get VPD from function 0 VPD */
201         PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
202         /* A non-root bridge where translation occurs, stop alias search here */
203         PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
204         /* Do not use FLR even if device advertises PCI_AF_CAP */
205         PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
206         /* Don't use Relaxed Ordering for TLPs directed at this device */
207         PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
208 };
209 
210 enum pci_irq_reroute_variant {
211         INTEL_IRQ_REROUTE_VARIANT = 1,
212         MAX_IRQ_REROUTE_VARIANTS = 3
213 };
214 
215 typedef unsigned short __bitwise pci_bus_flags_t;
216 enum pci_bus_flags {
217         PCI_BUS_FLAGS_NO_MSI    = (__force pci_bus_flags_t) 1,
218         PCI_BUS_FLAGS_NO_MMRBC  = (__force pci_bus_flags_t) 2,
219         PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
220 };
221 
222 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
223 enum pcie_link_width {
224         PCIE_LNK_WIDTH_RESRV    = 0x00,
225         PCIE_LNK_X1             = 0x01,
226         PCIE_LNK_X2             = 0x02,
227         PCIE_LNK_X4             = 0x04,
228         PCIE_LNK_X8             = 0x08,
229         PCIE_LNK_X12            = 0x0c,
230         PCIE_LNK_X16            = 0x10,
231         PCIE_LNK_X32            = 0x20,
232         PCIE_LNK_WIDTH_UNKNOWN  = 0xff,
233 };
234 
235 /* Based on the PCI Hotplug Spec, but some values are made up by us */
236 enum pci_bus_speed {
237         PCI_SPEED_33MHz                 = 0x00,
238         PCI_SPEED_66MHz                 = 0x01,
239         PCI_SPEED_66MHz_PCIX            = 0x02,
240         PCI_SPEED_100MHz_PCIX           = 0x03,
241         PCI_SPEED_133MHz_PCIX           = 0x04,
242         PCI_SPEED_66MHz_PCIX_ECC        = 0x05,
243         PCI_SPEED_100MHz_PCIX_ECC       = 0x06,
244         PCI_SPEED_133MHz_PCIX_ECC       = 0x07,
245         PCI_SPEED_66MHz_PCIX_266        = 0x09,
246         PCI_SPEED_100MHz_PCIX_266       = 0x0a,
247         PCI_SPEED_133MHz_PCIX_266       = 0x0b,
248         AGP_UNKNOWN                     = 0x0c,
249         AGP_1X                          = 0x0d,
250         AGP_2X                          = 0x0e,
251         AGP_4X                          = 0x0f,
252         AGP_8X                          = 0x10,
253         PCI_SPEED_66MHz_PCIX_533        = 0x11,
254         PCI_SPEED_100MHz_PCIX_533       = 0x12,
255         PCI_SPEED_133MHz_PCIX_533       = 0x13,
256         PCIE_SPEED_2_5GT                = 0x14,
257         PCIE_SPEED_5_0GT                = 0x15,
258         PCIE_SPEED_8_0GT                = 0x16,
259         PCIE_SPEED_16_0GT               = 0x17,
260         PCI_SPEED_UNKNOWN               = 0xff,
261 };
262 
263 struct pci_cap_saved_data {
264         u16             cap_nr;
265         bool            cap_extended;
266         unsigned int    size;
267         u32             data[0];
268 };
269 
270 struct pci_cap_saved_state {
271         struct hlist_node               next;
272         struct pci_cap_saved_data       cap;
273 };
274 
275 struct irq_affinity;
276 struct pcie_link_state;
277 struct pci_vpd;
278 struct pci_sriov;
279 struct pci_ats;
280 
281 /* The pci_dev structure describes PCI devices */
282 struct pci_dev {
283         struct list_head bus_list;      /* Node in per-bus list */
284         struct pci_bus  *bus;           /* Bus this device is on */
285         struct pci_bus  *subordinate;   /* Bus this device bridges to */
286 
287         void            *sysdata;       /* Hook for sys-specific extension */
288         struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
289         struct pci_slot *slot;          /* Physical slot this device is in */
290 
291         unsigned int    devfn;          /* Encoded device & function index */
292         unsigned short  vendor;
293         unsigned short  device;
294         unsigned short  subsystem_vendor;
295         unsigned short  subsystem_device;
296         unsigned int    class;          /* 3 bytes: (base,sub,prog-if) */
297         u8              revision;       /* PCI revision, low byte of class word */
298         u8              hdr_type;       /* PCI header type (`multi' flag masked out) */
299 #ifdef CONFIG_PCIEAER
300         u16             aer_cap;        /* AER capability offset */
301 #endif
302         u8              pcie_cap;       /* PCIe capability offset */
303         u8              msi_cap;        /* MSI capability offset */
304         u8              msix_cap;       /* MSI-X capability offset */
305         u8              pcie_mpss:3;    /* PCIe Max Payload Size Supported */
306         u8              rom_base_reg;   /* Config register controlling ROM */
307         u8              pin;            /* Interrupt pin this device uses */
308         u16             pcie_flags_reg; /* Cached PCIe Capabilities Register */
309         unsigned long   *dma_alias_mask;/* Mask of enabled devfn aliases */
310 
311         struct pci_driver *driver;      /* Driver bound to this device */
312         u64             dma_mask;       /* Mask of the bits of bus address this
313                                            device implements.  Normally this is
314                                            0xffffffff.  You only need to change
315                                            this if your device has broken DMA
316                                            or supports 64-bit transfers.  */
317 
318         struct device_dma_parameters dma_parms;
319 
320         pci_power_t     current_state;  /* Current operating state. In ACPI,
321                                            this is D0-D3, D0 being fully
322                                            functional, and D3 being off. */
323         u8              pm_cap;         /* PM capability offset */
324         unsigned int    pme_support:5;  /* Bitmask of states from which PME#
325                                            can be generated */
326         unsigned int    pme_poll:1;     /* Poll device's PME status bit */
327         unsigned int    d1_support:1;   /* Low power state D1 is supported */
328         unsigned int    d2_support:1;   /* Low power state D2 is supported */
329         unsigned int    no_d1d2:1;      /* D1 and D2 are forbidden */
330         unsigned int    no_d3cold:1;    /* D3cold is forbidden */
331         unsigned int    bridge_d3:1;    /* Allow D3 for bridge */
332         unsigned int    d3cold_allowed:1;       /* D3cold is allowed by user */
333         unsigned int    mmio_always_on:1;       /* Disallow turning off io/mem
334                                                    decoding during BAR sizing */
335         unsigned int    wakeup_prepared:1;
336         unsigned int    runtime_d3cold:1;       /* Whether go through runtime
337                                                    D3cold, not set for devices
338                                                    powered on/off by the
339                                                    corresponding bridge */
340         unsigned int    ignore_hotplug:1;       /* Ignore hotplug events */
341         unsigned int    hotplug_user_indicators:1; /* SlotCtl indicators
342                                                       controlled exclusively by
343                                                       user sysfs */
344         unsigned int    d3_delay;       /* D3->D0 transition time in ms */
345         unsigned int    d3cold_delay;   /* D3cold->D0 transition time in ms */
346 
347 #ifdef CONFIG_PCIEASPM
348         struct pcie_link_state  *link_state;    /* ASPM link state */
349         unsigned int    ltr_path:1;     /* Latency Tolerance Reporting
350                                            supported from root to here */
351 #endif
352 
353         pci_channel_state_t error_state;        /* Current connectivity state */
354         struct device   dev;                    /* Generic device interface */
355 
356         int             cfg_size;               /* Size of config space */
357 
358         /*
359          * Instead of touching interrupt line and base address registers
360          * directly, use the values stored here. They might be different!
361          */
362         unsigned int    irq;
363         struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
364 
365         bool            match_driver;           /* Skip attaching driver */
366 
367         unsigned int    transparent:1;          /* Subtractive decode bridge */
368         unsigned int    multifunction:1;        /* Multi-function device */
369 
370         unsigned int    is_added:1;
371         unsigned int    is_busmaster:1;         /* Is busmaster */
372         unsigned int    no_msi:1;               /* May not use MSI */
373         unsigned int    no_64bit_msi:1;         /* May only use 32-bit MSIs */
374         unsigned int    block_cfg_access:1;     /* Config space access blocked */
375         unsigned int    broken_parity_status:1; /* Generates false positive parity */
376         unsigned int    irq_reroute_variant:2;  /* Needs IRQ rerouting variant */
377         unsigned int    msi_enabled:1;
378         unsigned int    msix_enabled:1;
379         unsigned int    ari_enabled:1;          /* ARI forwarding */
380         unsigned int    ats_enabled:1;          /* Address Translation Svc */
381         unsigned int    pasid_enabled:1;        /* Process Address Space ID */
382         unsigned int    pri_enabled:1;          /* Page Request Interface */
383         unsigned int    is_managed:1;
384         unsigned int    needs_freset:1;         /* Requires fundamental reset */
385         unsigned int    state_saved:1;
386         unsigned int    is_physfn:1;
387         unsigned int    is_virtfn:1;
388         unsigned int    reset_fn:1;
389         unsigned int    is_hotplug_bridge:1;
390         unsigned int    is_thunderbolt:1;       /* Thunderbolt controller */
391         unsigned int    __aer_firmware_first_valid:1;
392         unsigned int    __aer_firmware_first:1;
393         unsigned int    broken_intx_masking:1;  /* INTx masking can't be used */
394         unsigned int    io_window_1k:1;         /* Intel bridge 1K I/O windows */
395         unsigned int    irq_managed:1;
396         unsigned int    has_secondary_link:1;
397         unsigned int    non_compliant_bars:1;   /* Broken BARs; ignore them */
398         unsigned int    is_probed:1;            /* Device probing in progress */
399         pci_dev_flags_t dev_flags;
400         atomic_t        enable_cnt;     /* pci_enable_device has been called */
401 
402         u32             saved_config_space[16]; /* Config space saved at suspend time */
403         struct hlist_head saved_cap_space;
404         struct bin_attribute *rom_attr;         /* Attribute descriptor for sysfs ROM entry */
405         int             rom_attr_enabled;       /* Display of ROM attribute enabled? */
406         struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
407         struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
408 
409 #ifdef CONFIG_PCIE_PTM
410         unsigned int    ptm_root:1;
411         unsigned int    ptm_enabled:1;
412         u8              ptm_granularity;
413 #endif
414 #ifdef CONFIG_PCI_MSI
415         const struct attribute_group **msi_irq_groups;
416 #endif
417         struct pci_vpd *vpd;
418 #ifdef CONFIG_PCI_ATS
419         union {
420                 struct pci_sriov        *sriov;         /* PF: SR-IOV info */
421                 struct pci_dev          *physfn;        /* VF: related PF */
422         };
423         u16             ats_cap;        /* ATS Capability offset */
424         u8              ats_stu;        /* ATS Smallest Translation Unit */
425         atomic_t        ats_ref_cnt;    /* Number of VFs with ATS enabled */
426 #endif
427 #ifdef CONFIG_PCI_PRI
428         u32             pri_reqs_alloc; /* Number of PRI requests allocated */
429 #endif
430 #ifdef CONFIG_PCI_PASID
431         u16             pasid_features;
432 #endif
433         phys_addr_t     rom;            /* Physical address if not from BAR */
434         size_t          romlen;         /* Length if not from BAR */
435         char            *driver_override; /* Driver name to force a match */
436 
437         unsigned long   priv_flags;     /* Private flags for the PCI driver */
438 };
439 
440 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
441 {
442 #ifdef CONFIG_PCI_IOV
443         if (dev->is_virtfn)
444                 dev = dev->physfn;
445 #endif
446         return dev;
447 }
448 
449 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
450 
451 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
452 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
453 
454 static inline int pci_channel_offline(struct pci_dev *pdev)
455 {
456         return (pdev->error_state != pci_channel_io_normal);
457 }
458 
459 struct pci_host_bridge {
460         struct device   dev;
461         struct pci_bus  *bus;           /* Root bus */
462         struct pci_ops  *ops;
463         void            *sysdata;
464         int             busnr;
465         struct list_head windows;       /* resource_entry */
466         u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
467         int (*map_irq)(const struct pci_dev *, u8, u8);
468         void (*release_fn)(struct pci_host_bridge *);
469         void            *release_data;
470         struct msi_controller *msi;
471         unsigned int    ignore_reset_delay:1;   /* For entire hierarchy */
472         unsigned int    no_ext_tags:1;          /* No Extended Tags */
473         unsigned int    native_aer:1;           /* OS may use PCIe AER */
474         unsigned int    native_hotplug:1;       /* OS may use PCIe hotplug */
475         unsigned int    native_pme:1;           /* OS may use PCIe PME */
476         /* Resource alignment requirements */
477         resource_size_t (*align_resource)(struct pci_dev *dev,
478                         const struct resource *res,
479                         resource_size_t start,
480                         resource_size_t size,
481                         resource_size_t align);
482         unsigned long   private[0] ____cacheline_aligned;
483 };
484 
485 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
486 
487 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
488 {
489         return (void *)bridge->private;
490 }
491 
492 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
493 {
494         return container_of(priv, struct pci_host_bridge, private);
495 }
496 
497 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
498 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
499                                                    size_t priv);
500 void pci_free_host_bridge(struct pci_host_bridge *bridge);
501 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
502 
503 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
504                                  void (*release_fn)(struct pci_host_bridge *),
505                                  void *release_data);
506 
507 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
508 
509 /*
510  * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
511  * to P2P or CardBus bridge windows) go in a table.  Additional ones (for
512  * buses below host bridges or subtractive decode bridges) go in the list.
513  * Use pci_bus_for_each_resource() to iterate through all the resources.
514  */
515 
516 /*
517  * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
518  * and there's no way to program the bridge with the details of the window.
519  * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
520  * decode bit set, because they are explicit and can be programmed with _SRS.
521  */
522 #define PCI_SUBTRACTIVE_DECODE  0x1
523 
524 struct pci_bus_resource {
525         struct list_head        list;
526         struct resource         *res;
527         unsigned int            flags;
528 };
529 
530 #define PCI_REGION_FLAG_MASK    0x0fU   /* These bits of resource flags tell us the PCI region flags */
531 
532 struct pci_bus {
533         struct list_head node;          /* Node in list of buses */
534         struct pci_bus  *parent;        /* Parent bus this bridge is on */
535         struct list_head children;      /* List of child buses */
536         struct list_head devices;       /* List of devices on this bus */
537         struct pci_dev  *self;          /* Bridge device as seen by parent */
538         struct list_head slots;         /* List of slots on this bus;
539                                            protected by pci_slot_mutex */
540         struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
541         struct list_head resources;     /* Address space routed to this bus */
542         struct resource busn_res;       /* Bus numbers routed to this bus */
543 
544         struct pci_ops  *ops;           /* Configuration access functions */
545         struct msi_controller *msi;     /* MSI controller */
546         void            *sysdata;       /* Hook for sys-specific extension */
547         struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
548 
549         unsigned char   number;         /* Bus number */
550         unsigned char   primary;        /* Number of primary bridge */
551         unsigned char   max_bus_speed;  /* enum pci_bus_speed */
552         unsigned char   cur_bus_speed;  /* enum pci_bus_speed */
553 #ifdef CONFIG_PCI_DOMAINS_GENERIC
554         int             domain_nr;
555 #endif
556 
557         char            name[48];
558 
559         unsigned short  bridge_ctl;     /* Manage NO_ISA/FBB/et al behaviors */
560         pci_bus_flags_t bus_flags;      /* Inherited by child buses */
561         struct device           *bridge;
562         struct device           dev;
563         struct bin_attribute    *legacy_io;     /* Legacy I/O for this bus */
564         struct bin_attribute    *legacy_mem;    /* Legacy mem */
565         unsigned int            is_added:1;
566 };
567 
568 #define to_pci_bus(n)   container_of(n, struct pci_bus, dev)
569 
570 /*
571  * Returns true if the PCI bus is root (behind host-PCI bridge),
572  * false otherwise
573  *
574  * Some code assumes that "bus->self == NULL" means that bus is a root bus.
575  * This is incorrect because "virtual" buses added for SR-IOV (via
576  * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
577  */
578 static inline bool pci_is_root_bus(struct pci_bus *pbus)
579 {
580         return !(pbus->parent);
581 }
582 
583 /**
584  * pci_is_bridge - check if the PCI device is a bridge
585  * @dev: PCI device
586  *
587  * Return true if the PCI device is bridge whether it has subordinate
588  * or not.
589  */
590 static inline bool pci_is_bridge(struct pci_dev *dev)
591 {
592         return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
593                 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
594 }
595 
596 #define for_each_pci_bridge(dev, bus)                           \
597         list_for_each_entry(dev, &bus->devices, bus_list)       \
598                 if (!pci_is_bridge(dev)) {} else
599 
600 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
601 {
602         dev = pci_physfn(dev);
603         if (pci_is_root_bus(dev->bus))
604                 return NULL;
605 
606         return dev->bus->self;
607 }
608 
609 struct device *pci_get_host_bridge_device(struct pci_dev *dev);
610 void pci_put_host_bridge_device(struct device *dev);
611 
612 #ifdef CONFIG_PCI_MSI
613 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
614 {
615         return pci_dev->msi_enabled || pci_dev->msix_enabled;
616 }
617 #else
618 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
619 #endif
620 
621 /* Error values that may be returned by PCI functions */
622 #define PCIBIOS_SUCCESSFUL              0x00
623 #define PCIBIOS_FUNC_NOT_SUPPORTED      0x81
624 #define PCIBIOS_BAD_VENDOR_ID           0x83
625 #define PCIBIOS_DEVICE_NOT_FOUND        0x86
626 #define PCIBIOS_BAD_REGISTER_NUMBER     0x87
627 #define PCIBIOS_SET_FAILED              0x88
628 #define PCIBIOS_BUFFER_TOO_SMALL        0x89
629 
630 /* Translate above to generic errno for passing back through non-PCI code */
631 static inline int pcibios_err_to_errno(int err)
632 {
633         if (err <= PCIBIOS_SUCCESSFUL)
634                 return err; /* Assume already errno */
635 
636         switch (err) {
637         case PCIBIOS_FUNC_NOT_SUPPORTED:
638                 return -ENOENT;
639         case PCIBIOS_BAD_VENDOR_ID:
640                 return -ENOTTY;
641         case PCIBIOS_DEVICE_NOT_FOUND:
642                 return -ENODEV;
643         case PCIBIOS_BAD_REGISTER_NUMBER:
644                 return -EFAULT;
645         case PCIBIOS_SET_FAILED:
646                 return -EIO;
647         case PCIBIOS_BUFFER_TOO_SMALL:
648                 return -ENOSPC;
649         }
650 
651         return -ERANGE;
652 }
653 
654 /* Low-level architecture-dependent routines */
655 
656 struct pci_ops {
657         int (*add_bus)(struct pci_bus *bus);
658         void (*remove_bus)(struct pci_bus *bus);
659         void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
660         int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
661         int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
662 };
663 
664 /*
665  * ACPI needs to be able to access PCI config space before we've done a
666  * PCI bus scan and created pci_bus structures.
667  */
668 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
669                  int reg, int len, u32 *val);
670 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
671                   int reg, int len, u32 val);
672 
673 #ifdef CONFIG_PCI_BUS_ADDR_T_64BIT
674 typedef u64 pci_bus_addr_t;
675 #else
676 typedef u32 pci_bus_addr_t;
677 #endif
678 
679 struct pci_bus_region {
680         pci_bus_addr_t  start;
681         pci_bus_addr_t  end;
682 };
683 
684 struct pci_dynids {
685         spinlock_t              lock;   /* Protects list, index */
686         struct list_head        list;   /* For IDs added at runtime */
687 };
688 
689 
690 /*
691  * PCI Error Recovery System (PCI-ERS).  If a PCI device driver provides
692  * a set of callbacks in struct pci_error_handlers, that device driver
693  * will be notified of PCI bus errors, and will be driven to recovery
694  * when an error occurs.
695  */
696 
697 typedef unsigned int __bitwise pci_ers_result_t;
698 
699 enum pci_ers_result {
700         /* No result/none/not supported in device driver */
701         PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
702 
703         /* Device driver can recover without slot reset */
704         PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
705 
706         /* Device driver wants slot to be reset */
707         PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
708 
709         /* Device has completely failed, is unrecoverable */
710         PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
711 
712         /* Device driver is fully recovered and operational */
713         PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
714 
715         /* No AER capabilities registered for the driver */
716         PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
717 };
718 
719 /* PCI bus error event callbacks */
720 struct pci_error_handlers {
721         /* PCI bus error detected on this device */
722         pci_ers_result_t (*error_detected)(struct pci_dev *dev,
723                                            enum pci_channel_state error);
724 
725         /* MMIO has been re-enabled, but not DMA */
726         pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
727 
728         /* PCI slot has been reset */
729         pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
730 
731         /* PCI function reset prepare or completed */
732         void (*reset_prepare)(struct pci_dev *dev);
733         void (*reset_done)(struct pci_dev *dev);
734 
735         /* Device driver may resume normal operations */
736         void (*resume)(struct pci_dev *dev);
737 };
738 
739 
740 struct module;
741 struct pci_driver {
742         struct list_head        node;
743         const char              *name;
744         const struct pci_device_id *id_table;   /* Must be non-NULL for probe to be called */
745         int  (*probe)(struct pci_dev *dev, const struct pci_device_id *id);     /* New device inserted */
746         void (*remove)(struct pci_dev *dev);    /* Device removed (NULL if not a hot-plug capable driver) */
747         int  (*suspend)(struct pci_dev *dev, pm_message_t state);       /* Device suspended */
748         int  (*suspend_late)(struct pci_dev *dev, pm_message_t state);
749         int  (*resume_early)(struct pci_dev *dev);
750         int  (*resume) (struct pci_dev *dev);   /* Device woken up */
751         void (*shutdown) (struct pci_dev *dev);
752         int  (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* On PF */
753         const struct pci_error_handlers *err_handler;
754         const struct attribute_group **groups;
755         struct device_driver    driver;
756         struct pci_dynids       dynids;
757 };
758 
759 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
760 
761 /**
762  * PCI_DEVICE - macro used to describe a specific PCI device
763  * @vend: the 16 bit PCI Vendor ID
764  * @dev: the 16 bit PCI Device ID
765  *
766  * This macro is used to create a struct pci_device_id that matches a
767  * specific device.  The subvendor and subdevice fields will be set to
768  * PCI_ANY_ID.
769  */
770 #define PCI_DEVICE(vend,dev) \
771         .vendor = (vend), .device = (dev), \
772         .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
773 
774 /**
775  * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
776  * @vend: the 16 bit PCI Vendor ID
777  * @dev: the 16 bit PCI Device ID
778  * @subvend: the 16 bit PCI Subvendor ID
779  * @subdev: the 16 bit PCI Subdevice ID
780  *
781  * This macro is used to create a struct pci_device_id that matches a
782  * specific device with subsystem information.
783  */
784 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
785         .vendor = (vend), .device = (dev), \
786         .subvendor = (subvend), .subdevice = (subdev)
787 
788 /**
789  * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
790  * @dev_class: the class, subclass, prog-if triple for this device
791  * @dev_class_mask: the class mask for this device
792  *
793  * This macro is used to create a struct pci_device_id that matches a
794  * specific PCI class.  The vendor, device, subvendor, and subdevice
795  * fields will be set to PCI_ANY_ID.
796  */
797 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
798         .class = (dev_class), .class_mask = (dev_class_mask), \
799         .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
800         .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
801 
802 /**
803  * PCI_VDEVICE - macro used to describe a specific PCI device in short form
804  * @vend: the vendor name
805  * @dev: the 16 bit PCI Device ID
806  *
807  * This macro is used to create a struct pci_device_id that matches a
808  * specific PCI device.  The subvendor, and subdevice fields will be set
809  * to PCI_ANY_ID. The macro allows the next field to follow as the device
810  * private data.
811  */
812 #define PCI_VDEVICE(vend, dev) \
813         .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
814         .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
815 
816 enum {
817         PCI_REASSIGN_ALL_RSRC   = 0x00000001,   /* Ignore firmware setup */
818         PCI_REASSIGN_ALL_BUS    = 0x00000002,   /* Reassign all bus numbers */
819         PCI_PROBE_ONLY          = 0x00000004,   /* Use existing setup */
820         PCI_CAN_SKIP_ISA_ALIGN  = 0x00000008,   /* Don't do ISA alignment */
821         PCI_ENABLE_PROC_DOMAINS = 0x00000010,   /* Enable domains in /proc */
822         PCI_COMPAT_DOMAIN_0     = 0x00000020,   /* ... except domain 0 */
823         PCI_SCAN_ALL_PCIE_DEVS  = 0x00000040,   /* Scan all, not just dev 0 */
824 };
825 
826 /* These external functions are only available when PCI support is enabled */
827 #ifdef CONFIG_PCI
828 
829 extern unsigned int pci_flags;
830 
831 static inline void pci_set_flags(int flags) { pci_flags = flags; }
832 static inline void pci_add_flags(int flags) { pci_flags |= flags; }
833 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
834 static inline int pci_has_flag(int flag) { return pci_flags & flag; }
835 
836 void pcie_bus_configure_settings(struct pci_bus *bus);
837 
838 enum pcie_bus_config_types {
839         PCIE_BUS_TUNE_OFF,      /* Don't touch MPS at all */
840         PCIE_BUS_DEFAULT,       /* Ensure MPS matches upstream bridge */
841         PCIE_BUS_SAFE,          /* Use largest MPS boot-time devices support */
842         PCIE_BUS_PERFORMANCE,   /* Use MPS and MRRS for best performance */
843         PCIE_BUS_PEER2PEER,     /* Set MPS = 128 for all devices */
844 };
845 
846 extern enum pcie_bus_config_types pcie_bus_config;
847 
848 extern struct bus_type pci_bus_type;
849 
850 /* Do NOT directly access these two variables, unless you are arch-specific PCI
851  * code, or PCI core code. */
852 extern struct list_head pci_root_buses; /* List of all known PCI buses */
853 /* Some device drivers need know if PCI is initiated */
854 int no_pci_devices(void);
855 
856 void pcibios_resource_survey_bus(struct pci_bus *bus);
857 void pcibios_bus_add_device(struct pci_dev *pdev);
858 void pcibios_add_bus(struct pci_bus *bus);
859 void pcibios_remove_bus(struct pci_bus *bus);
860 void pcibios_fixup_bus(struct pci_bus *);
861 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
862 /* Architecture-specific versions may override this (weak) */
863 char *pcibios_setup(char *str);
864 
865 /* Used only when drivers/pci/setup.c is used */
866 resource_size_t pcibios_align_resource(void *, const struct resource *,
867                                 resource_size_t,
868                                 resource_size_t);
869 
870 /* Weak but can be overriden by arch */
871 void pci_fixup_cardbus(struct pci_bus *);
872 
873 /* Generic PCI functions used internally */
874 
875 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
876                              struct resource *res);
877 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
878                              struct pci_bus_region *region);
879 void pcibios_scan_specific_bus(int busn);
880 struct pci_bus *pci_find_bus(int domain, int busnr);
881 void pci_bus_add_devices(const struct pci_bus *bus);
882 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
883 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
884                                     struct pci_ops *ops, void *sysdata,
885                                     struct list_head *resources);
886 int pci_host_probe(struct pci_host_bridge *bridge);
887 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
888 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
889 void pci_bus_release_busn_res(struct pci_bus *b);
890 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
891                                   struct pci_ops *ops, void *sysdata,
892                                   struct list_head *resources);
893 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
894 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
895                                 int busnr);
896 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
897 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
898                                  const char *name,
899                                  struct hotplug_slot *hotplug);
900 void pci_destroy_slot(struct pci_slot *slot);
901 #ifdef CONFIG_SYSFS
902 void pci_dev_assign_slot(struct pci_dev *dev);
903 #else
904 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
905 #endif
906 int pci_scan_slot(struct pci_bus *bus, int devfn);
907 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
908 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
909 unsigned int pci_scan_child_bus(struct pci_bus *bus);
910 void pci_bus_add_device(struct pci_dev *dev);
911 void pci_read_bridge_bases(struct pci_bus *child);
912 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
913                                           struct resource *res);
914 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev);
915 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
916 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
917 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
918 struct pci_dev *pci_dev_get(struct pci_dev *dev);
919 void pci_dev_put(struct pci_dev *dev);
920 void pci_remove_bus(struct pci_bus *b);
921 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
922 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
923 void pci_stop_root_bus(struct pci_bus *bus);
924 void pci_remove_root_bus(struct pci_bus *bus);
925 void pci_setup_cardbus(struct pci_bus *bus);
926 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
927 void pci_sort_breadthfirst(void);
928 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
929 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
930 
931 /* Generic PCI functions exported to card drivers */
932 
933 enum pci_lost_interrupt_reason {
934         PCI_LOST_IRQ_NO_INFORMATION = 0,
935         PCI_LOST_IRQ_DISABLE_MSI,
936         PCI_LOST_IRQ_DISABLE_MSIX,
937         PCI_LOST_IRQ_DISABLE_ACPI,
938 };
939 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
940 int pci_find_capability(struct pci_dev *dev, int cap);
941 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
942 int pci_find_ext_capability(struct pci_dev *dev, int cap);
943 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
944 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
945 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
946 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
947 
948 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
949                                struct pci_dev *from);
950 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
951                                unsigned int ss_vendor, unsigned int ss_device,
952                                struct pci_dev *from);
953 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
954 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
955                                             unsigned int devfn);
956 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
957 int pci_dev_present(const struct pci_device_id *ids);
958 
959 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
960                              int where, u8 *val);
961 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
962                              int where, u16 *val);
963 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
964                               int where, u32 *val);
965 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
966                               int where, u8 val);
967 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
968                               int where, u16 val);
969 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
970                                int where, u32 val);
971 
972 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
973                             int where, int size, u32 *val);
974 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
975                             int where, int size, u32 val);
976 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
977                               int where, int size, u32 *val);
978 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
979                                int where, int size, u32 val);
980 
981 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
982 
983 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
984 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
985 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
986 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
987 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
988 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
989 
990 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
991 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
992 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
993 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
994 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
995                                        u16 clear, u16 set);
996 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
997                                         u32 clear, u32 set);
998 
999 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1000                                            u16 set)
1001 {
1002         return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1003 }
1004 
1005 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1006                                             u32 set)
1007 {
1008         return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1009 }
1010 
1011 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1012                                              u16 clear)
1013 {
1014         return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1015 }
1016 
1017 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1018                                               u32 clear)
1019 {
1020         return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1021 }
1022 
1023 /* User-space driven config access */
1024 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1025 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1026 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1027 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1028 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1029 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1030 
1031 int __must_check pci_enable_device(struct pci_dev *dev);
1032 int __must_check pci_enable_device_io(struct pci_dev *dev);
1033 int __must_check pci_enable_device_mem(struct pci_dev *dev);
1034 int __must_check pci_reenable_device(struct pci_dev *);
1035 int __must_check pcim_enable_device(struct pci_dev *pdev);
1036 void pcim_pin_device(struct pci_dev *pdev);
1037 
1038 static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1039 {
1040         /*
1041          * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1042          * writable and no quirk has marked the feature broken.
1043          */
1044         return !pdev->broken_intx_masking;
1045 }
1046 
1047 static inline int pci_is_enabled(struct pci_dev *pdev)
1048 {
1049         return (atomic_read(&pdev->enable_cnt) > 0);
1050 }
1051 
1052 static inline int pci_is_managed(struct pci_dev *pdev)
1053 {
1054         return pdev->is_managed;
1055 }
1056 
1057 void pci_disable_device(struct pci_dev *dev);
1058 
1059 extern unsigned int pcibios_max_latency;
1060 void pci_set_master(struct pci_dev *dev);
1061 void pci_clear_master(struct pci_dev *dev);
1062 
1063 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1064 int pci_set_cacheline_size(struct pci_dev *dev);
1065 #define HAVE_PCI_SET_MWI
1066 int __must_check pci_set_mwi(struct pci_dev *dev);
1067 int __must_check pcim_set_mwi(struct pci_dev *dev);
1068 int pci_try_set_mwi(struct pci_dev *dev);
1069 void pci_clear_mwi(struct pci_dev *dev);
1070 void pci_intx(struct pci_dev *dev, int enable);
1071 bool pci_check_and_mask_intx(struct pci_dev *dev);
1072 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1073 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1074 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1075 int pcix_get_max_mmrbc(struct pci_dev *dev);
1076 int pcix_get_mmrbc(struct pci_dev *dev);
1077 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1078 int pcie_get_readrq(struct pci_dev *dev);
1079 int pcie_set_readrq(struct pci_dev *dev, int rq);
1080 int pcie_get_mps(struct pci_dev *dev);
1081 int pcie_set_mps(struct pci_dev *dev, int mps);
1082 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
1083                           enum pcie_link_width *width);
1084 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1085                              enum pci_bus_speed *speed,
1086                              enum pcie_link_width *width);
1087 void pcie_print_link_status(struct pci_dev *dev);
1088 int pcie_flr(struct pci_dev *dev);
1089 int __pci_reset_function_locked(struct pci_dev *dev);
1090 int pci_reset_function(struct pci_dev *dev);
1091 int pci_reset_function_locked(struct pci_dev *dev);
1092 int pci_try_reset_function(struct pci_dev *dev);
1093 int pci_probe_reset_slot(struct pci_slot *slot);
1094 int pci_reset_slot(struct pci_slot *slot);
1095 int pci_try_reset_slot(struct pci_slot *slot);
1096 int pci_probe_reset_bus(struct pci_bus *bus);
1097 int pci_reset_bus(struct pci_bus *bus);
1098 int pci_try_reset_bus(struct pci_bus *bus);
1099 void pci_reset_secondary_bus(struct pci_dev *dev);
1100 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1101 int pci_reset_bridge_secondary_bus(struct pci_dev *dev);
1102 void pci_update_resource(struct pci_dev *dev, int resno);
1103 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1104 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1105 void pci_release_resource(struct pci_dev *dev, int resno);
1106 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1107 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1108 bool pci_device_is_present(struct pci_dev *pdev);
1109 void pci_ignore_hotplug(struct pci_dev *dev);
1110 
1111 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1112                 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1113                 const char *fmt, ...);
1114 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1115 
1116 /* ROM control related routines */
1117 int pci_enable_rom(struct pci_dev *pdev);
1118 void pci_disable_rom(struct pci_dev *pdev);
1119 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1120 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1121 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
1122 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
1123 
1124 /* Power management related routines */
1125 int pci_save_state(struct pci_dev *dev);
1126 void pci_restore_state(struct pci_dev *dev);
1127 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1128 int pci_load_saved_state(struct pci_dev *dev,
1129                          struct pci_saved_state *state);
1130 int pci_load_and_free_saved_state(struct pci_dev *dev,
1131                                   struct pci_saved_state **state);
1132 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1133 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1134                                                    u16 cap);
1135 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1136 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1137                                 u16 cap, unsigned int size);
1138 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
1139 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1140 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1141 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1142 void pci_pme_active(struct pci_dev *dev, bool enable);
1143 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1144 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1145 int pci_prepare_to_sleep(struct pci_dev *dev);
1146 int pci_back_from_sleep(struct pci_dev *dev);
1147 bool pci_dev_run_wake(struct pci_dev *dev);
1148 bool pci_check_pme_status(struct pci_dev *dev);
1149 void pci_pme_wakeup_bus(struct pci_bus *bus);
1150 void pci_d3cold_enable(struct pci_dev *dev);
1151 void pci_d3cold_disable(struct pci_dev *dev);
1152 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1153 void pci_wakeup_bus(struct pci_bus *bus);
1154 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1155 
1156 /* PCI Virtual Channel */
1157 int pci_save_vc_state(struct pci_dev *dev);
1158 void pci_restore_vc_state(struct pci_dev *dev);
1159 void pci_allocate_vc_save_buffers(struct pci_dev *dev);
1160 
1161 /* For use by arch with custom probe code */
1162 void set_pcie_port_type(struct pci_dev *pdev);
1163 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1164 
1165 /* Functions for PCI Hotplug drivers to use */
1166 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1167 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1168 unsigned int pci_rescan_bus(struct pci_bus *bus);
1169 void pci_lock_rescan_remove(void);
1170 void pci_unlock_rescan_remove(void);
1171 
1172 /* Vital Product Data routines */
1173 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1174 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1175 int pci_set_vpd_size(struct pci_dev *dev, size_t len);
1176 
1177 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1178 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1179 void pci_bus_assign_resources(const struct pci_bus *bus);
1180 void pci_bus_claim_resources(struct pci_bus *bus);
1181 void pci_bus_size_bridges(struct pci_bus *bus);
1182 int pci_claim_resource(struct pci_dev *, int);
1183 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1184 void pci_assign_unassigned_resources(void);
1185 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1186 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1187 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1188 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1189 void pdev_enable_device(struct pci_dev *);
1190 int pci_enable_resources(struct pci_dev *, int mask);
1191 void pci_assign_irq(struct pci_dev *dev);
1192 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1193 #define HAVE_PCI_REQ_REGIONS    2
1194 int __must_check pci_request_regions(struct pci_dev *, const char *);
1195 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1196 void pci_release_regions(struct pci_dev *);
1197 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1198 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1199 void pci_release_region(struct pci_dev *, int);
1200 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1201 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1202 void pci_release_selected_regions(struct pci_dev *, int);
1203 
1204 /* drivers/pci/bus.c */
1205 struct pci_bus *pci_bus_get(struct pci_bus *bus);
1206 void pci_bus_put(struct pci_bus *bus);
1207 void pci_add_resource(struct list_head *resources, struct resource *res);
1208 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1209                              resource_size_t offset);
1210 void pci_free_resource_list(struct list_head *resources);
1211 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1212                           unsigned int flags);
1213 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1214 void pci_bus_remove_resources(struct pci_bus *bus);
1215 int devm_request_pci_bus_resources(struct device *dev,
1216                                    struct list_head *resources);
1217 
1218 #define pci_bus_for_each_resource(bus, res, i)                          \
1219         for (i = 0;                                                     \
1220             (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1221              i++)
1222 
1223 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1224                         struct resource *res, resource_size_t size,
1225                         resource_size_t align, resource_size_t min,
1226                         unsigned long type_mask,
1227                         resource_size_t (*alignf)(void *,
1228                                                   const struct resource *,
1229                                                   resource_size_t,
1230                                                   resource_size_t),
1231                         void *alignf_data);
1232 
1233 
1234 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1235                         resource_size_t size);
1236 unsigned long pci_address_to_pio(phys_addr_t addr);
1237 phys_addr_t pci_pio_to_address(unsigned long pio);
1238 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1239 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1240                            phys_addr_t phys_addr);
1241 void pci_unmap_iospace(struct resource *res);
1242 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1243                                       resource_size_t offset,
1244                                       resource_size_t size);
1245 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1246                                           struct resource *res);
1247 
1248 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1249 {
1250         struct pci_bus_region region;
1251 
1252         pcibios_resource_to_bus(pdev->bus, &region, &pdev->resource[bar]);
1253         return region.start;
1254 }
1255 
1256 /* Proper probing supporting hot-pluggable devices */
1257 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1258                                        const char *mod_name);
1259 
1260 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
1261 #define pci_register_driver(driver)             \
1262         __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1263 
1264 void pci_unregister_driver(struct pci_driver *dev);
1265 
1266 /**
1267  * module_pci_driver() - Helper macro for registering a PCI driver
1268  * @__pci_driver: pci_driver struct
1269  *
1270  * Helper macro for PCI drivers which do not do anything special in module
1271  * init/exit. This eliminates a lot of boilerplate. Each module may only
1272  * use this macro once, and calling it replaces module_init() and module_exit()
1273  */
1274 #define module_pci_driver(__pci_driver) \
1275         module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1276 
1277 /**
1278  * builtin_pci_driver() - Helper macro for registering a PCI driver
1279  * @__pci_driver: pci_driver struct
1280  *
1281  * Helper macro for PCI drivers which do not do anything special in their
1282  * init code. This eliminates a lot of boilerplate. Each driver may only
1283  * use this macro once, and calling it replaces device_initcall(...)
1284  */
1285 #define builtin_pci_driver(__pci_driver) \
1286         builtin_driver(__pci_driver, pci_register_driver)
1287 
1288 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1289 int pci_add_dynid(struct pci_driver *drv,
1290                   unsigned int vendor, unsigned int device,
1291                   unsigned int subvendor, unsigned int subdevice,
1292                   unsigned int class, unsigned int class_mask,
1293                   unsigned long driver_data);
1294 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1295                                          struct pci_dev *dev);
1296 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1297                     int pass);
1298 
1299 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1300                   void *userdata);
1301 int pci_cfg_space_size(struct pci_dev *dev);
1302 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1303 void pci_setup_bridge(struct pci_bus *bus);
1304 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1305                                          unsigned long type);
1306 
1307 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1308 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1309 
1310 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1311                       unsigned int command_bits, u32 flags);
1312 
1313 #define PCI_IRQ_LEGACY          (1 << 0) /* Allow legacy interrupts */
1314 #define PCI_IRQ_MSI             (1 << 1) /* Allow MSI interrupts */
1315 #define PCI_IRQ_MSIX            (1 << 2) /* Allow MSI-X interrupts */
1316 #define PCI_IRQ_AFFINITY        (1 << 3) /* Auto-assign affinity */
1317 #define PCI_IRQ_ALL_TYPES \
1318         (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1319 
1320 /* kmem_cache style wrapper around pci_alloc_consistent() */
1321 
1322 #include <linux/pci-dma.h>
1323 #include <linux/dmapool.h>
1324 
1325 #define pci_pool dma_pool
1326 #define pci_pool_create(name, pdev, size, align, allocation) \
1327                 dma_pool_create(name, &pdev->dev, size, align, allocation)
1328 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1329 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1330 #define pci_pool_zalloc(pool, flags, handle) \
1331                 dma_pool_zalloc(pool, flags, handle)
1332 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1333 
1334 struct msix_entry {
1335         u32     vector; /* Kernel uses to write allocated vector */
1336         u16     entry;  /* Driver uses to specify entry, OS writes */
1337 };
1338 
1339 #ifdef CONFIG_PCI_MSI
1340 int pci_msi_vec_count(struct pci_dev *dev);
1341 void pci_disable_msi(struct pci_dev *dev);
1342 int pci_msix_vec_count(struct pci_dev *dev);
1343 void pci_disable_msix(struct pci_dev *dev);
1344 void pci_restore_msi_state(struct pci_dev *dev);
1345 int pci_msi_enabled(void);
1346 int pci_enable_msi(struct pci_dev *dev);
1347 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1348                           int minvec, int maxvec);
1349 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1350                                         struct msix_entry *entries, int nvec)
1351 {
1352         int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1353         if (rc < 0)
1354                 return rc;
1355         return 0;
1356 }
1357 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1358                                    unsigned int max_vecs, unsigned int flags,
1359                                    const struct irq_affinity *affd);
1360 
1361 void pci_free_irq_vectors(struct pci_dev *dev);
1362 int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1363 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1364 int pci_irq_get_node(struct pci_dev *pdev, int vec);
1365 
1366 #else
1367 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1368 static inline void pci_disable_msi(struct pci_dev *dev) { }
1369 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1370 static inline void pci_disable_msix(struct pci_dev *dev) { }
1371 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1372 static inline int pci_msi_enabled(void) { return 0; }
1373 static inline int pci_enable_msi(struct pci_dev *dev)
1374 { return -ENOSYS; }
1375 static inline int pci_enable_msix_range(struct pci_dev *dev,
1376                         struct msix_entry *entries, int minvec, int maxvec)
1377 { return -ENOSYS; }
1378 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1379                         struct msix_entry *entries, int nvec)
1380 { return -ENOSYS; }
1381 
1382 static inline int
1383 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1384                                unsigned int max_vecs, unsigned int flags,
1385                                const struct irq_affinity *aff_desc)
1386 {
1387         if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1388                 return 1;
1389         return -ENOSPC;
1390 }
1391 
1392 static inline void pci_free_irq_vectors(struct pci_dev *dev)
1393 {
1394 }
1395 
1396 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1397 {
1398         if (WARN_ON_ONCE(nr > 0))
1399                 return -EINVAL;
1400         return dev->irq;
1401 }
1402 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1403                 int vec)
1404 {
1405         return cpu_possible_mask;
1406 }
1407 
1408 static inline int pci_irq_get_node(struct pci_dev *pdev, int vec)
1409 {
1410         return first_online_node;
1411 }
1412 #endif
1413 
1414 static inline int
1415 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1416                       unsigned int max_vecs, unsigned int flags)
1417 {
1418         return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1419                                               NULL);
1420 }
1421 
1422 /**
1423  * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1424  * @d: the INTx IRQ domain
1425  * @node: the DT node for the device whose interrupt we're translating
1426  * @intspec: the interrupt specifier data from the DT
1427  * @intsize: the number of entries in @intspec
1428  * @out_hwirq: pointer at which to write the hwirq number
1429  * @out_type: pointer at which to write the interrupt type
1430  *
1431  * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1432  * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1433  * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1434  * INTx value to obtain the hwirq number.
1435  *
1436  * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1437  */
1438 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1439                                       struct device_node *node,
1440                                       const u32 *intspec,
1441                                       unsigned int intsize,
1442                                       unsigned long *out_hwirq,
1443                                       unsigned int *out_type)
1444 {
1445         const u32 intx = intspec[0];
1446 
1447         if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1448                 return -EINVAL;
1449 
1450         *out_hwirq = intx - PCI_INTERRUPT_INTA;
1451         return 0;
1452 }
1453 
1454 #ifdef CONFIG_PCIEPORTBUS
1455 extern bool pcie_ports_disabled;
1456 #else
1457 #define pcie_ports_disabled     true
1458 #endif
1459 
1460 #ifdef CONFIG_PCIEASPM
1461 bool pcie_aspm_support_enabled(void);
1462 #else
1463 static inline bool pcie_aspm_support_enabled(void) { return false; }
1464 #endif
1465 
1466 #ifdef CONFIG_PCIEAER
1467 void pci_no_aer(void);
1468 bool pci_aer_available(void);
1469 int pci_aer_init(struct pci_dev *dev);
1470 #else
1471 static inline void pci_no_aer(void) { }
1472 static inline bool pci_aer_available(void) { return false; }
1473 static inline int pci_aer_init(struct pci_dev *d) { return -ENODEV; }
1474 #endif
1475 
1476 #ifdef CONFIG_PCIE_ECRC
1477 void pcie_set_ecrc_checking(struct pci_dev *dev);
1478 void pcie_ecrc_get_policy(char *str);
1479 #else
1480 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
1481 static inline void pcie_ecrc_get_policy(char *str) { }
1482 #endif
1483 
1484 #ifdef CONFIG_PCI_ATS
1485 /* Address Translation Service */
1486 void pci_ats_init(struct pci_dev *dev);
1487 int pci_enable_ats(struct pci_dev *dev, int ps);
1488 void pci_disable_ats(struct pci_dev *dev);
1489 int pci_ats_queue_depth(struct pci_dev *dev);
1490 #else
1491 static inline void pci_ats_init(struct pci_dev *d) { }
1492 static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; }
1493 static inline void pci_disable_ats(struct pci_dev *d) { }
1494 static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; }
1495 #endif
1496 
1497 #ifdef CONFIG_PCIE_PTM
1498 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1499 #else
1500 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1501 { return -EINVAL; }
1502 #endif
1503 
1504 void pci_cfg_access_lock(struct pci_dev *dev);
1505 bool pci_cfg_access_trylock(struct pci_dev *dev);
1506 void pci_cfg_access_unlock(struct pci_dev *dev);
1507 
1508 /*
1509  * PCI domain support.  Sometimes called PCI segment (eg by ACPI),
1510  * a PCI domain is defined to be a set of PCI buses which share
1511  * configuration space.
1512  */
1513 #ifdef CONFIG_PCI_DOMAINS
1514 extern int pci_domains_supported;
1515 int pci_get_new_domain_nr(void);
1516 #else
1517 enum { pci_domains_supported = 0 };
1518 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1519 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1520 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1521 #endif /* CONFIG_PCI_DOMAINS */
1522 
1523 /*
1524  * Generic implementation for PCI domain support. If your
1525  * architecture does not need custom management of PCI
1526  * domains then this implementation will be used
1527  */
1528 #ifdef CONFIG_PCI_DOMAINS_GENERIC
1529 static inline int pci_domain_nr(struct pci_bus *bus)
1530 {
1531         return bus->domain_nr;
1532 }
1533 #ifdef CONFIG_ACPI
1534 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1535 #else
1536 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1537 { return 0; }
1538 #endif
1539 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1540 #endif
1541 
1542 /* Some architectures require additional setup to direct VGA traffic */
1543 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1544                                     unsigned int command_bits, u32 flags);
1545 void pci_register_set_vga_state(arch_set_vga_state_t func);
1546 
1547 static inline int
1548 pci_request_io_regions(struct pci_dev *pdev, const char *name)
1549 {
1550         return pci_request_selected_regions(pdev,
1551                             pci_select_bars(pdev, IORESOURCE_IO), name);
1552 }
1553 
1554 static inline void
1555 pci_release_io_regions(struct pci_dev *pdev)
1556 {
1557         return pci_release_selected_regions(pdev,
1558                             pci_select_bars(pdev, IORESOURCE_IO));
1559 }
1560 
1561 static inline int
1562 pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1563 {
1564         return pci_request_selected_regions(pdev,
1565                             pci_select_bars(pdev, IORESOURCE_MEM), name);
1566 }
1567 
1568 static inline void
1569 pci_release_mem_regions(struct pci_dev *pdev)
1570 {
1571         return pci_release_selected_regions(pdev,
1572                             pci_select_bars(pdev, IORESOURCE_MEM));
1573 }
1574 
1575 #else /* CONFIG_PCI is not enabled */
1576 
1577 static inline void pci_set_flags(int flags) { }
1578 static inline void pci_add_flags(int flags) { }
1579 static inline void pci_clear_flags(int flags) { }
1580 static inline int pci_has_flag(int flag) { return 0; }
1581 
1582 /*
1583  * If the system does not have PCI, clearly these return errors.  Define
1584  * these as simple inline functions to avoid hair in drivers.
1585  */
1586 #define _PCI_NOP(o, s, t) \
1587         static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1588                                                 int where, t val) \
1589                 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1590 
1591 #define _PCI_NOP_ALL(o, x)      _PCI_NOP(o, byte, u8 x) \
1592                                 _PCI_NOP(o, word, u16 x) \
1593                                 _PCI_NOP(o, dword, u32 x)
1594 _PCI_NOP_ALL(read, *)
1595 _PCI_NOP_ALL(write,)
1596 
1597 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1598                                              unsigned int device,
1599                                              struct pci_dev *from)
1600 { return NULL; }
1601 
1602 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1603                                              unsigned int device,
1604                                              unsigned int ss_vendor,
1605                                              unsigned int ss_device,
1606                                              struct pci_dev *from)
1607 { return NULL; }
1608 
1609 static inline struct pci_dev *pci_get_class(unsigned int class,
1610                                             struct pci_dev *from)
1611 { return NULL; }
1612 
1613 #define pci_dev_present(ids)    (0)
1614 #define no_pci_devices()        (1)
1615 #define pci_dev_put(dev)        do { } while (0)
1616 
1617 static inline void pci_set_master(struct pci_dev *dev) { }
1618 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1619 static inline void pci_disable_device(struct pci_dev *dev) { }
1620 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1621 { return -EBUSY; }
1622 static inline int __pci_register_driver(struct pci_driver *drv,
1623                                         struct module *owner)
1624 { return 0; }
1625 static inline int pci_register_driver(struct pci_driver *drv)
1626 { return 0; }
1627 static inline void pci_unregister_driver(struct pci_driver *drv) { }
1628 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1629 { return 0; }
1630 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1631                                            int cap)
1632 { return 0; }
1633 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1634 { return 0; }
1635 
1636 /* Power management related routines */
1637 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1638 static inline void pci_restore_state(struct pci_dev *dev) { }
1639 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1640 { return 0; }
1641 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1642 { return 0; }
1643 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1644                                            pm_message_t state)
1645 { return PCI_D0; }
1646 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1647                                   int enable)
1648 { return 0; }
1649 
1650 static inline struct resource *pci_find_resource(struct pci_dev *dev,
1651                                                  struct resource *res)
1652 { return NULL; }
1653 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1654 { return -EIO; }
1655 static inline void pci_release_regions(struct pci_dev *dev) { }
1656 
1657 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1658 
1659 static inline void pci_block_cfg_access(struct pci_dev *dev) { }
1660 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1661 { return 0; }
1662 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { }
1663 
1664 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1665 { return NULL; }
1666 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1667                                                 unsigned int devfn)
1668 { return NULL; }
1669 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1670                                         unsigned int bus, unsigned int devfn)
1671 { return NULL; }
1672 
1673 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1674 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1675 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1676 
1677 #define dev_is_pci(d) (false)
1678 #define dev_is_pf(d) (false)
1679 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1680 { return false; }
1681 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1682                                       struct device_node *node,
1683                                       const u32 *intspec,
1684                                       unsigned int intsize,
1685                                       unsigned long *out_hwirq,
1686                                       unsigned int *out_type)
1687 { return -EINVAL; }
1688 #endif /* CONFIG_PCI */
1689 
1690 /* Include architecture-dependent settings and functions */
1691 
1692 #include <asm/pci.h>
1693 
1694 /* These two functions provide almost identical functionality. Depennding
1695  * on the architecture, one will be implemented as a wrapper around the
1696  * other (in drivers/pci/mmap.c).
1697  *
1698  * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1699  * is expected to be an offset within that region.
1700  *
1701  * pci_mmap_page_range() is the legacy architecture-specific interface,
1702  * which accepts a "user visible" resource address converted by
1703  * pci_resource_to_user(), as used in the legacy mmap() interface in
1704  * /proc/bus/pci/.
1705  */
1706 int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1707                             struct vm_area_struct *vma,
1708                             enum pci_mmap_state mmap_state, int write_combine);
1709 int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1710                         struct vm_area_struct *vma,
1711                         enum pci_mmap_state mmap_state, int write_combine);
1712 
1713 #ifndef arch_can_pci_mmap_wc
1714 #define arch_can_pci_mmap_wc()          0
1715 #endif
1716 
1717 #ifndef arch_can_pci_mmap_io
1718 #define arch_can_pci_mmap_io()          0
1719 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1720 #else
1721 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1722 #endif
1723 
1724 #ifndef pci_root_bus_fwnode
1725 #define pci_root_bus_fwnode(bus)        NULL
1726 #endif
1727 
1728 /*
1729  * These helpers provide future and backwards compatibility
1730  * for accessing popular PCI BAR info
1731  */
1732 #define pci_resource_start(dev, bar)    ((dev)->resource[(bar)].start)
1733 #define pci_resource_end(dev, bar)      ((dev)->resource[(bar)].end)
1734 #define pci_resource_flags(dev, bar)    ((dev)->resource[(bar)].flags)
1735 #define pci_resource_len(dev,bar) \
1736         ((pci_resource_start((dev), (bar)) == 0 &&      \
1737           pci_resource_end((dev), (bar)) ==             \
1738           pci_resource_start((dev), (bar))) ? 0 :       \
1739                                                         \
1740          (pci_resource_end((dev), (bar)) -              \
1741           pci_resource_start((dev), (bar)) + 1))
1742 
1743 /*
1744  * Similar to the helpers above, these manipulate per-pci_dev
1745  * driver-specific data.  They are really just a wrapper around
1746  * the generic device structure functions of these calls.
1747  */
1748 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1749 {
1750         return dev_get_drvdata(&pdev->dev);
1751 }
1752 
1753 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1754 {
1755         dev_set_drvdata(&pdev->dev, data);
1756 }
1757 
1758 static inline const char *pci_name(const struct pci_dev *pdev)
1759 {
1760         return dev_name(&pdev->dev);
1761 }
1762 
1763 
1764 /*
1765  * Some archs don't want to expose struct resource to userland as-is
1766  * in sysfs and /proc
1767  */
1768 #ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER
1769 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1770                           const struct resource *rsrc,
1771                           resource_size_t *start, resource_size_t *end);
1772 #else
1773 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1774                 const struct resource *rsrc, resource_size_t *start,
1775                 resource_size_t *end)
1776 {
1777         *start = rsrc->start;
1778         *end = rsrc->end;
1779 }
1780 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1781 
1782 
1783 /*
1784  * The world is not perfect and supplies us with broken PCI devices.
1785  * For at least a part of these bugs we need a work-around, so both
1786  * generic (drivers/pci/quirks.c) and per-architecture code can define
1787  * fixup hooks to be called for particular buggy devices.
1788  */
1789 
1790 struct pci_fixup {
1791         u16 vendor;                     /* Or PCI_ANY_ID */
1792         u16 device;                     /* Or PCI_ANY_ID */
1793         u32 class;                      /* Or PCI_ANY_ID */
1794         unsigned int class_shift;       /* should be 0, 8, 16 */
1795         void (*hook)(struct pci_dev *dev);
1796 };
1797 
1798 enum pci_fixup_pass {
1799         pci_fixup_early,        /* Before probing BARs */
1800         pci_fixup_header,       /* After reading configuration header */
1801         pci_fixup_final,        /* Final phase of device fixups */
1802         pci_fixup_enable,       /* pci_enable_device() time */
1803         pci_fixup_resume,       /* pci_device_resume() */
1804         pci_fixup_suspend,      /* pci_device_suspend() */
1805         pci_fixup_resume_early, /* pci_device_resume_early() */
1806         pci_fixup_suspend_late, /* pci_device_suspend_late() */
1807 };
1808 
1809 /* Anonymous variables would be nice... */
1810 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1811                                   class_shift, hook)                    \
1812         static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used       \
1813         __attribute__((__section__(#section), aligned((sizeof(void *)))))    \
1814                 = { vendor, device, class, class_shift, hook };
1815 
1816 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class,            \
1817                                          class_shift, hook)             \
1818         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early,                     \
1819                 hook, vendor, device, class, class_shift, hook)
1820 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class,           \
1821                                          class_shift, hook)             \
1822         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header,                    \
1823                 hook, vendor, device, class, class_shift, hook)
1824 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class,            \
1825                                          class_shift, hook)             \
1826         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final,                     \
1827                 hook, vendor, device, class, class_shift, hook)
1828 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class,           \
1829                                          class_shift, hook)             \
1830         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable,                    \
1831                 hook, vendor, device, class, class_shift, hook)
1832 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class,           \
1833                                          class_shift, hook)             \
1834         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume,                    \
1835                 resume##hook, vendor, device, class, class_shift, hook)
1836 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class,     \
1837                                          class_shift, hook)             \
1838         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early,              \
1839                 resume_early##hook, vendor, device, class, class_shift, hook)
1840 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class,          \
1841                                          class_shift, hook)             \
1842         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend,                   \
1843                 suspend##hook, vendor, device, class, class_shift, hook)
1844 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class,     \
1845                                          class_shift, hook)             \
1846         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late,              \
1847                 suspend_late##hook, vendor, device, class, class_shift, hook)
1848 
1849 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook)                   \
1850         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early,                     \
1851                 hook, vendor, device, PCI_ANY_ID, 0, hook)
1852 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook)                  \
1853         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header,                    \
1854                 hook, vendor, device, PCI_ANY_ID, 0, hook)
1855 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook)                   \
1856         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final,                     \
1857                 hook, vendor, device, PCI_ANY_ID, 0, hook)
1858 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook)                  \
1859         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable,                    \
1860                 hook, vendor, device, PCI_ANY_ID, 0, hook)
1861 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook)                  \
1862         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume,                    \
1863                 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
1864 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook)            \
1865         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early,              \
1866                 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
1867 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook)                 \
1868         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend,                   \
1869                 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
1870 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook)            \
1871         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late,              \
1872                 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
1873 
1874 #ifdef CONFIG_PCI_QUIRKS
1875 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1876 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
1877 int pci_dev_specific_enable_acs(struct pci_dev *dev);
1878 #else
1879 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1880                                     struct pci_dev *dev) { }
1881 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1882                                                u16 acs_flags)
1883 {
1884         return -ENOTTY;
1885 }
1886 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
1887 {
1888         return -ENOTTY;
1889 }
1890 #endif
1891 
1892 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1893 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1894 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1895 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1896 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1897                                    const char *name);
1898 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1899 
1900 extern int pci_pci_problems;
1901 #define PCIPCI_FAIL             1       /* No PCI PCI DMA */
1902 #define PCIPCI_TRITON           2
1903 #define PCIPCI_NATOMA           4
1904 #define PCIPCI_VIAETBF          8
1905 #define PCIPCI_VSFX             16
1906 #define PCIPCI_ALIMAGIK         32      /* Need low latency setting */
1907 #define PCIAGP_FAIL             64      /* No PCI to AGP DMA */
1908 
1909 extern unsigned long pci_cardbus_io_size;
1910 extern unsigned long pci_cardbus_mem_size;
1911 extern u8 pci_dfl_cache_line_size;
1912 extern u8 pci_cache_line_size;
1913 
1914 extern unsigned long pci_hotplug_io_size;
1915 extern unsigned long pci_hotplug_mem_size;
1916 extern unsigned long pci_hotplug_bus_size;
1917 
1918 /* Architecture-specific versions may override these (weak) */
1919 void pcibios_disable_device(struct pci_dev *dev);
1920 void pcibios_set_master(struct pci_dev *dev);
1921 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1922                                  enum pcie_reset_state state);
1923 int pcibios_add_device(struct pci_dev *dev);
1924 void pcibios_release_device(struct pci_dev *dev);
1925 void pcibios_penalize_isa_irq(int irq, int active);
1926 int pcibios_alloc_irq(struct pci_dev *dev);
1927 void pcibios_free_irq(struct pci_dev *dev);
1928 resource_size_t pcibios_default_alignment(void);
1929 
1930 #ifdef CONFIG_HIBERNATE_CALLBACKS
1931 extern struct dev_pm_ops pcibios_pm_ops;
1932 #endif
1933 
1934 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
1935 void __init pci_mmcfg_early_init(void);
1936 void __init pci_mmcfg_late_init(void);
1937 #else
1938 static inline void pci_mmcfg_early_init(void) { }
1939 static inline void pci_mmcfg_late_init(void) { }
1940 #endif
1941 
1942 int pci_ext_cfg_avail(void);
1943 
1944 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1945 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
1946 
1947 #ifdef CONFIG_PCI_IOV
1948 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
1949 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
1950 
1951 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1952 void pci_disable_sriov(struct pci_dev *dev);
1953 int pci_iov_add_virtfn(struct pci_dev *dev, int id);
1954 void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
1955 int pci_num_vf(struct pci_dev *dev);
1956 int pci_vfs_assigned(struct pci_dev *dev);
1957 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1958 int pci_sriov_get_totalvfs(struct pci_dev *dev);
1959 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
1960 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
1961 
1962 /* Arch may override these (weak) */
1963 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
1964 int pcibios_sriov_disable(struct pci_dev *pdev);
1965 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
1966 #else
1967 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
1968 {
1969         return -ENOSYS;
1970 }
1971 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
1972 {
1973         return -ENOSYS;
1974 }
1975 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1976 { return -ENODEV; }
1977 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
1978 {
1979         return -ENOSYS;
1980 }
1981 static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
1982                                          int id) { }
1983 static inline void pci_disable_sriov(struct pci_dev *dev) { }
1984 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
1985 static inline int pci_vfs_assigned(struct pci_dev *dev)
1986 { return 0; }
1987 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
1988 { return 0; }
1989 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
1990 { return 0; }
1991 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
1992 { return 0; }
1993 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
1994 #endif
1995 
1996 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1997 void pci_hp_create_module_link(struct pci_slot *pci_slot);
1998 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1999 #endif
2000 
2001 /**
2002  * pci_pcie_cap - get the saved PCIe capability offset
2003  * @dev: PCI device
2004  *
2005  * PCIe capability offset is calculated at PCI device initialization
2006  * time and saved in the data structure. This function returns saved
2007  * PCIe capability offset. Using this instead of pci_find_capability()
2008  * reduces unnecessary search in the PCI configuration space. If you
2009  * need to calculate PCIe capability offset from raw device for some
2010  * reasons, please use pci_find_capability() instead.
2011  */
2012 static inline int pci_pcie_cap(struct pci_dev *dev)
2013 {
2014         return dev->pcie_cap;
2015 }
2016 
2017 /**
2018  * pci_is_pcie - check if the PCI device is PCI Express capable
2019  * @dev: PCI device
2020  *
2021  * Returns: true if the PCI device is PCI Express capable, false otherwise.
2022  */
2023 static inline bool pci_is_pcie(struct pci_dev *dev)
2024 {
2025         return pci_pcie_cap(dev);
2026 }
2027 
2028 /**
2029  * pcie_caps_reg - get the PCIe Capabilities Register
2030  * @dev: PCI device
2031  */
2032 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2033 {
2034         return dev->pcie_flags_reg;
2035 }
2036 
2037 /**
2038  * pci_pcie_type - get the PCIe device/port type
2039  * @dev: PCI device
2040  */
2041 static inline int pci_pcie_type(const struct pci_dev *dev)
2042 {
2043         return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2044 }
2045 
2046 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2047 {
2048         while (1) {
2049                 if (!pci_is_pcie(dev))
2050                         break;
2051                 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2052                         return dev;
2053                 if (!dev->bus->self)
2054                         break;
2055                 dev = dev->bus->self;
2056         }
2057         return NULL;
2058 }
2059 
2060 void pci_request_acs(void);
2061 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2062 bool pci_acs_path_enabled(struct pci_dev *start,
2063                           struct pci_dev *end, u16 acs_flags);
2064 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2065 
2066 #define PCI_VPD_LRDT                    0x80    /* Large Resource Data Type */
2067 #define PCI_VPD_LRDT_ID(x)              ((x) | PCI_VPD_LRDT)
2068 
2069 /* Large Resource Data Type Tag Item Names */
2070 #define PCI_VPD_LTIN_ID_STRING          0x02    /* Identifier String */
2071 #define PCI_VPD_LTIN_RO_DATA            0x10    /* Read-Only Data */
2072 #define PCI_VPD_LTIN_RW_DATA            0x11    /* Read-Write Data */
2073 
2074 #define PCI_VPD_LRDT_ID_STRING          PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2075 #define PCI_VPD_LRDT_RO_DATA            PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2076 #define PCI_VPD_LRDT_RW_DATA            PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2077 
2078 /* Small Resource Data Type Tag Item Names */
2079 #define PCI_VPD_STIN_END                0x0f    /* End */
2080 
2081 #define PCI_VPD_SRDT_END                (PCI_VPD_STIN_END << 3)
2082 
2083 #define PCI_VPD_SRDT_TIN_MASK           0x78
2084 #define PCI_VPD_SRDT_LEN_MASK           0x07
2085 #define PCI_VPD_LRDT_TIN_MASK           0x7f
2086 
2087 #define PCI_VPD_LRDT_TAG_SIZE           3
2088 #define PCI_VPD_SRDT_TAG_SIZE           1
2089 
2090 #define PCI_VPD_INFO_FLD_HDR_SIZE       3
2091 
2092 #define PCI_VPD_RO_KEYWORD_PARTNO       "PN"
2093 #define PCI_VPD_RO_KEYWORD_MFR_ID       "MN"
2094 #define PCI_VPD_RO_KEYWORD_VENDOR0      "V0"
2095 #define PCI_VPD_RO_KEYWORD_CHKSUM       "RV"
2096 
2097 /**
2098  * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
2099  * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2100  *
2101  * Returns the extracted Large Resource Data Type length.
2102  */
2103 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
2104 {
2105         return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
2106 }
2107 
2108 /**
2109  * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
2110  * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2111  *
2112  * Returns the extracted Large Resource Data Type Tag item.
2113  */
2114 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
2115 {
2116         return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
2117 }
2118 
2119 /**
2120  * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
2121  * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2122  *
2123  * Returns the extracted Small Resource Data Type length.
2124  */
2125 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
2126 {
2127         return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
2128 }
2129 
2130 /**
2131  * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
2132  * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2133  *
2134  * Returns the extracted Small Resource Data Type Tag Item.
2135  */
2136 static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
2137 {
2138         return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
2139 }
2140 
2141 /**
2142  * pci_vpd_info_field_size - Extracts the information field length
2143  * @lrdt: Pointer to the beginning of an information field header
2144  *
2145  * Returns the extracted information field length.
2146  */
2147 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
2148 {
2149         return info_field[2];
2150 }
2151 
2152 /**
2153  * pci_vpd_find_tag - Locates the Resource Data Type tag provided
2154  * @buf: Pointer to buffered vpd data
2155  * @off: The offset into the buffer at which to begin the search
2156  * @len: The length of the vpd buffer
2157  * @rdt: The Resource Data Type to search for
2158  *
2159  * Returns the index where the Resource Data Type was found or
2160  * -ENOENT otherwise.
2161  */
2162 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
2163 
2164 /**
2165  * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
2166  * @buf: Pointer to buffered vpd data
2167  * @off: The offset into the buffer at which to begin the search
2168  * @len: The length of the buffer area, relative to off, in which to search
2169  * @kw: The keyword to search for
2170  *
2171  * Returns the index where the information field keyword was found or
2172  * -ENOENT otherwise.
2173  */
2174 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2175                               unsigned int len, const char *kw);
2176 
2177 /* PCI <-> OF binding helpers */
2178 #ifdef CONFIG_OF
2179 struct device_node;
2180 struct irq_domain;
2181 void pci_set_of_node(struct pci_dev *dev);
2182 void pci_release_of_node(struct pci_dev *dev);
2183 void pci_set_bus_of_node(struct pci_bus *bus);
2184 void pci_release_bus_of_node(struct pci_bus *bus);
2185 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2186 int pci_parse_request_of_pci_ranges(struct device *dev,
2187                                     struct list_head *resources,
2188                                     struct resource **bus_range);
2189 
2190 /* Arch may override this (weak) */
2191 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2192 
2193 #else   /* CONFIG_OF */
2194 static inline void pci_set_of_node(struct pci_dev *dev) { }
2195 static inline void pci_release_of_node(struct pci_dev *dev) { }
2196 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
2197 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
2198 static inline struct irq_domain *
2199 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2200 static inline int pci_parse_request_of_pci_ranges(struct device *dev,
2201                                                   struct list_head *resources,
2202                                                   struct resource **bus_range)
2203 {
2204         return -EINVAL;
2205 }
2206 #endif  /* CONFIG_OF */
2207 
2208 static inline struct device_node *
2209 pci_device_to_OF_node(const struct pci_dev *pdev)
2210 {
2211         return pdev ? pdev->dev.of_node : NULL;
2212 }
2213 
2214 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2215 {
2216         return bus ? bus->dev.of_node : NULL;
2217 }
2218 
2219 #ifdef CONFIG_ACPI
2220 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2221 
2222 void
2223 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2224 #else
2225 static inline struct irq_domain *
2226 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2227 #endif
2228 
2229 #ifdef CONFIG_EEH
2230 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2231 {
2232         return pdev->dev.archdata.edev;
2233 }
2234 #endif
2235 
2236 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn);
2237 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2238 int pci_for_each_dma_alias(struct pci_dev *pdev,
2239                            int (*fn)(struct pci_dev *pdev,
2240                                      u16 alias, void *data), void *data);
2241 
2242 /* Helper functions for operation of device flag */
2243 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2244 {
2245         pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2246 }
2247 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2248 {
2249         pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2250 }
2251 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2252 {
2253         return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2254 }
2255 
2256 /**
2257  * pci_ari_enabled - query ARI forwarding status
2258  * @bus: the PCI bus
2259  *
2260  * Returns true if ARI forwarding is enabled.
2261  */
2262 static inline bool pci_ari_enabled(struct pci_bus *bus)
2263 {
2264         return bus->self && bus->self->ari_enabled;
2265 }
2266 
2267 /**
2268  * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2269  * @pdev: PCI device to check
2270  *
2271  * Walk upwards from @pdev and check for each encountered bridge if it's part
2272  * of a Thunderbolt controller.  Reaching the host bridge means @pdev is not
2273  * Thunderbolt-attached.  (But rather soldered to the mainboard usually.)
2274  */
2275 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2276 {
2277         struct pci_dev *parent = pdev;
2278 
2279         if (pdev->is_thunderbolt)
2280                 return true;
2281 
2282         while ((parent = pci_upstream_bridge(parent)))
2283                 if (parent->is_thunderbolt)
2284                         return true;
2285 
2286         return false;
2287 }
2288 
2289 #if defined(CONFIG_PCIEAER) || defined(CONFIG_EEH)
2290 void pci_uevent_ers(struct pci_dev *pdev, enum  pci_ers_result err_type);
2291 #endif
2292 
2293 /* Provide the legacy pci_dma_* API */
2294 #include <linux/pci-dma-compat.h>
2295 
2296 #define pci_printk(level, pdev, fmt, arg...) \
2297         dev_printk(level, &(pdev)->dev, fmt, ##arg)
2298 
2299 #define pci_emerg(pdev, fmt, arg...)    dev_emerg(&(pdev)->dev, fmt, ##arg)
2300 #define pci_alert(pdev, fmt, arg...)    dev_alert(&(pdev)->dev, fmt, ##arg)
2301 #define pci_crit(pdev, fmt, arg...)     dev_crit(&(pdev)->dev, fmt, ##arg)
2302 #define pci_err(pdev, fmt, arg...)      dev_err(&(pdev)->dev, fmt, ##arg)
2303 #define pci_warn(pdev, fmt, arg...)     dev_warn(&(pdev)->dev, fmt, ##arg)
2304 #define pci_notice(pdev, fmt, arg...)   dev_notice(&(pdev)->dev, fmt, ##arg)
2305 #define pci_info(pdev, fmt, arg...)     dev_info(&(pdev)->dev, fmt, ##arg)
2306 #define pci_dbg(pdev, fmt, arg...)      dev_dbg(&(pdev)->dev, fmt, ##arg)
2307 
2308 #endif /* LINUX_PCI_H */
2309 

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