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TOMOYO Linux Cross Reference
Linux/include/linux/pxa2xx_ssp.h

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  1 /*
  2  *  pxa2xx_ssp.h
  3  *
  4  *  Copyright (C) 2003 Russell King, All Rights Reserved.
  5  *
  6  * This program is free software; you can redistribute it and/or modify
  7  * it under the terms of the GNU General Public License version 2 as
  8  * published by the Free Software Foundation.
  9  *
 10  * This driver supports the following PXA CPU/SSP ports:-
 11  *
 12  *       PXA250     SSP
 13  *       PXA255     SSP, NSSP
 14  *       PXA26x     SSP, NSSP, ASSP
 15  *       PXA27x     SSP1, SSP2, SSP3
 16  *       PXA3xx     SSP1, SSP2, SSP3, SSP4
 17  */
 18 
 19 #ifndef __LINUX_SSP_H
 20 #define __LINUX_SSP_H
 21 
 22 #include <linux/list.h>
 23 #include <linux/io.h>
 24 #include <linux/of.h>
 25 
 26 
 27 /*
 28  * SSP Serial Port Registers
 29  * PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different.
 30  * PXA255, PXA26x and PXA27x have extra ports, registers and bits.
 31  */
 32 
 33 #define SSCR0           (0x00)  /* SSP Control Register 0 */
 34 #define SSCR1           (0x04)  /* SSP Control Register 1 */
 35 #define SSSR            (0x08)  /* SSP Status Register */
 36 #define SSITR           (0x0C)  /* SSP Interrupt Test Register */
 37 #define SSDR            (0x10)  /* SSP Data Write/Data Read Register */
 38 
 39 #define SSTO            (0x28)  /* SSP Time Out Register */
 40 #define DDS_RATE        (0x28)  /* SSP DDS Clock Rate Register (Intel Quark) */
 41 #define SSPSP           (0x2C)  /* SSP Programmable Serial Protocol */
 42 #define SSTSA           (0x30)  /* SSP Tx Timeslot Active */
 43 #define SSRSA           (0x34)  /* SSP Rx Timeslot Active */
 44 #define SSTSS           (0x38)  /* SSP Timeslot Status */
 45 #define SSACD           (0x3C)  /* SSP Audio Clock Divider */
 46 #define SSACDD          (0x40)  /* SSP Audio Clock Dither Divider */
 47 
 48 /* Common PXA2xx bits first */
 49 #define SSCR0_DSS       (0x0000000f)    /* Data Size Select (mask) */
 50 #define SSCR0_DataSize(x)  ((x) - 1)    /* Data Size Select [4..16] */
 51 #define SSCR0_FRF       (0x00000030)    /* FRame Format (mask) */
 52 #define SSCR0_Motorola  (0x0 << 4)      /* Motorola's Serial Peripheral Interface (SPI) */
 53 #define SSCR0_TI        (0x1 << 4)      /* Texas Instruments' Synchronous Serial Protocol (SSP) */
 54 #define SSCR0_National  (0x2 << 4)      /* National Microwire */
 55 #define SSCR0_ECS       (1 << 6)        /* External clock select */
 56 #define SSCR0_SSE       (1 << 7)        /* Synchronous Serial Port Enable */
 57 #define SSCR0_SCR(x)    ((x) << 8)      /* Serial Clock Rate (mask) */
 58 
 59 /* PXA27x, PXA3xx */
 60 #define SSCR0_EDSS      (1 << 20)       /* Extended data size select */
 61 #define SSCR0_NCS       (1 << 21)       /* Network clock select */
 62 #define SSCR0_RIM       (1 << 22)       /* Receive FIFO overrrun interrupt mask */
 63 #define SSCR0_TUM       (1 << 23)       /* Transmit FIFO underrun interrupt mask */
 64 #define SSCR0_FRDC      (0x07000000)    /* Frame rate divider control (mask) */
 65 #define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24)  /* Time slots per frame [1..8] */
 66 #define SSCR0_FPCKE     (1 << 29)       /* FIFO packing enable */
 67 #define SSCR0_ACS       (1 << 30)       /* Audio clock select */
 68 #define SSCR0_MOD       (1 << 31)       /* Mode (normal or network) */
 69 
 70 
 71 #define SSCR1_RIE       (1 << 0)        /* Receive FIFO Interrupt Enable */
 72 #define SSCR1_TIE       (1 << 1)        /* Transmit FIFO Interrupt Enable */
 73 #define SSCR1_LBM       (1 << 2)        /* Loop-Back Mode */
 74 #define SSCR1_SPO       (1 << 3)        /* Motorola SPI SSPSCLK polarity setting */
 75 #define SSCR1_SPH       (1 << 4)        /* Motorola SPI SSPSCLK phase setting */
 76 #define SSCR1_MWDS      (1 << 5)        /* Microwire Transmit Data Size */
 77 
 78 #define SSSR_ALT_FRM_MASK       3       /* Masks the SFRM signal number */
 79 #define SSSR_TNF        (1 << 2)        /* Transmit FIFO Not Full */
 80 #define SSSR_RNE        (1 << 3)        /* Receive FIFO Not Empty */
 81 #define SSSR_BSY        (1 << 4)        /* SSP Busy */
 82 #define SSSR_TFS        (1 << 5)        /* Transmit FIFO Service Request */
 83 #define SSSR_RFS        (1 << 6)        /* Receive FIFO Service Request */
 84 #define SSSR_ROR        (1 << 7)        /* Receive FIFO Overrun */
 85 
 86 #ifdef CONFIG_ARCH_PXA
 87 #define RX_THRESH_DFLT  8
 88 #define TX_THRESH_DFLT  8
 89 
 90 #define SSSR_TFL_MASK   (0xf << 8)      /* Transmit FIFO Level mask */
 91 #define SSSR_RFL_MASK   (0xf << 12)     /* Receive FIFO Level mask */
 92 
 93 #define SSCR1_TFT       (0x000003c0)    /* Transmit FIFO Threshold (mask) */
 94 #define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */
 95 #define SSCR1_RFT       (0x00003c00)    /* Receive FIFO Threshold (mask) */
 96 #define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */
 97 
 98 #else
 99 
100 #define RX_THRESH_DFLT  2
101 #define TX_THRESH_DFLT  2
102 
103 #define SSSR_TFL_MASK   (0x3 << 8)      /* Transmit FIFO Level mask */
104 #define SSSR_RFL_MASK   (0x3 << 12)     /* Receive FIFO Level mask */
105 
106 #define SSCR1_TFT       (0x000000c0)    /* Transmit FIFO Threshold (mask) */
107 #define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..4] */
108 #define SSCR1_RFT       (0x00000c00)    /* Receive FIFO Threshold (mask) */
109 #define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..4] */
110 #endif
111 
112 /* QUARK_X1000 SSCR0 bit definition */
113 #define QUARK_X1000_SSCR0_DSS   (0x1F)          /* Data Size Select (mask) */
114 #define QUARK_X1000_SSCR0_DataSize(x)  ((x) - 1)        /* Data Size Select [4..32] */
115 #define QUARK_X1000_SSCR0_FRF   (0x3 << 5)      /* FRame Format (mask) */
116 #define QUARK_X1000_SSCR0_Motorola      (0x0 << 5)      /* Motorola's Serial Peripheral Interface (SPI) */
117 
118 #define RX_THRESH_QUARK_X1000_DFLT      1
119 #define TX_THRESH_QUARK_X1000_DFLT      16
120 
121 #define QUARK_X1000_SSSR_TFL_MASK       (0x1F << 8)     /* Transmit FIFO Level mask */
122 #define QUARK_X1000_SSSR_RFL_MASK       (0x1F << 13)    /* Receive FIFO Level mask */
123 
124 #define QUARK_X1000_SSCR1_TFT   (0x1F << 6)     /* Transmit FIFO Threshold (mask) */
125 #define QUARK_X1000_SSCR1_TxTresh(x) (((x) - 1) << 6)   /* level [1..32] */
126 #define QUARK_X1000_SSCR1_RFT   (0x1F << 11)    /* Receive FIFO Threshold (mask) */
127 #define QUARK_X1000_SSCR1_RxTresh(x) (((x) - 1) << 11)  /* level [1..32] */
128 #define QUARK_X1000_SSCR1_STRF       (1 << 17)          /* Select FIFO or EFWR */
129 #define QUARK_X1000_SSCR1_EFWR  (1 << 16)               /* Enable FIFO Write/Read */
130 
131 /* extra bits in PXA255, PXA26x and PXA27x SSP ports */
132 #define SSCR0_TISSP             (1 << 4)        /* TI Sync Serial Protocol */
133 #define SSCR0_PSP               (3 << 4)        /* PSP - Programmable Serial Protocol */
134 #define SSCR1_TTELP             (1 << 31)       /* TXD Tristate Enable Last Phase */
135 #define SSCR1_TTE               (1 << 30)       /* TXD Tristate Enable */
136 #define SSCR1_EBCEI             (1 << 29)       /* Enable Bit Count Error interrupt */
137 #define SSCR1_SCFR              (1 << 28)       /* Slave Clock free Running */
138 #define SSCR1_ECRA              (1 << 27)       /* Enable Clock Request A */
139 #define SSCR1_ECRB              (1 << 26)       /* Enable Clock request B */
140 #define SSCR1_SCLKDIR           (1 << 25)       /* Serial Bit Rate Clock Direction */
141 #define SSCR1_SFRMDIR           (1 << 24)       /* Frame Direction */
142 #define SSCR1_RWOT              (1 << 23)       /* Receive Without Transmit */
143 #define SSCR1_TRAIL             (1 << 22)       /* Trailing Byte */
144 #define SSCR1_TSRE              (1 << 21)       /* Transmit Service Request Enable */
145 #define SSCR1_RSRE              (1 << 20)       /* Receive Service Request Enable */
146 #define SSCR1_TINTE             (1 << 19)       /* Receiver Time-out Interrupt enable */
147 #define SSCR1_PINTE             (1 << 18)       /* Peripheral Trailing Byte Interrupt Enable */
148 #define SSCR1_IFS               (1 << 16)       /* Invert Frame Signal */
149 #define SSCR1_STRF              (1 << 15)       /* Select FIFO or EFWR */
150 #define SSCR1_EFWR              (1 << 14)       /* Enable FIFO Write/Read */
151 
152 #define SSSR_BCE                (1 << 23)       /* Bit Count Error */
153 #define SSSR_CSS                (1 << 22)       /* Clock Synchronisation Status */
154 #define SSSR_TUR                (1 << 21)       /* Transmit FIFO Under Run */
155 #define SSSR_EOC                (1 << 20)       /* End Of Chain */
156 #define SSSR_TINT               (1 << 19)       /* Receiver Time-out Interrupt */
157 #define SSSR_PINT               (1 << 18)       /* Peripheral Trailing Byte Interrupt */
158 
159 
160 #define SSPSP_SCMODE(x)         ((x) << 0)      /* Serial Bit Rate Clock Mode */
161 #define SSPSP_SFRMP             (1 << 2)        /* Serial Frame Polarity */
162 #define SSPSP_ETDS              (1 << 3)        /* End of Transfer data State */
163 #define SSPSP_STRTDLY(x)        ((x) << 4)      /* Start Delay */
164 #define SSPSP_DMYSTRT(x)        ((x) << 7)      /* Dummy Start */
165 #define SSPSP_SFRMDLY(x)        ((x) << 9)      /* Serial Frame Delay */
166 #define SSPSP_SFRMWDTH(x)       ((x) << 16)     /* Serial Frame Width */
167 #define SSPSP_DMYSTOP(x)        ((x) << 23)     /* Dummy Stop */
168 #define SSPSP_FSRT              (1 << 25)       /* Frame Sync Relative Timing */
169 
170 /* PXA3xx */
171 #define SSPSP_EDMYSTRT(x)       ((x) << 26)     /* Extended Dummy Start */
172 #define SSPSP_EDMYSTOP(x)       ((x) << 28)     /* Extended Dummy Stop */
173 #define SSPSP_TIMING_MASK       (0x7f8001f0)
174 
175 #define SSACD_SCDB              (1 << 3)        /* SSPSYSCLK Divider Bypass */
176 #define SSACD_ACPS(x)           ((x) << 4)      /* Audio clock PLL select */
177 #define SSACD_ACDS(x)           ((x) << 0)      /* Audio clock divider select */
178 #define SSACD_SCDX8             (1 << 7)        /* SYSCLK division ratio select */
179 
180 /* LPSS SSP */
181 #define SSITF                   0x44            /* TX FIFO trigger level */
182 #define SSITF_TxLoThresh(x)     (((x) - 1) << 8)
183 #define SSITF_TxHiThresh(x)     ((x) - 1)
184 
185 #define SSIRF                   0x48            /* RX FIFO trigger level */
186 #define SSIRF_RxThresh(x)       ((x) - 1)
187 
188 enum pxa_ssp_type {
189         SSP_UNDEFINED = 0,
190         PXA25x_SSP,  /* pxa 210, 250, 255, 26x */
191         PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */
192         PXA27x_SSP,
193         PXA3xx_SSP,
194         PXA168_SSP,
195         PXA910_SSP,
196         CE4100_SSP,
197         QUARK_X1000_SSP,
198         LPSS_LPT_SSP, /* Keep LPSS types sorted with lpss_platforms[] */
199         LPSS_BYT_SSP,
200         LPSS_BSW_SSP,
201         LPSS_SPT_SSP,
202         LPSS_BXT_SSP,
203 };
204 
205 struct ssp_device {
206         struct platform_device *pdev;
207         struct list_head        node;
208 
209         struct clk      *clk;
210         void __iomem    *mmio_base;
211         unsigned long   phys_base;
212 
213         const char      *label;
214         int             port_id;
215         int             type;
216         int             use_count;
217         int             irq;
218         int             drcmr_rx;
219         int             drcmr_tx;
220 
221         struct device_node      *of_node;
222 };
223 
224 /**
225  * pxa_ssp_write_reg - Write to a SSP register
226  *
227  * @dev: SSP device to access
228  * @reg: Register to write to
229  * @val: Value to be written.
230  */
231 static inline void pxa_ssp_write_reg(struct ssp_device *dev, u32 reg, u32 val)
232 {
233         __raw_writel(val, dev->mmio_base + reg);
234 }
235 
236 /**
237  * pxa_ssp_read_reg - Read from a SSP register
238  *
239  * @dev: SSP device to access
240  * @reg: Register to read from
241  */
242 static inline u32 pxa_ssp_read_reg(struct ssp_device *dev, u32 reg)
243 {
244         return __raw_readl(dev->mmio_base + reg);
245 }
246 
247 #if IS_ENABLED(CONFIG_PXA_SSP)
248 struct ssp_device *pxa_ssp_request(int port, const char *label);
249 void pxa_ssp_free(struct ssp_device *);
250 struct ssp_device *pxa_ssp_request_of(const struct device_node *of_node,
251                                       const char *label);
252 #else
253 static inline struct ssp_device *pxa_ssp_request(int port, const char *label)
254 {
255         return NULL;
256 }
257 static inline struct ssp_device *pxa_ssp_request_of(const struct device_node *n,
258                                                     const char *name)
259 {
260         return NULL;
261 }
262 static inline void pxa_ssp_free(struct ssp_device *ssp) {}
263 #endif
264 
265 #endif
266 

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