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TOMOYO Linux Cross Reference
Linux/include/linux/qcom_scm.h

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  1 /* Copyright (c) 2010-2015, The Linux Foundation. All rights reserved.
  2  * Copyright (C) 2015 Linaro Ltd.
  3  *
  4  * This program is free software; you can redistribute it and/or modify
  5  * it under the terms of the GNU General Public License version 2 and
  6  * only version 2 as published by the Free Software Foundation.
  7  *
  8  * This program is distributed in the hope that it will be useful,
  9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 11  * GNU General Public License for more details.
 12  */
 13 #ifndef __QCOM_SCM_H
 14 #define __QCOM_SCM_H
 15 
 16 #include <linux/types.h>
 17 #include <linux/cpumask.h>
 18 
 19 #define QCOM_SCM_VERSION(major, minor)  (((major) << 16) | ((minor) & 0xFF))
 20 #define QCOM_SCM_CPU_PWR_DOWN_L2_ON     0x0
 21 #define QCOM_SCM_CPU_PWR_DOWN_L2_OFF    0x1
 22 #define QCOM_SCM_HDCP_MAX_REQ_CNT       5
 23 
 24 struct qcom_scm_hdcp_req {
 25         u32 addr;
 26         u32 val;
 27 };
 28 
 29 struct qcom_scm_vmperm {
 30         int vmid;
 31         int perm;
 32 };
 33 
 34 #define QCOM_SCM_VMID_HLOS       0x3
 35 #define QCOM_SCM_VMID_MSS_MSA    0xF
 36 #define QCOM_SCM_PERM_READ       0x4
 37 #define QCOM_SCM_PERM_WRITE      0x2
 38 #define QCOM_SCM_PERM_EXEC       0x1
 39 #define QCOM_SCM_PERM_RW (QCOM_SCM_PERM_READ | QCOM_SCM_PERM_WRITE)
 40 #define QCOM_SCM_PERM_RWX (QCOM_SCM_PERM_RW | QCOM_SCM_PERM_EXEC)
 41 
 42 #if IS_ENABLED(CONFIG_QCOM_SCM)
 43 extern int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
 44 extern int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus);
 45 extern bool qcom_scm_is_available(void);
 46 extern bool qcom_scm_hdcp_available(void);
 47 extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
 48                              u32 *resp);
 49 extern bool qcom_scm_pas_supported(u32 peripheral);
 50 extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
 51                                    size_t size);
 52 extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
 53                                   phys_addr_t size);
 54 extern int qcom_scm_pas_auth_and_reset(u32 peripheral);
 55 extern int qcom_scm_pas_shutdown(u32 peripheral);
 56 extern int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
 57                                unsigned int *src, struct qcom_scm_vmperm *newvm,
 58                                int dest_cnt);
 59 extern void qcom_scm_cpu_power_down(u32 flags);
 60 extern u32 qcom_scm_get_version(void);
 61 extern int qcom_scm_set_remote_state(u32 state, u32 id);
 62 extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
 63 extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);
 64 extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);
 65 extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
 66 extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
 67 #else
 68 static inline
 69 int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
 70 {
 71         return -ENODEV;
 72 }
 73 static inline
 74 int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
 75 {
 76         return -ENODEV;
 77 }
 78 static inline bool qcom_scm_is_available(void) { return false; }
 79 static inline bool qcom_scm_hdcp_available(void) { return false; }
 80 static inline int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
 81                                     u32 *resp) { return -ENODEV; }
 82 static inline bool qcom_scm_pas_supported(u32 peripheral) { return false; }
 83 static inline int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
 84                                           size_t size) { return -ENODEV; }
 85 static inline int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
 86                                          phys_addr_t size) { return -ENODEV; }
 87 static inline int
 88 qcom_scm_pas_auth_and_reset(u32 peripheral) { return -ENODEV; }
 89 static inline int qcom_scm_pas_shutdown(u32 peripheral) { return -ENODEV; }
 90 static inline void qcom_scm_cpu_power_down(u32 flags) {}
 91 static inline u32 qcom_scm_get_version(void) { return 0; }
 92 static inline u32
 93 qcom_scm_set_remote_state(u32 state,u32 id) { return -ENODEV; }
 94 static inline int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare) { return -ENODEV; }
 95 static inline int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size) { return -ENODEV; }
 96 static inline int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare) { return -ENODEV; }
 97 static inline int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val) { return -ENODEV; }
 98 static inline int qcom_scm_io_writel(phys_addr_t addr, unsigned int val) { return -ENODEV; }
 99 #endif
100 #endif
101 

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