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TOMOYO Linux Cross Reference
Linux/include/linux/spi/spi.h

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  1 /*
  2  * Copyright (C) 2005 David Brownell
  3  *
  4  * This program is free software; you can redistribute it and/or modify
  5  * it under the terms of the GNU General Public License as published by
  6  * the Free Software Foundation; either version 2 of the License, or
  7  * (at your option) any later version.
  8  *
  9  * This program is distributed in the hope that it will be useful,
 10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 12  * GNU General Public License for more details.
 13  */
 14 
 15 #ifndef __LINUX_SPI_H
 16 #define __LINUX_SPI_H
 17 
 18 #include <linux/device.h>
 19 #include <linux/mod_devicetable.h>
 20 #include <linux/slab.h>
 21 #include <linux/kthread.h>
 22 #include <linux/completion.h>
 23 #include <linux/scatterlist.h>
 24 
 25 struct dma_chan;
 26 struct property_entry;
 27 struct spi_controller;
 28 struct spi_transfer;
 29 struct spi_flash_read_message;
 30 
 31 /*
 32  * INTERFACES between SPI master-side drivers and SPI slave protocol handlers,
 33  * and SPI infrastructure.
 34  */
 35 extern struct bus_type spi_bus_type;
 36 
 37 /**
 38  * struct spi_statistics - statistics for spi transfers
 39  * @lock:          lock protecting this structure
 40  *
 41  * @messages:      number of spi-messages handled
 42  * @transfers:     number of spi_transfers handled
 43  * @errors:        number of errors during spi_transfer
 44  * @timedout:      number of timeouts during spi_transfer
 45  *
 46  * @spi_sync:      number of times spi_sync is used
 47  * @spi_sync_immediate:
 48  *                 number of times spi_sync is executed immediately
 49  *                 in calling context without queuing and scheduling
 50  * @spi_async:     number of times spi_async is used
 51  *
 52  * @bytes:         number of bytes transferred to/from device
 53  * @bytes_tx:      number of bytes sent to device
 54  * @bytes_rx:      number of bytes received from device
 55  *
 56  * @transfer_bytes_histo:
 57  *                 transfer bytes histogramm
 58  *
 59  * @transfers_split_maxsize:
 60  *                 number of transfers that have been split because of
 61  *                 maxsize limit
 62  */
 63 struct spi_statistics {
 64         spinlock_t              lock; /* lock for the whole structure */
 65 
 66         unsigned long           messages;
 67         unsigned long           transfers;
 68         unsigned long           errors;
 69         unsigned long           timedout;
 70 
 71         unsigned long           spi_sync;
 72         unsigned long           spi_sync_immediate;
 73         unsigned long           spi_async;
 74 
 75         unsigned long long      bytes;
 76         unsigned long long      bytes_rx;
 77         unsigned long long      bytes_tx;
 78 
 79 #define SPI_STATISTICS_HISTO_SIZE 17
 80         unsigned long transfer_bytes_histo[SPI_STATISTICS_HISTO_SIZE];
 81 
 82         unsigned long transfers_split_maxsize;
 83 };
 84 
 85 void spi_statistics_add_transfer_stats(struct spi_statistics *stats,
 86                                        struct spi_transfer *xfer,
 87                                        struct spi_controller *ctlr);
 88 
 89 #define SPI_STATISTICS_ADD_TO_FIELD(stats, field, count)        \
 90         do {                                                    \
 91                 unsigned long flags;                            \
 92                 spin_lock_irqsave(&(stats)->lock, flags);       \
 93                 (stats)->field += count;                        \
 94                 spin_unlock_irqrestore(&(stats)->lock, flags);  \
 95         } while (0)
 96 
 97 #define SPI_STATISTICS_INCREMENT_FIELD(stats, field)    \
 98         SPI_STATISTICS_ADD_TO_FIELD(stats, field, 1)
 99 
100 /**
101  * struct spi_device - Controller side proxy for an SPI slave device
102  * @dev: Driver model representation of the device.
103  * @controller: SPI controller used with the device.
104  * @master: Copy of controller, for backwards compatibility.
105  * @max_speed_hz: Maximum clock rate to be used with this chip
106  *      (on this board); may be changed by the device's driver.
107  *      The spi_transfer.speed_hz can override this for each transfer.
108  * @chip_select: Chipselect, distinguishing chips handled by @controller.
109  * @mode: The spi mode defines how data is clocked out and in.
110  *      This may be changed by the device's driver.
111  *      The "active low" default for chipselect mode can be overridden
112  *      (by specifying SPI_CS_HIGH) as can the "MSB first" default for
113  *      each word in a transfer (by specifying SPI_LSB_FIRST).
114  * @bits_per_word: Data transfers involve one or more words; word sizes
115  *      like eight or 12 bits are common.  In-memory wordsizes are
116  *      powers of two bytes (e.g. 20 bit samples use 32 bits).
117  *      This may be changed by the device's driver, or left at the
118  *      default (0) indicating protocol words are eight bit bytes.
119  *      The spi_transfer.bits_per_word can override this for each transfer.
120  * @irq: Negative, or the number passed to request_irq() to receive
121  *      interrupts from this device.
122  * @controller_state: Controller's runtime state
123  * @controller_data: Board-specific definitions for controller, such as
124  *      FIFO initialization parameters; from board_info.controller_data
125  * @modalias: Name of the driver to use with this device, or an alias
126  *      for that name.  This appears in the sysfs "modalias" attribute
127  *      for driver coldplugging, and in uevents used for hotplugging
128  * @cs_gpio: gpio number of the chipselect line (optional, -ENOENT when
129  *      not using a GPIO line)
130  *
131  * @statistics: statistics for the spi_device
132  *
133  * A @spi_device is used to interchange data between an SPI slave
134  * (usually a discrete chip) and CPU memory.
135  *
136  * In @dev, the platform_data is used to hold information about this
137  * device that's meaningful to the device's protocol driver, but not
138  * to its controller.  One example might be an identifier for a chip
139  * variant with slightly different functionality; another might be
140  * information about how this particular board wires the chip's pins.
141  */
142 struct spi_device {
143         struct device           dev;
144         struct spi_controller   *controller;
145         struct spi_controller   *master;        /* compatibility layer */
146         u32                     max_speed_hz;
147         u8                      chip_select;
148         u8                      bits_per_word;
149         u16                     mode;
150 #define SPI_CPHA        0x01                    /* clock phase */
151 #define SPI_CPOL        0x02                    /* clock polarity */
152 #define SPI_MODE_0      (0|0)                   /* (original MicroWire) */
153 #define SPI_MODE_1      (0|SPI_CPHA)
154 #define SPI_MODE_2      (SPI_CPOL|0)
155 #define SPI_MODE_3      (SPI_CPOL|SPI_CPHA)
156 #define SPI_CS_HIGH     0x04                    /* chipselect active high? */
157 #define SPI_LSB_FIRST   0x08                    /* per-word bits-on-wire */
158 #define SPI_3WIRE       0x10                    /* SI/SO signals shared */
159 #define SPI_LOOP        0x20                    /* loopback mode */
160 #define SPI_NO_CS       0x40                    /* 1 dev/bus, no chipselect */
161 #define SPI_READY       0x80                    /* slave pulls low to pause */
162 #define SPI_TX_DUAL     0x100                   /* transmit with 2 wires */
163 #define SPI_TX_QUAD     0x200                   /* transmit with 4 wires */
164 #define SPI_RX_DUAL     0x400                   /* receive with 2 wires */
165 #define SPI_RX_QUAD     0x800                   /* receive with 4 wires */
166         int                     irq;
167         void                    *controller_state;
168         void                    *controller_data;
169         char                    modalias[SPI_NAME_SIZE];
170         int                     cs_gpio;        /* chip select gpio */
171 
172         /* the statistics */
173         struct spi_statistics   statistics;
174 
175         /*
176          * likely need more hooks for more protocol options affecting how
177          * the controller talks to each chip, like:
178          *  - memory packing (12 bit samples into low bits, others zeroed)
179          *  - priority
180          *  - drop chipselect after each word
181          *  - chipselect delays
182          *  - ...
183          */
184 };
185 
186 static inline struct spi_device *to_spi_device(struct device *dev)
187 {
188         return dev ? container_of(dev, struct spi_device, dev) : NULL;
189 }
190 
191 /* most drivers won't need to care about device refcounting */
192 static inline struct spi_device *spi_dev_get(struct spi_device *spi)
193 {
194         return (spi && get_device(&spi->dev)) ? spi : NULL;
195 }
196 
197 static inline void spi_dev_put(struct spi_device *spi)
198 {
199         if (spi)
200                 put_device(&spi->dev);
201 }
202 
203 /* ctldata is for the bus_controller driver's runtime state */
204 static inline void *spi_get_ctldata(struct spi_device *spi)
205 {
206         return spi->controller_state;
207 }
208 
209 static inline void spi_set_ctldata(struct spi_device *spi, void *state)
210 {
211         spi->controller_state = state;
212 }
213 
214 /* device driver data */
215 
216 static inline void spi_set_drvdata(struct spi_device *spi, void *data)
217 {
218         dev_set_drvdata(&spi->dev, data);
219 }
220 
221 static inline void *spi_get_drvdata(struct spi_device *spi)
222 {
223         return dev_get_drvdata(&spi->dev);
224 }
225 
226 struct spi_message;
227 struct spi_transfer;
228 
229 /**
230  * struct spi_driver - Host side "protocol" driver
231  * @id_table: List of SPI devices supported by this driver
232  * @probe: Binds this driver to the spi device.  Drivers can verify
233  *      that the device is actually present, and may need to configure
234  *      characteristics (such as bits_per_word) which weren't needed for
235  *      the initial configuration done during system setup.
236  * @remove: Unbinds this driver from the spi device
237  * @shutdown: Standard shutdown callback used during system state
238  *      transitions such as powerdown/halt and kexec
239  * @driver: SPI device drivers should initialize the name and owner
240  *      field of this structure.
241  *
242  * This represents the kind of device driver that uses SPI messages to
243  * interact with the hardware at the other end of a SPI link.  It's called
244  * a "protocol" driver because it works through messages rather than talking
245  * directly to SPI hardware (which is what the underlying SPI controller
246  * driver does to pass those messages).  These protocols are defined in the
247  * specification for the device(s) supported by the driver.
248  *
249  * As a rule, those device protocols represent the lowest level interface
250  * supported by a driver, and it will support upper level interfaces too.
251  * Examples of such upper levels include frameworks like MTD, networking,
252  * MMC, RTC, filesystem character device nodes, and hardware monitoring.
253  */
254 struct spi_driver {
255         const struct spi_device_id *id_table;
256         int                     (*probe)(struct spi_device *spi);
257         int                     (*remove)(struct spi_device *spi);
258         void                    (*shutdown)(struct spi_device *spi);
259         struct device_driver    driver;
260 };
261 
262 static inline struct spi_driver *to_spi_driver(struct device_driver *drv)
263 {
264         return drv ? container_of(drv, struct spi_driver, driver) : NULL;
265 }
266 
267 extern int __spi_register_driver(struct module *owner, struct spi_driver *sdrv);
268 
269 /**
270  * spi_unregister_driver - reverse effect of spi_register_driver
271  * @sdrv: the driver to unregister
272  * Context: can sleep
273  */
274 static inline void spi_unregister_driver(struct spi_driver *sdrv)
275 {
276         if (sdrv)
277                 driver_unregister(&sdrv->driver);
278 }
279 
280 /* use a define to avoid include chaining to get THIS_MODULE */
281 #define spi_register_driver(driver) \
282         __spi_register_driver(THIS_MODULE, driver)
283 
284 /**
285  * module_spi_driver() - Helper macro for registering a SPI driver
286  * @__spi_driver: spi_driver struct
287  *
288  * Helper macro for SPI drivers which do not do anything special in module
289  * init/exit. This eliminates a lot of boilerplate. Each module may only
290  * use this macro once, and calling it replaces module_init() and module_exit()
291  */
292 #define module_spi_driver(__spi_driver) \
293         module_driver(__spi_driver, spi_register_driver, \
294                         spi_unregister_driver)
295 
296 /**
297  * struct spi_controller - interface to SPI master or slave controller
298  * @dev: device interface to this driver
299  * @list: link with the global spi_controller list
300  * @bus_num: board-specific (and often SOC-specific) identifier for a
301  *      given SPI controller.
302  * @num_chipselect: chipselects are used to distinguish individual
303  *      SPI slaves, and are numbered from zero to num_chipselects.
304  *      each slave has a chipselect signal, but it's common that not
305  *      every chipselect is connected to a slave.
306  * @dma_alignment: SPI controller constraint on DMA buffers alignment.
307  * @mode_bits: flags understood by this controller driver
308  * @bits_per_word_mask: A mask indicating which values of bits_per_word are
309  *      supported by the driver. Bit n indicates that a bits_per_word n+1 is
310  *      supported. If set, the SPI core will reject any transfer with an
311  *      unsupported bits_per_word. If not set, this value is simply ignored,
312  *      and it's up to the individual driver to perform any validation.
313  * @min_speed_hz: Lowest supported transfer speed
314  * @max_speed_hz: Highest supported transfer speed
315  * @flags: other constraints relevant to this driver
316  * @slave: indicates that this is an SPI slave controller
317  * @max_transfer_size: function that returns the max transfer size for
318  *      a &spi_device; may be %NULL, so the default %SIZE_MAX will be used.
319  * @max_message_size: function that returns the max message size for
320  *      a &spi_device; may be %NULL, so the default %SIZE_MAX will be used.
321  * @io_mutex: mutex for physical bus access
322  * @bus_lock_spinlock: spinlock for SPI bus locking
323  * @bus_lock_mutex: mutex for exclusion of multiple callers
324  * @bus_lock_flag: indicates that the SPI bus is locked for exclusive use
325  * @setup: updates the device mode and clocking records used by a
326  *      device's SPI controller; protocol code may call this.  This
327  *      must fail if an unrecognized or unsupported mode is requested.
328  *      It's always safe to call this unless transfers are pending on
329  *      the device whose settings are being modified.
330  * @transfer: adds a message to the controller's transfer queue.
331  * @cleanup: frees controller-specific state
332  * @can_dma: determine whether this controller supports DMA
333  * @queued: whether this controller is providing an internal message queue
334  * @kworker: thread struct for message pump
335  * @kworker_task: pointer to task for message pump kworker thread
336  * @pump_messages: work struct for scheduling work to the message pump
337  * @queue_lock: spinlock to syncronise access to message queue
338  * @queue: message queue
339  * @idling: the device is entering idle state
340  * @cur_msg: the currently in-flight message
341  * @cur_msg_prepared: spi_prepare_message was called for the currently
342  *                    in-flight message
343  * @cur_msg_mapped: message has been mapped for DMA
344  * @xfer_completion: used by core transfer_one_message()
345  * @busy: message pump is busy
346  * @running: message pump is running
347  * @rt: whether this queue is set to run as a realtime task
348  * @auto_runtime_pm: the core should ensure a runtime PM reference is held
349  *                   while the hardware is prepared, using the parent
350  *                   device for the spidev
351  * @max_dma_len: Maximum length of a DMA transfer for the device.
352  * @prepare_transfer_hardware: a message will soon arrive from the queue
353  *      so the subsystem requests the driver to prepare the transfer hardware
354  *      by issuing this call
355  * @transfer_one_message: the subsystem calls the driver to transfer a single
356  *      message while queuing transfers that arrive in the meantime. When the
357  *      driver is finished with this message, it must call
358  *      spi_finalize_current_message() so the subsystem can issue the next
359  *      message
360  * @unprepare_transfer_hardware: there are currently no more messages on the
361  *      queue so the subsystem notifies the driver that it may relax the
362  *      hardware by issuing this call
363  * @set_cs: set the logic level of the chip select line.  May be called
364  *          from interrupt context.
365  * @prepare_message: set up the controller to transfer a single message,
366  *                   for example doing DMA mapping.  Called from threaded
367  *                   context.
368  * @transfer_one: transfer a single spi_transfer.
369  *                  - return 0 if the transfer is finished,
370  *                  - return 1 if the transfer is still in progress. When
371  *                    the driver is finished with this transfer it must
372  *                    call spi_finalize_current_transfer() so the subsystem
373  *                    can issue the next transfer. Note: transfer_one and
374  *                    transfer_one_message are mutually exclusive; when both
375  *                    are set, the generic subsystem does not call your
376  *                    transfer_one callback.
377  * @handle_err: the subsystem calls the driver to handle an error that occurs
378  *              in the generic implementation of transfer_one_message().
379  * @unprepare_message: undo any work done by prepare_message().
380  * @slave_abort: abort the ongoing transfer request on an SPI slave controller
381  * @spi_flash_read: to support spi-controller hardwares that provide
382  *                  accelerated interface to read from flash devices.
383  * @spi_flash_can_dma: analogous to can_dma() interface, but for
384  *                     controllers implementing spi_flash_read.
385  * @flash_read_supported: spi device supports flash read
386  * @cs_gpios: Array of GPIOs to use as chip select lines; one per CS
387  *      number. Any individual value may be -ENOENT for CS lines that
388  *      are not GPIOs (driven by the SPI controller itself).
389  * @statistics: statistics for the spi_controller
390  * @dma_tx: DMA transmit channel
391  * @dma_rx: DMA receive channel
392  * @dummy_rx: dummy receive buffer for full-duplex devices
393  * @dummy_tx: dummy transmit buffer for full-duplex devices
394  * @fw_translate_cs: If the boot firmware uses different numbering scheme
395  *      what Linux expects, this optional hook can be used to translate
396  *      between the two.
397  *
398  * Each SPI controller can communicate with one or more @spi_device
399  * children.  These make a small bus, sharing MOSI, MISO and SCK signals
400  * but not chip select signals.  Each device may be configured to use a
401  * different clock rate, since those shared signals are ignored unless
402  * the chip is selected.
403  *
404  * The driver for an SPI controller manages access to those devices through
405  * a queue of spi_message transactions, copying data between CPU memory and
406  * an SPI slave device.  For each such message it queues, it calls the
407  * message's completion function when the transaction completes.
408  */
409 struct spi_controller {
410         struct device   dev;
411 
412         struct list_head list;
413 
414         /* other than negative (== assign one dynamically), bus_num is fully
415          * board-specific.  usually that simplifies to being SOC-specific.
416          * example:  one SOC has three SPI controllers, numbered 0..2,
417          * and one board's schematics might show it using SPI-2.  software
418          * would normally use bus_num=2 for that controller.
419          */
420         s16                     bus_num;
421 
422         /* chipselects will be integral to many controllers; some others
423          * might use board-specific GPIOs.
424          */
425         u16                     num_chipselect;
426 
427         /* some SPI controllers pose alignment requirements on DMAable
428          * buffers; let protocol drivers know about these requirements.
429          */
430         u16                     dma_alignment;
431 
432         /* spi_device.mode flags understood by this controller driver */
433         u16                     mode_bits;
434 
435         /* bitmask of supported bits_per_word for transfers */
436         u32                     bits_per_word_mask;
437 #define SPI_BPW_MASK(bits) BIT((bits) - 1)
438 #define SPI_BIT_MASK(bits) (((bits) == 32) ? ~0U : (BIT(bits) - 1))
439 #define SPI_BPW_RANGE_MASK(min, max) (SPI_BIT_MASK(max) - SPI_BIT_MASK(min - 1))
440 
441         /* limits on transfer speed */
442         u32                     min_speed_hz;
443         u32                     max_speed_hz;
444 
445         /* other constraints relevant to this driver */
446         u16                     flags;
447 #define SPI_CONTROLLER_HALF_DUPLEX      BIT(0)  /* can't do full duplex */
448 #define SPI_CONTROLLER_NO_RX            BIT(1)  /* can't do buffer read */
449 #define SPI_CONTROLLER_NO_TX            BIT(2)  /* can't do buffer write */
450 #define SPI_CONTROLLER_MUST_RX          BIT(3)  /* requires rx */
451 #define SPI_CONTROLLER_MUST_TX          BIT(4)  /* requires tx */
452 
453 #define SPI_MASTER_GPIO_SS              BIT(5)  /* GPIO CS must select slave */
454 
455         /* flag indicating this is an SPI slave controller */
456         bool                    slave;
457 
458         /*
459          * on some hardware transfer / message size may be constrained
460          * the limit may depend on device transfer settings
461          */
462         size_t (*max_transfer_size)(struct spi_device *spi);
463         size_t (*max_message_size)(struct spi_device *spi);
464 
465         /* I/O mutex */
466         struct mutex            io_mutex;
467 
468         /* lock and mutex for SPI bus locking */
469         spinlock_t              bus_lock_spinlock;
470         struct mutex            bus_lock_mutex;
471 
472         /* flag indicating that the SPI bus is locked for exclusive use */
473         bool                    bus_lock_flag;
474 
475         /* Setup mode and clock, etc (spi driver may call many times).
476          *
477          * IMPORTANT:  this may be called when transfers to another
478          * device are active.  DO NOT UPDATE SHARED REGISTERS in ways
479          * which could break those transfers.
480          */
481         int                     (*setup)(struct spi_device *spi);
482 
483         /* bidirectional bulk transfers
484          *
485          * + The transfer() method may not sleep; its main role is
486          *   just to add the message to the queue.
487          * + For now there's no remove-from-queue operation, or
488          *   any other request management
489          * + To a given spi_device, message queueing is pure fifo
490          *
491          * + The controller's main job is to process its message queue,
492          *   selecting a chip (for masters), then transferring data
493          * + If there are multiple spi_device children, the i/o queue
494          *   arbitration algorithm is unspecified (round robin, fifo,
495          *   priority, reservations, preemption, etc)
496          *
497          * + Chipselect stays active during the entire message
498          *   (unless modified by spi_transfer.cs_change != 0).
499          * + The message transfers use clock and SPI mode parameters
500          *   previously established by setup() for this device
501          */
502         int                     (*transfer)(struct spi_device *spi,
503                                                 struct spi_message *mesg);
504 
505         /* called on release() to free memory provided by spi_controller */
506         void                    (*cleanup)(struct spi_device *spi);
507 
508         /*
509          * Used to enable core support for DMA handling, if can_dma()
510          * exists and returns true then the transfer will be mapped
511          * prior to transfer_one() being called.  The driver should
512          * not modify or store xfer and dma_tx and dma_rx must be set
513          * while the device is prepared.
514          */
515         bool                    (*can_dma)(struct spi_controller *ctlr,
516                                            struct spi_device *spi,
517                                            struct spi_transfer *xfer);
518 
519         /*
520          * These hooks are for drivers that want to use the generic
521          * controller transfer queueing mechanism. If these are used, the
522          * transfer() function above must NOT be specified by the driver.
523          * Over time we expect SPI drivers to be phased over to this API.
524          */
525         bool                            queued;
526         struct kthread_worker           kworker;
527         struct task_struct              *kworker_task;
528         struct kthread_work             pump_messages;
529         spinlock_t                      queue_lock;
530         struct list_head                queue;
531         struct spi_message              *cur_msg;
532         bool                            idling;
533         bool                            busy;
534         bool                            running;
535         bool                            rt;
536         bool                            auto_runtime_pm;
537         bool                            cur_msg_prepared;
538         bool                            cur_msg_mapped;
539         struct completion               xfer_completion;
540         size_t                          max_dma_len;
541 
542         int (*prepare_transfer_hardware)(struct spi_controller *ctlr);
543         int (*transfer_one_message)(struct spi_controller *ctlr,
544                                     struct spi_message *mesg);
545         int (*unprepare_transfer_hardware)(struct spi_controller *ctlr);
546         int (*prepare_message)(struct spi_controller *ctlr,
547                                struct spi_message *message);
548         int (*unprepare_message)(struct spi_controller *ctlr,
549                                  struct spi_message *message);
550         int (*slave_abort)(struct spi_controller *ctlr);
551         int (*spi_flash_read)(struct  spi_device *spi,
552                               struct spi_flash_read_message *msg);
553         bool (*spi_flash_can_dma)(struct spi_device *spi,
554                                   struct spi_flash_read_message *msg);
555         bool (*flash_read_supported)(struct spi_device *spi);
556 
557         /*
558          * These hooks are for drivers that use a generic implementation
559          * of transfer_one_message() provied by the core.
560          */
561         void (*set_cs)(struct spi_device *spi, bool enable);
562         int (*transfer_one)(struct spi_controller *ctlr, struct spi_device *spi,
563                             struct spi_transfer *transfer);
564         void (*handle_err)(struct spi_controller *ctlr,
565                            struct spi_message *message);
566 
567         /* gpio chip select */
568         int                     *cs_gpios;
569 
570         /* statistics */
571         struct spi_statistics   statistics;
572 
573         /* DMA channels for use with core dmaengine helpers */
574         struct dma_chan         *dma_tx;
575         struct dma_chan         *dma_rx;
576 
577         /* dummy data for full duplex devices */
578         void                    *dummy_rx;
579         void                    *dummy_tx;
580 
581         int (*fw_translate_cs)(struct spi_controller *ctlr, unsigned cs);
582 };
583 
584 static inline void *spi_controller_get_devdata(struct spi_controller *ctlr)
585 {
586         return dev_get_drvdata(&ctlr->dev);
587 }
588 
589 static inline void spi_controller_set_devdata(struct spi_controller *ctlr,
590                                               void *data)
591 {
592         dev_set_drvdata(&ctlr->dev, data);
593 }
594 
595 static inline struct spi_controller *spi_controller_get(struct spi_controller *ctlr)
596 {
597         if (!ctlr || !get_device(&ctlr->dev))
598                 return NULL;
599         return ctlr;
600 }
601 
602 static inline void spi_controller_put(struct spi_controller *ctlr)
603 {
604         if (ctlr)
605                 put_device(&ctlr->dev);
606 }
607 
608 static inline bool spi_controller_is_slave(struct spi_controller *ctlr)
609 {
610         return IS_ENABLED(CONFIG_SPI_SLAVE) && ctlr->slave;
611 }
612 
613 /* PM calls that need to be issued by the driver */
614 extern int spi_controller_suspend(struct spi_controller *ctlr);
615 extern int spi_controller_resume(struct spi_controller *ctlr);
616 
617 /* Calls the driver make to interact with the message queue */
618 extern struct spi_message *spi_get_next_queued_message(struct spi_controller *ctlr);
619 extern void spi_finalize_current_message(struct spi_controller *ctlr);
620 extern void spi_finalize_current_transfer(struct spi_controller *ctlr);
621 
622 /* the spi driver core manages memory for the spi_controller classdev */
623 extern struct spi_controller *__spi_alloc_controller(struct device *host,
624                                                 unsigned int size, bool slave);
625 
626 static inline struct spi_controller *spi_alloc_master(struct device *host,
627                                                       unsigned int size)
628 {
629         return __spi_alloc_controller(host, size, false);
630 }
631 
632 static inline struct spi_controller *spi_alloc_slave(struct device *host,
633                                                      unsigned int size)
634 {
635         if (!IS_ENABLED(CONFIG_SPI_SLAVE))
636                 return NULL;
637 
638         return __spi_alloc_controller(host, size, true);
639 }
640 
641 extern int spi_register_controller(struct spi_controller *ctlr);
642 extern int devm_spi_register_controller(struct device *dev,
643                                         struct spi_controller *ctlr);
644 extern void spi_unregister_controller(struct spi_controller *ctlr);
645 
646 extern struct spi_controller *spi_busnum_to_master(u16 busnum);
647 
648 /*
649  * SPI resource management while processing a SPI message
650  */
651 
652 typedef void (*spi_res_release_t)(struct spi_controller *ctlr,
653                                   struct spi_message *msg,
654                                   void *res);
655 
656 /**
657  * struct spi_res - spi resource management structure
658  * @entry:   list entry
659  * @release: release code called prior to freeing this resource
660  * @data:    extra data allocated for the specific use-case
661  *
662  * this is based on ideas from devres, but focused on life-cycle
663  * management during spi_message processing
664  */
665 struct spi_res {
666         struct list_head        entry;
667         spi_res_release_t       release;
668         unsigned long long      data[]; /* guarantee ull alignment */
669 };
670 
671 extern void *spi_res_alloc(struct spi_device *spi,
672                            spi_res_release_t release,
673                            size_t size, gfp_t gfp);
674 extern void spi_res_add(struct spi_message *message, void *res);
675 extern void spi_res_free(void *res);
676 
677 extern void spi_res_release(struct spi_controller *ctlr,
678                             struct spi_message *message);
679 
680 /*---------------------------------------------------------------------------*/
681 
682 /*
683  * I/O INTERFACE between SPI controller and protocol drivers
684  *
685  * Protocol drivers use a queue of spi_messages, each transferring data
686  * between the controller and memory buffers.
687  *
688  * The spi_messages themselves consist of a series of read+write transfer
689  * segments.  Those segments always read the same number of bits as they
690  * write; but one or the other is easily ignored by passing a null buffer
691  * pointer.  (This is unlike most types of I/O API, because SPI hardware
692  * is full duplex.)
693  *
694  * NOTE:  Allocation of spi_transfer and spi_message memory is entirely
695  * up to the protocol driver, which guarantees the integrity of both (as
696  * well as the data buffers) for as long as the message is queued.
697  */
698 
699 /**
700  * struct spi_transfer - a read/write buffer pair
701  * @tx_buf: data to be written (dma-safe memory), or NULL
702  * @rx_buf: data to be read (dma-safe memory), or NULL
703  * @tx_dma: DMA address of tx_buf, if @spi_message.is_dma_mapped
704  * @rx_dma: DMA address of rx_buf, if @spi_message.is_dma_mapped
705  * @tx_nbits: number of bits used for writing. If 0 the default
706  *      (SPI_NBITS_SINGLE) is used.
707  * @rx_nbits: number of bits used for reading. If 0 the default
708  *      (SPI_NBITS_SINGLE) is used.
709  * @len: size of rx and tx buffers (in bytes)
710  * @speed_hz: Select a speed other than the device default for this
711  *      transfer. If 0 the default (from @spi_device) is used.
712  * @bits_per_word: select a bits_per_word other than the device default
713  *      for this transfer. If 0 the default (from @spi_device) is used.
714  * @cs_change: affects chipselect after this transfer completes
715  * @delay_usecs: microseconds to delay after this transfer before
716  *      (optionally) changing the chipselect status, then starting
717  *      the next transfer or completing this @spi_message.
718  * @transfer_list: transfers are sequenced through @spi_message.transfers
719  * @tx_sg: Scatterlist for transmit, currently not for client use
720  * @rx_sg: Scatterlist for receive, currently not for client use
721  *
722  * SPI transfers always write the same number of bytes as they read.
723  * Protocol drivers should always provide @rx_buf and/or @tx_buf.
724  * In some cases, they may also want to provide DMA addresses for
725  * the data being transferred; that may reduce overhead, when the
726  * underlying driver uses dma.
727  *
728  * If the transmit buffer is null, zeroes will be shifted out
729  * while filling @rx_buf.  If the receive buffer is null, the data
730  * shifted in will be discarded.  Only "len" bytes shift out (or in).
731  * It's an error to try to shift out a partial word.  (For example, by
732  * shifting out three bytes with word size of sixteen or twenty bits;
733  * the former uses two bytes per word, the latter uses four bytes.)
734  *
735  * In-memory data values are always in native CPU byte order, translated
736  * from the wire byte order (big-endian except with SPI_LSB_FIRST).  So
737  * for example when bits_per_word is sixteen, buffers are 2N bytes long
738  * (@len = 2N) and hold N sixteen bit words in CPU byte order.
739  *
740  * When the word size of the SPI transfer is not a power-of-two multiple
741  * of eight bits, those in-memory words include extra bits.  In-memory
742  * words are always seen by protocol drivers as right-justified, so the
743  * undefined (rx) or unused (tx) bits are always the most significant bits.
744  *
745  * All SPI transfers start with the relevant chipselect active.  Normally
746  * it stays selected until after the last transfer in a message.  Drivers
747  * can affect the chipselect signal using cs_change.
748  *
749  * (i) If the transfer isn't the last one in the message, this flag is
750  * used to make the chipselect briefly go inactive in the middle of the
751  * message.  Toggling chipselect in this way may be needed to terminate
752  * a chip command, letting a single spi_message perform all of group of
753  * chip transactions together.
754  *
755  * (ii) When the transfer is the last one in the message, the chip may
756  * stay selected until the next transfer.  On multi-device SPI busses
757  * with nothing blocking messages going to other devices, this is just
758  * a performance hint; starting a message to another device deselects
759  * this one.  But in other cases, this can be used to ensure correctness.
760  * Some devices need protocol transactions to be built from a series of
761  * spi_message submissions, where the content of one message is determined
762  * by the results of previous messages and where the whole transaction
763  * ends when the chipselect goes intactive.
764  *
765  * When SPI can transfer in 1x,2x or 4x. It can get this transfer information
766  * from device through @tx_nbits and @rx_nbits. In Bi-direction, these
767  * two should both be set. User can set transfer mode with SPI_NBITS_SINGLE(1x)
768  * SPI_NBITS_DUAL(2x) and SPI_NBITS_QUAD(4x) to support these three transfer.
769  *
770  * The code that submits an spi_message (and its spi_transfers)
771  * to the lower layers is responsible for managing its memory.
772  * Zero-initialize every field you don't set up explicitly, to
773  * insulate against future API updates.  After you submit a message
774  * and its transfers, ignore them until its completion callback.
775  */
776 struct spi_transfer {
777         /* it's ok if tx_buf == rx_buf (right?)
778          * for MicroWire, one buffer must be null
779          * buffers must work with dma_*map_single() calls, unless
780          *   spi_message.is_dma_mapped reports a pre-existing mapping
781          */
782         const void      *tx_buf;
783         void            *rx_buf;
784         unsigned        len;
785 
786         dma_addr_t      tx_dma;
787         dma_addr_t      rx_dma;
788         struct sg_table tx_sg;
789         struct sg_table rx_sg;
790 
791         unsigned        cs_change:1;
792         unsigned        tx_nbits:3;
793         unsigned        rx_nbits:3;
794 #define SPI_NBITS_SINGLE        0x01 /* 1bit transfer */
795 #define SPI_NBITS_DUAL          0x02 /* 2bits transfer */
796 #define SPI_NBITS_QUAD          0x04 /* 4bits transfer */
797         u8              bits_per_word;
798         u16             delay_usecs;
799         u32             speed_hz;
800 
801         struct list_head transfer_list;
802 };
803 
804 /**
805  * struct spi_message - one multi-segment SPI transaction
806  * @transfers: list of transfer segments in this transaction
807  * @spi: SPI device to which the transaction is queued
808  * @is_dma_mapped: if true, the caller provided both dma and cpu virtual
809  *      addresses for each transfer buffer
810  * @complete: called to report transaction completions
811  * @context: the argument to complete() when it's called
812  * @frame_length: the total number of bytes in the message
813  * @actual_length: the total number of bytes that were transferred in all
814  *      successful segments
815  * @status: zero for success, else negative errno
816  * @queue: for use by whichever driver currently owns the message
817  * @state: for use by whichever driver currently owns the message
818  * @resources: for resource management when the spi message is processed
819  *
820  * A @spi_message is used to execute an atomic sequence of data transfers,
821  * each represented by a struct spi_transfer.  The sequence is "atomic"
822  * in the sense that no other spi_message may use that SPI bus until that
823  * sequence completes.  On some systems, many such sequences can execute as
824  * as single programmed DMA transfer.  On all systems, these messages are
825  * queued, and might complete after transactions to other devices.  Messages
826  * sent to a given spi_device are always executed in FIFO order.
827  *
828  * The code that submits an spi_message (and its spi_transfers)
829  * to the lower layers is responsible for managing its memory.
830  * Zero-initialize every field you don't set up explicitly, to
831  * insulate against future API updates.  After you submit a message
832  * and its transfers, ignore them until its completion callback.
833  */
834 struct spi_message {
835         struct list_head        transfers;
836 
837         struct spi_device       *spi;
838 
839         unsigned                is_dma_mapped:1;
840 
841         /* REVISIT:  we might want a flag affecting the behavior of the
842          * last transfer ... allowing things like "read 16 bit length L"
843          * immediately followed by "read L bytes".  Basically imposing
844          * a specific message scheduling algorithm.
845          *
846          * Some controller drivers (message-at-a-time queue processing)
847          * could provide that as their default scheduling algorithm.  But
848          * others (with multi-message pipelines) could need a flag to
849          * tell them about such special cases.
850          */
851 
852         /* completion is reported through a callback */
853         void                    (*complete)(void *context);
854         void                    *context;
855         unsigned                frame_length;
856         unsigned                actual_length;
857         int                     status;
858 
859         /* for optional use by whatever driver currently owns the
860          * spi_message ...  between calls to spi_async and then later
861          * complete(), that's the spi_controller controller driver.
862          */
863         struct list_head        queue;
864         void                    *state;
865 
866         /* list of spi_res reources when the spi message is processed */
867         struct list_head        resources;
868 };
869 
870 static inline void spi_message_init_no_memset(struct spi_message *m)
871 {
872         INIT_LIST_HEAD(&m->transfers);
873         INIT_LIST_HEAD(&m->resources);
874 }
875 
876 static inline void spi_message_init(struct spi_message *m)
877 {
878         memset(m, 0, sizeof *m);
879         spi_message_init_no_memset(m);
880 }
881 
882 static inline void
883 spi_message_add_tail(struct spi_transfer *t, struct spi_message *m)
884 {
885         list_add_tail(&t->transfer_list, &m->transfers);
886 }
887 
888 static inline void
889 spi_transfer_del(struct spi_transfer *t)
890 {
891         list_del(&t->transfer_list);
892 }
893 
894 /**
895  * spi_message_init_with_transfers - Initialize spi_message and append transfers
896  * @m: spi_message to be initialized
897  * @xfers: An array of spi transfers
898  * @num_xfers: Number of items in the xfer array
899  *
900  * This function initializes the given spi_message and adds each spi_transfer in
901  * the given array to the message.
902  */
903 static inline void
904 spi_message_init_with_transfers(struct spi_message *m,
905 struct spi_transfer *xfers, unsigned int num_xfers)
906 {
907         unsigned int i;
908 
909         spi_message_init(m);
910         for (i = 0; i < num_xfers; ++i)
911                 spi_message_add_tail(&xfers[i], m);
912 }
913 
914 /* It's fine to embed message and transaction structures in other data
915  * structures so long as you don't free them while they're in use.
916  */
917 
918 static inline struct spi_message *spi_message_alloc(unsigned ntrans, gfp_t flags)
919 {
920         struct spi_message *m;
921 
922         m = kzalloc(sizeof(struct spi_message)
923                         + ntrans * sizeof(struct spi_transfer),
924                         flags);
925         if (m) {
926                 unsigned i;
927                 struct spi_transfer *t = (struct spi_transfer *)(m + 1);
928 
929                 spi_message_init_no_memset(m);
930                 for (i = 0; i < ntrans; i++, t++)
931                         spi_message_add_tail(t, m);
932         }
933         return m;
934 }
935 
936 static inline void spi_message_free(struct spi_message *m)
937 {
938         kfree(m);
939 }
940 
941 extern int spi_setup(struct spi_device *spi);
942 extern int spi_async(struct spi_device *spi, struct spi_message *message);
943 extern int spi_async_locked(struct spi_device *spi,
944                             struct spi_message *message);
945 extern int spi_slave_abort(struct spi_device *spi);
946 
947 static inline size_t
948 spi_max_message_size(struct spi_device *spi)
949 {
950         struct spi_controller *ctlr = spi->controller;
951 
952         if (!ctlr->max_message_size)
953                 return SIZE_MAX;
954         return ctlr->max_message_size(spi);
955 }
956 
957 static inline size_t
958 spi_max_transfer_size(struct spi_device *spi)
959 {
960         struct spi_controller *ctlr = spi->controller;
961         size_t tr_max = SIZE_MAX;
962         size_t msg_max = spi_max_message_size(spi);
963 
964         if (ctlr->max_transfer_size)
965                 tr_max = ctlr->max_transfer_size(spi);
966 
967         /* transfer size limit must not be greater than messsage size limit */
968         return min(tr_max, msg_max);
969 }
970 
971 /*---------------------------------------------------------------------------*/
972 
973 /* SPI transfer replacement methods which make use of spi_res */
974 
975 struct spi_replaced_transfers;
976 typedef void (*spi_replaced_release_t)(struct spi_controller *ctlr,
977                                        struct spi_message *msg,
978                                        struct spi_replaced_transfers *res);
979 /**
980  * struct spi_replaced_transfers - structure describing the spi_transfer
981  *                                 replacements that have occurred
982  *                                 so that they can get reverted
983  * @release:            some extra release code to get executed prior to
984  *                      relasing this structure
985  * @extradata:          pointer to some extra data if requested or NULL
986  * @replaced_transfers: transfers that have been replaced and which need
987  *                      to get restored
988  * @replaced_after:     the transfer after which the @replaced_transfers
989  *                      are to get re-inserted
990  * @inserted:           number of transfers inserted
991  * @inserted_transfers: array of spi_transfers of array-size @inserted,
992  *                      that have been replacing replaced_transfers
993  *
994  * note: that @extradata will point to @inserted_transfers[@inserted]
995  * if some extra allocation is requested, so alignment will be the same
996  * as for spi_transfers
997  */
998 struct spi_replaced_transfers {
999         spi_replaced_release_t release;
1000         void *extradata;
1001         struct list_head replaced_transfers;
1002         struct list_head *replaced_after;
1003         size_t inserted;
1004         struct spi_transfer inserted_transfers[];
1005 };
1006 
1007 extern struct spi_replaced_transfers *spi_replace_transfers(
1008         struct spi_message *msg,
1009         struct spi_transfer *xfer_first,
1010         size_t remove,
1011         size_t insert,
1012         spi_replaced_release_t release,
1013         size_t extradatasize,
1014         gfp_t gfp);
1015 
1016 /*---------------------------------------------------------------------------*/
1017 
1018 /* SPI transfer transformation methods */
1019 
1020 extern int spi_split_transfers_maxsize(struct spi_controller *ctlr,
1021                                        struct spi_message *msg,
1022                                        size_t maxsize,
1023                                        gfp_t gfp);
1024 
1025 /*---------------------------------------------------------------------------*/
1026 
1027 /* All these synchronous SPI transfer routines are utilities layered
1028  * over the core async transfer primitive.  Here, "synchronous" means
1029  * they will sleep uninterruptibly until the async transfer completes.
1030  */
1031 
1032 extern int spi_sync(struct spi_device *spi, struct spi_message *message);
1033 extern int spi_sync_locked(struct spi_device *spi, struct spi_message *message);
1034 extern int spi_bus_lock(struct spi_controller *ctlr);
1035 extern int spi_bus_unlock(struct spi_controller *ctlr);
1036 
1037 /**
1038  * spi_sync_transfer - synchronous SPI data transfer
1039  * @spi: device with which data will be exchanged
1040  * @xfers: An array of spi_transfers
1041  * @num_xfers: Number of items in the xfer array
1042  * Context: can sleep
1043  *
1044  * Does a synchronous SPI data transfer of the given spi_transfer array.
1045  *
1046  * For more specific semantics see spi_sync().
1047  *
1048  * Return: Return: zero on success, else a negative error code.
1049  */
1050 static inline int
1051 spi_sync_transfer(struct spi_device *spi, struct spi_transfer *xfers,
1052         unsigned int num_xfers)
1053 {
1054         struct spi_message msg;
1055 
1056         spi_message_init_with_transfers(&msg, xfers, num_xfers);
1057 
1058         return spi_sync(spi, &msg);
1059 }
1060 
1061 /**
1062  * spi_write - SPI synchronous write
1063  * @spi: device to which data will be written
1064  * @buf: data buffer
1065  * @len: data buffer size
1066  * Context: can sleep
1067  *
1068  * This function writes the buffer @buf.
1069  * Callable only from contexts that can sleep.
1070  *
1071  * Return: zero on success, else a negative error code.
1072  */
1073 static inline int
1074 spi_write(struct spi_device *spi, const void *buf, size_t len)
1075 {
1076         struct spi_transfer     t = {
1077                         .tx_buf         = buf,
1078                         .len            = len,
1079                 };
1080 
1081         return spi_sync_transfer(spi, &t, 1);
1082 }
1083 
1084 /**
1085  * spi_read - SPI synchronous read
1086  * @spi: device from which data will be read
1087  * @buf: data buffer
1088  * @len: data buffer size
1089  * Context: can sleep
1090  *
1091  * This function reads the buffer @buf.
1092  * Callable only from contexts that can sleep.
1093  *
1094  * Return: zero on success, else a negative error code.
1095  */
1096 static inline int
1097 spi_read(struct spi_device *spi, void *buf, size_t len)
1098 {
1099         struct spi_transfer     t = {
1100                         .rx_buf         = buf,
1101                         .len            = len,
1102                 };
1103 
1104         return spi_sync_transfer(spi, &t, 1);
1105 }
1106 
1107 /* this copies txbuf and rxbuf data; for small transfers only! */
1108 extern int spi_write_then_read(struct spi_device *spi,
1109                 const void *txbuf, unsigned n_tx,
1110                 void *rxbuf, unsigned n_rx);
1111 
1112 /**
1113  * spi_w8r8 - SPI synchronous 8 bit write followed by 8 bit read
1114  * @spi: device with which data will be exchanged
1115  * @cmd: command to be written before data is read back
1116  * Context: can sleep
1117  *
1118  * Callable only from contexts that can sleep.
1119  *
1120  * Return: the (unsigned) eight bit number returned by the
1121  * device, or else a negative error code.
1122  */
1123 static inline ssize_t spi_w8r8(struct spi_device *spi, u8 cmd)
1124 {
1125         ssize_t                 status;
1126         u8                      result;
1127 
1128         status = spi_write_then_read(spi, &cmd, 1, &result, 1);
1129 
1130         /* return negative errno or unsigned value */
1131         return (status < 0) ? status : result;
1132 }
1133 
1134 /**
1135  * spi_w8r16 - SPI synchronous 8 bit write followed by 16 bit read
1136  * @spi: device with which data will be exchanged
1137  * @cmd: command to be written before data is read back
1138  * Context: can sleep
1139  *
1140  * The number is returned in wire-order, which is at least sometimes
1141  * big-endian.
1142  *
1143  * Callable only from contexts that can sleep.
1144  *
1145  * Return: the (unsigned) sixteen bit number returned by the
1146  * device, or else a negative error code.
1147  */
1148 static inline ssize_t spi_w8r16(struct spi_device *spi, u8 cmd)
1149 {
1150         ssize_t                 status;
1151         u16                     result;
1152 
1153         status = spi_write_then_read(spi, &cmd, 1, &result, 2);
1154 
1155         /* return negative errno or unsigned value */
1156         return (status < 0) ? status : result;
1157 }
1158 
1159 /**
1160  * spi_w8r16be - SPI synchronous 8 bit write followed by 16 bit big-endian read
1161  * @spi: device with which data will be exchanged
1162  * @cmd: command to be written before data is read back
1163  * Context: can sleep
1164  *
1165  * This function is similar to spi_w8r16, with the exception that it will
1166  * convert the read 16 bit data word from big-endian to native endianness.
1167  *
1168  * Callable only from contexts that can sleep.
1169  *
1170  * Return: the (unsigned) sixteen bit number returned by the device in cpu
1171  * endianness, or else a negative error code.
1172  */
1173 static inline ssize_t spi_w8r16be(struct spi_device *spi, u8 cmd)
1174 
1175 {
1176         ssize_t status;
1177         __be16 result;
1178 
1179         status = spi_write_then_read(spi, &cmd, 1, &result, 2);
1180         if (status < 0)
1181                 return status;
1182 
1183         return be16_to_cpu(result);
1184 }
1185 
1186 /**
1187  * struct spi_flash_read_message - flash specific information for
1188  * spi-masters that provide accelerated flash read interfaces
1189  * @buf: buffer to read data
1190  * @from: offset within the flash from where data is to be read
1191  * @len: length of data to be read
1192  * @retlen: actual length of data read
1193  * @read_opcode: read_opcode to be used to communicate with flash
1194  * @addr_width: number of address bytes
1195  * @dummy_bytes: number of dummy bytes
1196  * @opcode_nbits: number of lines to send opcode
1197  * @addr_nbits: number of lines to send address
1198  * @data_nbits: number of lines for data
1199  * @rx_sg: Scatterlist for receive data read from flash
1200  * @cur_msg_mapped: message has been mapped for DMA
1201  */
1202 struct spi_flash_read_message {
1203         void *buf;
1204         loff_t from;
1205         size_t len;
1206         size_t retlen;
1207         u8 read_opcode;
1208         u8 addr_width;
1209         u8 dummy_bytes;
1210         u8 opcode_nbits;
1211         u8 addr_nbits;
1212         u8 data_nbits;
1213         struct sg_table rx_sg;
1214         bool cur_msg_mapped;
1215 };
1216 
1217 /* SPI core interface for flash read support */
1218 static inline bool spi_flash_read_supported(struct spi_device *spi)
1219 {
1220         return spi->controller->spi_flash_read &&
1221                (!spi->controller->flash_read_supported ||
1222                spi->controller->flash_read_supported(spi));
1223 }
1224 
1225 int spi_flash_read(struct spi_device *spi,
1226                    struct spi_flash_read_message *msg);
1227 
1228 /*---------------------------------------------------------------------------*/
1229 
1230 /*
1231  * INTERFACE between board init code and SPI infrastructure.
1232  *
1233  * No SPI driver ever sees these SPI device table segments, but
1234  * it's how the SPI core (or adapters that get hotplugged) grows
1235  * the driver model tree.
1236  *
1237  * As a rule, SPI devices can't be probed.  Instead, board init code
1238  * provides a table listing the devices which are present, with enough
1239  * information to bind and set up the device's driver.  There's basic
1240  * support for nonstatic configurations too; enough to handle adding
1241  * parport adapters, or microcontrollers acting as USB-to-SPI bridges.
1242  */
1243 
1244 /**
1245  * struct spi_board_info - board-specific template for a SPI device
1246  * @modalias: Initializes spi_device.modalias; identifies the driver.
1247  * @platform_data: Initializes spi_device.platform_data; the particular
1248  *      data stored there is driver-specific.
1249  * @properties: Additional device properties for the device.
1250  * @controller_data: Initializes spi_device.controller_data; some
1251  *      controllers need hints about hardware setup, e.g. for DMA.
1252  * @irq: Initializes spi_device.irq; depends on how the board is wired.
1253  * @max_speed_hz: Initializes spi_device.max_speed_hz; based on limits
1254  *      from the chip datasheet and board-specific signal quality issues.
1255  * @bus_num: Identifies which spi_controller parents the spi_device; unused
1256  *      by spi_new_device(), and otherwise depends on board wiring.
1257  * @chip_select: Initializes spi_device.chip_select; depends on how
1258  *      the board is wired.
1259  * @mode: Initializes spi_device.mode; based on the chip datasheet, board
1260  *      wiring (some devices support both 3WIRE and standard modes), and
1261  *      possibly presence of an inverter in the chipselect path.
1262  *
1263  * When adding new SPI devices to the device tree, these structures serve
1264  * as a partial device template.  They hold information which can't always
1265  * be determined by drivers.  Information that probe() can establish (such
1266  * as the default transfer wordsize) is not included here.
1267  *
1268  * These structures are used in two places.  Their primary role is to
1269  * be stored in tables of board-specific device descriptors, which are
1270  * declared early in board initialization and then used (much later) to
1271  * populate a controller's device tree after the that controller's driver
1272  * initializes.  A secondary (and atypical) role is as a parameter to
1273  * spi_new_device() call, which happens after those controller drivers
1274  * are active in some dynamic board configuration models.
1275  */
1276 struct spi_board_info {
1277         /* the device name and module name are coupled, like platform_bus;
1278          * "modalias" is normally the driver name.
1279          *
1280          * platform_data goes to spi_device.dev.platform_data,
1281          * controller_data goes to spi_device.controller_data,
1282          * device properties are copied and attached to spi_device,
1283          * irq is copied too
1284          */
1285         char            modalias[SPI_NAME_SIZE];
1286         const void      *platform_data;
1287         const struct property_entry *properties;
1288         void            *controller_data;
1289         int             irq;
1290 
1291         /* slower signaling on noisy or low voltage boards */
1292         u32             max_speed_hz;
1293 
1294 
1295         /* bus_num is board specific and matches the bus_num of some
1296          * spi_controller that will probably be registered later.
1297          *
1298          * chip_select reflects how this chip is wired to that master;
1299          * it's less than num_chipselect.
1300          */
1301         u16             bus_num;
1302         u16             chip_select;
1303 
1304         /* mode becomes spi_device.mode, and is essential for chips
1305          * where the default of SPI_CS_HIGH = 0 is wrong.
1306          */
1307         u16             mode;
1308 
1309         /* ... may need additional spi_device chip config data here.
1310          * avoid stuff protocol drivers can set; but include stuff
1311          * needed to behave without being bound to a driver:
1312          *  - quirks like clock rate mattering when not selected
1313          */
1314 };
1315 
1316 #ifdef  CONFIG_SPI
1317 extern int
1318 spi_register_board_info(struct spi_board_info const *info, unsigned n);
1319 #else
1320 /* board init code may ignore whether SPI is configured or not */
1321 static inline int
1322 spi_register_board_info(struct spi_board_info const *info, unsigned n)
1323         { return 0; }
1324 #endif
1325 
1326 
1327 /* If you're hotplugging an adapter with devices (parport, usb, etc)
1328  * use spi_new_device() to describe each device.  You can also call
1329  * spi_unregister_device() to start making that device vanish, but
1330  * normally that would be handled by spi_unregister_controller().
1331  *
1332  * You can also use spi_alloc_device() and spi_add_device() to use a two
1333  * stage registration sequence for each spi_device.  This gives the caller
1334  * some more control over the spi_device structure before it is registered,
1335  * but requires that caller to initialize fields that would otherwise
1336  * be defined using the board info.
1337  */
1338 extern struct spi_device *
1339 spi_alloc_device(struct spi_controller *ctlr);
1340 
1341 extern int
1342 spi_add_device(struct spi_device *spi);
1343 
1344 extern struct spi_device *
1345 spi_new_device(struct spi_controller *, struct spi_board_info *);
1346 
1347 extern void spi_unregister_device(struct spi_device *spi);
1348 
1349 extern const struct spi_device_id *
1350 spi_get_device_id(const struct spi_device *sdev);
1351 
1352 static inline bool
1353 spi_transfer_is_last(struct spi_controller *ctlr, struct spi_transfer *xfer)
1354 {
1355         return list_is_last(&xfer->transfer_list, &ctlr->cur_msg->transfers);
1356 }
1357 
1358 
1359 /* Compatibility layer */
1360 #define spi_master                      spi_controller
1361 
1362 #define SPI_MASTER_HALF_DUPLEX          SPI_CONTROLLER_HALF_DUPLEX
1363 #define SPI_MASTER_NO_RX                SPI_CONTROLLER_NO_RX
1364 #define SPI_MASTER_NO_TX                SPI_CONTROLLER_NO_TX
1365 #define SPI_MASTER_MUST_RX              SPI_CONTROLLER_MUST_RX
1366 #define SPI_MASTER_MUST_TX              SPI_CONTROLLER_MUST_TX
1367 
1368 #define spi_master_get_devdata(_ctlr)   spi_controller_get_devdata(_ctlr)
1369 #define spi_master_set_devdata(_ctlr, _data)    \
1370         spi_controller_set_devdata(_ctlr, _data)
1371 #define spi_master_get(_ctlr)           spi_controller_get(_ctlr)
1372 #define spi_master_put(_ctlr)           spi_controller_put(_ctlr)
1373 #define spi_master_suspend(_ctlr)       spi_controller_suspend(_ctlr)
1374 #define spi_master_resume(_ctlr)        spi_controller_resume(_ctlr)
1375 
1376 #define spi_register_master(_ctlr)      spi_register_controller(_ctlr)
1377 #define devm_spi_register_master(_dev, _ctlr) \
1378         devm_spi_register_controller(_dev, _ctlr)
1379 #define spi_unregister_master(_ctlr)    spi_unregister_controller(_ctlr)
1380 
1381 #endif /* __LINUX_SPI_H */
1382 

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