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TOMOYO Linux Cross Reference
Linux/include/net/irda/vlsi_ir.h

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  1 
  2 /*********************************************************************
  3  *
  4  *      vlsi_ir.h:      VLSI82C147 PCI IrDA controller driver for Linux
  5  *
  6  *      Version:        0.5
  7  *
  8  *      Copyright (c) 2001-2003 Martin Diehl
  9  *
 10  *      This program is free software; you can redistribute it and/or 
 11  *      modify it under the terms of the GNU General Public License as 
 12  *      published by the Free Software Foundation; either version 2 of 
 13  *      the License, or (at your option) any later version.
 14  *
 15  *      This program is distributed in the hope that it will be useful,
 16  *      but WITHOUT ANY WARRANTY; without even the implied warranty of
 17  *      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 18  *      GNU General Public License for more details.
 19  *
 20  *      You should have received a copy of the GNU General Public License 
 21  *      along with this program; if not, write to the Free Software 
 22  *      Foundation, Inc., 59 Temple Place, Suite 330, Boston, 
 23  *      MA 02111-1307 USA
 24  *
 25  ********************************************************************/
 26 
 27 #ifndef IRDA_VLSI_FIR_H
 28 #define IRDA_VLSI_FIR_H
 29 
 30 /* ================================================================
 31  * compatibility stuff
 32  */
 33 
 34 /* definitions not present in pci_ids.h */
 35 
 36 #ifndef PCI_CLASS_WIRELESS_IRDA
 37 #define PCI_CLASS_WIRELESS_IRDA         0x0d00
 38 #endif
 39 
 40 #ifndef PCI_CLASS_SUBCLASS_MASK
 41 #define PCI_CLASS_SUBCLASS_MASK         0xffff
 42 #endif
 43 
 44 /* missing pci-dma api call to give streaming dma buffer back to hw
 45  * patch was floating on lkml around 2.5.2x and might be present later.
 46  * Defining it this way is ok, since the vlsi-ir is only
 47  * used on two oldish x86-based notebooks which are cache-coherent
 48  * (and flush_write_buffers also handles PPro errata and C3 OOstore)
 49  */
 50 #ifdef CONFIG_X86
 51 #include <asm-i386/io.h>
 52 #define pci_dma_prep_single(dev, addr, size, direction) flush_write_buffers()
 53 #else
 54 #error missing pci dma api call
 55 #endif
 56 
 57 /* in recent 2.5 interrupt handlers have non-void return value */
 58 #ifndef IRQ_RETVAL
 59 typedef void irqreturn_t;
 60 #define IRQ_NONE
 61 #define IRQ_HANDLED
 62 #define IRQ_RETVAL(x)
 63 #endif
 64 
 65 /* some stuff need to check kernelversion. Not all 2.5 stuff was present
 66  * in early 2.5.x - the test is merely to separate 2.4 from 2.5
 67  */
 68 #include <linux/version.h>
 69 
 70 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
 71 
 72 /* PDE() introduced in 2.5.4 */
 73 #ifdef CONFIG_PROC_FS
 74 #define PDE(inode) ((inode)->u.generic_ip)
 75 #endif
 76 
 77 /* irda crc16 calculation exported in 2.5.42 */
 78 #define irda_calc_crc16(fcs,buf,len)    (GOOD_FCS)
 79 
 80 /* we use this for unified pci device name access */
 81 #define PCIDEV_NAME(pdev)       ((pdev)->name)
 82 
 83 #else /* 2.5 or later */
 84 
 85 /* recent 2.5/2.6 stores pci device names at varying places ;-) */
 86 #ifdef CONFIG_PCI_NAMES
 87 /* human readable name */
 88 #define PCIDEV_NAME(pdev)       ((pdev)->pretty_name)
 89 #else
 90 /* whatever we get from the associated struct device - bus:slot:dev.fn id */
 91 #define PCIDEV_NAME(pdev)       (pci_name(pdev))
 92 #endif
 93 
 94 #endif
 95 
 96 /* ================================================================ */
 97 
 98 /* non-standard PCI registers */
 99 
100 enum vlsi_pci_regs {
101         VLSI_PCI_CLKCTL         = 0x40,         /* chip clock input control */
102         VLSI_PCI_MSTRPAGE       = 0x41,         /* addr [31:24] for all busmaster cycles */
103         VLSI_PCI_IRMISC         = 0x42          /* mainly legacy UART related */
104 };
105 
106 /* ------------------------------------------ */
107 
108 /* VLSI_PCI_CLKCTL: Clock Control Register (u8, rw) */
109 
110 /* Three possible clock sources: either on-chip 48MHz PLL or
111  * external clock applied to EXTCLK pin. External clock may
112  * be either 48MHz or 40MHz, which is indicated by XCKSEL.
113  * CLKSTP controls whether the selected clock source gets
114  * connected to the IrDA block.
115  *
116  * On my HP OB-800 the BIOS sets external 40MHz clock as source
117  * when IrDA enabled and I've never detected any PLL lock success.
118  * Apparently the 14.3...MHz OSC input required for the PLL to work
119  * is not connected and the 40MHz EXTCLK is provided externally.
120  * At least this is what makes the driver working for me.
121  */
122 
123 enum vlsi_pci_clkctl {
124 
125         /* PLL control */
126 
127         CLKCTL_PD_INV           = 0x04,         /* PD#: inverted power down signal,
128                                                  * i.e. PLL is powered, if PD_INV set */
129         CLKCTL_LOCK             = 0x40,         /* (ro) set, if PLL is locked */
130 
131         /* clock source selection */
132 
133         CLKCTL_EXTCLK           = 0x20,         /* set to select external clock input, not PLL */
134         CLKCTL_XCKSEL           = 0x10,         /* set to indicate EXTCLK is 40MHz, not 48MHz */
135 
136         /* IrDA block control */
137 
138         CLKCTL_CLKSTP           = 0x80,         /* set to disconnect from selected clock source */
139         CLKCTL_WAKE             = 0x08          /* set to enable wakeup feature: whenever IR activity
140                                                  * is detected, PD_INV gets set(?) and CLKSTP cleared */
141 };
142 
143 /* ------------------------------------------ */
144 
145 /* VLSI_PCI_MSTRPAGE: Master Page Register (u8, rw) and busmastering stuff */
146 
147 #define DMA_MASK_USED_BY_HW     0xffffffff
148 #define DMA_MASK_MSTRPAGE       0x00ffffff
149 #define MSTRPAGE_VALUE          (DMA_MASK_MSTRPAGE >> 24)
150 
151         /* PCI busmastering is somewhat special for this guy - in short:
152          *
153          * We select to operate using fixed MSTRPAGE=0, use ISA DMA
154          * address restrictions to make the PCI BM api aware of this,
155          * but ensure the hardware is dealing with real 32bit access.
156          *
157          * In detail:
158          * The chip executes normal 32bit busmaster cycles, i.e.
159          * drives all 32 address lines. These addresses however are
160          * composed of [0:23] taken from various busaddr-pointers
161          * and [24:31] taken from the MSTRPAGE register in the VLSI82C147
162          * config space. Therefore _all_ busmastering must be
163          * targeted to/from one single 16MB (busaddr-) superpage!
164          * The point is to make sure all the allocations for memory
165          * locations with busmaster access (ring descriptors, buffers)
166          * are indeed bus-mappable to the same 16MB range (for x86 this
167          * means they must reside in the same 16MB physical memory address
168          * range). The only constraint we have which supports "several objects
169          * mappable to common 16MB range" paradigma, is the old ISA DMA
170          * restriction to the first 16MB of physical address range.
171          * Hence the approach here is to enable PCI busmaster support using
172          * the correct 32bit dma-mask used by the chip. Afterwards the device's
173          * dma-mask gets restricted to 24bit, which must be honoured somehow by
174          * all allocations for memory areas to be exposed to the chip ...
175          *
176          * Note:
177          * Don't be surprised to get "Setting latency timer..." messages every
178          * time when PCI busmastering is enabled for the chip.
179          * The chip has its PCI latency timer RO fixed at 0 - which is not a
180          * problem here, because it is never requesting _burst_ transactions.
181          */
182 
183 /* ------------------------------------------ */
184 
185 /* VLSI_PCIIRMISC: IR Miscellaneous Register (u8, rw) */
186 
187 /* legacy UART emulation - not used by this driver - would require:
188  * (see below for some register-value definitions)
189  *
190  *      - IRMISC_UARTEN must be set to enable UART address decoding
191  *      - IRMISC_UARTSEL configured
192  *      - IRCFG_MASTER must be cleared
193  *      - IRCFG_SIR must be set
194  *      - IRENABLE_PHYANDCLOCK must be asserted 0->1 (and hence IRENABLE_SIR_ON)
195  */
196 
197 enum vlsi_pci_irmisc {
198 
199         /* IR transceiver control */
200 
201         IRMISC_IRRAIL           = 0x40,         /* (ro?) IR rail power indication (and control?)
202                                                  * 0=3.3V / 1=5V. Probably set during power-on?
203                                                  * unclear - not touched by driver */
204         IRMISC_IRPD             = 0x08,         /* transceiver power down, if set */
205 
206         /* legacy UART control */
207 
208         IRMISC_UARTTST          = 0x80,         /* UART test mode - "always write 0" */
209         IRMISC_UARTEN           = 0x04,         /* enable UART address decoding */
210 
211         /* bits [1:0] IRMISC_UARTSEL to select legacy UART address */
212 
213         IRMISC_UARTSEL_3f8      = 0x00,
214         IRMISC_UARTSEL_2f8      = 0x01,
215         IRMISC_UARTSEL_3e8      = 0x02,
216         IRMISC_UARTSEL_2e8      = 0x03
217 };
218 
219 /* ================================================================ */
220 
221 /* registers mapped to 32 byte PCI IO space */
222 
223 /* note: better access all registers at the indicated u8/u16 size
224  *       although some of them contain only 1 byte of information.
225  *       some of them (particaluarly PROMPT and IRCFG) ignore
226  *       access when using the wrong addressing mode!
227  */
228 
229 enum vlsi_pio_regs {
230         VLSI_PIO_IRINTR         = 0x00,         /* interrupt enable/request (u8, rw) */
231         VLSI_PIO_RINGPTR        = 0x02,         /* rx/tx ring pointer (u16, ro) */
232         VLSI_PIO_RINGBASE       = 0x04,         /* [23:10] of ring address (u16, rw) */
233         VLSI_PIO_RINGSIZE       = 0x06,         /* rx/tx ring size (u16, rw) */
234         VLSI_PIO_PROMPT         = 0x08,         /* triggers ring processing (u16, wo) */
235         /* 0x0a-0x0f: reserved / duplicated UART regs */
236         VLSI_PIO_IRCFG          = 0x10,         /* configuration select (u16, rw) */
237         VLSI_PIO_SIRFLAG        = 0x12,         /* BOF/EOF for filtered SIR (u16, ro) */
238         VLSI_PIO_IRENABLE       = 0x14,         /* enable and status register (u16, rw/ro) */
239         VLSI_PIO_PHYCTL         = 0x16,         /* physical layer current status (u16, ro) */
240         VLSI_PIO_NPHYCTL        = 0x18,         /* next physical layer select (u16, rw) */
241         VLSI_PIO_MAXPKT         = 0x1a,         /* [11:0] max len for packet receive (u16, rw) */
242         VLSI_PIO_RCVBCNT        = 0x1c          /* current receive-FIFO byte count (u16, ro) */
243         /* 0x1e-0x1f: reserved / duplicated UART regs */
244 };
245 
246 /* ------------------------------------------ */
247 
248 /* VLSI_PIO_IRINTR: Interrupt Register (u8, rw) */
249 
250 /* enable-bits:
251  *              1 = enable / 0 = disable
252  * interrupt condition bits:
253  *              set according to corresponding interrupt source
254  *              (regardless of the state of the enable bits)
255  *              enable bit status indicates whether interrupt gets raised
256  *              write-to-clear
257  * note: RPKTINT and TPKTINT behave different in legacy UART mode (which we don't use :-)
258  */
259 
260 enum vlsi_pio_irintr {
261         IRINTR_ACTEN    = 0x80, /* activity interrupt enable */
262         IRINTR_ACTIVITY = 0x40, /* activity monitor (traffic detected) */
263         IRINTR_RPKTEN   = 0x20, /* receive packet interrupt enable*/
264         IRINTR_RPKTINT  = 0x10, /* rx-packet transfered from fifo to memory finished */
265         IRINTR_TPKTEN   = 0x08, /* transmit packet interrupt enable */
266         IRINTR_TPKTINT  = 0x04, /* last bit of tx-packet+crc shifted to ir-pulser */
267         IRINTR_OE_EN    = 0x02, /* UART rx fifo overrun error interrupt enable */
268         IRINTR_OE_INT   = 0x01  /* UART rx fifo overrun error (read LSR to clear) */
269 };
270 
271 /* we use this mask to check whether the (shared PCI) interrupt is ours */
272 
273 #define IRINTR_INT_MASK         (IRINTR_ACTIVITY|IRINTR_RPKTINT|IRINTR_TPKTINT)
274 
275 /* ------------------------------------------ */
276 
277 /* VLSI_PIO_RINGPTR: Ring Pointer Read-Back Register (u16, ro) */
278 
279 /* _both_ ring pointers are indices relative to the _entire_ rx,tx-ring!
280  * i.e. the referenced descriptor is located
281  * at RINGBASE + PTR * sizeof(descr) for rx and tx
282  * therefore, the tx-pointer has offset MAX_RING_DESCR
283  */
284 
285 #define MAX_RING_DESCR          64      /* tx, rx rings may contain up to 64 descr each */
286 
287 #define RINGPTR_RX_MASK         (MAX_RING_DESCR-1)
288 #define RINGPTR_TX_MASK         ((MAX_RING_DESCR-1)<<8)
289 
290 #define RINGPTR_GET_RX(p)       ((p)&RINGPTR_RX_MASK)
291 #define RINGPTR_GET_TX(p)       (((p)&RINGPTR_TX_MASK)>>8)
292 
293 /* ------------------------------------------ */
294 
295 /* VLSI_PIO_RINGBASE: Ring Pointer Base Address Register (u16, ro) */
296 
297 /* Contains [23:10] part of the ring base (bus-) address
298  * which must be 1k-alinged. [31:24] is taken from
299  * VLSI_PCI_MSTRPAGE above.
300  * The controller initiates non-burst PCI BM cycles to
301  * fetch and update the descriptors in the ring.
302  * Once fetched, the descriptor remains cached onchip
303  * until it gets closed and updated due to the ring
304  * processing state machine.
305  * The entire ring area is split in rx and tx areas with each
306  * area consisting of 64 descriptors of 8 bytes each.
307  * The rx(tx) ring is located at ringbase+0 (ringbase+64*8).
308  */
309 
310 #define BUS_TO_RINGBASE(p)      (((p)>>10)&0x3fff)
311 
312 /* ------------------------------------------ */
313 
314 /* VLSI_PIO_RINGSIZE: Ring Size Register (u16, rw) */
315 
316 /* bit mask to indicate the ring size to be used for rx and tx.
317  *      possible values         encoded bits
318  *               4                 0000
319  *               8                 0001
320  *              16                 0011
321  *              32                 0111
322  *              64                 1111
323  * located at [15:12] for tx and [11:8] for rx ([7:0] unused)
324  *
325  * note: probably a good idea to have IRCFG_MSTR cleared when writing
326  *       this so the state machines are stopped and the RINGPTR is reset!
327  */
328 
329 #define SIZE_TO_BITS(num)               ((((num)-1)>>2)&0x0f)
330 #define TX_RX_TO_RINGSIZE(tx,rx)        ((SIZE_TO_BITS(tx)<<12)|(SIZE_TO_BITS(rx)<<8))
331 #define RINGSIZE_TO_RXSIZE(rs)          ((((rs)&0x0f00)>>6)+4)
332 #define RINGSIZE_TO_TXSIZE(rs)          ((((rs)&0xf000)>>10)+4)
333 
334 
335 /* ------------------------------------------ */
336 
337 /* VLSI_PIO_PROMPT: Ring Prompting Register (u16, write-to-start) */
338 
339 /* writing any value kicks the ring processing state machines
340  * for both tx, rx rings as follows:
341  *      - active rings (currently owning an active descriptor)
342  *        ignore the prompt and continue
343  *      - idle rings fetch the next descr from the ring and start
344  *        their processing
345  */
346 
347 /* ------------------------------------------ */
348 
349 /* VLSI_PIO_IRCFG: IR Config Register (u16, rw) */
350 
351 /* notes:
352  *      - not more than one SIR/MIR/FIR bit must be set at any time
353  *      - SIR, MIR, FIR and CRC16 select the configuration which will
354  *        be applied on next 0->1 transition of IRENABLE_PHYANDCLOCK (see below).
355  *      - besides allowing the PCI interface to execute busmaster cycles
356  *        and therefore the ring SM to operate, the MSTR bit has side-effects:
357  *        when MSTR is cleared, the RINGPTR's get reset and the legacy UART mode
358  *        (in contrast to busmaster access mode) gets enabled.
359  *      - clearing ENRX or setting ENTX while data is received may stall the
360  *        receive fifo until ENRX reenabled _and_ another packet arrives
361  *      - SIRFILT means the chip performs the required unwrapping of hardware
362  *        headers (XBOF's, BOF/EOF) and un-escaping in the _receive_ direction.
363  *        Only the resulting IrLAP payload is copied to the receive buffers -
364  *        but with the 16bit FCS still encluded. Question remains, whether it
365  *        was already checked or we should do it before passing the packet to IrLAP?
366  */
367 
368 enum vlsi_pio_ircfg {
369         IRCFG_LOOP      = 0x4000,       /* enable loopback test mode */
370         IRCFG_ENTX      = 0x1000,       /* transmit enable */
371         IRCFG_ENRX      = 0x0800,       /* receive enable */
372         IRCFG_MSTR      = 0x0400,       /* master enable */
373         IRCFG_RXANY     = 0x0200,       /* receive any packet */
374         IRCFG_CRC16     = 0x0080,       /* 16bit (not 32bit) CRC select for MIR/FIR */
375         IRCFG_FIR       = 0x0040,       /* FIR 4PPM encoding mode enable */
376         IRCFG_MIR       = 0x0020,       /* MIR HDLC encoding mode enable */
377         IRCFG_SIR       = 0x0010,       /* SIR encoding mode enable */
378         IRCFG_SIRFILT   = 0x0008,       /* enable SIR decode filter (receiver unwrapping) */
379         IRCFG_SIRTEST   = 0x0004,       /* allow SIR decode filter when not in SIR mode */
380         IRCFG_TXPOL     = 0x0002,       /* invert tx polarity when set */
381         IRCFG_RXPOL     = 0x0001        /* invert rx polarity when set */
382 };
383 
384 /* ------------------------------------------ */
385 
386 /* VLSI_PIO_SIRFLAG: SIR Flag Register (u16, ro) */
387 
388 /* register contains hardcoded BOF=0xc0 at [7:0] and EOF=0xc1 at [15:8]
389  * which is used for unwrapping received frames in SIR decode-filter mode
390  */
391 
392 /* ------------------------------------------ */
393 
394 /* VLSI_PIO_IRENABLE: IR Enable Register (u16, rw/ro) */
395 
396 /* notes:
397  *      - IREN acts as gate for latching the configured IR mode information
398  *        from IRCFG and IRPHYCTL when IREN=reset and applying them when
399  *        IREN gets set afterwards.
400  *      - ENTXST reflects IRCFG_ENTX
401  *      - ENRXST = IRCFG_ENRX && (!IRCFG_ENTX || IRCFG_LOOP)
402  */
403 
404 enum vlsi_pio_irenable {
405         IRENABLE_PHYANDCLOCK    = 0x8000,  /* enable IR phy and gate the mode config (rw) */
406         IRENABLE_CFGER          = 0x4000,  /* mode configuration error (ro) */
407         IRENABLE_FIR_ON         = 0x2000,  /* FIR on status (ro) */
408         IRENABLE_MIR_ON         = 0x1000,  /* MIR on status (ro) */
409         IRENABLE_SIR_ON         = 0x0800,  /* SIR on status (ro) */
410         IRENABLE_ENTXST         = 0x0400,  /* transmit enable status (ro) */
411         IRENABLE_ENRXST         = 0x0200,  /* Receive enable status (ro) */
412         IRENABLE_CRC16_ON       = 0x0100   /* 16bit (not 32bit) CRC enabled status (ro) */
413 };
414 
415 #define   IRENABLE_MASK     0xff00  /* Read mask */
416 
417 /* ------------------------------------------ */
418 
419 /* VLSI_PIO_PHYCTL: IR Physical Layer Current Control Register (u16, ro) */
420 
421 /* read-back of the currently applied physical layer status.
422  * applied from VLSI_PIO_NPHYCTL at rising edge of IRENABLE_PHYANDCLOCK
423  * contents identical to VLSI_PIO_NPHYCTL (see below)
424  */
425 
426 /* ------------------------------------------ */
427 
428 /* VLSI_PIO_NPHYCTL: IR Physical Layer Next Control Register (u16, rw) */
429 
430 /* latched during IRENABLE_PHYANDCLOCK=0 and applied at 0-1 transition
431  *
432  * consists of BAUD[15:10], PLSWID[9:5] and PREAMB[4:0] bits defined as follows:
433  *
434  * SIR-mode:    BAUD = (115.2kHz / baudrate) - 1
435  *              PLSWID = (pulsetime * freq / (BAUD+1)) - 1
436  *                      where pulsetime is the requested IrPHY pulse width
437  *                      and freq is 8(16)MHz for 40(48)MHz primary input clock
438  *              PREAMB: don't care for SIR
439  *
440  *              The nominal SIR pulse width is 3/16 bit time so we have PLSWID=12
441  *              fixed for all SIR speeds at 40MHz input clock (PLSWID=24 at 48MHz).
442  *              IrPHY also allows shorter pulses down to the nominal pulse duration
443  *              at 115.2kbaud (minus some tolerance) which is 1.41 usec.
444  *              Using the expression PLSWID = 12/(BAUD+1)-1 (multiplied by two for 48MHz)
445  *              we get the minimum acceptable PLSWID values according to the VLSI
446  *              specification, which provides 1.5 usec pulse width for all speeds (except
447  *              for 2.4kbaud getting 6usec). This is fine with IrPHY v1.3 specs and
448  *              reduces the transceiver power which drains the battery. At 9.6kbaud for
449  *              example this amounts to more than 90% battery power saving!
450  *
451  * MIR-mode:    BAUD = 0
452  *              PLSWID = 9(10) for 40(48) MHz input clock
453  *                      to get nominal MIR pulse width
454  *              PREAMB = 1
455  *
456  * FIR-mode:    BAUD = 0
457  *              PLSWID: don't care
458  *              PREAMB = 15
459  */
460 
461 #define PHYCTL_BAUD_SHIFT       10
462 #define PHYCTL_BAUD_MASK        0xfc00
463 #define PHYCTL_PLSWID_SHIFT     5
464 #define PHYCTL_PLSWID_MASK      0x03e0
465 #define PHYCTL_PREAMB_SHIFT     0
466 #define PHYCTL_PREAMB_MASK      0x001f
467 
468 #define PHYCTL_TO_BAUD(bwp)     (((bwp)&PHYCTL_BAUD_MASK)>>PHYCTL_BAUD_SHIFT)
469 #define PHYCTL_TO_PLSWID(bwp)   (((bwp)&PHYCTL_PLSWID_MASK)>>PHYCTL_PLSWID_SHIFT)
470 #define PHYCTL_TO_PREAMB(bwp)   (((bwp)&PHYCTL_PREAMB_MASK)>>PHYCTL_PREAMB_SHIFT)
471 
472 #define BWP_TO_PHYCTL(b,w,p)    ((((b)<<PHYCTL_BAUD_SHIFT)&PHYCTL_BAUD_MASK) \
473                                  | (((w)<<PHYCTL_PLSWID_SHIFT)&PHYCTL_PLSWID_MASK) \
474                                  | (((p)<<PHYCTL_PREAMB_SHIFT)&PHYCTL_PREAMB_MASK))
475 
476 #define BAUD_BITS(br)           ((115200/(br))-1)
477 
478 static inline unsigned
479 calc_width_bits(unsigned baudrate, unsigned widthselect, unsigned clockselect)
480 {
481         unsigned        tmp;
482 
483         if (widthselect)        /* nominal 3/16 puls width */
484                 return (clockselect) ? 12 : 24;
485 
486         tmp = ((clockselect) ? 12 : 24) / (BAUD_BITS(baudrate)+1);
487 
488         /* intermediate result of integer division needed here */
489 
490         return (tmp>0) ? (tmp-1) : 0;
491 }
492 
493 #define PHYCTL_SIR(br,ws,cs)    BWP_TO_PHYCTL(BAUD_BITS(br),calc_width_bits((br),(ws),(cs)),0)
494 #define PHYCTL_MIR(cs)          BWP_TO_PHYCTL(0,((cs)?9:10),1)
495 #define PHYCTL_FIR              BWP_TO_PHYCTL(0,0,15)
496 
497 /* quite ugly, I know. But implementing these calculations here avoids
498  * having magic numbers in the code and allows some playing with pulsewidths
499  * without risk to violate the standards.
500  * FWIW, here is the table for reference:
501  *
502  * baudrate     BAUD    min-PLSWID      nom-PLSWID      PREAMB
503  *     2400       47       0(0)            12(24)          0
504  *     9600       11       0(0)            12(24)          0
505  *    19200        5       1(2)            12(24)          0
506  *    38400        2       3(6)            12(24)          0
507  *    57600        1       5(10)           12(24)          0
508  *   115200        0      11(22)           12(24)          0
509  *      MIR        0        -               9(10)          1
510  *      FIR        0        -               0             15
511  *
512  * note: x(y) means x-value for 40MHz / y-value for 48MHz primary input clock
513  */
514 
515 /* ------------------------------------------ */
516 
517 
518 /* VLSI_PIO_MAXPKT: Maximum Packet Length register (u16, rw) */
519 
520 /* maximum acceptable length for received packets */
521 
522 /* hw imposed limitation - register uses only [11:0] */
523 #define MAX_PACKET_LENGTH       0x0fff
524 
525 /* IrLAP I-field (apparently not defined elsewhere) */
526 #define IRDA_MTU                2048
527 
528 /* complete packet consists of A(1)+C(1)+I(<=IRDA_MTU) */
529 #define IRLAP_SKB_ALLOCSIZE     (1+1+IRDA_MTU)
530 
531 /* the buffers we use to exchange frames with the hardware need to be
532  * larger than IRLAP_SKB_ALLOCSIZE because we may have up to 4 bytes FCS
533  * appended and, in SIR mode, a lot of frame wrapping bytes. The worst
534  * case appears to be a SIR packet with I-size==IRDA_MTU and all bytes
535  * requiring to be escaped to provide transparency. Furthermore, the peer
536  * might ask for quite a number of additional XBOFs:
537  *      up to 115+48 XBOFS               163
538  *      regular BOF                        1
539  *      A-field                            1
540  *      C-field                            1
541  *      I-field, IRDA_MTU, all escaped  4096
542  *      FCS (16 bit at SIR, escaped)       4
543  *      EOF                                1
544  * AFAICS nothing in IrLAP guarantees A/C field not to need escaping
545  * (f.e. 0xc0/0xc1 - i.e. BOF/EOF - are legal values there) so in the
546  * worst case we have 4269 bytes total frame size.
547  * However, the VLSI uses 12 bits only for all buffer length values,
548  * which limits the maximum useable buffer size <= 4095.
549  * Note this is not a limitation in the receive case because we use
550  * the SIR filtering mode where the hw unwraps the frame and only the
551  * bare packet+fcs is stored into the buffer - in contrast to the SIR
552  * tx case where we have to pass frame-wrapped packets to the hw.
553  * If this would ever become an issue in real life, the only workaround
554  * I see would be using the legacy UART emulation in SIR mode.
555  */
556 
557 #define XFER_BUF_SIZE           MAX_PACKET_LENGTH
558 
559 /* ------------------------------------------ */
560 
561 /* VLSI_PIO_RCVBCNT: Receive Byte Count Register (u16, ro) */
562 
563 /* receive packet counter gets incremented on every non-filtered
564  * byte which was put in the receive fifo and reset for each
565  * new packet. Used to decide whether we are just in the middle
566  * of receiving
567  */
568 
569 /* better apply the [11:0] mask when reading, as some docs say the
570  * reserved [15:12] would return 1 when reading - which is wrong AFAICS
571  */
572 #define RCVBCNT_MASK    0x0fff
573 
574 /******************************************************************/
575 
576 /* descriptors for rx/tx ring
577  *
578  * accessed by hardware - don't change!
579  *
580  * the descriptor is owned by hardware, when the ACTIVE status bit
581  * is set and nothing (besides reading status to test the bit)
582  * shall be done. The bit gets cleared by hw, when the descriptor
583  * gets closed. Premature reaping of descriptors owned be the chip
584  * can be achieved by disabling IRCFG_MSTR
585  *
586  * Attention: Writing addr overwrites status!
587  *
588  * ### FIXME: depends on endianess (but there ain't no non-i586 ob800 ;-)
589  */
590 
591 struct ring_descr_hw {
592         volatile u16    rd_count;       /* tx/rx count [11:0] */
593         u16             reserved;
594         union {
595                 u32     addr;           /* [23:0] of the buffer's busaddress */
596                 struct {
597                         u8              addr_res[3];
598                         volatile u8     status;         /* descriptor status */
599                 } rd_s __attribute__((packed));
600         } rd_u __attribute((packed));
601 } __attribute__ ((packed));
602 
603 #define rd_addr         rd_u.addr
604 #define rd_status       rd_u.rd_s.status
605 
606 /* ring descriptor status bits */
607 
608 #define RD_ACTIVE               0x80    /* descriptor owned by hw (both TX,RX) */
609 
610 /* TX ring descriptor status */
611 
612 #define RD_TX_DISCRC            0x40    /* do not send CRC (for SIR) */
613 #define RD_TX_BADCRC            0x20    /* force a bad CRC */
614 #define RD_TX_PULSE             0x10    /* send indication pulse after this frame (MIR/FIR) */
615 #define RD_TX_FRCEUND           0x08    /* force underrun */
616 #define RD_TX_CLRENTX           0x04    /* clear ENTX after this frame */
617 #define RD_TX_UNDRN             0x01    /* TX fifo underrun (probably PCI problem) */
618 
619 /* RX ring descriptor status */
620 
621 #define RD_RX_PHYERR            0x40    /* physical encoding error */
622 #define RD_RX_CRCERR            0x20    /* CRC error (MIR/FIR) */
623 #define RD_RX_LENGTH            0x10    /* frame exceeds buffer length */
624 #define RD_RX_OVER              0x08    /* RX fifo overrun (probably PCI problem) */
625 #define RD_RX_SIRBAD            0x04    /* EOF missing: BOF follows BOF (SIR, filtered) */
626 
627 #define RD_RX_ERROR             0x7c    /* any error in received frame */
628 
629 /* the memory required to hold the 2 descriptor rings */
630 #define HW_RING_AREA_SIZE       (2 * MAX_RING_DESCR * sizeof(struct ring_descr_hw))
631 
632 /******************************************************************/
633 
634 /* sw-ring descriptors consists of a bus-mapped transfer buffer with
635  * associated skb and a pointer to the hw entry descriptor
636  */
637 
638 struct ring_descr {
639         struct ring_descr_hw    *hw;
640         struct sk_buff          *skb;
641         void                    *buf;
642 };
643 
644 /* wrappers for operations on hw-exposed ring descriptors
645  * access to the hw-part of the descriptors must use these.
646  */
647 
648 static inline int rd_is_active(struct ring_descr *rd)
649 {
650         return ((rd->hw->rd_status & RD_ACTIVE) != 0);
651 }
652 
653 static inline void rd_activate(struct ring_descr *rd)
654 {
655         rd->hw->rd_status |= RD_ACTIVE;
656 }
657 
658 static inline void rd_set_status(struct ring_descr *rd, u8 s)
659 {
660         rd->hw->rd_status = s;   /* may pass ownership to the hardware */
661 }
662 
663 static inline void rd_set_addr_status(struct ring_descr *rd, dma_addr_t a, u8 s)
664 {
665         /* order is important for two reasons:
666          *  - overlayed: writing addr overwrites status
667          *  - we want to write status last so we have valid address in
668          *    case status has RD_ACTIVE set
669          */
670 
671         if ((a & ~DMA_MASK_MSTRPAGE)>>24 != MSTRPAGE_VALUE) {
672                 ERROR("%s: pci busaddr inconsistency!\n", __FUNCTION__);
673                 dump_stack();
674                 return;
675         }
676 
677         a &= DMA_MASK_MSTRPAGE;  /* clear highbyte to make sure we won't write
678                                   * to status - just in case MSTRPAGE_VALUE!=0
679                                   */
680         rd->hw->rd_addr = cpu_to_le32(a);
681         wmb();
682         rd_set_status(rd, s);    /* may pass ownership to the hardware */
683 }
684 
685 static inline void rd_set_count(struct ring_descr *rd, u16 c)
686 {
687         rd->hw->rd_count = cpu_to_le16(c);
688 }
689 
690 static inline u8 rd_get_status(struct ring_descr *rd)
691 {
692         return rd->hw->rd_status;
693 }
694 
695 static inline dma_addr_t rd_get_addr(struct ring_descr *rd)
696 {
697         dma_addr_t      a;
698 
699         a = le32_to_cpu(rd->hw->rd_addr);
700         return (a & DMA_MASK_MSTRPAGE) | (MSTRPAGE_VALUE << 24);
701 }
702 
703 static inline u16 rd_get_count(struct ring_descr *rd)
704 {
705         return le16_to_cpu(rd->hw->rd_count);
706 }
707 
708 /******************************************************************/
709 
710 /* sw descriptor rings for rx, tx:
711  *
712  * operations follow producer-consumer paradigm, with the hw
713  * in the middle doing the processing.
714  * ring size must be power of two.
715  *
716  * producer advances r->tail after inserting for processing
717  * consumer advances r->head after removing processed rd
718  * ring is empty if head==tail / full if (tail+1)==head
719  */
720 
721 struct vlsi_ring {
722         struct pci_dev          *pdev;
723         int                     dir;
724         unsigned                len;
725         unsigned                size;
726         unsigned                mask;
727         atomic_t                head, tail;
728         struct ring_descr       *rd;
729 };
730 
731 /* ring processing helpers */
732 
733 static inline struct ring_descr *ring_last(struct vlsi_ring *r)
734 {
735         int t;
736 
737         t = atomic_read(&r->tail) & r->mask;
738         return (((t+1) & r->mask) == (atomic_read(&r->head) & r->mask)) ? NULL : &r->rd[t];
739 }
740 
741 static inline struct ring_descr *ring_put(struct vlsi_ring *r)
742 {
743         atomic_inc(&r->tail);
744         return ring_last(r);
745 }
746 
747 static inline struct ring_descr *ring_first(struct vlsi_ring *r)
748 {
749         int h;
750 
751         h = atomic_read(&r->head) & r->mask;
752         return (h == (atomic_read(&r->tail) & r->mask)) ? NULL : &r->rd[h];
753 }
754 
755 static inline struct ring_descr *ring_get(struct vlsi_ring *r)
756 {
757         atomic_inc(&r->head);
758         return ring_first(r);
759 }
760 
761 /******************************************************************/
762 
763 /* our private compound VLSI-PCI-IRDA device information */
764 
765 typedef struct vlsi_irda_dev {
766         struct pci_dev          *pdev;
767         struct net_device_stats stats;
768 
769         struct irlap_cb         *irlap;
770 
771         struct qos_info         qos;
772 
773         unsigned                mode;
774         int                     baud, new_baud;
775 
776         dma_addr_t              busaddr;
777         void                    *virtaddr;
778         struct vlsi_ring        *tx_ring, *rx_ring;
779 
780         struct timeval          last_rx;
781 
782         spinlock_t              lock;
783         struct semaphore        sem;
784 
785         u32                     cfg_space[64/sizeof(u32)];
786         u8                      resume_ok;      
787         struct proc_dir_entry   *proc_entry;
788 
789 } vlsi_irda_dev_t;
790 
791 /********************************************************/
792 
793 /* the remapped error flags we use for returning from frame
794  * post-processing in vlsi_process_tx/rx() after it was completed
795  * by the hardware. These functions either return the >=0 number
796  * of transfered bytes in case of success or the negative (-)
797  * of the or'ed error flags.
798  */
799 
800 #define VLSI_TX_DROP            0x0001
801 #define VLSI_TX_FIFO            0x0002
802 
803 #define VLSI_RX_DROP            0x0100
804 #define VLSI_RX_OVER            0x0200
805 #define VLSI_RX_LENGTH          0x0400
806 #define VLSI_RX_FRAME           0x0800
807 #define VLSI_RX_CRC             0x1000
808 
809 /********************************************************/
810 
811 #endif /* IRDA_VLSI_FIR_H */
812 
813 

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