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TOMOYO Linux Cross Reference
Linux/include/sound/ak4113.h

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  1 #ifndef __SOUND_AK4113_H
  2 #define __SOUND_AK4113_H
  3 
  4 /*
  5  *  Routines for Asahi Kasei AK4113
  6  *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
  7  *  Copyright (c) by Pavel Hofman <pavel.hofman@ivitera.com>,
  8  *
  9  *
 10  *   This program is free software; you can redistribute it and/or modify
 11  *   it under the terms of the GNU General Public License as published by
 12  *   the Free Software Foundation; either version 2 of the License, or
 13  *   (at your option) any later version.
 14  *
 15  *   This program is distributed in the hope that it will be useful,
 16  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 17  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 18  *   GNU General Public License for more details.
 19  *
 20  *   You should have received a copy of the GNU General Public License
 21  *   along with this program; if not, write to the Free Software
 22  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 23  *
 24  */
 25 
 26 /* AK4113 registers */
 27 /* power down */
 28 #define AK4113_REG_PWRDN        0x00
 29 /* format control */
 30 #define AK4113_REG_FORMAT       0x01
 31 /* input/output control */
 32 #define AK4113_REG_IO0          0x02
 33 /* input/output control */
 34 #define AK4113_REG_IO1          0x03
 35 /* interrupt0 mask */
 36 #define AK4113_REG_INT0_MASK    0x04
 37 /* interrupt1 mask */
 38 #define AK4113_REG_INT1_MASK    0x05
 39 /* DAT mask & DTS select */
 40 #define AK4113_REG_DATDTS       0x06
 41 /* receiver status 0 */
 42 #define AK4113_REG_RCS0         0x07
 43 /* receiver status 1 */
 44 #define AK4113_REG_RCS1         0x08
 45 /* receiver status 2 */
 46 #define AK4113_REG_RCS2         0x09
 47 /* RX channel status byte 0 */
 48 #define AK4113_REG_RXCSB0       0x0a
 49 /* RX channel status byte 1 */
 50 #define AK4113_REG_RXCSB1       0x0b
 51 /* RX channel status byte 2 */
 52 #define AK4113_REG_RXCSB2       0x0c
 53 /* RX channel status byte 3 */
 54 #define AK4113_REG_RXCSB3       0x0d
 55 /* RX channel status byte 4 */
 56 #define AK4113_REG_RXCSB4       0x0e
 57 /* burst preamble Pc byte 0 */
 58 #define AK4113_REG_Pc0          0x0f
 59 /* burst preamble Pc byte 1 */
 60 #define AK4113_REG_Pc1          0x10
 61 /* burst preamble Pd byte 0 */
 62 #define AK4113_REG_Pd0          0x11
 63 /* burst preamble Pd byte 1 */
 64 #define AK4113_REG_Pd1          0x12
 65 /* Q-subcode address + control */
 66 #define AK4113_REG_QSUB_ADDR    0x13
 67 /* Q-subcode track */
 68 #define AK4113_REG_QSUB_TRACK   0x14
 69 /* Q-subcode index */
 70 #define AK4113_REG_QSUB_INDEX   0x15
 71 /* Q-subcode minute */
 72 #define AK4113_REG_QSUB_MINUTE  0x16
 73 /* Q-subcode second */
 74 #define AK4113_REG_QSUB_SECOND  0x17
 75 /* Q-subcode frame */
 76 #define AK4113_REG_QSUB_FRAME   0x18
 77 /* Q-subcode zero */
 78 #define AK4113_REG_QSUB_ZERO    0x19
 79 /* Q-subcode absolute minute */
 80 #define AK4113_REG_QSUB_ABSMIN  0x1a
 81 /* Q-subcode absolute second */
 82 #define AK4113_REG_QSUB_ABSSEC  0x1b
 83 /* Q-subcode absolute frame */
 84 #define AK4113_REG_QSUB_ABSFRM  0x1c
 85 
 86 /* sizes */
 87 #define AK4113_REG_RXCSB_SIZE   ((AK4113_REG_RXCSB4-AK4113_REG_RXCSB0)+1)
 88 #define AK4113_REG_QSUB_SIZE    ((AK4113_REG_QSUB_ABSFRM-AK4113_REG_QSUB_ADDR)\
 89                 +1)
 90 
 91 #define AK4113_WRITABLE_REGS    (AK4113_REG_DATDTS + 1)
 92 
 93 /* AK4113_REG_PWRDN bits */
 94 /* Channel Status Select */
 95 #define AK4113_CS12             (1<<7)
 96 /* Block Start & C/U Output Mode */
 97 #define AK4113_BCU              (1<<6)
 98 /* Master Clock Operation Select */
 99 #define AK4113_CM1              (1<<5)
100 /* Master Clock Operation Select */
101 #define AK4113_CM0              (1<<4)
102 /* Master Clock Frequency Select */
103 #define AK4113_OCKS1            (1<<3)
104 /* Master Clock Frequency Select */
105 #define AK4113_OCKS0            (1<<2)
106 /* 0 = power down, 1 = normal operation */
107 #define AK4113_PWN              (1<<1)
108 /* 0 = reset & initialize (except thisregister), 1 = normal operation */
109 #define AK4113_RST              (1<<0)
110 
111 /* AK4113_REQ_FORMAT bits */
112 /* V/TX Output select: 0 = Validity Flag Output, 1 = TX */
113 #define AK4113_VTX              (1<<7)
114 /* Audio Data Control */
115 #define AK4113_DIF2             (1<<6)
116 /* Audio Data Control */
117 #define AK4113_DIF1             (1<<5)
118 /* Audio Data Control */
119 #define AK4113_DIF0             (1<<4)
120 /* Deemphasis Autodetect Enable (1 = enable) */
121 #define AK4113_DEAU             (1<<3)
122 /* 32kHz-48kHz Deemphasis Control */
123 #define AK4113_DEM1             (1<<2)
124 /* 32kHz-48kHz Deemphasis Control */
125 #define AK4113_DEM0             (1<<1)
126 #define AK4113_DEM_OFF          (AK4113_DEM0)
127 #define AK4113_DEM_44KHZ        (0)
128 #define AK4113_DEM_48KHZ        (AK4113_DEM1)
129 #define AK4113_DEM_32KHZ        (AK4113_DEM0|AK4113_DEM1)
130 /* STDO: 16-bit, right justified */
131 #define AK4113_DIF_16R          (0)
132 /* STDO: 18-bit, right justified */
133 #define AK4113_DIF_18R          (AK4113_DIF0)
134 /* STDO: 20-bit, right justified */
135 #define AK4113_DIF_20R          (AK4113_DIF1)
136 /* STDO: 24-bit, right justified */
137 #define AK4113_DIF_24R          (AK4113_DIF1|AK4113_DIF0)
138 /* STDO: 24-bit, left justified */
139 #define AK4113_DIF_24L          (AK4113_DIF2)
140 /* STDO: I2S */
141 #define AK4113_DIF_24I2S        (AK4113_DIF2|AK4113_DIF0)
142 /* STDO: 24-bit, left justified; LRCLK, BICK = Input */
143 #define AK4113_DIF_I24L         (AK4113_DIF2|AK4113_DIF1)
144 /* STDO: I2S;  LRCLK, BICK = Input */
145 #define AK4113_DIF_I24I2S       (AK4113_DIF2|AK4113_DIF1|AK4113_DIF0)
146 
147 /* AK4113_REG_IO0 */
148 /* XTL1=0,XTL0=0 -> 11.2896Mhz; XTL1=0,XTL0=1 -> 12.288Mhz */
149 #define AK4113_XTL1             (1<<6)
150 /* XTL1=1,XTL0=0 -> 24.576Mhz; XTL1=1,XTL0=1 -> use channel status */
151 #define AK4113_XTL0             (1<<5)
152 /* Block Start Signal Output: 0 = U-bit, 1 = C-bit (req. BCU = 1) */
153 #define AK4113_UCE              (1<<4)
154 /* TX Output Enable (1 = enable) */
155 #define AK4113_TXE              (1<<3)
156 /* Output Through Data Selector for TX pin */
157 #define AK4113_OPS2             (1<<2)
158 /* Output Through Data Selector for TX pin */
159 #define AK4113_OPS1             (1<<1)
160 /* Output Through Data Selector for TX pin */
161 #define AK4113_OPS0             (1<<0)
162 /* 11.2896 MHz ref. Xtal freq. */
163 #define AK4113_XTL_11_2896M     (0)
164 /* 12.288 MHz ref. Xtal freq. */
165 #define AK4113_XTL_12_288M      (AK4113_XTL0)
166 /* 24.576 MHz ref. Xtal freq. */
167 #define AK4113_XTL_24_576M      (AK4113_XTL1)
168 
169 /* AK4113_REG_IO1 */
170 /* Interrupt 0 pin Hold */
171 #define AK4113_EFH1             (1<<7)
172 /* Interrupt 0 pin Hold */
173 #define AK4113_EFH0             (1<<6)
174 #define AK4113_EFH_512LRCLK     (0)
175 #define AK4113_EFH_1024LRCLK    (AK4113_EFH0)
176 #define AK4113_EFH_2048LRCLK    (AK4113_EFH1)
177 #define AK4113_EFH_4096LRCLK    (AK4113_EFH1|AK4113_EFH0)
178 /* PLL Lock Time: 0 = 384/fs, 1 = 1/fs */
179 #define AK4113_FAST             (1<<5)
180 /* MCKO2 Output Select: 0 = CMx/OCKSx, 1 = Xtal */
181 #define AK4113_XMCK             (1<<4)
182 /* MCKO2 Output Freq. Select: 0 = x1, 1 = x0.5  (req. XMCK = 1) */
183 #define AK4113_DIV              (1<<3)
184 /* Input Recovery Data Select */
185 #define AK4113_IPS2             (1<<2)
186 /* Input Recovery Data Select */
187 #define AK4113_IPS1             (1<<1)
188 /* Input Recovery Data Select */
189 #define AK4113_IPS0             (1<<0)
190 #define AK4113_IPS(x)           ((x)&7)
191 
192 /* AK4113_REG_INT0_MASK && AK4113_REG_INT1_MASK*/
193 /* mask enable for QINT bit */
194 #define AK4113_MQI              (1<<7)
195 /* mask enable for AUTO bit */
196 #define AK4113_MAUT             (1<<6)
197 /* mask enable for CINT bit */
198 #define AK4113_MCIT             (1<<5)
199 /* mask enable for UNLOCK bit */
200 #define AK4113_MULK             (1<<4)
201 /* mask enable for V bit */
202 #define AK4113_V                (1<<3)
203 /* mask enable for STC bit */
204 #define AK4113_STC              (1<<2)
205 /* mask enable for AUDN bit */
206 #define AK4113_MAN              (1<<1)
207 /* mask enable for PAR bit */
208 #define AK4113_MPR              (1<<0)
209 
210 /* AK4113_REG_DATDTS */
211 /* DAT Start ID Counter */
212 #define AK4113_DCNT             (1<<4)
213 /* DTS-CD 16-bit Sync Word Detect */
214 #define AK4113_DTS16            (1<<3)
215 /* DTS-CD 14-bit Sync Word Detect */
216 #define AK4113_DTS14            (1<<2)
217 /* mask enable for DAT bit (if 1, no INT1 effect */
218 #define AK4113_MDAT1            (1<<1)
219 /* mask enable for DAT bit (if 1, no INT0 effect */
220 #define AK4113_MDAT0            (1<<0)
221 
222 /* AK4113_REG_RCS0 */
223 /* Q-subcode buffer interrupt, 0 = no change, 1 = changed */
224 #define AK4113_QINT             (1<<7)
225 /* Non-PCM or DTS stream auto detection, 0 = no detect, 1 = detect */
226 #define AK4113_AUTO             (1<<6)
227 /* channel status buffer interrupt, 0 = no change, 1 = change */
228 #define AK4113_CINT             (1<<5)
229 /* PLL lock status, 0 = lock, 1 = unlock */
230 #define AK4113_UNLCK            (1<<4)
231 /* Validity bit, 0 = valid, 1 = invalid */
232 #define AK4113_V                (1<<3)
233 /* sampling frequency or Pre-emphasis change, 0 = no detect, 1 = detect */
234 #define AK4113_STC              (1<<2)
235 /* audio bit output, 0 = audio, 1 = non-audio */
236 #define AK4113_AUDION           (1<<1)
237 /* parity error or biphase error status, 0 = no error, 1 = error */
238 #define AK4113_PAR              (1<<0)
239 
240 /* AK4113_REG_RCS1 */
241 /* sampling frequency detection */
242 #define AK4113_FS3              (1<<7)
243 #define AK4113_FS2              (1<<6)
244 #define AK4113_FS1              (1<<5)
245 #define AK4113_FS0              (1<<4)
246 /* Pre-emphasis detect, 0 = OFF, 1 = ON */
247 #define AK4113_PEM              (1<<3)
248 /* DAT Start ID Detect, 0 = no detect, 1 = detect */
249 #define AK4113_DAT              (1<<2)
250 /* DTS-CD bit audio stream detect, 0 = no detect, 1 = detect */
251 #define AK4113_DTSCD            (1<<1)
252 /* Non-PCM bit stream detection, 0 = no detect, 1 = detect */
253 #define AK4113_NPCM             (1<<0)
254 #define AK4113_FS_8000HZ        (AK4113_FS3|AK4113_FS0)
255 #define AK4113_FS_11025HZ       (AK4113_FS2|AK4113_FS0)
256 #define AK4113_FS_16000HZ       (AK4113_FS2|AK4113_FS1|AK4113_FS0)
257 #define AK4113_FS_22050HZ       (AK4113_FS2)
258 #define AK4113_FS_24000HZ       (AK4113_FS2|AK4113_FS1)
259 #define AK4113_FS_32000HZ       (AK4113_FS1|AK4113_FS0)
260 #define AK4113_FS_44100HZ       (0)
261 #define AK4113_FS_48000HZ       (AK4113_FS1)
262 #define AK4113_FS_64000HZ       (AK4113_FS3|AK4113_FS1|AK4113_FS0)
263 #define AK4113_FS_88200HZ       (AK4113_FS3)
264 #define AK4113_FS_96000HZ       (AK4113_FS3|AK4113_FS1)
265 #define AK4113_FS_176400HZ      (AK4113_FS3|AK4113_FS2)
266 #define AK4113_FS_192000HZ      (AK4113_FS3|AK4113_FS2|AK4113_FS1)
267 
268 /* AK4113_REG_RCS2 */
269 /* CRC for Q-subcode, 0 = no error, 1 = error */
270 #define AK4113_QCRC             (1<<1)
271 /* CRC for channel status, 0 = no error, 1 = error */
272 #define AK4113_CCRC             (1<<0)
273 
274 /* flags for snd_ak4113_check_rate_and_errors() */
275 #define AK4113_CHECK_NO_STAT    (1<<0)  /* no statistics */
276 #define AK4113_CHECK_NO_RATE    (1<<1)  /* no rate check */
277 
278 #define AK4113_CONTROLS         13
279 
280 typedef void (ak4113_write_t)(void *private_data, unsigned char addr,
281                 unsigned char data);
282 typedef unsigned char (ak4113_read_t)(void *private_data, unsigned char addr);
283 
284 struct ak4113 {
285         struct snd_card *card;
286         ak4113_write_t *write;
287         ak4113_read_t *read;
288         void *private_data;
289         atomic_t wq_processing;
290         struct mutex reinit_mutex;
291         spinlock_t lock;
292         unsigned char regmap[AK4113_WRITABLE_REGS];
293         struct snd_kcontrol *kctls[AK4113_CONTROLS];
294         struct snd_pcm_substream *substream;
295         unsigned long parity_errors;
296         unsigned long v_bit_errors;
297         unsigned long qcrc_errors;
298         unsigned long ccrc_errors;
299         unsigned char rcs0;
300         unsigned char rcs1;
301         unsigned char rcs2;
302         struct delayed_work work;
303         unsigned int check_flags;
304         void *change_callback_private;
305         void (*change_callback)(struct ak4113 *ak4113, unsigned char c0,
306                         unsigned char c1);
307 };
308 
309 int snd_ak4113_create(struct snd_card *card, ak4113_read_t *read,
310                 ak4113_write_t *write,
311                 const unsigned char *pgm,
312                 void *private_data, struct ak4113 **r_ak4113);
313 void snd_ak4113_reg_write(struct ak4113 *ak4113, unsigned char reg,
314                 unsigned char mask, unsigned char val);
315 void snd_ak4113_reinit(struct ak4113 *ak4113);
316 int snd_ak4113_build(struct ak4113 *ak4113,
317                 struct snd_pcm_substream *capture_substream);
318 int snd_ak4113_external_rate(struct ak4113 *ak4113);
319 int snd_ak4113_check_rate_and_errors(struct ak4113 *ak4113, unsigned int flags);
320 
321 #ifdef CONFIG_PM
322 void snd_ak4113_suspend(struct ak4113 *chip);
323 void snd_ak4113_resume(struct ak4113 *chip);
324 #else
325 static inline void snd_ak4113_suspend(struct ak4113 *chip) {}
326 static inline void snd_ak4113_resume(struct ak4113 *chip) {}
327 #endif
328 
329 #endif /* __SOUND_AK4113_H */
330 
331 

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