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TOMOYO Linux Cross Reference
Linux/include/sound/wm8903.h

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  1 /*
  2  * linux/sound/wm8903.h -- Platform data for WM8903
  3  *
  4  * Copyright 2010 Wolfson Microelectronics. PLC.
  5  *
  6  * This program is free software; you can redistribute it and/or modify
  7  * it under the terms of the GNU General Public License version 2 as
  8  * published by the Free Software Foundation.
  9  */
 10 
 11 #ifndef __LINUX_SND_WM8903_H
 12 #define __LINUX_SND_WM8903_H
 13 
 14 /*
 15  * Used to enable configuration of a GPIO to all zeros; a gpio_cfg value of
 16  * zero in platform data means "don't touch this pin".
 17  */
 18 #define WM8903_GPIO_CONFIG_ZERO 0x8000
 19 
 20 /*
 21  * R6 (0x06) - Mic Bias Control 0
 22  */
 23 #define WM8903_MICDET_THR_MASK                  0x0030  /* MICDET_THR - [5:4] */
 24 #define WM8903_MICDET_THR_SHIFT                      4  /* MICDET_THR - [5:4] */
 25 #define WM8903_MICDET_THR_WIDTH                      2  /* MICDET_THR - [5:4] */
 26 #define WM8903_MICSHORT_THR_MASK                0x000C  /* MICSHORT_THR - [3:2] */
 27 #define WM8903_MICSHORT_THR_SHIFT                    2  /* MICSHORT_THR - [3:2] */
 28 #define WM8903_MICSHORT_THR_WIDTH                    2  /* MICSHORT_THR - [3:2] */
 29 #define WM8903_MICDET_ENA                       0x0002  /* MICDET_ENA */
 30 #define WM8903_MICDET_ENA_MASK                  0x0002  /* MICDET_ENA */
 31 #define WM8903_MICDET_ENA_SHIFT                      1  /* MICDET_ENA */
 32 #define WM8903_MICDET_ENA_WIDTH                      1  /* MICDET_ENA */
 33 #define WM8903_MICBIAS_ENA                      0x0001  /* MICBIAS_ENA */
 34 #define WM8903_MICBIAS_ENA_MASK                 0x0001  /* MICBIAS_ENA */
 35 #define WM8903_MICBIAS_ENA_SHIFT                     0  /* MICBIAS_ENA */
 36 #define WM8903_MICBIAS_ENA_WIDTH                     1  /* MICBIAS_ENA */
 37 
 38 /*
 39  * WM8903_GPn_FN values
 40  *
 41  * See datasheets for list of valid values per pin
 42  */
 43 #define WM8903_GPn_FN_GPIO_OUTPUT                    0
 44 #define WM8903_GPn_FN_BCLK                           1
 45 #define WM8903_GPn_FN_IRQ_OUTPT                      2
 46 #define WM8903_GPn_FN_GPIO_INPUT                     3
 47 #define WM8903_GPn_FN_MICBIAS_CURRENT_DETECT         4
 48 #define WM8903_GPn_FN_MICBIAS_SHORT_DETECT           5
 49 #define WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT             6
 50 #define WM8903_GPn_FN_FLL_LOCK_OUTPUT                8
 51 #define WM8903_GPn_FN_FLL_CLOCK_OUTPUT               9
 52 
 53 /*
 54  * R116 (0x74) - GPIO Control 1
 55  */
 56 #define WM8903_GP1_FN_MASK                      0x1F00  /* GP1_FN - [12:8] */
 57 #define WM8903_GP1_FN_SHIFT                          8  /* GP1_FN - [12:8] */
 58 #define WM8903_GP1_FN_WIDTH                          5  /* GP1_FN - [12:8] */
 59 #define WM8903_GP1_DIR                          0x0080  /* GP1_DIR */
 60 #define WM8903_GP1_DIR_MASK                     0x0080  /* GP1_DIR */
 61 #define WM8903_GP1_DIR_SHIFT                         7  /* GP1_DIR */
 62 #define WM8903_GP1_DIR_WIDTH                         1  /* GP1_DIR */
 63 #define WM8903_GP1_OP_CFG                       0x0040  /* GP1_OP_CFG */
 64 #define WM8903_GP1_OP_CFG_MASK                  0x0040  /* GP1_OP_CFG */
 65 #define WM8903_GP1_OP_CFG_SHIFT                      6  /* GP1_OP_CFG */
 66 #define WM8903_GP1_OP_CFG_WIDTH                      1  /* GP1_OP_CFG */
 67 #define WM8903_GP1_IP_CFG                       0x0020  /* GP1_IP_CFG */
 68 #define WM8903_GP1_IP_CFG_MASK                  0x0020  /* GP1_IP_CFG */
 69 #define WM8903_GP1_IP_CFG_SHIFT                      5  /* GP1_IP_CFG */
 70 #define WM8903_GP1_IP_CFG_WIDTH                      1  /* GP1_IP_CFG */
 71 #define WM8903_GP1_LVL                          0x0010  /* GP1_LVL */
 72 #define WM8903_GP1_LVL_MASK                     0x0010  /* GP1_LVL */
 73 #define WM8903_GP1_LVL_SHIFT                         4  /* GP1_LVL */
 74 #define WM8903_GP1_LVL_WIDTH                         1  /* GP1_LVL */
 75 #define WM8903_GP1_PD                           0x0008  /* GP1_PD */
 76 #define WM8903_GP1_PD_MASK                      0x0008  /* GP1_PD */
 77 #define WM8903_GP1_PD_SHIFT                          3  /* GP1_PD */
 78 #define WM8903_GP1_PD_WIDTH                          1  /* GP1_PD */
 79 #define WM8903_GP1_PU                           0x0004  /* GP1_PU */
 80 #define WM8903_GP1_PU_MASK                      0x0004  /* GP1_PU */
 81 #define WM8903_GP1_PU_SHIFT                          2  /* GP1_PU */
 82 #define WM8903_GP1_PU_WIDTH                          1  /* GP1_PU */
 83 #define WM8903_GP1_INTMODE                      0x0002  /* GP1_INTMODE */
 84 #define WM8903_GP1_INTMODE_MASK                 0x0002  /* GP1_INTMODE */
 85 #define WM8903_GP1_INTMODE_SHIFT                     1  /* GP1_INTMODE */
 86 #define WM8903_GP1_INTMODE_WIDTH                     1  /* GP1_INTMODE */
 87 #define WM8903_GP1_DB                           0x0001  /* GP1_DB */
 88 #define WM8903_GP1_DB_MASK                      0x0001  /* GP1_DB */
 89 #define WM8903_GP1_DB_SHIFT                          0  /* GP1_DB */
 90 #define WM8903_GP1_DB_WIDTH                          1  /* GP1_DB */
 91 
 92 /*
 93  * R117 (0x75) - GPIO Control 2
 94  */
 95 #define WM8903_GP2_FN_MASK                      0x1F00  /* GP2_FN - [12:8] */
 96 #define WM8903_GP2_FN_SHIFT                          8  /* GP2_FN - [12:8] */
 97 #define WM8903_GP2_FN_WIDTH                          5  /* GP2_FN - [12:8] */
 98 #define WM8903_GP2_DIR                          0x0080  /* GP2_DIR */
 99 #define WM8903_GP2_DIR_MASK                     0x0080  /* GP2_DIR */
100 #define WM8903_GP2_DIR_SHIFT                         7  /* GP2_DIR */
101 #define WM8903_GP2_DIR_WIDTH                         1  /* GP2_DIR */
102 #define WM8903_GP2_OP_CFG                       0x0040  /* GP2_OP_CFG */
103 #define WM8903_GP2_OP_CFG_MASK                  0x0040  /* GP2_OP_CFG */
104 #define WM8903_GP2_OP_CFG_SHIFT                      6  /* GP2_OP_CFG */
105 #define WM8903_GP2_OP_CFG_WIDTH                      1  /* GP2_OP_CFG */
106 #define WM8903_GP2_IP_CFG                       0x0020  /* GP2_IP_CFG */
107 #define WM8903_GP2_IP_CFG_MASK                  0x0020  /* GP2_IP_CFG */
108 #define WM8903_GP2_IP_CFG_SHIFT                      5  /* GP2_IP_CFG */
109 #define WM8903_GP2_IP_CFG_WIDTH                      1  /* GP2_IP_CFG */
110 #define WM8903_GP2_LVL                          0x0010  /* GP2_LVL */
111 #define WM8903_GP2_LVL_MASK                     0x0010  /* GP2_LVL */
112 #define WM8903_GP2_LVL_SHIFT                         4  /* GP2_LVL */
113 #define WM8903_GP2_LVL_WIDTH                         1  /* GP2_LVL */
114 #define WM8903_GP2_PD                           0x0008  /* GP2_PD */
115 #define WM8903_GP2_PD_MASK                      0x0008  /* GP2_PD */
116 #define WM8903_GP2_PD_SHIFT                          3  /* GP2_PD */
117 #define WM8903_GP2_PD_WIDTH                          1  /* GP2_PD */
118 #define WM8903_GP2_PU                           0x0004  /* GP2_PU */
119 #define WM8903_GP2_PU_MASK                      0x0004  /* GP2_PU */
120 #define WM8903_GP2_PU_SHIFT                          2  /* GP2_PU */
121 #define WM8903_GP2_PU_WIDTH                          1  /* GP2_PU */
122 #define WM8903_GP2_INTMODE                      0x0002  /* GP2_INTMODE */
123 #define WM8903_GP2_INTMODE_MASK                 0x0002  /* GP2_INTMODE */
124 #define WM8903_GP2_INTMODE_SHIFT                     1  /* GP2_INTMODE */
125 #define WM8903_GP2_INTMODE_WIDTH                     1  /* GP2_INTMODE */
126 #define WM8903_GP2_DB                           0x0001  /* GP2_DB */
127 #define WM8903_GP2_DB_MASK                      0x0001  /* GP2_DB */
128 #define WM8903_GP2_DB_SHIFT                          0  /* GP2_DB */
129 #define WM8903_GP2_DB_WIDTH                          1  /* GP2_DB */
130 
131 /*
132  * R118 (0x76) - GPIO Control 3
133  */
134 #define WM8903_GP3_FN_MASK                      0x1F00  /* GP3_FN - [12:8] */
135 #define WM8903_GP3_FN_SHIFT                          8  /* GP3_FN - [12:8] */
136 #define WM8903_GP3_FN_WIDTH                          5  /* GP3_FN - [12:8] */
137 #define WM8903_GP3_DIR                          0x0080  /* GP3_DIR */
138 #define WM8903_GP3_DIR_MASK                     0x0080  /* GP3_DIR */
139 #define WM8903_GP3_DIR_SHIFT                         7  /* GP3_DIR */
140 #define WM8903_GP3_DIR_WIDTH                         1  /* GP3_DIR */
141 #define WM8903_GP3_OP_CFG                       0x0040  /* GP3_OP_CFG */
142 #define WM8903_GP3_OP_CFG_MASK                  0x0040  /* GP3_OP_CFG */
143 #define WM8903_GP3_OP_CFG_SHIFT                      6  /* GP3_OP_CFG */
144 #define WM8903_GP3_OP_CFG_WIDTH                      1  /* GP3_OP_CFG */
145 #define WM8903_GP3_IP_CFG                       0x0020  /* GP3_IP_CFG */
146 #define WM8903_GP3_IP_CFG_MASK                  0x0020  /* GP3_IP_CFG */
147 #define WM8903_GP3_IP_CFG_SHIFT                      5  /* GP3_IP_CFG */
148 #define WM8903_GP3_IP_CFG_WIDTH                      1  /* GP3_IP_CFG */
149 #define WM8903_GP3_LVL                          0x0010  /* GP3_LVL */
150 #define WM8903_GP3_LVL_MASK                     0x0010  /* GP3_LVL */
151 #define WM8903_GP3_LVL_SHIFT                         4  /* GP3_LVL */
152 #define WM8903_GP3_LVL_WIDTH                         1  /* GP3_LVL */
153 #define WM8903_GP3_PD                           0x0008  /* GP3_PD */
154 #define WM8903_GP3_PD_MASK                      0x0008  /* GP3_PD */
155 #define WM8903_GP3_PD_SHIFT                          3  /* GP3_PD */
156 #define WM8903_GP3_PD_WIDTH                          1  /* GP3_PD */
157 #define WM8903_GP3_PU                           0x0004  /* GP3_PU */
158 #define WM8903_GP3_PU_MASK                      0x0004  /* GP3_PU */
159 #define WM8903_GP3_PU_SHIFT                          2  /* GP3_PU */
160 #define WM8903_GP3_PU_WIDTH                          1  /* GP3_PU */
161 #define WM8903_GP3_INTMODE                      0x0002  /* GP3_INTMODE */
162 #define WM8903_GP3_INTMODE_MASK                 0x0002  /* GP3_INTMODE */
163 #define WM8903_GP3_INTMODE_SHIFT                     1  /* GP3_INTMODE */
164 #define WM8903_GP3_INTMODE_WIDTH                     1  /* GP3_INTMODE */
165 #define WM8903_GP3_DB                           0x0001  /* GP3_DB */
166 #define WM8903_GP3_DB_MASK                      0x0001  /* GP3_DB */
167 #define WM8903_GP3_DB_SHIFT                          0  /* GP3_DB */
168 #define WM8903_GP3_DB_WIDTH                          1  /* GP3_DB */
169 
170 /*
171  * R119 (0x77) - GPIO Control 4
172  */
173 #define WM8903_GP4_FN_MASK                      0x1F00  /* GP4_FN - [12:8] */
174 #define WM8903_GP4_FN_SHIFT                          8  /* GP4_FN - [12:8] */
175 #define WM8903_GP4_FN_WIDTH                          5  /* GP4_FN - [12:8] */
176 #define WM8903_GP4_DIR                          0x0080  /* GP4_DIR */
177 #define WM8903_GP4_DIR_MASK                     0x0080  /* GP4_DIR */
178 #define WM8903_GP4_DIR_SHIFT                         7  /* GP4_DIR */
179 #define WM8903_GP4_DIR_WIDTH                         1  /* GP4_DIR */
180 #define WM8903_GP4_OP_CFG                       0x0040  /* GP4_OP_CFG */
181 #define WM8903_GP4_OP_CFG_MASK                  0x0040  /* GP4_OP_CFG */
182 #define WM8903_GP4_OP_CFG_SHIFT                      6  /* GP4_OP_CFG */
183 #define WM8903_GP4_OP_CFG_WIDTH                      1  /* GP4_OP_CFG */
184 #define WM8903_GP4_IP_CFG                       0x0020  /* GP4_IP_CFG */
185 #define WM8903_GP4_IP_CFG_MASK                  0x0020  /* GP4_IP_CFG */
186 #define WM8903_GP4_IP_CFG_SHIFT                      5  /* GP4_IP_CFG */
187 #define WM8903_GP4_IP_CFG_WIDTH                      1  /* GP4_IP_CFG */
188 #define WM8903_GP4_LVL                          0x0010  /* GP4_LVL */
189 #define WM8903_GP4_LVL_MASK                     0x0010  /* GP4_LVL */
190 #define WM8903_GP4_LVL_SHIFT                         4  /* GP4_LVL */
191 #define WM8903_GP4_LVL_WIDTH                         1  /* GP4_LVL */
192 #define WM8903_GP4_PD                           0x0008  /* GP4_PD */
193 #define WM8903_GP4_PD_MASK                      0x0008  /* GP4_PD */
194 #define WM8903_GP4_PD_SHIFT                          3  /* GP4_PD */
195 #define WM8903_GP4_PD_WIDTH                          1  /* GP4_PD */
196 #define WM8903_GP4_PU                           0x0004  /* GP4_PU */
197 #define WM8903_GP4_PU_MASK                      0x0004  /* GP4_PU */
198 #define WM8903_GP4_PU_SHIFT                          2  /* GP4_PU */
199 #define WM8903_GP4_PU_WIDTH                          1  /* GP4_PU */
200 #define WM8903_GP4_INTMODE                      0x0002  /* GP4_INTMODE */
201 #define WM8903_GP4_INTMODE_MASK                 0x0002  /* GP4_INTMODE */
202 #define WM8903_GP4_INTMODE_SHIFT                     1  /* GP4_INTMODE */
203 #define WM8903_GP4_INTMODE_WIDTH                     1  /* GP4_INTMODE */
204 #define WM8903_GP4_DB                           0x0001  /* GP4_DB */
205 #define WM8903_GP4_DB_MASK                      0x0001  /* GP4_DB */
206 #define WM8903_GP4_DB_SHIFT                          0  /* GP4_DB */
207 #define WM8903_GP4_DB_WIDTH                          1  /* GP4_DB */
208 
209 /*
210  * R120 (0x78) - GPIO Control 5
211  */
212 #define WM8903_GP5_FN_MASK                      0x1F00  /* GP5_FN - [12:8] */
213 #define WM8903_GP5_FN_SHIFT                          8  /* GP5_FN - [12:8] */
214 #define WM8903_GP5_FN_WIDTH                          5  /* GP5_FN - [12:8] */
215 #define WM8903_GP5_DIR                          0x0080  /* GP5_DIR */
216 #define WM8903_GP5_DIR_MASK                     0x0080  /* GP5_DIR */
217 #define WM8903_GP5_DIR_SHIFT                         7  /* GP5_DIR */
218 #define WM8903_GP5_DIR_WIDTH                         1  /* GP5_DIR */
219 #define WM8903_GP5_OP_CFG                       0x0040  /* GP5_OP_CFG */
220 #define WM8903_GP5_OP_CFG_MASK                  0x0040  /* GP5_OP_CFG */
221 #define WM8903_GP5_OP_CFG_SHIFT                      6  /* GP5_OP_CFG */
222 #define WM8903_GP5_OP_CFG_WIDTH                      1  /* GP5_OP_CFG */
223 #define WM8903_GP5_IP_CFG                       0x0020  /* GP5_IP_CFG */
224 #define WM8903_GP5_IP_CFG_MASK                  0x0020  /* GP5_IP_CFG */
225 #define WM8903_GP5_IP_CFG_SHIFT                      5  /* GP5_IP_CFG */
226 #define WM8903_GP5_IP_CFG_WIDTH                      1  /* GP5_IP_CFG */
227 #define WM8903_GP5_LVL                          0x0010  /* GP5_LVL */
228 #define WM8903_GP5_LVL_MASK                     0x0010  /* GP5_LVL */
229 #define WM8903_GP5_LVL_SHIFT                         4  /* GP5_LVL */
230 #define WM8903_GP5_LVL_WIDTH                         1  /* GP5_LVL */
231 #define WM8903_GP5_PD                           0x0008  /* GP5_PD */
232 #define WM8903_GP5_PD_MASK                      0x0008  /* GP5_PD */
233 #define WM8903_GP5_PD_SHIFT                          3  /* GP5_PD */
234 #define WM8903_GP5_PD_WIDTH                          1  /* GP5_PD */
235 #define WM8903_GP5_PU                           0x0004  /* GP5_PU */
236 #define WM8903_GP5_PU_MASK                      0x0004  /* GP5_PU */
237 #define WM8903_GP5_PU_SHIFT                          2  /* GP5_PU */
238 #define WM8903_GP5_PU_WIDTH                          1  /* GP5_PU */
239 #define WM8903_GP5_INTMODE                      0x0002  /* GP5_INTMODE */
240 #define WM8903_GP5_INTMODE_MASK                 0x0002  /* GP5_INTMODE */
241 #define WM8903_GP5_INTMODE_SHIFT                     1  /* GP5_INTMODE */
242 #define WM8903_GP5_INTMODE_WIDTH                     1  /* GP5_INTMODE */
243 #define WM8903_GP5_DB                           0x0001  /* GP5_DB */
244 #define WM8903_GP5_DB_MASK                      0x0001  /* GP5_DB */
245 #define WM8903_GP5_DB_SHIFT                          0  /* GP5_DB */
246 #define WM8903_GP5_DB_WIDTH                          1  /* GP5_DB */
247 
248 #define WM8903_NUM_GPIO 5
249 
250 struct wm8903_platform_data {
251         bool irq_active_low;   /* Set if IRQ active low, default high */
252 
253         /* Default register value for R6 (Mic bias), used to configure
254          * microphone detection.  In conjunction with gpio_cfg this
255          * can be used to route the microphone status signals out onto
256          * the GPIOs for use with snd_soc_jack_add_gpios().
257          */
258         u16 micdet_cfg;
259 
260         int micdet_delay;      /* Delay after microphone detection (ms) */
261 
262         int gpio_base;
263         u32 gpio_cfg[WM8903_NUM_GPIO]; /* Default register values for GPIO pin mux */
264 };
265 
266 #endif
267 

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