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TOMOYO Linux Cross Reference
Linux/include/video/imx-ipu-v3.h

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  1 /*
  2  * Copyright 2005-2009 Freescale Semiconductor, Inc.
  3  *
  4  * The code contained herein is licensed under the GNU Lesser General
  5  * Public License.  You may obtain a copy of the GNU Lesser General
  6  * Public License Version 2.1 or later at the following locations:
  7  *
  8  * http://www.opensource.org/licenses/lgpl-license.html
  9  * http://www.gnu.org/copyleft/lgpl.html
 10  */
 11 
 12 #ifndef __DRM_IPU_H__
 13 #define __DRM_IPU_H__
 14 
 15 #include <linux/types.h>
 16 #include <linux/videodev2.h>
 17 #include <linux/bitmap.h>
 18 #include <linux/fb.h>
 19 #include <media/v4l2-mediabus.h>
 20 #include <video/videomode.h>
 21 
 22 struct ipu_soc;
 23 
 24 enum ipuv3_type {
 25         IPUV3EX,
 26         IPUV3M,
 27         IPUV3H,
 28 };
 29 
 30 #define IPU_PIX_FMT_GBR24       v4l2_fourcc('G', 'B', 'R', '3')
 31 
 32 /*
 33  * Bitfield of Display Interface signal polarities.
 34  */
 35 struct ipu_di_signal_cfg {
 36         unsigned data_pol:1;    /* true = inverted */
 37         unsigned clk_pol:1;     /* true = rising edge */
 38         unsigned enable_pol:1;
 39 
 40         struct videomode mode;
 41 
 42         u32 bus_format;
 43         u32 v_to_h_sync;
 44 
 45 #define IPU_DI_CLKMODE_SYNC     (1 << 0)
 46 #define IPU_DI_CLKMODE_EXT      (1 << 1)
 47         unsigned long clkflags;
 48 
 49         u8 hsync_pin;
 50         u8 vsync_pin;
 51 };
 52 
 53 /*
 54  * Enumeration of CSI destinations
 55  */
 56 enum ipu_csi_dest {
 57         IPU_CSI_DEST_IDMAC, /* to memory via SMFC */
 58         IPU_CSI_DEST_IC,        /* to Image Converter */
 59         IPU_CSI_DEST_VDIC,  /* to VDIC */
 60 };
 61 
 62 /*
 63  * Enumeration of IPU rotation modes
 64  */
 65 enum ipu_rotate_mode {
 66         IPU_ROTATE_NONE = 0,
 67         IPU_ROTATE_VERT_FLIP,
 68         IPU_ROTATE_HORIZ_FLIP,
 69         IPU_ROTATE_180,
 70         IPU_ROTATE_90_RIGHT,
 71         IPU_ROTATE_90_RIGHT_VFLIP,
 72         IPU_ROTATE_90_RIGHT_HFLIP,
 73         IPU_ROTATE_90_LEFT,
 74 };
 75 
 76 enum ipu_color_space {
 77         IPUV3_COLORSPACE_RGB,
 78         IPUV3_COLORSPACE_YUV,
 79         IPUV3_COLORSPACE_UNKNOWN,
 80 };
 81 
 82 struct ipuv3_channel;
 83 
 84 enum ipu_channel_irq {
 85         IPU_IRQ_EOF = 0,
 86         IPU_IRQ_NFACK = 64,
 87         IPU_IRQ_NFB4EOF = 128,
 88         IPU_IRQ_EOS = 192,
 89 };
 90 
 91 /*
 92  * Enumeration of IDMAC channels
 93  */
 94 #define IPUV3_CHANNEL_CSI0                       0
 95 #define IPUV3_CHANNEL_CSI1                       1
 96 #define IPUV3_CHANNEL_CSI2                       2
 97 #define IPUV3_CHANNEL_CSI3                       3
 98 #define IPUV3_CHANNEL_VDI_MEM_IC_VF              5
 99 #define IPUV3_CHANNEL_MEM_IC_PP                 11
100 #define IPUV3_CHANNEL_MEM_IC_PRP_VF             12
101 #define IPUV3_CHANNEL_G_MEM_IC_PRP_VF           14
102 #define IPUV3_CHANNEL_G_MEM_IC_PP               15
103 #define IPUV3_CHANNEL_IC_PRP_ENC_MEM            20
104 #define IPUV3_CHANNEL_IC_PRP_VF_MEM             21
105 #define IPUV3_CHANNEL_IC_PP_MEM                 22
106 #define IPUV3_CHANNEL_MEM_BG_SYNC               23
107 #define IPUV3_CHANNEL_MEM_BG_ASYNC              24
108 #define IPUV3_CHANNEL_MEM_FG_SYNC               27
109 #define IPUV3_CHANNEL_MEM_DC_SYNC               28
110 #define IPUV3_CHANNEL_MEM_FG_ASYNC              29
111 #define IPUV3_CHANNEL_MEM_FG_SYNC_ALPHA         31
112 #define IPUV3_CHANNEL_MEM_DC_ASYNC              41
113 #define IPUV3_CHANNEL_MEM_ROT_ENC               45
114 #define IPUV3_CHANNEL_MEM_ROT_VF                46
115 #define IPUV3_CHANNEL_MEM_ROT_PP                47
116 #define IPUV3_CHANNEL_ROT_ENC_MEM               48
117 #define IPUV3_CHANNEL_ROT_VF_MEM                49
118 #define IPUV3_CHANNEL_ROT_PP_MEM                50
119 #define IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA         51
120 
121 int ipu_map_irq(struct ipu_soc *ipu, int irq);
122 int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
123                 enum ipu_channel_irq irq);
124 
125 #define IPU_IRQ_DP_SF_START             (448 + 2)
126 #define IPU_IRQ_DP_SF_END               (448 + 3)
127 #define IPU_IRQ_BG_SF_END               IPU_IRQ_DP_SF_END,
128 #define IPU_IRQ_DC_FC_0                 (448 + 8)
129 #define IPU_IRQ_DC_FC_1                 (448 + 9)
130 #define IPU_IRQ_DC_FC_2                 (448 + 10)
131 #define IPU_IRQ_DC_FC_3                 (448 + 11)
132 #define IPU_IRQ_DC_FC_4                 (448 + 12)
133 #define IPU_IRQ_DC_FC_6                 (448 + 13)
134 #define IPU_IRQ_VSYNC_PRE_0             (448 + 14)
135 #define IPU_IRQ_VSYNC_PRE_1             (448 + 15)
136 
137 /*
138  * IPU Common functions
139  */
140 void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2);
141 void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi);
142 void ipu_dump(struct ipu_soc *ipu);
143 
144 /*
145  * IPU Image DMA Controller (idmac) functions
146  */
147 struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned channel);
148 void ipu_idmac_put(struct ipuv3_channel *);
149 
150 int ipu_idmac_enable_channel(struct ipuv3_channel *channel);
151 int ipu_idmac_disable_channel(struct ipuv3_channel *channel);
152 void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable);
153 int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts);
154 int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms);
155 
156 void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
157                 bool doublebuffer);
158 int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel);
159 bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num);
160 void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num);
161 void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num);
162 
163 /*
164  * IPU Channel Parameter Memory (cpmem) functions
165  */
166 struct ipu_rgb {
167         struct fb_bitfield      red;
168         struct fb_bitfield      green;
169         struct fb_bitfield      blue;
170         struct fb_bitfield      transp;
171         int                     bits_per_pixel;
172 };
173 
174 struct ipu_image {
175         struct v4l2_pix_format pix;
176         struct v4l2_rect rect;
177         dma_addr_t phys0;
178         dma_addr_t phys1;
179 };
180 
181 void ipu_cpmem_zero(struct ipuv3_channel *ch);
182 void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int xres, int yres);
183 void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride);
184 void ipu_cpmem_set_high_priority(struct ipuv3_channel *ch);
185 void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf);
186 void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride);
187 void ipu_cpmem_set_axi_id(struct ipuv3_channel *ch, u32 id);
188 void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize);
189 void ipu_cpmem_set_block_mode(struct ipuv3_channel *ch);
190 void ipu_cpmem_set_rotation(struct ipuv3_channel *ch,
191                             enum ipu_rotate_mode rot);
192 int ipu_cpmem_set_format_rgb(struct ipuv3_channel *ch,
193                              const struct ipu_rgb *rgb);
194 int ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width);
195 void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format);
196 void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch,
197                                    u32 pixel_format, int stride,
198                                    int u_offset, int v_offset);
199 void ipu_cpmem_set_yuv_planar(struct ipuv3_channel *ch,
200                               u32 pixel_format, int stride, int height);
201 int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc);
202 int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image);
203 void ipu_cpmem_dump(struct ipuv3_channel *ch);
204 
205 /*
206  * IPU Display Controller (dc) functions
207  */
208 struct ipu_dc;
209 struct ipu_di;
210 struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel);
211 void ipu_dc_put(struct ipu_dc *dc);
212 int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
213                 u32 pixel_fmt, u32 width);
214 void ipu_dc_enable(struct ipu_soc *ipu);
215 void ipu_dc_enable_channel(struct ipu_dc *dc);
216 void ipu_dc_disable_channel(struct ipu_dc *dc);
217 void ipu_dc_disable(struct ipu_soc *ipu);
218 
219 /*
220  * IPU Display Interface (di) functions
221  */
222 struct ipu_di *ipu_di_get(struct ipu_soc *ipu, int disp);
223 void ipu_di_put(struct ipu_di *);
224 int ipu_di_disable(struct ipu_di *);
225 int ipu_di_enable(struct ipu_di *);
226 int ipu_di_get_num(struct ipu_di *);
227 int ipu_di_adjust_videomode(struct ipu_di *di, struct videomode *mode);
228 int ipu_di_init_sync_panel(struct ipu_di *, struct ipu_di_signal_cfg *sig);
229 
230 /*
231  * IPU Display Multi FIFO Controller (dmfc) functions
232  */
233 struct dmfc_channel;
234 int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc);
235 void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc);
236 int ipu_dmfc_alloc_bandwidth(struct dmfc_channel *dmfc,
237                 unsigned long bandwidth_mbs, int burstsize);
238 void ipu_dmfc_free_bandwidth(struct dmfc_channel *dmfc);
239 int ipu_dmfc_init_channel(struct dmfc_channel *dmfc, int width);
240 struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipuv3_channel);
241 void ipu_dmfc_put(struct dmfc_channel *dmfc);
242 
243 /*
244  * IPU Display Processor (dp) functions
245  */
246 #define IPU_DP_FLOW_SYNC_BG     0
247 #define IPU_DP_FLOW_SYNC_FG     1
248 #define IPU_DP_FLOW_ASYNC0_BG   2
249 #define IPU_DP_FLOW_ASYNC0_FG   3
250 #define IPU_DP_FLOW_ASYNC1_BG   4
251 #define IPU_DP_FLOW_ASYNC1_FG   5
252 
253 struct ipu_dp *ipu_dp_get(struct ipu_soc *ipu, unsigned int flow);
254 void ipu_dp_put(struct ipu_dp *);
255 int ipu_dp_enable(struct ipu_soc *ipu);
256 int ipu_dp_enable_channel(struct ipu_dp *dp);
257 void ipu_dp_disable_channel(struct ipu_dp *dp);
258 void ipu_dp_disable(struct ipu_soc *ipu);
259 int ipu_dp_setup_channel(struct ipu_dp *dp,
260                 enum ipu_color_space in, enum ipu_color_space out);
261 int ipu_dp_set_window_pos(struct ipu_dp *, u16 x_pos, u16 y_pos);
262 int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable, u8 alpha,
263                 bool bg_chan);
264 
265 /*
266  * IPU CMOS Sensor Interface (csi) functions
267  */
268 struct ipu_csi;
269 int ipu_csi_init_interface(struct ipu_csi *csi,
270                            struct v4l2_mbus_config *mbus_cfg,
271                            struct v4l2_mbus_framefmt *mbus_fmt);
272 bool ipu_csi_is_interlaced(struct ipu_csi *csi);
273 void ipu_csi_get_window(struct ipu_csi *csi, struct v4l2_rect *w);
274 void ipu_csi_set_window(struct ipu_csi *csi, struct v4l2_rect *w);
275 void ipu_csi_set_test_generator(struct ipu_csi *csi, bool active,
276                                 u32 r_value, u32 g_value, u32 b_value,
277                                 u32 pix_clk);
278 int ipu_csi_set_mipi_datatype(struct ipu_csi *csi, u32 vc,
279                               struct v4l2_mbus_framefmt *mbus_fmt);
280 int ipu_csi_set_skip_smfc(struct ipu_csi *csi, u32 skip,
281                           u32 max_ratio, u32 id);
282 int ipu_csi_set_dest(struct ipu_csi *csi, enum ipu_csi_dest csi_dest);
283 int ipu_csi_enable(struct ipu_csi *csi);
284 int ipu_csi_disable(struct ipu_csi *csi);
285 struct ipu_csi *ipu_csi_get(struct ipu_soc *ipu, int id);
286 void ipu_csi_put(struct ipu_csi *csi);
287 void ipu_csi_dump(struct ipu_csi *csi);
288 
289 /*
290  * IPU Image Converter (ic) functions
291  */
292 enum ipu_ic_task {
293         IC_TASK_ENCODER,
294         IC_TASK_VIEWFINDER,
295         IC_TASK_POST_PROCESSOR,
296         IC_NUM_TASKS,
297 };
298 
299 struct ipu_ic;
300 int ipu_ic_task_init(struct ipu_ic *ic,
301                      int in_width, int in_height,
302                      int out_width, int out_height,
303                      enum ipu_color_space in_cs,
304                      enum ipu_color_space out_cs);
305 int ipu_ic_task_graphics_init(struct ipu_ic *ic,
306                               enum ipu_color_space in_g_cs,
307                               bool galpha_en, u32 galpha,
308                               bool colorkey_en, u32 colorkey);
309 void ipu_ic_task_enable(struct ipu_ic *ic);
310 void ipu_ic_task_disable(struct ipu_ic *ic);
311 int ipu_ic_task_idma_init(struct ipu_ic *ic, struct ipuv3_channel *channel,
312                           u32 width, u32 height, int burst_size,
313                           enum ipu_rotate_mode rot);
314 int ipu_ic_enable(struct ipu_ic *ic);
315 int ipu_ic_disable(struct ipu_ic *ic);
316 struct ipu_ic *ipu_ic_get(struct ipu_soc *ipu, enum ipu_ic_task task);
317 void ipu_ic_put(struct ipu_ic *ic);
318 void ipu_ic_dump(struct ipu_ic *ic);
319 
320 /*
321  * IPU Sensor Multiple FIFO Controller (SMFC) functions
322  */
323 struct ipu_smfc *ipu_smfc_get(struct ipu_soc *ipu, unsigned int chno);
324 void ipu_smfc_put(struct ipu_smfc *smfc);
325 int ipu_smfc_enable(struct ipu_smfc *smfc);
326 int ipu_smfc_disable(struct ipu_smfc *smfc);
327 int ipu_smfc_map_channel(struct ipu_smfc *smfc, int csi_id, int mipi_id);
328 int ipu_smfc_set_burstsize(struct ipu_smfc *smfc, int burstsize);
329 int ipu_smfc_set_watermark(struct ipu_smfc *smfc, u32 set_level, u32 clr_level);
330 
331 enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc);
332 enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat);
333 enum ipu_color_space ipu_mbus_code_to_colorspace(u32 mbus_code);
334 int ipu_stride_to_bytes(u32 pixel_stride, u32 pixelformat);
335 bool ipu_pixelformat_is_planar(u32 pixelformat);
336 int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees,
337                             bool hflip, bool vflip);
338 int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode,
339                             bool hflip, bool vflip);
340 
341 struct ipu_client_platformdata {
342         int csi;
343         int di;
344         int dc;
345         int dp;
346         int dmfc;
347         int dma[2];
348 };
349 
350 #endif /* __DRM_IPU_H__ */
351 

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