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TOMOYO Linux Cross Reference
Linux/include/video/sh_mobile_lcdc.h

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  1 /* SPDX-License-Identifier: GPL-2.0 */
  2 #ifndef __ASM_SH_MOBILE_LCDC_H__
  3 #define __ASM_SH_MOBILE_LCDC_H__
  4 
  5 #include <linux/fb.h>
  6 
  7 /* Register definitions */
  8 #define _LDDCKR                 0x410
  9 #define LDDCKR_ICKSEL_BUS       (0 << 16)
 10 #define LDDCKR_ICKSEL_MIPI      (1 << 16)
 11 #define LDDCKR_ICKSEL_HDMI      (2 << 16)
 12 #define LDDCKR_ICKSEL_EXT       (3 << 16)
 13 #define LDDCKR_ICKSEL_MASK      (7 << 16)
 14 #define LDDCKR_MOSEL            (1 << 6)
 15 #define _LDDCKSTPR              0x414
 16 #define _LDINTR                 0x468
 17 #define LDINTR_FE               (1 << 10)
 18 #define LDINTR_VSE              (1 << 9)
 19 #define LDINTR_VEE              (1 << 8)
 20 #define LDINTR_FS               (1 << 2)
 21 #define LDINTR_VSS              (1 << 1)
 22 #define LDINTR_VES              (1 << 0)
 23 #define LDINTR_STATUS_MASK      (0xff << 0)
 24 #define _LDSR                   0x46c
 25 #define LDSR_MSS                (1 << 10)
 26 #define LDSR_MRS                (1 << 8)
 27 #define LDSR_AS                 (1 << 1)
 28 #define _LDCNT1R                0x470
 29 #define LDCNT1R_DE              (1 << 0)
 30 #define _LDCNT2R                0x474
 31 #define LDCNT2R_BR              (1 << 8)
 32 #define LDCNT2R_MD              (1 << 3)
 33 #define LDCNT2R_SE              (1 << 2)
 34 #define LDCNT2R_ME              (1 << 1)
 35 #define LDCNT2R_DO              (1 << 0)
 36 #define _LDRCNTR                0x478
 37 #define LDRCNTR_SRS             (1 << 17)
 38 #define LDRCNTR_SRC             (1 << 16)
 39 #define LDRCNTR_MRS             (1 << 1)
 40 #define LDRCNTR_MRC             (1 << 0)
 41 #define _LDDDSR                 0x47c
 42 #define LDDDSR_LS               (1 << 2)
 43 #define LDDDSR_WS               (1 << 1)
 44 #define LDDDSR_BS               (1 << 0)
 45 
 46 #define LDMT1R_VPOL             (1 << 28)
 47 #define LDMT1R_HPOL             (1 << 27)
 48 #define LDMT1R_DWPOL            (1 << 26)
 49 #define LDMT1R_DIPOL            (1 << 25)
 50 #define LDMT1R_DAPOL            (1 << 24)
 51 #define LDMT1R_HSCNT            (1 << 17)
 52 #define LDMT1R_DWCNT            (1 << 16)
 53 #define LDMT1R_IFM              (1 << 12)
 54 #define LDMT1R_MIFTYP_RGB8      (0x0 << 0)
 55 #define LDMT1R_MIFTYP_RGB9      (0x4 << 0)
 56 #define LDMT1R_MIFTYP_RGB12A    (0x5 << 0)
 57 #define LDMT1R_MIFTYP_RGB12B    (0x6 << 0)
 58 #define LDMT1R_MIFTYP_RGB16     (0x7 << 0)
 59 #define LDMT1R_MIFTYP_RGB18     (0xa << 0)
 60 #define LDMT1R_MIFTYP_RGB24     (0xb << 0)
 61 #define LDMT1R_MIFTYP_YCBCR     (0xf << 0)
 62 #define LDMT1R_MIFTYP_SYS8A     (0x0 << 0)
 63 #define LDMT1R_MIFTYP_SYS8B     (0x1 << 0)
 64 #define LDMT1R_MIFTYP_SYS8C     (0x2 << 0)
 65 #define LDMT1R_MIFTYP_SYS8D     (0x3 << 0)
 66 #define LDMT1R_MIFTYP_SYS9      (0x4 << 0)
 67 #define LDMT1R_MIFTYP_SYS12     (0x5 << 0)
 68 #define LDMT1R_MIFTYP_SYS16A    (0x7 << 0)
 69 #define LDMT1R_MIFTYP_SYS16B    (0x8 << 0)
 70 #define LDMT1R_MIFTYP_SYS16C    (0x9 << 0)
 71 #define LDMT1R_MIFTYP_SYS18     (0xa << 0)
 72 #define LDMT1R_MIFTYP_SYS24     (0xb << 0)
 73 #define LDMT1R_MIFTYP_MASK      (0xf << 0)
 74 
 75 #define LDDFR_CF1               (1 << 18)
 76 #define LDDFR_CF0               (1 << 17)
 77 #define LDDFR_CC                (1 << 16)
 78 #define LDDFR_YF_420            (0 << 8)
 79 #define LDDFR_YF_422            (1 << 8)
 80 #define LDDFR_YF_444            (2 << 8)
 81 #define LDDFR_YF_MASK           (3 << 8)
 82 #define LDDFR_PKF_ARGB32        (0x00 << 0)
 83 #define LDDFR_PKF_RGB16         (0x03 << 0)
 84 #define LDDFR_PKF_RGB24         (0x0b << 0)
 85 #define LDDFR_PKF_MASK          (0x1f << 0)
 86 
 87 #define LDSM1R_OS               (1 << 0)
 88 
 89 #define LDSM2R_OSTRG            (1 << 0)
 90 
 91 #define LDPMR_LPS               (3 << 0)
 92 
 93 #define _LDDWD0R                0x800
 94 #define LDDWDxR_WDACT           (1 << 28)
 95 #define LDDWDxR_RSW             (1 << 24)
 96 #define _LDDRDR                 0x840
 97 #define LDDRDR_RSR              (1 << 24)
 98 #define LDDRDR_DRD_MASK         (0x3ffff << 0)
 99 #define _LDDWAR                 0x900
100 #define LDDWAR_WA               (1 << 0)
101 #define _LDDRAR                 0x904
102 #define LDDRAR_RA               (1 << 0)
103 
104 enum {
105         RGB8    = LDMT1R_MIFTYP_RGB8,   /* 24bpp, 8:8:8 */
106         RGB9    = LDMT1R_MIFTYP_RGB9,   /* 18bpp, 9:9 */
107         RGB12A  = LDMT1R_MIFTYP_RGB12A, /* 24bpp, 12:12 */
108         RGB12B  = LDMT1R_MIFTYP_RGB12B, /* 12bpp */
109         RGB16   = LDMT1R_MIFTYP_RGB16,  /* 16bpp */
110         RGB18   = LDMT1R_MIFTYP_RGB18,  /* 18bpp */
111         RGB24   = LDMT1R_MIFTYP_RGB24,  /* 24bpp */
112         YUV422  = LDMT1R_MIFTYP_YCBCR,  /* 16bpp */
113         SYS8A   = LDMT1R_IFM | LDMT1R_MIFTYP_SYS8A,     /* 24bpp, 8:8:8 */
114         SYS8B   = LDMT1R_IFM | LDMT1R_MIFTYP_SYS8B,     /* 18bpp, 8:8:2 */
115         SYS8C   = LDMT1R_IFM | LDMT1R_MIFTYP_SYS8C,     /* 18bpp, 2:8:8 */
116         SYS8D   = LDMT1R_IFM | LDMT1R_MIFTYP_SYS8D,     /* 16bpp, 8:8 */
117         SYS9    = LDMT1R_IFM | LDMT1R_MIFTYP_SYS9,      /* 18bpp, 9:9 */
118         SYS12   = LDMT1R_IFM | LDMT1R_MIFTYP_SYS12,     /* 24bpp, 12:12 */
119         SYS16A  = LDMT1R_IFM | LDMT1R_MIFTYP_SYS16A,    /* 16bpp */
120         SYS16B  = LDMT1R_IFM | LDMT1R_MIFTYP_SYS16B,    /* 18bpp, 16:2 */
121         SYS16C  = LDMT1R_IFM | LDMT1R_MIFTYP_SYS16C,    /* 18bpp, 2:16 */
122         SYS18   = LDMT1R_IFM | LDMT1R_MIFTYP_SYS18,     /* 18bpp */
123         SYS24   = LDMT1R_IFM | LDMT1R_MIFTYP_SYS24,     /* 24bpp */
124 };
125 
126 enum { LCDC_CHAN_DISABLED = 0,
127        LCDC_CHAN_MAINLCD,
128        LCDC_CHAN_SUBLCD };
129 
130 enum { LCDC_CLK_BUS, LCDC_CLK_PERIPHERAL, LCDC_CLK_EXTERNAL };
131 
132 #define LCDC_FLAGS_DWPOL (1 << 0) /* Rising edge dot clock data latch */
133 #define LCDC_FLAGS_DIPOL (1 << 1) /* Active low display enable polarity */
134 #define LCDC_FLAGS_DAPOL (1 << 2) /* Active low display data polarity */
135 #define LCDC_FLAGS_HSCNT (1 << 3) /* Disable HSYNC during VBLANK */
136 #define LCDC_FLAGS_DWCNT (1 << 4) /* Disable dotclock during blanking */
137 
138 struct sh_mobile_lcdc_sys_bus_cfg {
139         unsigned long ldmt2r;
140         unsigned long ldmt3r;
141         unsigned long deferred_io_msec;
142 };
143 
144 struct sh_mobile_lcdc_sys_bus_ops {
145         void (*write_index)(void *handle, unsigned long data);
146         void (*write_data)(void *handle, unsigned long data);
147         unsigned long (*read_data)(void *handle);
148 };
149 
150 struct sh_mobile_lcdc_panel_cfg {
151         unsigned long width;            /* Panel width in mm */
152         unsigned long height;           /* Panel height in mm */
153         int (*setup_sys)(void *sys_ops_handle,
154                          struct sh_mobile_lcdc_sys_bus_ops *sys_ops);
155         void (*start_transfer)(void *sys_ops_handle,
156                                struct sh_mobile_lcdc_sys_bus_ops *sys_ops);
157         void (*display_on)(void);
158         void (*display_off)(void);
159 };
160 
161 /* backlight info */
162 struct sh_mobile_lcdc_bl_info {
163         const char *name;
164         int max_brightness;
165         int (*set_brightness)(int brightness);
166 };
167 
168 struct sh_mobile_lcdc_overlay_cfg {
169         int fourcc;
170         unsigned int max_xres;
171         unsigned int max_yres;
172 };
173 
174 struct sh_mobile_lcdc_chan_cfg {
175         int chan;
176         int fourcc;
177         int colorspace;
178         int interface_type; /* selects RGBn or SYSn I/F, see above */
179         int clock_divider;
180         unsigned long flags; /* LCDC_FLAGS_... */
181         const struct fb_videomode *lcd_modes;
182         int num_modes;
183         struct sh_mobile_lcdc_panel_cfg panel_cfg;
184         struct sh_mobile_lcdc_bl_info bl_info;
185         struct sh_mobile_lcdc_sys_bus_cfg sys_bus_cfg; /* only for SYSn I/F */
186 
187         struct platform_device *tx_dev; /* HDMI/DSI transmitter device */
188 };
189 
190 struct sh_mobile_lcdc_info {
191         int clock_source;
192         struct sh_mobile_lcdc_chan_cfg ch[2];
193         struct sh_mobile_lcdc_overlay_cfg overlays[4];
194 };
195 
196 #endif /* __ASM_SH_MOBILE_LCDC_H__ */
197 

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