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TOMOYO Linux Cross Reference
Linux/include/xen/interface/xen.h

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  1 /******************************************************************************
  2  * xen.h
  3  *
  4  * Guest OS interface to Xen.
  5  *
  6  * Permission is hereby granted, free of charge, to any person obtaining a copy
  7  * of this software and associated documentation files (the "Software"), to
  8  * deal in the Software without restriction, including without limitation the
  9  * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
 10  * sell copies of the Software, and to permit persons to whom the Software is
 11  * furnished to do so, subject to the following conditions:
 12  *
 13  * The above copyright notice and this permission notice shall be included in
 14  * all copies or substantial portions of the Software.
 15  *
 16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 19  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 22  * DEALINGS IN THE SOFTWARE.
 23  *
 24  * Copyright (c) 2004, K A Fraser
 25  */
 26 
 27 #ifndef __XEN_PUBLIC_XEN_H__
 28 #define __XEN_PUBLIC_XEN_H__
 29 
 30 #include <asm/xen/interface.h>
 31 
 32 /*
 33  * XEN "SYSTEM CALLS" (a.k.a. HYPERCALLS).
 34  */
 35 
 36 /*
 37  * x86_32: EAX = vector; EBX, ECX, EDX, ESI, EDI = args 1, 2, 3, 4, 5.
 38  *         EAX = return value
 39  *         (argument registers may be clobbered on return)
 40  * x86_64: RAX = vector; RDI, RSI, RDX, R10, R8, R9 = args 1, 2, 3, 4, 5, 6.
 41  *         RAX = return value
 42  *         (argument registers not clobbered on return; RCX, R11 are)
 43  */
 44 #define __HYPERVISOR_set_trap_table        0
 45 #define __HYPERVISOR_mmu_update            1
 46 #define __HYPERVISOR_set_gdt               2
 47 #define __HYPERVISOR_stack_switch          3
 48 #define __HYPERVISOR_set_callbacks         4
 49 #define __HYPERVISOR_fpu_taskswitch        5
 50 #define __HYPERVISOR_sched_op_compat       6
 51 #define __HYPERVISOR_platform_op           7
 52 #define __HYPERVISOR_set_debugreg          8
 53 #define __HYPERVISOR_get_debugreg          9
 54 #define __HYPERVISOR_update_descriptor    10
 55 #define __HYPERVISOR_memory_op            12
 56 #define __HYPERVISOR_multicall            13
 57 #define __HYPERVISOR_update_va_mapping    14
 58 #define __HYPERVISOR_set_timer_op         15
 59 #define __HYPERVISOR_event_channel_op_compat 16
 60 #define __HYPERVISOR_xen_version          17
 61 #define __HYPERVISOR_console_io           18
 62 #define __HYPERVISOR_physdev_op_compat    19
 63 #define __HYPERVISOR_grant_table_op       20
 64 #define __HYPERVISOR_vm_assist            21
 65 #define __HYPERVISOR_update_va_mapping_otherdomain 22
 66 #define __HYPERVISOR_iret                 23 /* x86 only */
 67 #define __HYPERVISOR_vcpu_op              24
 68 #define __HYPERVISOR_set_segment_base     25 /* x86/64 only */
 69 #define __HYPERVISOR_mmuext_op            26
 70 #define __HYPERVISOR_xsm_op               27
 71 #define __HYPERVISOR_nmi_op               28
 72 #define __HYPERVISOR_sched_op             29
 73 #define __HYPERVISOR_callback_op          30
 74 #define __HYPERVISOR_xenoprof_op          31
 75 #define __HYPERVISOR_event_channel_op     32
 76 #define __HYPERVISOR_physdev_op           33
 77 #define __HYPERVISOR_hvm_op               34
 78 #define __HYPERVISOR_sysctl               35
 79 #define __HYPERVISOR_domctl               36
 80 #define __HYPERVISOR_kexec_op             37
 81 #define __HYPERVISOR_tmem_op              38
 82 #define __HYPERVISOR_xc_reserved_op       39 /* reserved for XenClient */
 83 #define __HYPERVISOR_xenpmu_op            40
 84 #define __HYPERVISOR_dm_op                41
 85 
 86 /* Architecture-specific hypercall definitions. */
 87 #define __HYPERVISOR_arch_0               48
 88 #define __HYPERVISOR_arch_1               49
 89 #define __HYPERVISOR_arch_2               50
 90 #define __HYPERVISOR_arch_3               51
 91 #define __HYPERVISOR_arch_4               52
 92 #define __HYPERVISOR_arch_5               53
 93 #define __HYPERVISOR_arch_6               54
 94 #define __HYPERVISOR_arch_7               55
 95 
 96 /*
 97  * VIRTUAL INTERRUPTS
 98  *
 99  * Virtual interrupts that a guest OS may receive from Xen.
100  * In the side comments, 'V.' denotes a per-VCPU VIRQ while 'G.' denotes a
101  * global VIRQ. The former can be bound once per VCPU and cannot be re-bound.
102  * The latter can be allocated only once per guest: they must initially be
103  * allocated to VCPU0 but can subsequently be re-bound.
104  */
105 #define VIRQ_TIMER      0  /* V. Timebase update, and/or requested timeout.  */
106 #define VIRQ_DEBUG      1  /* V. Request guest to dump debug info.           */
107 #define VIRQ_CONSOLE    2  /* G. (DOM0) Bytes received on emergency console. */
108 #define VIRQ_DOM_EXC    3  /* G. (DOM0) Exceptional event for some domain.   */
109 #define VIRQ_TBUF       4  /* G. (DOM0) Trace buffer has records available.  */
110 #define VIRQ_DEBUGGER   6  /* G. (DOM0) A domain has paused for debugging.   */
111 #define VIRQ_XENOPROF   7  /* V. XenOprofile interrupt: new sample available */
112 #define VIRQ_CON_RING   8  /* G. (DOM0) Bytes received on console            */
113 #define VIRQ_PCPU_STATE 9  /* G. (DOM0) PCPU state changed                   */
114 #define VIRQ_MEM_EVENT  10 /* G. (DOM0) A memory event has occured           */
115 #define VIRQ_XC_RESERVED 11 /* G. Reserved for XenClient                     */
116 #define VIRQ_ENOMEM     12 /* G. (DOM0) Low on heap memory       */
117 #define VIRQ_XENPMU     13  /* PMC interrupt                                 */
118 
119 /* Architecture-specific VIRQ definitions. */
120 #define VIRQ_ARCH_0    16
121 #define VIRQ_ARCH_1    17
122 #define VIRQ_ARCH_2    18
123 #define VIRQ_ARCH_3    19
124 #define VIRQ_ARCH_4    20
125 #define VIRQ_ARCH_5    21
126 #define VIRQ_ARCH_6    22
127 #define VIRQ_ARCH_7    23
128 
129 #define NR_VIRQS       24
130 
131 /*
132  * enum neg_errnoval HYPERVISOR_mmu_update(const struct mmu_update reqs[],
133  *                                         unsigned count, unsigned *done_out,
134  *                                         unsigned foreigndom)
135  * @reqs is an array of mmu_update_t structures ((ptr, val) pairs).
136  * @count is the length of the above array.
137  * @pdone is an output parameter indicating number of completed operations
138  * @foreigndom[15:0]: FD, the expected owner of data pages referenced in this
139  *                    hypercall invocation. Can be DOMID_SELF.
140  * @foreigndom[31:16]: PFD, the expected owner of pagetable pages referenced
141  *                     in this hypercall invocation. The value of this field
142  *                     (x) encodes the PFD as follows:
143  *                     x == 0 => PFD == DOMID_SELF
144  *                     x != 0 => PFD == x - 1
145  *
146  * Sub-commands: ptr[1:0] specifies the appropriate MMU_* command.
147  * -------------
148  * ptr[1:0] == MMU_NORMAL_PT_UPDATE:
149  * Updates an entry in a page table belonging to PFD. If updating an L1 table,
150  * and the new table entry is valid/present, the mapped frame must belong to
151  * FD. If attempting to map an I/O page then the caller assumes the privilege
152  * of the FD.
153  * FD == DOMID_IO: Permit /only/ I/O mappings, at the priv level of the caller.
154  * FD == DOMID_XEN: Map restricted areas of Xen's heap space.
155  * ptr[:2]  -- Machine address of the page-table entry to modify.
156  * val      -- Value to write.
157  *
158  * There also certain implicit requirements when using this hypercall. The
159  * pages that make up a pagetable must be mapped read-only in the guest.
160  * This prevents uncontrolled guest updates to the pagetable. Xen strictly
161  * enforces this, and will disallow any pagetable update which will end up
162  * mapping pagetable page RW, and will disallow using any writable page as a
163  * pagetable. In practice it means that when constructing a page table for a
164  * process, thread, etc, we MUST be very dilligient in following these rules:
165  *  1). Start with top-level page (PGD or in Xen language: L4). Fill out
166  *      the entries.
167  *  2). Keep on going, filling out the upper (PUD or L3), and middle (PMD
168  *      or L2).
169  *  3). Start filling out the PTE table (L1) with the PTE entries. Once
170  *      done, make sure to set each of those entries to RO (so writeable bit
171  *      is unset). Once that has been completed, set the PMD (L2) for this
172  *      PTE table as RO.
173  *  4). When completed with all of the PMD (L2) entries, and all of them have
174  *      been set to RO, make sure to set RO the PUD (L3). Do the same
175  *      operation on PGD (L4) pagetable entries that have a PUD (L3) entry.
176  *  5). Now before you can use those pages (so setting the cr3), you MUST also
177  *      pin them so that the hypervisor can verify the entries. This is done
178  *      via the HYPERVISOR_mmuext_op(MMUEXT_PIN_L4_TABLE, guest physical frame
179  *      number of the PGD (L4)). And this point the HYPERVISOR_mmuext_op(
180  *      MMUEXT_NEW_BASEPTR, guest physical frame number of the PGD (L4)) can be
181  *      issued.
182  * For 32-bit guests, the L4 is not used (as there is less pagetables), so
183  * instead use L3.
184  * At this point the pagetables can be modified using the MMU_NORMAL_PT_UPDATE
185  * hypercall. Also if so desired the OS can also try to write to the PTE
186  * and be trapped by the hypervisor (as the PTE entry is RO).
187  *
188  * To deallocate the pages, the operations are the reverse of the steps
189  * mentioned above. The argument is MMUEXT_UNPIN_TABLE for all levels and the
190  * pagetable MUST not be in use (meaning that the cr3 is not set to it).
191  *
192  * ptr[1:0] == MMU_MACHPHYS_UPDATE:
193  * Updates an entry in the machine->pseudo-physical mapping table.
194  * ptr[:2]  -- Machine address within the frame whose mapping to modify.
195  *             The frame must belong to the FD, if one is specified.
196  * val      -- Value to write into the mapping entry.
197  *
198  * ptr[1:0] == MMU_PT_UPDATE_PRESERVE_AD:
199  * As MMU_NORMAL_PT_UPDATE above, but A/D bits currently in the PTE are ORed
200  * with those in @val.
201  *
202  * @val is usually the machine frame number along with some attributes.
203  * The attributes by default follow the architecture defined bits. Meaning that
204  * if this is a X86_64 machine and four page table layout is used, the layout
205  * of val is:
206  *  - 63 if set means No execute (NX)
207  *  - 46-13 the machine frame number
208  *  - 12 available for guest
209  *  - 11 available for guest
210  *  - 10 available for guest
211  *  - 9 available for guest
212  *  - 8 global
213  *  - 7 PAT (PSE is disabled, must use hypercall to make 4MB or 2MB pages)
214  *  - 6 dirty
215  *  - 5 accessed
216  *  - 4 page cached disabled
217  *  - 3 page write through
218  *  - 2 userspace accessible
219  *  - 1 writeable
220  *  - 0 present
221  *
222  *  The one bits that does not fit with the default layout is the PAGE_PSE
223  *  also called PAGE_PAT). The MMUEXT_[UN]MARK_SUPER arguments to the
224  *  HYPERVISOR_mmuext_op serve as mechanism to set a pagetable to be 4MB
225  *  (or 2MB) instead of using the PAGE_PSE bit.
226  *
227  *  The reason that the PAGE_PSE (bit 7) is not being utilized is due to Xen
228  *  using it as the Page Attribute Table (PAT) bit - for details on it please
229  *  refer to Intel SDM 10.12. The PAT allows to set the caching attributes of
230  *  pages instead of using MTRRs.
231  *
232  *  The PAT MSR is as follows (it is a 64-bit value, each entry is 8 bits):
233  *                    PAT4                 PAT0
234  *  +-----+-----+----+----+----+-----+----+----+
235  *  | UC  | UC- | WC | WB | UC | UC- | WC | WB |  <= Linux
236  *  +-----+-----+----+----+----+-----+----+----+
237  *  | UC  | UC- | WT | WB | UC | UC- | WT | WB |  <= BIOS (default when machine boots)
238  *  +-----+-----+----+----+----+-----+----+----+
239  *  | rsv | rsv | WP | WC | UC | UC- | WT | WB |  <= Xen
240  *  +-----+-----+----+----+----+-----+----+----+
241  *
242  *  The lookup of this index table translates to looking up
243  *  Bit 7, Bit 4, and Bit 3 of val entry:
244  *
245  *  PAT/PSE (bit 7) ... PCD (bit 4) .. PWT (bit 3).
246  *
247  *  If all bits are off, then we are using PAT0. If bit 3 turned on,
248  *  then we are using PAT1, if bit 3 and bit 4, then PAT2..
249  *
250  *  As you can see, the Linux PAT1 translates to PAT4 under Xen. Which means
251  *  that if a guest that follows Linux's PAT setup and would like to set Write
252  *  Combined on pages it MUST use PAT4 entry. Meaning that Bit 7 (PAGE_PAT) is
253  *  set. For example, under Linux it only uses PAT0, PAT1, and PAT2 for the
254  *  caching as:
255  *
256  *   WB = none (so PAT0)
257  *   WC = PWT (bit 3 on)
258  *   UC = PWT | PCD (bit 3 and 4 are on).
259  *
260  * To make it work with Xen, it needs to translate the WC bit as so:
261  *
262  *  PWT (so bit 3 on) --> PAT (so bit 7 is on) and clear bit 3
263  *
264  * And to translate back it would:
265  *
266  * PAT (bit 7 on) --> PWT (bit 3 on) and clear bit 7.
267  */
268 #define MMU_NORMAL_PT_UPDATE       0 /* checked '*ptr = val'. ptr is MA.      */
269 #define MMU_MACHPHYS_UPDATE        1 /* ptr = MA of frame to modify entry for */
270 #define MMU_PT_UPDATE_PRESERVE_AD  2 /* atomically: *ptr = val | (*ptr&(A|D)) */
271 #define MMU_PT_UPDATE_NO_TRANSLATE 3 /* checked '*ptr = val'. ptr is MA.      */
272 
273 /*
274  * MMU EXTENDED OPERATIONS
275  *
276  * enum neg_errnoval HYPERVISOR_mmuext_op(mmuext_op_t uops[],
277  *                                        unsigned int count,
278  *                                        unsigned int *pdone,
279  *                                        unsigned int foreigndom)
280  */
281 /* HYPERVISOR_mmuext_op() accepts a list of mmuext_op structures.
282  * A foreigndom (FD) can be specified (or DOMID_SELF for none).
283  * Where the FD has some effect, it is described below.
284  *
285  * cmd: MMUEXT_(UN)PIN_*_TABLE
286  * mfn: Machine frame number to be (un)pinned as a p.t. page.
287  *      The frame must belong to the FD, if one is specified.
288  *
289  * cmd: MMUEXT_NEW_BASEPTR
290  * mfn: Machine frame number of new page-table base to install in MMU.
291  *
292  * cmd: MMUEXT_NEW_USER_BASEPTR [x86/64 only]
293  * mfn: Machine frame number of new page-table base to install in MMU
294  *      when in user space.
295  *
296  * cmd: MMUEXT_TLB_FLUSH_LOCAL
297  * No additional arguments. Flushes local TLB.
298  *
299  * cmd: MMUEXT_INVLPG_LOCAL
300  * linear_addr: Linear address to be flushed from the local TLB.
301  *
302  * cmd: MMUEXT_TLB_FLUSH_MULTI
303  * vcpumask: Pointer to bitmap of VCPUs to be flushed.
304  *
305  * cmd: MMUEXT_INVLPG_MULTI
306  * linear_addr: Linear address to be flushed.
307  * vcpumask: Pointer to bitmap of VCPUs to be flushed.
308  *
309  * cmd: MMUEXT_TLB_FLUSH_ALL
310  * No additional arguments. Flushes all VCPUs' TLBs.
311  *
312  * cmd: MMUEXT_INVLPG_ALL
313  * linear_addr: Linear address to be flushed from all VCPUs' TLBs.
314  *
315  * cmd: MMUEXT_FLUSH_CACHE
316  * No additional arguments. Writes back and flushes cache contents.
317  *
318  * cmd: MMUEXT_FLUSH_CACHE_GLOBAL
319  * No additional arguments. Writes back and flushes cache contents
320  * on all CPUs in the system.
321  *
322  * cmd: MMUEXT_SET_LDT
323  * linear_addr: Linear address of LDT base (NB. must be page-aligned).
324  * nr_ents: Number of entries in LDT.
325  *
326  * cmd: MMUEXT_CLEAR_PAGE
327  * mfn: Machine frame number to be cleared.
328  *
329  * cmd: MMUEXT_COPY_PAGE
330  * mfn: Machine frame number of the destination page.
331  * src_mfn: Machine frame number of the source page.
332  *
333  * cmd: MMUEXT_[UN]MARK_SUPER
334  * mfn: Machine frame number of head of superpage to be [un]marked.
335  */
336 #define MMUEXT_PIN_L1_TABLE      0
337 #define MMUEXT_PIN_L2_TABLE      1
338 #define MMUEXT_PIN_L3_TABLE      2
339 #define MMUEXT_PIN_L4_TABLE      3
340 #define MMUEXT_UNPIN_TABLE       4
341 #define MMUEXT_NEW_BASEPTR       5
342 #define MMUEXT_TLB_FLUSH_LOCAL   6
343 #define MMUEXT_INVLPG_LOCAL      7
344 #define MMUEXT_TLB_FLUSH_MULTI   8
345 #define MMUEXT_INVLPG_MULTI      9
346 #define MMUEXT_TLB_FLUSH_ALL    10
347 #define MMUEXT_INVLPG_ALL       11
348 #define MMUEXT_FLUSH_CACHE      12
349 #define MMUEXT_SET_LDT          13
350 #define MMUEXT_NEW_USER_BASEPTR 15
351 #define MMUEXT_CLEAR_PAGE       16
352 #define MMUEXT_COPY_PAGE        17
353 #define MMUEXT_FLUSH_CACHE_GLOBAL 18
354 #define MMUEXT_MARK_SUPER       19
355 #define MMUEXT_UNMARK_SUPER     20
356 
357 #ifndef __ASSEMBLY__
358 struct mmuext_op {
359         unsigned int cmd;
360         union {
361                 /* [UN]PIN_TABLE, NEW_BASEPTR, NEW_USER_BASEPTR
362                  * CLEAR_PAGE, COPY_PAGE, [UN]MARK_SUPER */
363                 xen_pfn_t mfn;
364                 /* INVLPG_LOCAL, INVLPG_ALL, SET_LDT */
365                 unsigned long linear_addr;
366         } arg1;
367         union {
368                 /* SET_LDT */
369                 unsigned int nr_ents;
370                 /* TLB_FLUSH_MULTI, INVLPG_MULTI */
371                 void *vcpumask;
372                 /* COPY_PAGE */
373                 xen_pfn_t src_mfn;
374         } arg2;
375 };
376 DEFINE_GUEST_HANDLE_STRUCT(mmuext_op);
377 #endif
378 
379 /* These are passed as 'flags' to update_va_mapping. They can be ORed. */
380 /* When specifying UVMF_MULTI, also OR in a pointer to a CPU bitmap.   */
381 /* UVMF_LOCAL is merely UVMF_MULTI with a NULL bitmap pointer.         */
382 #define UVMF_NONE               (0UL<<0) /* No flushing at all.   */
383 #define UVMF_TLB_FLUSH          (1UL<<0) /* Flush entire TLB(s).  */
384 #define UVMF_INVLPG             (2UL<<0) /* Flush only one entry. */
385 #define UVMF_FLUSHTYPE_MASK     (3UL<<0)
386 #define UVMF_MULTI              (0UL<<2) /* Flush subset of TLBs. */
387 #define UVMF_LOCAL              (0UL<<2) /* Flush local TLB.      */
388 #define UVMF_ALL                (1UL<<2) /* Flush all TLBs.       */
389 
390 /*
391  * Commands to HYPERVISOR_console_io().
392  */
393 #define CONSOLEIO_write         0
394 #define CONSOLEIO_read          1
395 
396 /*
397  * Commands to HYPERVISOR_vm_assist().
398  */
399 #define VMASST_CMD_enable                0
400 #define VMASST_CMD_disable               1
401 
402 /* x86/32 guests: simulate full 4GB segment limits. */
403 #define VMASST_TYPE_4gb_segments         0
404 
405 /* x86/32 guests: trap (vector 15) whenever above vmassist is used. */
406 #define VMASST_TYPE_4gb_segments_notify  1
407 
408 /*
409  * x86 guests: support writes to bottom-level PTEs.
410  * NB1. Page-directory entries cannot be written.
411  * NB2. Guest must continue to remove all writable mappings of PTEs.
412  */
413 #define VMASST_TYPE_writable_pagetables  2
414 
415 /* x86/PAE guests: support PDPTs above 4GB. */
416 #define VMASST_TYPE_pae_extended_cr3     3
417 
418 /*
419  * x86 guests: Sane behaviour for virtual iopl
420  *  - virtual iopl updated from do_iret() hypercalls.
421  *  - virtual iopl reported in bounce frames.
422  *  - guest kernels assumed to be level 0 for the purpose of iopl checks.
423  */
424 #define VMASST_TYPE_architectural_iopl   4
425 
426 /*
427  * All guests: activate update indicator in vcpu_runstate_info
428  * Enable setting the XEN_RUNSTATE_UPDATE flag in guest memory mapped
429  * vcpu_runstate_info during updates of the runstate information.
430  */
431 #define VMASST_TYPE_runstate_update_flag 5
432 
433 #define MAX_VMASST_TYPE 5
434 
435 #ifndef __ASSEMBLY__
436 
437 typedef uint16_t domid_t;
438 
439 /* Domain ids >= DOMID_FIRST_RESERVED cannot be used for ordinary domains. */
440 #define DOMID_FIRST_RESERVED (0x7FF0U)
441 
442 /* DOMID_SELF is used in certain contexts to refer to oneself. */
443 #define DOMID_SELF (0x7FF0U)
444 
445 /*
446  * DOMID_IO is used to restrict page-table updates to mapping I/O memory.
447  * Although no Foreign Domain need be specified to map I/O pages, DOMID_IO
448  * is useful to ensure that no mappings to the OS's own heap are accidentally
449  * installed. (e.g., in Linux this could cause havoc as reference counts
450  * aren't adjusted on the I/O-mapping code path).
451  * This only makes sense in MMUEXT_SET_FOREIGNDOM, but in that context can
452  * be specified by any calling domain.
453  */
454 #define DOMID_IO   (0x7FF1U)
455 
456 /*
457  * DOMID_XEN is used to allow privileged domains to map restricted parts of
458  * Xen's heap space (e.g., the machine_to_phys table).
459  * This only makes sense in MMUEXT_SET_FOREIGNDOM, and is only permitted if
460  * the caller is privileged.
461  */
462 #define DOMID_XEN  (0x7FF2U)
463 
464 /* DOMID_COW is used as the owner of sharable pages */
465 #define DOMID_COW  (0x7FF3U)
466 
467 /* DOMID_INVALID is used to identify pages with unknown owner. */
468 #define DOMID_INVALID (0x7FF4U)
469 
470 /* Idle domain. */
471 #define DOMID_IDLE (0x7FFFU)
472 
473 /*
474  * Send an array of these to HYPERVISOR_mmu_update().
475  * NB. The fields are natural pointer/address size for this architecture.
476  */
477 struct mmu_update {
478     uint64_t ptr;       /* Machine address of PTE. */
479     uint64_t val;       /* New contents of PTE.    */
480 };
481 DEFINE_GUEST_HANDLE_STRUCT(mmu_update);
482 
483 /*
484  * Send an array of these to HYPERVISOR_multicall().
485  * NB. The fields are logically the natural register size for this
486  * architecture. In cases where xen_ulong_t is larger than this then
487  * any unused bits in the upper portion must be zero.
488  */
489 struct multicall_entry {
490     xen_ulong_t op;
491     xen_long_t result;
492     xen_ulong_t args[6];
493 };
494 DEFINE_GUEST_HANDLE_STRUCT(multicall_entry);
495 
496 struct vcpu_time_info {
497         /*
498          * Updates to the following values are preceded and followed
499          * by an increment of 'version'. The guest can therefore
500          * detect updates by looking for changes to 'version'. If the
501          * least-significant bit of the version number is set then an
502          * update is in progress and the guest must wait to read a
503          * consistent set of values.  The correct way to interact with
504          * the version number is similar to Linux's seqlock: see the
505          * implementations of read_seqbegin/read_seqretry.
506          */
507         uint32_t version;
508         uint32_t pad0;
509         uint64_t tsc_timestamp;   /* TSC at last update of time vals.  */
510         uint64_t system_time;     /* Time, in nanosecs, since boot.    */
511         /*
512          * Current system time:
513          *   system_time + ((tsc - tsc_timestamp) << tsc_shift) * tsc_to_system_mul
514          * CPU frequency (Hz):
515          *   ((10^9 << 32) / tsc_to_system_mul) >> tsc_shift
516          */
517         uint32_t tsc_to_system_mul;
518         int8_t   tsc_shift;
519         int8_t   pad1[3];
520 }; /* 32 bytes */
521 
522 struct vcpu_info {
523         /*
524          * 'evtchn_upcall_pending' is written non-zero by Xen to indicate
525          * a pending notification for a particular VCPU. It is then cleared
526          * by the guest OS /before/ checking for pending work, thus avoiding
527          * a set-and-check race. Note that the mask is only accessed by Xen
528          * on the CPU that is currently hosting the VCPU. This means that the
529          * pending and mask flags can be updated by the guest without special
530          * synchronisation (i.e., no need for the x86 LOCK prefix).
531          * This may seem suboptimal because if the pending flag is set by
532          * a different CPU then an IPI may be scheduled even when the mask
533          * is set. However, note:
534          *  1. The task of 'interrupt holdoff' is covered by the per-event-
535          *     channel mask bits. A 'noisy' event that is continually being
536          *     triggered can be masked at source at this very precise
537          *     granularity.
538          *  2. The main purpose of the per-VCPU mask is therefore to restrict
539          *     reentrant execution: whether for concurrency control, or to
540          *     prevent unbounded stack usage. Whatever the purpose, we expect
541          *     that the mask will be asserted only for short periods at a time,
542          *     and so the likelihood of a 'spurious' IPI is suitably small.
543          * The mask is read before making an event upcall to the guest: a
544          * non-zero mask therefore guarantees that the VCPU will not receive
545          * an upcall activation. The mask is cleared when the VCPU requests
546          * to block: this avoids wakeup-waiting races.
547          */
548         uint8_t evtchn_upcall_pending;
549         uint8_t evtchn_upcall_mask;
550         xen_ulong_t evtchn_pending_sel;
551         struct arch_vcpu_info arch;
552         struct pvclock_vcpu_time_info time;
553 }; /* 64 bytes (x86) */
554 
555 /*
556  * Xen/kernel shared data -- pointer provided in start_info.
557  * NB. We expect that this struct is smaller than a page.
558  */
559 struct shared_info {
560         struct vcpu_info vcpu_info[MAX_VIRT_CPUS];
561 
562         /*
563          * A domain can create "event channels" on which it can send and receive
564          * asynchronous event notifications. There are three classes of event that
565          * are delivered by this mechanism:
566          *  1. Bi-directional inter- and intra-domain connections. Domains must
567          *     arrange out-of-band to set up a connection (usually by allocating
568          *     an unbound 'listener' port and avertising that via a storage service
569          *     such as xenstore).
570          *  2. Physical interrupts. A domain with suitable hardware-access
571          *     privileges can bind an event-channel port to a physical interrupt
572          *     source.
573          *  3. Virtual interrupts ('events'). A domain can bind an event-channel
574          *     port to a virtual interrupt source, such as the virtual-timer
575          *     device or the emergency console.
576          *
577          * Event channels are addressed by a "port index". Each channel is
578          * associated with two bits of information:
579          *  1. PENDING -- notifies the domain that there is a pending notification
580          *     to be processed. This bit is cleared by the guest.
581          *  2. MASK -- if this bit is clear then a 0->1 transition of PENDING
582          *     will cause an asynchronous upcall to be scheduled. This bit is only
583          *     updated by the guest. It is read-only within Xen. If a channel
584          *     becomes pending while the channel is masked then the 'edge' is lost
585          *     (i.e., when the channel is unmasked, the guest must manually handle
586          *     pending notifications as no upcall will be scheduled by Xen).
587          *
588          * To expedite scanning of pending notifications, any 0->1 pending
589          * transition on an unmasked channel causes a corresponding bit in a
590          * per-vcpu selector word to be set. Each bit in the selector covers a
591          * 'C long' in the PENDING bitfield array.
592          */
593         xen_ulong_t evtchn_pending[sizeof(xen_ulong_t) * 8];
594         xen_ulong_t evtchn_mask[sizeof(xen_ulong_t) * 8];
595 
596         /*
597          * Wallclock time: updated only by control software. Guests should base
598          * their gettimeofday() syscall on this wallclock-base value.
599          */
600         struct pvclock_wall_clock wc;
601 
602         struct arch_shared_info arch;
603 
604 };
605 
606 /*
607  * Start-of-day memory layout
608  *
609  *  1. The domain is started within contiguous virtual-memory region.
610  *  2. The contiguous region begins and ends on an aligned 4MB boundary.
611  *  3. This the order of bootstrap elements in the initial virtual region:
612  *      a. relocated kernel image
613  *      b. initial ram disk              [mod_start, mod_len]
614  *         (may be omitted)
615  *      c. list of allocated page frames [mfn_list, nr_pages]
616  *         (unless relocated due to XEN_ELFNOTE_INIT_P2M)
617  *      d. start_info_t structure        [register ESI (x86)]
618  *         in case of dom0 this page contains the console info, too
619  *      e. unless dom0: xenstore ring page
620  *      f. unless dom0: console ring page
621  *      g. bootstrap page tables         [pt_base, CR3 (x86)]
622  *      h. bootstrap stack               [register ESP (x86)]
623  *  4. Bootstrap elements are packed together, but each is 4kB-aligned.
624  *  5. The list of page frames forms a contiguous 'pseudo-physical' memory
625  *     layout for the domain. In particular, the bootstrap virtual-memory
626  *     region is a 1:1 mapping to the first section of the pseudo-physical map.
627  *  6. All bootstrap elements are mapped read-writable for the guest OS. The
628  *     only exception is the bootstrap page table, which is mapped read-only.
629  *  7. There is guaranteed to be at least 512kB padding after the final
630  *     bootstrap element. If necessary, the bootstrap virtual region is
631  *     extended by an extra 4MB to ensure this.
632  */
633 
634 #define MAX_GUEST_CMDLINE 1024
635 struct start_info {
636         /* THE FOLLOWING ARE FILLED IN BOTH ON INITIAL BOOT AND ON RESUME.    */
637         char magic[32];             /* "xen-<version>-<platform>".            */
638         unsigned long nr_pages;     /* Total pages allocated to this domain.  */
639         unsigned long shared_info;  /* MACHINE address of shared info struct. */
640         uint32_t flags;             /* SIF_xxx flags.                         */
641         xen_pfn_t store_mfn;        /* MACHINE page number of shared page.    */
642         uint32_t store_evtchn;      /* Event channel for store communication. */
643         union {
644                 struct {
645                         xen_pfn_t mfn;      /* MACHINE page number of console page.   */
646                         uint32_t  evtchn;   /* Event channel for console page.        */
647                 } domU;
648                 struct {
649                         uint32_t info_off;  /* Offset of console_info struct.         */
650                         uint32_t info_size; /* Size of console_info struct from start.*/
651                 } dom0;
652         } console;
653         /* THE FOLLOWING ARE ONLY FILLED IN ON INITIAL BOOT (NOT RESUME).     */
654         unsigned long pt_base;      /* VIRTUAL address of page directory.     */
655         unsigned long nr_pt_frames; /* Number of bootstrap p.t. frames.       */
656         unsigned long mfn_list;     /* VIRTUAL address of page-frame list.    */
657         unsigned long mod_start;    /* VIRTUAL address of pre-loaded module.  */
658         unsigned long mod_len;      /* Size (bytes) of pre-loaded module.     */
659         int8_t cmd_line[MAX_GUEST_CMDLINE];
660         /* The pfn range here covers both page table and p->m table frames.   */
661         unsigned long first_p2m_pfn;/* 1st pfn forming initial P->M table.    */
662         unsigned long nr_p2m_frames;/* # of pfns forming initial P->M table.  */
663 };
664 
665 /* These flags are passed in the 'flags' field of start_info_t. */
666 #define SIF_PRIVILEGED      (1<<0)  /* Is the domain privileged? */
667 #define SIF_INITDOMAIN      (1<<1)  /* Is this the initial control domain? */
668 #define SIF_MULTIBOOT_MOD   (1<<2)  /* Is mod_start a multiboot module? */
669 #define SIF_MOD_START_PFN   (1<<3)  /* Is mod_start a PFN? */
670 #define SIF_VIRT_P2M_4TOOLS (1<<4)  /* Do Xen tools understand a virt. mapped */
671                                     /* P->M making the 3 level tree obsolete? */
672 #define SIF_PM_MASK       (0xFF<<8) /* reserve 1 byte for xen-pm options */
673 
674 /*
675  * A multiboot module is a package containing modules very similar to a
676  * multiboot module array. The only differences are:
677  * - the array of module descriptors is by convention simply at the beginning
678  *   of the multiboot module,
679  * - addresses in the module descriptors are based on the beginning of the
680  *   multiboot module,
681  * - the number of modules is determined by a termination descriptor that has
682  *   mod_start == 0.
683  *
684  * This permits to both build it statically and reference it in a configuration
685  * file, and let the PV guest easily rebase the addresses to virtual addresses
686  * and at the same time count the number of modules.
687  */
688 struct xen_multiboot_mod_list {
689         /* Address of first byte of the module */
690         uint32_t mod_start;
691         /* Address of last byte of the module (inclusive) */
692         uint32_t mod_end;
693         /* Address of zero-terminated command line */
694         uint32_t cmdline;
695         /* Unused, must be zero */
696         uint32_t pad;
697 };
698 /*
699  * The console structure in start_info.console.dom0
700  *
701  * This structure includes a variety of information required to
702  * have a working VGA/VESA console.
703  */
704 struct dom0_vga_console_info {
705         uint8_t video_type;
706 #define XEN_VGATYPE_TEXT_MODE_3 0x03
707 #define XEN_VGATYPE_VESA_LFB    0x23
708 #define XEN_VGATYPE_EFI_LFB     0x70
709 
710         union {
711                 struct {
712                         /* Font height, in pixels. */
713                         uint16_t font_height;
714                         /* Cursor location (column, row). */
715                         uint16_t cursor_x, cursor_y;
716                         /* Number of rows and columns (dimensions in characters). */
717                         uint16_t rows, columns;
718                 } text_mode_3;
719 
720                 struct {
721                         /* Width and height, in pixels. */
722                         uint16_t width, height;
723                         /* Bytes per scan line. */
724                         uint16_t bytes_per_line;
725                         /* Bits per pixel. */
726                         uint16_t bits_per_pixel;
727                         /* LFB physical address, and size (in units of 64kB). */
728                         uint32_t lfb_base;
729                         uint32_t lfb_size;
730                         /* RGB mask offsets and sizes, as defined by VBE 1.2+ */
731                         uint8_t  red_pos, red_size;
732                         uint8_t  green_pos, green_size;
733                         uint8_t  blue_pos, blue_size;
734                         uint8_t  rsvd_pos, rsvd_size;
735 
736                         /* VESA capabilities (offset 0xa, VESA command 0x4f00). */
737                         uint32_t gbl_caps;
738                         /* Mode attributes (offset 0x0, VESA command 0x4f01). */
739                         uint16_t mode_attrs;
740                 } vesa_lfb;
741         } u;
742 };
743 
744 typedef uint64_t cpumap_t;
745 
746 typedef uint8_t xen_domain_handle_t[16];
747 
748 /* Turn a plain number into a C unsigned long constant. */
749 #define __mk_unsigned_long(x) x ## UL
750 #define mk_unsigned_long(x) __mk_unsigned_long(x)
751 
752 #define TMEM_SPEC_VERSION 1
753 
754 struct tmem_op {
755         uint32_t cmd;
756         int32_t pool_id;
757         union {
758                 struct {  /* for cmd == TMEM_NEW_POOL */
759                         uint64_t uuid[2];
760                         uint32_t flags;
761                 } new;
762                 struct {
763                         uint64_t oid[3];
764                         uint32_t index;
765                         uint32_t tmem_offset;
766                         uint32_t pfn_offset;
767                         uint32_t len;
768                         GUEST_HANDLE(void) gmfn; /* guest machine page frame */
769                 } gen;
770         } u;
771 };
772 
773 DEFINE_GUEST_HANDLE(u64);
774 
775 #else /* __ASSEMBLY__ */
776 
777 /* In assembly code we cannot use C numeric constant suffixes. */
778 #define mk_unsigned_long(x) x
779 
780 #endif /* !__ASSEMBLY__ */
781 
782 #endif /* __XEN_PUBLIC_XEN_H__ */
783 

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