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Linux/sound/arm/pxa2xx-ac97-lib.c

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  1 /*
  2  * Based on sound/arm/pxa2xx-ac97.c and sound/soc/pxa/pxa2xx-ac97.c
  3  * which contain:
  4  *
  5  * Author:      Nicolas Pitre
  6  * Created:     Dec 02, 2004
  7  * Copyright:   MontaVista Software Inc.
  8  *
  9  * This program is free software; you can redistribute it and/or modify
 10  * it under the terms of the GNU General Public License version 2 as
 11  * published by the Free Software Foundation.
 12  */
 13 
 14 #include <linux/kernel.h>
 15 #include <linux/platform_device.h>
 16 #include <linux/interrupt.h>
 17 #include <linux/clk.h>
 18 #include <linux/delay.h>
 19 #include <linux/module.h>
 20 #include <linux/gpio.h>
 21 
 22 #include <sound/ac97_codec.h>
 23 #include <sound/pxa2xx-lib.h>
 24 
 25 #include <asm/irq.h>
 26 #include <mach/regs-ac97.h>
 27 #include <mach/audio.h>
 28 
 29 static DEFINE_MUTEX(car_mutex);
 30 static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
 31 static volatile long gsr_bits;
 32 static struct clk *ac97_clk;
 33 static struct clk *ac97conf_clk;
 34 static int reset_gpio;
 35 
 36 extern void pxa27x_assert_ac97reset(int reset_gpio, int on);
 37 
 38 /*
 39  * Beware PXA27x bugs:
 40  *
 41  *   o Slot 12 read from modem space will hang controller.
 42  *   o CDONE, SDONE interrupt fails after any slot 12 IO.
 43  *
 44  * We therefore have an hybrid approach for waiting on SDONE (interrupt or
 45  * 1 jiffy timeout if interrupt never comes).
 46  */
 47 
 48 unsigned short pxa2xx_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
 49 {
 50         unsigned short val = -1;
 51         volatile u32 *reg_addr;
 52 
 53         mutex_lock(&car_mutex);
 54 
 55         /* set up primary or secondary codec space */
 56         if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
 57                 reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
 58         else
 59                 reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
 60         reg_addr += (reg >> 1);
 61 
 62         /* start read access across the ac97 link */
 63         GSR = GSR_CDONE | GSR_SDONE;
 64         gsr_bits = 0;
 65         val = *reg_addr;
 66         if (reg == AC97_GPIO_STATUS)
 67                 goto out;
 68         if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1) <= 0 &&
 69             !((GSR | gsr_bits) & GSR_SDONE)) {
 70                 printk(KERN_ERR "%s: read error (ac97_reg=%d GSR=%#lx)\n",
 71                                 __func__, reg, GSR | gsr_bits);
 72                 val = -1;
 73                 goto out;
 74         }
 75 
 76         /* valid data now */
 77         GSR = GSR_CDONE | GSR_SDONE;
 78         gsr_bits = 0;
 79         val = *reg_addr;
 80         /* but we've just started another cycle... */
 81         wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1);
 82 
 83 out:    mutex_unlock(&car_mutex);
 84         return val;
 85 }
 86 EXPORT_SYMBOL_GPL(pxa2xx_ac97_read);
 87 
 88 void pxa2xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
 89                         unsigned short val)
 90 {
 91         volatile u32 *reg_addr;
 92 
 93         mutex_lock(&car_mutex);
 94 
 95         /* set up primary or secondary codec space */
 96         if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
 97                 reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
 98         else
 99                 reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
100         reg_addr += (reg >> 1);
101 
102         GSR = GSR_CDONE | GSR_SDONE;
103         gsr_bits = 0;
104         *reg_addr = val;
105         if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_CDONE, 1) <= 0 &&
106             !((GSR | gsr_bits) & GSR_CDONE))
107                 printk(KERN_ERR "%s: write error (ac97_reg=%d GSR=%#lx)\n",
108                                 __func__, reg, GSR | gsr_bits);
109 
110         mutex_unlock(&car_mutex);
111 }
112 EXPORT_SYMBOL_GPL(pxa2xx_ac97_write);
113 
114 #ifdef CONFIG_PXA25x
115 static inline void pxa_ac97_warm_pxa25x(void)
116 {
117         gsr_bits = 0;
118 
119         GCR |= GCR_WARM_RST | GCR_PRIRDY_IEN | GCR_SECRDY_IEN;
120         wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
121 }
122 
123 static inline void pxa_ac97_cold_pxa25x(void)
124 {
125         GCR &=  GCR_COLD_RST;  /* clear everything but nCRST */
126         GCR &= ~GCR_COLD_RST;  /* then assert nCRST */
127 
128         gsr_bits = 0;
129 
130         GCR = GCR_COLD_RST;
131         GCR |= GCR_CDONE_IE|GCR_SDONE_IE;
132         wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
133 }
134 #endif
135 
136 #ifdef CONFIG_PXA27x
137 static inline void pxa_ac97_warm_pxa27x(void)
138 {
139         gsr_bits = 0;
140 
141         /* warm reset broken on Bulverde, so manually keep AC97 reset high */
142         pxa27x_assert_ac97reset(reset_gpio, 1);
143         udelay(10);
144         GCR |= GCR_WARM_RST;
145         pxa27x_assert_ac97reset(reset_gpio, 0);
146         udelay(500);
147 }
148 
149 static inline void pxa_ac97_cold_pxa27x(void)
150 {
151         unsigned int timeout;
152 
153         GCR &=  GCR_COLD_RST;  /* clear everything but nCRST */
154         GCR &= ~GCR_COLD_RST;  /* then assert nCRST */
155 
156         gsr_bits = 0;
157 
158         /* PXA27x Developers Manual section 13.5.2.2.1 */
159         clk_enable(ac97conf_clk);
160         udelay(5);
161         clk_disable(ac97conf_clk);
162         GCR = GCR_COLD_RST | GCR_WARM_RST;
163         timeout = 100;     /* wait for the codec-ready bit to be set */
164         while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
165                 mdelay(1);
166 }
167 #endif
168 
169 #ifdef CONFIG_PXA3xx
170 static inline void pxa_ac97_warm_pxa3xx(void)
171 {
172         int timeout = 100;
173 
174         gsr_bits = 0;
175 
176         /* Can't use interrupts */
177         GCR |= GCR_WARM_RST;
178         while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
179                 mdelay(1);
180 }
181 
182 static inline void pxa_ac97_cold_pxa3xx(void)
183 {
184         int timeout = 1000;
185 
186         /* Hold CLKBPB for 100us */
187         GCR = 0;
188         GCR = GCR_CLKBPB;
189         udelay(100);
190         GCR = 0;
191 
192         GCR &=  GCR_COLD_RST;  /* clear everything but nCRST */
193         GCR &= ~GCR_COLD_RST;  /* then assert nCRST */
194 
195         gsr_bits = 0;
196 
197         /* Can't use interrupts on PXA3xx */
198         GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
199 
200         GCR = GCR_WARM_RST | GCR_COLD_RST;
201         while (!(GSR & (GSR_PCR | GSR_SCR)) && timeout--)
202                 mdelay(10);
203 }
204 #endif
205 
206 bool pxa2xx_ac97_try_warm_reset(struct snd_ac97 *ac97)
207 {
208         unsigned long gsr;
209 
210 #ifdef CONFIG_PXA25x
211         if (cpu_is_pxa25x())
212                 pxa_ac97_warm_pxa25x();
213         else
214 #endif
215 #ifdef CONFIG_PXA27x
216         if (cpu_is_pxa27x())
217                 pxa_ac97_warm_pxa27x();
218         else
219 #endif
220 #ifdef CONFIG_PXA3xx
221         if (cpu_is_pxa3xx())
222                 pxa_ac97_warm_pxa3xx();
223         else
224 #endif
225                 BUG();
226         gsr = GSR | gsr_bits;
227         if (!(gsr & (GSR_PCR | GSR_SCR))) {
228                 printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
229                                  __func__, gsr);
230 
231                 return false;
232         }
233 
234         return true;
235 }
236 EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_warm_reset);
237 
238 bool pxa2xx_ac97_try_cold_reset(struct snd_ac97 *ac97)
239 {
240         unsigned long gsr;
241 
242 #ifdef CONFIG_PXA25x
243         if (cpu_is_pxa25x())
244                 pxa_ac97_cold_pxa25x();
245         else
246 #endif
247 #ifdef CONFIG_PXA27x
248         if (cpu_is_pxa27x())
249                 pxa_ac97_cold_pxa27x();
250         else
251 #endif
252 #ifdef CONFIG_PXA3xx
253         if (cpu_is_pxa3xx())
254                 pxa_ac97_cold_pxa3xx();
255         else
256 #endif
257                 BUG();
258 
259         gsr = GSR | gsr_bits;
260         if (!(gsr & (GSR_PCR | GSR_SCR))) {
261                 printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
262                                  __func__, gsr);
263 
264                 return false;
265         }
266 
267         return true;
268 }
269 EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_cold_reset);
270 
271 
272 void pxa2xx_ac97_finish_reset(struct snd_ac97 *ac97)
273 {
274         GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
275         GCR |= GCR_SDONE_IE|GCR_CDONE_IE;
276 }
277 EXPORT_SYMBOL_GPL(pxa2xx_ac97_finish_reset);
278 
279 static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id)
280 {
281         long status;
282 
283         status = GSR;
284         if (status) {
285                 GSR = status;
286                 gsr_bits |= status;
287                 wake_up(&gsr_wq);
288 
289                 /* Although we don't use those we still need to clear them
290                    since they tend to spuriously trigger when MMC is used
291                    (hardware bug? go figure)... */
292                 if (cpu_is_pxa27x()) {
293                         MISR = MISR_EOC;
294                         PISR = PISR_EOC;
295                         MCSR = MCSR_EOC;
296                 }
297 
298                 return IRQ_HANDLED;
299         }
300 
301         return IRQ_NONE;
302 }
303 
304 #ifdef CONFIG_PM
305 int pxa2xx_ac97_hw_suspend(void)
306 {
307         GCR |= GCR_ACLINK_OFF;
308         clk_disable(ac97_clk);
309         return 0;
310 }
311 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_suspend);
312 
313 int pxa2xx_ac97_hw_resume(void)
314 {
315         clk_enable(ac97_clk);
316         return 0;
317 }
318 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_resume);
319 #endif
320 
321 int __devinit pxa2xx_ac97_hw_probe(struct platform_device *dev)
322 {
323         int ret;
324         pxa2xx_audio_ops_t *pdata = dev->dev.platform_data;
325 
326         if (pdata) {
327                 switch (pdata->reset_gpio) {
328                 case 95:
329                 case 113:
330                         reset_gpio = pdata->reset_gpio;
331                         break;
332                 case 0:
333                         reset_gpio = 113;
334                         break;
335                 case -1:
336                         break;
337                 default:
338                         dev_err(&dev->dev, "Invalid reset GPIO %d\n",
339                                 pdata->reset_gpio);
340                 }
341         } else {
342                 if (cpu_is_pxa27x())
343                         reset_gpio = 113;
344         }
345 
346         if (cpu_is_pxa27x()) {
347                 /*
348                  * This gpio is needed for a work-around to a bug in the ac97
349                  * controller during warm reset.  The direction and level is set
350                  * here so that it is an output driven high when switching from
351                  * AC97_nRESET alt function to generic gpio.
352                  */
353                 ret = gpio_request_one(reset_gpio, GPIOF_OUT_INIT_HIGH,
354                                        "pxa27x ac97 reset");
355                 if (ret < 0) {
356                         pr_err("%s: gpio_request_one() failed: %d\n",
357                                __func__, ret);
358                         goto err_conf;
359                 }
360                 pxa27x_assert_ac97reset(reset_gpio, 0);
361 
362                 ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK");
363                 if (IS_ERR(ac97conf_clk)) {
364                         ret = PTR_ERR(ac97conf_clk);
365                         ac97conf_clk = NULL;
366                         goto err_conf;
367                 }
368         }
369 
370         ac97_clk = clk_get(&dev->dev, "AC97CLK");
371         if (IS_ERR(ac97_clk)) {
372                 ret = PTR_ERR(ac97_clk);
373                 ac97_clk = NULL;
374                 goto err_clk;
375         }
376 
377         ret = clk_enable(ac97_clk);
378         if (ret)
379                 goto err_clk2;
380 
381         ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, 0, "AC97", NULL);
382         if (ret < 0)
383                 goto err_irq;
384 
385         return 0;
386 
387 err_irq:
388         GCR |= GCR_ACLINK_OFF;
389 err_clk2:
390         clk_put(ac97_clk);
391         ac97_clk = NULL;
392 err_clk:
393         if (ac97conf_clk) {
394                 clk_put(ac97conf_clk);
395                 ac97conf_clk = NULL;
396         }
397 err_conf:
398         return ret;
399 }
400 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_probe);
401 
402 void pxa2xx_ac97_hw_remove(struct platform_device *dev)
403 {
404         if (cpu_is_pxa27x())
405                 gpio_free(reset_gpio);
406         GCR |= GCR_ACLINK_OFF;
407         free_irq(IRQ_AC97, NULL);
408         if (ac97conf_clk) {
409                 clk_put(ac97conf_clk);
410                 ac97conf_clk = NULL;
411         }
412         clk_disable(ac97_clk);
413         clk_put(ac97_clk);
414         ac97_clk = NULL;
415 }
416 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_remove);
417 
418 MODULE_AUTHOR("Nicolas Pitre");
419 MODULE_DESCRIPTION("Intel/Marvell PXA sound library");
420 MODULE_LICENSE("GPL");
421 
422 

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