1 /*
2 * TC Applied Technologies Digital Interface Communications Engine driver
3 *
4 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
5 * Licensed under the terms of the GNU General Public License, version 2.
6 */
7
8 #include <linux/compat.h>
9 #include <linux/completion.h>
10 #include <linux/delay.h>
11 #include <linux/device.h>
12 #include <linux/firewire.h>
13 #include <linux/firewire-constants.h>
14 #include <linux/jiffies.h>
15 #include <linux/module.h>
16 #include <linux/mod_devicetable.h>
17 #include <linux/mutex.h>
18 #include <linux/slab.h>
19 #include <linux/spinlock.h>
20 #include <linux/wait.h>
21 #include <sound/control.h>
22 #include <sound/core.h>
23 #include <sound/firewire.h>
24 #include <sound/hwdep.h>
25 #include <sound/info.h>
26 #include <sound/initval.h>
27 #include <sound/pcm.h>
28 #include <sound/pcm_params.h>
29 #include "amdtp.h"
30 #include "iso-resources.h"
31 #include "lib.h"
32 #include "dice-interface.h"
33
34
35 struct dice {
36 struct snd_card *card;
37 struct fw_unit *unit;
38 spinlock_t lock;
39 struct mutex mutex;
40 unsigned int global_offset;
41 unsigned int rx_offset;
42 unsigned int clock_caps;
43 unsigned int rx_channels[3];
44 unsigned int rx_midi_ports[3];
45 struct fw_address_handler notification_handler;
46 int owner_generation;
47 int dev_lock_count; /* > 0 driver, < 0 userspace */
48 bool dev_lock_changed;
49 bool global_enabled;
50 struct completion clock_accepted;
51 wait_queue_head_t hwdep_wait;
52 u32 notification_bits;
53 struct fw_iso_resources resources;
54 struct amdtp_out_stream stream;
55 };
56
57 MODULE_DESCRIPTION("DICE driver");
58 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
59 MODULE_LICENSE("GPL v2");
60
61 static const unsigned int dice_rates[] = {
62 /* mode 0 */
63 [0] = 32000,
64 [1] = 44100,
65 [2] = 48000,
66 /* mode 1 */
67 [3] = 88200,
68 [4] = 96000,
69 /* mode 2 */
70 [5] = 176400,
71 [6] = 192000,
72 };
73
74 static unsigned int rate_to_index(unsigned int rate)
75 {
76 unsigned int i;
77
78 for (i = 0; i < ARRAY_SIZE(dice_rates); ++i)
79 if (dice_rates[i] == rate)
80 return i;
81
82 return 0;
83 }
84
85 static unsigned int rate_index_to_mode(unsigned int rate_index)
86 {
87 return ((int)rate_index - 1) / 2;
88 }
89
90 static void dice_lock_changed(struct dice *dice)
91 {
92 dice->dev_lock_changed = true;
93 wake_up(&dice->hwdep_wait);
94 }
95
96 static int dice_try_lock(struct dice *dice)
97 {
98 int err;
99
100 spin_lock_irq(&dice->lock);
101
102 if (dice->dev_lock_count < 0) {
103 err = -EBUSY;
104 goto out;
105 }
106
107 if (dice->dev_lock_count++ == 0)
108 dice_lock_changed(dice);
109 err = 0;
110
111 out:
112 spin_unlock_irq(&dice->lock);
113
114 return err;
115 }
116
117 static void dice_unlock(struct dice *dice)
118 {
119 spin_lock_irq(&dice->lock);
120
121 if (WARN_ON(dice->dev_lock_count <= 0))
122 goto out;
123
124 if (--dice->dev_lock_count == 0)
125 dice_lock_changed(dice);
126
127 out:
128 spin_unlock_irq(&dice->lock);
129 }
130
131 static inline u64 global_address(struct dice *dice, unsigned int offset)
132 {
133 return DICE_PRIVATE_SPACE + dice->global_offset + offset;
134 }
135
136 // TODO: rx index
137 static inline u64 rx_address(struct dice *dice, unsigned int offset)
138 {
139 return DICE_PRIVATE_SPACE + dice->rx_offset + offset;
140 }
141
142 static int dice_owner_set(struct dice *dice)
143 {
144 struct fw_device *device = fw_parent_device(dice->unit);
145 __be64 *buffer;
146 int err, errors = 0;
147
148 buffer = kmalloc(2 * 8, GFP_KERNEL);
149 if (!buffer)
150 return -ENOMEM;
151
152 for (;;) {
153 buffer[0] = cpu_to_be64(OWNER_NO_OWNER);
154 buffer[1] = cpu_to_be64(
155 ((u64)device->card->node_id << OWNER_NODE_SHIFT) |
156 dice->notification_handler.offset);
157
158 dice->owner_generation = device->generation;
159 smp_rmb(); /* node_id vs. generation */
160 err = snd_fw_transaction(dice->unit,
161 TCODE_LOCK_COMPARE_SWAP,
162 global_address(dice, GLOBAL_OWNER),
163 buffer, 2 * 8,
164 FW_FIXED_GENERATION |
165 dice->owner_generation);
166
167 if (err == 0) {
168 if (buffer[0] != cpu_to_be64(OWNER_NO_OWNER)) {
169 dev_err(&dice->unit->device,
170 "device is already in use\n");
171 err = -EBUSY;
172 }
173 break;
174 }
175 if (err != -EAGAIN || ++errors >= 3)
176 break;
177
178 msleep(20);
179 }
180
181 kfree(buffer);
182
183 return err;
184 }
185
186 static int dice_owner_update(struct dice *dice)
187 {
188 struct fw_device *device = fw_parent_device(dice->unit);
189 __be64 *buffer;
190 int err;
191
192 if (dice->owner_generation == -1)
193 return 0;
194
195 buffer = kmalloc(2 * 8, GFP_KERNEL);
196 if (!buffer)
197 return -ENOMEM;
198
199 buffer[0] = cpu_to_be64(OWNER_NO_OWNER);
200 buffer[1] = cpu_to_be64(
201 ((u64)device->card->node_id << OWNER_NODE_SHIFT) |
202 dice->notification_handler.offset);
203
204 dice->owner_generation = device->generation;
205 smp_rmb(); /* node_id vs. generation */
206 err = snd_fw_transaction(dice->unit, TCODE_LOCK_COMPARE_SWAP,
207 global_address(dice, GLOBAL_OWNER),
208 buffer, 2 * 8,
209 FW_FIXED_GENERATION | dice->owner_generation);
210
211 if (err == 0) {
212 if (buffer[0] != cpu_to_be64(OWNER_NO_OWNER)) {
213 dev_err(&dice->unit->device,
214 "device is already in use\n");
215 err = -EBUSY;
216 }
217 } else if (err == -EAGAIN) {
218 err = 0; /* try again later */
219 }
220
221 kfree(buffer);
222
223 if (err < 0)
224 dice->owner_generation = -1;
225
226 return err;
227 }
228
229 static void dice_owner_clear(struct dice *dice)
230 {
231 struct fw_device *device = fw_parent_device(dice->unit);
232 __be64 *buffer;
233
234 buffer = kmalloc(2 * 8, GFP_KERNEL);
235 if (!buffer)
236 return;
237
238 buffer[0] = cpu_to_be64(
239 ((u64)device->card->node_id << OWNER_NODE_SHIFT) |
240 dice->notification_handler.offset);
241 buffer[1] = cpu_to_be64(OWNER_NO_OWNER);
242 snd_fw_transaction(dice->unit, TCODE_LOCK_COMPARE_SWAP,
243 global_address(dice, GLOBAL_OWNER),
244 buffer, 2 * 8, FW_QUIET |
245 FW_FIXED_GENERATION | dice->owner_generation);
246
247 kfree(buffer);
248
249 dice->owner_generation = -1;
250 }
251
252 static int dice_enable_set(struct dice *dice)
253 {
254 __be32 value;
255 int err;
256
257 value = cpu_to_be32(1);
258 err = snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
259 global_address(dice, GLOBAL_ENABLE),
260 &value, 4,
261 FW_FIXED_GENERATION | dice->owner_generation);
262 if (err < 0)
263 return err;
264
265 dice->global_enabled = true;
266
267 return 0;
268 }
269
270 static void dice_enable_clear(struct dice *dice)
271 {
272 __be32 value;
273
274 if (!dice->global_enabled)
275 return;
276
277 value = 0;
278 snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
279 global_address(dice, GLOBAL_ENABLE),
280 &value, 4, FW_QUIET |
281 FW_FIXED_GENERATION | dice->owner_generation);
282
283 dice->global_enabled = false;
284 }
285
286 static void dice_notification(struct fw_card *card, struct fw_request *request,
287 int tcode, int destination, int source,
288 int generation, unsigned long long offset,
289 void *data, size_t length, void *callback_data)
290 {
291 struct dice *dice = callback_data;
292 u32 bits;
293 unsigned long flags;
294
295 if (tcode != TCODE_WRITE_QUADLET_REQUEST) {
296 fw_send_response(card, request, RCODE_TYPE_ERROR);
297 return;
298 }
299 if ((offset & 3) != 0) {
300 fw_send_response(card, request, RCODE_ADDRESS_ERROR);
301 return;
302 }
303
304 bits = be32_to_cpup(data);
305
306 spin_lock_irqsave(&dice->lock, flags);
307 dice->notification_bits |= bits;
308 spin_unlock_irqrestore(&dice->lock, flags);
309
310 fw_send_response(card, request, RCODE_COMPLETE);
311
312 if (bits & NOTIFY_CLOCK_ACCEPTED)
313 complete(&dice->clock_accepted);
314 wake_up(&dice->hwdep_wait);
315 }
316
317 static int dice_rate_constraint(struct snd_pcm_hw_params *params,
318 struct snd_pcm_hw_rule *rule)
319 {
320 struct dice *dice = rule->private;
321 const struct snd_interval *channels =
322 hw_param_interval_c(params, SNDRV_PCM_HW_PARAM_CHANNELS);
323 struct snd_interval *rate =
324 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
325 struct snd_interval allowed_rates = {
326 .min = UINT_MAX, .max = 0, .integer = 1
327 };
328 unsigned int i, mode;
329
330 for (i = 0; i < ARRAY_SIZE(dice_rates); ++i) {
331 mode = rate_index_to_mode(i);
332 if ((dice->clock_caps & (1 << i)) &&
333 snd_interval_test(channels, dice->rx_channels[mode])) {
334 allowed_rates.min = min(allowed_rates.min,
335 dice_rates[i]);
336 allowed_rates.max = max(allowed_rates.max,
337 dice_rates[i]);
338 }
339 }
340
341 return snd_interval_refine(rate, &allowed_rates);
342 }
343
344 static int dice_channels_constraint(struct snd_pcm_hw_params *params,
345 struct snd_pcm_hw_rule *rule)
346 {
347 struct dice *dice = rule->private;
348 const struct snd_interval *rate =
349 hw_param_interval_c(params, SNDRV_PCM_HW_PARAM_RATE);
350 struct snd_interval *channels =
351 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
352 struct snd_interval allowed_channels = {
353 .min = UINT_MAX, .max = 0, .integer = 1
354 };
355 unsigned int i, mode;
356
357 for (i = 0; i < ARRAY_SIZE(dice_rates); ++i)
358 if ((dice->clock_caps & (1 << i)) &&
359 snd_interval_test(rate, dice_rates[i])) {
360 mode = rate_index_to_mode(i);
361 allowed_channels.min = min(allowed_channels.min,
362 dice->rx_channels[mode]);
363 allowed_channels.max = max(allowed_channels.max,
364 dice->rx_channels[mode]);
365 }
366
367 return snd_interval_refine(channels, &allowed_channels);
368 }
369
370 static int dice_open(struct snd_pcm_substream *substream)
371 {
372 static const struct snd_pcm_hardware hardware = {
373 .info = SNDRV_PCM_INFO_MMAP |
374 SNDRV_PCM_INFO_MMAP_VALID |
375 SNDRV_PCM_INFO_BATCH |
376 SNDRV_PCM_INFO_INTERLEAVED |
377 SNDRV_PCM_INFO_BLOCK_TRANSFER,
378 .formats = AMDTP_OUT_PCM_FORMAT_BITS,
379 .channels_min = UINT_MAX,
380 .channels_max = 0,
381 .buffer_bytes_max = 16 * 1024 * 1024,
382 .period_bytes_min = 1,
383 .period_bytes_max = UINT_MAX,
384 .periods_min = 1,
385 .periods_max = UINT_MAX,
386 };
387 struct dice *dice = substream->private_data;
388 struct snd_pcm_runtime *runtime = substream->runtime;
389 unsigned int i;
390 int err;
391
392 err = dice_try_lock(dice);
393 if (err < 0)
394 goto error;
395
396 runtime->hw = hardware;
397
398 for (i = 0; i < ARRAY_SIZE(dice_rates); ++i)
399 if (dice->clock_caps & (1 << i))
400 runtime->hw.rates |=
401 snd_pcm_rate_to_rate_bit(dice_rates[i]);
402 snd_pcm_limit_hw_rates(runtime);
403
404 for (i = 0; i < 3; ++i)
405 if (dice->rx_channels[i]) {
406 runtime->hw.channels_min = min(runtime->hw.channels_min,
407 dice->rx_channels[i]);
408 runtime->hw.channels_max = max(runtime->hw.channels_max,
409 dice->rx_channels[i]);
410 }
411
412 err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
413 dice_rate_constraint, dice,
414 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
415 if (err < 0)
416 goto err_lock;
417 err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
418 dice_channels_constraint, dice,
419 SNDRV_PCM_HW_PARAM_RATE, -1);
420 if (err < 0)
421 goto err_lock;
422
423 err = snd_pcm_hw_constraint_step(runtime, 0,
424 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 32);
425 if (err < 0)
426 goto err_lock;
427 err = snd_pcm_hw_constraint_step(runtime, 0,
428 SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 32);
429 if (err < 0)
430 goto err_lock;
431
432 err = snd_pcm_hw_constraint_minmax(runtime,
433 SNDRV_PCM_HW_PARAM_PERIOD_TIME,
434 5000, UINT_MAX);
435 if (err < 0)
436 goto err_lock;
437
438 err = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
439 if (err < 0)
440 goto err_lock;
441
442 return 0;
443
444 err_lock:
445 dice_unlock(dice);
446 error:
447 return err;
448 }
449
450 static int dice_close(struct snd_pcm_substream *substream)
451 {
452 struct dice *dice = substream->private_data;
453
454 dice_unlock(dice);
455
456 return 0;
457 }
458
459 static int dice_stream_start_packets(struct dice *dice)
460 {
461 int err;
462
463 if (amdtp_out_stream_running(&dice->stream))
464 return 0;
465
466 err = amdtp_out_stream_start(&dice->stream, dice->resources.channel,
467 fw_parent_device(dice->unit)->max_speed);
468 if (err < 0)
469 return err;
470
471 err = dice_enable_set(dice);
472 if (err < 0) {
473 amdtp_out_stream_stop(&dice->stream);
474 return err;
475 }
476
477 return 0;
478 }
479
480 static int dice_stream_start(struct dice *dice)
481 {
482 __be32 channel;
483 int err;
484
485 if (!dice->resources.allocated) {
486 err = fw_iso_resources_allocate(&dice->resources,
487 amdtp_out_stream_get_max_payload(&dice->stream),
488 fw_parent_device(dice->unit)->max_speed);
489 if (err < 0)
490 goto error;
491
492 channel = cpu_to_be32(dice->resources.channel);
493 err = snd_fw_transaction(dice->unit,
494 TCODE_WRITE_QUADLET_REQUEST,
495 rx_address(dice, RX_ISOCHRONOUS),
496 &channel, 4, 0);
497 if (err < 0)
498 goto err_resources;
499 }
500
501 err = dice_stream_start_packets(dice);
502 if (err < 0)
503 goto err_rx_channel;
504
505 return 0;
506
507 err_rx_channel:
508 channel = cpu_to_be32((u32)-1);
509 snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
510 rx_address(dice, RX_ISOCHRONOUS), &channel, 4, 0);
511 err_resources:
512 fw_iso_resources_free(&dice->resources);
513 error:
514 return err;
515 }
516
517 static void dice_stream_stop_packets(struct dice *dice)
518 {
519 if (amdtp_out_stream_running(&dice->stream)) {
520 dice_enable_clear(dice);
521 amdtp_out_stream_stop(&dice->stream);
522 }
523 }
524
525 static void dice_stream_stop(struct dice *dice)
526 {
527 __be32 channel;
528
529 dice_stream_stop_packets(dice);
530
531 if (!dice->resources.allocated)
532 return;
533
534 channel = cpu_to_be32((u32)-1);
535 snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
536 rx_address(dice, RX_ISOCHRONOUS), &channel, 4, 0);
537
538 fw_iso_resources_free(&dice->resources);
539 }
540
541 static int dice_change_rate(struct dice *dice, unsigned int clock_rate)
542 {
543 __be32 value;
544 int err;
545
546 reinit_completion(&dice->clock_accepted);
547
548 value = cpu_to_be32(clock_rate | CLOCK_SOURCE_ARX1);
549 err = snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
550 global_address(dice, GLOBAL_CLOCK_SELECT),
551 &value, 4, 0);
552 if (err < 0)
553 return err;
554
555 if (!wait_for_completion_timeout(&dice->clock_accepted,
556 msecs_to_jiffies(100)))
557 dev_warn(&dice->unit->device, "clock change timed out\n");
558
559 return 0;
560 }
561
562 static int dice_hw_params(struct snd_pcm_substream *substream,
563 struct snd_pcm_hw_params *hw_params)
564 {
565 struct dice *dice = substream->private_data;
566 unsigned int rate_index, mode;
567 int err;
568
569 mutex_lock(&dice->mutex);
570 dice_stream_stop(dice);
571 mutex_unlock(&dice->mutex);
572
573 err = snd_pcm_lib_alloc_vmalloc_buffer(substream,
574 params_buffer_bytes(hw_params));
575 if (err < 0)
576 return err;
577
578 rate_index = rate_to_index(params_rate(hw_params));
579 err = dice_change_rate(dice, rate_index << CLOCK_RATE_SHIFT);
580 if (err < 0)
581 return err;
582
583 mode = rate_index_to_mode(rate_index);
584 amdtp_out_stream_set_parameters(&dice->stream,
585 params_rate(hw_params),
586 params_channels(hw_params),
587 dice->rx_midi_ports[mode]);
588 amdtp_out_stream_set_pcm_format(&dice->stream,
589 params_format(hw_params));
590
591 return 0;
592 }
593
594 static int dice_hw_free(struct snd_pcm_substream *substream)
595 {
596 struct dice *dice = substream->private_data;
597
598 mutex_lock(&dice->mutex);
599 dice_stream_stop(dice);
600 mutex_unlock(&dice->mutex);
601
602 return snd_pcm_lib_free_vmalloc_buffer(substream);
603 }
604
605 static int dice_prepare(struct snd_pcm_substream *substream)
606 {
607 struct dice *dice = substream->private_data;
608 int err;
609
610 mutex_lock(&dice->mutex);
611
612 if (amdtp_out_streaming_error(&dice->stream))
613 dice_stream_stop_packets(dice);
614
615 err = dice_stream_start(dice);
616 if (err < 0) {
617 mutex_unlock(&dice->mutex);
618 return err;
619 }
620
621 mutex_unlock(&dice->mutex);
622
623 amdtp_out_stream_pcm_prepare(&dice->stream);
624
625 return 0;
626 }
627
628 static int dice_trigger(struct snd_pcm_substream *substream, int cmd)
629 {
630 struct dice *dice = substream->private_data;
631 struct snd_pcm_substream *pcm;
632
633 switch (cmd) {
634 case SNDRV_PCM_TRIGGER_START:
635 pcm = substream;
636 break;
637 case SNDRV_PCM_TRIGGER_STOP:
638 pcm = NULL;
639 break;
640 default:
641 return -EINVAL;
642 }
643 amdtp_out_stream_pcm_trigger(&dice->stream, pcm);
644
645 return 0;
646 }
647
648 static snd_pcm_uframes_t dice_pointer(struct snd_pcm_substream *substream)
649 {
650 struct dice *dice = substream->private_data;
651
652 return amdtp_out_stream_pcm_pointer(&dice->stream);
653 }
654
655 static int dice_create_pcm(struct dice *dice)
656 {
657 static struct snd_pcm_ops ops = {
658 .open = dice_open,
659 .close = dice_close,
660 .ioctl = snd_pcm_lib_ioctl,
661 .hw_params = dice_hw_params,
662 .hw_free = dice_hw_free,
663 .prepare = dice_prepare,
664 .trigger = dice_trigger,
665 .pointer = dice_pointer,
666 .page = snd_pcm_lib_get_vmalloc_page,
667 .mmap = snd_pcm_lib_mmap_vmalloc,
668 };
669 struct snd_pcm *pcm;
670 int err;
671
672 err = snd_pcm_new(dice->card, "DICE", 0, 1, 0, &pcm);
673 if (err < 0)
674 return err;
675 pcm->private_data = dice;
676 strcpy(pcm->name, dice->card->shortname);
677 pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream->ops = &ops;
678
679 return 0;
680 }
681
682 static long dice_hwdep_read(struct snd_hwdep *hwdep, char __user *buf,
683 long count, loff_t *offset)
684 {
685 struct dice *dice = hwdep->private_data;
686 DEFINE_WAIT(wait);
687 union snd_firewire_event event;
688
689 spin_lock_irq(&dice->lock);
690
691 while (!dice->dev_lock_changed && dice->notification_bits == 0) {
692 prepare_to_wait(&dice->hwdep_wait, &wait, TASK_INTERRUPTIBLE);
693 spin_unlock_irq(&dice->lock);
694 schedule();
695 finish_wait(&dice->hwdep_wait, &wait);
696 if (signal_pending(current))
697 return -ERESTARTSYS;
698 spin_lock_irq(&dice->lock);
699 }
700
701 memset(&event, 0, sizeof(event));
702 if (dice->dev_lock_changed) {
703 event.lock_status.type = SNDRV_FIREWIRE_EVENT_LOCK_STATUS;
704 event.lock_status.status = dice->dev_lock_count > 0;
705 dice->dev_lock_changed = false;
706
707 count = min(count, (long)sizeof(event.lock_status));
708 } else {
709 event.dice_notification.type = SNDRV_FIREWIRE_EVENT_DICE_NOTIFICATION;
710 event.dice_notification.notification = dice->notification_bits;
711 dice->notification_bits = 0;
712
713 count = min(count, (long)sizeof(event.dice_notification));
714 }
715
716 spin_unlock_irq(&dice->lock);
717
718 if (copy_to_user(buf, &event, count))
719 return -EFAULT;
720
721 return count;
722 }
723
724 static unsigned int dice_hwdep_poll(struct snd_hwdep *hwdep, struct file *file,
725 poll_table *wait)
726 {
727 struct dice *dice = hwdep->private_data;
728 unsigned int events;
729
730 poll_wait(file, &dice->hwdep_wait, wait);
731
732 spin_lock_irq(&dice->lock);
733 if (dice->dev_lock_changed || dice->notification_bits != 0)
734 events = POLLIN | POLLRDNORM;
735 else
736 events = 0;
737 spin_unlock_irq(&dice->lock);
738
739 return events;
740 }
741
742 static int dice_hwdep_get_info(struct dice *dice, void __user *arg)
743 {
744 struct fw_device *dev = fw_parent_device(dice->unit);
745 struct snd_firewire_get_info info;
746
747 memset(&info, 0, sizeof(info));
748 info.type = SNDRV_FIREWIRE_TYPE_DICE;
749 info.card = dev->card->index;
750 *(__be32 *)&info.guid[0] = cpu_to_be32(dev->config_rom[3]);
751 *(__be32 *)&info.guid[4] = cpu_to_be32(dev->config_rom[4]);
752 strlcpy(info.device_name, dev_name(&dev->device),
753 sizeof(info.device_name));
754
755 if (copy_to_user(arg, &info, sizeof(info)))
756 return -EFAULT;
757
758 return 0;
759 }
760
761 static int dice_hwdep_lock(struct dice *dice)
762 {
763 int err;
764
765 spin_lock_irq(&dice->lock);
766
767 if (dice->dev_lock_count == 0) {
768 dice->dev_lock_count = -1;
769 err = 0;
770 } else {
771 err = -EBUSY;
772 }
773
774 spin_unlock_irq(&dice->lock);
775
776 return err;
777 }
778
779 static int dice_hwdep_unlock(struct dice *dice)
780 {
781 int err;
782
783 spin_lock_irq(&dice->lock);
784
785 if (dice->dev_lock_count == -1) {
786 dice->dev_lock_count = 0;
787 err = 0;
788 } else {
789 err = -EBADFD;
790 }
791
792 spin_unlock_irq(&dice->lock);
793
794 return err;
795 }
796
797 static int dice_hwdep_release(struct snd_hwdep *hwdep, struct file *file)
798 {
799 struct dice *dice = hwdep->private_data;
800
801 spin_lock_irq(&dice->lock);
802 if (dice->dev_lock_count == -1)
803 dice->dev_lock_count = 0;
804 spin_unlock_irq(&dice->lock);
805
806 return 0;
807 }
808
809 static int dice_hwdep_ioctl(struct snd_hwdep *hwdep, struct file *file,
810 unsigned int cmd, unsigned long arg)
811 {
812 struct dice *dice = hwdep->private_data;
813
814 switch (cmd) {
815 case SNDRV_FIREWIRE_IOCTL_GET_INFO:
816 return dice_hwdep_get_info(dice, (void __user *)arg);
817 case SNDRV_FIREWIRE_IOCTL_LOCK:
818 return dice_hwdep_lock(dice);
819 case SNDRV_FIREWIRE_IOCTL_UNLOCK:
820 return dice_hwdep_unlock(dice);
821 default:
822 return -ENOIOCTLCMD;
823 }
824 }
825
826 #ifdef CONFIG_COMPAT
827 static int dice_hwdep_compat_ioctl(struct snd_hwdep *hwdep, struct file *file,
828 unsigned int cmd, unsigned long arg)
829 {
830 return dice_hwdep_ioctl(hwdep, file, cmd,
831 (unsigned long)compat_ptr(arg));
832 }
833 #else
834 #define dice_hwdep_compat_ioctl NULL
835 #endif
836
837 static int dice_create_hwdep(struct dice *dice)
838 {
839 static const struct snd_hwdep_ops ops = {
840 .read = dice_hwdep_read,
841 .release = dice_hwdep_release,
842 .poll = dice_hwdep_poll,
843 .ioctl = dice_hwdep_ioctl,
844 .ioctl_compat = dice_hwdep_compat_ioctl,
845 };
846 struct snd_hwdep *hwdep;
847 int err;
848
849 err = snd_hwdep_new(dice->card, "DICE", 0, &hwdep);
850 if (err < 0)
851 return err;
852 strcpy(hwdep->name, "DICE");
853 hwdep->iface = SNDRV_HWDEP_IFACE_FW_DICE;
854 hwdep->ops = ops;
855 hwdep->private_data = dice;
856 hwdep->exclusive = true;
857
858 return 0;
859 }
860
861 static int dice_proc_read_mem(struct dice *dice, void *buffer,
862 unsigned int offset_q, unsigned int quadlets)
863 {
864 unsigned int i;
865 int err;
866
867 err = snd_fw_transaction(dice->unit, TCODE_READ_BLOCK_REQUEST,
868 DICE_PRIVATE_SPACE + 4 * offset_q,
869 buffer, 4 * quadlets, 0);
870 if (err < 0)
871 return err;
872
873 for (i = 0; i < quadlets; ++i)
874 be32_to_cpus(&((u32 *)buffer)[i]);
875
876 return 0;
877 }
878
879 static const char *str_from_array(const char *const strs[], unsigned int count,
880 unsigned int i)
881 {
882 if (i < count)
883 return strs[i];
884 else
885 return "(unknown)";
886 }
887
888 static void dice_proc_fixup_string(char *s, unsigned int size)
889 {
890 unsigned int i;
891
892 for (i = 0; i < size; i += 4)
893 cpu_to_le32s((u32 *)(s + i));
894
895 for (i = 0; i < size - 2; ++i) {
896 if (s[i] == '\0')
897 return;
898 if (s[i] == '\\' && s[i + 1] == '\\') {
899 s[i + 2] = '\0';
900 return;
901 }
902 }
903 s[size - 1] = '\0';
904 }
905
906 static void dice_proc_read(struct snd_info_entry *entry,
907 struct snd_info_buffer *buffer)
908 {
909 static const char *const section_names[5] = {
910 "global", "tx", "rx", "ext_sync", "unused2"
911 };
912 static const char *const clock_sources[] = {
913 "aes1", "aes2", "aes3", "aes4", "aes", "adat", "tdif",
914 "wc", "arx1", "arx2", "arx3", "arx4", "internal"
915 };
916 static const char *const rates[] = {
917 "32000", "44100", "48000", "88200", "96000", "176400", "192000",
918 "any low", "any mid", "any high", "none"
919 };
920 struct dice *dice = entry->private_data;
921 u32 sections[ARRAY_SIZE(section_names) * 2];
922 struct {
923 u32 number;
924 u32 size;
925 } tx_rx_header;
926 union {
927 struct {
928 u32 owner_hi, owner_lo;
929 u32 notification;
930 char nick_name[NICK_NAME_SIZE];
931 u32 clock_select;
932 u32 enable;
933 u32 status;
934 u32 extended_status;
935 u32 sample_rate;
936 u32 version;
937 u32 clock_caps;
938 char clock_source_names[CLOCK_SOURCE_NAMES_SIZE];
939 } global;
940 struct {
941 u32 iso;
942 u32 number_audio;
943 u32 number_midi;
944 u32 speed;
945 char names[TX_NAMES_SIZE];
946 u32 ac3_caps;
947 u32 ac3_enable;
948 } tx;
949 struct {
950 u32 iso;
951 u32 seq_start;
952 u32 number_audio;
953 u32 number_midi;
954 char names[RX_NAMES_SIZE];
955 u32 ac3_caps;
956 u32 ac3_enable;
957 } rx;
958 struct {
959 u32 clock_source;
960 u32 locked;
961 u32 rate;
962 u32 adat_user_data;
963 } ext_sync;
964 } buf;
965 unsigned int quadlets, stream, i;
966
967 if (dice_proc_read_mem(dice, sections, 0, ARRAY_SIZE(sections)) < 0)
968 return;
969 snd_iprintf(buffer, "sections:\n");
970 for (i = 0; i < ARRAY_SIZE(section_names); ++i)
971 snd_iprintf(buffer, " %s: offset %u, size %u\n",
972 section_names[i],
973 sections[i * 2], sections[i * 2 + 1]);
974
975 quadlets = min_t(u32, sections[1], sizeof(buf.global) / 4);
976 if (dice_proc_read_mem(dice, &buf.global, sections[0], quadlets) < 0)
977 return;
978 snd_iprintf(buffer, "global:\n");
979 snd_iprintf(buffer, " owner: %04x:%04x%08x\n",
980 buf.global.owner_hi >> 16,
981 buf.global.owner_hi & 0xffff, buf.global.owner_lo);
982 snd_iprintf(buffer, " notification: %08x\n", buf.global.notification);
983 dice_proc_fixup_string(buf.global.nick_name, NICK_NAME_SIZE);
984 snd_iprintf(buffer, " nick name: %s\n", buf.global.nick_name);
985 snd_iprintf(buffer, " clock select: %s %s\n",
986 str_from_array(clock_sources, ARRAY_SIZE(clock_sources),
987 buf.global.clock_select & CLOCK_SOURCE_MASK),
988 str_from_array(rates, ARRAY_SIZE(rates),
989 (buf.global.clock_select & CLOCK_RATE_MASK)
990 >> CLOCK_RATE_SHIFT));
991 snd_iprintf(buffer, " enable: %u\n", buf.global.enable);
992 snd_iprintf(buffer, " status: %slocked %s\n",
993 buf.global.status & STATUS_SOURCE_LOCKED ? "" : "un",
994 str_from_array(rates, ARRAY_SIZE(rates),
995 (buf.global.status &
996 STATUS_NOMINAL_RATE_MASK)
997 >> CLOCK_RATE_SHIFT));
998 snd_iprintf(buffer, " ext status: %08x\n", buf.global.extended_status);
999 snd_iprintf(buffer, " sample rate: %u\n", buf.global.sample_rate);
1000 snd_iprintf(buffer, " version: %u.%u.%u.%u\n",
1001 (buf.global.version >> 24) & 0xff,
1002 (buf.global.version >> 16) & 0xff,
1003 (buf.global.version >> 8) & 0xff,
1004 (buf.global.version >> 0) & 0xff);
1005 if (quadlets >= 90) {
1006 snd_iprintf(buffer, " clock caps:");
1007 for (i = 0; i <= 6; ++i)
1008 if (buf.global.clock_caps & (1 << i))
1009 snd_iprintf(buffer, " %s", rates[i]);
1010 for (i = 0; i <= 12; ++i)
1011 if (buf.global.clock_caps & (1 << (16 + i)))
1012 snd_iprintf(buffer, " %s", clock_sources[i]);
1013 snd_iprintf(buffer, "\n");
1014 dice_proc_fixup_string(buf.global.clock_source_names,
1015 CLOCK_SOURCE_NAMES_SIZE);
1016 snd_iprintf(buffer, " clock source names: %s\n",
1017 buf.global.clock_source_names);
1018 }
1019
1020 if (dice_proc_read_mem(dice, &tx_rx_header, sections[2], 2) < 0)
1021 return;
1022 quadlets = min_t(u32, tx_rx_header.size, sizeof(buf.tx) / 4);
1023 for (stream = 0; stream < tx_rx_header.number; ++stream) {
1024 if (dice_proc_read_mem(dice, &buf.tx, sections[2] + 2 +
1025 stream * tx_rx_header.size,
1026 quadlets) < 0)
1027 break;
1028 snd_iprintf(buffer, "tx %u:\n", stream);
1029 snd_iprintf(buffer, " iso channel: %d\n", (int)buf.tx.iso);
1030 snd_iprintf(buffer, " audio channels: %u\n",
1031 buf.tx.number_audio);
1032 snd_iprintf(buffer, " midi ports: %u\n", buf.tx.number_midi);
1033 snd_iprintf(buffer, " speed: S%u\n", 100u << buf.tx.speed);
1034 if (quadlets >= 68) {
1035 dice_proc_fixup_string(buf.tx.names, TX_NAMES_SIZE);
1036 snd_iprintf(buffer, " names: %s\n", buf.tx.names);
1037 }
1038 if (quadlets >= 70) {
1039 snd_iprintf(buffer, " ac3 caps: %08x\n",
1040 buf.tx.ac3_caps);
1041 snd_iprintf(buffer, " ac3 enable: %08x\n",
1042 buf.tx.ac3_enable);
1043 }
1044 }
1045
1046 if (dice_proc_read_mem(dice, &tx_rx_header, sections[4], 2) < 0)
1047 return;
1048 quadlets = min_t(u32, tx_rx_header.size, sizeof(buf.rx) / 4);
1049 for (stream = 0; stream < tx_rx_header.number; ++stream) {
1050 if (dice_proc_read_mem(dice, &buf.rx, sections[4] + 2 +
1051 stream * tx_rx_header.size,
1052 quadlets) < 0)
1053 break;
1054 snd_iprintf(buffer, "rx %u:\n", stream);
1055 snd_iprintf(buffer, " iso channel: %d\n", (int)buf.rx.iso);
1056 snd_iprintf(buffer, " sequence start: %u\n", buf.rx.seq_start);
1057 snd_iprintf(buffer, " audio channels: %u\n",
1058 buf.rx.number_audio);
1059 snd_iprintf(buffer, " midi ports: %u\n", buf.rx.number_midi);
1060 if (quadlets >= 68) {
1061 dice_proc_fixup_string(buf.rx.names, RX_NAMES_SIZE);
1062 snd_iprintf(buffer, " names: %s\n", buf.rx.names);
1063 }
1064 if (quadlets >= 70) {
1065 snd_iprintf(buffer, " ac3 caps: %08x\n",
1066 buf.rx.ac3_caps);
1067 snd_iprintf(buffer, " ac3 enable: %08x\n",
1068 buf.rx.ac3_enable);
1069 }
1070 }
1071
1072 quadlets = min_t(u32, sections[7], sizeof(buf.ext_sync) / 4);
1073 if (quadlets >= 4) {
1074 if (dice_proc_read_mem(dice, &buf.ext_sync,
1075 sections[6], 4) < 0)
1076 return;
1077 snd_iprintf(buffer, "ext status:\n");
1078 snd_iprintf(buffer, " clock source: %s\n",
1079 str_from_array(clock_sources,
1080 ARRAY_SIZE(clock_sources),
1081 buf.ext_sync.clock_source));
1082 snd_iprintf(buffer, " locked: %u\n", buf.ext_sync.locked);
1083 snd_iprintf(buffer, " rate: %s\n",
1084 str_from_array(rates, ARRAY_SIZE(rates),
1085 buf.ext_sync.rate));
1086 snd_iprintf(buffer, " adat user data: ");
1087 if (buf.ext_sync.adat_user_data & ADAT_USER_DATA_NO_DATA)
1088 snd_iprintf(buffer, "-\n");
1089 else
1090 snd_iprintf(buffer, "%x\n",
1091 buf.ext_sync.adat_user_data);
1092 }
1093 }
1094
1095 static void dice_create_proc(struct dice *dice)
1096 {
1097 struct snd_info_entry *entry;
1098
1099 if (!snd_card_proc_new(dice->card, "dice", &entry))
1100 snd_info_set_text_ops(entry, dice, dice_proc_read);
1101 }
1102
1103 static void dice_card_free(struct snd_card *card)
1104 {
1105 struct dice *dice = card->private_data;
1106
1107 amdtp_out_stream_destroy(&dice->stream);
1108 fw_core_remove_address_handler(&dice->notification_handler);
1109 mutex_destroy(&dice->mutex);
1110 }
1111
1112 #define OUI_WEISS 0x001c6a
1113
1114 #define DICE_CATEGORY_ID 0x04
1115 #define WEISS_CATEGORY_ID 0x00
1116
1117 static int dice_interface_check(struct fw_unit *unit)
1118 {
1119 static const int min_values[10] = {
1120 10, 0x64 / 4,
1121 10, 0x18 / 4,
1122 10, 0x18 / 4,
1123 0, 0,
1124 0, 0,
1125 };
1126 struct fw_device *device = fw_parent_device(unit);
1127 struct fw_csr_iterator it;
1128 int key, value, vendor = -1, model = -1, err;
1129 unsigned int category, i;
1130 __be32 pointers[ARRAY_SIZE(min_values)];
1131 __be32 tx_data[4];
1132 __be32 version;
1133
1134 /*
1135 * Check that GUID and unit directory are constructed according to DICE
1136 * rules, i.e., that the specifier ID is the GUID's OUI, and that the
1137 * GUID chip ID consists of the 8-bit category ID, the 10-bit product
1138 * ID, and a 22-bit serial number.
1139 */
1140 fw_csr_iterator_init(&it, unit->directory);
1141 while (fw_csr_iterator_next(&it, &key, &value)) {
1142 switch (key) {
1143 case CSR_SPECIFIER_ID:
1144 vendor = value;
1145 break;
1146 case CSR_MODEL:
1147 model = value;
1148 break;
1149 }
1150 }
1151 if (vendor == OUI_WEISS)
1152 category = WEISS_CATEGORY_ID;
1153 else
1154 category = DICE_CATEGORY_ID;
1155 if (device->config_rom[3] != ((vendor << 8) | category) ||
1156 device->config_rom[4] >> 22 != model)
1157 return -ENODEV;
1158
1159 /*
1160 * Check that the sub address spaces exist and are located inside the
1161 * private address space. The minimum values are chosen so that all
1162 * minimally required registers are included.
1163 */
1164 err = snd_fw_transaction(unit, TCODE_READ_BLOCK_REQUEST,
1165 DICE_PRIVATE_SPACE,
1166 pointers, sizeof(pointers), 0);
1167 if (err < 0)
1168 return -ENODEV;
1169 for (i = 0; i < ARRAY_SIZE(pointers); ++i) {
1170 value = be32_to_cpu(pointers[i]);
1171 if (value < min_values[i] || value >= 0x40000)
1172 return -ENODEV;
1173 }
1174
1175 /* We support playback only. Let capture devices be handled by FFADO. */
1176 err = snd_fw_transaction(unit, TCODE_READ_BLOCK_REQUEST,
1177 DICE_PRIVATE_SPACE +
1178 be32_to_cpu(pointers[2]) * 4,
1179 tx_data, sizeof(tx_data), 0);
1180 if (err < 0 || (tx_data[0] && tx_data[3]))
1181 return -ENODEV;
1182
1183 /*
1184 * Check that the implemented DICE driver specification major version
1185 * number matches.
1186 */
1187 err = snd_fw_transaction(unit, TCODE_READ_QUADLET_REQUEST,
1188 DICE_PRIVATE_SPACE +
1189 be32_to_cpu(pointers[0]) * 4 + GLOBAL_VERSION,
1190 &version, 4, 0);
1191 if (err < 0)
1192 return -ENODEV;
1193 if ((version & cpu_to_be32(0xff000000)) != cpu_to_be32(0x01000000)) {
1194 dev_err(&unit->device,
1195 "unknown DICE version: 0x%08x\n", be32_to_cpu(version));
1196 return -ENODEV;
1197 }
1198
1199 return 0;
1200 }
1201
1202 static int highest_supported_mode_rate(struct dice *dice, unsigned int mode)
1203 {
1204 int i;
1205
1206 for (i = ARRAY_SIZE(dice_rates) - 1; i >= 0; --i)
1207 if ((dice->clock_caps & (1 << i)) &&
1208 rate_index_to_mode(i) == mode)
1209 return i;
1210
1211 return -1;
1212 }
1213
1214 static int dice_read_mode_params(struct dice *dice, unsigned int mode)
1215 {
1216 __be32 values[2];
1217 int rate_index, err;
1218
1219 rate_index = highest_supported_mode_rate(dice, mode);
1220 if (rate_index < 0) {
1221 dice->rx_channels[mode] = 0;
1222 dice->rx_midi_ports[mode] = 0;
1223 return 0;
1224 }
1225
1226 err = dice_change_rate(dice, rate_index << CLOCK_RATE_SHIFT);
1227 if (err < 0)
1228 return err;
1229
1230 err = snd_fw_transaction(dice->unit, TCODE_READ_BLOCK_REQUEST,
1231 rx_address(dice, RX_NUMBER_AUDIO),
1232 values, 2 * 4, 0);
1233 if (err < 0)
1234 return err;
1235
1236 dice->rx_channels[mode] = be32_to_cpu(values[0]);
1237 dice->rx_midi_ports[mode] = be32_to_cpu(values[1]);
1238
1239 return 0;
1240 }
1241
1242 static int dice_read_params(struct dice *dice)
1243 {
1244 __be32 pointers[6];
1245 __be32 value;
1246 int mode, err;
1247
1248 err = snd_fw_transaction(dice->unit, TCODE_READ_BLOCK_REQUEST,
1249 DICE_PRIVATE_SPACE,
1250 pointers, sizeof(pointers), 0);
1251 if (err < 0)
1252 return err;
1253
1254 dice->global_offset = be32_to_cpu(pointers[0]) * 4;
1255 dice->rx_offset = be32_to_cpu(pointers[4]) * 4;
1256
1257 /* some very old firmwares don't tell about their clock support */
1258 if (be32_to_cpu(pointers[1]) * 4 >= GLOBAL_CLOCK_CAPABILITIES + 4) {
1259 err = snd_fw_transaction(
1260 dice->unit, TCODE_READ_QUADLET_REQUEST,
1261 global_address(dice, GLOBAL_CLOCK_CAPABILITIES),
1262 &value, 4, 0);
1263 if (err < 0)
1264 return err;
1265 dice->clock_caps = be32_to_cpu(value);
1266 } else {
1267 /* this should be supported by any device */
1268 dice->clock_caps = CLOCK_CAP_RATE_44100 |
1269 CLOCK_CAP_RATE_48000 |
1270 CLOCK_CAP_SOURCE_ARX1 |
1271 CLOCK_CAP_SOURCE_INTERNAL;
1272 }
1273
1274 for (mode = 2; mode >= 0; --mode) {
1275 err = dice_read_mode_params(dice, mode);
1276 if (err < 0)
1277 return err;
1278 }
1279
1280 return 0;
1281 }
1282
1283 static void dice_card_strings(struct dice *dice)
1284 {
1285 struct snd_card *card = dice->card;
1286 struct fw_device *dev = fw_parent_device(dice->unit);
1287 char vendor[32], model[32];
1288 unsigned int i;
1289 int err;
1290
1291 strcpy(card->driver, "DICE");
1292
1293 strcpy(card->shortname, "DICE");
1294 BUILD_BUG_ON(NICK_NAME_SIZE < sizeof(card->shortname));
1295 err = snd_fw_transaction(dice->unit, TCODE_READ_BLOCK_REQUEST,
1296 global_address(dice, GLOBAL_NICK_NAME),
1297 card->shortname, sizeof(card->shortname), 0);
1298 if (err >= 0) {
1299 /* DICE strings are returned in "always-wrong" endianness */
1300 BUILD_BUG_ON(sizeof(card->shortname) % 4 != 0);
1301 for (i = 0; i < sizeof(card->shortname); i += 4)
1302 swab32s((u32 *)&card->shortname[i]);
1303 card->shortname[sizeof(card->shortname) - 1] = '\0';
1304 }
1305
1306 strcpy(vendor, "?");
1307 fw_csr_string(dev->config_rom + 5, CSR_VENDOR, vendor, sizeof(vendor));
1308 strcpy(model, "?");
1309 fw_csr_string(dice->unit->directory, CSR_MODEL, model, sizeof(model));
1310 snprintf(card->longname, sizeof(card->longname),
1311 "%s %s (serial %u) at %s, S%d",
1312 vendor, model, dev->config_rom[4] & 0x3fffff,
1313 dev_name(&dice->unit->device), 100 << dev->max_speed);
1314
1315 strcpy(card->mixername, "DICE");
1316 }
1317
1318 static int dice_probe(struct fw_unit *unit, const struct ieee1394_device_id *id)
1319 {
1320 struct snd_card *card;
1321 struct dice *dice;
1322 __be32 clock_sel;
1323 int err;
1324
1325 err = dice_interface_check(unit);
1326 if (err < 0)
1327 return err;
1328
1329 err = snd_card_new(&unit->device, -1, NULL, THIS_MODULE,
1330 sizeof(*dice), &card);
1331 if (err < 0)
1332 return err;
1333
1334 dice = card->private_data;
1335 dice->card = card;
1336 spin_lock_init(&dice->lock);
1337 mutex_init(&dice->mutex);
1338 dice->unit = unit;
1339 init_completion(&dice->clock_accepted);
1340 init_waitqueue_head(&dice->hwdep_wait);
1341
1342 dice->notification_handler.length = 4;
1343 dice->notification_handler.address_callback = dice_notification;
1344 dice->notification_handler.callback_data = dice;
1345 err = fw_core_add_address_handler(&dice->notification_handler,
1346 &fw_high_memory_region);
1347 if (err < 0)
1348 goto err_mutex;
1349
1350 err = dice_owner_set(dice);
1351 if (err < 0)
1352 goto err_notification_handler;
1353
1354 err = dice_read_params(dice);
1355 if (err < 0)
1356 goto err_owner;
1357
1358 err = fw_iso_resources_init(&dice->resources, unit);
1359 if (err < 0)
1360 goto err_owner;
1361 dice->resources.channels_mask = 0x00000000ffffffffuLL;
1362
1363 err = amdtp_out_stream_init(&dice->stream, unit,
1364 CIP_BLOCKING | CIP_HI_DUALWIRE);
1365 if (err < 0)
1366 goto err_resources;
1367
1368 card->private_free = dice_card_free;
1369
1370 dice_card_strings(dice);
1371
1372 err = snd_fw_transaction(unit, TCODE_READ_QUADLET_REQUEST,
1373 global_address(dice, GLOBAL_CLOCK_SELECT),
1374 &clock_sel, 4, 0);
1375 if (err < 0)
1376 goto error;
1377 clock_sel &= cpu_to_be32(~CLOCK_SOURCE_MASK);
1378 clock_sel |= cpu_to_be32(CLOCK_SOURCE_ARX1);
1379 err = snd_fw_transaction(unit, TCODE_WRITE_QUADLET_REQUEST,
1380 global_address(dice, GLOBAL_CLOCK_SELECT),
1381 &clock_sel, 4, 0);
1382 if (err < 0)
1383 goto error;
1384
1385 err = dice_create_pcm(dice);
1386 if (err < 0)
1387 goto error;
1388
1389 err = dice_create_hwdep(dice);
1390 if (err < 0)
1391 goto error;
1392
1393 dice_create_proc(dice);
1394
1395 err = snd_card_register(card);
1396 if (err < 0)
1397 goto error;
1398
1399 dev_set_drvdata(&unit->device, dice);
1400
1401 return 0;
1402
1403 err_resources:
1404 fw_iso_resources_destroy(&dice->resources);
1405 err_owner:
1406 dice_owner_clear(dice);
1407 err_notification_handler:
1408 fw_core_remove_address_handler(&dice->notification_handler);
1409 err_mutex:
1410 mutex_destroy(&dice->mutex);
1411 error:
1412 snd_card_free(card);
1413 return err;
1414 }
1415
1416 static void dice_remove(struct fw_unit *unit)
1417 {
1418 struct dice *dice = dev_get_drvdata(&unit->device);
1419
1420 amdtp_out_stream_pcm_abort(&dice->stream);
1421
1422 snd_card_disconnect(dice->card);
1423
1424 mutex_lock(&dice->mutex);
1425
1426 dice_stream_stop(dice);
1427 dice_owner_clear(dice);
1428
1429 mutex_unlock(&dice->mutex);
1430
1431 snd_card_free_when_closed(dice->card);
1432 }
1433
1434 static void dice_bus_reset(struct fw_unit *unit)
1435 {
1436 struct dice *dice = dev_get_drvdata(&unit->device);
1437
1438 /*
1439 * On a bus reset, the DICE firmware disables streaming and then goes
1440 * off contemplating its own navel for hundreds of milliseconds before
1441 * it can react to any of our attempts to reenable streaming. This
1442 * means that we lose synchronization anyway, so we force our streams
1443 * to stop so that the application can restart them in an orderly
1444 * manner.
1445 */
1446 amdtp_out_stream_pcm_abort(&dice->stream);
1447
1448 mutex_lock(&dice->mutex);
1449
1450 dice->global_enabled = false;
1451 dice_stream_stop_packets(dice);
1452
1453 dice_owner_update(dice);
1454
1455 fw_iso_resources_update(&dice->resources);
1456
1457 mutex_unlock(&dice->mutex);
1458 }
1459
1460 #define DICE_INTERFACE 0x000001
1461
1462 static const struct ieee1394_device_id dice_id_table[] = {
1463 {
1464 .match_flags = IEEE1394_MATCH_VERSION,
1465 .version = DICE_INTERFACE,
1466 },
1467 { }
1468 };
1469 MODULE_DEVICE_TABLE(ieee1394, dice_id_table);
1470
1471 static struct fw_driver dice_driver = {
1472 .driver = {
1473 .owner = THIS_MODULE,
1474 .name = KBUILD_MODNAME,
1475 .bus = &fw_bus_type,
1476 },
1477 .probe = dice_probe,
1478 .update = dice_bus_reset,
1479 .remove = dice_remove,
1480 .id_table = dice_id_table,
1481 };
1482
1483 static int __init alsa_dice_init(void)
1484 {
1485 return driver_register(&dice_driver.driver);
1486 }
1487
1488 static void __exit alsa_dice_exit(void)
1489 {
1490 driver_unregister(&dice_driver.driver);
1491 }
1492
1493 module_init(alsa_dice_init);
1494 module_exit(alsa_dice_exit);
1495
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