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Linux/sound/hda/hdac_stream.c

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  1 // SPDX-License-Identifier: GPL-2.0-only
  2 /*
  3  * HD-audio stream operations
  4  */
  5 
  6 #include <linux/kernel.h>
  7 #include <linux/delay.h>
  8 #include <linux/export.h>
  9 #include <linux/clocksource.h>
 10 #include <sound/core.h>
 11 #include <sound/pcm.h>
 12 #include <sound/hdaudio.h>
 13 #include <sound/hda_register.h>
 14 #include "trace.h"
 15 
 16 /**
 17  * snd_hdac_get_stream_stripe_ctl - get stripe control value
 18  * @bus: HD-audio core bus
 19  * @substream: PCM substream
 20  */
 21 int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus,
 22                                    struct snd_pcm_substream *substream)
 23 {
 24         struct snd_pcm_runtime *runtime = substream->runtime;
 25         unsigned int channels = runtime->channels,
 26                      rate = runtime->rate,
 27                      bits_per_sample = runtime->sample_bits,
 28                      max_sdo_lines, value, sdo_line;
 29 
 30         /* T_AZA_GCAP_NSDO is 1:2 bitfields in GCAP */
 31         max_sdo_lines = snd_hdac_chip_readl(bus, GCAP) & AZX_GCAP_NSDO;
 32 
 33         /* following is from HD audio spec */
 34         for (sdo_line = max_sdo_lines; sdo_line > 0; sdo_line >>= 1) {
 35                 if (rate > 48000)
 36                         value = (channels * bits_per_sample *
 37                                         (rate / 48000)) / sdo_line;
 38                 else
 39                         value = (channels * bits_per_sample) / sdo_line;
 40 
 41                 if (value >= 8)
 42                         break;
 43         }
 44 
 45         /* stripe value: 0 for 1SDO, 1 for 2SDO, 2 for 4SDO lines */
 46         return sdo_line >> 1;
 47 }
 48 EXPORT_SYMBOL_GPL(snd_hdac_get_stream_stripe_ctl);
 49 
 50 /**
 51  * snd_hdac_stream_init - initialize each stream (aka device)
 52  * @bus: HD-audio core bus
 53  * @azx_dev: HD-audio core stream object to initialize
 54  * @idx: stream index number
 55  * @direction: stream direction (SNDRV_PCM_STREAM_PLAYBACK or SNDRV_PCM_STREAM_CAPTURE)
 56  * @tag: the tag id to assign
 57  *
 58  * Assign the starting bdl address to each stream (device) and initialize.
 59  */
 60 void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev,
 61                           int idx, int direction, int tag)
 62 {
 63         azx_dev->bus = bus;
 64         /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
 65         azx_dev->sd_addr = bus->remap_addr + (0x20 * idx + 0x80);
 66         /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
 67         azx_dev->sd_int_sta_mask = 1 << idx;
 68         azx_dev->index = idx;
 69         azx_dev->direction = direction;
 70         azx_dev->stream_tag = tag;
 71         snd_hdac_dsp_lock_init(azx_dev);
 72         list_add_tail(&azx_dev->list, &bus->stream_list);
 73 }
 74 EXPORT_SYMBOL_GPL(snd_hdac_stream_init);
 75 
 76 /**
 77  * snd_hdac_stream_start - start a stream
 78  * @azx_dev: HD-audio core stream to start
 79  * @fresh_start: false = wallclock timestamp relative to period wallclock
 80  *
 81  * Start a stream, set start_wallclk and set the running flag.
 82  */
 83 void snd_hdac_stream_start(struct hdac_stream *azx_dev, bool fresh_start)
 84 {
 85         struct hdac_bus *bus = azx_dev->bus;
 86         int stripe_ctl;
 87 
 88         trace_snd_hdac_stream_start(bus, azx_dev);
 89 
 90         azx_dev->start_wallclk = snd_hdac_chip_readl(bus, WALLCLK);
 91         if (!fresh_start)
 92                 azx_dev->start_wallclk -= azx_dev->period_wallclk;
 93 
 94         /* enable SIE */
 95         snd_hdac_chip_updatel(bus, INTCTL,
 96                               1 << azx_dev->index,
 97                               1 << azx_dev->index);
 98         /* set stripe control */
 99         if (azx_dev->stripe) {
100                 if (azx_dev->substream)
101                         stripe_ctl = snd_hdac_get_stream_stripe_ctl(bus, azx_dev->substream);
102                 else
103                         stripe_ctl = 0;
104                 snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK,
105                                         stripe_ctl);
106         }
107         /* set DMA start and interrupt mask */
108         snd_hdac_stream_updateb(azx_dev, SD_CTL,
109                                 0, SD_CTL_DMA_START | SD_INT_MASK);
110         azx_dev->running = true;
111 }
112 EXPORT_SYMBOL_GPL(snd_hdac_stream_start);
113 
114 /**
115  * snd_hdac_stream_clear - stop a stream DMA
116  * @azx_dev: HD-audio core stream to stop
117  */
118 void snd_hdac_stream_clear(struct hdac_stream *azx_dev)
119 {
120         snd_hdac_stream_updateb(azx_dev, SD_CTL,
121                                 SD_CTL_DMA_START | SD_INT_MASK, 0);
122         snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
123         if (azx_dev->stripe) {
124                 snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK, 0);
125                 azx_dev->stripe = 0;
126         }
127         azx_dev->running = false;
128 }
129 EXPORT_SYMBOL_GPL(snd_hdac_stream_clear);
130 
131 /**
132  * snd_hdac_stream_stop - stop a stream
133  * @azx_dev: HD-audio core stream to stop
134  *
135  * Stop a stream DMA and disable stream interrupt
136  */
137 void snd_hdac_stream_stop(struct hdac_stream *azx_dev)
138 {
139         trace_snd_hdac_stream_stop(azx_dev->bus, azx_dev);
140 
141         snd_hdac_stream_clear(azx_dev);
142         /* disable SIE */
143         snd_hdac_chip_updatel(azx_dev->bus, INTCTL, 1 << azx_dev->index, 0);
144 }
145 EXPORT_SYMBOL_GPL(snd_hdac_stream_stop);
146 
147 /**
148  * snd_hdac_stream_reset - reset a stream
149  * @azx_dev: HD-audio core stream to reset
150  */
151 void snd_hdac_stream_reset(struct hdac_stream *azx_dev)
152 {
153         unsigned char val;
154         int timeout;
155 
156         snd_hdac_stream_clear(azx_dev);
157 
158         snd_hdac_stream_updateb(azx_dev, SD_CTL, 0, SD_CTL_STREAM_RESET);
159         udelay(3);
160         timeout = 300;
161         do {
162                 val = snd_hdac_stream_readb(azx_dev, SD_CTL) &
163                         SD_CTL_STREAM_RESET;
164                 if (val)
165                         break;
166         } while (--timeout);
167         val &= ~SD_CTL_STREAM_RESET;
168         snd_hdac_stream_writeb(azx_dev, SD_CTL, val);
169         udelay(3);
170 
171         timeout = 300;
172         /* waiting for hardware to report that the stream is out of reset */
173         do {
174                 val = snd_hdac_stream_readb(azx_dev, SD_CTL) &
175                         SD_CTL_STREAM_RESET;
176                 if (!val)
177                         break;
178         } while (--timeout);
179 
180         /* reset first position - may not be synced with hw at this time */
181         if (azx_dev->posbuf)
182                 *azx_dev->posbuf = 0;
183 }
184 EXPORT_SYMBOL_GPL(snd_hdac_stream_reset);
185 
186 /**
187  * snd_hdac_stream_setup -  set up the SD for streaming
188  * @azx_dev: HD-audio core stream to set up
189  */
190 int snd_hdac_stream_setup(struct hdac_stream *azx_dev)
191 {
192         struct hdac_bus *bus = azx_dev->bus;
193         struct snd_pcm_runtime *runtime;
194         unsigned int val;
195 
196         if (azx_dev->substream)
197                 runtime = azx_dev->substream->runtime;
198         else
199                 runtime = NULL;
200         /* make sure the run bit is zero for SD */
201         snd_hdac_stream_clear(azx_dev);
202         /* program the stream_tag */
203         val = snd_hdac_stream_readl(azx_dev, SD_CTL);
204         val = (val & ~SD_CTL_STREAM_TAG_MASK) |
205                 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
206         if (!bus->snoop)
207                 val |= SD_CTL_TRAFFIC_PRIO;
208         snd_hdac_stream_writel(azx_dev, SD_CTL, val);
209 
210         /* program the length of samples in cyclic buffer */
211         snd_hdac_stream_writel(azx_dev, SD_CBL, azx_dev->bufsize);
212 
213         /* program the stream format */
214         /* this value needs to be the same as the one programmed */
215         snd_hdac_stream_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
216 
217         /* program the stream LVI (last valid index) of the BDL */
218         snd_hdac_stream_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
219 
220         /* program the BDL address */
221         /* lower BDL address */
222         snd_hdac_stream_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
223         /* upper BDL address */
224         snd_hdac_stream_writel(azx_dev, SD_BDLPU,
225                                upper_32_bits(azx_dev->bdl.addr));
226 
227         /* enable the position buffer */
228         if (bus->use_posbuf && bus->posbuf.addr) {
229                 if (!(snd_hdac_chip_readl(bus, DPLBASE) & AZX_DPLBASE_ENABLE))
230                         snd_hdac_chip_writel(bus, DPLBASE,
231                                 (u32)bus->posbuf.addr | AZX_DPLBASE_ENABLE);
232         }
233 
234         /* set the interrupt enable bits in the descriptor control register */
235         snd_hdac_stream_updatel(azx_dev, SD_CTL, 0, SD_INT_MASK);
236 
237         if (azx_dev->direction == SNDRV_PCM_STREAM_PLAYBACK)
238                 azx_dev->fifo_size =
239                         snd_hdac_stream_readw(azx_dev, SD_FIFOSIZE) + 1;
240         else
241                 azx_dev->fifo_size = 0;
242 
243         /* when LPIB delay correction gives a small negative value,
244          * we ignore it; currently set the threshold statically to
245          * 64 frames
246          */
247         if (runtime && runtime->period_size > 64)
248                 azx_dev->delay_negative_threshold =
249                         -frames_to_bytes(runtime, 64);
250         else
251                 azx_dev->delay_negative_threshold = 0;
252 
253         /* wallclk has 24Mhz clock source */
254         if (runtime)
255                 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
256                                     runtime->rate) * 1000);
257 
258         return 0;
259 }
260 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup);
261 
262 /**
263  * snd_hdac_stream_cleanup - cleanup a stream
264  * @azx_dev: HD-audio core stream to clean up
265  */
266 void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev)
267 {
268         snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
269         snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
270         snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
271         azx_dev->bufsize = 0;
272         azx_dev->period_bytes = 0;
273         azx_dev->format_val = 0;
274 }
275 EXPORT_SYMBOL_GPL(snd_hdac_stream_cleanup);
276 
277 /**
278  * snd_hdac_stream_assign - assign a stream for the PCM
279  * @bus: HD-audio core bus
280  * @substream: PCM substream to assign
281  *
282  * Look for an unused stream for the given PCM substream, assign it
283  * and return the stream object.  If no stream is free, returns NULL.
284  * The function tries to keep using the same stream object when it's used
285  * beforehand.  Also, when bus->reverse_assign flag is set, the last free
286  * or matching entry is returned.  This is needed for some strange codecs.
287  */
288 struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus,
289                                            struct snd_pcm_substream *substream)
290 {
291         struct hdac_stream *azx_dev;
292         struct hdac_stream *res = NULL;
293 
294         /* make a non-zero unique key for the substream */
295         int key = (substream->pcm->device << 16) | (substream->number << 2) |
296                 (substream->stream + 1);
297 
298         list_for_each_entry(azx_dev, &bus->stream_list, list) {
299                 if (azx_dev->direction != substream->stream)
300                         continue;
301                 if (azx_dev->opened)
302                         continue;
303                 if (azx_dev->assigned_key == key) {
304                         res = azx_dev;
305                         break;
306                 }
307                 if (!res || bus->reverse_assign)
308                         res = azx_dev;
309         }
310         if (res) {
311                 spin_lock_irq(&bus->reg_lock);
312                 res->opened = 1;
313                 res->running = 0;
314                 res->assigned_key = key;
315                 res->substream = substream;
316                 spin_unlock_irq(&bus->reg_lock);
317         }
318         return res;
319 }
320 EXPORT_SYMBOL_GPL(snd_hdac_stream_assign);
321 
322 /**
323  * snd_hdac_stream_release - release the assigned stream
324  * @azx_dev: HD-audio core stream to release
325  *
326  * Release the stream that has been assigned by snd_hdac_stream_assign().
327  */
328 void snd_hdac_stream_release(struct hdac_stream *azx_dev)
329 {
330         struct hdac_bus *bus = azx_dev->bus;
331 
332         spin_lock_irq(&bus->reg_lock);
333         azx_dev->opened = 0;
334         azx_dev->running = 0;
335         azx_dev->substream = NULL;
336         spin_unlock_irq(&bus->reg_lock);
337 }
338 EXPORT_SYMBOL_GPL(snd_hdac_stream_release);
339 
340 /**
341  * snd_hdac_get_stream - return hdac_stream based on stream_tag and
342  * direction
343  *
344  * @bus: HD-audio core bus
345  * @dir: direction for the stream to be found
346  * @stream_tag: stream tag for stream to be found
347  */
348 struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus,
349                                         int dir, int stream_tag)
350 {
351         struct hdac_stream *s;
352 
353         list_for_each_entry(s, &bus->stream_list, list) {
354                 if (s->direction == dir && s->stream_tag == stream_tag)
355                         return s;
356         }
357 
358         return NULL;
359 }
360 EXPORT_SYMBOL_GPL(snd_hdac_get_stream);
361 
362 /*
363  * set up a BDL entry
364  */
365 static int setup_bdle(struct hdac_bus *bus,
366                       struct snd_dma_buffer *dmab,
367                       struct hdac_stream *azx_dev, __le32 **bdlp,
368                       int ofs, int size, int with_ioc)
369 {
370         __le32 *bdl = *bdlp;
371 
372         while (size > 0) {
373                 dma_addr_t addr;
374                 int chunk;
375 
376                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
377                         return -EINVAL;
378 
379                 addr = snd_sgbuf_get_addr(dmab, ofs);
380                 /* program the address field of the BDL entry */
381                 bdl[0] = cpu_to_le32((u32)addr);
382                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
383                 /* program the size field of the BDL entry */
384                 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
385                 /* one BDLE cannot cross 4K boundary on CTHDA chips */
386                 if (bus->align_bdle_4k) {
387                         u32 remain = 0x1000 - (ofs & 0xfff);
388 
389                         if (chunk > remain)
390                                 chunk = remain;
391                 }
392                 bdl[2] = cpu_to_le32(chunk);
393                 /* program the IOC to enable interrupt
394                  * only when the whole fragment is processed
395                  */
396                 size -= chunk;
397                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
398                 bdl += 4;
399                 azx_dev->frags++;
400                 ofs += chunk;
401         }
402         *bdlp = bdl;
403         return ofs;
404 }
405 
406 /**
407  * snd_hdac_stream_setup_periods - set up BDL entries
408  * @azx_dev: HD-audio core stream to set up
409  *
410  * Set up the buffer descriptor table of the given stream based on the
411  * period and buffer sizes of the assigned PCM substream.
412  */
413 int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev)
414 {
415         struct hdac_bus *bus = azx_dev->bus;
416         struct snd_pcm_substream *substream = azx_dev->substream;
417         struct snd_pcm_runtime *runtime = substream->runtime;
418         __le32 *bdl;
419         int i, ofs, periods, period_bytes;
420         int pos_adj, pos_align;
421 
422         /* reset BDL address */
423         snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
424         snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
425 
426         period_bytes = azx_dev->period_bytes;
427         periods = azx_dev->bufsize / period_bytes;
428 
429         /* program the initial BDL entries */
430         bdl = (__le32 *)azx_dev->bdl.area;
431         ofs = 0;
432         azx_dev->frags = 0;
433 
434         pos_adj = bus->bdl_pos_adj;
435         if (!azx_dev->no_period_wakeup && pos_adj > 0) {
436                 pos_align = pos_adj;
437                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
438                 if (!pos_adj)
439                         pos_adj = pos_align;
440                 else
441                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
442                                 pos_align;
443                 pos_adj = frames_to_bytes(runtime, pos_adj);
444                 if (pos_adj >= period_bytes) {
445                         dev_warn(bus->dev, "Too big adjustment %d\n",
446                                  pos_adj);
447                         pos_adj = 0;
448                 } else {
449                         ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
450                                          azx_dev,
451                                          &bdl, ofs, pos_adj, true);
452                         if (ofs < 0)
453                                 goto error;
454                 }
455         } else
456                 pos_adj = 0;
457 
458         for (i = 0; i < periods; i++) {
459                 if (i == periods - 1 && pos_adj)
460                         ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
461                                          azx_dev, &bdl, ofs,
462                                          period_bytes - pos_adj, 0);
463                 else
464                         ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
465                                          azx_dev, &bdl, ofs,
466                                          period_bytes,
467                                          !azx_dev->no_period_wakeup);
468                 if (ofs < 0)
469                         goto error;
470         }
471         return 0;
472 
473  error:
474         dev_err(bus->dev, "Too many BDL entries: buffer=%d, period=%d\n",
475                 azx_dev->bufsize, period_bytes);
476         return -EINVAL;
477 }
478 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup_periods);
479 
480 /**
481  * snd_hdac_stream_set_params - set stream parameters
482  * @azx_dev: HD-audio core stream for which parameters are to be set
483  * @format_val: format value parameter
484  *
485  * Setup the HD-audio core stream parameters from substream of the stream
486  * and passed format value
487  */
488 int snd_hdac_stream_set_params(struct hdac_stream *azx_dev,
489                                  unsigned int format_val)
490 {
491 
492         unsigned int bufsize, period_bytes;
493         struct snd_pcm_substream *substream = azx_dev->substream;
494         struct snd_pcm_runtime *runtime;
495         int err;
496 
497         if (!substream)
498                 return -EINVAL;
499         runtime = substream->runtime;
500         bufsize = snd_pcm_lib_buffer_bytes(substream);
501         period_bytes = snd_pcm_lib_period_bytes(substream);
502 
503         if (bufsize != azx_dev->bufsize ||
504             period_bytes != azx_dev->period_bytes ||
505             format_val != azx_dev->format_val ||
506             runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
507                 azx_dev->bufsize = bufsize;
508                 azx_dev->period_bytes = period_bytes;
509                 azx_dev->format_val = format_val;
510                 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
511                 err = snd_hdac_stream_setup_periods(azx_dev);
512                 if (err < 0)
513                         return err;
514         }
515         return 0;
516 }
517 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_params);
518 
519 static u64 azx_cc_read(const struct cyclecounter *cc)
520 {
521         struct hdac_stream *azx_dev = container_of(cc, struct hdac_stream, cc);
522 
523         return snd_hdac_chip_readl(azx_dev->bus, WALLCLK);
524 }
525 
526 static void azx_timecounter_init(struct hdac_stream *azx_dev,
527                                  bool force, u64 last)
528 {
529         struct timecounter *tc = &azx_dev->tc;
530         struct cyclecounter *cc = &azx_dev->cc;
531         u64 nsec;
532 
533         cc->read = azx_cc_read;
534         cc->mask = CLOCKSOURCE_MASK(32);
535 
536         /*
537          * Converting from 24 MHz to ns means applying a 125/3 factor.
538          * To avoid any saturation issues in intermediate operations,
539          * the 125 factor is applied first. The division is applied
540          * last after reading the timecounter value.
541          * Applying the 1/3 factor as part of the multiplication
542          * requires at least 20 bits for a decent precision, however
543          * overflows occur after about 4 hours or less, not a option.
544          */
545 
546         cc->mult = 125; /* saturation after 195 years */
547         cc->shift = 0;
548 
549         nsec = 0; /* audio time is elapsed time since trigger */
550         timecounter_init(tc, cc, nsec);
551         if (force) {
552                 /*
553                  * force timecounter to use predefined value,
554                  * used for synchronized starts
555                  */
556                 tc->cycle_last = last;
557         }
558 }
559 
560 /**
561  * snd_hdac_stream_timecounter_init - initialize time counter
562  * @azx_dev: HD-audio core stream (master stream)
563  * @streams: bit flags of streams to set up
564  *
565  * Initializes the time counter of streams marked by the bit flags (each
566  * bit corresponds to the stream index).
567  * The trigger timestamp of PCM substream assigned to the given stream is
568  * updated accordingly, too.
569  */
570 void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev,
571                                       unsigned int streams)
572 {
573         struct hdac_bus *bus = azx_dev->bus;
574         struct snd_pcm_runtime *runtime = azx_dev->substream->runtime;
575         struct hdac_stream *s;
576         bool inited = false;
577         u64 cycle_last = 0;
578         int i = 0;
579 
580         list_for_each_entry(s, &bus->stream_list, list) {
581                 if (streams & (1 << i)) {
582                         azx_timecounter_init(s, inited, cycle_last);
583                         if (!inited) {
584                                 inited = true;
585                                 cycle_last = s->tc.cycle_last;
586                         }
587                 }
588                 i++;
589         }
590 
591         snd_pcm_gettime(runtime, &runtime->trigger_tstamp);
592         runtime->trigger_tstamp_latched = true;
593 }
594 EXPORT_SYMBOL_GPL(snd_hdac_stream_timecounter_init);
595 
596 /**
597  * snd_hdac_stream_sync_trigger - turn on/off stream sync register
598  * @azx_dev: HD-audio core stream (master stream)
599  * @streams: bit flags of streams to sync
600  */
601 void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set,
602                                   unsigned int streams, unsigned int reg)
603 {
604         struct hdac_bus *bus = azx_dev->bus;
605         unsigned int val;
606 
607         if (!reg)
608                 reg = AZX_REG_SSYNC;
609         val = _snd_hdac_chip_readl(bus, reg);
610         if (set)
611                 val |= streams;
612         else
613                 val &= ~streams;
614         _snd_hdac_chip_writel(bus, reg, val);
615 }
616 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync_trigger);
617 
618 /**
619  * snd_hdac_stream_sync - sync with start/strop trigger operation
620  * @azx_dev: HD-audio core stream (master stream)
621  * @start: true = start, false = stop
622  * @streams: bit flags of streams to sync
623  *
624  * For @start = true, wait until all FIFOs get ready.
625  * For @start = false, wait until all RUN bits are cleared.
626  */
627 void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start,
628                           unsigned int streams)
629 {
630         struct hdac_bus *bus = azx_dev->bus;
631         int i, nwait, timeout;
632         struct hdac_stream *s;
633 
634         for (timeout = 5000; timeout; timeout--) {
635                 nwait = 0;
636                 i = 0;
637                 list_for_each_entry(s, &bus->stream_list, list) {
638                         if (streams & (1 << i)) {
639                                 if (start) {
640                                         /* check FIFO gets ready */
641                                         if (!(snd_hdac_stream_readb(s, SD_STS) &
642                                               SD_STS_FIFO_READY))
643                                                 nwait++;
644                                 } else {
645                                         /* check RUN bit is cleared */
646                                         if (snd_hdac_stream_readb(s, SD_CTL) &
647                                             SD_CTL_DMA_START)
648                                                 nwait++;
649                                 }
650                         }
651                         i++;
652                 }
653                 if (!nwait)
654                         break;
655                 cpu_relax();
656         }
657 }
658 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync);
659 
660 #ifdef CONFIG_SND_HDA_DSP_LOADER
661 /**
662  * snd_hdac_dsp_prepare - prepare for DSP loading
663  * @azx_dev: HD-audio core stream used for DSP loading
664  * @format: HD-audio stream format
665  * @byte_size: data chunk byte size
666  * @bufp: allocated buffer
667  *
668  * Allocate the buffer for the given size and set up the given stream for
669  * DSP loading.  Returns the stream tag (>= 0), or a negative error code.
670  */
671 int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,
672                          unsigned int byte_size, struct snd_dma_buffer *bufp)
673 {
674         struct hdac_bus *bus = azx_dev->bus;
675         __le32 *bdl;
676         int err;
677 
678         snd_hdac_dsp_lock(azx_dev);
679         spin_lock_irq(&bus->reg_lock);
680         if (azx_dev->running || azx_dev->locked) {
681                 spin_unlock_irq(&bus->reg_lock);
682                 err = -EBUSY;
683                 goto unlock;
684         }
685         azx_dev->locked = true;
686         spin_unlock_irq(&bus->reg_lock);
687 
688         err = bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV_SG,
689                                            byte_size, bufp);
690         if (err < 0)
691                 goto err_alloc;
692 
693         azx_dev->substream = NULL;
694         azx_dev->bufsize = byte_size;
695         azx_dev->period_bytes = byte_size;
696         azx_dev->format_val = format;
697 
698         snd_hdac_stream_reset(azx_dev);
699 
700         /* reset BDL address */
701         snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
702         snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
703 
704         azx_dev->frags = 0;
705         bdl = (__le32 *)azx_dev->bdl.area;
706         err = setup_bdle(bus, bufp, azx_dev, &bdl, 0, byte_size, 0);
707         if (err < 0)
708                 goto error;
709 
710         snd_hdac_stream_setup(azx_dev);
711         snd_hdac_dsp_unlock(azx_dev);
712         return azx_dev->stream_tag;
713 
714  error:
715         bus->io_ops->dma_free_pages(bus, bufp);
716  err_alloc:
717         spin_lock_irq(&bus->reg_lock);
718         azx_dev->locked = false;
719         spin_unlock_irq(&bus->reg_lock);
720  unlock:
721         snd_hdac_dsp_unlock(azx_dev);
722         return err;
723 }
724 EXPORT_SYMBOL_GPL(snd_hdac_dsp_prepare);
725 
726 /**
727  * snd_hdac_dsp_trigger - start / stop DSP loading
728  * @azx_dev: HD-audio core stream used for DSP loading
729  * @start: trigger start or stop
730  */
731 void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start)
732 {
733         if (start)
734                 snd_hdac_stream_start(azx_dev, true);
735         else
736                 snd_hdac_stream_stop(azx_dev);
737 }
738 EXPORT_SYMBOL_GPL(snd_hdac_dsp_trigger);
739 
740 /**
741  * snd_hdac_dsp_cleanup - clean up the stream from DSP loading to normal
742  * @azx_dev: HD-audio core stream used for DSP loading
743  * @dmab: buffer used by DSP loading
744  */
745 void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,
746                           struct snd_dma_buffer *dmab)
747 {
748         struct hdac_bus *bus = azx_dev->bus;
749 
750         if (!dmab->area || !azx_dev->locked)
751                 return;
752 
753         snd_hdac_dsp_lock(azx_dev);
754         /* reset BDL address */
755         snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
756         snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
757         snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
758         azx_dev->bufsize = 0;
759         azx_dev->period_bytes = 0;
760         azx_dev->format_val = 0;
761 
762         bus->io_ops->dma_free_pages(bus, dmab);
763         dmab->area = NULL;
764 
765         spin_lock_irq(&bus->reg_lock);
766         azx_dev->locked = false;
767         spin_unlock_irq(&bus->reg_lock);
768         snd_hdac_dsp_unlock(azx_dev);
769 }
770 EXPORT_SYMBOL_GPL(snd_hdac_dsp_cleanup);
771 #endif /* CONFIG_SND_HDA_DSP_LOADER */
772 

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