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TOMOYO Linux Cross Reference
Linux/sound/mips/hal2.c

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Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  *  Driver for A2 audio system used in SGI machines
  3  *  Copyright (c) 2008 Thomas Bogendoerfer <tsbogend@alpha.fanken.de>
  4  *
  5  *  Based on OSS code from Ladislav Michl <ladis@linux-mips.org>, which
  6  *  was based on code from Ulf Carlsson
  7  *
  8  *  This program is free software; you can redistribute it and/or modify
  9  *  it under the terms of the GNU General Public License version 2 as
 10  *  published by the Free Software Foundation.
 11  *
 12  *  This program is distributed in the hope that it will be useful,
 13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 15  *  GNU General Public License for more details.
 16  *
 17  *  You should have received a copy of the GNU General Public License
 18  *  along with this program; if not, write to the Free Software
 19  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 20  *
 21  */
 22 #include <linux/kernel.h>
 23 #include <linux/init.h>
 24 #include <linux/interrupt.h>
 25 #include <linux/dma-mapping.h>
 26 #include <linux/platform_device.h>
 27 #include <linux/io.h>
 28 #include <linux/slab.h>
 29 #include <linux/module.h>
 30 
 31 #include <asm/sgi/hpc3.h>
 32 #include <asm/sgi/ip22.h>
 33 
 34 #include <sound/core.h>
 35 #include <sound/control.h>
 36 #include <sound/pcm.h>
 37 #include <sound/pcm-indirect.h>
 38 #include <sound/initval.h>
 39 
 40 #include "hal2.h"
 41 
 42 static int index = SNDRV_DEFAULT_IDX1;  /* Index 0-MAX */
 43 static char *id = SNDRV_DEFAULT_STR1;   /* ID for this card */
 44 
 45 module_param(index, int, 0444);
 46 MODULE_PARM_DESC(index, "Index value for SGI HAL2 soundcard.");
 47 module_param(id, charp, 0444);
 48 MODULE_PARM_DESC(id, "ID string for SGI HAL2 soundcard.");
 49 MODULE_DESCRIPTION("ALSA driver for SGI HAL2 audio");
 50 MODULE_AUTHOR("Thomas Bogendoerfer");
 51 MODULE_LICENSE("GPL");
 52 
 53 
 54 #define H2_BLOCK_SIZE   1024
 55 #define H2_BUF_SIZE     16384
 56 
 57 struct hal2_pbus {
 58         struct hpc3_pbus_dmacregs *pbus;
 59         int pbusnr;
 60         unsigned int ctrl;              /* Current state of pbus->pbdma_ctrl */
 61 };
 62 
 63 struct hal2_desc {
 64         struct hpc_dma_desc desc;
 65         u32 pad;                        /* padding */
 66 };
 67 
 68 struct hal2_codec {
 69         struct snd_pcm_indirect pcm_indirect;
 70         struct snd_pcm_substream *substream;
 71 
 72         unsigned char *buffer;
 73         dma_addr_t buffer_dma;
 74         struct hal2_desc *desc;
 75         dma_addr_t desc_dma;
 76         int desc_count;
 77         struct hal2_pbus pbus;
 78         int voices;                     /* mono/stereo */
 79         unsigned int sample_rate;
 80         unsigned int master;            /* Master frequency */
 81         unsigned short mod;             /* MOD value */
 82         unsigned short inc;             /* INC value */
 83 };
 84 
 85 #define H2_MIX_OUTPUT_ATT       0
 86 #define H2_MIX_INPUT_GAIN       1
 87 
 88 struct snd_hal2 {
 89         struct snd_card *card;
 90 
 91         struct hal2_ctl_regs *ctl_regs; /* HAL2 ctl registers */
 92         struct hal2_aes_regs *aes_regs; /* HAL2 aes registers */
 93         struct hal2_vol_regs *vol_regs; /* HAL2 vol registers */
 94         struct hal2_syn_regs *syn_regs; /* HAL2 syn registers */
 95 
 96         struct hal2_codec dac;
 97         struct hal2_codec adc;
 98 };
 99 
100 #define H2_INDIRECT_WAIT(regs)  while (hal2_read(&regs->isr) & H2_ISR_TSTATUS);
101 
102 #define H2_READ_ADDR(addr)      (addr | (1<<7))
103 #define H2_WRITE_ADDR(addr)     (addr)
104 
105 static inline u32 hal2_read(u32 *reg)
106 {
107         return __raw_readl(reg);
108 }
109 
110 static inline void hal2_write(u32 val, u32 *reg)
111 {
112         __raw_writel(val, reg);
113 }
114 
115 
116 static u32 hal2_i_read32(struct snd_hal2 *hal2, u16 addr)
117 {
118         u32 ret;
119         struct hal2_ctl_regs *regs = hal2->ctl_regs;
120 
121         hal2_write(H2_READ_ADDR(addr), &regs->iar);
122         H2_INDIRECT_WAIT(regs);
123         ret = hal2_read(&regs->idr0) & 0xffff;
124         hal2_write(H2_READ_ADDR(addr) | 0x1, &regs->iar);
125         H2_INDIRECT_WAIT(regs);
126         ret |= (hal2_read(&regs->idr0) & 0xffff) << 16;
127         return ret;
128 }
129 
130 static void hal2_i_write16(struct snd_hal2 *hal2, u16 addr, u16 val)
131 {
132         struct hal2_ctl_regs *regs = hal2->ctl_regs;
133 
134         hal2_write(val, &regs->idr0);
135         hal2_write(0, &regs->idr1);
136         hal2_write(0, &regs->idr2);
137         hal2_write(0, &regs->idr3);
138         hal2_write(H2_WRITE_ADDR(addr), &regs->iar);
139         H2_INDIRECT_WAIT(regs);
140 }
141 
142 static void hal2_i_write32(struct snd_hal2 *hal2, u16 addr, u32 val)
143 {
144         struct hal2_ctl_regs *regs = hal2->ctl_regs;
145 
146         hal2_write(val & 0xffff, &regs->idr0);
147         hal2_write(val >> 16, &regs->idr1);
148         hal2_write(0, &regs->idr2);
149         hal2_write(0, &regs->idr3);
150         hal2_write(H2_WRITE_ADDR(addr), &regs->iar);
151         H2_INDIRECT_WAIT(regs);
152 }
153 
154 static void hal2_i_setbit16(struct snd_hal2 *hal2, u16 addr, u16 bit)
155 {
156         struct hal2_ctl_regs *regs = hal2->ctl_regs;
157 
158         hal2_write(H2_READ_ADDR(addr), &regs->iar);
159         H2_INDIRECT_WAIT(regs);
160         hal2_write((hal2_read(&regs->idr0) & 0xffff) | bit, &regs->idr0);
161         hal2_write(0, &regs->idr1);
162         hal2_write(0, &regs->idr2);
163         hal2_write(0, &regs->idr3);
164         hal2_write(H2_WRITE_ADDR(addr), &regs->iar);
165         H2_INDIRECT_WAIT(regs);
166 }
167 
168 static void hal2_i_clearbit16(struct snd_hal2 *hal2, u16 addr, u16 bit)
169 {
170         struct hal2_ctl_regs *regs = hal2->ctl_regs;
171 
172         hal2_write(H2_READ_ADDR(addr), &regs->iar);
173         H2_INDIRECT_WAIT(regs);
174         hal2_write((hal2_read(&regs->idr0) & 0xffff) & ~bit, &regs->idr0);
175         hal2_write(0, &regs->idr1);
176         hal2_write(0, &regs->idr2);
177         hal2_write(0, &regs->idr3);
178         hal2_write(H2_WRITE_ADDR(addr), &regs->iar);
179         H2_INDIRECT_WAIT(regs);
180 }
181 
182 static int hal2_gain_info(struct snd_kcontrol *kcontrol,
183                                struct snd_ctl_elem_info *uinfo)
184 {
185         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
186         uinfo->count = 2;
187         uinfo->value.integer.min = 0;
188         switch ((int)kcontrol->private_value) {
189         case H2_MIX_OUTPUT_ATT:
190                 uinfo->value.integer.max = 31;
191                 break;
192         case H2_MIX_INPUT_GAIN:
193                 uinfo->value.integer.max = 15;
194                 break;
195         }
196         return 0;
197 }
198 
199 static int hal2_gain_get(struct snd_kcontrol *kcontrol,
200                                struct snd_ctl_elem_value *ucontrol)
201 {
202         struct snd_hal2 *hal2 = snd_kcontrol_chip(kcontrol);
203         u32 tmp;
204         int l, r;
205 
206         switch ((int)kcontrol->private_value) {
207         case H2_MIX_OUTPUT_ATT:
208                 tmp = hal2_i_read32(hal2, H2I_DAC_C2);
209                 if (tmp & H2I_C2_MUTE) {
210                         l = 0;
211                         r = 0;
212                 } else {
213                         l = 31 - ((tmp >> H2I_C2_L_ATT_SHIFT) & 31);
214                         r = 31 - ((tmp >> H2I_C2_R_ATT_SHIFT) & 31);
215                 }
216                 break;
217         case H2_MIX_INPUT_GAIN:
218                 tmp = hal2_i_read32(hal2, H2I_ADC_C2);
219                 l = (tmp >> H2I_C2_L_GAIN_SHIFT) & 15;
220                 r = (tmp >> H2I_C2_R_GAIN_SHIFT) & 15;
221                 break;
222         default:
223                 return -EINVAL;
224         }
225         ucontrol->value.integer.value[0] = l;
226         ucontrol->value.integer.value[1] = r;
227 
228         return 0;
229 }
230 
231 static int hal2_gain_put(struct snd_kcontrol *kcontrol,
232                          struct snd_ctl_elem_value *ucontrol)
233 {
234         struct snd_hal2 *hal2 = snd_kcontrol_chip(kcontrol);
235         u32 old, new;
236         int l, r;
237 
238         l = ucontrol->value.integer.value[0];
239         r = ucontrol->value.integer.value[1];
240 
241         switch ((int)kcontrol->private_value) {
242         case H2_MIX_OUTPUT_ATT:
243                 old = hal2_i_read32(hal2, H2I_DAC_C2);
244                 new = old & ~(H2I_C2_L_ATT_M | H2I_C2_R_ATT_M | H2I_C2_MUTE);
245                 if (l | r) {
246                         l = 31 - l;
247                         r = 31 - r;
248                         new |= (l << H2I_C2_L_ATT_SHIFT);
249                         new |= (r << H2I_C2_R_ATT_SHIFT);
250                 } else
251                         new |= H2I_C2_L_ATT_M | H2I_C2_R_ATT_M | H2I_C2_MUTE;
252                 hal2_i_write32(hal2, H2I_DAC_C2, new);
253                 break;
254         case H2_MIX_INPUT_GAIN:
255                 old = hal2_i_read32(hal2, H2I_ADC_C2);
256                 new = old & ~(H2I_C2_L_GAIN_M | H2I_C2_R_GAIN_M);
257                 new |= (l << H2I_C2_L_GAIN_SHIFT);
258                 new |= (r << H2I_C2_R_GAIN_SHIFT);
259                 hal2_i_write32(hal2, H2I_ADC_C2, new);
260                 break;
261         default:
262                 return -EINVAL;
263         }
264         return old != new;
265 }
266 
267 static const struct snd_kcontrol_new hal2_ctrl_headphone = {
268         .iface          = SNDRV_CTL_ELEM_IFACE_MIXER,
269         .name           = "Headphone Playback Volume",
270         .access         = SNDRV_CTL_ELEM_ACCESS_READWRITE,
271         .private_value  = H2_MIX_OUTPUT_ATT,
272         .info           = hal2_gain_info,
273         .get            = hal2_gain_get,
274         .put            = hal2_gain_put,
275 };
276 
277 static const struct snd_kcontrol_new hal2_ctrl_mic = {
278         .iface          = SNDRV_CTL_ELEM_IFACE_MIXER,
279         .name           = "Mic Capture Volume",
280         .access         = SNDRV_CTL_ELEM_ACCESS_READWRITE,
281         .private_value  = H2_MIX_INPUT_GAIN,
282         .info           = hal2_gain_info,
283         .get            = hal2_gain_get,
284         .put            = hal2_gain_put,
285 };
286 
287 static int hal2_mixer_create(struct snd_hal2 *hal2)
288 {
289         int err;
290 
291         /* mute DAC */
292         hal2_i_write32(hal2, H2I_DAC_C2,
293                        H2I_C2_L_ATT_M | H2I_C2_R_ATT_M | H2I_C2_MUTE);
294         /* mute ADC */
295         hal2_i_write32(hal2, H2I_ADC_C2, 0);
296 
297         err = snd_ctl_add(hal2->card,
298                           snd_ctl_new1(&hal2_ctrl_headphone, hal2));
299         if (err < 0)
300                 return err;
301 
302         err = snd_ctl_add(hal2->card,
303                           snd_ctl_new1(&hal2_ctrl_mic, hal2));
304         if (err < 0)
305                 return err;
306 
307         return 0;
308 }
309 
310 static irqreturn_t hal2_interrupt(int irq, void *dev_id)
311 {
312         struct snd_hal2 *hal2 = dev_id;
313         irqreturn_t ret = IRQ_NONE;
314 
315         /* decide what caused this interrupt */
316         if (hal2->dac.pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_INT) {
317                 snd_pcm_period_elapsed(hal2->dac.substream);
318                 ret = IRQ_HANDLED;
319         }
320         if (hal2->adc.pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_INT) {
321                 snd_pcm_period_elapsed(hal2->adc.substream);
322                 ret = IRQ_HANDLED;
323         }
324         return ret;
325 }
326 
327 static int hal2_compute_rate(struct hal2_codec *codec, unsigned int rate)
328 {
329         unsigned short mod;
330 
331         if (44100 % rate < 48000 % rate) {
332                 mod = 4 * 44100 / rate;
333                 codec->master = 44100;
334         } else {
335                 mod = 4 * 48000 / rate;
336                 codec->master = 48000;
337         }
338 
339         codec->inc = 4;
340         codec->mod = mod;
341         rate = 4 * codec->master / mod;
342 
343         return rate;
344 }
345 
346 static void hal2_set_dac_rate(struct snd_hal2 *hal2)
347 {
348         unsigned int master = hal2->dac.master;
349         int inc = hal2->dac.inc;
350         int mod = hal2->dac.mod;
351 
352         hal2_i_write16(hal2, H2I_BRES1_C1, (master == 44100) ? 1 : 0);
353         hal2_i_write32(hal2, H2I_BRES1_C2,
354                        ((0xffff & (inc - mod - 1)) << 16) | inc);
355 }
356 
357 static void hal2_set_adc_rate(struct snd_hal2 *hal2)
358 {
359         unsigned int master = hal2->adc.master;
360         int inc = hal2->adc.inc;
361         int mod = hal2->adc.mod;
362 
363         hal2_i_write16(hal2, H2I_BRES2_C1, (master == 44100) ? 1 : 0);
364         hal2_i_write32(hal2, H2I_BRES2_C2,
365                        ((0xffff & (inc - mod - 1)) << 16) | inc);
366 }
367 
368 static void hal2_setup_dac(struct snd_hal2 *hal2)
369 {
370         unsigned int fifobeg, fifoend, highwater, sample_size;
371         struct hal2_pbus *pbus = &hal2->dac.pbus;
372 
373         /* Now we set up some PBUS information. The PBUS needs information about
374          * what portion of the fifo it will use. If it's receiving or
375          * transmitting, and finally whether the stream is little endian or big
376          * endian. The information is written later, on the start call.
377          */
378         sample_size = 2 * hal2->dac.voices;
379         /* Fifo should be set to hold exactly four samples. Highwater mark
380          * should be set to two samples. */
381         highwater = (sample_size * 2) >> 1;     /* halfwords */
382         fifobeg = 0;                            /* playback is first */
383         fifoend = (sample_size * 4) >> 3;       /* doublewords */
384         pbus->ctrl = HPC3_PDMACTRL_RT | HPC3_PDMACTRL_LD |
385                      (highwater << 8) | (fifobeg << 16) | (fifoend << 24);
386         /* We disable everything before we do anything at all */
387         pbus->pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
388         hal2_i_clearbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECTX);
389         /* Setup the HAL2 for playback */
390         hal2_set_dac_rate(hal2);
391         /* Set endianess */
392         hal2_i_clearbit16(hal2, H2I_DMA_END, H2I_DMA_END_CODECTX);
393         /* Set DMA bus */
394         hal2_i_setbit16(hal2, H2I_DMA_DRV, (1 << pbus->pbusnr));
395         /* We are using 1st Bresenham clock generator for playback */
396         hal2_i_write16(hal2, H2I_DAC_C1, (pbus->pbusnr << H2I_C1_DMA_SHIFT)
397                         | (1 << H2I_C1_CLKID_SHIFT)
398                         | (hal2->dac.voices << H2I_C1_DATAT_SHIFT));
399 }
400 
401 static void hal2_setup_adc(struct snd_hal2 *hal2)
402 {
403         unsigned int fifobeg, fifoend, highwater, sample_size;
404         struct hal2_pbus *pbus = &hal2->adc.pbus;
405 
406         sample_size = 2 * hal2->adc.voices;
407         highwater = (sample_size * 2) >> 1;             /* halfwords */
408         fifobeg = (4 * 4) >> 3;                         /* record is second */
409         fifoend = (4 * 4 + sample_size * 4) >> 3;       /* doublewords */
410         pbus->ctrl = HPC3_PDMACTRL_RT | HPC3_PDMACTRL_RCV | HPC3_PDMACTRL_LD |
411                      (highwater << 8) | (fifobeg << 16) | (fifoend << 24);
412         pbus->pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
413         hal2_i_clearbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECR);
414         /* Setup the HAL2 for record */
415         hal2_set_adc_rate(hal2);
416         /* Set endianess */
417         hal2_i_clearbit16(hal2, H2I_DMA_END, H2I_DMA_END_CODECR);
418         /* Set DMA bus */
419         hal2_i_setbit16(hal2, H2I_DMA_DRV, (1 << pbus->pbusnr));
420         /* We are using 2nd Bresenham clock generator for record */
421         hal2_i_write16(hal2, H2I_ADC_C1, (pbus->pbusnr << H2I_C1_DMA_SHIFT)
422                         | (2 << H2I_C1_CLKID_SHIFT)
423                         | (hal2->adc.voices << H2I_C1_DATAT_SHIFT));
424 }
425 
426 static void hal2_start_dac(struct snd_hal2 *hal2)
427 {
428         struct hal2_pbus *pbus = &hal2->dac.pbus;
429 
430         pbus->pbus->pbdma_dptr = hal2->dac.desc_dma;
431         pbus->pbus->pbdma_ctrl = pbus->ctrl | HPC3_PDMACTRL_ACT;
432         /* enable DAC */
433         hal2_i_setbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECTX);
434 }
435 
436 static void hal2_start_adc(struct snd_hal2 *hal2)
437 {
438         struct hal2_pbus *pbus = &hal2->adc.pbus;
439 
440         pbus->pbus->pbdma_dptr = hal2->adc.desc_dma;
441         pbus->pbus->pbdma_ctrl = pbus->ctrl | HPC3_PDMACTRL_ACT;
442         /* enable ADC */
443         hal2_i_setbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECR);
444 }
445 
446 static inline void hal2_stop_dac(struct snd_hal2 *hal2)
447 {
448         hal2->dac.pbus.pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
449         /* The HAL2 itself may remain enabled safely */
450 }
451 
452 static inline void hal2_stop_adc(struct snd_hal2 *hal2)
453 {
454         hal2->adc.pbus.pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
455 }
456 
457 static int hal2_alloc_dmabuf(struct hal2_codec *codec)
458 {
459         struct hal2_desc *desc;
460         dma_addr_t desc_dma, buffer_dma;
461         int count = H2_BUF_SIZE / H2_BLOCK_SIZE;
462         int i;
463 
464         codec->buffer = dma_alloc_attrs(NULL, H2_BUF_SIZE, &buffer_dma,
465                                         GFP_KERNEL, DMA_ATTR_NON_CONSISTENT);
466         if (!codec->buffer)
467                 return -ENOMEM;
468         desc = dma_alloc_attrs(NULL, count * sizeof(struct hal2_desc),
469                                &desc_dma, GFP_KERNEL, DMA_ATTR_NON_CONSISTENT);
470         if (!desc) {
471                 dma_free_attrs(NULL, H2_BUF_SIZE, codec->buffer, buffer_dma,
472                                DMA_ATTR_NON_CONSISTENT);
473                 return -ENOMEM;
474         }
475         codec->buffer_dma = buffer_dma;
476         codec->desc_dma = desc_dma;
477         codec->desc = desc;
478         for (i = 0; i < count; i++) {
479                 desc->desc.pbuf = buffer_dma + i * H2_BLOCK_SIZE;
480                 desc->desc.cntinfo = HPCDMA_XIE | H2_BLOCK_SIZE;
481                 desc->desc.pnext = (i == count - 1) ?
482                       desc_dma : desc_dma + (i + 1) * sizeof(struct hal2_desc);
483                 desc++;
484         }
485         dma_cache_sync(NULL, codec->desc, count * sizeof(struct hal2_desc),
486                        DMA_TO_DEVICE);
487         codec->desc_count = count;
488         return 0;
489 }
490 
491 static void hal2_free_dmabuf(struct hal2_codec *codec)
492 {
493         dma_free_attrs(NULL, codec->desc_count * sizeof(struct hal2_desc),
494                        codec->desc, codec->desc_dma, DMA_ATTR_NON_CONSISTENT);
495         dma_free_attrs(NULL, H2_BUF_SIZE, codec->buffer, codec->buffer_dma,
496                        DMA_ATTR_NON_CONSISTENT);
497 }
498 
499 static const struct snd_pcm_hardware hal2_pcm_hw = {
500         .info = (SNDRV_PCM_INFO_MMAP |
501                  SNDRV_PCM_INFO_MMAP_VALID |
502                  SNDRV_PCM_INFO_INTERLEAVED |
503                  SNDRV_PCM_INFO_BLOCK_TRANSFER),
504         .formats =          SNDRV_PCM_FMTBIT_S16_BE,
505         .rates =            SNDRV_PCM_RATE_8000_48000,
506         .rate_min =         8000,
507         .rate_max =         48000,
508         .channels_min =     2,
509         .channels_max =     2,
510         .buffer_bytes_max = 65536,
511         .period_bytes_min = 1024,
512         .period_bytes_max = 65536,
513         .periods_min =      2,
514         .periods_max =      1024,
515 };
516 
517 static int hal2_pcm_hw_params(struct snd_pcm_substream *substream,
518                               struct snd_pcm_hw_params *params)
519 {
520         int err;
521 
522         err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
523         if (err < 0)
524                 return err;
525 
526         return 0;
527 }
528 
529 static int hal2_pcm_hw_free(struct snd_pcm_substream *substream)
530 {
531         return snd_pcm_lib_free_pages(substream);
532 }
533 
534 static int hal2_playback_open(struct snd_pcm_substream *substream)
535 {
536         struct snd_pcm_runtime *runtime = substream->runtime;
537         struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
538         int err;
539 
540         runtime->hw = hal2_pcm_hw;
541 
542         err = hal2_alloc_dmabuf(&hal2->dac);
543         if (err)
544                 return err;
545         return 0;
546 }
547 
548 static int hal2_playback_close(struct snd_pcm_substream *substream)
549 {
550         struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
551 
552         hal2_free_dmabuf(&hal2->dac);
553         return 0;
554 }
555 
556 static int hal2_playback_prepare(struct snd_pcm_substream *substream)
557 {
558         struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
559         struct snd_pcm_runtime *runtime = substream->runtime;
560         struct hal2_codec *dac = &hal2->dac;
561 
562         dac->voices = runtime->channels;
563         dac->sample_rate = hal2_compute_rate(dac, runtime->rate);
564         memset(&dac->pcm_indirect, 0, sizeof(dac->pcm_indirect));
565         dac->pcm_indirect.hw_buffer_size = H2_BUF_SIZE;
566         dac->pcm_indirect.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
567         dac->substream = substream;
568         hal2_setup_dac(hal2);
569         return 0;
570 }
571 
572 static int hal2_playback_trigger(struct snd_pcm_substream *substream, int cmd)
573 {
574         struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
575 
576         switch (cmd) {
577         case SNDRV_PCM_TRIGGER_START:
578                 hal2->dac.pcm_indirect.hw_io = hal2->dac.buffer_dma;
579                 hal2->dac.pcm_indirect.hw_data = 0;
580                 substream->ops->ack(substream);
581                 hal2_start_dac(hal2);
582                 break;
583         case SNDRV_PCM_TRIGGER_STOP:
584                 hal2_stop_dac(hal2);
585                 break;
586         default:
587                 return -EINVAL;
588         }
589         return 0;
590 }
591 
592 static snd_pcm_uframes_t
593 hal2_playback_pointer(struct snd_pcm_substream *substream)
594 {
595         struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
596         struct hal2_codec *dac = &hal2->dac;
597 
598         return snd_pcm_indirect_playback_pointer(substream, &dac->pcm_indirect,
599                                                  dac->pbus.pbus->pbdma_bptr);
600 }
601 
602 static void hal2_playback_transfer(struct snd_pcm_substream *substream,
603                                    struct snd_pcm_indirect *rec, size_t bytes)
604 {
605         struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
606         unsigned char *buf = hal2->dac.buffer + rec->hw_data;
607 
608         memcpy(buf, substream->runtime->dma_area + rec->sw_data, bytes);
609         dma_cache_sync(NULL, buf, bytes, DMA_TO_DEVICE);
610 
611 }
612 
613 static int hal2_playback_ack(struct snd_pcm_substream *substream)
614 {
615         struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
616         struct hal2_codec *dac = &hal2->dac;
617 
618         dac->pcm_indirect.hw_queue_size = H2_BUF_SIZE / 2;
619         return snd_pcm_indirect_playback_transfer(substream,
620                                                   &dac->pcm_indirect,
621                                                   hal2_playback_transfer);
622 }
623 
624 static int hal2_capture_open(struct snd_pcm_substream *substream)
625 {
626         struct snd_pcm_runtime *runtime = substream->runtime;
627         struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
628         struct hal2_codec *adc = &hal2->adc;
629         int err;
630 
631         runtime->hw = hal2_pcm_hw;
632 
633         err = hal2_alloc_dmabuf(adc);
634         if (err)
635                 return err;
636         return 0;
637 }
638 
639 static int hal2_capture_close(struct snd_pcm_substream *substream)
640 {
641         struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
642 
643         hal2_free_dmabuf(&hal2->adc);
644         return 0;
645 }
646 
647 static int hal2_capture_prepare(struct snd_pcm_substream *substream)
648 {
649         struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
650         struct snd_pcm_runtime *runtime = substream->runtime;
651         struct hal2_codec *adc = &hal2->adc;
652 
653         adc->voices = runtime->channels;
654         adc->sample_rate = hal2_compute_rate(adc, runtime->rate);
655         memset(&adc->pcm_indirect, 0, sizeof(adc->pcm_indirect));
656         adc->pcm_indirect.hw_buffer_size = H2_BUF_SIZE;
657         adc->pcm_indirect.hw_queue_size = H2_BUF_SIZE / 2;
658         adc->pcm_indirect.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
659         adc->substream = substream;
660         hal2_setup_adc(hal2);
661         return 0;
662 }
663 
664 static int hal2_capture_trigger(struct snd_pcm_substream *substream, int cmd)
665 {
666         struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
667 
668         switch (cmd) {
669         case SNDRV_PCM_TRIGGER_START:
670                 hal2->adc.pcm_indirect.hw_io = hal2->adc.buffer_dma;
671                 hal2->adc.pcm_indirect.hw_data = 0;
672                 printk(KERN_DEBUG "buffer_dma %x\n", hal2->adc.buffer_dma);
673                 hal2_start_adc(hal2);
674                 break;
675         case SNDRV_PCM_TRIGGER_STOP:
676                 hal2_stop_adc(hal2);
677                 break;
678         default:
679                 return -EINVAL;
680         }
681         return 0;
682 }
683 
684 static snd_pcm_uframes_t
685 hal2_capture_pointer(struct snd_pcm_substream *substream)
686 {
687         struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
688         struct hal2_codec *adc = &hal2->adc;
689 
690         return snd_pcm_indirect_capture_pointer(substream, &adc->pcm_indirect,
691                                                 adc->pbus.pbus->pbdma_bptr);
692 }
693 
694 static void hal2_capture_transfer(struct snd_pcm_substream *substream,
695                                   struct snd_pcm_indirect *rec, size_t bytes)
696 {
697         struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
698         unsigned char *buf = hal2->adc.buffer + rec->hw_data;
699 
700         dma_cache_sync(NULL, buf, bytes, DMA_FROM_DEVICE);
701         memcpy(substream->runtime->dma_area + rec->sw_data, buf, bytes);
702 }
703 
704 static int hal2_capture_ack(struct snd_pcm_substream *substream)
705 {
706         struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
707         struct hal2_codec *adc = &hal2->adc;
708 
709         return snd_pcm_indirect_capture_transfer(substream,
710                                                  &adc->pcm_indirect,
711                                                  hal2_capture_transfer);
712 }
713 
714 static const struct snd_pcm_ops hal2_playback_ops = {
715         .open =        hal2_playback_open,
716         .close =       hal2_playback_close,
717         .ioctl =       snd_pcm_lib_ioctl,
718         .hw_params =   hal2_pcm_hw_params,
719         .hw_free =     hal2_pcm_hw_free,
720         .prepare =     hal2_playback_prepare,
721         .trigger =     hal2_playback_trigger,
722         .pointer =     hal2_playback_pointer,
723         .ack =         hal2_playback_ack,
724 };
725 
726 static const struct snd_pcm_ops hal2_capture_ops = {
727         .open =        hal2_capture_open,
728         .close =       hal2_capture_close,
729         .ioctl =       snd_pcm_lib_ioctl,
730         .hw_params =   hal2_pcm_hw_params,
731         .hw_free =     hal2_pcm_hw_free,
732         .prepare =     hal2_capture_prepare,
733         .trigger =     hal2_capture_trigger,
734         .pointer =     hal2_capture_pointer,
735         .ack =         hal2_capture_ack,
736 };
737 
738 static int hal2_pcm_create(struct snd_hal2 *hal2)
739 {
740         struct snd_pcm *pcm;
741         int err;
742 
743         /* create first pcm device with one outputs and one input */
744         err = snd_pcm_new(hal2->card, "SGI HAL2 Audio", 0, 1, 1, &pcm);
745         if (err < 0)
746                 return err;
747 
748         pcm->private_data = hal2;
749         strcpy(pcm->name, "SGI HAL2");
750 
751         /* set operators */
752         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
753                         &hal2_playback_ops);
754         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
755                         &hal2_capture_ops);
756         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS,
757                                            snd_dma_continuous_data(GFP_KERNEL),
758                                            0, 1024 * 1024);
759 
760         return 0;
761 }
762 
763 static int hal2_dev_free(struct snd_device *device)
764 {
765         struct snd_hal2 *hal2 = device->device_data;
766 
767         free_irq(SGI_HPCDMA_IRQ, hal2);
768         kfree(hal2);
769         return 0;
770 }
771 
772 static struct snd_device_ops hal2_ops = {
773         .dev_free = hal2_dev_free,
774 };
775 
776 static void hal2_init_codec(struct hal2_codec *codec, struct hpc3_regs *hpc3,
777                             int index)
778 {
779         codec->pbus.pbusnr = index;
780         codec->pbus.pbus = &hpc3->pbdma[index];
781 }
782 
783 static int hal2_detect(struct snd_hal2 *hal2)
784 {
785         unsigned short board, major, minor;
786         unsigned short rev;
787 
788         /* reset HAL2 */
789         hal2_write(0, &hal2->ctl_regs->isr);
790 
791         /* release reset */
792         hal2_write(H2_ISR_GLOBAL_RESET_N | H2_ISR_CODEC_RESET_N,
793                    &hal2->ctl_regs->isr);
794 
795 
796         hal2_i_write16(hal2, H2I_RELAY_C, H2I_RELAY_C_STATE);
797         rev = hal2_read(&hal2->ctl_regs->rev);
798         if (rev & H2_REV_AUDIO_PRESENT)
799                 return -ENODEV;
800 
801         board = (rev & H2_REV_BOARD_M) >> 12;
802         major = (rev & H2_REV_MAJOR_CHIP_M) >> 4;
803         minor = (rev & H2_REV_MINOR_CHIP_M);
804 
805         printk(KERN_INFO "SGI HAL2 revision %i.%i.%i\n",
806                board, major, minor);
807 
808         return 0;
809 }
810 
811 static int hal2_create(struct snd_card *card, struct snd_hal2 **rchip)
812 {
813         struct snd_hal2 *hal2;
814         struct hpc3_regs *hpc3 = hpc3c0;
815         int err;
816 
817         hal2 = kzalloc(sizeof(*hal2), GFP_KERNEL);
818         if (!hal2)
819                 return -ENOMEM;
820 
821         hal2->card = card;
822 
823         if (request_irq(SGI_HPCDMA_IRQ, hal2_interrupt, IRQF_SHARED,
824                         "SGI HAL2", hal2)) {
825                 printk(KERN_ERR "HAL2: Can't get irq %d\n", SGI_HPCDMA_IRQ);
826                 kfree(hal2);
827                 return -EAGAIN;
828         }
829 
830         hal2->ctl_regs = (struct hal2_ctl_regs *)hpc3->pbus_extregs[0];
831         hal2->aes_regs = (struct hal2_aes_regs *)hpc3->pbus_extregs[1];
832         hal2->vol_regs = (struct hal2_vol_regs *)hpc3->pbus_extregs[2];
833         hal2->syn_regs = (struct hal2_syn_regs *)hpc3->pbus_extregs[3];
834 
835         if (hal2_detect(hal2) < 0) {
836                 kfree(hal2);
837                 return -ENODEV;
838         }
839 
840         hal2_init_codec(&hal2->dac, hpc3, 0);
841         hal2_init_codec(&hal2->adc, hpc3, 1);
842 
843         /*
844          * All DMA channel interfaces in HAL2 are designed to operate with
845          * PBUS programmed for 2 cycles in D3, 2 cycles in D4 and 2 cycles
846          * in D5. HAL2 is a 16-bit device which can accept both big and little
847          * endian format. It assumes that even address bytes are on high
848          * portion of PBUS (15:8) and assumes that HPC3 is programmed to
849          * accept a live (unsynchronized) version of P_DREQ_N from HAL2.
850          */
851 #define HAL2_PBUS_DMACFG ((0 << HPC3_DMACFG_D3R_SHIFT) | \
852                           (2 << HPC3_DMACFG_D4R_SHIFT) | \
853                           (2 << HPC3_DMACFG_D5R_SHIFT) | \
854                           (0 << HPC3_DMACFG_D3W_SHIFT) | \
855                           (2 << HPC3_DMACFG_D4W_SHIFT) | \
856                           (2 << HPC3_DMACFG_D5W_SHIFT) | \
857                                 HPC3_DMACFG_DS16 | \
858                                 HPC3_DMACFG_EVENHI | \
859                                 HPC3_DMACFG_RTIME | \
860                           (8 << HPC3_DMACFG_BURST_SHIFT) | \
861                                 HPC3_DMACFG_DRQLIVE)
862         /*
863          * Ignore what's mentioned in the specification and write value which
864          * works in The Real World (TM)
865          */
866         hpc3->pbus_dmacfg[hal2->dac.pbus.pbusnr][0] = 0x8208844;
867         hpc3->pbus_dmacfg[hal2->adc.pbus.pbusnr][0] = 0x8208844;
868 
869         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, hal2, &hal2_ops);
870         if (err < 0) {
871                 free_irq(SGI_HPCDMA_IRQ, hal2);
872                 kfree(hal2);
873                 return err;
874         }
875         *rchip = hal2;
876         return 0;
877 }
878 
879 static int hal2_probe(struct platform_device *pdev)
880 {
881         struct snd_card *card;
882         struct snd_hal2 *chip;
883         int err;
884 
885         err = snd_card_new(&pdev->dev, index, id, THIS_MODULE, 0, &card);
886         if (err < 0)
887                 return err;
888 
889         err = hal2_create(card, &chip);
890         if (err < 0) {
891                 snd_card_free(card);
892                 return err;
893         }
894 
895         err = hal2_pcm_create(chip);
896         if (err < 0) {
897                 snd_card_free(card);
898                 return err;
899         }
900         err = hal2_mixer_create(chip);
901         if (err < 0) {
902                 snd_card_free(card);
903                 return err;
904         }
905 
906         strcpy(card->driver, "SGI HAL2 Audio");
907         strcpy(card->shortname, "SGI HAL2 Audio");
908         sprintf(card->longname, "%s irq %i",
909                 card->shortname,
910                 SGI_HPCDMA_IRQ);
911 
912         err = snd_card_register(card);
913         if (err < 0) {
914                 snd_card_free(card);
915                 return err;
916         }
917         platform_set_drvdata(pdev, card);
918         return 0;
919 }
920 
921 static int hal2_remove(struct platform_device *pdev)
922 {
923         struct snd_card *card = platform_get_drvdata(pdev);
924 
925         snd_card_free(card);
926         return 0;
927 }
928 
929 static struct platform_driver hal2_driver = {
930         .probe  = hal2_probe,
931         .remove = hal2_remove,
932         .driver = {
933                 .name   = "sgihal2",
934         }
935 };
936 
937 module_platform_driver(hal2_driver);
938 

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