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TOMOYO Linux Cross Reference
Linux/sound/oss/vwsnd.c

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  1 /*
  2  * Sound driver for Silicon Graphics 320 and 540 Visual Workstations'
  3  * onboard audio.  See notes in Documentation/sound/oss/vwsnd .
  4  *
  5  * Copyright 1999 Silicon Graphics, Inc.  All rights reserved.
  6  *
  7  * This program is free software; you can redistribute it and/or modify
  8  * it under the terms of the GNU General Public License as published by
  9  * the Free Software Foundation; either version 2 of the License, or
 10  * (at your option) any later version.
 11  *
 12  * This program is distributed in the hope that it will be useful,
 13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 15  * GNU General Public License for more details.
 16  *
 17  * You should have received a copy of the GNU General Public License
 18  * along with this program; if not, write to the Free Software
 19  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 20  */
 21 
 22 #undef VWSND_DEBUG                      /* define for debugging */
 23 
 24 /*
 25  * XXX to do -
 26  *
 27  *      External sync.
 28  *      Rename swbuf, hwbuf, u&i, hwptr&swptr to something rational.
 29  *      Bug - if select() called before read(), pcm_setup() not called.
 30  *      Bug - output doesn't stop soon enough if process killed.
 31  */
 32 
 33 /*
 34  * Things to test -
 35  *
 36  *      Will readv/writev work?  Write a test.
 37  *
 38  *      insmod/rmmod 100 million times.
 39  *
 40  *      Run I/O until int ptrs wrap around (roughly 6.2 hours @ DAT
 41  *      rate).
 42  *
 43  *      Concurrent threads banging on mixer simultaneously, both UP
 44  *      and SMP kernels.  Especially, watch for thread A changing
 45  *      OUTSRC while thread B changes gain -- both write to the same
 46  *      ad1843 register.
 47  *
 48  *      What happens if a client opens /dev/audio then forks?
 49  *      Do two procs have /dev/audio open?  Test.
 50  *
 51  *      Pump audio through the CD, MIC and line inputs and verify that
 52  *      they mix/mute into the output.
 53  *
 54  *      Apps:
 55  *              amp
 56  *              mpg123
 57  *              x11amp
 58  *              mxv
 59  *              kmedia
 60  *              esound
 61  *              need more input apps
 62  *
 63  *      Run tests while bombarding with signals.  setitimer(2) will do it...  */
 64 
 65 /*
 66  * This driver is organized in nine sections.
 67  * The nine sections are:
 68  *
 69  *      debug stuff
 70  *      low level lithium access
 71  *      high level lithium access
 72  *      AD1843 access
 73  *      PCM I/O
 74  *      audio driver
 75  *      mixer driver
 76  *      probe/attach/unload
 77  *      initialization and loadable kernel module interface
 78  *
 79  * That is roughly the order of increasing abstraction, so forward
 80  * dependencies are minimal.
 81  */
 82 
 83 /*
 84  * Locking Notes
 85  *
 86  *      INC_USE_COUNT and DEC_USE_COUNT keep track of the number of
 87  *      open descriptors to this driver. They store it in vwsnd_use_count.
 88  *      The global device list, vwsnd_dev_list, is immutable when the IN_USE
 89  *      is true.
 90  *
 91  *      devc->open_lock is a semaphore that is used to enforce the
 92  *      single reader/single writer rule for /dev/audio.  The rule is
 93  *      that each device may have at most one reader and one writer.
 94  *      Open will block until the previous client has closed the
 95  *      device, unless O_NONBLOCK is specified.
 96  *
 97  *      The semaphore devc->io_mutex serializes PCM I/O syscalls.  This
 98  *      is unnecessary in Linux 2.2, because the kernel lock
 99  *      serializes read, write, and ioctl globally, but it's there,
100  *      ready for the brave, new post-kernel-lock world.
101  *
102  *      Locking between interrupt and baselevel is handled by the
103  *      "lock" spinlock in vwsnd_port (one lock each for read and
104  *      write).  Each half holds the lock just long enough to see what
105  *      area it owns and update its pointers.  See pcm_output() and
106  *      pcm_input() for most of the gory stuff.
107  *
108  *      devc->mix_mutex serializes all mixer ioctls.  This is also
109  *      redundant because of the kernel lock.
110  *
111  *      The lowest level lock is lith->lithium_lock.  It is a
112  *      spinlock which is held during the two-register tango of
113  *      reading/writing an AD1843 register.  See
114  *      li_{read,write}_ad1843_reg().
115  */
116 
117 /*
118  * Sample Format Notes
119  *
120  *      Lithium's DMA engine has two formats: 16-bit 2's complement
121  *      and 8-bit unsigned .  16-bit transfers the data unmodified, 2
122  *      bytes per sample.  8-bit unsigned transfers 1 byte per sample
123  *      and XORs each byte with 0x80.  Lithium can input or output
124  *      either mono or stereo in either format.
125  *
126  *      The AD1843 has four formats: 16-bit 2's complement, 8-bit
127  *      unsigned, 8-bit mu-Law and 8-bit A-Law.
128  *
129  *      This driver supports five formats: AFMT_S8, AFMT_U8,
130  *      AFMT_MU_LAW, AFMT_A_LAW, and AFMT_S16_LE.
131  *
132  *      For AFMT_U8 output, we keep the AD1843 in 16-bit mode, and
133  *      rely on Lithium's XOR to translate between U8 and S8.
134  *
135  *      For AFMT_S8, AFMT_MU_LAW and AFMT_A_LAW output, we have to XOR
136  *      the 0x80 bit in software to compensate for Lithium's XOR.
137  *      This happens in pcm_copy_{in,out}().
138  *
139  * Changes:
140  * 11-10-2000   Bartlomiej Zolnierkiewicz <bkz@linux-ide.org>
141  *              Added some __init/__exit
142  */
143 
144 #include <linux/module.h>
145 #include <linux/init.h>
146 
147 #include <linux/spinlock.h>
148 #include <linux/wait.h>
149 #include <linux/interrupt.h>
150 #include <linux/mutex.h>
151 #include <linux/slab.h>
152 #include <linux/delay.h>
153 
154 #include <asm/visws/cobalt.h>
155 
156 #include "sound_config.h"
157 
158 static DEFINE_MUTEX(vwsnd_mutex);
159 
160 /*****************************************************************************/
161 /* debug stuff */
162 
163 #ifdef VWSND_DEBUG
164 
165 static int shut_up = 1;
166 
167 /*
168  * dbgassert - called when an assertion fails.
169  */
170 
171 static void dbgassert(const char *fcn, int line, const char *expr)
172 {
173         if (in_interrupt())
174                 panic("ASSERTION FAILED IN INTERRUPT, %s:%s:%d %s\n",
175                       __FILE__, fcn, line, expr);
176         else {
177                 int x;
178                 printk(KERN_ERR "ASSERTION FAILED, %s:%s:%d %s\n",
179                        __FILE__, fcn, line, expr);
180                 x = * (volatile int *) 0; /* force proc to exit */
181         }
182 }
183 
184 /*
185  * Bunch of useful debug macros:
186  *
187  *      ASSERT  - print unless e nonzero (panic if in interrupt)
188  *      DBGDO   - include arbitrary code if debugging
189  *      DBGX    - debug print raw (w/o function name)
190  *      DBGP    - debug print w/ function name
191  *      DBGE    - debug print function entry
192  *      DBGC    - debug print function call
193  *      DBGR    - debug print function return
194  *      DBGXV   - debug print raw when verbose
195  *      DBGPV   - debug print when verbose
196  *      DBGEV   - debug print function entry when verbose
197  *      DBGRV   - debug print function return when verbose
198  */
199 
200 #define ASSERT(e)      ((e) ? (void) 0 : dbgassert(__func__, __LINE__, #e))
201 #define DBGDO(x)            x
202 #define DBGX(fmt, args...)  (in_interrupt() ? 0 : printk(KERN_ERR fmt, ##args))
203 #define DBGP(fmt, args...)  (DBGX("%s: " fmt, __func__ , ##args))
204 #define DBGE(fmt, args...)  (DBGX("%s" fmt, __func__ , ##args))
205 #define DBGC(rtn)           (DBGP("calling %s\n", rtn))
206 #define DBGR()              (DBGP("returning\n"))
207 #define DBGXV(fmt, args...) (shut_up ? 0 : DBGX(fmt, ##args))
208 #define DBGPV(fmt, args...) (shut_up ? 0 : DBGP(fmt, ##args))
209 #define DBGEV(fmt, args...) (shut_up ? 0 : DBGE(fmt, ##args))
210 #define DBGCV(rtn)          (shut_up ? 0 : DBGC(rtn))
211 #define DBGRV()             (shut_up ? 0 : DBGR())
212 
213 #else /* !VWSND_DEBUG */
214 
215 #define ASSERT(e)           ((void) 0)
216 #define DBGDO(x)            /* don't */
217 #define DBGX(fmt, args...)  ((void) 0)
218 #define DBGP(fmt, args...)  ((void) 0)
219 #define DBGE(fmt, args...)  ((void) 0)
220 #define DBGC(rtn)           ((void) 0)
221 #define DBGR()              ((void) 0)
222 #define DBGPV(fmt, args...) ((void) 0)
223 #define DBGXV(fmt, args...) ((void) 0)
224 #define DBGEV(fmt, args...) ((void) 0)
225 #define DBGCV(rtn)          ((void) 0)
226 #define DBGRV()             ((void) 0)
227 
228 #endif /* !VWSND_DEBUG */
229 
230 /*****************************************************************************/
231 /* low level lithium access */
232 
233 /*
234  * We need to talk to Lithium registers on three pages.  Here are
235  * the pages' offsets from the base address (0xFF001000).
236  */
237 
238 enum {
239         LI_PAGE0_OFFSET = 0x01000 - 0x1000, /* FF001000 */
240         LI_PAGE1_OFFSET = 0x0F000 - 0x1000, /* FF00F000 */
241         LI_PAGE2_OFFSET = 0x10000 - 0x1000, /* FF010000 */
242 };
243 
244 /* low-level lithium data */
245 
246 typedef struct lithium {
247         void *          page0;          /* virtual addresses */
248         void *          page1;
249         void *          page2;
250         spinlock_t      lock;           /* protects codec and UST/MSC access */
251 } lithium_t;
252 
253 /*
254  * li_destroy destroys the lithium_t structure and vm mappings.
255  */
256 
257 static void li_destroy(lithium_t *lith)
258 {
259         if (lith->page0) {
260                 iounmap(lith->page0);
261                 lith->page0 = NULL;
262         }
263         if (lith->page1) {
264                 iounmap(lith->page1);
265                 lith->page1 = NULL;
266         }
267         if (lith->page2) {
268                 iounmap(lith->page2);
269                 lith->page2 = NULL;
270         }
271 }
272 
273 /*
274  * li_create initializes the lithium_t structure and sets up vm mappings
275  * to access the registers.
276  * Returns 0 on success, -errno on failure.
277  */
278 
279 static int __init li_create(lithium_t *lith, unsigned long baseaddr)
280 {
281         spin_lock_init(&lith->lock);
282         lith->page0 = ioremap_nocache(baseaddr + LI_PAGE0_OFFSET, PAGE_SIZE);
283         lith->page1 = ioremap_nocache(baseaddr + LI_PAGE1_OFFSET, PAGE_SIZE);
284         lith->page2 = ioremap_nocache(baseaddr + LI_PAGE2_OFFSET, PAGE_SIZE);
285         if (!lith->page0 || !lith->page1 || !lith->page2) {
286                 li_destroy(lith);
287                 return -ENOMEM;
288         }
289         return 0;
290 }
291 
292 /*
293  * basic register accessors - read/write long/byte
294  */
295 
296 static __inline__ unsigned long li_readl(lithium_t *lith, int off)
297 {
298         return * (volatile unsigned long *) (lith->page0 + off);
299 }
300 
301 static __inline__ unsigned char li_readb(lithium_t *lith, int off)
302 {
303         return * (volatile unsigned char *) (lith->page0 + off);
304 }
305 
306 static __inline__ void li_writel(lithium_t *lith, int off, unsigned long val)
307 {
308         * (volatile unsigned long *) (lith->page0 + off) = val;
309 }
310 
311 static __inline__ void li_writeb(lithium_t *lith, int off, unsigned char val)
312 {
313         * (volatile unsigned char *) (lith->page0 + off) = val;
314 }
315 
316 /*****************************************************************************/
317 /* High Level Lithium Access */
318 
319 /*
320  * Lithium DMA Notes
321  *
322  * Lithium has two dedicated DMA channels for audio.  They are known
323  * as comm1 and comm2 (communication areas 1 and 2).  Comm1 is for
324  * input, and comm2 is for output.  Each is controlled by three
325  * registers: BASE (base address), CFG (config) and CCTL
326  * (config/control).
327  *
328  * Each DMA channel points to a physically contiguous ring buffer in
329  * main memory of up to 8 Kbytes.  (This driver always uses 8 Kb.)
330  * There are three pointers into the ring buffer: read, write, and
331  * trigger.  The pointers are 8 bits each.  Each pointer points to
332  * 32-byte "chunks" of data.  The DMA engine moves 32 bytes at a time,
333  * so there is no finer-granularity control.
334  *
335  * In comm1, the hardware updates the write ptr, and software updates
336  * the read ptr.  In comm2, it's the opposite: hardware updates the
337  * read ptr, and software updates the write ptr.  I designate the
338  * hardware-updated ptr as the hwptr, and the software-updated ptr as
339  * the swptr.
340  *
341  * The trigger ptr and trigger mask are used to trigger interrupts.
342  * From the Lithium spec, section 5.6.8, revision of 12/15/1998:
343  *
344  *      Trigger Mask Value
345  *
346  *      A three bit wide field that represents a power of two mask
347  *      that is used whenever the trigger pointer is compared to its
348  *      respective read or write pointer.  A value of zero here
349  *      implies a mask of 0xFF and a value of seven implies a mask
350  *      0x01.  This value can be used to sub-divide the ring buffer
351  *      into pie sections so that interrupts monitor the progress of
352  *      hardware from section to section.
353  *
354  * My interpretation of that is, whenever the hw ptr is updated, it is
355  * compared with the trigger ptr, and the result is masked by the
356  * trigger mask.  (Actually, by the complement of the trigger mask.)
357  * If the result is zero, an interrupt is triggered.  I.e., interrupt
358  * if ((hwptr & ~mask) == (trptr & ~mask)).  The mask is formed from
359  * the trigger register value as mask = (1 << (8 - tmreg)) - 1.
360  *
361  * In yet different words, setting tmreg to 0 causes an interrupt after
362  * every 256 DMA chunks (8192 bytes) or once per traversal of the
363  * ring buffer.  Setting it to 7 caues an interrupt every 2 DMA chunks
364  * (64 bytes) or 128 times per traversal of the ring buffer.
365  */
366 
367 /* Lithium register offsets and bit definitions */
368 
369 #define LI_HOST_CONTROLLER      0x000
370 # define LI_HC_RESET             0x00008000
371 # define LI_HC_LINK_ENABLE       0x00004000
372 # define LI_HC_LINK_FAILURE      0x00000004
373 # define LI_HC_LINK_CODEC        0x00000002
374 # define LI_HC_LINK_READY        0x00000001
375 
376 #define LI_INTR_STATUS          0x010
377 #define LI_INTR_MASK            0x014
378 # define LI_INTR_LINK_ERR        0x00008000
379 # define LI_INTR_COMM2_TRIG      0x00000008
380 # define LI_INTR_COMM2_UNDERFLOW 0x00000004
381 # define LI_INTR_COMM1_TRIG      0x00000002
382 # define LI_INTR_COMM1_OVERFLOW  0x00000001
383 
384 #define LI_CODEC_COMMAND        0x018
385 # define LI_CC_BUSY              0x00008000
386 # define LI_CC_DIR               0x00000080
387 #  define LI_CC_DIR_RD            LI_CC_DIR
388 #  define LI_CC_DIR_WR          (!LI_CC_DIR)
389 # define LI_CC_ADDR_MASK         0x0000007F
390 
391 #define LI_CODEC_DATA           0x01C
392 
393 #define LI_COMM1_BASE           0x100
394 #define LI_COMM1_CTL            0x104
395 # define LI_CCTL_RESET           0x80000000
396 # define LI_CCTL_SIZE            0x70000000
397 # define LI_CCTL_DMA_ENABLE      0x08000000
398 # define LI_CCTL_TMASK           0x07000000 /* trigger mask */
399 # define LI_CCTL_TPTR            0x00FF0000 /* trigger pointer */
400 # define LI_CCTL_RPTR            0x0000FF00
401 # define LI_CCTL_WPTR            0x000000FF
402 #define LI_COMM1_CFG            0x108
403 # define LI_CCFG_LOCK            0x00008000
404 # define LI_CCFG_SLOT            0x00000070
405 # define LI_CCFG_DIRECTION       0x00000008
406 #  define LI_CCFG_DIR_IN        (!LI_CCFG_DIRECTION)
407 #  define LI_CCFG_DIR_OUT         LI_CCFG_DIRECTION
408 # define LI_CCFG_MODE            0x00000004
409 #  define LI_CCFG_MODE_MONO     (!LI_CCFG_MODE)
410 #  define LI_CCFG_MODE_STEREO     LI_CCFG_MODE
411 # define LI_CCFG_FORMAT          0x00000003
412 #  define LI_CCFG_FMT_8BIT        0x00000000
413 #  define LI_CCFG_FMT_16BIT       0x00000001
414 #define LI_COMM2_BASE           0x10C
415 #define LI_COMM2_CTL            0x110
416  /* bit definitions are the same as LI_COMM1_CTL */
417 #define LI_COMM2_CFG            0x114
418  /* bit definitions are the same as LI_COMM1_CFG */
419 
420 #define LI_UST_LOW              0x200   /* 64-bit Unadjusted System Time is */
421 #define LI_UST_HIGH             0x204   /* microseconds since boot */
422 
423 #define LI_AUDIO1_UST           0x300   /* UST-MSC pairs */
424 #define LI_AUDIO1_MSC           0x304   /* MSC (Media Stream Counter) */
425 #define LI_AUDIO2_UST           0x308   /* counts samples actually */
426 #define LI_AUDIO2_MSC           0x30C   /* processed as of time UST */
427 
428 /* 
429  * Lithium's DMA engine operates on chunks of 32 bytes.  We call that
430  * a DMACHUNK.
431  */
432 
433 #define DMACHUNK_SHIFT 5
434 #define DMACHUNK_SIZE (1 << DMACHUNK_SHIFT)
435 #define BYTES_TO_CHUNKS(bytes) ((bytes) >> DMACHUNK_SHIFT)
436 #define CHUNKS_TO_BYTES(chunks) ((chunks) << DMACHUNK_SHIFT)
437 
438 /*
439  * Two convenient macros to shift bitfields into/out of position.
440  *
441  * Observe that (mask & -mask) is (1 << low_set_bit_of(mask)).
442  * As long as mask is constant, we trust the compiler will change the
443  * multiply and divide into shifts.
444  */
445 
446 #define SHIFT_FIELD(val, mask) (((val) * ((mask) & -(mask))) & (mask))
447 #define UNSHIFT_FIELD(val, mask) (((val) & (mask)) / ((mask) & -(mask)))
448 
449 /*
450  * dma_chan_desc is invariant information about a Lithium
451  * DMA channel.  There are two instances, li_comm1 and li_comm2.
452  *
453  * Note that the CCTL register fields are write ptr and read ptr, but what
454  * we care about are which pointer is updated by software and which by
455  * hardware.
456  */
457 
458 typedef struct dma_chan_desc {
459         int basereg;
460         int cfgreg;
461         int ctlreg;
462         int hwptrreg;
463         int swptrreg;
464         int ustreg;
465         int mscreg;
466         unsigned long swptrmask;
467         int ad1843_slot;
468         int direction;                  /* LI_CCTL_DIR_IN/OUT */
469 } dma_chan_desc_t;
470 
471 static const dma_chan_desc_t li_comm1 = {
472         LI_COMM1_BASE,                  /* base register offset */
473         LI_COMM1_CFG,                   /* config register offset */
474         LI_COMM1_CTL,                   /* control register offset */
475         LI_COMM1_CTL + 0,               /* hw ptr reg offset (write ptr) */
476         LI_COMM1_CTL + 1,               /* sw ptr reg offset (read ptr) */
477         LI_AUDIO1_UST,                  /* ust reg offset */
478         LI_AUDIO1_MSC,                  /* msc reg offset */
479         LI_CCTL_RPTR,                   /* sw ptr bitmask in ctlval */
480         2,                              /* ad1843 serial slot */
481         LI_CCFG_DIR_IN                  /* direction */
482 };
483 
484 static const dma_chan_desc_t li_comm2 = {
485         LI_COMM2_BASE,                  /* base register offset */
486         LI_COMM2_CFG,                   /* config register offset */
487         LI_COMM2_CTL,                   /* control register offset */
488         LI_COMM2_CTL + 1,               /* hw ptr reg offset (read ptr) */
489         LI_COMM2_CTL + 0,               /* sw ptr reg offset (writr ptr) */
490         LI_AUDIO2_UST,                  /* ust reg offset */
491         LI_AUDIO2_MSC,                  /* msc reg offset */
492         LI_CCTL_WPTR,                   /* sw ptr bitmask in ctlval */
493         2,                              /* ad1843 serial slot */
494         LI_CCFG_DIR_OUT                 /* direction */
495 };
496 
497 /*
498  * dma_chan is variable information about a Lithium DMA channel.
499  *
500  * The desc field points to invariant information.
501  * The lith field points to a lithium_t which is passed
502  * to li_read* and li_write* to access the registers.
503  * The *val fields shadow the lithium registers' contents.
504  */
505 
506 typedef struct dma_chan {
507         const dma_chan_desc_t *desc;
508         lithium_t      *lith;
509         unsigned long   baseval;
510         unsigned long   cfgval;
511         unsigned long   ctlval;
512 } dma_chan_t;
513 
514 /*
515  * ustmsc is a UST/MSC pair (Unadjusted System Time/Media Stream Counter).
516  * UST is time in microseconds since the system booted, and MSC is a
517  * counter that increments with every audio sample.
518  */
519 
520 typedef struct ustmsc {
521         unsigned long long ust;
522         unsigned long msc;
523 } ustmsc_t;
524 
525 /*
526  * li_ad1843_wait waits until lithium says the AD1843 register
527  * exchange is not busy.  Returns 0 on success, -EBUSY on timeout.
528  *
529  * Locking: must be called with lithium_lock held.
530  */
531 
532 static int li_ad1843_wait(lithium_t *lith)
533 {
534         unsigned long later = jiffies + 2;
535         while (li_readl(lith, LI_CODEC_COMMAND) & LI_CC_BUSY)
536                 if (time_after_eq(jiffies, later))
537                         return -EBUSY;
538         return 0;
539 }
540 
541 /*
542  * li_read_ad1843_reg returns the current contents of a 16 bit AD1843 register.
543  *
544  * Returns unsigned register value on success, -errno on failure.
545  */
546 
547 static int li_read_ad1843_reg(lithium_t *lith, int reg)
548 {
549         int val;
550 
551         ASSERT(!in_interrupt());
552         spin_lock(&lith->lock);
553         {
554                 val = li_ad1843_wait(lith);
555                 if (val == 0) {
556                         li_writel(lith, LI_CODEC_COMMAND, LI_CC_DIR_RD | reg);
557                         val = li_ad1843_wait(lith);
558                 }
559                 if (val == 0)
560                         val = li_readl(lith, LI_CODEC_DATA);
561         }
562         spin_unlock(&lith->lock);
563 
564         DBGXV("li_read_ad1843_reg(lith=0x%p, reg=%d) returns 0x%04x\n",
565               lith, reg, val);
566 
567         return val;
568 }
569 
570 /*
571  * li_write_ad1843_reg writes the specified value to a 16 bit AD1843 register.
572  */
573 
574 static void li_write_ad1843_reg(lithium_t *lith, int reg, int newval)
575 {
576         spin_lock(&lith->lock);
577         {
578                 if (li_ad1843_wait(lith) == 0) {
579                         li_writel(lith, LI_CODEC_DATA, newval);
580                         li_writel(lith, LI_CODEC_COMMAND, LI_CC_DIR_WR | reg);
581                 }
582         }
583         spin_unlock(&lith->lock);
584 }
585 
586 /*
587  * li_setup_dma calculates all the register settings for DMA in a particular
588  * mode.  It takes too many arguments.
589  */
590 
591 static void li_setup_dma(dma_chan_t *chan,
592                          const dma_chan_desc_t *desc,
593                          lithium_t *lith,
594                          unsigned long buffer_paddr,
595                          int bufshift,
596                          int fragshift,
597                          int channels,
598                          int sampsize)
599 {
600         unsigned long mode, format;
601         unsigned long size, tmask;
602 
603         DBGEV("(chan=0x%p, desc=0x%p, lith=0x%p, buffer_paddr=0x%lx, "
604              "bufshift=%d, fragshift=%d, channels=%d, sampsize=%d)\n",
605              chan, desc, lith, buffer_paddr,
606              bufshift, fragshift, channels, sampsize);
607 
608         /* Reset the channel first. */
609 
610         li_writel(lith, desc->ctlreg, LI_CCTL_RESET);
611 
612         ASSERT(channels == 1 || channels == 2);
613         if (channels == 2)
614                 mode = LI_CCFG_MODE_STEREO;
615         else
616                 mode = LI_CCFG_MODE_MONO;
617         ASSERT(sampsize == 1 || sampsize == 2);
618         if (sampsize == 2)
619                 format = LI_CCFG_FMT_16BIT;
620         else
621                 format = LI_CCFG_FMT_8BIT;
622         chan->desc = desc;
623         chan->lith = lith;
624 
625         /*
626          * Lithium DMA address register takes a 40-bit physical
627          * address, right-shifted by 8 so it fits in 32 bits.  Bit 37
628          * must be set -- it enables cache coherence.
629          */
630 
631         ASSERT(!(buffer_paddr & 0xFF));
632         chan->baseval = (buffer_paddr >> 8) | 1 << (37 - 8);
633 
634         chan->cfgval = ((chan->cfgval & ~LI_CCFG_LOCK) |
635                         SHIFT_FIELD(desc->ad1843_slot, LI_CCFG_SLOT) |
636                         desc->direction |
637                         mode |
638                         format);
639 
640         size = bufshift - 6;
641         tmask = 13 - fragshift;         /* See Lithium DMA Notes above. */
642         ASSERT(size >= 2 && size <= 7);
643         ASSERT(tmask >= 1 && tmask <= 7);
644         chan->ctlval = ((chan->ctlval & ~LI_CCTL_RESET) |
645                         SHIFT_FIELD(size, LI_CCTL_SIZE) |
646                         (chan->ctlval & ~LI_CCTL_DMA_ENABLE) |
647                         SHIFT_FIELD(tmask, LI_CCTL_TMASK) |
648                         SHIFT_FIELD(0, LI_CCTL_TPTR));
649 
650         DBGPV("basereg 0x%x = 0x%lx\n", desc->basereg, chan->baseval);
651         DBGPV("cfgreg 0x%x = 0x%lx\n", desc->cfgreg, chan->cfgval);
652         DBGPV("ctlreg 0x%x = 0x%lx\n", desc->ctlreg, chan->ctlval);
653 
654         li_writel(lith, desc->basereg, chan->baseval);
655         li_writel(lith, desc->cfgreg, chan->cfgval);
656         li_writel(lith, desc->ctlreg, chan->ctlval);
657 
658         DBGRV();
659 }
660 
661 static void li_shutdown_dma(dma_chan_t *chan)
662 {
663         lithium_t *lith = chan->lith;
664         void * lith1 = lith->page1;
665 
666         DBGEV("(chan=0x%p)\n", chan);
667         
668         chan->ctlval &= ~LI_CCTL_DMA_ENABLE;
669         DBGPV("ctlreg 0x%x = 0x%lx\n", chan->desc->ctlreg, chan->ctlval);
670         li_writel(lith, chan->desc->ctlreg, chan->ctlval);
671 
672         /*
673          * Offset 0x500 on Lithium page 1 is an undocumented,
674          * unsupported register that holds the zero sample value.
675          * Lithium is supposed to output zero samples when DMA is
676          * inactive, and repeat the last sample when DMA underflows.
677          * But it has a bug, where, after underflow occurs, the zero
678          * sample is not reset.
679          *
680          * I expect this to break in a future rev of Lithium.
681          */
682 
683         if (lith1 && chan->desc->direction == LI_CCFG_DIR_OUT)
684                 * (volatile unsigned long *) (lith1 + 0x500) = 0;
685 }
686 
687 /*
688  * li_activate_dma always starts dma at the beginning of the buffer.
689  *
690  * N.B., these may be called from interrupt.
691  */
692 
693 static __inline__ void li_activate_dma(dma_chan_t *chan)
694 {
695         chan->ctlval |= LI_CCTL_DMA_ENABLE;
696         DBGPV("ctlval = 0x%lx\n", chan->ctlval);
697         li_writel(chan->lith, chan->desc->ctlreg, chan->ctlval);
698 }
699 
700 static void li_deactivate_dma(dma_chan_t *chan)
701 {
702         lithium_t *lith = chan->lith;
703         void * lith2 = lith->page2;
704 
705         chan->ctlval &= ~(LI_CCTL_DMA_ENABLE | LI_CCTL_RPTR | LI_CCTL_WPTR);
706         DBGPV("ctlval = 0x%lx\n", chan->ctlval);
707         DBGPV("ctlreg 0x%x = 0x%lx\n", chan->desc->ctlreg, chan->ctlval);
708         li_writel(lith, chan->desc->ctlreg, chan->ctlval);
709 
710         /*
711          * Offsets 0x98 and 0x9C on Lithium page 2 are undocumented,
712          * unsupported registers that are internal copies of the DMA
713          * read and write pointers.  Because of a Lithium bug, these
714          * registers aren't zeroed correctly when DMA is shut off.  So
715          * we whack them directly.
716          *
717          * I expect this to break in a future rev of Lithium.
718          */
719 
720         if (lith2 && chan->desc->direction == LI_CCFG_DIR_OUT) {
721                 * (volatile unsigned long *) (lith2 + 0x98) = 0;
722                 * (volatile unsigned long *) (lith2 + 0x9C) = 0;
723         }
724 }
725 
726 /*
727  * read/write the ring buffer pointers.  These routines' arguments and results
728  * are byte offsets from the beginning of the ring buffer.
729  */
730 
731 static __inline__ int li_read_swptr(dma_chan_t *chan)
732 {
733         const unsigned long mask = chan->desc->swptrmask;
734 
735         return CHUNKS_TO_BYTES(UNSHIFT_FIELD(chan->ctlval, mask));
736 }
737 
738 static __inline__ int li_read_hwptr(dma_chan_t *chan)
739 {
740         return CHUNKS_TO_BYTES(li_readb(chan->lith, chan->desc->hwptrreg));
741 }
742 
743 static __inline__ void li_write_swptr(dma_chan_t *chan, int val)
744 {
745         const unsigned long mask = chan->desc->swptrmask;
746 
747         ASSERT(!(val & ~CHUNKS_TO_BYTES(0xFF)));
748         val = BYTES_TO_CHUNKS(val);
749         chan->ctlval = (chan->ctlval & ~mask) | SHIFT_FIELD(val, mask);
750         li_writeb(chan->lith, chan->desc->swptrreg, val);
751 }
752 
753 /* li_read_USTMSC() returns a UST/MSC pair for the given channel. */
754 
755 static void li_read_USTMSC(dma_chan_t *chan, ustmsc_t *ustmsc)
756 {
757         lithium_t *lith = chan->lith;
758         const dma_chan_desc_t *desc = chan->desc;
759         unsigned long now_low, now_high0, now_high1, chan_ust;
760 
761         spin_lock(&lith->lock);
762         {
763                 /*
764                  * retry until we do all five reads without the
765                  * high word changing.  (High word increments
766                  * every 2^32 microseconds, i.e., not often)
767                  */
768                 do {
769                         now_high0 = li_readl(lith, LI_UST_HIGH);
770                         now_low = li_readl(lith, LI_UST_LOW);
771 
772                         /*
773                          * Lithium guarantees these two reads will be
774                          * atomic -- ust will not increment after msc
775                          * is read.
776                          */
777 
778                         ustmsc->msc = li_readl(lith, desc->mscreg);
779                         chan_ust = li_readl(lith, desc->ustreg);
780 
781                         now_high1 = li_readl(lith, LI_UST_HIGH);
782                 } while (now_high0 != now_high1);
783         }       
784         spin_unlock(&lith->lock);
785         ustmsc->ust = ((unsigned long long) now_high0 << 32 | chan_ust);
786 }
787 
788 static void li_enable_interrupts(lithium_t *lith, unsigned int mask)
789 {
790         DBGEV("(lith=0x%p, mask=0x%x)\n", lith, mask);
791 
792         /* clear any already-pending interrupts. */
793 
794         li_writel(lith, LI_INTR_STATUS, mask);
795 
796         /* enable the interrupts. */
797 
798         mask |= li_readl(lith, LI_INTR_MASK);
799         li_writel(lith, LI_INTR_MASK, mask);
800 }
801 
802 static void li_disable_interrupts(lithium_t *lith, unsigned int mask)
803 {
804         unsigned int keepmask;
805 
806         DBGEV("(lith=0x%p, mask=0x%x)\n", lith, mask);
807 
808         /* disable the interrupts */
809 
810         keepmask = li_readl(lith, LI_INTR_MASK) & ~mask;
811         li_writel(lith, LI_INTR_MASK, keepmask);
812 
813         /* clear any pending interrupts. */
814 
815         li_writel(lith, LI_INTR_STATUS, mask);
816 }
817 
818 /* Get the interrupt status and clear all pending interrupts. */
819 
820 static unsigned int li_get_clear_intr_status(lithium_t *lith)
821 {
822         unsigned int status;
823 
824         status = li_readl(lith, LI_INTR_STATUS);
825         li_writel(lith, LI_INTR_STATUS, ~0);
826         return status & li_readl(lith, LI_INTR_MASK);
827 }
828 
829 static int li_init(lithium_t *lith)
830 {
831         /* 1. System power supplies stabilize. */
832 
833         /* 2. Assert the ~RESET signal. */
834 
835         li_writel(lith, LI_HOST_CONTROLLER, LI_HC_RESET);
836         udelay(1);
837 
838         /* 3. Deassert the ~RESET signal and enter a wait period to allow
839            the AD1843 internal clocks and the external crystal oscillator
840            to stabilize. */
841 
842         li_writel(lith, LI_HOST_CONTROLLER, LI_HC_LINK_ENABLE);
843         udelay(1);
844 
845         return 0;
846 }
847 
848 /*****************************************************************************/
849 /* AD1843 access */
850 
851 /*
852  * AD1843 bitfield definitions.  All are named as in the AD1843 data
853  * sheet, with ad1843_ prepended and individual bit numbers removed.
854  *
855  * E.g., bits LSS0 through LSS2 become ad1843_LSS.
856  *
857  * Only the bitfields we need are defined.
858  */
859 
860 typedef struct ad1843_bitfield {
861         char reg;
862         char lo_bit;
863         char nbits;
864 } ad1843_bitfield_t;
865 
866 static const ad1843_bitfield_t
867         ad1843_PDNO   = {  0, 14,  1 }, /* Converter Power-Down Flag */
868         ad1843_INIT   = {  0, 15,  1 }, /* Clock Initialization Flag */
869         ad1843_RIG    = {  2,  0,  4 }, /* Right ADC Input Gain */
870         ad1843_RMGE   = {  2,  4,  1 }, /* Right ADC Mic Gain Enable */
871         ad1843_RSS    = {  2,  5,  3 }, /* Right ADC Source Select */
872         ad1843_LIG    = {  2,  8,  4 }, /* Left ADC Input Gain */
873         ad1843_LMGE   = {  2, 12,  1 }, /* Left ADC Mic Gain Enable */
874         ad1843_LSS    = {  2, 13,  3 }, /* Left ADC Source Select */
875         ad1843_RX1M   = {  4,  0,  5 }, /* Right Aux 1 Mix Gain/Atten */
876         ad1843_RX1MM  = {  4,  7,  1 }, /* Right Aux 1 Mix Mute */
877         ad1843_LX1M   = {  4,  8,  5 }, /* Left Aux 1 Mix Gain/Atten */
878         ad1843_LX1MM  = {  4, 15,  1 }, /* Left Aux 1 Mix Mute */
879         ad1843_RX2M   = {  5,  0,  5 }, /* Right Aux 2 Mix Gain/Atten */
880         ad1843_RX2MM  = {  5,  7,  1 }, /* Right Aux 2 Mix Mute */
881         ad1843_LX2M   = {  5,  8,  5 }, /* Left Aux 2 Mix Gain/Atten */
882         ad1843_LX2MM  = {  5, 15,  1 }, /* Left Aux 2 Mix Mute */
883         ad1843_RMCM   = {  7,  0,  5 }, /* Right Mic Mix Gain/Atten */
884         ad1843_RMCMM  = {  7,  7,  1 }, /* Right Mic Mix Mute */
885         ad1843_LMCM   = {  7,  8,  5 }, /* Left Mic Mix Gain/Atten */
886         ad1843_LMCMM  = {  7, 15,  1 }, /* Left Mic Mix Mute */
887         ad1843_HPOS   = {  8,  4,  1 }, /* Headphone Output Voltage Swing */
888         ad1843_HPOM   = {  8,  5,  1 }, /* Headphone Output Mute */
889         ad1843_RDA1G  = {  9,  0,  6 }, /* Right DAC1 Analog/Digital Gain */
890         ad1843_RDA1GM = {  9,  7,  1 }, /* Right DAC1 Analog Mute */
891         ad1843_LDA1G  = {  9,  8,  6 }, /* Left DAC1 Analog/Digital Gain */
892         ad1843_LDA1GM = {  9, 15,  1 }, /* Left DAC1 Analog Mute */
893         ad1843_RDA1AM = { 11,  7,  1 }, /* Right DAC1 Digital Mute */
894         ad1843_LDA1AM = { 11, 15,  1 }, /* Left DAC1 Digital Mute */
895         ad1843_ADLC   = { 15,  0,  2 }, /* ADC Left Sample Rate Source */
896         ad1843_ADRC   = { 15,  2,  2 }, /* ADC Right Sample Rate Source */
897         ad1843_DA1C   = { 15,  8,  2 }, /* DAC1 Sample Rate Source */
898         ad1843_C1C    = { 17,  0, 16 }, /* Clock 1 Sample Rate Select */
899         ad1843_C2C    = { 20,  0, 16 }, /* Clock 1 Sample Rate Select */
900         ad1843_DAADL  = { 25,  4,  2 }, /* Digital ADC Left Source Select */
901         ad1843_DAADR  = { 25,  6,  2 }, /* Digital ADC Right Source Select */
902         ad1843_DRSFLT = { 25, 15,  1 }, /* Digital Reampler Filter Mode */
903         ad1843_ADLF   = { 26,  0,  2 }, /* ADC Left Channel Data Format */
904         ad1843_ADRF   = { 26,  2,  2 }, /* ADC Right Channel Data Format */
905         ad1843_ADTLK  = { 26,  4,  1 }, /* ADC Transmit Lock Mode Select */
906         ad1843_SCF    = { 26,  7,  1 }, /* SCLK Frequency Select */
907         ad1843_DA1F   = { 26,  8,  2 }, /* DAC1 Data Format Select */
908         ad1843_DA1SM  = { 26, 14,  1 }, /* DAC1 Stereo/Mono Mode Select */
909         ad1843_ADLEN  = { 27,  0,  1 }, /* ADC Left Channel Enable */
910         ad1843_ADREN  = { 27,  1,  1 }, /* ADC Right Channel Enable */
911         ad1843_AAMEN  = { 27,  4,  1 }, /* Analog to Analog Mix Enable */
912         ad1843_ANAEN  = { 27,  7,  1 }, /* Analog Channel Enable */
913         ad1843_DA1EN  = { 27,  8,  1 }, /* DAC1 Enable */
914         ad1843_DA2EN  = { 27,  9,  1 }, /* DAC2 Enable */
915         ad1843_C1EN   = { 28, 11,  1 }, /* Clock Generator 1 Enable */
916         ad1843_C2EN   = { 28, 12,  1 }, /* Clock Generator 2 Enable */
917         ad1843_PDNI   = { 28, 15,  1 }; /* Converter Power Down */
918 
919 /*
920  * The various registers of the AD1843 use three different formats for
921  * specifying gain.  The ad1843_gain structure parameterizes the
922  * formats.
923  */
924 
925 typedef struct ad1843_gain {
926 
927         int     negative;               /* nonzero if gain is negative. */
928         const ad1843_bitfield_t *lfield;
929         const ad1843_bitfield_t *rfield;
930 
931 } ad1843_gain_t;
932 
933 static const ad1843_gain_t ad1843_gain_RECLEV
934                                 = { 0, &ad1843_LIG,   &ad1843_RIG };
935 static const ad1843_gain_t ad1843_gain_LINE
936                                 = { 1, &ad1843_LX1M,  &ad1843_RX1M };
937 static const ad1843_gain_t ad1843_gain_CD
938                                 = { 1, &ad1843_LX2M,  &ad1843_RX2M };
939 static const ad1843_gain_t ad1843_gain_MIC
940                                 = { 1, &ad1843_LMCM,  &ad1843_RMCM };
941 static const ad1843_gain_t ad1843_gain_PCM
942                                 = { 1, &ad1843_LDA1G, &ad1843_RDA1G };
943 
944 /* read the current value of an AD1843 bitfield. */
945 
946 static int ad1843_read_bits(lithium_t *lith, const ad1843_bitfield_t *field)
947 {
948         int w = li_read_ad1843_reg(lith, field->reg);
949         int val = w >> field->lo_bit & ((1 << field->nbits) - 1);
950 
951         DBGXV("ad1843_read_bits(lith=0x%p, field->{%d %d %d}) returns 0x%x\n",
952               lith, field->reg, field->lo_bit, field->nbits, val);
953 
954         return val;
955 }
956 
957 /*
958  * write a new value to an AD1843 bitfield and return the old value.
959  */
960 
961 static int ad1843_write_bits(lithium_t *lith,
962                              const ad1843_bitfield_t *field,
963                              int newval)
964 {
965         int w = li_read_ad1843_reg(lith, field->reg);
966         int mask = ((1 << field->nbits) - 1) << field->lo_bit;
967         int oldval = (w & mask) >> field->lo_bit;
968         int newbits = (newval << field->lo_bit) & mask;
969         w = (w & ~mask) | newbits;
970         (void) li_write_ad1843_reg(lith, field->reg, w);
971 
972         DBGXV("ad1843_write_bits(lith=0x%p, field->{%d %d %d}, val=0x%x) "
973               "returns 0x%x\n",
974               lith, field->reg, field->lo_bit, field->nbits, newval,
975               oldval);
976 
977         return oldval;
978 }
979 
980 /*
981  * ad1843_read_multi reads multiple bitfields from the same AD1843
982  * register.  It uses a single read cycle to do it.  (Reading the
983  * ad1843 requires 256 bit times at 12.288 MHz, or nearly 20
984  * microseconds.)
985  *
986  * Called ike this.
987  *
988  *  ad1843_read_multi(lith, nfields,
989  *                    &ad1843_FIELD1, &val1,
990  *                    &ad1843_FIELD2, &val2, ...);
991  */
992 
993 static void ad1843_read_multi(lithium_t *lith, int argcount, ...)
994 {
995         va_list ap;
996         const ad1843_bitfield_t *fp;
997         int w = 0, mask, *value, reg = -1;
998 
999         va_start(ap, argcount);
1000         while (--argcount >= 0) {
1001                 fp = va_arg(ap, const ad1843_bitfield_t *);
1002                 value = va_arg(ap, int *);
1003                 if (reg == -1) {
1004                         reg = fp->reg;
1005                         w = li_read_ad1843_reg(lith, reg);
1006                 }
1007                 ASSERT(reg == fp->reg);
1008                 mask = (1 << fp->nbits) - 1;
1009                 *value = w >> fp->lo_bit & mask;
1010         }
1011         va_end(ap);
1012 }
1013 
1014 /*
1015  * ad1843_write_multi stores multiple bitfields into the same AD1843
1016  * register.  It uses one read and one write cycle to do it.
1017  *
1018  * Called like this.
1019  *
1020  *  ad1843_write_multi(lith, nfields,
1021  *                     &ad1843_FIELD1, val1,
1022  *                     &ad1843_FIELF2, val2, ...);
1023  */
1024 
1025 static void ad1843_write_multi(lithium_t *lith, int argcount, ...)
1026 {
1027         va_list ap;
1028         int reg;
1029         const ad1843_bitfield_t *fp;
1030         int value;
1031         int w, m, mask, bits;
1032 
1033         mask = 0;
1034         bits = 0;
1035         reg = -1;
1036 
1037         va_start(ap, argcount);
1038         while (--argcount >= 0) {
1039                 fp = va_arg(ap, const ad1843_bitfield_t *);
1040                 value = va_arg(ap, int);
1041                 if (reg == -1)
1042                         reg = fp->reg;
1043                 ASSERT(fp->reg == reg);
1044                 m = ((1 << fp->nbits) - 1) << fp->lo_bit;
1045                 mask |= m;
1046                 bits |= (value << fp->lo_bit) & m;
1047         }
1048         va_end(ap);
1049         ASSERT(!(bits & ~mask));
1050         if (~mask & 0xFFFF)
1051                 w = li_read_ad1843_reg(lith, reg);
1052         else
1053                 w = 0;
1054         w = (w & ~mask) | bits;
1055         (void) li_write_ad1843_reg(lith, reg, w);
1056 }
1057 
1058 /*
1059  * ad1843_get_gain reads the specified register and extracts the gain value
1060  * using the supplied gain type.  It returns the gain in OSS format.
1061  */
1062 
1063 static int ad1843_get_gain(lithium_t *lith, const ad1843_gain_t *gp)
1064 {
1065         int lg, rg;
1066         unsigned short mask = (1 << gp->lfield->nbits) - 1;
1067 
1068         ad1843_read_multi(lith, 2, gp->lfield, &lg, gp->rfield, &rg);
1069         if (gp->negative) {
1070                 lg = mask - lg;
1071                 rg = mask - rg;
1072         }
1073         lg = (lg * 100 + (mask >> 1)) / mask;
1074         rg = (rg * 100 + (mask >> 1)) / mask;
1075         return lg << 0 | rg << 8;
1076 }
1077 
1078 /*
1079  * Set an audio channel's gain. Converts from OSS format to AD1843's
1080  * format.
1081  *
1082  * Returns the new gain, which may be lower than the old gain.
1083  */
1084 
1085 static int ad1843_set_gain(lithium_t *lith,
1086                            const ad1843_gain_t *gp,
1087                            int newval)
1088 {
1089         unsigned short mask = (1 << gp->lfield->nbits) - 1;
1090 
1091         int lg = newval >> 0 & 0xFF;
1092         int rg = newval >> 8;
1093         if (lg < 0 || lg > 100 || rg < 0 || rg > 100)
1094                 return -EINVAL;
1095         lg = (lg * mask + (mask >> 1)) / 100;
1096         rg = (rg * mask + (mask >> 1)) / 100;
1097         if (gp->negative) {
1098                 lg = mask - lg;
1099                 rg = mask - rg;
1100         }
1101         ad1843_write_multi(lith, 2, gp->lfield, lg, gp->rfield, rg);
1102         return ad1843_get_gain(lith, gp);
1103 }
1104 
1105 /* Returns the current recording source, in OSS format. */
1106 
1107 static int ad1843_get_recsrc(lithium_t *lith)
1108 {
1109         int ls = ad1843_read_bits(lith, &ad1843_LSS);
1110 
1111         switch (ls) {
1112         case 1:
1113                 return SOUND_MASK_MIC;
1114         case 2:
1115                 return SOUND_MASK_LINE;
1116         case 3:
1117                 return SOUND_MASK_CD;
1118         case 6:
1119                 return SOUND_MASK_PCM;
1120         default:
1121                 ASSERT(0);
1122                 return -1;
1123         }
1124 }
1125 
1126 /*
1127  * Enable/disable digital resample mode in the AD1843.
1128  *
1129  * The AD1843 requires that ADL, ADR, DA1 and DA2 be powered down
1130  * while switching modes.  So we save DA1's state (DA2's state is not
1131  * interesting), power them down, switch into/out of resample mode,
1132  * power them up, and restore state.
1133  *
1134  * This will cause audible glitches if D/A or A/D is going on, so the
1135  * driver disallows that (in mixer_write_ioctl()).
1136  *
1137  * The open question is, is this worth doing?  I'm leaving it in,
1138  * because it's written, but...
1139  */
1140 
1141 static void ad1843_set_resample_mode(lithium_t *lith, int onoff)
1142 {
1143         /* Save DA1 mute and gain (addr 9 is DA1 analog gain/attenuation) */
1144         int save_da1 = li_read_ad1843_reg(lith, 9);
1145 
1146         /* Power down A/D and D/A. */
1147         ad1843_write_multi(lith, 4,
1148                            &ad1843_DA1EN, 0,
1149                            &ad1843_DA2EN, 0,
1150                            &ad1843_ADLEN, 0,
1151                            &ad1843_ADREN, 0);
1152 
1153         /* Switch mode */
1154         ASSERT(onoff == 0 || onoff == 1);
1155         ad1843_write_bits(lith, &ad1843_DRSFLT, onoff);
1156 
1157         /* Power up A/D and D/A. */
1158         ad1843_write_multi(lith, 3,
1159                            &ad1843_DA1EN, 1,
1160                            &ad1843_ADLEN, 1,
1161                            &ad1843_ADREN, 1);
1162 
1163         /* Restore DA1 mute and gain. */
1164         li_write_ad1843_reg(lith, 9, save_da1);
1165 }
1166 
1167 /*
1168  * Set recording source.  Arg newsrc specifies an OSS channel mask.
1169  *
1170  * The complication is that when we switch into/out of loopback mode
1171  * (i.e., src = SOUND_MASK_PCM), we change the AD1843 into/out of
1172  * digital resampling mode.
1173  *
1174  * Returns newsrc on success, -errno on failure.
1175  */
1176 
1177 static int ad1843_set_recsrc(lithium_t *lith, int newsrc)
1178 {
1179         int bits;
1180         int oldbits;
1181 
1182         switch (newsrc) {
1183         case SOUND_MASK_PCM:
1184                 bits = 6;
1185                 break;
1186 
1187         case SOUND_MASK_MIC:
1188                 bits = 1;
1189                 break;
1190 
1191         case SOUND_MASK_LINE:
1192                 bits = 2;
1193                 break;
1194 
1195         case SOUND_MASK_CD:
1196                 bits = 3;
1197                 break;
1198 
1199         default:
1200                 return -EINVAL;
1201         }
1202         oldbits = ad1843_read_bits(lith, &ad1843_LSS);
1203         if (newsrc == SOUND_MASK_PCM && oldbits != 6) {
1204                 DBGP("enabling digital resample mode\n");
1205                 ad1843_set_resample_mode(lith, 1);
1206                 ad1843_write_multi(lith, 2,
1207                                    &ad1843_DAADL, 2,
1208                                    &ad1843_DAADR, 2);
1209         } else if (newsrc != SOUND_MASK_PCM && oldbits == 6) {
1210                 DBGP("disabling digital resample mode\n");
1211                 ad1843_set_resample_mode(lith, 0);
1212                 ad1843_write_multi(lith, 2,
1213                                    &ad1843_DAADL, 0,
1214                                    &ad1843_DAADR, 0);
1215         }
1216         ad1843_write_multi(lith, 2, &ad1843_LSS, bits, &ad1843_RSS, bits);
1217         return newsrc;
1218 }
1219 
1220 /*
1221  * Return current output sources, in OSS format.
1222  */
1223 
1224 static int ad1843_get_outsrc(lithium_t *lith)
1225 {
1226         int pcm, line, mic, cd;
1227 
1228         pcm  = ad1843_read_bits(lith, &ad1843_LDA1GM) ? 0 : SOUND_MASK_PCM;
1229         line = ad1843_read_bits(lith, &ad1843_LX1MM)  ? 0 : SOUND_MASK_LINE;
1230         cd   = ad1843_read_bits(lith, &ad1843_LX2MM)  ? 0 : SOUND_MASK_CD;
1231         mic  = ad1843_read_bits(lith, &ad1843_LMCMM)  ? 0 : SOUND_MASK_MIC;
1232 
1233         return pcm | line | cd | mic;
1234 }
1235 
1236 /*
1237  * Set output sources.  Arg is a mask of active sources in OSS format.
1238  *
1239  * Returns source mask on success, -errno on failure.
1240  */
1241 
1242 static int ad1843_set_outsrc(lithium_t *lith, int mask)
1243 {
1244         int pcm, line, mic, cd;
1245 
1246         if (mask & ~(SOUND_MASK_PCM | SOUND_MASK_LINE |
1247                      SOUND_MASK_CD | SOUND_MASK_MIC))
1248                 return -EINVAL;
1249         pcm  = (mask & SOUND_MASK_PCM)  ? 0 : 1;
1250         line = (mask & SOUND_MASK_LINE) ? 0 : 1;
1251         mic  = (mask & SOUND_MASK_MIC)  ? 0 : 1;
1252         cd   = (mask & SOUND_MASK_CD)   ? 0 : 1;
1253 
1254         ad1843_write_multi(lith, 2, &ad1843_LDA1GM, pcm, &ad1843_RDA1GM, pcm);
1255         ad1843_write_multi(lith, 2, &ad1843_LX1MM, line, &ad1843_RX1MM, line);
1256         ad1843_write_multi(lith, 2, &ad1843_LX2MM, cd,   &ad1843_RX2MM, cd);
1257         ad1843_write_multi(lith, 2, &ad1843_LMCMM, mic,  &ad1843_RMCMM, mic);
1258 
1259         return mask;
1260 }
1261 
1262 /* Setup ad1843 for D/A conversion. */
1263 
1264 static void ad1843_setup_dac(lithium_t *lith,
1265                              int framerate,
1266                              int fmt,
1267                              int channels)
1268 {
1269         int ad_fmt = 0, ad_mode = 0;
1270 
1271         DBGEV("(lith=0x%p, framerate=%d, fmt=%d, channels=%d)\n",
1272               lith, framerate, fmt, channels);
1273 
1274         switch (fmt) {
1275         case AFMT_S8:           ad_fmt = 1; break;
1276         case AFMT_U8:           ad_fmt = 1; break;
1277         case AFMT_S16_LE:       ad_fmt = 1; break;
1278         case AFMT_MU_LAW:       ad_fmt = 2; break;
1279         case AFMT_A_LAW:        ad_fmt = 3; break;
1280         default:                ASSERT(0);
1281         }
1282 
1283         switch (channels) {
1284         case 2:                 ad_mode = 0; break;
1285         case 1:                 ad_mode = 1; break;
1286         default:                ASSERT(0);
1287         }
1288                 
1289         DBGPV("ad_mode = %d, ad_fmt = %d\n", ad_mode, ad_fmt);
1290         ASSERT(framerate >= 4000 && framerate <= 49000);
1291         ad1843_write_bits(lith, &ad1843_C1C, framerate);
1292         ad1843_write_multi(lith, 2,
1293                            &ad1843_DA1SM, ad_mode, &ad1843_DA1F, ad_fmt);
1294 }
1295 
1296 static void ad1843_shutdown_dac(lithium_t *lith)
1297 {
1298         ad1843_write_bits(lith, &ad1843_DA1F, 1);
1299 }
1300 
1301 static void ad1843_setup_adc(lithium_t *lith, int framerate, int fmt, int channels)
1302 {
1303         int da_fmt = 0;
1304 
1305         DBGEV("(lith=0x%p, framerate=%d, fmt=%d, channels=%d)\n",
1306               lith, framerate, fmt, channels);
1307 
1308         switch (fmt) {
1309         case AFMT_S8:           da_fmt = 1; break;
1310         case AFMT_U8:           da_fmt = 1; break;
1311         case AFMT_S16_LE:       da_fmt = 1; break;
1312         case AFMT_MU_LAW:       da_fmt = 2; break;
1313         case AFMT_A_LAW:        da_fmt = 3; break;
1314         default:                ASSERT(0);
1315         }
1316 
1317         DBGPV("da_fmt = %d\n", da_fmt);
1318         ASSERT(framerate >= 4000 && framerate <= 49000);
1319         ad1843_write_bits(lith, &ad1843_C2C, framerate);
1320         ad1843_write_multi(lith, 2,
1321                            &ad1843_ADLF, da_fmt, &ad1843_ADRF, da_fmt);
1322 }
1323 
1324 static void ad1843_shutdown_adc(lithium_t *lith)
1325 {
1326         /* nothing to do */
1327 }
1328 
1329 /*
1330  * Fully initialize the ad1843.  As described in the AD1843 data
1331  * sheet, section "START-UP SEQUENCE".  The numbered comments are
1332  * subsection headings from the data sheet.  See the data sheet, pages
1333  * 52-54, for more info.
1334  *
1335  * return 0 on success, -errno on failure.  */
1336 
1337 static int __init ad1843_init(lithium_t *lith)
1338 {
1339         unsigned long later;
1340         int err;
1341 
1342         err = li_init(lith);
1343         if (err)
1344                 return err;
1345 
1346         if (ad1843_read_bits(lith, &ad1843_INIT) != 0) {
1347                 printk(KERN_ERR "vwsnd sound: AD1843 won't initialize\n");
1348                 return -EIO;
1349         }
1350 
1351         ad1843_write_bits(lith, &ad1843_SCF, 1);
1352 
1353         /* 4. Put the conversion resources into standby. */
1354 
1355         ad1843_write_bits(lith, &ad1843_PDNI, 0);
1356         later = jiffies + HZ / 2;       /* roughly half a second */
1357         DBGDO(shut_up++);
1358         while (ad1843_read_bits(lith, &ad1843_PDNO)) {
1359                 if (time_after(jiffies, later)) {
1360                         printk(KERN_ERR
1361                                "vwsnd audio: AD1843 won't power up\n");
1362                         return -EIO;
1363                 }
1364                 schedule();
1365         }
1366         DBGDO(shut_up--);
1367 
1368         /* 5. Power up the clock generators and enable clock output pins. */
1369 
1370         ad1843_write_multi(lith, 2, &ad1843_C1EN, 1, &ad1843_C2EN, 1);
1371 
1372         /* 6. Configure conversion resources while they are in standby. */
1373 
1374         /* DAC1 uses clock 1 as source, ADC uses clock 2.  Always. */
1375 
1376         ad1843_write_multi(lith, 3,
1377                            &ad1843_DA1C, 1,
1378                            &ad1843_ADLC, 2,
1379                            &ad1843_ADRC, 2);
1380 
1381         /* 7. Enable conversion resources. */
1382 
1383         ad1843_write_bits(lith, &ad1843_ADTLK, 1);
1384         ad1843_write_multi(lith, 5,
1385                            &ad1843_ANAEN, 1,
1386                            &ad1843_AAMEN, 1,
1387                            &ad1843_DA1EN, 1,
1388                            &ad1843_ADLEN, 1,
1389                            &ad1843_ADREN, 1);
1390 
1391         /* 8. Configure conversion resources while they are enabled. */
1392 
1393         ad1843_write_bits(lith, &ad1843_DA1C, 1);
1394 
1395         /* Unmute all channels. */
1396 
1397         ad1843_set_outsrc(lith,
1398                           (SOUND_MASK_PCM | SOUND_MASK_LINE |
1399                            SOUND_MASK_MIC | SOUND_MASK_CD));
1400         ad1843_write_multi(lith, 2, &ad1843_LDA1AM, 0, &ad1843_RDA1AM, 0);
1401 
1402         /* Set default recording source to Line In and set
1403          * mic gain to +20 dB.
1404          */
1405 
1406         ad1843_set_recsrc(lith, SOUND_MASK_LINE);
1407         ad1843_write_multi(lith, 2, &ad1843_LMGE, 1, &ad1843_RMGE, 1);
1408 
1409         /* Set Speaker Out level to +/- 4V and unmute it. */
1410 
1411         ad1843_write_multi(lith, 2, &ad1843_HPOS, 1, &ad1843_HPOM, 0);
1412 
1413         return 0;
1414 }
1415 
1416 /*****************************************************************************/
1417 /* PCM I/O */
1418 
1419 #define READ_INTR_MASK  (LI_INTR_COMM1_TRIG | LI_INTR_COMM1_OVERFLOW)
1420 #define WRITE_INTR_MASK (LI_INTR_COMM2_TRIG | LI_INTR_COMM2_UNDERFLOW)
1421 
1422 typedef enum vwsnd_port_swstate {       /* software state */
1423         SW_OFF,
1424         SW_INITIAL,
1425         SW_RUN,
1426         SW_DRAIN,
1427 } vwsnd_port_swstate_t;
1428 
1429 typedef enum vwsnd_port_hwstate {       /* hardware state */
1430         HW_STOPPED,
1431         HW_RUNNING,
1432 } vwsnd_port_hwstate_t;
1433 
1434 /*
1435  * These flags are read by ISR, but only written at baseline.
1436  */
1437 
1438 typedef enum vwsnd_port_flags {
1439         DISABLED = 1 << 0,
1440         ERFLOWN  = 1 << 1,              /* overflown or underflown */
1441         HW_BUSY  = 1 << 2,
1442 } vwsnd_port_flags_t;
1443 
1444 /*
1445  * vwsnd_port is the per-port data structure.  Each device has two
1446  * ports, one for input and one for output.
1447  *
1448  * Locking:
1449  *
1450  *      port->lock protects: hwstate, flags, swb_[iu]_avail.
1451  *
1452  *      devc->io_mutex protects: swstate, sw_*, swb_[iu]_idx.
1453  *
1454  *      everything else is only written by open/release or
1455  *      pcm_{setup,shutdown}(), which are serialized by a
1456  *      combination of devc->open_mutex and devc->io_mutex.
1457  */
1458 
1459 typedef struct vwsnd_port {
1460 
1461         spinlock_t      lock;
1462         wait_queue_head_t queue;
1463         vwsnd_port_swstate_t swstate;
1464         vwsnd_port_hwstate_t hwstate;
1465         vwsnd_port_flags_t flags;
1466 
1467         int             sw_channels;
1468         int             sw_samplefmt;
1469         int             sw_framerate;
1470         int             sample_size;
1471         int             frame_size;
1472         unsigned int    zero_word;      /* zero for the sample format */
1473 
1474         int             sw_fragshift;
1475         int             sw_fragcount;
1476         int             sw_subdivshift;
1477 
1478         unsigned int    hw_fragshift;
1479         unsigned int    hw_fragsize;
1480         unsigned int    hw_fragcount;
1481 
1482         int             hwbuf_size;
1483         unsigned long   hwbuf_paddr;
1484         unsigned long   hwbuf_vaddr;
1485         void *          hwbuf;          /* hwbuf == hwbuf_vaddr */
1486         int             hwbuf_max;      /* max bytes to preload */
1487 
1488         void *          swbuf;
1489         unsigned int    swbuf_size;     /* size in bytes */
1490         unsigned int    swb_u_idx;      /* index of next user byte */
1491         unsigned int    swb_i_idx;      /* index of next intr byte */
1492         unsigned int    swb_u_avail;    /* # bytes avail to user */
1493         unsigned int    swb_i_avail;    /* # bytes avail to intr */
1494 
1495         dma_chan_t      chan;
1496 
1497         /* Accounting */
1498 
1499         int             byte_count;
1500         int             frag_count;
1501         int             MSC_offset;
1502 
1503 } vwsnd_port_t;
1504 
1505 /* vwsnd_dev is the per-device data structure. */
1506 
1507 typedef struct vwsnd_dev {
1508         struct vwsnd_dev *next_dev;
1509         int             audio_minor;    /* minor number of audio device */
1510         int             mixer_minor;    /* minor number of mixer device */
1511 
1512         struct mutex open_mutex;
1513         struct mutex io_mutex;
1514         struct mutex mix_mutex;
1515         fmode_t         open_mode;
1516         wait_queue_head_t open_wait;
1517 
1518         lithium_t       lith;
1519 
1520         vwsnd_port_t    rport;
1521         vwsnd_port_t    wport;
1522 } vwsnd_dev_t;
1523 
1524 static vwsnd_dev_t *vwsnd_dev_list;     /* linked list of all devices */
1525 
1526 static atomic_t vwsnd_use_count = ATOMIC_INIT(0);
1527 
1528 # define INC_USE_COUNT (atomic_inc(&vwsnd_use_count))
1529 # define DEC_USE_COUNT (atomic_dec(&vwsnd_use_count))
1530 # define IN_USE        (atomic_read(&vwsnd_use_count) != 0)
1531 
1532 /*
1533  * Lithium can only DMA multiples of 32 bytes.  Its DMA buffer may
1534  * be up to 8 Kb.  This driver always uses 8 Kb.
1535  *
1536  * Memory bug workaround -- I'm not sure what's going on here, but
1537  * somehow pcm_copy_out() was triggering segv's going on to the next
1538  * page of the hw buffer.  So, I make the hw buffer one size bigger
1539  * than we actually use.  That way, the following page is allocated
1540  * and mapped, and no error.  I suspect that something is broken
1541  * in Cobalt, but haven't really investigated.  HBO is the actual
1542  * size of the buffer, and HWBUF_ORDER is what we allocate.
1543  */
1544 
1545 #define HWBUF_SHIFT 13
1546 #define HWBUF_SIZE (1 << HWBUF_SHIFT)
1547 # define HBO         (HWBUF_SHIFT > PAGE_SHIFT ? HWBUF_SHIFT - PAGE_SHIFT : 0)
1548 # define HWBUF_ORDER (HBO + 1)          /* next size bigger */
1549 #define MIN_SPEED 4000
1550 #define MAX_SPEED 49000
1551 
1552 #define MIN_FRAGSHIFT                   (DMACHUNK_SHIFT + 1)
1553 #define MAX_FRAGSHIFT                   (PAGE_SHIFT)
1554 #define MIN_FRAGSIZE                    (1 << MIN_FRAGSHIFT)
1555 #define MAX_FRAGSIZE                    (1 << MAX_FRAGSHIFT)
1556 #define MIN_FRAGCOUNT(fragsize)         3
1557 #define MAX_FRAGCOUNT(fragsize)         (32 * PAGE_SIZE / (fragsize))
1558 #define DEFAULT_FRAGSHIFT               12
1559 #define DEFAULT_FRAGCOUNT               16
1560 #define DEFAULT_SUBDIVSHIFT             0
1561 
1562 /*
1563  * The software buffer (swbuf) is a ring buffer shared between user
1564  * level and interrupt level.  Each level owns some of the bytes in
1565  * the buffer, and may give bytes away by calling swb_inc_{u,i}().
1566  * User level calls _u for user, and interrupt level calls _i for
1567  * interrupt.
1568  *
1569  * port->swb_{u,i}_avail is the number of bytes available to that level.
1570  *
1571  * port->swb_{u,i}_idx is the index of the first available byte in the
1572  * buffer.
1573  *
1574  * Each level calls swb_inc_{u,i}() to atomically increment its index,
1575  * recalculate the number of bytes available for both sides, and
1576  * return the number of bytes available.  Since each side can only
1577  * give away bytes, the other side can only increase the number of
1578  * bytes available to this side.  Each side updates its own index
1579  * variable, swb_{u,i}_idx, so no lock is needed to read it.
1580  *
1581  * To query the number of bytes available, call swb_inc_{u,i} with an
1582  * increment of zero.
1583  */
1584 
1585 static __inline__ unsigned int __swb_inc_u(vwsnd_port_t *port, int inc)
1586 {
1587         if (inc) {
1588                 port->swb_u_idx += inc;
1589                 port->swb_u_idx %= port->swbuf_size;
1590                 port->swb_u_avail -= inc;
1591                 port->swb_i_avail += inc;
1592         }
1593         return port->swb_u_avail;
1594 }
1595 
1596 static __inline__ unsigned int swb_inc_u(vwsnd_port_t *port, int inc)
1597 {
1598         unsigned long flags;
1599         unsigned int ret;
1600 
1601         spin_lock_irqsave(&port->lock, flags);
1602         {
1603                 ret = __swb_inc_u(port, inc);
1604         }
1605         spin_unlock_irqrestore(&port->lock, flags);
1606         return ret;
1607 }
1608 
1609 static __inline__ unsigned int __swb_inc_i(vwsnd_port_t *port, int inc)
1610 {
1611         if (inc) {
1612                 port->swb_i_idx += inc;
1613                 port->swb_i_idx %= port->swbuf_size;
1614                 port->swb_i_avail -= inc;
1615                 port->swb_u_avail += inc;
1616         }
1617         return port->swb_i_avail;
1618 }
1619 
1620 static __inline__ unsigned int swb_inc_i(vwsnd_port_t *port, int inc)
1621 {
1622         unsigned long flags;
1623         unsigned int ret;
1624 
1625         spin_lock_irqsave(&port->lock, flags);
1626         {
1627                 ret = __swb_inc_i(port, inc);
1628         }
1629         spin_unlock_irqrestore(&port->lock, flags);
1630         return ret;
1631 }
1632 
1633 /*
1634  * pcm_setup - this routine initializes all port state after
1635  * mode-setting ioctls have been done, but before the first I/O is
1636  * done.
1637  *
1638  * Locking: called with devc->io_mutex held.
1639  *
1640  * Returns 0 on success, -errno on failure.
1641  */
1642 
1643 static int pcm_setup(vwsnd_dev_t *devc,
1644                      vwsnd_port_t *rport,
1645                      vwsnd_port_t *wport)
1646 {
1647         vwsnd_port_t *aport = rport ? rport : wport;
1648         int sample_size;
1649         unsigned int zero_word;
1650 
1651         DBGEV("(devc=0x%p, rport=0x%p, wport=0x%p)\n", devc, rport, wport);
1652 
1653         ASSERT(aport != NULL);
1654         if (aport->swbuf != NULL)
1655                 return 0;
1656         switch (aport->sw_samplefmt) {
1657         case AFMT_MU_LAW:
1658                 sample_size = 1;
1659                 zero_word = 0xFFFFFFFF ^ 0x80808080;
1660                 break;
1661 
1662         case AFMT_A_LAW:
1663                 sample_size = 1;
1664                 zero_word = 0xD5D5D5D5 ^ 0x80808080;
1665                 break;
1666 
1667         case AFMT_U8:
1668                 sample_size = 1;
1669                 zero_word = 0x80808080;
1670                 break;
1671 
1672         case AFMT_S8:
1673                 sample_size = 1;
1674                 zero_word = 0x00000000;
1675                 break;
1676 
1677         case AFMT_S16_LE:
1678                 sample_size = 2;
1679                 zero_word = 0x00000000;
1680                 break;
1681 
1682         default:
1683                 sample_size = 0;        /* prevent compiler warning */
1684                 zero_word = 0;
1685                 ASSERT(0);
1686         }
1687         aport->sample_size  = sample_size;
1688         aport->zero_word    = zero_word;
1689         aport->frame_size   = aport->sw_channels * aport->sample_size;
1690         aport->hw_fragshift = aport->sw_fragshift - aport->sw_subdivshift;
1691         aport->hw_fragsize  = 1 << aport->hw_fragshift;
1692         aport->hw_fragcount = aport->sw_fragcount << aport->sw_subdivshift;
1693         ASSERT(aport->hw_fragsize >= MIN_FRAGSIZE);
1694         ASSERT(aport->hw_fragsize <= MAX_FRAGSIZE);
1695         ASSERT(aport->hw_fragcount >= MIN_FRAGCOUNT(aport->hw_fragsize));
1696         ASSERT(aport->hw_fragcount <= MAX_FRAGCOUNT(aport->hw_fragsize));
1697         if (rport) {
1698                 int hwfrags, swfrags;
1699                 rport->hwbuf_max = aport->hwbuf_size - DMACHUNK_SIZE;
1700                 hwfrags = rport->hwbuf_max >> aport->hw_fragshift;
1701                 swfrags = aport->hw_fragcount - hwfrags;
1702                 if (swfrags < 2)
1703                         swfrags = 2;
1704                 rport->swbuf_size = swfrags * aport->hw_fragsize;
1705                 DBGPV("hwfrags = %d, swfrags = %d\n", hwfrags, swfrags);
1706                 DBGPV("read hwbuf_max = %d, swbuf_size = %d\n",
1707                      rport->hwbuf_max, rport->swbuf_size);
1708         }
1709         if (wport) {
1710                 int hwfrags, swfrags;
1711                 int total_bytes = aport->hw_fragcount * aport->hw_fragsize;
1712                 wport->hwbuf_max = aport->hwbuf_size - DMACHUNK_SIZE;
1713                 if (wport->hwbuf_max > total_bytes)
1714                         wport->hwbuf_max = total_bytes;
1715                 hwfrags = wport->hwbuf_max >> aport->hw_fragshift;
1716                 DBGPV("hwfrags = %d\n", hwfrags);
1717                 swfrags = aport->hw_fragcount - hwfrags;
1718                 if (swfrags < 2)
1719                         swfrags = 2;
1720                 wport->swbuf_size = swfrags * aport->hw_fragsize;
1721                 DBGPV("hwfrags = %d, swfrags = %d\n", hwfrags, swfrags);
1722                 DBGPV("write hwbuf_max = %d, swbuf_size = %d\n",
1723                      wport->hwbuf_max, wport->swbuf_size);
1724         }
1725 
1726         aport->swb_u_idx    = 0;
1727         aport->swb_i_idx    = 0;
1728         aport->byte_count   = 0;
1729 
1730         /*
1731          * Is this a Cobalt bug?  We need to make this buffer extend
1732          * one page further than we actually use -- somehow memcpy
1733          * causes an exceptoin otherwise.  I suspect there's a bug in
1734          * Cobalt (or somewhere) where it's generating a fault on a
1735          * speculative load or something.  Obviously, I haven't taken
1736          * the time to track it down.
1737          */
1738 
1739         aport->swbuf        = vmalloc(aport->swbuf_size + PAGE_SIZE);
1740         if (!aport->swbuf)
1741                 return -ENOMEM;
1742         if (rport && wport) {
1743                 ASSERT(aport == rport);
1744                 ASSERT(wport->swbuf == NULL);
1745                 /* One extra page - see comment above. */
1746                 wport->swbuf = vmalloc(aport->swbuf_size + PAGE_SIZE);
1747                 if (!wport->swbuf) {
1748                         vfree(aport->swbuf);
1749                         aport->swbuf = NULL;
1750                         return -ENOMEM;
1751                 }
1752                 wport->sample_size  = rport->sample_size;
1753                 wport->zero_word    = rport->zero_word;
1754                 wport->frame_size   = rport->frame_size;
1755                 wport->hw_fragshift = rport->hw_fragshift;
1756                 wport->hw_fragsize  = rport->hw_fragsize;
1757                 wport->hw_fragcount = rport->hw_fragcount;
1758                 wport->swbuf_size   = rport->swbuf_size;
1759                 wport->hwbuf_max    = rport->hwbuf_max;
1760                 wport->swb_u_idx    = rport->swb_u_idx;
1761                 wport->swb_i_idx    = rport->swb_i_idx;
1762                 wport->byte_count   = rport->byte_count;
1763         }
1764         if (rport) {
1765                 rport->swb_u_avail = 0;
1766                 rport->swb_i_avail = rport->swbuf_size;
1767                 rport->swstate = SW_RUN;
1768                 li_setup_dma(&rport->chan,
1769                              &li_comm1,
1770                              &devc->lith,
1771                              rport->hwbuf_paddr,
1772                              HWBUF_SHIFT,
1773                              rport->hw_fragshift,
1774                              rport->sw_channels,
1775                              rport->sample_size);
1776                 ad1843_setup_adc(&devc->lith,
1777                                  rport->sw_framerate,
1778                                  rport->sw_samplefmt,
1779                                  rport->sw_channels);
1780                 li_enable_interrupts(&devc->lith, READ_INTR_MASK);
1781                 if (!(rport->flags & DISABLED)) {
1782                         ustmsc_t ustmsc;
1783                         rport->hwstate = HW_RUNNING;
1784                         li_activate_dma(&rport->chan);
1785                         li_read_USTMSC(&rport->chan, &ustmsc);
1786                         rport->MSC_offset = ustmsc.msc;
1787                 }
1788         }
1789         if (wport) {
1790                 if (wport->hwbuf_max > wport->swbuf_size)
1791                         wport->hwbuf_max = wport->swbuf_size;
1792                 wport->flags &= ~ERFLOWN;
1793                 wport->swb_u_avail = wport->swbuf_size;
1794                 wport->swb_i_avail = 0;
1795                 wport->swstate = SW_RUN;
1796                 li_setup_dma(&wport->chan,
1797                              &li_comm2,
1798                              &devc->lith,
1799                              wport->hwbuf_paddr,
1800                              HWBUF_SHIFT,
1801                              wport->hw_fragshift,
1802                              wport->sw_channels,
1803                              wport->sample_size);
1804                 ad1843_setup_dac(&devc->lith,
1805                                  wport->sw_framerate,
1806                                  wport->sw_samplefmt,
1807                                  wport->sw_channels);
1808                 li_enable_interrupts(&devc->lith, WRITE_INTR_MASK);
1809         }
1810         DBGRV();
1811         return 0;
1812 }
1813 
1814 /*
1815  * pcm_shutdown_port - shut down one port (direction) for PCM I/O.
1816  * Only called from pcm_shutdown.
1817  */
1818 
1819 static void pcm_shutdown_port(vwsnd_dev_t *devc,
1820                               vwsnd_port_t *aport,
1821                               unsigned int mask)
1822 {
1823         unsigned long flags;
1824         vwsnd_port_hwstate_t hwstate;
1825         DECLARE_WAITQUEUE(wait, current);
1826 
1827         aport->swstate = SW_INITIAL;
1828         add_wait_queue(&aport->queue, &wait);
1829         while (1) {
1830                 set_current_state(TASK_UNINTERRUPTIBLE);
1831                 spin_lock_irqsave(&aport->lock, flags);
1832                 {
1833                         hwstate = aport->hwstate;
1834                 }               
1835                 spin_unlock_irqrestore(&aport->lock, flags);
1836                 if (hwstate == HW_STOPPED)
1837                         break;
1838                 schedule();
1839         }
1840         current->state = TASK_RUNNING;
1841         remove_wait_queue(&aport->queue, &wait);
1842         li_disable_interrupts(&devc->lith, mask);
1843         if (aport == &devc->rport)
1844                 ad1843_shutdown_adc(&devc->lith);
1845         else /* aport == &devc->wport) */
1846                 ad1843_shutdown_dac(&devc->lith);
1847         li_shutdown_dma(&aport->chan);
1848         vfree(aport->swbuf);
1849         aport->swbuf = NULL;
1850         aport->byte_count = 0;
1851 }
1852 
1853 /*
1854  * pcm_shutdown undoes what pcm_setup did.
1855  * Also sets the ports' swstate to newstate.
1856  */
1857 
1858 static void pcm_shutdown(vwsnd_dev_t *devc,
1859                          vwsnd_port_t *rport,
1860                          vwsnd_port_t *wport)
1861 {
1862         DBGEV("(devc=0x%p, rport=0x%p, wport=0x%p)\n", devc, rport, wport);
1863 
1864         if (rport && rport->swbuf) {
1865                 DBGPV("shutting down rport\n");
1866                 pcm_shutdown_port(devc, rport, READ_INTR_MASK);
1867         }
1868         if (wport && wport->swbuf) {
1869                 DBGPV("shutting down wport\n");
1870                 pcm_shutdown_port(devc, wport, WRITE_INTR_MASK);
1871         }
1872         DBGRV();
1873 }
1874 
1875 static void pcm_copy_in(vwsnd_port_t *rport, int swidx, int hwidx, int nb)
1876 {
1877         char *src = rport->hwbuf + hwidx;
1878         char *dst = rport->swbuf + swidx;
1879         int fmt = rport->sw_samplefmt;
1880 
1881         DBGPV("swidx = %d, hwidx = %d\n", swidx, hwidx);
1882         ASSERT(rport->hwbuf != NULL);
1883         ASSERT(rport->swbuf != NULL);
1884         ASSERT(nb > 0 && (nb % 32) == 0);
1885         ASSERT(swidx % 32 == 0 && hwidx % 32 == 0);
1886         ASSERT(swidx >= 0 && swidx + nb <= rport->swbuf_size);
1887         ASSERT(hwidx >= 0 && hwidx + nb <= rport->hwbuf_size);
1888 
1889         if (fmt == AFMT_MU_LAW || fmt == AFMT_A_LAW || fmt == AFMT_S8) {
1890 
1891                 /* See Sample Format Notes above. */
1892 
1893                 char *end = src + nb;
1894                 while (src < end)
1895                         *dst++ = *src++ ^ 0x80;
1896         } else
1897                 memcpy(dst, src, nb);
1898 }
1899 
1900 static void pcm_copy_out(vwsnd_port_t *wport, int swidx, int hwidx, int nb)
1901 {
1902         char *src = wport->swbuf + swidx;
1903         char *dst = wport->hwbuf + hwidx;
1904         int fmt = wport->sw_samplefmt;
1905 
1906         ASSERT(nb > 0 && (nb % 32) == 0);
1907         ASSERT(wport->hwbuf != NULL);
1908         ASSERT(wport->swbuf != NULL);
1909         ASSERT(swidx % 32 == 0 && hwidx % 32 == 0);
1910         ASSERT(swidx >= 0 && swidx + nb <= wport->swbuf_size);
1911         ASSERT(hwidx >= 0 && hwidx + nb <= wport->hwbuf_size);
1912         if (fmt == AFMT_MU_LAW || fmt == AFMT_A_LAW || fmt == AFMT_S8) {
1913 
1914                 /* See Sample Format Notes above. */
1915 
1916                 char *end = src + nb;
1917                 while (src < end)
1918                         *dst++ = *src++ ^ 0x80;
1919         } else
1920                 memcpy(dst, src, nb);
1921 }
1922 
1923 /*
1924  * pcm_output() is called both from baselevel and from interrupt level.
1925  * This is where audio frames are copied into the hardware-accessible
1926  * ring buffer.
1927  *
1928  * Locking note: The part of this routine that figures out what to do
1929  * holds wport->lock.  The longer part releases wport->lock, but sets
1930  * wport->flags & HW_BUSY.  Afterward, it reacquires wport->lock, and
1931  * checks for more work to do.
1932  *
1933  * If another thread calls pcm_output() while HW_BUSY is set, it
1934  * returns immediately, knowing that the thread that set HW_BUSY will
1935  * look for more work to do before returning.
1936  *
1937  * This has the advantage that port->lock is held for several short
1938  * periods instead of one long period.  Also, when pcm_output is
1939  * called from base level, it reenables interrupts.
1940  */
1941 
1942 static void pcm_output(vwsnd_dev_t *devc, int erflown, int nb)
1943 {
1944         vwsnd_port_t *wport = &devc->wport;
1945         const int hwmax  = wport->hwbuf_max;
1946         const int hwsize = wport->hwbuf_size;
1947         const int swsize = wport->swbuf_size;
1948         const int fragsize = wport->hw_fragsize;
1949         unsigned long iflags;
1950 
1951         DBGEV("(devc=0x%p, erflown=%d, nb=%d)\n", devc, erflown, nb);
1952         spin_lock_irqsave(&wport->lock, iflags);
1953         if (erflown)
1954                 wport->flags |= ERFLOWN;
1955         (void) __swb_inc_u(wport, nb);
1956         if (wport->flags & HW_BUSY) {
1957                 spin_unlock_irqrestore(&wport->lock, iflags);
1958                 DBGPV("returning: HW BUSY\n");
1959                 return;
1960         }
1961         if (wport->flags & DISABLED) {
1962                 spin_unlock_irqrestore(&wport->lock, iflags);
1963                 DBGPV("returning: DISABLED\n");
1964                 return;
1965         }
1966         wport->flags |= HW_BUSY;
1967         while (1) {
1968                 int swptr, hwptr, hw_avail, sw_avail, swidx;
1969                 vwsnd_port_hwstate_t hwstate = wport->hwstate;
1970                 vwsnd_port_swstate_t swstate = wport->swstate;
1971                 int hw_unavail;
1972                 ustmsc_t ustmsc;
1973 
1974                 hwptr = li_read_hwptr(&wport->chan);
1975                 swptr = li_read_swptr(&wport->chan);
1976                 hw_unavail = (swptr - hwptr + hwsize) % hwsize;
1977                 hw_avail = (hwmax - hw_unavail) & -fragsize;
1978                 sw_avail = wport->swb_i_avail & -fragsize;
1979                 if (sw_avail && swstate == SW_RUN) {
1980                         if (wport->flags & ERFLOWN) {
1981                                 wport->flags &= ~ERFLOWN;
1982                         }
1983                 } else if (swstate == SW_INITIAL ||
1984                          swstate == SW_OFF ||
1985                          (swstate == SW_DRAIN &&
1986                           !sw_avail &&
1987                           (wport->flags & ERFLOWN))) {
1988                         DBGP("stopping.  hwstate = %d\n", hwstate);
1989                         if (hwstate != HW_STOPPED) {
1990                                 li_deactivate_dma(&wport->chan);
1991                                 wport->hwstate = HW_STOPPED;
1992                         }
1993                         wake_up(&wport->queue);
1994                         break;
1995                 }
1996                 if (!sw_avail || !hw_avail)
1997                         break;
1998                 spin_unlock_irqrestore(&wport->lock, iflags);
1999 
2000                 /*
2001                  * We gave up the port lock, but we have the HW_BUSY flag.
2002                  * Proceed without accessing any nonlocal state.
2003                  * Do not exit the loop -- must check for more work.
2004                  */
2005 
2006                 swidx = wport->swb_i_idx;
2007                 nb = hw_avail;
2008                 if (nb > sw_avail)
2009                         nb = sw_avail;
2010                 if (nb > hwsize - swptr)
2011                         nb = hwsize - swptr; /* don't overflow hwbuf */
2012                 if (nb > swsize - swidx)
2013                         nb = swsize - swidx; /* don't overflow swbuf */
2014                 ASSERT(nb > 0);
2015                 if (nb % fragsize) {
2016                         DBGP("nb = %d, fragsize = %d\n", nb, fragsize);
2017                         DBGP("hw_avail = %d\n", hw_avail);
2018                         DBGP("sw_avail = %d\n", sw_avail);
2019                         DBGP("hwsize = %d, swptr = %d\n", hwsize, swptr);
2020                         DBGP("swsize = %d, swidx = %d\n", swsize, swidx);
2021                 }
2022                 ASSERT(!(nb % fragsize));
2023                 DBGPV("copying swb[%d..%d] to hwb[%d..%d]\n",
2024                       swidx, swidx + nb, swptr, swptr + nb);
2025                 pcm_copy_out(wport, swidx, swptr, nb);
2026                 li_write_swptr(&wport->chan, (swptr + nb) % hwsize);
2027                 spin_lock_irqsave(&wport->lock, iflags);
2028                 if (hwstate == HW_STOPPED) {
2029                         DBGPV("starting\n");
2030                         li_activate_dma(&wport->chan);
2031                         wport->hwstate = HW_RUNNING;
2032                         li_read_USTMSC(&wport->chan, &ustmsc);
2033                         ASSERT(wport->byte_count % wport->frame_size == 0);
2034                         wport->MSC_offset = ustmsc.msc - wport->byte_count / wport->frame_size;
2035                 }
2036                 __swb_inc_i(wport, nb);
2037                 wport->byte_count += nb;
2038                 wport->frag_count += nb / fragsize;
2039                 ASSERT(nb % fragsize == 0);
2040                 wake_up(&wport->queue);
2041         }
2042         wport->flags &= ~HW_BUSY;
2043         spin_unlock_irqrestore(&wport->lock, iflags);
2044         DBGRV();
2045 }
2046 
2047 /*
2048  * pcm_input() is called both from baselevel and from interrupt level.
2049  * This is where audio frames are copied out of the hardware-accessible
2050  * ring buffer.
2051  *
2052  * Locking note: The part of this routine that figures out what to do
2053  * holds rport->lock.  The longer part releases rport->lock, but sets
2054  * rport->flags & HW_BUSY.  Afterward, it reacquires rport->lock, and
2055  * checks for more work to do.
2056  *
2057  * If another thread calls pcm_input() while HW_BUSY is set, it
2058  * returns immediately, knowing that the thread that set HW_BUSY will
2059  * look for more work to do before returning.
2060  *
2061  * This has the advantage that port->lock is held for several short
2062  * periods instead of one long period.  Also, when pcm_input is
2063  * called from base level, it reenables interrupts.
2064  */
2065 
2066 static void pcm_input(vwsnd_dev_t *devc, int erflown, int nb)
2067 {
2068         vwsnd_port_t *rport = &devc->rport;
2069         const int hwmax  = rport->hwbuf_max;
2070         const int hwsize = rport->hwbuf_size;
2071         const int swsize = rport->swbuf_size;
2072         const int fragsize = rport->hw_fragsize;
2073         unsigned long iflags;
2074 
2075         DBGEV("(devc=0x%p, erflown=%d, nb=%d)\n", devc, erflown, nb);
2076 
2077         spin_lock_irqsave(&rport->lock, iflags);
2078         if (erflown)
2079                 rport->flags |= ERFLOWN;
2080         (void) __swb_inc_u(rport, nb);
2081         if (rport->flags & HW_BUSY || !rport->swbuf) {
2082                 spin_unlock_irqrestore(&rport->lock, iflags);
2083                 DBGPV("returning: HW BUSY or !swbuf\n");
2084                 return;
2085         }
2086         if (rport->flags & DISABLED) {
2087                 spin_unlock_irqrestore(&rport->lock, iflags);
2088                 DBGPV("returning: DISABLED\n");
2089                 return;
2090         }
2091         rport->flags |= HW_BUSY;
2092         while (1) {
2093                 int swptr, hwptr, hw_avail, sw_avail, swidx;
2094                 vwsnd_port_hwstate_t hwstate = rport->hwstate;
2095                 vwsnd_port_swstate_t swstate = rport->swstate;
2096 
2097                 hwptr = li_read_hwptr(&rport->chan);
2098                 swptr = li_read_swptr(&rport->chan);
2099                 hw_avail = (hwptr - swptr + hwsize) % hwsize & -fragsize;
2100                 if (hw_avail > hwmax)
2101                         hw_avail = hwmax;
2102                 sw_avail = rport->swb_i_avail & -fragsize;
2103                 if (swstate != SW_RUN) {
2104                         DBGP("stopping.  hwstate = %d\n", hwstate);
2105                         if (hwstate != HW_STOPPED) {
2106                                 li_deactivate_dma(&rport->chan);
2107                                 rport->hwstate = HW_STOPPED;
2108                         }
2109                         wake_up(&rport->queue);
2110                         break;
2111                 }
2112                 if (!sw_avail || !hw_avail)
2113                         break;
2114                 spin_unlock_irqrestore(&rport->lock, iflags);
2115 
2116                 /*
2117                  * We gave up the port lock, but we have the HW_BUSY flag.
2118                  * Proceed without accessing any nonlocal state.
2119                  * Do not exit the loop -- must check for more work.
2120                  */
2121 
2122                 swidx = rport->swb_i_idx;
2123                 nb = hw_avail;
2124                 if (nb > sw_avail)
2125                         nb = sw_avail;
2126                 if (nb > hwsize - swptr)
2127                         nb = hwsize - swptr; /* don't overflow hwbuf */
2128                 if (nb > swsize - swidx)
2129                         nb = swsize - swidx; /* don't overflow swbuf */
2130                 ASSERT(nb > 0);
2131                 if (nb % fragsize) {
2132                         DBGP("nb = %d, fragsize = %d\n", nb, fragsize);
2133                         DBGP("hw_avail = %d\n", hw_avail);
2134                         DBGP("sw_avail = %d\n", sw_avail);
2135                         DBGP("hwsize = %d, swptr = %d\n", hwsize, swptr);
2136                         DBGP("swsize = %d, swidx = %d\n", swsize, swidx);
2137                 }
2138                 ASSERT(!(nb % fragsize));
2139                 DBGPV("copying hwb[%d..%d] to swb[%d..%d]\n",
2140                       swptr, swptr + nb, swidx, swidx + nb);
2141                 pcm_copy_in(rport, swidx, swptr, nb);
2142                 li_write_swptr(&rport->chan, (swptr + nb) % hwsize);
2143                 spin_lock_irqsave(&rport->lock, iflags);
2144                 __swb_inc_i(rport, nb);
2145                 rport->byte_count += nb;
2146                 rport->frag_count += nb / fragsize;
2147                 ASSERT(nb % fragsize == 0);
2148                 wake_up(&rport->queue);
2149         }
2150         rport->flags &= ~HW_BUSY;
2151         spin_unlock_irqrestore(&rport->lock, iflags);
2152         DBGRV();
2153 }
2154 
2155 /*
2156  * pcm_flush_frag() writes zero samples to fill the current fragment,
2157  * then flushes it to the hardware.
2158  *
2159  * It is only meaningful to flush output, not input.
2160  */
2161 
2162 static void pcm_flush_frag(vwsnd_dev_t *devc)
2163 {
2164         vwsnd_port_t *wport = &devc->wport;
2165 
2166         DBGPV("swstate = %d\n", wport->swstate);
2167         if (wport->swstate == SW_RUN) {
2168                 int idx = wport->swb_u_idx;
2169                 int end = (idx + wport->hw_fragsize - 1)
2170                         >> wport->hw_fragshift
2171                         << wport->hw_fragshift;
2172                 int nb = end - idx;
2173                 DBGPV("clearing %d bytes\n", nb);
2174                 if (nb)
2175                         memset(wport->swbuf + idx,
2176                                (char) wport->zero_word,
2177                                nb);
2178                 wport->swstate = SW_DRAIN;
2179                 pcm_output(devc, 0, nb);
2180         }
2181         DBGRV();
2182 }
2183 
2184 /*
2185  * Wait for output to drain.  This sleeps uninterruptibly because
2186  * there is nothing intelligent we can do if interrupted.  This
2187  * means the process will be delayed in responding to the signal.
2188  */
2189 
2190 static void pcm_write_sync(vwsnd_dev_t *devc)
2191 {
2192         vwsnd_port_t *wport = &devc->wport;
2193         DECLARE_WAITQUEUE(wait, current);
2194         unsigned long flags;
2195         vwsnd_port_hwstate_t hwstate;
2196 
2197         DBGEV("(devc=0x%p)\n", devc);
2198         add_wait_queue(&wport->queue, &wait);
2199         while (1) {
2200                 set_current_state(TASK_UNINTERRUPTIBLE);
2201                 spin_lock_irqsave(&wport->lock, flags);
2202                 {
2203                         hwstate = wport->hwstate;
2204                 }
2205                 spin_unlock_irqrestore(&wport->lock, flags);
2206                 if (hwstate == HW_STOPPED)
2207                         break;
2208                 schedule();
2209         }
2210         current->state = TASK_RUNNING;
2211         remove_wait_queue(&wport->queue, &wait);
2212         DBGPV("swstate = %d, hwstate = %d\n", wport->swstate, wport->hwstate);
2213         DBGRV();
2214 }
2215 
2216 /*****************************************************************************/
2217 /* audio driver */
2218 
2219 /*
2220  * seek on an audio device always fails.
2221  */
2222 
2223 static void vwsnd_audio_read_intr(vwsnd_dev_t *devc, unsigned int status)
2224 {
2225         int overflown = status & LI_INTR_COMM1_OVERFLOW;
2226 
2227         if (status & READ_INTR_MASK)
2228                 pcm_input(devc, overflown, 0);
2229 }
2230 
2231 static void vwsnd_audio_write_intr(vwsnd_dev_t *devc, unsigned int status)
2232 {
2233         int underflown = status & LI_INTR_COMM2_UNDERFLOW;
2234 
2235         if (status & WRITE_INTR_MASK)
2236                 pcm_output(devc, underflown, 0);
2237 }
2238 
2239 static irqreturn_t vwsnd_audio_intr(int irq, void *dev_id)
2240 {
2241         vwsnd_dev_t *devc = dev_id;
2242         unsigned int status;
2243 
2244         DBGEV("(irq=%d, dev_id=0x%p)\n", irq, dev_id);
2245 
2246         status = li_get_clear_intr_status(&devc->lith);
2247         vwsnd_audio_read_intr(devc, status);
2248         vwsnd_audio_write_intr(devc, status);
2249         return IRQ_HANDLED;
2250 }
2251 
2252 static ssize_t vwsnd_audio_do_read(struct file *file,
2253                                    char *buffer,
2254                                    size_t count,
2255                                    loff_t *ppos)
2256 {
2257         vwsnd_dev_t *devc = file->private_data;
2258         vwsnd_port_t *rport = ((file->f_mode & FMODE_READ) ?
2259                                &devc->rport : NULL);
2260         int ret, nb;
2261 
2262         DBGEV("(file=0x%p, buffer=0x%p, count=%d, ppos=0x%p)\n",
2263              file, buffer, count, ppos);
2264 
2265         if (!rport)
2266                 return -EINVAL;
2267 
2268         if (rport->swbuf == NULL) {
2269                 vwsnd_port_t *wport = (file->f_mode & FMODE_WRITE) ?
2270                         &devc->wport : NULL;
2271                 ret = pcm_setup(devc, rport, wport);
2272                 if (ret < 0)
2273                         return ret;
2274         }
2275 
2276         if (!access_ok(VERIFY_READ, buffer, count))
2277                 return -EFAULT;
2278         ret = 0;
2279         while (count) {
2280                 DECLARE_WAITQUEUE(wait, current);
2281                 add_wait_queue(&rport->queue, &wait);
2282                 while ((nb = swb_inc_u(rport, 0)) == 0) {
2283                         DBGPV("blocking\n");
2284                         set_current_state(TASK_INTERRUPTIBLE);
2285                         if (rport->flags & DISABLED ||
2286                             file->f_flags & O_NONBLOCK) {
2287                                 current->state = TASK_RUNNING;
2288                                 remove_wait_queue(&rport->queue, &wait);
2289                                 return ret ? ret : -EAGAIN;
2290                         }
2291                         schedule();
2292                         if (signal_pending(current)) {
2293                                 current->state = TASK_RUNNING;
2294                                 remove_wait_queue(&rport->queue, &wait);
2295                                 return ret ? ret : -ERESTARTSYS;
2296                         }
2297                 }
2298                 current->state = TASK_RUNNING;
2299                 remove_wait_queue(&rport->queue, &wait);
2300                 pcm_input(devc, 0, 0);
2301                 /* nb bytes are available in userbuf. */
2302                 if (nb > count)
2303                         nb = count;
2304                 DBGPV("nb = %d\n", nb);
2305                 if (copy_to_user(buffer, rport->swbuf + rport->swb_u_idx, nb))
2306                         return -EFAULT;
2307                 (void) swb_inc_u(rport, nb);
2308                 buffer += nb;
2309                 count -= nb;
2310                 ret += nb;
2311         }
2312         DBGPV("returning %d\n", ret);
2313         return ret;
2314 }
2315 
2316 static ssize_t vwsnd_audio_read(struct file *file,
2317                                 char *buffer,
2318                                 size_t count,
2319                                 loff_t *ppos)
2320 {
2321         vwsnd_dev_t *devc = file->private_data;
2322         ssize_t ret;
2323 
2324         mutex_lock(&devc->io_mutex);
2325         ret = vwsnd_audio_do_read(file, buffer, count, ppos);
2326         mutex_unlock(&devc->io_mutex);
2327         return ret;
2328 }
2329 
2330 static ssize_t vwsnd_audio_do_write(struct file *file,
2331                                     const char *buffer,
2332                                     size_t count,
2333                                     loff_t *ppos)
2334 {
2335         vwsnd_dev_t *devc = file->private_data;
2336         vwsnd_port_t *wport = ((file->f_mode & FMODE_WRITE) ?
2337                                &devc->wport : NULL);
2338         int ret, nb;
2339 
2340         DBGEV("(file=0x%p, buffer=0x%p, count=%d, ppos=0x%p)\n",
2341               file, buffer, count, ppos);
2342 
2343         if (!wport)
2344                 return -EINVAL;
2345 
2346         if (wport->swbuf == NULL) {
2347                 vwsnd_port_t *rport = (file->f_mode & FMODE_READ) ?
2348                         &devc->rport : NULL;
2349                 ret = pcm_setup(devc, rport, wport);
2350                 if (ret < 0)
2351                         return ret;
2352         }
2353         if (!access_ok(VERIFY_WRITE, buffer, count))
2354                 return -EFAULT;
2355         ret = 0;
2356         while (count) {
2357                 DECLARE_WAITQUEUE(wait, current);
2358                 add_wait_queue(&wport->queue, &wait);
2359                 while ((nb = swb_inc_u(wport, 0)) == 0) {
2360                         set_current_state(TASK_INTERRUPTIBLE);
2361                         if (wport->flags & DISABLED ||
2362                             file->f_flags & O_NONBLOCK) {
2363                                 current->state = TASK_RUNNING;
2364                                 remove_wait_queue(&wport->queue, &wait);
2365                                 return ret ? ret : -EAGAIN;
2366                         }
2367                         schedule();
2368                         if (signal_pending(current)) {
2369                                 current->state = TASK_RUNNING;
2370                                 remove_wait_queue(&wport->queue, &wait);
2371                                 return ret ? ret : -ERESTARTSYS;
2372                         }
2373                 }
2374                 current->state = TASK_RUNNING;
2375                 remove_wait_queue(&wport->queue, &wait);
2376                 /* nb bytes are available in userbuf. */
2377                 if (nb > count)
2378                         nb = count;
2379                 DBGPV("nb = %d\n", nb);
2380                 if (copy_from_user(wport->swbuf + wport->swb_u_idx, buffer, nb))
2381                         return -EFAULT;
2382                 pcm_output(devc, 0, nb);
2383                 buffer += nb;
2384                 count -= nb;
2385                 ret += nb;
2386         }
2387         DBGPV("returning %d\n", ret);
2388         return ret;
2389 }
2390 
2391 static ssize_t vwsnd_audio_write(struct file *file,
2392                                  const char *buffer,
2393                                  size_t count,
2394                                  loff_t *ppos)
2395 {
2396         vwsnd_dev_t *devc = file->private_data;
2397         ssize_t ret;
2398 
2399         mutex_lock(&devc->io_mutex);
2400         ret = vwsnd_audio_do_write(file, buffer, count, ppos);
2401         mutex_unlock(&devc->io_mutex);
2402         return ret;
2403 }
2404 
2405 /* No kernel lock - fine */
2406 static unsigned int vwsnd_audio_poll(struct file *file,
2407                                      struct poll_table_struct *wait)
2408 {
2409         vwsnd_dev_t *devc = (vwsnd_dev_t *) file->private_data;
2410         vwsnd_port_t *rport = (file->f_mode & FMODE_READ) ?
2411                 &devc->rport : NULL;
2412         vwsnd_port_t *wport = (file->f_mode & FMODE_WRITE) ?
2413                 &devc->wport : NULL;
2414         unsigned int mask = 0;
2415 
2416         DBGEV("(file=0x%p, wait=0x%p)\n", file, wait);
2417 
2418         ASSERT(rport || wport);
2419         if (rport) {
2420                 poll_wait(file, &rport->queue, wait);
2421                 if (swb_inc_u(rport, 0))
2422                         mask |= (POLLIN | POLLRDNORM);
2423         }
2424         if (wport) {
2425                 poll_wait(file, &wport->queue, wait);
2426                 if (wport->swbuf == NULL || swb_inc_u(wport, 0))
2427                         mask |= (POLLOUT | POLLWRNORM);
2428         }
2429 
2430         DBGPV("returning 0x%x\n", mask);
2431         return mask;
2432 }
2433 
2434 static int vwsnd_audio_do_ioctl(struct file *file,
2435                                 unsigned int cmd,
2436                                 unsigned long arg)
2437 {
2438         vwsnd_dev_t *devc = (vwsnd_dev_t *) file->private_data;
2439         vwsnd_port_t *rport = (file->f_mode & FMODE_READ) ?
2440                 &devc->rport : NULL;
2441         vwsnd_port_t *wport = (file->f_mode & FMODE_WRITE) ?
2442                 &devc->wport : NULL;
2443         vwsnd_port_t *aport = rport ? rport : wport;
2444         struct audio_buf_info buf_info;
2445         struct count_info info;
2446         unsigned long flags;
2447         int ival;
2448 
2449         
2450         DBGEV("(file=0x%p, cmd=0x%x, arg=0x%lx)\n",
2451               file, cmd, arg);
2452         switch (cmd) {
2453         case OSS_GETVERSION:            /* _SIOR ('M', 118, int) */
2454                 DBGX("OSS_GETVERSION\n");
2455                 ival = SOUND_VERSION;
2456                 return put_user(ival, (int *) arg);
2457 
2458         case SNDCTL_DSP_GETCAPS:        /* _SIOR ('P',15, int) */
2459                 DBGX("SNDCTL_DSP_GETCAPS\n");
2460                 ival = DSP_CAP_DUPLEX | DSP_CAP_REALTIME | DSP_CAP_TRIGGER;
2461                 return put_user(ival, (int *) arg);
2462 
2463         case SNDCTL_DSP_GETFMTS:        /* _SIOR ('P',11, int) */
2464                 DBGX("SNDCTL_DSP_GETFMTS\n");
2465                 ival = (AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW |
2466                         AFMT_U8 | AFMT_S8);
2467                 return put_user(ival, (int *) arg);
2468                 break;
2469 
2470         case SOUND_PCM_READ_RATE:       /* _SIOR ('P', 2, int) */
2471                 DBGX("SOUND_PCM_READ_RATE\n");
2472                 ival = aport->sw_framerate;
2473                 return put_user(ival, (int *) arg);
2474 
2475         case SOUND_PCM_READ_CHANNELS:   /* _SIOR ('P', 6, int) */
2476                 DBGX("SOUND_PCM_READ_CHANNELS\n");
2477                 ival = aport->sw_channels;
2478                 return put_user(ival, (int *) arg);
2479 
2480         case SNDCTL_DSP_SPEED:          /* _SIOWR('P', 2, int) */
2481                 if (get_user(ival, (int *) arg))
2482                         return -EFAULT;
2483                 DBGX("SNDCTL_DSP_SPEED %d\n", ival);
2484                 if (ival) {
2485                         if (aport->swstate != SW_INITIAL) {
2486                                 DBGX("SNDCTL_DSP_SPEED failed: swstate = %d\n",
2487                                      aport->swstate);
2488                                 return -EINVAL;
2489                         }
2490                         if (ival < MIN_SPEED)
2491                                 ival = MIN_SPEED;
2492                         if (ival > MAX_SPEED)
2493                                 ival = MAX_SPEED;
2494                         if (rport)
2495                                 rport->sw_framerate = ival;
2496                         if (wport)
2497                                 wport->sw_framerate = ival;
2498                 } else
2499                         ival = aport->sw_framerate;
2500                 return put_user(ival, (int *) arg);
2501 
2502         case SNDCTL_DSP_STEREO:         /* _SIOWR('P', 3, int) */
2503                 if (get_user(ival, (int *) arg))
2504                         return -EFAULT;
2505                 DBGX("SNDCTL_DSP_STEREO %d\n", ival);
2506                 if (ival != 0 && ival != 1)
2507                         return -EINVAL;
2508                 if (aport->swstate != SW_INITIAL)
2509                         return -EINVAL;
2510                 if (rport)
2511                         rport->sw_channels = ival + 1;
2512                 if (wport)
2513                         wport->sw_channels = ival + 1;
2514                 return put_user(ival, (int *) arg);
2515 
2516         case SNDCTL_DSP_CHANNELS:       /* _SIOWR('P', 6, int) */
2517                 if (get_user(ival, (int *) arg))
2518                         return -EFAULT;
2519                 DBGX("SNDCTL_DSP_CHANNELS %d\n", ival);
2520                 if (ival != 1 && ival != 2)
2521                         return -EINVAL;
2522                 if (aport->swstate != SW_INITIAL)
2523                         return -EINVAL;
2524                 if (rport)
2525                         rport->sw_channels = ival;
2526                 if (wport)
2527                         wport->sw_channels = ival;
2528                 return put_user(ival, (int *) arg);
2529 
2530         case SNDCTL_DSP_GETBLKSIZE:     /* _SIOWR('P', 4, int) */
2531                 ival = pcm_setup(devc, rport, wport);
2532                 if (ival < 0) {
2533                         DBGX("SNDCTL_DSP_GETBLKSIZE failed, errno %d\n", ival);
2534                         return ival;
2535                 }
2536                 ival = 1 << aport->sw_fragshift;
2537                 DBGX("SNDCTL_DSP_GETBLKSIZE returning %d\n", ival);
2538                 return put_user(ival, (int *) arg);
2539 
2540         case SNDCTL_DSP_SETFRAGMENT:    /* _SIOWR('P',10, int) */
2541                 if (get_user(ival, (int *) arg))
2542                         return -EFAULT;
2543                 DBGX("SNDCTL_DSP_SETFRAGMENT %d:%d\n",
2544                      ival >> 16, ival & 0xFFFF);
2545                 if (aport->swstate != SW_INITIAL)
2546                         return -EINVAL;
2547                 {
2548                         int sw_fragshift = ival & 0xFFFF;
2549                         int sw_subdivshift = aport->sw_subdivshift;
2550                         int hw_fragshift = sw_fragshift - sw_subdivshift;
2551                         int sw_fragcount = (ival >> 16) & 0xFFFF;
2552                         int hw_fragsize;
2553                         if (hw_fragshift < MIN_FRAGSHIFT)
2554                                 hw_fragshift = MIN_FRAGSHIFT;
2555                         if (hw_fragshift > MAX_FRAGSHIFT)
2556                                 hw_fragshift = MAX_FRAGSHIFT;
2557                         sw_fragshift = hw_fragshift + aport->sw_subdivshift;
2558                         hw_fragsize = 1 << hw_fragshift;
2559                         if (sw_fragcount < MIN_FRAGCOUNT(hw_fragsize))
2560                                 sw_fragcount = MIN_FRAGCOUNT(hw_fragsize);
2561                         if (sw_fragcount > MAX_FRAGCOUNT(hw_fragsize))
2562                                 sw_fragcount = MAX_FRAGCOUNT(hw_fragsize);
2563                         DBGPV("sw_fragshift = %d\n", sw_fragshift);
2564                         DBGPV("rport = 0x%p, wport = 0x%p\n", rport, wport);
2565                         if (rport) {
2566                                 rport->sw_fragshift = sw_fragshift;
2567                                 rport->sw_fragcount = sw_fragcount;
2568                         }
2569                         if (wport) {
2570                                 wport->sw_fragshift = sw_fragshift;
2571                                 wport->sw_fragcount = sw_fragcount;
2572                         }
2573                         ival = sw_fragcount << 16 | sw_fragshift;
2574                 }
2575                 DBGX("SNDCTL_DSP_SETFRAGMENT returns %d:%d\n",
2576                       ival >> 16, ival & 0xFFFF);
2577                 return put_user(ival, (int *) arg);
2578 
2579         case SNDCTL_DSP_SUBDIVIDE:      /* _SIOWR('P', 9, int) */
2580                 if (get_user(ival, (int *) arg))
2581                         return -EFAULT;
2582                 DBGX("SNDCTL_DSP_SUBDIVIDE %d\n", ival);
2583                 if (aport->swstate != SW_INITIAL)
2584                         return -EINVAL;
2585                 {
2586                         int subdivshift;
2587                         int hw_fragshift, hw_fragsize, hw_fragcount;
2588                         switch (ival) {
2589                         case 1: subdivshift = 0; break;
2590                         case 2: subdivshift = 1; break;
2591                         case 4: subdivshift = 2; break;
2592                         default: return -EINVAL;
2593                         }
2594                         hw_fragshift = aport->sw_fragshift - subdivshift;
2595                         if (hw_fragshift < MIN_FRAGSHIFT ||
2596                             hw_fragshift > MAX_FRAGSHIFT)
2597                                 return -EINVAL;
2598                         hw_fragsize = 1 << hw_fragshift;
2599                         hw_fragcount = aport->sw_fragcount >> subdivshift;
2600                         if (hw_fragcount < MIN_FRAGCOUNT(hw_fragsize) ||
2601                             hw_fragcount > MAX_FRAGCOUNT(hw_fragsize))
2602                                 return -EINVAL;
2603                         if (rport)
2604                                 rport->sw_subdivshift = subdivshift;
2605                         if (wport)
2606                                 wport->sw_subdivshift = subdivshift;
2607                 }
2608                 return 0;
2609 
2610         case SNDCTL_DSP_SETFMT:         /* _SIOWR('P',5, int) */
2611                 if (get_user(ival, (int *) arg))
2612                         return -EFAULT;
2613                 DBGX("SNDCTL_DSP_SETFMT %d\n", ival);
2614                 if (ival != AFMT_QUERY) {
2615                         if (aport->swstate != SW_INITIAL) {
2616                                 DBGP("SETFMT failed, swstate = %d\n",
2617                                      aport->swstate);
2618                                 return -EINVAL;
2619                         }
2620                         switch (ival) {
2621                         case AFMT_MU_LAW:
2622                         case AFMT_A_LAW:
2623                         case AFMT_U8:
2624                         case AFMT_S8:
2625                         case AFMT_S16_LE:
2626                                 if (rport)
2627                                         rport->sw_samplefmt = ival;
2628                                 if (wport)
2629                                         wport->sw_samplefmt = ival;
2630                                 break;
2631                         default:
2632                                 return -EINVAL;
2633                         }
2634                 }
2635                 ival = aport->sw_samplefmt;
2636                 return put_user(ival, (int *) arg);
2637 
2638         case SNDCTL_DSP_GETOSPACE:      /* _SIOR ('P',12, audio_buf_info) */
2639                 DBGXV("SNDCTL_DSP_GETOSPACE\n");
2640                 if (!wport)
2641                         return -EINVAL;
2642                 ival = pcm_setup(devc, rport, wport);
2643                 if (ival < 0)
2644                         return ival;
2645                 ival = swb_inc_u(wport, 0);
2646                 buf_info.fragments = ival >> wport->sw_fragshift;
2647                 buf_info.fragstotal = wport->sw_fragcount;
2648                 buf_info.fragsize = 1 << wport->sw_fragshift;
2649                 buf_info.bytes = ival;
2650                 DBGXV("SNDCTL_DSP_GETOSPACE returns { %d %d %d %d }\n",
2651                      buf_info.fragments, buf_info.fragstotal,
2652                      buf_info.fragsize, buf_info.bytes);
2653                 if (copy_to_user((void *) arg, &buf_info, sizeof buf_info))
2654                         return -EFAULT;
2655                 return 0;
2656 
2657         case SNDCTL_DSP_GETISPACE:      /* _SIOR ('P',13, audio_buf_info) */
2658                 DBGX("SNDCTL_DSP_GETISPACE\n");
2659                 if (!rport)
2660                         return -EINVAL;
2661                 ival = pcm_setup(devc, rport, wport);
2662                 if (ival < 0)
2663                         return ival;
2664                 ival = swb_inc_u(rport, 0);
2665                 buf_info.fragments = ival >> rport->sw_fragshift;
2666                 buf_info.fragstotal = rport->sw_fragcount;
2667                 buf_info.fragsize = 1 << rport->sw_fragshift;
2668                 buf_info.bytes = ival;
2669                 DBGX("SNDCTL_DSP_GETISPACE returns { %d %d %d %d }\n",
2670                      buf_info.fragments, buf_info.fragstotal,
2671                      buf_info.fragsize, buf_info.bytes);
2672                 if (copy_to_user((void *) arg, &buf_info, sizeof buf_info))
2673                         return -EFAULT;
2674                 return 0;
2675 
2676         case SNDCTL_DSP_NONBLOCK:       /* _SIO  ('P',14) */
2677                 DBGX("SNDCTL_DSP_NONBLOCK\n");
2678                 spin_lock(&file->f_lock);
2679                 file->f_flags |= O_NONBLOCK;
2680                 spin_unlock(&file->f_lock);
2681                 return 0;
2682 
2683         case SNDCTL_DSP_RESET:          /* _SIO  ('P', 0) */
2684                 DBGX("SNDCTL_DSP_RESET\n");
2685                 /*
2686                  * Nothing special needs to be done for input.  Input
2687                  * samples sit in swbuf, but it will be reinitialized
2688                  * to empty when pcm_setup() is called.
2689                  */
2690                 if (wport && wport->swbuf) {
2691                         wport->swstate = SW_INITIAL;
2692                         pcm_output(devc, 0, 0);
2693                         pcm_write_sync(devc);
2694                 }
2695                 pcm_shutdown(devc, rport, wport);
2696                 return 0;
2697 
2698         case SNDCTL_DSP_SYNC:           /* _SIO  ('P', 1) */
2699                 DBGX("SNDCTL_DSP_SYNC\n");
2700                 if (wport) {
2701                         pcm_flush_frag(devc);
2702                         pcm_write_sync(devc);
2703                 }
2704                 pcm_shutdown(devc, rport, wport);
2705                 return 0;
2706 
2707         case SNDCTL_DSP_POST:           /* _SIO  ('P', 8) */
2708                 DBGX("SNDCTL_DSP_POST\n");
2709                 if (!wport)
2710                         return -EINVAL;
2711                 pcm_flush_frag(devc);
2712                 return 0;
2713 
2714         case SNDCTL_DSP_GETIPTR:        /* _SIOR ('P', 17, count_info) */
2715                 DBGX("SNDCTL_DSP_GETIPTR\n");
2716                 if (!rport)
2717                         return -EINVAL;
2718                 spin_lock_irqsave(&rport->lock, flags);
2719                 {
2720                         ustmsc_t ustmsc;
2721                         if (rport->hwstate == HW_RUNNING) {
2722                                 ASSERT(rport->swstate == SW_RUN);
2723                                 li_read_USTMSC(&rport->chan, &ustmsc);
2724                                 info.bytes = ustmsc.msc - rport->MSC_offset;
2725                                 info.bytes *= rport->frame_size;
2726                         } else {
2727                                 info.bytes = rport->byte_count;
2728                         }
2729                         info.blocks = rport->frag_count;
2730                         info.ptr = 0;   /* not implemented */
2731                         rport->frag_count = 0;
2732                 }
2733                 spin_unlock_irqrestore(&rport->lock, flags);
2734                 if (copy_to_user((void *) arg, &info, sizeof info))
2735                         return -EFAULT;
2736                 return 0;
2737 
2738         case SNDCTL_DSP_GETOPTR:        /* _SIOR ('P',18, count_info) */
2739                 DBGX("SNDCTL_DSP_GETOPTR\n");
2740                 if (!wport)
2741                         return -EINVAL;
2742                 spin_lock_irqsave(&wport->lock, flags);
2743                 {
2744                         ustmsc_t ustmsc;
2745                         if (wport->hwstate == HW_RUNNING) {
2746                                 ASSERT(wport->swstate == SW_RUN);
2747                                 li_read_USTMSC(&wport->chan, &ustmsc);
2748                                 info.bytes = ustmsc.msc - wport->MSC_offset;
2749                                 info.bytes *= wport->frame_size;
2750                         } else {
2751                                 info.bytes = wport->byte_count;
2752                         }
2753                         info.blocks = wport->frag_count;
2754                         info.ptr = 0;   /* not implemented */
2755                         wport->frag_count = 0;
2756                 }
2757                 spin_unlock_irqrestore(&wport->lock, flags);
2758                 if (copy_to_user((void *) arg, &info, sizeof info))
2759                         return -EFAULT;
2760                 return 0;
2761 
2762         case SNDCTL_DSP_GETODELAY:      /* _SIOR ('P', 23, int) */
2763                 DBGX("SNDCTL_DSP_GETODELAY\n");
2764                 if (!wport)
2765                         return -EINVAL;
2766                 spin_lock_irqsave(&wport->lock, flags);
2767                 {
2768                         int fsize = wport->frame_size;
2769                         ival = wport->swb_i_avail / fsize;
2770                         if (wport->hwstate == HW_RUNNING) {
2771                                 int swptr, hwptr, hwframes, hwbytes, hwsize;
2772                                 int totalhwbytes;
2773                                 ustmsc_t ustmsc;
2774 
2775                                 hwsize = wport->hwbuf_size;
2776                                 swptr = li_read_swptr(&wport->chan);
2777                                 li_read_USTMSC(&wport->chan, &ustmsc);
2778                                 hwframes = ustmsc.msc - wport->MSC_offset;
2779                                 totalhwbytes = hwframes * fsize;
2780                                 hwptr = totalhwbytes % hwsize;
2781                                 hwbytes = (swptr - hwptr + hwsize) % hwsize;
2782                                 ival += hwbytes / fsize;
2783                         }
2784                 }
2785                 spin_unlock_irqrestore(&wport->lock, flags);
2786                 return put_user(ival, (int *) arg);
2787 
2788         case SNDCTL_DSP_PROFILE:        /* _SIOW ('P', 23, int) */
2789                 DBGX("SNDCTL_DSP_PROFILE\n");
2790 
2791                 /*
2792                  * Thomas Sailer explains SNDCTL_DSP_PROFILE
2793                  * (private email, March 24, 1999):
2794                  *
2795                  *     This gives the sound driver a hint on what it
2796                  *     should do with partial fragments
2797                  *     (i.e. fragments partially filled with write).
2798                  *     This can direct the driver to zero them or
2799                  *     leave them alone.  But don't ask me what this
2800                  *     is good for, my driver just zeroes the last
2801                  *     fragment before the receiver stops, no idea
2802                  *     what good for any other behaviour could
2803                  *     be. Implementing it as NOP seems safe.
2804                  */
2805 
2806                 break;
2807 
2808         case SNDCTL_DSP_GETTRIGGER:     /* _SIOR ('P',16, int) */
2809                 DBGX("SNDCTL_DSP_GETTRIGGER\n");
2810                 ival = 0;
2811                 if (rport) {
2812                         spin_lock_irqsave(&rport->lock, flags);
2813                         {
2814                                 if (!(rport->flags & DISABLED))
2815                                         ival |= PCM_ENABLE_INPUT;
2816                         }
2817                         spin_unlock_irqrestore(&rport->lock, flags);
2818                 }
2819                 if (wport) {
2820                         spin_lock_irqsave(&wport->lock, flags);
2821                         {
2822                                 if (!(wport->flags & DISABLED))
2823                                         ival |= PCM_ENABLE_OUTPUT;
2824                         }
2825                         spin_unlock_irqrestore(&wport->lock, flags);
2826                 }
2827                 return put_user(ival, (int *) arg);
2828 
2829         case SNDCTL_DSP_SETTRIGGER:     /* _SIOW ('P',16, int) */
2830                 if (get_user(ival, (int *) arg))
2831                         return -EFAULT;
2832                 DBGX("SNDCTL_DSP_SETTRIGGER %d\n", ival);
2833 
2834                 /*
2835                  * If user is disabling I/O and port is not in initial
2836                  * state, fail with EINVAL.
2837                  */
2838 
2839                 if (((rport && !(ival & PCM_ENABLE_INPUT)) ||
2840                      (wport && !(ival & PCM_ENABLE_OUTPUT))) &&
2841                     aport->swstate != SW_INITIAL)
2842                         return -EINVAL;
2843 
2844                 if (rport) {
2845                         vwsnd_port_hwstate_t hwstate;
2846                         spin_lock_irqsave(&rport->lock, flags);
2847                         {
2848                                 hwstate = rport->hwstate;
2849                                 if (ival & PCM_ENABLE_INPUT)
2850                                         rport->flags &= ~DISABLED;
2851                                 else
2852                                         rport->flags |= DISABLED;
2853                         }
2854                         spin_unlock_irqrestore(&rport->lock, flags);
2855                         if (hwstate != HW_RUNNING && ival & PCM_ENABLE_INPUT) {
2856 
2857                                 if (rport->swstate == SW_INITIAL)
2858                                         pcm_setup(devc, rport, wport);
2859                                 else
2860                                         li_activate_dma(&rport->chan);
2861                         }
2862                 }
2863                 if (wport) {
2864                         vwsnd_port_flags_t pflags;
2865                         spin_lock_irqsave(&wport->lock, flags);
2866                         {
2867                                 pflags = wport->flags;
2868                                 if (ival & PCM_ENABLE_OUTPUT)
2869                                         wport->flags &= ~DISABLED;
2870                                 else
2871                                         wport->flags |= DISABLED;
2872                         }
2873                         spin_unlock_irqrestore(&wport->lock, flags);
2874                         if (pflags & DISABLED && ival & PCM_ENABLE_OUTPUT) {
2875                                 if (wport->swstate == SW_RUN)
2876                                         pcm_output(devc, 0, 0);
2877                         }
2878                 }
2879                 return 0;
2880 
2881         default:
2882                 DBGP("unknown ioctl 0x%x\n", cmd);
2883                 return -EINVAL;
2884         }
2885         DBGP("unimplemented ioctl 0x%x\n", cmd);
2886         return -EINVAL;
2887 }
2888 
2889 static long vwsnd_audio_ioctl(struct file *file,
2890                                 unsigned int cmd,
2891                                 unsigned long arg)
2892 {
2893         vwsnd_dev_t *devc = (vwsnd_dev_t *) file->private_data;
2894         int ret;
2895 
2896         mutex_lock(&vwsnd_mutex);
2897         mutex_lock(&devc->io_mutex);
2898         ret = vwsnd_audio_do_ioctl(file, cmd, arg);
2899         mutex_unlock(&devc->io_mutex);
2900         mutex_unlock(&vwsnd_mutex);
2901 
2902         return ret;
2903 }
2904 
2905 /* No mmap. */
2906 
2907 static int vwsnd_audio_mmap(struct file *file, struct vm_area_struct *vma)
2908 {
2909         DBGE("(file=0x%p, vma=0x%p)\n", file, vma);
2910         return -ENODEV;
2911 }
2912 
2913 /*
2914  * Open the audio device for read and/or write.
2915  *
2916  * Returns 0 on success, -errno on failure.
2917  */
2918 
2919 static int vwsnd_audio_open(struct inode *inode, struct file *file)
2920 {
2921         vwsnd_dev_t *devc;
2922         int minor = iminor(inode);
2923         int sw_samplefmt;
2924 
2925         DBGE("(inode=0x%p, file=0x%p)\n", inode, file);
2926 
2927         mutex_lock(&vwsnd_mutex);
2928         INC_USE_COUNT;
2929         for (devc = vwsnd_dev_list; devc; devc = devc->next_dev)
2930                 if ((devc->audio_minor & ~0x0F) == (minor & ~0x0F))
2931                         break;
2932 
2933         if (devc == NULL) {
2934                 DEC_USE_COUNT;
2935                 mutex_unlock(&vwsnd_mutex);
2936                 return -ENODEV;
2937         }
2938 
2939         mutex_lock(&devc->open_mutex);
2940         while (devc->open_mode & file->f_mode) {
2941                 mutex_unlock(&devc->open_mutex);
2942                 if (file->f_flags & O_NONBLOCK) {
2943                         DEC_USE_COUNT;
2944                         mutex_unlock(&vwsnd_mutex);
2945                         return -EBUSY;
2946                 }
2947                 interruptible_sleep_on(&devc->open_wait);
2948                 if (signal_pending(current)) {
2949                         DEC_USE_COUNT;
2950                         mutex_unlock(&vwsnd_mutex);
2951                         return -ERESTARTSYS;
2952                 }
2953                 mutex_lock(&devc->open_mutex);
2954         }
2955         devc->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
2956         mutex_unlock(&devc->open_mutex);
2957 
2958         /* get default sample format from minor number. */
2959 
2960         sw_samplefmt = 0;
2961         if ((minor & 0xF) == SND_DEV_DSP)
2962                 sw_samplefmt = AFMT_U8;
2963         else if ((minor & 0xF) == SND_DEV_AUDIO)
2964                 sw_samplefmt = AFMT_MU_LAW;
2965         else if ((minor & 0xF) == SND_DEV_DSP16)
2966                 sw_samplefmt = AFMT_S16_LE;
2967         else
2968                 ASSERT(0);
2969 
2970         /* Initialize vwsnd_ports. */
2971 
2972         mutex_lock(&devc->io_mutex);
2973         {
2974                 if (file->f_mode & FMODE_READ) {
2975                         devc->rport.swstate        = SW_INITIAL;
2976                         devc->rport.flags          = 0;
2977                         devc->rport.sw_channels    = 1;
2978                         devc->rport.sw_samplefmt   = sw_samplefmt;
2979                         devc->rport.sw_framerate   = 8000;
2980                         devc->rport.sw_fragshift   = DEFAULT_FRAGSHIFT;
2981                         devc->rport.sw_fragcount   = DEFAULT_FRAGCOUNT;
2982                         devc->rport.sw_subdivshift = DEFAULT_SUBDIVSHIFT;
2983                         devc->rport.byte_count     = 0;
2984                         devc->rport.frag_count     = 0;
2985                 }
2986                 if (file->f_mode & FMODE_WRITE) {
2987                         devc->wport.swstate        = SW_INITIAL;
2988                         devc->wport.flags          = 0;
2989                         devc->wport.sw_channels    = 1;
2990                         devc->wport.sw_samplefmt   = sw_samplefmt;
2991                         devc->wport.sw_framerate   = 8000;
2992                         devc->wport.sw_fragshift   = DEFAULT_FRAGSHIFT;
2993                         devc->wport.sw_fragcount   = DEFAULT_FRAGCOUNT;
2994                         devc->wport.sw_subdivshift = DEFAULT_SUBDIVSHIFT;
2995                         devc->wport.byte_count     = 0;
2996                         devc->wport.frag_count     = 0;
2997                 }
2998         }
2999         mutex_unlock(&devc->io_mutex);
3000 
3001         file->private_data = devc;
3002         DBGRV();
3003         mutex_unlock(&vwsnd_mutex);
3004         return 0;
3005 }
3006 
3007 /*
3008  * Release (close) the audio device.
3009  */
3010 
3011 static int vwsnd_audio_release(struct inode *inode, struct file *file)
3012 {
3013         vwsnd_dev_t *devc = (vwsnd_dev_t *) file->private_data;
3014         vwsnd_port_t *wport = NULL, *rport = NULL;
3015         int err = 0;
3016 
3017         mutex_lock(&vwsnd_mutex);
3018         mutex_lock(&devc->io_mutex);
3019         {
3020                 DBGEV("(inode=0x%p, file=0x%p)\n", inode, file);
3021 
3022                 if (file->f_mode & FMODE_READ)
3023                         rport = &devc->rport;
3024                 if (file->f_mode & FMODE_WRITE) {
3025                         wport = &devc->wport;
3026                         pcm_flush_frag(devc);
3027                         pcm_write_sync(devc);
3028                 }
3029                 pcm_shutdown(devc, rport, wport);
3030                 if (rport)
3031                         rport->swstate = SW_OFF;
3032                 if (wport)
3033                         wport->swstate = SW_OFF;
3034         }
3035         mutex_unlock(&devc->io_mutex);
3036 
3037         mutex_lock(&devc->open_mutex);
3038         {
3039                 devc->open_mode &= ~file->f_mode;
3040         }
3041         mutex_unlock(&devc->open_mutex);
3042         wake_up(&devc->open_wait);
3043         DEC_USE_COUNT;
3044         DBGR();
3045         mutex_unlock(&vwsnd_mutex);
3046         return err;
3047 }
3048 
3049 static const struct file_operations vwsnd_audio_fops = {
3050         .owner =        THIS_MODULE,
3051         .llseek =       no_llseek,
3052         .read =         vwsnd_audio_read,
3053         .write =        vwsnd_audio_write,
3054         .poll =         vwsnd_audio_poll,
3055         .unlocked_ioctl = vwsnd_audio_ioctl,
3056         .mmap =         vwsnd_audio_mmap,
3057         .open =         vwsnd_audio_open,
3058         .release =      vwsnd_audio_release,
3059 };
3060 
3061 /*****************************************************************************/
3062 /* mixer driver */
3063 
3064 /* open the mixer device. */
3065 
3066 static int vwsnd_mixer_open(struct inode *inode, struct file *file)
3067 {
3068         vwsnd_dev_t *devc;
3069 
3070         DBGEV("(inode=0x%p, file=0x%p)\n", inode, file);
3071 
3072         INC_USE_COUNT;
3073         mutex_lock(&vwsnd_mutex);
3074         for (devc = vwsnd_dev_list; devc; devc = devc->next_dev)
3075                 if (devc->mixer_minor == iminor(inode))
3076                         break;
3077 
3078         if (devc == NULL) {
3079                 DEC_USE_COUNT;
3080                 mutex_unlock(&vwsnd_mutex);
3081                 return -ENODEV;
3082         }
3083         file->private_data = devc;
3084         mutex_unlock(&vwsnd_mutex);
3085         return 0;
3086 }
3087 
3088 /* release (close) the mixer device. */
3089 
3090 static int vwsnd_mixer_release(struct inode *inode, struct file *file)
3091 {
3092         DBGEV("(inode=0x%p, file=0x%p)\n", inode, file);
3093         DEC_USE_COUNT;
3094         return 0;
3095 }
3096 
3097 /* mixer_read_ioctl handles all read ioctls on the mixer device. */
3098 
3099 static int mixer_read_ioctl(vwsnd_dev_t *devc, unsigned int nr, void __user *arg)
3100 {
3101         int val = -1;
3102 
3103         DBGEV("(devc=0x%p, nr=0x%x, arg=0x%p)\n", devc, nr, arg);
3104 
3105         switch (nr) {
3106         case SOUND_MIXER_CAPS:
3107                 val = SOUND_CAP_EXCL_INPUT;
3108                 break;
3109 
3110         case SOUND_MIXER_DEVMASK:
3111                 val = (SOUND_MASK_PCM | SOUND_MASK_LINE |
3112                        SOUND_MASK_MIC | SOUND_MASK_CD | SOUND_MASK_RECLEV);
3113                 break;
3114 
3115         case SOUND_MIXER_STEREODEVS:
3116                 val = (SOUND_MASK_PCM | SOUND_MASK_LINE |
3117                        SOUND_MASK_MIC | SOUND_MASK_CD | SOUND_MASK_RECLEV);
3118                 break;
3119 
3120         case SOUND_MIXER_OUTMASK:
3121                 val = (SOUND_MASK_PCM | SOUND_MASK_LINE |
3122                        SOUND_MASK_MIC | SOUND_MASK_CD);
3123                 break;
3124 
3125         case SOUND_MIXER_RECMASK:
3126                 val = (SOUND_MASK_PCM | SOUND_MASK_LINE |
3127                        SOUND_MASK_MIC | SOUND_MASK_CD);
3128                 break;
3129 
3130         case SOUND_MIXER_PCM:
3131                 val = ad1843_get_gain(&devc->lith, &ad1843_gain_PCM);
3132                 break;
3133 
3134         case SOUND_MIXER_LINE:
3135                 val = ad1843_get_gain(&devc->lith, &ad1843_gain_LINE);
3136                 break;
3137 
3138         case SOUND_MIXER_MIC:
3139                 val = ad1843_get_gain(&devc->lith, &ad1843_gain_MIC);
3140                 break;
3141 
3142         case SOUND_MIXER_CD:
3143                 val = ad1843_get_gain(&devc->lith, &ad1843_gain_CD);
3144                 break;
3145 
3146         case SOUND_MIXER_RECLEV:
3147                 val = ad1843_get_gain(&devc->lith, &ad1843_gain_RECLEV);
3148                 break;
3149 
3150         case SOUND_MIXER_RECSRC:
3151                 val = ad1843_get_recsrc(&devc->lith);
3152                 break;
3153 
3154         case SOUND_MIXER_OUTSRC:
3155                 val = ad1843_get_outsrc(&devc->lith);
3156                 break;
3157 
3158         default:
3159                 return -EINVAL;
3160         }
3161         return put_user(val, (int __user *) arg);
3162 }
3163 
3164 /* mixer_write_ioctl handles all write ioctls on the mixer device. */
3165 
3166 static int mixer_write_ioctl(vwsnd_dev_t *devc, unsigned int nr, void __user *arg)
3167 {
3168         int val;
3169         int err;
3170 
3171         DBGEV("(devc=0x%p, nr=0x%x, arg=0x%p)\n", devc, nr, arg);
3172 
3173         err = get_user(val, (int __user *) arg);
3174         if (err)
3175                 return -EFAULT;
3176         switch (nr) {
3177         case SOUND_MIXER_PCM:
3178                 val = ad1843_set_gain(&devc->lith, &ad1843_gain_PCM, val);
3179                 break;
3180 
3181         case SOUND_MIXER_LINE:
3182                 val = ad1843_set_gain(&devc->lith, &ad1843_gain_LINE, val);
3183                 break;
3184 
3185         case SOUND_MIXER_MIC:
3186                 val = ad1843_set_gain(&devc->lith, &ad1843_gain_MIC, val);
3187                 break;
3188 
3189         case SOUND_MIXER_CD:
3190                 val = ad1843_set_gain(&devc->lith, &ad1843_gain_CD, val);
3191                 break;
3192 
3193         case SOUND_MIXER_RECLEV:
3194                 val = ad1843_set_gain(&devc->lith, &ad1843_gain_RECLEV, val);
3195                 break;
3196 
3197         case SOUND_MIXER_RECSRC:
3198                 if (devc->rport.swbuf || devc->wport.swbuf)
3199                         return -EBUSY;  /* can't change recsrc while running */
3200                 val = ad1843_set_recsrc(&devc->lith, val);
3201                 break;
3202 
3203         case SOUND_MIXER_OUTSRC:
3204                 val = ad1843_set_outsrc(&devc->lith, val);
3205                 break;
3206 
3207         default:
3208                 return -EINVAL;
3209         }
3210         if (val < 0)
3211                 return val;
3212         return put_user(val, (int __user *) arg);
3213 }
3214 
3215 /* This is the ioctl entry to the mixer driver. */
3216 
3217 static long vwsnd_mixer_ioctl(struct file *file,
3218                               unsigned int cmd,
3219                               unsigned long arg)
3220 {
3221         vwsnd_dev_t *devc = (vwsnd_dev_t *) file->private_data;
3222         const unsigned int nrmask = _IOC_NRMASK << _IOC_NRSHIFT;
3223         const unsigned int nr = (cmd & nrmask) >> _IOC_NRSHIFT;
3224         int retval;
3225 
3226         DBGEV("(devc=0x%p, cmd=0x%x, arg=0x%lx)\n", devc, cmd, arg);
3227 
3228         mutex_lock(&vwsnd_mutex);
3229         mutex_lock(&devc->mix_mutex);
3230         {
3231                 if ((cmd & ~nrmask) == MIXER_READ(0))
3232                         retval = mixer_read_ioctl(devc, nr, (void __user *) arg);
3233                 else if ((cmd & ~nrmask) == MIXER_WRITE(0))
3234                         retval = mixer_write_ioctl(devc, nr, (void __user *) arg);
3235                 else
3236                         retval = -EINVAL;
3237         }
3238         mutex_unlock(&devc->mix_mutex);
3239         mutex_unlock(&vwsnd_mutex);
3240         return retval;
3241 }
3242 
3243 static const struct file_operations vwsnd_mixer_fops = {
3244         .owner =        THIS_MODULE,
3245         .llseek =       no_llseek,
3246         .unlocked_ioctl = vwsnd_mixer_ioctl,
3247         .open =         vwsnd_mixer_open,
3248         .release =      vwsnd_mixer_release,
3249 };
3250 
3251 /*****************************************************************************/
3252 /* probe/attach/unload */
3253 
3254 /* driver probe routine.  Return nonzero if hardware is found. */
3255 
3256 static int __init probe_vwsnd(struct address_info *hw_config)
3257 {
3258         lithium_t lith;
3259         int w;
3260         unsigned long later;
3261 
3262         DBGEV("(hw_config=0x%p)\n", hw_config);
3263 
3264         /* XXX verify lithium present (to prevent crash on non-vw) */
3265 
3266         if (li_create(&lith, hw_config->io_base) != 0) {
3267                 printk(KERN_WARNING "probe_vwsnd: can't map lithium\n");
3268                 return 0;
3269         }
3270         later = jiffies + 2;
3271         li_writel(&lith, LI_HOST_CONTROLLER, LI_HC_LINK_ENABLE);
3272         do {
3273                 w = li_readl(&lith, LI_HOST_CONTROLLER);
3274         } while (w == LI_HC_LINK_ENABLE && time_before(jiffies, later));
3275         
3276         li_destroy(&lith);
3277 
3278         DBGPV("HC = 0x%04x\n", w);
3279 
3280         if ((w == LI_HC_LINK_ENABLE) || (w & LI_HC_LINK_CODEC)) {
3281 
3282                 /* This may indicate a beta machine with no audio,
3283                  * or a future machine with different audio.
3284                  * On beta-release 320 w/ no audio, HC == 0x4000 */
3285 
3286                 printk(KERN_WARNING "probe_vwsnd: audio codec not found\n");
3287                 return 0;
3288         }
3289 
3290         if (w & LI_HC_LINK_FAILURE) {
3291                 printk(KERN_WARNING "probe_vwsnd: can't init audio codec\n");
3292                 return 0;
3293         }
3294 
3295         printk(KERN_INFO "vwsnd: lithium audio at mmio %#x irq %d\n",
3296                 hw_config->io_base, hw_config->irq);
3297 
3298         return 1;
3299 }
3300 
3301 /*
3302  * driver attach routine.  Initialize driver data structures and
3303  * initialize hardware.  A new vwsnd_dev_t is allocated and put
3304  * onto the global list, vwsnd_dev_list.
3305  *
3306  * Return +minor_dev on success, -errno on failure.
3307  */
3308 
3309 static int __init attach_vwsnd(struct address_info *hw_config)
3310 {
3311         vwsnd_dev_t *devc = NULL;
3312         int err = -ENOMEM;
3313 
3314         DBGEV("(hw_config=0x%p)\n", hw_config);
3315 
3316         devc = kmalloc(sizeof (vwsnd_dev_t), GFP_KERNEL);
3317         if (devc == NULL)
3318                 goto fail0;
3319 
3320         err = li_create(&devc->lith, hw_config->io_base);
3321         if (err)
3322                 goto fail1;
3323 
3324         init_waitqueue_head(&devc->open_wait);
3325 
3326         devc->rport.hwbuf_size = HWBUF_SIZE;
3327         devc->rport.hwbuf_vaddr = __get_free_pages(GFP_KERNEL, HWBUF_ORDER);
3328         if (!devc->rport.hwbuf_vaddr)
3329                 goto fail2;
3330         devc->rport.hwbuf = (void *) devc->rport.hwbuf_vaddr;
3331         devc->rport.hwbuf_paddr = virt_to_phys(devc->rport.hwbuf);
3332 
3333         /*
3334          * Quote from the NT driver:
3335          *
3336          * // WARNING!!! HACK to setup output dma!!!
3337          * // This is required because even on output there is some data
3338          * // trickling into the input DMA channel.  This is a bug in the
3339          * // Lithium microcode.
3340          * // --sde
3341          *
3342          * We set the input side's DMA base address here.  It will remain
3343          * valid until the driver is unloaded.
3344          */
3345 
3346         li_writel(&devc->lith, LI_COMM1_BASE,
3347                   devc->rport.hwbuf_paddr >> 8 | 1 << (37 - 8));
3348 
3349         devc->wport.hwbuf_size = HWBUF_SIZE;
3350         devc->wport.hwbuf_vaddr = __get_free_pages(GFP_KERNEL, HWBUF_ORDER);
3351         if (!devc->wport.hwbuf_vaddr)
3352                 goto fail3;
3353         devc->wport.hwbuf = (void *) devc->wport.hwbuf_vaddr;
3354         devc->wport.hwbuf_paddr = virt_to_phys(devc->wport.hwbuf);
3355         DBGP("wport hwbuf = 0x%p\n", devc->wport.hwbuf);
3356 
3357         DBGDO(shut_up++);
3358         err = ad1843_init(&devc->lith);
3359         DBGDO(shut_up--);
3360         if (err)
3361                 goto fail4;
3362 
3363         /* install interrupt handler */
3364 
3365         err = request_irq(hw_config->irq, vwsnd_audio_intr, 0, "vwsnd", devc);
3366         if (err)
3367                 goto fail5;
3368 
3369         /* register this device's drivers. */
3370 
3371         devc->audio_minor = register_sound_dsp(&vwsnd_audio_fops, -1);
3372         if ((err = devc->audio_minor) < 0) {
3373                 DBGDO(printk(KERN_WARNING
3374                              "attach_vwsnd: register_sound_dsp error %d\n",
3375                              err));
3376                 goto fail6;
3377         }
3378         devc->mixer_minor = register_sound_mixer(&vwsnd_mixer_fops,
3379                                                  devc->audio_minor >> 4);
3380         if ((err = devc->mixer_minor) < 0) {
3381                 DBGDO(printk(KERN_WARNING
3382                              "attach_vwsnd: register_sound_mixer error %d\n",
3383                              err));
3384                 goto fail7;
3385         }
3386 
3387         /* Squirrel away device indices for unload routine. */
3388 
3389         hw_config->slots[0] = devc->audio_minor;
3390 
3391         /* Initialize as much of *devc as possible */
3392 
3393         mutex_init(&devc->open_mutex);
3394         mutex_init(&devc->io_mutex);
3395         mutex_init(&devc->mix_mutex);
3396         devc->open_mode = 0;
3397         spin_lock_init(&devc->rport.lock);
3398         init_waitqueue_head(&devc->rport.queue);
3399         devc->rport.swstate = SW_OFF;
3400         devc->rport.hwstate = HW_STOPPED;
3401         devc->rport.flags = 0;
3402         devc->rport.swbuf = NULL;
3403         spin_lock_init(&devc->wport.lock);
3404         init_waitqueue_head(&devc->wport.queue);
3405         devc->wport.swstate = SW_OFF;
3406         devc->wport.hwstate = HW_STOPPED;
3407         devc->wport.flags = 0;
3408         devc->wport.swbuf = NULL;
3409 
3410         /* Success.  Link us onto the local device list. */
3411 
3412         devc->next_dev = vwsnd_dev_list;
3413         vwsnd_dev_list = devc;
3414         return devc->audio_minor;
3415 
3416         /* So many ways to fail.  Undo what we did. */
3417 
3418  fail7:
3419         unregister_sound_dsp(devc->audio_minor);
3420  fail6:
3421         free_irq(hw_config->irq, devc);
3422  fail5:
3423  fail4:
3424         free_pages(devc->wport.hwbuf_vaddr, HWBUF_ORDER);
3425  fail3:
3426         free_pages(devc->rport.hwbuf_vaddr, HWBUF_ORDER);
3427  fail2:
3428         li_destroy(&devc->lith);
3429  fail1:
3430         kfree(devc);
3431  fail0:
3432         return err;
3433 }
3434 
3435 static int __exit unload_vwsnd(struct address_info *hw_config)
3436 {
3437         vwsnd_dev_t *devc, **devcp;
3438 
3439         DBGE("()\n");
3440 
3441         devcp = &vwsnd_dev_list;
3442         while ((devc = *devcp)) {
3443                 if (devc->audio_minor == hw_config->slots[0]) {
3444                         *devcp = devc->next_dev;
3445                         break;
3446                 }
3447                 devcp = &devc->next_dev;
3448         }
3449 
3450         if (!devc)
3451                 return -ENODEV;
3452 
3453         unregister_sound_mixer(devc->mixer_minor);
3454         unregister_sound_dsp(devc->audio_minor);
3455         free_irq(hw_config->irq, devc);
3456         free_pages(devc->wport.hwbuf_vaddr, HWBUF_ORDER);
3457         free_pages(devc->rport.hwbuf_vaddr, HWBUF_ORDER);
3458         li_destroy(&devc->lith);
3459         kfree(devc);
3460 
3461         return 0;
3462 }
3463 
3464 /*****************************************************************************/
3465 /* initialization and loadable kernel module interface */
3466 
3467 static struct address_info the_hw_config = {
3468         0xFF001000,                     /* lithium phys addr  */
3469         CO_IRQ(CO_APIC_LI_AUDIO)        /* irq */
3470 };
3471 
3472 MODULE_DESCRIPTION("SGI Visual Workstation sound module");
3473 MODULE_AUTHOR("Bob Miller <kbob@sgi.com>");
3474 MODULE_LICENSE("GPL");
3475 
3476 static int __init init_vwsnd(void)
3477 {
3478         int err;
3479 
3480         DBGXV("\n");
3481         DBGXV("sound::vwsnd::init_module()\n");
3482 
3483         if (!probe_vwsnd(&the_hw_config))
3484                 return -ENODEV;
3485 
3486         err = attach_vwsnd(&the_hw_config);
3487         if (err < 0)
3488                 return err;
3489         return 0;
3490 }
3491 
3492 static void __exit cleanup_vwsnd(void)
3493 {
3494         DBGX("sound::vwsnd::cleanup_module()\n");
3495 
3496         unload_vwsnd(&the_hw_config);
3497 }
3498 
3499 module_init(init_vwsnd);
3500 module_exit(cleanup_vwsnd);
3501 

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