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TOMOYO Linux Cross Reference
Linux/sound/pci/cs4281.c

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  1 // SPDX-License-Identifier: GPL-2.0-or-later
  2 /*
  3  *  Driver for Cirrus Logic CS4281 based PCI soundcard
  4  *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
  5  */
  6 
  7 #include <linux/io.h>
  8 #include <linux/delay.h>
  9 #include <linux/interrupt.h>
 10 #include <linux/init.h>
 11 #include <linux/pci.h>
 12 #include <linux/slab.h>
 13 #include <linux/gameport.h>
 14 #include <linux/module.h>
 15 #include <sound/core.h>
 16 #include <sound/control.h>
 17 #include <sound/pcm.h>
 18 #include <sound/rawmidi.h>
 19 #include <sound/ac97_codec.h>
 20 #include <sound/tlv.h>
 21 #include <sound/opl3.h>
 22 #include <sound/initval.h>
 23 
 24 
 25 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
 26 MODULE_DESCRIPTION("Cirrus Logic CS4281");
 27 MODULE_LICENSE("GPL");
 28 MODULE_SUPPORTED_DEVICE("{{Cirrus Logic,CS4281}}");
 29 
 30 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
 31 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
 32 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;     /* Enable switches */
 33 static bool dual_codec[SNDRV_CARDS];    /* dual codec */
 34 
 35 module_param_array(index, int, NULL, 0444);
 36 MODULE_PARM_DESC(index, "Index value for CS4281 soundcard.");
 37 module_param_array(id, charp, NULL, 0444);
 38 MODULE_PARM_DESC(id, "ID string for CS4281 soundcard.");
 39 module_param_array(enable, bool, NULL, 0444);
 40 MODULE_PARM_DESC(enable, "Enable CS4281 soundcard.");
 41 module_param_array(dual_codec, bool, NULL, 0444);
 42 MODULE_PARM_DESC(dual_codec, "Secondary Codec ID (0 = disabled).");
 43 
 44 /*
 45  *  Direct registers
 46  */
 47 
 48 #define CS4281_BA0_SIZE         0x1000
 49 #define CS4281_BA1_SIZE         0x10000
 50 
 51 /*
 52  *  BA0 registers
 53  */
 54 #define BA0_HISR                0x0000  /* Host Interrupt Status Register */
 55 #define BA0_HISR_INTENA         (1<<31) /* Internal Interrupt Enable Bit */
 56 #define BA0_HISR_MIDI           (1<<22) /* MIDI port interrupt */
 57 #define BA0_HISR_FIFOI          (1<<20) /* FIFO polled interrupt */
 58 #define BA0_HISR_DMAI           (1<<18) /* DMA interrupt (half or end) */
 59 #define BA0_HISR_FIFO(c)        (1<<(12+(c))) /* FIFO channel interrupt */
 60 #define BA0_HISR_DMA(c)         (1<<(8+(c)))  /* DMA channel interrupt */
 61 #define BA0_HISR_GPPI           (1<<5)  /* General Purpose Input (Primary chip) */
 62 #define BA0_HISR_GPSI           (1<<4)  /* General Purpose Input (Secondary chip) */
 63 #define BA0_HISR_GP3I           (1<<3)  /* GPIO3 pin Interrupt */
 64 #define BA0_HISR_GP1I           (1<<2)  /* GPIO1 pin Interrupt */
 65 #define BA0_HISR_VUPI           (1<<1)  /* VOLUP pin Interrupt */
 66 #define BA0_HISR_VDNI           (1<<0)  /* VOLDN pin Interrupt */
 67 
 68 #define BA0_HICR                0x0008  /* Host Interrupt Control Register */
 69 #define BA0_HICR_CHGM           (1<<1)  /* INTENA Change Mask */
 70 #define BA0_HICR_IEV            (1<<0)  /* INTENA Value */
 71 #define BA0_HICR_EOI            (3<<0)  /* End of Interrupt command */
 72 
 73 #define BA0_HIMR                0x000c  /* Host Interrupt Mask Register */
 74                                         /* Use same contants as for BA0_HISR */
 75 
 76 #define BA0_IIER                0x0010  /* ISA Interrupt Enable Register */
 77 
 78 #define BA0_HDSR0               0x00f0  /* Host DMA Engine 0 Status Register */
 79 #define BA0_HDSR1               0x00f4  /* Host DMA Engine 1 Status Register */
 80 #define BA0_HDSR2               0x00f8  /* Host DMA Engine 2 Status Register */
 81 #define BA0_HDSR3               0x00fc  /* Host DMA Engine 3 Status Register */
 82 
 83 #define BA0_HDSR_CH1P           (1<<25) /* Channel 1 Pending */
 84 #define BA0_HDSR_CH2P           (1<<24) /* Channel 2 Pending */
 85 #define BA0_HDSR_DHTC           (1<<17) /* DMA Half Terminal Count */
 86 #define BA0_HDSR_DTC            (1<<16) /* DMA Terminal Count */
 87 #define BA0_HDSR_DRUN           (1<<15) /* DMA Running */
 88 #define BA0_HDSR_RQ             (1<<7)  /* Pending Request */
 89 
 90 #define BA0_DCA0                0x0110  /* Host DMA Engine 0 Current Address */
 91 #define BA0_DCC0                0x0114  /* Host DMA Engine 0 Current Count */
 92 #define BA0_DBA0                0x0118  /* Host DMA Engine 0 Base Address */
 93 #define BA0_DBC0                0x011c  /* Host DMA Engine 0 Base Count */
 94 #define BA0_DCA1                0x0120  /* Host DMA Engine 1 Current Address */
 95 #define BA0_DCC1                0x0124  /* Host DMA Engine 1 Current Count */
 96 #define BA0_DBA1                0x0128  /* Host DMA Engine 1 Base Address */
 97 #define BA0_DBC1                0x012c  /* Host DMA Engine 1 Base Count */
 98 #define BA0_DCA2                0x0130  /* Host DMA Engine 2 Current Address */
 99 #define BA0_DCC2                0x0134  /* Host DMA Engine 2 Current Count */
100 #define BA0_DBA2                0x0138  /* Host DMA Engine 2 Base Address */
101 #define BA0_DBC2                0x013c  /* Host DMA Engine 2 Base Count */
102 #define BA0_DCA3                0x0140  /* Host DMA Engine 3 Current Address */
103 #define BA0_DCC3                0x0144  /* Host DMA Engine 3 Current Count */
104 #define BA0_DBA3                0x0148  /* Host DMA Engine 3 Base Address */
105 #define BA0_DBC3                0x014c  /* Host DMA Engine 3 Base Count */
106 #define BA0_DMR0                0x0150  /* Host DMA Engine 0 Mode */
107 #define BA0_DCR0                0x0154  /* Host DMA Engine 0 Command */
108 #define BA0_DMR1                0x0158  /* Host DMA Engine 1 Mode */
109 #define BA0_DCR1                0x015c  /* Host DMA Engine 1 Command */
110 #define BA0_DMR2                0x0160  /* Host DMA Engine 2 Mode */
111 #define BA0_DCR2                0x0164  /* Host DMA Engine 2 Command */
112 #define BA0_DMR3                0x0168  /* Host DMA Engine 3 Mode */
113 #define BA0_DCR3                0x016c  /* Host DMA Engine 3 Command */
114 
115 #define BA0_DMR_DMA             (1<<29) /* Enable DMA mode */
116 #define BA0_DMR_POLL            (1<<28) /* Enable poll mode */
117 #define BA0_DMR_TBC             (1<<25) /* Transfer By Channel */
118 #define BA0_DMR_CBC             (1<<24) /* Count By Channel (0 = frame resolution) */
119 #define BA0_DMR_SWAPC           (1<<22) /* Swap Left/Right Channels */
120 #define BA0_DMR_SIZE20          (1<<20) /* Sample is 20-bit */
121 #define BA0_DMR_USIGN           (1<<19) /* Unsigned */
122 #define BA0_DMR_BEND            (1<<18) /* Big Endian */
123 #define BA0_DMR_MONO            (1<<17) /* Mono */
124 #define BA0_DMR_SIZE8           (1<<16) /* Sample is 8-bit */
125 #define BA0_DMR_TYPE_DEMAND     (0<<6)
126 #define BA0_DMR_TYPE_SINGLE     (1<<6)
127 #define BA0_DMR_TYPE_BLOCK      (2<<6)
128 #define BA0_DMR_TYPE_CASCADE    (3<<6)  /* Not supported */
129 #define BA0_DMR_DEC             (1<<5)  /* Access Increment (0) or Decrement (1) */
130 #define BA0_DMR_AUTO            (1<<4)  /* Auto-Initialize */
131 #define BA0_DMR_TR_VERIFY       (0<<2)  /* Verify Transfer */
132 #define BA0_DMR_TR_WRITE        (1<<2)  /* Write Transfer */
133 #define BA0_DMR_TR_READ         (2<<2)  /* Read Transfer */
134 
135 #define BA0_DCR_HTCIE           (1<<17) /* Half Terminal Count Interrupt */
136 #define BA0_DCR_TCIE            (1<<16) /* Terminal Count Interrupt */
137 #define BA0_DCR_MSK             (1<<0)  /* DMA Mask bit */
138 
139 #define BA0_FCR0                0x0180  /* FIFO Control 0 */
140 #define BA0_FCR1                0x0184  /* FIFO Control 1 */
141 #define BA0_FCR2                0x0188  /* FIFO Control 2 */
142 #define BA0_FCR3                0x018c  /* FIFO Control 3 */
143 
144 #define BA0_FCR_FEN             (1<<31) /* FIFO Enable bit */
145 #define BA0_FCR_DACZ            (1<<30) /* DAC Zero */
146 #define BA0_FCR_PSH             (1<<29) /* Previous Sample Hold */
147 #define BA0_FCR_RS(x)           (((x)&0x1f)<<24) /* Right Slot Mapping */
148 #define BA0_FCR_LS(x)           (((x)&0x1f)<<16) /* Left Slot Mapping */
149 #define BA0_FCR_SZ(x)           (((x)&0x7f)<<8) /* FIFO buffer size (in samples) */
150 #define BA0_FCR_OF(x)           (((x)&0x7f)<<0) /* FIFO starting offset (in samples) */
151 
152 #define BA0_FPDR0               0x0190  /* FIFO Polled Data 0 */
153 #define BA0_FPDR1               0x0194  /* FIFO Polled Data 1 */
154 #define BA0_FPDR2               0x0198  /* FIFO Polled Data 2 */
155 #define BA0_FPDR3               0x019c  /* FIFO Polled Data 3 */
156 
157 #define BA0_FCHS                0x020c  /* FIFO Channel Status */
158 #define BA0_FCHS_RCO(x)         (1<<(7+(((x)&3)<<3))) /* Right Channel Out */
159 #define BA0_FCHS_LCO(x)         (1<<(6+(((x)&3)<<3))) /* Left Channel Out */
160 #define BA0_FCHS_MRP(x)         (1<<(5+(((x)&3)<<3))) /* Move Read Pointer */
161 #define BA0_FCHS_FE(x)          (1<<(4+(((x)&3)<<3))) /* FIFO Empty */
162 #define BA0_FCHS_FF(x)          (1<<(3+(((x)&3)<<3))) /* FIFO Full */
163 #define BA0_FCHS_IOR(x)         (1<<(2+(((x)&3)<<3))) /* Internal Overrun Flag */
164 #define BA0_FCHS_RCI(x)         (1<<(1+(((x)&3)<<3))) /* Right Channel In */
165 #define BA0_FCHS_LCI(x)         (1<<(0+(((x)&3)<<3))) /* Left Channel In */
166 
167 #define BA0_FSIC0               0x0210  /* FIFO Status and Interrupt Control 0 */
168 #define BA0_FSIC1               0x0214  /* FIFO Status and Interrupt Control 1 */
169 #define BA0_FSIC2               0x0218  /* FIFO Status and Interrupt Control 2 */
170 #define BA0_FSIC3               0x021c  /* FIFO Status and Interrupt Control 3 */
171 
172 #define BA0_FSIC_FIC(x)         (((x)&0x7f)<<24) /* FIFO Interrupt Count */
173 #define BA0_FSIC_FORIE          (1<<23) /* FIFO OverRun Interrupt Enable */
174 #define BA0_FSIC_FURIE          (1<<22) /* FIFO UnderRun Interrupt Enable */
175 #define BA0_FSIC_FSCIE          (1<<16) /* FIFO Sample Count Interrupt Enable */
176 #define BA0_FSIC_FSC(x)         (((x)&0x7f)<<8) /* FIFO Sample Count */
177 #define BA0_FSIC_FOR            (1<<7)  /* FIFO OverRun */
178 #define BA0_FSIC_FUR            (1<<6)  /* FIFO UnderRun */
179 #define BA0_FSIC_FSCR           (1<<0)  /* FIFO Sample Count Reached */
180 
181 #define BA0_PMCS                0x0344  /* Power Management Control/Status */
182 #define BA0_CWPR                0x03e0  /* Configuration Write Protect */
183 
184 #define BA0_EPPMC               0x03e4  /* Extended PCI Power Management Control */
185 #define BA0_EPPMC_FPDN          (1<<14) /* Full Power DowN */
186 
187 #define BA0_GPIOR               0x03e8  /* GPIO Pin Interface Register */
188 
189 #define BA0_SPMC                0x03ec  /* Serial Port Power Management Control (& ASDIN2 enable) */
190 #define BA0_SPMC_GIPPEN         (1<<15) /* GP INT Primary PME# Enable */
191 #define BA0_SPMC_GISPEN         (1<<14) /* GP INT Secondary PME# Enable */
192 #define BA0_SPMC_EESPD          (1<<9)  /* EEPROM Serial Port Disable */
193 #define BA0_SPMC_ASDI2E         (1<<8)  /* ASDIN2 Enable */
194 #define BA0_SPMC_ASDO           (1<<7)  /* Asynchronous ASDOUT Assertion */
195 #define BA0_SPMC_WUP2           (1<<3)  /* Wakeup for Secondary Input */
196 #define BA0_SPMC_WUP1           (1<<2)  /* Wakeup for Primary Input */
197 #define BA0_SPMC_ASYNC          (1<<1)  /* Asynchronous ASYNC Assertion */
198 #define BA0_SPMC_RSTN           (1<<0)  /* Reset Not! */
199 
200 #define BA0_CFLR                0x03f0  /* Configuration Load Register (EEPROM or BIOS) */
201 #define BA0_CFLR_DEFAULT        0x00000001 /* CFLR must be in AC97 link mode */
202 #define BA0_IISR                0x03f4  /* ISA Interrupt Select */
203 #define BA0_TMS                 0x03f8  /* Test Register */
204 #define BA0_SSVID               0x03fc  /* Subsystem ID register */
205 
206 #define BA0_CLKCR1              0x0400  /* Clock Control Register 1 */
207 #define BA0_CLKCR1_CLKON        (1<<25) /* Read Only */
208 #define BA0_CLKCR1_DLLRDY       (1<<24) /* DLL Ready */
209 #define BA0_CLKCR1_DLLOS        (1<<6)  /* DLL Output Select */
210 #define BA0_CLKCR1_SWCE         (1<<5)  /* Clock Enable */
211 #define BA0_CLKCR1_DLLP         (1<<4)  /* DLL PowerUp */
212 #define BA0_CLKCR1_DLLSS        (((x)&3)<<3) /* DLL Source Select */
213 
214 #define BA0_FRR                 0x0410  /* Feature Reporting Register */
215 #define BA0_SLT12O              0x041c  /* Slot 12 GPIO Output Register for AC-Link */
216 
217 #define BA0_SERMC               0x0420  /* Serial Port Master Control */
218 #define BA0_SERMC_FCRN          (1<<27) /* Force Codec Ready Not */
219 #define BA0_SERMC_ODSEN2        (1<<25) /* On-Demand Support Enable ASDIN2 */
220 #define BA0_SERMC_ODSEN1        (1<<24) /* On-Demand Support Enable ASDIN1 */
221 #define BA0_SERMC_SXLB          (1<<21) /* ASDIN2 to ASDOUT Loopback */
222 #define BA0_SERMC_SLB           (1<<20) /* ASDOUT to ASDIN2 Loopback */
223 #define BA0_SERMC_LOVF          (1<<19) /* Loopback Output Valid Frame bit */
224 #define BA0_SERMC_TCID(x)       (((x)&3)<<16) /* Target Secondary Codec ID */
225 #define BA0_SERMC_PXLB          (5<<1)  /* Primary Port External Loopback */
226 #define BA0_SERMC_PLB           (4<<1)  /* Primary Port Internal Loopback */
227 #define BA0_SERMC_PTC           (7<<1)  /* Port Timing Configuration */
228 #define BA0_SERMC_PTC_AC97      (1<<1)  /* AC97 mode */
229 #define BA0_SERMC_MSPE          (1<<0)  /* Master Serial Port Enable */
230 
231 #define BA0_SERC1               0x0428  /* Serial Port Configuration 1 */
232 #define BA0_SERC1_SO1F(x)       (((x)&7)>>1) /* Primary Output Port Format */
233 #define BA0_SERC1_AC97          (1<<1)
234 #define BA0_SERC1_SO1EN         (1<<0)  /* Primary Output Port Enable */
235 
236 #define BA0_SERC2               0x042c  /* Serial Port Configuration 2 */
237 #define BA0_SERC2_SI1F(x)       (((x)&7)>>1) /* Primary Input Port Format */
238 #define BA0_SERC2_AC97          (1<<1)
239 #define BA0_SERC2_SI1EN         (1<<0)  /* Primary Input Port Enable */
240 
241 #define BA0_SLT12M              0x045c  /* Slot 12 Monitor Register for Primary AC-Link */
242 
243 #define BA0_ACCTL               0x0460  /* AC'97 Control */
244 #define BA0_ACCTL_TC            (1<<6)  /* Target Codec */
245 #define BA0_ACCTL_CRW           (1<<4)  /* 0=Write, 1=Read Command */
246 #define BA0_ACCTL_DCV           (1<<3)  /* Dynamic Command Valid */
247 #define BA0_ACCTL_VFRM          (1<<2)  /* Valid Frame */
248 #define BA0_ACCTL_ESYN          (1<<1)  /* Enable Sync */
249 
250 #define BA0_ACSTS               0x0464  /* AC'97 Status */
251 #define BA0_ACSTS_VSTS          (1<<1)  /* Valid Status */
252 #define BA0_ACSTS_CRDY          (1<<0)  /* Codec Ready */
253 
254 #define BA0_ACOSV               0x0468  /* AC'97 Output Slot Valid */
255 #define BA0_ACOSV_SLV(x)        (1<<((x)-3))
256 
257 #define BA0_ACCAD               0x046c  /* AC'97 Command Address */
258 #define BA0_ACCDA               0x0470  /* AC'97 Command Data */
259 
260 #define BA0_ACISV               0x0474  /* AC'97 Input Slot Valid */
261 #define BA0_ACISV_SLV(x)        (1<<((x)-3))
262 
263 #define BA0_ACSAD               0x0478  /* AC'97 Status Address */
264 #define BA0_ACSDA               0x047c  /* AC'97 Status Data */
265 #define BA0_JSPT                0x0480  /* Joystick poll/trigger */
266 #define BA0_JSCTL               0x0484  /* Joystick control */
267 #define BA0_JSC1                0x0488  /* Joystick control */
268 #define BA0_JSC2                0x048c  /* Joystick control */
269 #define BA0_JSIO                0x04a0
270 
271 #define BA0_MIDCR               0x0490  /* MIDI Control */
272 #define BA0_MIDCR_MRST          (1<<5)  /* Reset MIDI Interface */
273 #define BA0_MIDCR_MLB           (1<<4)  /* MIDI Loop Back Enable */
274 #define BA0_MIDCR_TIE           (1<<3)  /* MIDI Transmuit Interrupt Enable */
275 #define BA0_MIDCR_RIE           (1<<2)  /* MIDI Receive Interrupt Enable */
276 #define BA0_MIDCR_RXE           (1<<1)  /* MIDI Receive Enable */
277 #define BA0_MIDCR_TXE           (1<<0)  /* MIDI Transmit Enable */
278 
279 #define BA0_MIDCMD              0x0494  /* MIDI Command (wo) */
280 
281 #define BA0_MIDSR               0x0494  /* MIDI Status (ro) */
282 #define BA0_MIDSR_RDA           (1<<15) /* Sticky bit (RBE 1->0) */
283 #define BA0_MIDSR_TBE           (1<<14) /* Sticky bit (TBF 0->1) */
284 #define BA0_MIDSR_RBE           (1<<7)  /* Receive Buffer Empty */
285 #define BA0_MIDSR_TBF           (1<<6)  /* Transmit Buffer Full */
286 
287 #define BA0_MIDWP               0x0498  /* MIDI Write */
288 #define BA0_MIDRP               0x049c  /* MIDI Read (ro) */
289 
290 #define BA0_AODSD1              0x04a8  /* AC'97 On-Demand Slot Disable for primary link (ro) */
291 #define BA0_AODSD1_NDS(x)       (1<<((x)-3))
292 
293 #define BA0_AODSD2              0x04ac  /* AC'97 On-Demand Slot Disable for secondary link (ro) */
294 #define BA0_AODSD2_NDS(x)       (1<<((x)-3))
295 
296 #define BA0_CFGI                0x04b0  /* Configure Interface (EEPROM interface) */
297 #define BA0_SLT12M2             0x04dc  /* Slot 12 Monitor Register 2 for secondary AC-link */
298 #define BA0_ACSTS2              0x04e4  /* AC'97 Status Register 2 */
299 #define BA0_ACISV2              0x04f4  /* AC'97 Input Slot Valid Register 2 */
300 #define BA0_ACSAD2              0x04f8  /* AC'97 Status Address Register 2 */
301 #define BA0_ACSDA2              0x04fc  /* AC'97 Status Data Register 2 */
302 #define BA0_FMSR                0x0730  /* FM Synthesis Status (ro) */
303 #define BA0_B0AP                0x0730  /* FM Bank 0 Address Port (wo) */
304 #define BA0_FMDP                0x0734  /* FM Data Port */
305 #define BA0_B1AP                0x0738  /* FM Bank 1 Address Port */
306 #define BA0_B1DP                0x073c  /* FM Bank 1 Data Port */
307 
308 #define BA0_SSPM                0x0740  /* Sound System Power Management */
309 #define BA0_SSPM_MIXEN          (1<<6)  /* Playback SRC + FM/Wavetable MIX */
310 #define BA0_SSPM_CSRCEN         (1<<5)  /* Capture Sample Rate Converter Enable */
311 #define BA0_SSPM_PSRCEN         (1<<4)  /* Playback Sample Rate Converter Enable */
312 #define BA0_SSPM_JSEN           (1<<3)  /* Joystick Enable */
313 #define BA0_SSPM_ACLEN          (1<<2)  /* Serial Port Engine and AC-Link Enable */
314 #define BA0_SSPM_FMEN           (1<<1)  /* FM Synthesis Block Enable */
315 
316 #define BA0_DACSR               0x0744  /* DAC Sample Rate - Playback SRC */
317 #define BA0_ADCSR               0x0748  /* ADC Sample Rate - Capture SRC */
318 
319 #define BA0_SSCR                0x074c  /* Sound System Control Register */
320 #define BA0_SSCR_HVS1           (1<<23) /* Hardwave Volume Step (0=1,1=2) */
321 #define BA0_SSCR_MVCS           (1<<19) /* Master Volume Codec Select */
322 #define BA0_SSCR_MVLD           (1<<18) /* Master Volume Line Out Disable */
323 #define BA0_SSCR_MVAD           (1<<17) /* Master Volume Alternate Out Disable */
324 #define BA0_SSCR_MVMD           (1<<16) /* Master Volume Mono Out Disable */
325 #define BA0_SSCR_XLPSRC         (1<<8)  /* External SRC Loopback Mode */
326 #define BA0_SSCR_LPSRC          (1<<7)  /* SRC Loopback Mode */
327 #define BA0_SSCR_CDTX           (1<<5)  /* CD Transfer Data */
328 #define BA0_SSCR_HVC            (1<<3)  /* Harware Volume Control Enable */
329 
330 #define BA0_FMLVC               0x0754  /* FM Synthesis Left Volume Control */
331 #define BA0_FMRVC               0x0758  /* FM Synthesis Right Volume Control */
332 #define BA0_SRCSA               0x075c  /* SRC Slot Assignments */
333 #define BA0_PPLVC               0x0760  /* PCM Playback Left Volume Control */
334 #define BA0_PPRVC               0x0764  /* PCM Playback Right Volume Control */
335 #define BA0_PASR                0x0768  /* playback sample rate */
336 #define BA0_CASR                0x076C  /* capture sample rate */
337 
338 /* Source Slot Numbers - Playback */
339 #define SRCSLOT_LEFT_PCM_PLAYBACK               0
340 #define SRCSLOT_RIGHT_PCM_PLAYBACK              1
341 #define SRCSLOT_PHONE_LINE_1_DAC                2
342 #define SRCSLOT_CENTER_PCM_PLAYBACK             3
343 #define SRCSLOT_LEFT_SURROUND_PCM_PLAYBACK      4
344 #define SRCSLOT_RIGHT_SURROUND_PCM_PLAYBACK     5
345 #define SRCSLOT_LFE_PCM_PLAYBACK                6
346 #define SRCSLOT_PHONE_LINE_2_DAC                7
347 #define SRCSLOT_HEADSET_DAC                     8
348 #define SRCSLOT_LEFT_WT                         29  /* invalid for BA0_SRCSA */
349 #define SRCSLOT_RIGHT_WT                        30  /* invalid for BA0_SRCSA */
350 
351 /* Source Slot Numbers - Capture */
352 #define SRCSLOT_LEFT_PCM_RECORD                 10
353 #define SRCSLOT_RIGHT_PCM_RECORD                11
354 #define SRCSLOT_PHONE_LINE_1_ADC                12
355 #define SRCSLOT_MIC_ADC                         13
356 #define SRCSLOT_PHONE_LINE_2_ADC                17
357 #define SRCSLOT_HEADSET_ADC                     18
358 #define SRCSLOT_SECONDARY_LEFT_PCM_RECORD       20
359 #define SRCSLOT_SECONDARY_RIGHT_PCM_RECORD      21
360 #define SRCSLOT_SECONDARY_PHONE_LINE_1_ADC      22
361 #define SRCSLOT_SECONDARY_MIC_ADC               23
362 #define SRCSLOT_SECONDARY_PHONE_LINE_2_ADC      27
363 #define SRCSLOT_SECONDARY_HEADSET_ADC           28
364 
365 /* Source Slot Numbers - Others */
366 #define SRCSLOT_POWER_DOWN                      31
367 
368 /* MIDI modes */
369 #define CS4281_MODE_OUTPUT              (1<<0)
370 #define CS4281_MODE_INPUT               (1<<1)
371 
372 /* joystick bits */
373 /* Bits for JSPT */
374 #define JSPT_CAX                                0x00000001
375 #define JSPT_CAY                                0x00000002
376 #define JSPT_CBX                                0x00000004
377 #define JSPT_CBY                                0x00000008
378 #define JSPT_BA1                                0x00000010
379 #define JSPT_BA2                                0x00000020
380 #define JSPT_BB1                                0x00000040
381 #define JSPT_BB2                                0x00000080
382 
383 /* Bits for JSCTL */
384 #define JSCTL_SP_MASK                           0x00000003
385 #define JSCTL_SP_SLOW                           0x00000000
386 #define JSCTL_SP_MEDIUM_SLOW                    0x00000001
387 #define JSCTL_SP_MEDIUM_FAST                    0x00000002
388 #define JSCTL_SP_FAST                           0x00000003
389 #define JSCTL_ARE                               0x00000004
390 
391 /* Data register pairs masks */
392 #define JSC1_Y1V_MASK                           0x0000FFFF
393 #define JSC1_X1V_MASK                           0xFFFF0000
394 #define JSC1_Y1V_SHIFT                          0
395 #define JSC1_X1V_SHIFT                          16
396 #define JSC2_Y2V_MASK                           0x0000FFFF
397 #define JSC2_X2V_MASK                           0xFFFF0000
398 #define JSC2_Y2V_SHIFT                          0
399 #define JSC2_X2V_SHIFT                          16
400 
401 /* JS GPIO */
402 #define JSIO_DAX                                0x00000001
403 #define JSIO_DAY                                0x00000002
404 #define JSIO_DBX                                0x00000004
405 #define JSIO_DBY                                0x00000008
406 #define JSIO_AXOE                               0x00000010
407 #define JSIO_AYOE                               0x00000020
408 #define JSIO_BXOE                               0x00000040
409 #define JSIO_BYOE                               0x00000080
410 
411 /*
412  *
413  */
414 
415 struct cs4281_dma {
416         struct snd_pcm_substream *substream;
417         unsigned int regDBA;            /* offset to DBA register */
418         unsigned int regDCA;            /* offset to DCA register */
419         unsigned int regDBC;            /* offset to DBC register */
420         unsigned int regDCC;            /* offset to DCC register */
421         unsigned int regDMR;            /* offset to DMR register */
422         unsigned int regDCR;            /* offset to DCR register */
423         unsigned int regHDSR;           /* offset to HDSR register */
424         unsigned int regFCR;            /* offset to FCR register */
425         unsigned int regFSIC;           /* offset to FSIC register */
426         unsigned int valDMR;            /* DMA mode */
427         unsigned int valDCR;            /* DMA command */
428         unsigned int valFCR;            /* FIFO control */
429         unsigned int fifo_offset;       /* FIFO offset within BA1 */
430         unsigned char left_slot;        /* FIFO left slot */
431         unsigned char right_slot;       /* FIFO right slot */
432         int frag;                       /* period number */
433 };
434 
435 #define SUSPEND_REGISTERS       20
436 
437 struct cs4281 {
438         int irq;
439 
440         void __iomem *ba0;              /* virtual (accessible) address */
441         void __iomem *ba1;              /* virtual (accessible) address */
442         unsigned long ba0_addr;
443         unsigned long ba1_addr;
444 
445         int dual_codec;
446 
447         struct snd_ac97_bus *ac97_bus;
448         struct snd_ac97 *ac97;
449         struct snd_ac97 *ac97_secondary;
450 
451         struct pci_dev *pci;
452         struct snd_card *card;
453         struct snd_pcm *pcm;
454         struct snd_rawmidi *rmidi;
455         struct snd_rawmidi_substream *midi_input;
456         struct snd_rawmidi_substream *midi_output;
457 
458         struct cs4281_dma dma[4];
459 
460         unsigned char src_left_play_slot;
461         unsigned char src_right_play_slot;
462         unsigned char src_left_rec_slot;
463         unsigned char src_right_rec_slot;
464 
465         unsigned int spurious_dhtc_irq;
466         unsigned int spurious_dtc_irq;
467 
468         spinlock_t reg_lock;
469         unsigned int midcr;
470         unsigned int uartm;
471 
472         struct gameport *gameport;
473 
474 #ifdef CONFIG_PM_SLEEP
475         u32 suspend_regs[SUSPEND_REGISTERS];
476 #endif
477 
478 };
479 
480 static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id);
481 
482 static const struct pci_device_id snd_cs4281_ids[] = {
483         { PCI_VDEVICE(CIRRUS, 0x6005), 0, },    /* CS4281 */
484         { 0, }
485 };
486 
487 MODULE_DEVICE_TABLE(pci, snd_cs4281_ids);
488 
489 /*
490  *  constants
491  */
492 
493 #define CS4281_FIFO_SIZE        32
494 
495 /*
496  *  common I/O routines
497  */
498 
499 static inline void snd_cs4281_pokeBA0(struct cs4281 *chip, unsigned long offset,
500                                       unsigned int val)
501 {
502         writel(val, chip->ba0 + offset);
503 }
504 
505 static inline unsigned int snd_cs4281_peekBA0(struct cs4281 *chip, unsigned long offset)
506 {
507         return readl(chip->ba0 + offset);
508 }
509 
510 static void snd_cs4281_ac97_write(struct snd_ac97 *ac97,
511                                   unsigned short reg, unsigned short val)
512 {
513         /*
514          *  1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
515          *  2. Write ACCDA = Command Data Register = 470h    for data to write to AC97
516          *  3. Write ACCTL = Control Register = 460h for initiating the write
517          *  4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
518          *  5. if DCV not cleared, break and return error
519          */
520         struct cs4281 *chip = ac97->private_data;
521         int count;
522 
523         /*
524          *  Setup the AC97 control registers on the CS461x to send the
525          *  appropriate command to the AC97 to perform the read.
526          *  ACCAD = Command Address Register = 46Ch
527          *  ACCDA = Command Data Register = 470h
528          *  ACCTL = Control Register = 460h
529          *  set DCV - will clear when process completed
530          *  reset CRW - Write command
531          *  set VFRM - valid frame enabled
532          *  set ESYN - ASYNC generation enabled
533          *  set RSTN - ARST# inactive, AC97 codec not reset
534          */
535         snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
536         snd_cs4281_pokeBA0(chip, BA0_ACCDA, val);
537         snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_VFRM |
538                                             BA0_ACCTL_ESYN | (ac97->num ? BA0_ACCTL_TC : 0));
539         for (count = 0; count < 2000; count++) {
540                 /*
541                  *  First, we want to wait for a short time.
542                  */
543                 udelay(10);
544                 /*
545                  *  Now, check to see if the write has completed.
546                  *  ACCTL = 460h, DCV should be reset by now and 460h = 07h
547                  */
548                 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV)) {
549                         return;
550                 }
551         }
552         dev_err(chip->card->dev,
553                 "AC'97 write problem, reg = 0x%x, val = 0x%x\n", reg, val);
554 }
555 
556 static unsigned short snd_cs4281_ac97_read(struct snd_ac97 *ac97,
557                                            unsigned short reg)
558 {
559         struct cs4281 *chip = ac97->private_data;
560         int count;
561         unsigned short result;
562         // FIXME: volatile is necessary in the following due to a bug of
563         // some gcc versions
564         volatile int ac97_num = ((volatile struct snd_ac97 *)ac97)->num;
565 
566         /*
567          *  1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
568          *  2. Write ACCDA = Command Data Register = 470h    for data to write to AC97 
569          *  3. Write ACCTL = Control Register = 460h for initiating the write
570          *  4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
571          *  5. if DCV not cleared, break and return error
572          *  6. Read ACSTS = Status Register = 464h, check VSTS bit
573          */
574 
575         snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
576 
577         /*
578          *  Setup the AC97 control registers on the CS461x to send the
579          *  appropriate command to the AC97 to perform the read.
580          *  ACCAD = Command Address Register = 46Ch
581          *  ACCDA = Command Data Register = 470h
582          *  ACCTL = Control Register = 460h
583          *  set DCV - will clear when process completed
584          *  set CRW - Read command
585          *  set VFRM - valid frame enabled
586          *  set ESYN - ASYNC generation enabled
587          *  set RSTN - ARST# inactive, AC97 codec not reset
588          */
589 
590         snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
591         snd_cs4281_pokeBA0(chip, BA0_ACCDA, 0);
592         snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_CRW |
593                                             BA0_ACCTL_VFRM | BA0_ACCTL_ESYN |
594                            (ac97_num ? BA0_ACCTL_TC : 0));
595 
596 
597         /*
598          *  Wait for the read to occur.
599          */
600         for (count = 0; count < 500; count++) {
601                 /*
602                  *  First, we want to wait for a short time.
603                  */
604                 udelay(10);
605                 /*
606                  *  Now, check to see if the read has completed.
607                  *  ACCTL = 460h, DCV should be reset by now and 460h = 17h
608                  */
609                 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV))
610                         goto __ok1;
611         }
612 
613         dev_err(chip->card->dev,
614                 "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
615         result = 0xffff;
616         goto __end;
617         
618       __ok1:
619         /*
620          *  Wait for the valid status bit to go active.
621          */
622         for (count = 0; count < 100; count++) {
623                 /*
624                  *  Read the AC97 status register.
625                  *  ACSTS = Status Register = 464h
626                  *  VSTS - Valid Status
627                  */
628                 if (snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSTS2 : BA0_ACSTS) & BA0_ACSTS_VSTS)
629                         goto __ok2;
630                 udelay(10);
631         }
632         
633         dev_err(chip->card->dev,
634                 "AC'97 read problem (ACSTS_VSTS), reg = 0x%x\n", reg);
635         result = 0xffff;
636         goto __end;
637 
638       __ok2:
639         /*
640          *  Read the data returned from the AC97 register.
641          *  ACSDA = Status Data Register = 474h
642          */
643         result = snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
644 
645       __end:
646         return result;
647 }
648 
649 /*
650  *  PCM part
651  */
652 
653 static int snd_cs4281_trigger(struct snd_pcm_substream *substream, int cmd)
654 {
655         struct cs4281_dma *dma = substream->runtime->private_data;
656         struct cs4281 *chip = snd_pcm_substream_chip(substream);
657 
658         spin_lock(&chip->reg_lock);
659         switch (cmd) {
660         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
661                 dma->valDCR |= BA0_DCR_MSK;
662                 dma->valFCR |= BA0_FCR_FEN;
663                 break;
664         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
665                 dma->valDCR &= ~BA0_DCR_MSK;
666                 dma->valFCR &= ~BA0_FCR_FEN;
667                 break;
668         case SNDRV_PCM_TRIGGER_START:
669         case SNDRV_PCM_TRIGGER_RESUME:
670                 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR & ~BA0_DMR_DMA);
671                 dma->valDMR |= BA0_DMR_DMA;
672                 dma->valDCR &= ~BA0_DCR_MSK;
673                 dma->valFCR |= BA0_FCR_FEN;
674                 break;
675         case SNDRV_PCM_TRIGGER_STOP:
676         case SNDRV_PCM_TRIGGER_SUSPEND:
677                 dma->valDMR &= ~(BA0_DMR_DMA|BA0_DMR_POLL);
678                 dma->valDCR |= BA0_DCR_MSK;
679                 dma->valFCR &= ~BA0_FCR_FEN;
680                 /* Leave wave playback FIFO enabled for FM */
681                 if (dma->regFCR != BA0_FCR0)
682                         dma->valFCR &= ~BA0_FCR_FEN;
683                 break;
684         default:
685                 spin_unlock(&chip->reg_lock);
686                 return -EINVAL;
687         }
688         snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR);
689         snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR);
690         snd_cs4281_pokeBA0(chip, dma->regDCR, dma->valDCR);
691         spin_unlock(&chip->reg_lock);
692         return 0;
693 }
694 
695 static unsigned int snd_cs4281_rate(unsigned int rate, unsigned int *real_rate)
696 {
697         unsigned int val;
698         
699         if (real_rate)
700                 *real_rate = rate;
701         /* special "hardcoded" rates */
702         switch (rate) {
703         case 8000:      return 5;
704         case 11025:     return 4;
705         case 16000:     return 3;
706         case 22050:     return 2;
707         case 44100:     return 1;
708         case 48000:     return 0;
709         default:
710                 break;
711         }
712         val = 1536000 / rate;
713         if (real_rate)
714                 *real_rate = 1536000 / val;
715         return val;
716 }
717 
718 static void snd_cs4281_mode(struct cs4281 *chip, struct cs4281_dma *dma,
719                             struct snd_pcm_runtime *runtime,
720                             int capture, int src)
721 {
722         int rec_mono;
723 
724         dma->valDMR = BA0_DMR_TYPE_SINGLE | BA0_DMR_AUTO |
725                       (capture ? BA0_DMR_TR_WRITE : BA0_DMR_TR_READ);
726         if (runtime->channels == 1)
727                 dma->valDMR |= BA0_DMR_MONO;
728         if (snd_pcm_format_unsigned(runtime->format) > 0)
729                 dma->valDMR |= BA0_DMR_USIGN;
730         if (snd_pcm_format_big_endian(runtime->format) > 0)
731                 dma->valDMR |= BA0_DMR_BEND;
732         switch (snd_pcm_format_width(runtime->format)) {
733         case 8: dma->valDMR |= BA0_DMR_SIZE8;
734                 if (runtime->channels == 1)
735                         dma->valDMR |= BA0_DMR_SWAPC;
736                 break;
737         case 32: dma->valDMR |= BA0_DMR_SIZE20; break;
738         }
739         dma->frag = 0;  /* for workaround */
740         dma->valDCR = BA0_DCR_TCIE | BA0_DCR_MSK;
741         if (runtime->buffer_size != runtime->period_size)
742                 dma->valDCR |= BA0_DCR_HTCIE;
743         /* Initialize DMA */
744         snd_cs4281_pokeBA0(chip, dma->regDBA, runtime->dma_addr);
745         snd_cs4281_pokeBA0(chip, dma->regDBC, runtime->buffer_size - 1);
746         rec_mono = (chip->dma[1].valDMR & BA0_DMR_MONO) == BA0_DMR_MONO;
747         snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
748                                             (chip->src_right_play_slot << 8) |
749                                             (chip->src_left_rec_slot << 16) |
750                                             ((rec_mono ? 31 : chip->src_right_rec_slot) << 24));
751         if (!src)
752                 goto __skip_src;
753         if (!capture) {
754                 if (dma->left_slot == chip->src_left_play_slot) {
755                         unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
756                         snd_BUG_ON(dma->right_slot != chip->src_right_play_slot);
757                         snd_cs4281_pokeBA0(chip, BA0_DACSR, val);
758                 }
759         } else {
760                 if (dma->left_slot == chip->src_left_rec_slot) {
761                         unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
762                         snd_BUG_ON(dma->right_slot != chip->src_right_rec_slot);
763                         snd_cs4281_pokeBA0(chip, BA0_ADCSR, val);
764                 }
765         }
766       __skip_src:
767         /* Deactivate wave playback FIFO before changing slot assignments */
768         if (dma->regFCR == BA0_FCR0)
769                 snd_cs4281_pokeBA0(chip, dma->regFCR, snd_cs4281_peekBA0(chip, dma->regFCR) & ~BA0_FCR_FEN);
770         /* Initialize FIFO */
771         dma->valFCR = BA0_FCR_LS(dma->left_slot) |
772                       BA0_FCR_RS(capture && (dma->valDMR & BA0_DMR_MONO) ? 31 : dma->right_slot) |
773                       BA0_FCR_SZ(CS4281_FIFO_SIZE) |
774                       BA0_FCR_OF(dma->fifo_offset);
775         snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | (capture ? BA0_FCR_PSH : 0));
776         /* Activate FIFO again for FM playback */
777         if (dma->regFCR == BA0_FCR0)
778                 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | BA0_FCR_FEN);
779         /* Clear FIFO Status and Interrupt Control Register */
780         snd_cs4281_pokeBA0(chip, dma->regFSIC, 0);
781 }
782 
783 static int snd_cs4281_hw_params(struct snd_pcm_substream *substream,
784                                 struct snd_pcm_hw_params *hw_params)
785 {
786         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
787 }
788 
789 static int snd_cs4281_hw_free(struct snd_pcm_substream *substream)
790 {
791         return snd_pcm_lib_free_pages(substream);
792 }
793 
794 static int snd_cs4281_playback_prepare(struct snd_pcm_substream *substream)
795 {
796         struct snd_pcm_runtime *runtime = substream->runtime;
797         struct cs4281_dma *dma = runtime->private_data;
798         struct cs4281 *chip = snd_pcm_substream_chip(substream);
799 
800         spin_lock_irq(&chip->reg_lock);
801         snd_cs4281_mode(chip, dma, runtime, 0, 1);
802         spin_unlock_irq(&chip->reg_lock);
803         return 0;
804 }
805 
806 static int snd_cs4281_capture_prepare(struct snd_pcm_substream *substream)
807 {
808         struct snd_pcm_runtime *runtime = substream->runtime;
809         struct cs4281_dma *dma = runtime->private_data;
810         struct cs4281 *chip = snd_pcm_substream_chip(substream);
811 
812         spin_lock_irq(&chip->reg_lock);
813         snd_cs4281_mode(chip, dma, runtime, 1, 1);
814         spin_unlock_irq(&chip->reg_lock);
815         return 0;
816 }
817 
818 static snd_pcm_uframes_t snd_cs4281_pointer(struct snd_pcm_substream *substream)
819 {
820         struct snd_pcm_runtime *runtime = substream->runtime;
821         struct cs4281_dma *dma = runtime->private_data;
822         struct cs4281 *chip = snd_pcm_substream_chip(substream);
823 
824         /*
825         dev_dbg(chip->card->dev,
826                 "DCC = 0x%x, buffer_size = 0x%x, jiffies = %li\n",
827                 snd_cs4281_peekBA0(chip, dma->regDCC), runtime->buffer_size,
828                jiffies);
829         */
830         return runtime->buffer_size -
831                snd_cs4281_peekBA0(chip, dma->regDCC) - 1;
832 }
833 
834 static const struct snd_pcm_hardware snd_cs4281_playback =
835 {
836         .info =                 SNDRV_PCM_INFO_MMAP |
837                                 SNDRV_PCM_INFO_INTERLEAVED |
838                                 SNDRV_PCM_INFO_MMAP_VALID |
839                                 SNDRV_PCM_INFO_PAUSE |
840                                 SNDRV_PCM_INFO_RESUME,
841         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
842                                 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
843                                 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
844                                 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
845                                 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
846         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
847         .rate_min =             4000,
848         .rate_max =             48000,
849         .channels_min =         1,
850         .channels_max =         2,
851         .buffer_bytes_max =     (512*1024),
852         .period_bytes_min =     64,
853         .period_bytes_max =     (512*1024),
854         .periods_min =          1,
855         .periods_max =          2,
856         .fifo_size =            CS4281_FIFO_SIZE,
857 };
858 
859 static const struct snd_pcm_hardware snd_cs4281_capture =
860 {
861         .info =                 SNDRV_PCM_INFO_MMAP |
862                                 SNDRV_PCM_INFO_INTERLEAVED |
863                                 SNDRV_PCM_INFO_MMAP_VALID |
864                                 SNDRV_PCM_INFO_PAUSE |
865                                 SNDRV_PCM_INFO_RESUME,
866         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
867                                 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
868                                 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
869                                 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
870                                 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
871         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
872         .rate_min =             4000,
873         .rate_max =             48000,
874         .channels_min =         1,
875         .channels_max =         2,
876         .buffer_bytes_max =     (512*1024),
877         .period_bytes_min =     64,
878         .period_bytes_max =     (512*1024),
879         .periods_min =          1,
880         .periods_max =          2,
881         .fifo_size =            CS4281_FIFO_SIZE,
882 };
883 
884 static int snd_cs4281_playback_open(struct snd_pcm_substream *substream)
885 {
886         struct cs4281 *chip = snd_pcm_substream_chip(substream);
887         struct snd_pcm_runtime *runtime = substream->runtime;
888         struct cs4281_dma *dma;
889 
890         dma = &chip->dma[0];
891         dma->substream = substream;
892         dma->left_slot = 0;
893         dma->right_slot = 1;
894         runtime->private_data = dma;
895         runtime->hw = snd_cs4281_playback;
896         /* should be detected from the AC'97 layer, but it seems
897            that although CS4297A rev B reports 18-bit ADC resolution,
898            samples are 20-bit */
899         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
900         return 0;
901 }
902 
903 static int snd_cs4281_capture_open(struct snd_pcm_substream *substream)
904 {
905         struct cs4281 *chip = snd_pcm_substream_chip(substream);
906         struct snd_pcm_runtime *runtime = substream->runtime;
907         struct cs4281_dma *dma;
908 
909         dma = &chip->dma[1];
910         dma->substream = substream;
911         dma->left_slot = 10;
912         dma->right_slot = 11;
913         runtime->private_data = dma;
914         runtime->hw = snd_cs4281_capture;
915         /* should be detected from the AC'97 layer, but it seems
916            that although CS4297A rev B reports 18-bit ADC resolution,
917            samples are 20-bit */
918         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
919         return 0;
920 }
921 
922 static int snd_cs4281_playback_close(struct snd_pcm_substream *substream)
923 {
924         struct cs4281_dma *dma = substream->runtime->private_data;
925 
926         dma->substream = NULL;
927         return 0;
928 }
929 
930 static int snd_cs4281_capture_close(struct snd_pcm_substream *substream)
931 {
932         struct cs4281_dma *dma = substream->runtime->private_data;
933 
934         dma->substream = NULL;
935         return 0;
936 }
937 
938 static const struct snd_pcm_ops snd_cs4281_playback_ops = {
939         .open =         snd_cs4281_playback_open,
940         .close =        snd_cs4281_playback_close,
941         .ioctl =        snd_pcm_lib_ioctl,
942         .hw_params =    snd_cs4281_hw_params,
943         .hw_free =      snd_cs4281_hw_free,
944         .prepare =      snd_cs4281_playback_prepare,
945         .trigger =      snd_cs4281_trigger,
946         .pointer =      snd_cs4281_pointer,
947 };
948 
949 static const struct snd_pcm_ops snd_cs4281_capture_ops = {
950         .open =         snd_cs4281_capture_open,
951         .close =        snd_cs4281_capture_close,
952         .ioctl =        snd_pcm_lib_ioctl,
953         .hw_params =    snd_cs4281_hw_params,
954         .hw_free =      snd_cs4281_hw_free,
955         .prepare =      snd_cs4281_capture_prepare,
956         .trigger =      snd_cs4281_trigger,
957         .pointer =      snd_cs4281_pointer,
958 };
959 
960 static int snd_cs4281_pcm(struct cs4281 *chip, int device)
961 {
962         struct snd_pcm *pcm;
963         int err;
964 
965         err = snd_pcm_new(chip->card, "CS4281", device, 1, 1, &pcm);
966         if (err < 0)
967                 return err;
968 
969         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4281_playback_ops);
970         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4281_capture_ops);
971 
972         pcm->private_data = chip;
973         pcm->info_flags = 0;
974         strcpy(pcm->name, "CS4281");
975         chip->pcm = pcm;
976 
977         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
978                                               snd_dma_pci_data(chip->pci), 64*1024, 512*1024);
979 
980         return 0;
981 }
982 
983 /*
984  *  Mixer section
985  */
986 
987 #define CS_VOL_MASK     0x1f
988 
989 static int snd_cs4281_info_volume(struct snd_kcontrol *kcontrol,
990                                   struct snd_ctl_elem_info *uinfo)
991 {
992         uinfo->type              = SNDRV_CTL_ELEM_TYPE_INTEGER;
993         uinfo->count             = 2;
994         uinfo->value.integer.min = 0;
995         uinfo->value.integer.max = CS_VOL_MASK;
996         return 0;
997 }
998  
999 static int snd_cs4281_get_volume(struct snd_kcontrol *kcontrol,
1000                                  struct snd_ctl_elem_value *ucontrol)
1001 {
1002         struct cs4281 *chip = snd_kcontrol_chip(kcontrol);
1003         int regL = (kcontrol->private_value >> 16) & 0xffff;
1004         int regR = kcontrol->private_value & 0xffff;
1005         int volL, volR;
1006 
1007         volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
1008         volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
1009 
1010         ucontrol->value.integer.value[0] = volL;
1011         ucontrol->value.integer.value[1] = volR;
1012         return 0;
1013 }
1014 
1015 static int snd_cs4281_put_volume(struct snd_kcontrol *kcontrol,
1016                                  struct snd_ctl_elem_value *ucontrol)
1017 {
1018         struct cs4281 *chip = snd_kcontrol_chip(kcontrol);
1019         int change = 0;
1020         int regL = (kcontrol->private_value >> 16) & 0xffff;
1021         int regR = kcontrol->private_value & 0xffff;
1022         int volL, volR;
1023 
1024         volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
1025         volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
1026 
1027         if (ucontrol->value.integer.value[0] != volL) {
1028                 volL = CS_VOL_MASK - (ucontrol->value.integer.value[0] & CS_VOL_MASK);
1029                 snd_cs4281_pokeBA0(chip, regL, volL);
1030                 change = 1;
1031         }
1032         if (ucontrol->value.integer.value[1] != volR) {
1033                 volR = CS_VOL_MASK - (ucontrol->value.integer.value[1] & CS_VOL_MASK);
1034                 snd_cs4281_pokeBA0(chip, regR, volR);
1035                 change = 1;
1036         }
1037         return change;
1038 }
1039 
1040 static const DECLARE_TLV_DB_SCALE(db_scale_dsp, -4650, 150, 0);
1041 
1042 static const struct snd_kcontrol_new snd_cs4281_fm_vol =
1043 {
1044         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1045         .name = "Synth Playback Volume",
1046         .info = snd_cs4281_info_volume, 
1047         .get = snd_cs4281_get_volume,
1048         .put = snd_cs4281_put_volume, 
1049         .private_value = ((BA0_FMLVC << 16) | BA0_FMRVC),
1050         .tlv = { .p = db_scale_dsp },
1051 };
1052 
1053 static const struct snd_kcontrol_new snd_cs4281_pcm_vol =
1054 {
1055         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1056         .name = "PCM Stream Playback Volume",
1057         .info = snd_cs4281_info_volume, 
1058         .get = snd_cs4281_get_volume,
1059         .put = snd_cs4281_put_volume, 
1060         .private_value = ((BA0_PPLVC << 16) | BA0_PPRVC),
1061         .tlv = { .p = db_scale_dsp },
1062 };
1063 
1064 static void snd_cs4281_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1065 {
1066         struct cs4281 *chip = bus->private_data;
1067         chip->ac97_bus = NULL;
1068 }
1069 
1070 static void snd_cs4281_mixer_free_ac97(struct snd_ac97 *ac97)
1071 {
1072         struct cs4281 *chip = ac97->private_data;
1073         if (ac97->num)
1074                 chip->ac97_secondary = NULL;
1075         else
1076                 chip->ac97 = NULL;
1077 }
1078 
1079 static int snd_cs4281_mixer(struct cs4281 *chip)
1080 {
1081         struct snd_card *card = chip->card;
1082         struct snd_ac97_template ac97;
1083         int err;
1084         static struct snd_ac97_bus_ops ops = {
1085                 .write = snd_cs4281_ac97_write,
1086                 .read = snd_cs4281_ac97_read,
1087         };
1088 
1089         if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0)
1090                 return err;
1091         chip->ac97_bus->private_free = snd_cs4281_mixer_free_ac97_bus;
1092 
1093         memset(&ac97, 0, sizeof(ac97));
1094         ac97.private_data = chip;
1095         ac97.private_free = snd_cs4281_mixer_free_ac97;
1096         if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0)
1097                 return err;
1098         if (chip->dual_codec) {
1099                 ac97.num = 1;
1100                 if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97_secondary)) < 0)
1101                         return err;
1102         }
1103         if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_fm_vol, chip))) < 0)
1104                 return err;
1105         if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_pcm_vol, chip))) < 0)
1106                 return err;
1107         return 0;
1108 }
1109 
1110 
1111 /*
1112  * proc interface
1113  */
1114 
1115 static void snd_cs4281_proc_read(struct snd_info_entry *entry, 
1116                                   struct snd_info_buffer *buffer)
1117 {
1118         struct cs4281 *chip = entry->private_data;
1119 
1120         snd_iprintf(buffer, "Cirrus Logic CS4281\n\n");
1121         snd_iprintf(buffer, "Spurious half IRQs   : %u\n", chip->spurious_dhtc_irq);
1122         snd_iprintf(buffer, "Spurious end IRQs    : %u\n", chip->spurious_dtc_irq);
1123 }
1124 
1125 static ssize_t snd_cs4281_BA0_read(struct snd_info_entry *entry,
1126                                    void *file_private_data,
1127                                    struct file *file, char __user *buf,
1128                                    size_t count, loff_t pos)
1129 {
1130         struct cs4281 *chip = entry->private_data;
1131         
1132         if (copy_to_user_fromio(buf, chip->ba0 + pos, count))
1133                 return -EFAULT;
1134         return count;
1135 }
1136 
1137 static ssize_t snd_cs4281_BA1_read(struct snd_info_entry *entry,
1138                                    void *file_private_data,
1139                                    struct file *file, char __user *buf,
1140                                    size_t count, loff_t pos)
1141 {
1142         struct cs4281 *chip = entry->private_data;
1143         
1144         if (copy_to_user_fromio(buf, chip->ba1 + pos, count))
1145                 return -EFAULT;
1146         return count;
1147 }
1148 
1149 static struct snd_info_entry_ops snd_cs4281_proc_ops_BA0 = {
1150         .read = snd_cs4281_BA0_read,
1151 };
1152 
1153 static struct snd_info_entry_ops snd_cs4281_proc_ops_BA1 = {
1154         .read = snd_cs4281_BA1_read,
1155 };
1156 
1157 static void snd_cs4281_proc_init(struct cs4281 *chip)
1158 {
1159         struct snd_info_entry *entry;
1160 
1161         snd_card_ro_proc_new(chip->card, "cs4281", chip, snd_cs4281_proc_read);
1162         if (! snd_card_proc_new(chip->card, "cs4281_BA0", &entry)) {
1163                 entry->content = SNDRV_INFO_CONTENT_DATA;
1164                 entry->private_data = chip;
1165                 entry->c.ops = &snd_cs4281_proc_ops_BA0;
1166                 entry->size = CS4281_BA0_SIZE;
1167         }
1168         if (! snd_card_proc_new(chip->card, "cs4281_BA1", &entry)) {
1169                 entry->content = SNDRV_INFO_CONTENT_DATA;
1170                 entry->private_data = chip;
1171                 entry->c.ops = &snd_cs4281_proc_ops_BA1;
1172                 entry->size = CS4281_BA1_SIZE;
1173         }
1174 }
1175 
1176 /*
1177  * joystick support
1178  */
1179 
1180 #if IS_REACHABLE(CONFIG_GAMEPORT)
1181 
1182 static void snd_cs4281_gameport_trigger(struct gameport *gameport)
1183 {
1184         struct cs4281 *chip = gameport_get_port_data(gameport);
1185 
1186         if (snd_BUG_ON(!chip))
1187                 return;
1188         snd_cs4281_pokeBA0(chip, BA0_JSPT, 0xff);
1189 }
1190 
1191 static unsigned char snd_cs4281_gameport_read(struct gameport *gameport)
1192 {
1193         struct cs4281 *chip = gameport_get_port_data(gameport);
1194 
1195         if (snd_BUG_ON(!chip))
1196                 return 0;
1197         return snd_cs4281_peekBA0(chip, BA0_JSPT);
1198 }
1199 
1200 #ifdef COOKED_MODE
1201 static int snd_cs4281_gameport_cooked_read(struct gameport *gameport,
1202                                            int *axes, int *buttons)
1203 {
1204         struct cs4281 *chip = gameport_get_port_data(gameport);
1205         unsigned js1, js2, jst;
1206         
1207         if (snd_BUG_ON(!chip))
1208                 return 0;
1209 
1210         js1 = snd_cs4281_peekBA0(chip, BA0_JSC1);
1211         js2 = snd_cs4281_peekBA0(chip, BA0_JSC2);
1212         jst = snd_cs4281_peekBA0(chip, BA0_JSPT);
1213         
1214         *buttons = (~jst >> 4) & 0x0F; 
1215         
1216         axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
1217         axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
1218         axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
1219         axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
1220 
1221         for (jst = 0; jst < 4; ++jst)
1222                 if (axes[jst] == 0xFFFF) axes[jst] = -1;
1223         return 0;
1224 }
1225 #else
1226 #define snd_cs4281_gameport_cooked_read NULL
1227 #endif
1228 
1229 static int snd_cs4281_gameport_open(struct gameport *gameport, int mode)
1230 {
1231         switch (mode) {
1232 #ifdef COOKED_MODE
1233         case GAMEPORT_MODE_COOKED:
1234                 return 0;
1235 #endif
1236         case GAMEPORT_MODE_RAW:
1237                 return 0;
1238         default:
1239                 return -1;
1240         }
1241         return 0;
1242 }
1243 
1244 static int snd_cs4281_create_gameport(struct cs4281 *chip)
1245 {
1246         struct gameport *gp;
1247 
1248         chip->gameport = gp = gameport_allocate_port();
1249         if (!gp) {
1250                 dev_err(chip->card->dev,
1251                         "cannot allocate memory for gameport\n");
1252                 return -ENOMEM;
1253         }
1254 
1255         gameport_set_name(gp, "CS4281 Gameport");
1256         gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
1257         gameport_set_dev_parent(gp, &chip->pci->dev);
1258         gp->open = snd_cs4281_gameport_open;
1259         gp->read = snd_cs4281_gameport_read;
1260         gp->trigger = snd_cs4281_gameport_trigger;
1261         gp->cooked_read = snd_cs4281_gameport_cooked_read;
1262         gameport_set_port_data(gp, chip);
1263 
1264         snd_cs4281_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
1265         snd_cs4281_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
1266 
1267         gameport_register_port(gp);
1268 
1269         return 0;
1270 }
1271 
1272 static void snd_cs4281_free_gameport(struct cs4281 *chip)
1273 {
1274         if (chip->gameport) {
1275                 gameport_unregister_port(chip->gameport);
1276                 chip->gameport = NULL;
1277         }
1278 }
1279 #else
1280 static inline int snd_cs4281_create_gameport(struct cs4281 *chip) { return -ENOSYS; }
1281 static inline void snd_cs4281_free_gameport(struct cs4281 *chip) { }
1282 #endif /* IS_REACHABLE(CONFIG_GAMEPORT) */
1283 
1284 static int snd_cs4281_free(struct cs4281 *chip)
1285 {
1286         snd_cs4281_free_gameport(chip);
1287 
1288         if (chip->irq >= 0)
1289                 synchronize_irq(chip->irq);
1290 
1291         /* Mask interrupts */
1292         snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff);
1293         /* Stop the DLL Clock logic. */
1294         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1295         /* Sound System Power Management - Turn Everything OFF */
1296         snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
1297         /* PCI interface - D3 state */
1298         pci_set_power_state(chip->pci, PCI_D3hot);
1299 
1300         if (chip->irq >= 0)
1301                 free_irq(chip->irq, chip);
1302         iounmap(chip->ba0);
1303         iounmap(chip->ba1);
1304         pci_release_regions(chip->pci);
1305         pci_disable_device(chip->pci);
1306 
1307         kfree(chip);
1308         return 0;
1309 }
1310 
1311 static int snd_cs4281_dev_free(struct snd_device *device)
1312 {
1313         struct cs4281 *chip = device->device_data;
1314         return snd_cs4281_free(chip);
1315 }
1316 
1317 static int snd_cs4281_chip_init(struct cs4281 *chip); /* defined below */
1318 
1319 static int snd_cs4281_create(struct snd_card *card,
1320                              struct pci_dev *pci,
1321                              struct cs4281 **rchip,
1322                              int dual_codec)
1323 {
1324         struct cs4281 *chip;
1325         unsigned int tmp;
1326         int err;
1327         static struct snd_device_ops ops = {
1328                 .dev_free =     snd_cs4281_dev_free,
1329         };
1330 
1331         *rchip = NULL;
1332         if ((err = pci_enable_device(pci)) < 0)
1333                 return err;
1334         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1335         if (chip == NULL) {
1336                 pci_disable_device(pci);
1337                 return -ENOMEM;
1338         }
1339         spin_lock_init(&chip->reg_lock);
1340         chip->card = card;
1341         chip->pci = pci;
1342         chip->irq = -1;
1343         pci_set_master(pci);
1344         if (dual_codec < 0 || dual_codec > 3) {
1345                 dev_err(card->dev, "invalid dual_codec option %d\n", dual_codec);
1346                 dual_codec = 0;
1347         }
1348         chip->dual_codec = dual_codec;
1349 
1350         if ((err = pci_request_regions(pci, "CS4281")) < 0) {
1351                 kfree(chip);
1352                 pci_disable_device(pci);
1353                 return err;
1354         }
1355         chip->ba0_addr = pci_resource_start(pci, 0);
1356         chip->ba1_addr = pci_resource_start(pci, 1);
1357 
1358         chip->ba0 = pci_ioremap_bar(pci, 0);
1359         chip->ba1 = pci_ioremap_bar(pci, 1);
1360         if (!chip->ba0 || !chip->ba1) {
1361                 snd_cs4281_free(chip);
1362                 return -ENOMEM;
1363         }
1364         
1365         if (request_irq(pci->irq, snd_cs4281_interrupt, IRQF_SHARED,
1366                         KBUILD_MODNAME, chip)) {
1367                 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
1368                 snd_cs4281_free(chip);
1369                 return -ENOMEM;
1370         }
1371         chip->irq = pci->irq;
1372 
1373         tmp = snd_cs4281_chip_init(chip);
1374         if (tmp) {
1375                 snd_cs4281_free(chip);
1376                 return tmp;
1377         }
1378 
1379         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1380                 snd_cs4281_free(chip);
1381                 return err;
1382         }
1383 
1384         snd_cs4281_proc_init(chip);
1385 
1386         *rchip = chip;
1387         return 0;
1388 }
1389 
1390 static int snd_cs4281_chip_init(struct cs4281 *chip)
1391 {
1392         unsigned int tmp;
1393         unsigned long end_time;
1394         int retry_count = 2;
1395 
1396         /* Having EPPMC.FPDN=1 prevent proper chip initialisation */
1397         tmp = snd_cs4281_peekBA0(chip, BA0_EPPMC);
1398         if (tmp & BA0_EPPMC_FPDN)
1399                 snd_cs4281_pokeBA0(chip, BA0_EPPMC, tmp & ~BA0_EPPMC_FPDN);
1400 
1401       __retry:
1402         tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1403         if (tmp != BA0_CFLR_DEFAULT) {
1404                 snd_cs4281_pokeBA0(chip, BA0_CFLR, BA0_CFLR_DEFAULT);
1405                 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1406                 if (tmp != BA0_CFLR_DEFAULT) {
1407                         dev_err(chip->card->dev,
1408                                 "CFLR setup failed (0x%x)\n", tmp);
1409                         return -EIO;
1410                 }
1411         }
1412 
1413         /* Set the 'Configuration Write Protect' register
1414          * to 4281h.  Allows vendor-defined configuration
1415          * space between 0e4h and 0ffh to be written. */        
1416         snd_cs4281_pokeBA0(chip, BA0_CWPR, 0x4281);
1417         
1418         if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC1)) != (BA0_SERC1_SO1EN | BA0_SERC1_AC97)) {
1419                 dev_err(chip->card->dev,
1420                         "SERC1 AC'97 check failed (0x%x)\n", tmp);
1421                 return -EIO;
1422         }
1423         if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC2)) != (BA0_SERC2_SI1EN | BA0_SERC2_AC97)) {
1424                 dev_err(chip->card->dev,
1425                         "SERC2 AC'97 check failed (0x%x)\n", tmp);
1426                 return -EIO;
1427         }
1428 
1429         /* Sound System Power Management */
1430         snd_cs4281_pokeBA0(chip, BA0_SSPM, BA0_SSPM_MIXEN | BA0_SSPM_CSRCEN |
1431                                            BA0_SSPM_PSRCEN | BA0_SSPM_JSEN |
1432                                            BA0_SSPM_ACLEN | BA0_SSPM_FMEN);
1433 
1434         /* Serial Port Power Management */
1435         /* Blast the clock control register to zero so that the
1436          * PLL starts out in a known state, and blast the master serial
1437          * port control register to zero so that the serial ports also
1438          * start out in a known state. */
1439         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1440         snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
1441 
1442         /* Make ESYN go to zero to turn off
1443          * the Sync pulse on the AC97 link. */
1444         snd_cs4281_pokeBA0(chip, BA0_ACCTL, 0);
1445         udelay(50);
1446                 
1447         /*  Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
1448          *  spec) and then drive it high.  This is done for non AC97 modes since
1449          *  there might be logic external to the CS4281 that uses the ARST# line
1450          *  for a reset. */
1451         snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
1452         udelay(50);
1453         snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN);
1454         msleep(50);
1455 
1456         if (chip->dual_codec)
1457                 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN | BA0_SPMC_ASDI2E);
1458 
1459         /*
1460          *  Set the serial port timing configuration.
1461          */
1462         snd_cs4281_pokeBA0(chip, BA0_SERMC,
1463                            (chip->dual_codec ? BA0_SERMC_TCID(chip->dual_codec) : BA0_SERMC_TCID(1)) |
1464                            BA0_SERMC_PTC_AC97 | BA0_SERMC_MSPE);
1465 
1466         /*
1467          *  Start the DLL Clock logic.
1468          */
1469         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_DLLP);
1470         msleep(50);
1471         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_SWCE | BA0_CLKCR1_DLLP);
1472 
1473         /*
1474          * Wait for the DLL ready signal from the clock logic.
1475          */
1476         end_time = jiffies + HZ;
1477         do {
1478                 /*
1479                  *  Read the AC97 status register to see if we've seen a CODEC
1480                  *  signal from the AC97 codec.
1481                  */
1482                 if (snd_cs4281_peekBA0(chip, BA0_CLKCR1) & BA0_CLKCR1_DLLRDY)
1483                         goto __ok0;
1484                 schedule_timeout_uninterruptible(1);
1485         } while (time_after_eq(end_time, jiffies));
1486 
1487         dev_err(chip->card->dev, "DLLRDY not seen\n");
1488         return -EIO;
1489 
1490       __ok0:
1491 
1492         /*
1493          *  The first thing we do here is to enable sync generation.  As soon
1494          *  as we start receiving bit clock, we'll start producing the SYNC
1495          *  signal.
1496          */
1497         snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_ESYN);
1498 
1499         /*
1500          * Wait for the codec ready signal from the AC97 codec.
1501          */
1502         end_time = jiffies + HZ;
1503         do {
1504                 /*
1505                  *  Read the AC97 status register to see if we've seen a CODEC
1506                  *  signal from the AC97 codec.
1507                  */
1508                 if (snd_cs4281_peekBA0(chip, BA0_ACSTS) & BA0_ACSTS_CRDY)
1509                         goto __ok1;
1510                 schedule_timeout_uninterruptible(1);
1511         } while (time_after_eq(end_time, jiffies));
1512 
1513         dev_err(chip->card->dev,
1514                 "never read codec ready from AC'97 (0x%x)\n",
1515                 snd_cs4281_peekBA0(chip, BA0_ACSTS));
1516         return -EIO;
1517 
1518       __ok1:
1519         if (chip->dual_codec) {
1520                 end_time = jiffies + HZ;
1521                 do {
1522                         if (snd_cs4281_peekBA0(chip, BA0_ACSTS2) & BA0_ACSTS_CRDY)
1523                                 goto __codec2_ok;
1524                         schedule_timeout_uninterruptible(1);
1525                 } while (time_after_eq(end_time, jiffies));
1526                 dev_info(chip->card->dev,
1527                          "secondary codec doesn't respond. disable it...\n");
1528                 chip->dual_codec = 0;
1529         __codec2_ok: ;
1530         }
1531 
1532         /*
1533          *  Assert the valid frame signal so that we can start sending commands
1534          *  to the AC97 codec.
1535          */
1536 
1537         snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_VFRM | BA0_ACCTL_ESYN);
1538 
1539         /*
1540          *  Wait until we've sampled input slots 3 and 4 as valid, meaning that
1541          *  the codec is pumping ADC data across the AC-link.
1542          */
1543 
1544         end_time = jiffies + HZ;
1545         do {
1546                 /*
1547                  *  Read the input slot valid register and see if input slots 3
1548                  *  4 are valid yet.
1549                  */
1550                 if ((snd_cs4281_peekBA0(chip, BA0_ACISV) & (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) == (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4)))
1551                         goto __ok2;
1552                 schedule_timeout_uninterruptible(1);
1553         } while (time_after_eq(end_time, jiffies));
1554 
1555         if (--retry_count > 0)
1556                 goto __retry;
1557         dev_err(chip->card->dev, "never read ISV3 and ISV4 from AC'97\n");
1558         return -EIO;
1559 
1560       __ok2:
1561 
1562         /*
1563          *  Now, assert valid frame and the slot 3 and 4 valid bits.  This will
1564          *  commense the transfer of digital audio data to the AC97 codec.
1565          */
1566         snd_cs4281_pokeBA0(chip, BA0_ACOSV, BA0_ACOSV_SLV(3) | BA0_ACOSV_SLV(4));
1567 
1568         /*
1569          *  Initialize DMA structures
1570          */
1571         for (tmp = 0; tmp < 4; tmp++) {
1572                 struct cs4281_dma *dma = &chip->dma[tmp];
1573                 dma->regDBA = BA0_DBA0 + (tmp * 0x10);
1574                 dma->regDCA = BA0_DCA0 + (tmp * 0x10);
1575                 dma->regDBC = BA0_DBC0 + (tmp * 0x10);
1576                 dma->regDCC = BA0_DCC0 + (tmp * 0x10);
1577                 dma->regDMR = BA0_DMR0 + (tmp * 8);
1578                 dma->regDCR = BA0_DCR0 + (tmp * 8);
1579                 dma->regHDSR = BA0_HDSR0 + (tmp * 4);
1580                 dma->regFCR = BA0_FCR0 + (tmp * 4);
1581                 dma->regFSIC = BA0_FSIC0 + (tmp * 4);
1582                 dma->fifo_offset = tmp * CS4281_FIFO_SIZE;
1583                 snd_cs4281_pokeBA0(chip, dma->regFCR,
1584                                    BA0_FCR_LS(31) |
1585                                    BA0_FCR_RS(31) |
1586                                    BA0_FCR_SZ(CS4281_FIFO_SIZE) |
1587                                    BA0_FCR_OF(dma->fifo_offset));
1588         }
1589 
1590         chip->src_left_play_slot = 0;   /* AC'97 left PCM playback (3) */
1591         chip->src_right_play_slot = 1;  /* AC'97 right PCM playback (4) */
1592         chip->src_left_rec_slot = 10;   /* AC'97 left PCM record (3) */
1593         chip->src_right_rec_slot = 11;  /* AC'97 right PCM record (4) */
1594 
1595         /* Activate wave playback FIFO for FM playback */
1596         chip->dma[0].valFCR = BA0_FCR_FEN | BA0_FCR_LS(0) |
1597                               BA0_FCR_RS(1) |
1598                               BA0_FCR_SZ(CS4281_FIFO_SIZE) |
1599                               BA0_FCR_OF(chip->dma[0].fifo_offset);
1600         snd_cs4281_pokeBA0(chip, chip->dma[0].regFCR, chip->dma[0].valFCR);
1601         snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
1602                                             (chip->src_right_play_slot << 8) |
1603                                             (chip->src_left_rec_slot << 16) |
1604                                             (chip->src_right_rec_slot << 24));
1605 
1606         /* Initialize digital volume */
1607         snd_cs4281_pokeBA0(chip, BA0_PPLVC, 0);
1608         snd_cs4281_pokeBA0(chip, BA0_PPRVC, 0);
1609 
1610         /* Enable IRQs */
1611         snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1612         /* Unmask interrupts */
1613         snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff & ~(
1614                                         BA0_HISR_MIDI |
1615                                         BA0_HISR_DMAI |
1616                                         BA0_HISR_DMA(0) |
1617                                         BA0_HISR_DMA(1) |
1618                                         BA0_HISR_DMA(2) |
1619                                         BA0_HISR_DMA(3)));
1620         synchronize_irq(chip->irq);
1621 
1622         return 0;
1623 }
1624 
1625 /*
1626  *  MIDI section
1627  */
1628 
1629 static void snd_cs4281_midi_reset(struct cs4281 *chip)
1630 {
1631         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr | BA0_MIDCR_MRST);
1632         udelay(100);
1633         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1634 }
1635 
1636 static int snd_cs4281_midi_input_open(struct snd_rawmidi_substream *substream)
1637 {
1638         struct cs4281 *chip = substream->rmidi->private_data;
1639 
1640         spin_lock_irq(&chip->reg_lock);
1641         chip->midcr |= BA0_MIDCR_RXE;
1642         chip->midi_input = substream;
1643         if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
1644                 snd_cs4281_midi_reset(chip);
1645         } else {
1646                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1647         }
1648         spin_unlock_irq(&chip->reg_lock);
1649         return 0;
1650 }
1651 
1652 static int snd_cs4281_midi_input_close(struct snd_rawmidi_substream *substream)
1653 {
1654         struct cs4281 *chip = substream->rmidi->private_data;
1655 
1656         spin_lock_irq(&chip->reg_lock);
1657         chip->midcr &= ~(BA0_MIDCR_RXE | BA0_MIDCR_RIE);
1658         chip->midi_input = NULL;
1659         if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
1660                 snd_cs4281_midi_reset(chip);
1661         } else {
1662                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1663         }
1664         chip->uartm &= ~CS4281_MODE_INPUT;
1665         spin_unlock_irq(&chip->reg_lock);
1666         return 0;
1667 }
1668 
1669 static int snd_cs4281_midi_output_open(struct snd_rawmidi_substream *substream)
1670 {
1671         struct cs4281 *chip = substream->rmidi->private_data;
1672 
1673         spin_lock_irq(&chip->reg_lock);
1674         chip->uartm |= CS4281_MODE_OUTPUT;
1675         chip->midcr |= BA0_MIDCR_TXE;
1676         chip->midi_output = substream;
1677         if (!(chip->uartm & CS4281_MODE_INPUT)) {
1678                 snd_cs4281_midi_reset(chip);
1679         } else {
1680                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1681         }
1682         spin_unlock_irq(&chip->reg_lock);
1683         return 0;
1684 }
1685 
1686 static int snd_cs4281_midi_output_close(struct snd_rawmidi_substream *substream)
1687 {
1688         struct cs4281 *chip = substream->rmidi->private_data;
1689 
1690         spin_lock_irq(&chip->reg_lock);
1691         chip->midcr &= ~(BA0_MIDCR_TXE | BA0_MIDCR_TIE);
1692         chip->midi_output = NULL;
1693         if (!(chip->uartm & CS4281_MODE_INPUT)) {
1694                 snd_cs4281_midi_reset(chip);
1695         } else {
1696                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1697         }
1698         chip->uartm &= ~CS4281_MODE_OUTPUT;
1699         spin_unlock_irq(&chip->reg_lock);
1700         return 0;
1701 }
1702 
1703 static void snd_cs4281_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1704 {
1705         unsigned long flags;
1706         struct cs4281 *chip = substream->rmidi->private_data;
1707 
1708         spin_lock_irqsave(&chip->reg_lock, flags);
1709         if (up) {
1710                 if ((chip->midcr & BA0_MIDCR_RIE) == 0) {
1711                         chip->midcr |= BA0_MIDCR_RIE;
1712                         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1713                 }
1714         } else {
1715                 if (chip->midcr & BA0_MIDCR_RIE) {
1716                         chip->midcr &= ~BA0_MIDCR_RIE;
1717                         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1718                 }
1719         }
1720         spin_unlock_irqrestore(&chip->reg_lock, flags);
1721 }
1722 
1723 static void snd_cs4281_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1724 {
1725         unsigned long flags;
1726         struct cs4281 *chip = substream->rmidi->private_data;
1727         unsigned char byte;
1728 
1729         spin_lock_irqsave(&chip->reg_lock, flags);
1730         if (up) {
1731                 if ((chip->midcr & BA0_MIDCR_TIE) == 0) {
1732                         chip->midcr |= BA0_MIDCR_TIE;
1733                         /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
1734                         while ((chip->midcr & BA0_MIDCR_TIE) &&
1735                                (snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
1736                                 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
1737                                         chip->midcr &= ~BA0_MIDCR_TIE;
1738                                 } else {
1739                                         snd_cs4281_pokeBA0(chip, BA0_MIDWP, byte);
1740                                 }
1741                         }
1742                         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1743                 }
1744         } else {
1745                 if (chip->midcr & BA0_MIDCR_TIE) {
1746                         chip->midcr &= ~BA0_MIDCR_TIE;
1747                         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1748                 }
1749         }
1750         spin_unlock_irqrestore(&chip->reg_lock, flags);
1751 }
1752 
1753 static const struct snd_rawmidi_ops snd_cs4281_midi_output =
1754 {
1755         .open =         snd_cs4281_midi_output_open,
1756         .close =        snd_cs4281_midi_output_close,
1757         .trigger =      snd_cs4281_midi_output_trigger,
1758 };
1759 
1760 static const struct snd_rawmidi_ops snd_cs4281_midi_input =
1761 {
1762         .open =         snd_cs4281_midi_input_open,
1763         .close =        snd_cs4281_midi_input_close,
1764         .trigger =      snd_cs4281_midi_input_trigger,
1765 };
1766 
1767 static int snd_cs4281_midi(struct cs4281 *chip, int device)
1768 {
1769         struct snd_rawmidi *rmidi;
1770         int err;
1771 
1772         if ((err = snd_rawmidi_new(chip->card, "CS4281", device, 1, 1, &rmidi)) < 0)
1773                 return err;
1774         strcpy(rmidi->name, "CS4281");
1775         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs4281_midi_output);
1776         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs4281_midi_input);
1777         rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
1778         rmidi->private_data = chip;
1779         chip->rmidi = rmidi;
1780         return 0;
1781 }
1782 
1783 /*
1784  *  Interrupt handler
1785  */
1786 
1787 static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id)
1788 {
1789         struct cs4281 *chip = dev_id;
1790         unsigned int status, dma, val;
1791         struct cs4281_dma *cdma;
1792 
1793         if (chip == NULL)
1794                 return IRQ_NONE;
1795         status = snd_cs4281_peekBA0(chip, BA0_HISR);
1796         if ((status & 0x7fffffff) == 0) {
1797                 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1798                 return IRQ_NONE;
1799         }
1800 
1801         if (status & (BA0_HISR_DMA(0)|BA0_HISR_DMA(1)|BA0_HISR_DMA(2)|BA0_HISR_DMA(3))) {
1802                 for (dma = 0; dma < 4; dma++)
1803                         if (status & BA0_HISR_DMA(dma)) {
1804                                 cdma = &chip->dma[dma];
1805                                 spin_lock(&chip->reg_lock);
1806                                 /* ack DMA IRQ */
1807                                 val = snd_cs4281_peekBA0(chip, cdma->regHDSR);
1808                                 /* workaround, sometimes CS4281 acknowledges */
1809                                 /* end or middle transfer position twice */
1810                                 cdma->frag++;
1811                                 if ((val & BA0_HDSR_DHTC) && !(cdma->frag & 1)) {
1812                                         cdma->frag--;
1813                                         chip->spurious_dhtc_irq++;
1814                                         spin_unlock(&chip->reg_lock);
1815                                         continue;
1816                                 }
1817                                 if ((val & BA0_HDSR_DTC) && (cdma->frag & 1)) {
1818                                         cdma->frag--;
1819                                         chip->spurious_dtc_irq++;
1820                                         spin_unlock(&chip->reg_lock);
1821                                         continue;
1822                                 }
1823                                 spin_unlock(&chip->reg_lock);
1824                                 snd_pcm_period_elapsed(cdma->substream);
1825                         }
1826         }
1827 
1828         if ((status & BA0_HISR_MIDI) && chip->rmidi) {
1829                 unsigned char c;
1830                 
1831                 spin_lock(&chip->reg_lock);
1832                 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_RBE) == 0) {
1833                         c = snd_cs4281_peekBA0(chip, BA0_MIDRP);
1834                         if ((chip->midcr & BA0_MIDCR_RIE) == 0)
1835                                 continue;
1836                         snd_rawmidi_receive(chip->midi_input, &c, 1);
1837                 }
1838                 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
1839                         if ((chip->midcr & BA0_MIDCR_TIE) == 0)
1840                                 break;
1841                         if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1842                                 chip->midcr &= ~BA0_MIDCR_TIE;
1843                                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1844                                 break;
1845                         }
1846                         snd_cs4281_pokeBA0(chip, BA0_MIDWP, c);
1847                 }
1848                 spin_unlock(&chip->reg_lock);
1849         }
1850 
1851         /* EOI to the PCI part... reenables interrupts */
1852         snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1853 
1854         return IRQ_HANDLED;
1855 }
1856 
1857 
1858 /*
1859  * OPL3 command
1860  */
1861 static void snd_cs4281_opl3_command(struct snd_opl3 *opl3, unsigned short cmd,
1862                                     unsigned char val)
1863 {
1864         unsigned long flags;
1865         struct cs4281 *chip = opl3->private_data;
1866         void __iomem *port;
1867 
1868         if (cmd & OPL3_RIGHT)
1869                 port = chip->ba0 + BA0_B1AP; /* right port */
1870         else
1871                 port = chip->ba0 + BA0_B0AP; /* left port */
1872 
1873         spin_lock_irqsave(&opl3->reg_lock, flags);
1874 
1875         writel((unsigned int)cmd, port);
1876         udelay(10);
1877 
1878         writel((unsigned int)val, port + 4);
1879         udelay(30);
1880 
1881         spin_unlock_irqrestore(&opl3->reg_lock, flags);
1882 }
1883 
1884 static int snd_cs4281_probe(struct pci_dev *pci,
1885                             const struct pci_device_id *pci_id)
1886 {
1887         static int dev;
1888         struct snd_card *card;
1889         struct cs4281 *chip;
1890         struct snd_opl3 *opl3;
1891         int err;
1892 
1893         if (dev >= SNDRV_CARDS)
1894                 return -ENODEV;
1895         if (!enable[dev]) {
1896                 dev++;
1897                 return -ENOENT;
1898         }
1899 
1900         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1901                            0, &card);
1902         if (err < 0)
1903                 return err;
1904 
1905         if ((err = snd_cs4281_create(card, pci, &chip, dual_codec[dev])) < 0) {
1906                 snd_card_free(card);
1907                 return err;
1908         }
1909         card->private_data = chip;
1910 
1911         if ((err = snd_cs4281_mixer(chip)) < 0) {
1912                 snd_card_free(card);
1913                 return err;
1914         }
1915         if ((err = snd_cs4281_pcm(chip, 0)) < 0) {
1916                 snd_card_free(card);
1917                 return err;
1918         }
1919         if ((err = snd_cs4281_midi(chip, 0)) < 0) {
1920                 snd_card_free(card);
1921                 return err;
1922         }
1923         if ((err = snd_opl3_new(card, OPL3_HW_OPL3_CS4281, &opl3)) < 0) {
1924                 snd_card_free(card);
1925                 return err;
1926         }
1927         opl3->private_data = chip;
1928         opl3->command = snd_cs4281_opl3_command;
1929         snd_opl3_init(opl3);
1930         if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
1931                 snd_card_free(card);
1932                 return err;
1933         }
1934         snd_cs4281_create_gameport(chip);
1935         strcpy(card->driver, "CS4281");
1936         strcpy(card->shortname, "Cirrus Logic CS4281");
1937         sprintf(card->longname, "%s at 0x%lx, irq %d",
1938                 card->shortname,
1939                 chip->ba0_addr,
1940                 chip->irq);
1941 
1942         if ((err = snd_card_register(card)) < 0) {
1943                 snd_card_free(card);
1944                 return err;
1945         }
1946 
1947         pci_set_drvdata(pci, card);
1948         dev++;
1949         return 0;
1950 }
1951 
1952 static void snd_cs4281_remove(struct pci_dev *pci)
1953 {
1954         snd_card_free(pci_get_drvdata(pci));
1955 }
1956 
1957 /*
1958  * Power Management
1959  */
1960 #ifdef CONFIG_PM_SLEEP
1961 
1962 static int saved_regs[SUSPEND_REGISTERS] = {
1963         BA0_JSCTL,
1964         BA0_GPIOR,
1965         BA0_SSCR,
1966         BA0_MIDCR,
1967         BA0_SRCSA,
1968         BA0_PASR,
1969         BA0_CASR,
1970         BA0_DACSR,
1971         BA0_ADCSR,
1972         BA0_FMLVC,
1973         BA0_FMRVC,
1974         BA0_PPLVC,
1975         BA0_PPRVC,
1976 };
1977 
1978 #define CLKCR1_CKRA                             0x00010000L
1979 
1980 static int cs4281_suspend(struct device *dev)
1981 {
1982         struct snd_card *card = dev_get_drvdata(dev);
1983         struct cs4281 *chip = card->private_data;
1984         u32 ulCLK;
1985         unsigned int i;
1986 
1987         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1988         snd_ac97_suspend(chip->ac97);
1989         snd_ac97_suspend(chip->ac97_secondary);
1990 
1991         ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
1992         ulCLK |= CLKCR1_CKRA;
1993         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
1994 
1995         /* Disable interrupts. */
1996         snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_CHGM);
1997 
1998         /* remember the status registers */
1999         for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
2000                 if (saved_regs[i])
2001                         chip->suspend_regs[i] = snd_cs4281_peekBA0(chip, saved_regs[i]);
2002 
2003         /* Turn off the serial ports. */
2004         snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
2005 
2006         /* Power off FM, Joystick, AC link, */
2007         snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
2008 
2009         /* DLL off. */
2010         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
2011 
2012         /* AC link off. */
2013         snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
2014 
2015         ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2016         ulCLK &= ~CLKCR1_CKRA;
2017         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2018         return 0;
2019 }
2020 
2021 static int cs4281_resume(struct device *dev)
2022 {
2023         struct snd_card *card = dev_get_drvdata(dev);
2024         struct cs4281 *chip = card->private_data;
2025         unsigned int i;
2026         u32 ulCLK;
2027 
2028         ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2029         ulCLK |= CLKCR1_CKRA;
2030         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2031 
2032         snd_cs4281_chip_init(chip);
2033 
2034         /* restore the status registers */
2035         for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
2036                 if (saved_regs[i])
2037                         snd_cs4281_pokeBA0(chip, saved_regs[i], chip->suspend_regs[i]);
2038 
2039         snd_ac97_resume(chip->ac97);
2040         snd_ac97_resume(chip->ac97_secondary);
2041 
2042         ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2043         ulCLK &= ~CLKCR1_CKRA;
2044         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2045 
2046         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2047         return 0;
2048 }
2049 
2050 static SIMPLE_DEV_PM_OPS(cs4281_pm, cs4281_suspend, cs4281_resume);
2051 #define CS4281_PM_OPS   &cs4281_pm
2052 #else
2053 #define CS4281_PM_OPS   NULL
2054 #endif /* CONFIG_PM_SLEEP */
2055 
2056 static struct pci_driver cs4281_driver = {
2057         .name = KBUILD_MODNAME,
2058         .id_table = snd_cs4281_ids,
2059         .probe = snd_cs4281_probe,
2060         .remove = snd_cs4281_remove,
2061         .driver = {
2062                 .pm = CS4281_PM_OPS,
2063         },
2064 };
2065         
2066 module_pci_driver(cs4281_driver);
2067 

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