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TOMOYO Linux Cross Reference
Linux/sound/pci/cs4281.c

Version: ~ [ linux-5.2-rc1 ] ~ [ linux-5.1.2 ] ~ [ linux-5.0.16 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.43 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.119 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.176 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.179 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.19.8 ] ~ [ linux-3.18.139 ] ~ [ linux-3.17.8 ] ~ [ linux-3.16.67 ] ~ [ linux-3.15.10 ] ~ [ linux-3.14.79 ] ~ [ linux-3.13.11 ] ~ [ linux-3.12.74 ] ~ [ linux-3.11.10 ] ~ [ linux-3.10.108 ] ~ [ linux-3.9.11 ] ~ [ linux-3.8.13 ] ~ [ linux-3.7.10 ] ~ [ linux-3.6.11 ] ~ [ linux-3.5.7 ] ~ [ linux-3.4.113 ] ~ [ linux-3.3.8 ] ~ [ linux-3.2.102 ] ~ [ linux-3.1.10 ] ~ [ linux-3.0.101 ] ~ [ linux-2.6.39.4 ] ~ [ linux-2.6.38.8 ] ~ [ linux-2.6.37.6 ] ~ [ linux-2.6.36.4 ] ~ [ linux-2.6.35.14 ] ~ [ linux-2.6.34.15 ] ~ [ linux-2.6.33.20 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.5 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  *  Driver for Cirrus Logic CS4281 based PCI soundcard
  3  *  Copyright (c) by Jaroslav Kysela <perex@suse.cz>,
  4  *
  5  *
  6  *   This program is free software; you can redistribute it and/or modify
  7  *   it under the terms of the GNU General Public License as published by
  8  *   the Free Software Foundation; either version 2 of the License, or
  9  *   (at your option) any later version.
 10  *
 11  *   This program is distributed in the hope that it will be useful,
 12  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 13  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 14  *   GNU General Public License for more details.
 15  *
 16  *   You should have received a copy of the GNU General Public License
 17  *   along with this program; if not, write to the Free Software
 18  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 19  *
 20  */
 21 
 22 #include <sound/driver.h>
 23 #include <asm/io.h>
 24 #include <linux/delay.h>
 25 #include <linux/interrupt.h>
 26 #include <linux/init.h>
 27 #include <linux/pci.h>
 28 #include <linux/slab.h>
 29 #include <linux/gameport.h>
 30 #include <sound/core.h>
 31 #include <sound/control.h>
 32 #include <sound/pcm.h>
 33 #include <sound/rawmidi.h>
 34 #include <sound/ac97_codec.h>
 35 #include <sound/opl3.h>
 36 #define SNDRV_GET_ID
 37 #include <sound/initval.h>
 38 
 39 
 40 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
 41 MODULE_DESCRIPTION("Cirrus Logic CS4281");
 42 MODULE_LICENSE("GPL");
 43 MODULE_CLASSES("{sound}");
 44 MODULE_DEVICES("{{Cirrus Logic,CS4281}}");
 45 
 46 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
 47 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
 48 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;      /* Enable switches */
 49 static int dual_codec[SNDRV_CARDS];     /* dual codec */
 50 
 51 MODULE_PARM(index, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
 52 MODULE_PARM_DESC(index, "Index value for CS4281 soundcard.");
 53 MODULE_PARM_SYNTAX(index, SNDRV_INDEX_DESC);
 54 MODULE_PARM(id, "1-" __MODULE_STRING(SNDRV_CARDS) "s");
 55 MODULE_PARM_DESC(id, "ID string for CS4281 soundcard.");
 56 MODULE_PARM_SYNTAX(id, SNDRV_ID_DESC);
 57 MODULE_PARM(enable, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
 58 MODULE_PARM_DESC(enable, "Enable CS4281 soundcard.");
 59 MODULE_PARM_SYNTAX(enable, SNDRV_ENABLE_DESC);
 60 MODULE_PARM(dual_codec, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
 61 MODULE_PARM_DESC(dual_codec, "Secondary Codec ID (0 = disabled).");
 62 MODULE_PARM_SYNTAX(dual_codec, SNDRV_ENABLED ",allows:{{0,3}}");
 63 
 64 /*
 65  *
 66  */
 67 
 68 #ifndef PCI_VENDOR_ID_CIRRUS
 69 #define PCI_VENDOR_ID_CIRRUS            0x1013
 70 #endif
 71 #ifndef PCI_DEVICE_ID_CIRRUS_4281
 72 #define PCI_DEVICE_ID_CIRRUS_4281       0x6005
 73 #endif
 74 
 75 /*
 76  *  Direct registers
 77  */
 78 
 79 #define CS4281_BA0_SIZE         0x1000
 80 #define CS4281_BA1_SIZE         0x10000
 81 
 82 /*
 83  *  BA0 registers
 84  */
 85 #define BA0_HISR                0x0000  /* Host Interrupt Status Register */
 86 #define BA0_HISR_INTENA         (1<<31) /* Internal Interrupt Enable Bit */
 87 #define BA0_HISR_MIDI           (1<<22) /* MIDI port interrupt */
 88 #define BA0_HISR_FIFOI          (1<<20) /* FIFO polled interrupt */
 89 #define BA0_HISR_DMAI           (1<<18) /* DMA interrupt (half or end) */
 90 #define BA0_HISR_FIFO(c)        (1<<(12+(c))) /* FIFO channel interrupt */
 91 #define BA0_HISR_DMA(c)         (1<<(8+(c)))  /* DMA channel interrupt */
 92 #define BA0_HISR_GPPI           (1<<5)  /* General Purpose Input (Primary chip) */
 93 #define BA0_HISR_GPSI           (1<<4)  /* General Purpose Input (Secondary chip) */
 94 #define BA0_HISR_GP3I           (1<<3)  /* GPIO3 pin Interrupt */
 95 #define BA0_HISR_GP1I           (1<<2)  /* GPIO1 pin Interrupt */
 96 #define BA0_HISR_VUPI           (1<<1)  /* VOLUP pin Interrupt */
 97 #define BA0_HISR_VDNI           (1<<0)  /* VOLDN pin Interrupt */
 98 
 99 #define BA0_HICR                0x0008  /* Host Interrupt Control Register */
100 #define BA0_HICR_CHGM           (1<<1)  /* INTENA Change Mask */
101 #define BA0_HICR_IEV            (1<<0)  /* INTENA Value */
102 #define BA0_HICR_EOI            (3<<0)  /* End of Interrupt command */
103 
104 #define BA0_HIMR                0x000c  /* Host Interrupt Mask Register */
105                                         /* Use same contants as for BA0_HISR */
106 
107 #define BA0_IIER                0x0010  /* ISA Interrupt Enable Register */
108 
109 #define BA0_HDSR0               0x00f0  /* Host DMA Engine 0 Status Register */
110 #define BA0_HDSR1               0x00f4  /* Host DMA Engine 1 Status Register */
111 #define BA0_HDSR2               0x00f8  /* Host DMA Engine 2 Status Register */
112 #define BA0_HDSR3               0x00fc  /* Host DMA Engine 3 Status Register */
113 
114 #define BA0_HDSR_CH1P           (1<<25) /* Channel 1 Pending */
115 #define BA0_HDSR_CH2P           (1<<24) /* Channel 2 Pending */
116 #define BA0_HDSR_DHTC           (1<<17) /* DMA Half Terminal Count */
117 #define BA0_HDSR_DTC            (1<<16) /* DMA Terminal Count */
118 #define BA0_HDSR_DRUN           (1<<15) /* DMA Running */
119 #define BA0_HDSR_RQ             (1<<7)  /* Pending Request */
120 
121 #define BA0_DCA0                0x0110  /* Host DMA Engine 0 Current Address */
122 #define BA0_DCC0                0x0114  /* Host DMA Engine 0 Current Count */
123 #define BA0_DBA0                0x0118  /* Host DMA Engine 0 Base Address */
124 #define BA0_DBC0                0x011c  /* Host DMA Engine 0 Base Count */
125 #define BA0_DCA1                0x0120  /* Host DMA Engine 1 Current Address */
126 #define BA0_DCC1                0x0124  /* Host DMA Engine 1 Current Count */
127 #define BA0_DBA1                0x0128  /* Host DMA Engine 1 Base Address */
128 #define BA0_DBC1                0x012c  /* Host DMA Engine 1 Base Count */
129 #define BA0_DCA2                0x0130  /* Host DMA Engine 2 Current Address */
130 #define BA0_DCC2                0x0134  /* Host DMA Engine 2 Current Count */
131 #define BA0_DBA2                0x0138  /* Host DMA Engine 2 Base Address */
132 #define BA0_DBC2                0x013c  /* Host DMA Engine 2 Base Count */
133 #define BA0_DCA3                0x0140  /* Host DMA Engine 3 Current Address */
134 #define BA0_DCC3                0x0144  /* Host DMA Engine 3 Current Count */
135 #define BA0_DBA3                0x0148  /* Host DMA Engine 3 Base Address */
136 #define BA0_DBC3                0x014c  /* Host DMA Engine 3 Base Count */
137 #define BA0_DMR0                0x0150  /* Host DMA Engine 0 Mode */
138 #define BA0_DCR0                0x0154  /* Host DMA Engine 0 Command */
139 #define BA0_DMR1                0x0158  /* Host DMA Engine 1 Mode */
140 #define BA0_DCR1                0x015c  /* Host DMA Engine 1 Command */
141 #define BA0_DMR2                0x0160  /* Host DMA Engine 2 Mode */
142 #define BA0_DCR2                0x0164  /* Host DMA Engine 2 Command */
143 #define BA0_DMR3                0x0168  /* Host DMA Engine 3 Mode */
144 #define BA0_DCR3                0x016c  /* Host DMA Engine 3 Command */
145 
146 #define BA0_DMR_DMA             (1<<29) /* Enable DMA mode */
147 #define BA0_DMR_POLL            (1<<28) /* Enable poll mode */
148 #define BA0_DMR_TBC             (1<<25) /* Transfer By Channel */
149 #define BA0_DMR_CBC             (1<<24) /* Count By Channel (0 = frame resolution) */
150 #define BA0_DMR_SWAPC           (1<<22) /* Swap Left/Right Channels */
151 #define BA0_DMR_SIZE20          (1<<20) /* Sample is 20-bit */
152 #define BA0_DMR_USIGN           (1<<19) /* Unsigned */
153 #define BA0_DMR_BEND            (1<<18) /* Big Endian */
154 #define BA0_DMR_MONO            (1<<17) /* Mono */
155 #define BA0_DMR_SIZE8           (1<<16) /* Sample is 8-bit */
156 #define BA0_DMR_TYPE_DEMAND     (0<<6)
157 #define BA0_DMR_TYPE_SINGLE     (1<<6)
158 #define BA0_DMR_TYPE_BLOCK      (2<<6)
159 #define BA0_DMR_TYPE_CASCADE    (3<<6)  /* Not supported */
160 #define BA0_DMR_DEC             (1<<5)  /* Access Increment (0) or Decrement (1) */
161 #define BA0_DMR_AUTO            (1<<4)  /* Auto-Initialize */
162 #define BA0_DMR_TR_VERIFY       (0<<2)  /* Verify Transfer */
163 #define BA0_DMR_TR_WRITE        (1<<2)  /* Write Transfer */
164 #define BA0_DMR_TR_READ         (2<<2)  /* Read Transfer */
165 
166 #define BA0_DCR_HTCIE           (1<<17) /* Half Terminal Count Interrupt */
167 #define BA0_DCR_TCIE            (1<<16) /* Terminal Count Interrupt */
168 #define BA0_DCR_MSK             (1<<0)  /* DMA Mask bit */
169 
170 #define BA0_FCR0                0x0180  /* FIFO Control 0 */
171 #define BA0_FCR1                0x0184  /* FIFO Control 1 */
172 #define BA0_FCR2                0x0188  /* FIFO Control 2 */
173 #define BA0_FCR3                0x018c  /* FIFO Control 3 */
174 
175 #define BA0_FCR_FEN             (1<<31) /* FIFO Enable bit */
176 #define BA0_FCR_DACZ            (1<<30) /* DAC Zero */
177 #define BA0_FCR_PSH             (1<<29) /* Previous Sample Hold */
178 #define BA0_FCR_RS(x)           (((x)&0x1f)<<24) /* Right Slot Mapping */
179 #define BA0_FCR_LS(x)           (((x)&0x1f)<<16) /* Left Slot Mapping */
180 #define BA0_FCR_SZ(x)           (((x)&0x7f)<<8) /* FIFO buffer size (in samples) */
181 #define BA0_FCR_OF(x)           (((x)&0x7f)<<0) /* FIFO starting offset (in samples) */
182 
183 #define BA0_FPDR0               0x0190  /* FIFO Polled Data 0 */
184 #define BA0_FPDR1               0x0194  /* FIFO Polled Data 1 */
185 #define BA0_FPDR2               0x0198  /* FIFO Polled Data 2 */
186 #define BA0_FPDR3               0x019c  /* FIFO Polled Data 3 */
187 
188 #define BA0_FCHS                0x020c  /* FIFO Channel Status */
189 #define BA0_FCHS_RCO(x)         (1<<(7+(((x)&3)<<3))) /* Right Channel Out */
190 #define BA0_FCHS_LCO(x)         (1<<(6+(((x)&3)<<3))) /* Left Channel Out */
191 #define BA0_FCHS_MRP(x)         (1<<(5+(((x)&3)<<3))) /* Move Read Pointer */
192 #define BA0_FCHS_FE(x)          (1<<(4+(((x)&3)<<3))) /* FIFO Empty */
193 #define BA0_FCHS_FF(x)          (1<<(3+(((x)&3)<<3))) /* FIFO Full */
194 #define BA0_FCHS_IOR(x)         (1<<(2+(((x)&3)<<3))) /* Internal Overrun Flag */
195 #define BA0_FCHS_RCI(x)         (1<<(1+(((x)&3)<<3))) /* Right Channel In */
196 #define BA0_FCHS_LCI(x)         (1<<(0+(((x)&3)<<3))) /* Left Channel In */
197 
198 #define BA0_FSIC0               0x0210  /* FIFO Status and Interrupt Control 0 */
199 #define BA0_FSIC1               0x0214  /* FIFO Status and Interrupt Control 1 */
200 #define BA0_FSIC2               0x0218  /* FIFO Status and Interrupt Control 2 */
201 #define BA0_FSIC3               0x021c  /* FIFO Status and Interrupt Control 3 */
202 
203 #define BA0_FSIC_FIC(x)         (((x)&0x7f)<<24) /* FIFO Interrupt Count */
204 #define BA0_FSIC_FORIE          (1<<23) /* FIFO OverRun Interrupt Enable */
205 #define BA0_FSIC_FURIE          (1<<22) /* FIFO UnderRun Interrupt Enable */
206 #define BA0_FSIC_FSCIE          (1<<16) /* FIFO Sample Count Interrupt Enable */
207 #define BA0_FSIC_FSC(x)         (((x)&0x7f)<<8) /* FIFO Sample Count */
208 #define BA0_FSIC_FOR            (1<<7)  /* FIFO OverRun */
209 #define BA0_FSIC_FUR            (1<<6)  /* FIFO UnderRun */
210 #define BA0_FSIC_FSCR           (1<<0)  /* FIFO Sample Count Reached */
211 
212 #define BA0_PMCS                0x0344  /* Power Management Control/Status */
213 #define BA0_CWPR                0x03e0  /* Configuration Write Protect */
214 #define BA0_EPPMC               0x03e4  /* Extended PCI Power Management Control */
215 #define BA0_GPIOR               0x03e8  /* GPIO Pin Interface Register */
216 
217 #define BA0_SPMC                0x03ec  /* Serial Port Power Management Control (& ASDIN2 enable) */
218 #define BA0_SPMC_GIPPEN         (1<<15) /* GP INT Primary PME# Enable */
219 #define BA0_SPMC_GISPEN         (1<<14) /* GP INT Secondary PME# Enable */
220 #define BA0_SPMC_EESPD          (1<<9)  /* EEPROM Serial Port Disable */
221 #define BA0_SPMC_ASDI2E         (1<<8)  /* ASDIN2 Enable */
222 #define BA0_SPMC_ASDO           (1<<7)  /* Asynchronous ASDOUT Assertion */
223 #define BA0_SPMC_WUP2           (1<<3)  /* Wakeup for Secondary Input */
224 #define BA0_SPMC_WUP1           (1<<2)  /* Wakeup for Primary Input */
225 #define BA0_SPMC_ASYNC          (1<<1)  /* Asynchronous ASYNC Assertion */
226 #define BA0_SPMC_RSTN           (1<<0)  /* Reset Not! */
227 
228 #define BA0_CFLR                0x03f0  /* Configuration Load Register (EEPROM or BIOS) */
229 #define BA0_CFLR_DEFAULT        0x00000001 /* CFLR must be in AC97 link mode */
230 #define BA0_IISR                0x03f4  /* ISA Interrupt Select */
231 #define BA0_TMS                 0x03f8  /* Test Register */
232 #define BA0_SSVID               0x03fc  /* Subsystem ID register */
233 
234 #define BA0_CLKCR1              0x0400  /* Clock Control Register 1 */
235 #define BA0_CLKCR1_CLKON        (1<<25) /* Read Only */
236 #define BA0_CLKCR1_DLLRDY       (1<<24) /* DLL Ready */
237 #define BA0_CLKCR1_DLLOS        (1<<6)  /* DLL Output Select */
238 #define BA0_CLKCR1_SWCE         (1<<5)  /* Clock Enable */
239 #define BA0_CLKCR1_DLLP         (1<<4)  /* DLL PowerUp */
240 #define BA0_CLKCR1_DLLSS        (((x)&3)<<3) /* DLL Source Select */
241 
242 #define BA0_FRR                 0x0410  /* Feature Reporting Register */
243 #define BA0_SLT12O              0x041c  /* Slot 12 GPIO Output Register for AC-Link */
244 
245 #define BA0_SERMC               0x0420  /* Serial Port Master Control */
246 #define BA0_SERMC_FCRN          (1<<27) /* Force Codec Ready Not */
247 #define BA0_SERMC_ODSEN2        (1<<25) /* On-Demand Support Enable ASDIN2 */
248 #define BA0_SERMC_ODSEN1        (1<<24) /* On-Demand Support Enable ASDIN1 */
249 #define BA0_SERMC_SXLB          (1<<21) /* ASDIN2 to ASDOUT Loopback */
250 #define BA0_SERMC_SLB           (1<<20) /* ASDOUT to ASDIN2 Loopback */
251 #define BA0_SERMC_LOVF          (1<<19) /* Loopback Output Valid Frame bit */
252 #define BA0_SERMC_TCID(x)       (((x)&3)<<16) /* Target Secondary Codec ID */
253 #define BA0_SERMC_PXLB          (5<<1)  /* Primary Port External Loopback */
254 #define BA0_SERMC_PLB           (4<<1)  /* Primary Port Internal Loopback */
255 #define BA0_SERMC_PTC           (7<<1)  /* Port Timing Configuration */
256 #define BA0_SERMC_PTC_AC97      (1<<1)  /* AC97 mode */
257 #define BA0_SERMC_MSPE          (1<<0)  /* Master Serial Port Enable */
258 
259 #define BA0_SERC1               0x0428  /* Serial Port Configuration 1 */
260 #define BA0_SERC1_SO1F(x)       (((x)&7)>>1) /* Primary Output Port Format */
261 #define BA0_SERC1_AC97          (1<<1)
262 #define BA0_SERC1_SO1EN         (1<<0)  /* Primary Output Port Enable */
263 
264 #define BA0_SERC2               0x042c  /* Serial Port Configuration 2 */
265 #define BA0_SERC2_SI1F(x)       (((x)&7)>>1) /* Primary Input Port Format */
266 #define BA0_SERC2_AC97          (1<<1)
267 #define BA0_SERC2_SI1EN         (1<<0)  /* Primary Input Port Enable */
268 
269 #define BA0_SLT12M              0x045c  /* Slot 12 Monitor Register for Primary AC-Link */
270 
271 #define BA0_ACCTL               0x0460  /* AC'97 Control */
272 #define BA0_ACCTL_TC            (1<<6)  /* Target Codec */
273 #define BA0_ACCTL_CRW           (1<<4)  /* 0=Write, 1=Read Command */
274 #define BA0_ACCTL_DCV           (1<<3)  /* Dynamic Command Valid */
275 #define BA0_ACCTL_VFRM          (1<<2)  /* Valid Frame */
276 #define BA0_ACCTL_ESYN          (1<<1)  /* Enable Sync */
277 
278 #define BA0_ACSTS               0x0464  /* AC'97 Status */
279 #define BA0_ACSTS_VSTS          (1<<1)  /* Valid Status */
280 #define BA0_ACSTS_CRDY          (1<<0)  /* Codec Ready */
281 
282 #define BA0_ACOSV               0x0468  /* AC'97 Output Slot Valid */
283 #define BA0_ACOSV_SLV(x)        (1<<((x)-3))
284 
285 #define BA0_ACCAD               0x046c  /* AC'97 Command Address */
286 #define BA0_ACCDA               0x0470  /* AC'97 Command Data */
287 
288 #define BA0_ACISV               0x0474  /* AC'97 Input Slot Valid */
289 #define BA0_ACISV_SLV(x)        (1<<((x)-3))
290 
291 #define BA0_ACSAD               0x0478  /* AC'97 Status Address */
292 #define BA0_ACSDA               0x047c  /* AC'97 Status Data */
293 #define BA0_JSPT                0x0480  /* Joystick poll/trigger */
294 #define BA0_JSCTL               0x0484  /* Joystick control */
295 #define BA0_JSC1                0x0488  /* Joystick control */
296 #define BA0_JSC2                0x048c  /* Joystick control */
297 #define BA0_JSIO                0x04a0
298 
299 #define BA0_MIDCR               0x0490  /* MIDI Control */
300 #define BA0_MIDCR_MRST          (1<<5)  /* Reset MIDI Interface */
301 #define BA0_MIDCR_MLB           (1<<4)  /* MIDI Loop Back Enable */
302 #define BA0_MIDCR_TIE           (1<<3)  /* MIDI Transmuit Interrupt Enable */
303 #define BA0_MIDCR_RIE           (1<<2)  /* MIDI Receive Interrupt Enable */
304 #define BA0_MIDCR_RXE           (1<<1)  /* MIDI Receive Enable */
305 #define BA0_MIDCR_TXE           (1<<0)  /* MIDI Transmit Enable */
306 
307 #define BA0_MIDCMD              0x0494  /* MIDI Command (wo) */
308 
309 #define BA0_MIDSR               0x0494  /* MIDI Status (ro) */
310 #define BA0_MIDSR_RDA           (1<<15) /* Sticky bit (RBE 1->0) */
311 #define BA0_MIDSR_TBE           (1<<14) /* Sticky bit (TBF 0->1) */
312 #define BA0_MIDSR_RBE           (1<<7)  /* Receive Buffer Empty */
313 #define BA0_MIDSR_TBF           (1<<6)  /* Transmit Buffer Full */
314 
315 #define BA0_MIDWP               0x0498  /* MIDI Write */
316 #define BA0_MIDRP               0x049c  /* MIDI Read (ro) */
317 
318 #define BA0_AODSD1              0x04a8  /* AC'97 On-Demand Slot Disable for primary link (ro) */
319 #define BA0_AODSD1_NDS(x)       (1<<((x)-3))
320 
321 #define BA0_AODSD2              0x04ac  /* AC'97 On-Demand Slot Disable for secondary link (ro) */
322 #define BA0_AODSD2_NDS(x)       (1<<((x)-3))
323 
324 #define BA0_CFGI                0x04b0  /* Configure Interface (EEPROM interface) */
325 #define BA0_SLT12M2             0x04dc  /* Slot 12 Monitor Register 2 for secondary AC-link */
326 #define BA0_ACSTS2              0x04e4  /* AC'97 Status Register 2 */
327 #define BA0_ACISV2              0x04f4  /* AC'97 Input Slot Valid Register 2 */
328 #define BA0_ACSAD2              0x04f8  /* AC'97 Status Address Register 2 */
329 #define BA0_ACSDA2              0x04fc  /* AC'97 Status Data Register 2 */
330 #define BA0_FMSR                0x0730  /* FM Synthesis Status (ro) */
331 #define BA0_B0AP                0x0730  /* FM Bank 0 Address Port (wo) */
332 #define BA0_FMDP                0x0734  /* FM Data Port */
333 #define BA0_B1AP                0x0738  /* FM Bank 1 Address Port */
334 #define BA0_B1DP                0x073c  /* FM Bank 1 Data Port */
335 
336 #define BA0_SSPM                0x0740  /* Sound System Power Management */
337 #define BA0_SSPM_MIXEN          (1<<6)  /* Playback SRC + FM/Wavetable MIX */
338 #define BA0_SSPM_CSRCEN         (1<<5)  /* Capture Sample Rate Converter Enable */
339 #define BA0_SSPM_PSRCEN         (1<<4)  /* Playback Sample Rate Converter Enable */
340 #define BA0_SSPM_JSEN           (1<<3)  /* Joystick Enable */
341 #define BA0_SSPM_ACLEN          (1<<2)  /* Serial Port Engine and AC-Link Enable */
342 #define BA0_SSPM_FMEN           (1<<1)  /* FM Synthesis Block Enable */
343 
344 #define BA0_DACSR               0x0744  /* DAC Sample Rate - Playback SRC */
345 #define BA0_ADCSR               0x0748  /* ADC Sample Rate - Capture SRC */
346 
347 #define BA0_SSCR                0x074c  /* Sound System Control Register */
348 #define BA0_SSCR_HVS1           (1<<23) /* Hardwave Volume Step (0=1,1=2) */
349 #define BA0_SSCR_MVCS           (1<<19) /* Master Volume Codec Select */
350 #define BA0_SSCR_MVLD           (1<<18) /* Master Volume Line Out Disable */
351 #define BA0_SSCR_MVAD           (1<<17) /* Master Volume Alternate Out Disable */
352 #define BA0_SSCR_MVMD           (1<<16) /* Master Volume Mono Out Disable */
353 #define BA0_SSCR_XLPSRC         (1<<8)  /* External SRC Loopback Mode */
354 #define BA0_SSCR_LPSRC          (1<<7)  /* SRC Loopback Mode */
355 #define BA0_SSCR_CDTX           (1<<5)  /* CD Transfer Data */
356 #define BA0_SSCR_HVC            (1<<3)  /* Harware Volume Control Enable */
357 
358 #define BA0_FMLVC               0x0754  /* FM Synthesis Left Volume Control */
359 #define BA0_FMRVC               0x0758  /* FM Synthesis Right Volume Control */
360 #define BA0_SRCSA               0x075c  /* SRC Slot Assignments */
361 #define BA0_PPLVC               0x0760  /* PCM Playback Left Volume Control */
362 #define BA0_PPRVC               0x0764  /* PCM Playback Right Volume Control */
363 #define BA0_PASR                0x0768  /* playback sample rate */
364 #define BA0_CASR                0x076C  /* capture sample rate */
365 
366 /* Source Slot Numbers - Playback */
367 #define SRCSLOT_LEFT_PCM_PLAYBACK               0
368 #define SRCSLOT_RIGHT_PCM_PLAYBACK              1
369 #define SRCSLOT_PHONE_LINE_1_DAC                2
370 #define SRCSLOT_CENTER_PCM_PLAYBACK             3
371 #define SRCSLOT_LEFT_SURROUND_PCM_PLAYBACK      4
372 #define SRCSLOT_RIGHT_SURROUND_PCM_PLAYBACK     5
373 #define SRCSLOT_LFE_PCM_PLAYBACK                6
374 #define SRCSLOT_PHONE_LINE_2_DAC                7
375 #define SRCSLOT_HEADSET_DAC                     8
376 #define SRCSLOT_LEFT_WT                         29  /* invalid for BA0_SRCSA */
377 #define SRCSLOT_RIGHT_WT                        30  /* invalid for BA0_SRCSA */
378 
379 /* Source Slot Numbers - Capture */
380 #define SRCSLOT_LEFT_PCM_RECORD                 10
381 #define SRCSLOT_RIGHT_PCM_RECORD                11
382 #define SRCSLOT_PHONE_LINE_1_ADC                12
383 #define SRCSLOT_MIC_ADC                         13
384 #define SRCSLOT_PHONE_LINE_2_ADC                17
385 #define SRCSLOT_HEADSET_ADC                     18
386 #define SRCSLOT_SECONDARY_LEFT_PCM_RECORD       20
387 #define SRCSLOT_SECONDARY_RIGHT_PCM_RECORD      21
388 #define SRCSLOT_SECONDARY_PHONE_LINE_1_ADC      22
389 #define SRCSLOT_SECONDARY_MIC_ADC               23
390 #define SRCSLOT_SECONDARY_PHONE_LINE_2_ADC      27
391 #define SRCSLOT_SECONDARY_HEADSET_ADC           28
392 
393 /* Source Slot Numbers - Others */
394 #define SRCSLOT_POWER_DOWN                      31
395 
396 /* MIDI modes */
397 #define CS4281_MODE_OUTPUT              (1<<0)
398 #define CS4281_MODE_INPUT               (1<<1)
399 
400 /* joystick bits */
401 /* Bits for JSPT */
402 #define JSPT_CAX                                0x00000001
403 #define JSPT_CAY                                0x00000002
404 #define JSPT_CBX                                0x00000004
405 #define JSPT_CBY                                0x00000008
406 #define JSPT_BA1                                0x00000010
407 #define JSPT_BA2                                0x00000020
408 #define JSPT_BB1                                0x00000040
409 #define JSPT_BB2                                0x00000080
410 
411 /* Bits for JSCTL */
412 #define JSCTL_SP_MASK                           0x00000003
413 #define JSCTL_SP_SLOW                           0x00000000
414 #define JSCTL_SP_MEDIUM_SLOW                    0x00000001
415 #define JSCTL_SP_MEDIUM_FAST                    0x00000002
416 #define JSCTL_SP_FAST                           0x00000003
417 #define JSCTL_ARE                               0x00000004
418 
419 /* Data register pairs masks */
420 #define JSC1_Y1V_MASK                           0x0000FFFF
421 #define JSC1_X1V_MASK                           0xFFFF0000
422 #define JSC1_Y1V_SHIFT                          0
423 #define JSC1_X1V_SHIFT                          16
424 #define JSC2_Y2V_MASK                           0x0000FFFF
425 #define JSC2_X2V_MASK                           0xFFFF0000
426 #define JSC2_Y2V_SHIFT                          0
427 #define JSC2_X2V_SHIFT                          16
428 
429 /* JS GPIO */
430 #define JSIO_DAX                                0x00000001
431 #define JSIO_DAY                                0x00000002
432 #define JSIO_DBX                                0x00000004
433 #define JSIO_DBY                                0x00000008
434 #define JSIO_AXOE                               0x00000010
435 #define JSIO_AYOE                               0x00000020
436 #define JSIO_BXOE                               0x00000040
437 #define JSIO_BYOE                               0x00000080
438 
439 /*
440  *
441  */
442 
443 #define chip_t cs4281_t
444 
445 typedef struct snd_cs4281 cs4281_t;
446 typedef struct snd_cs4281_dma cs4281_dma_t;
447 
448 struct snd_cs4281_dma {
449         snd_pcm_substream_t *substream;
450         unsigned int regDBA;            /* offset to DBA register */
451         unsigned int regDCA;            /* offset to DCA register */
452         unsigned int regDBC;            /* offset to DBC register */
453         unsigned int regDCC;            /* offset to DCC register */
454         unsigned int regDMR;            /* offset to DMR register */
455         unsigned int regDCR;            /* offset to DCR register */
456         unsigned int regHDSR;           /* offset to HDSR register */
457         unsigned int regFCR;            /* offset to FCR register */
458         unsigned int regFSIC;           /* offset to FSIC register */
459         unsigned int valDMR;            /* DMA mode */
460         unsigned int valDCR;            /* DMA command */
461         unsigned int valFCR;            /* FIFO control */
462         unsigned int fifo_offset;       /* FIFO offset within BA1 */
463         unsigned char left_slot;        /* FIFO left slot */
464         unsigned char right_slot;       /* FIFO right slot */
465         int frag;                       /* period number */
466 };
467 
468 #define SUSPEND_REGISTERS       20
469 
470 struct snd_cs4281 {
471         int irq;
472 
473         unsigned long ba0;              /* virtual (accessible) address */
474         unsigned long ba1;              /* virtual (accessible) address */
475         unsigned long ba0_addr;
476         unsigned long ba1_addr;
477         struct resource *ba0_res;
478         struct resource *ba1_res;
479 
480         int dual_codec;
481 
482         ac97_t *ac97;
483         ac97_t *ac97_secondary;
484 
485         struct pci_dev *pci;
486         snd_card_t *card;
487         snd_pcm_t *pcm;
488         snd_rawmidi_t *rmidi;
489         snd_rawmidi_substream_t *midi_input;
490         snd_rawmidi_substream_t *midi_output;
491 
492         cs4281_dma_t dma[4];
493 
494         unsigned char src_left_play_slot;
495         unsigned char src_right_play_slot;
496         unsigned char src_left_rec_slot;
497         unsigned char src_right_rec_slot;
498 
499         unsigned int spurious_dhtc_irq;
500         unsigned int spurious_dtc_irq;
501 
502         spinlock_t reg_lock;
503         unsigned int midcr;
504         unsigned int uartm;
505 
506         struct snd_cs4281_gameport *gameport;
507 
508 #ifdef CONFIG_PM
509         u32 suspend_regs[SUSPEND_REGISTERS];
510 #endif
511 
512 };
513 
514 static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id, struct pt_regs *regs);
515 
516 static struct pci_device_id snd_cs4281_ids[] = {
517         { 0x1013, 0x6005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },   /* CS4281 */
518         { 0, }
519 };
520 
521 MODULE_DEVICE_TABLE(pci, snd_cs4281_ids);
522 
523 /*
524  *  constants
525  */
526 
527 #define CS4281_FIFO_SIZE        32
528 
529 /*
530  *  common I/O routines
531  */
532 
533 static void snd_cs4281_delay(unsigned int delay)
534 {
535         if (delay > 999) {
536                 unsigned long end_time;
537                 delay = (delay * HZ) / 1000000;
538                 if (delay < 1)
539                         delay = 1;
540                 end_time = jiffies + delay;
541                 do {
542                         set_current_state(TASK_UNINTERRUPTIBLE);
543                         schedule_timeout(1);
544                 } while (time_after_eq(end_time, jiffies));
545         } else {
546                 udelay(delay);
547         }
548 }
549 
550 inline static void snd_cs4281_delay_long(void)
551 {
552         set_current_state(TASK_UNINTERRUPTIBLE);
553         schedule_timeout(1);
554 }
555 
556 static inline void snd_cs4281_pokeBA0(cs4281_t *chip, unsigned long offset, unsigned int val)
557 {
558         writel(val, chip->ba0 + offset);
559 }
560 
561 static inline unsigned int snd_cs4281_peekBA0(cs4281_t *chip, unsigned long offset)
562 {
563         return readl(chip->ba0 + offset);
564 }
565 
566 static void snd_cs4281_ac97_write(ac97_t *ac97,
567                                    unsigned short reg, unsigned short val)
568 {
569         /*
570          *  1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
571          *  2. Write ACCDA = Command Data Register = 470h    for data to write to AC97
572          *  3. Write ACCTL = Control Register = 460h for initiating the write
573          *  4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
574          *  5. if DCV not cleared, break and return error
575          */
576         cs4281_t *chip = snd_magic_cast(cs4281_t, ac97->private_data, return);
577         int count;
578 
579         /*
580          *  Setup the AC97 control registers on the CS461x to send the
581          *  appropriate command to the AC97 to perform the read.
582          *  ACCAD = Command Address Register = 46Ch
583          *  ACCDA = Command Data Register = 470h
584          *  ACCTL = Control Register = 460h
585          *  set DCV - will clear when process completed
586          *  reset CRW - Write command
587          *  set VFRM - valid frame enabled
588          *  set ESYN - ASYNC generation enabled
589          *  set RSTN - ARST# inactive, AC97 codec not reset
590          */
591         snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
592         snd_cs4281_pokeBA0(chip, BA0_ACCDA, val);
593         snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_VFRM |
594                                             BA0_ACCTL_ESYN | (ac97->num ? BA0_ACCTL_TC : 0));
595         for (count = 0; count < 2000; count++) {
596                 /*
597                  *  First, we want to wait for a short time.
598                  */
599                 udelay(10);
600                 /*
601                  *  Now, check to see if the write has completed.
602                  *  ACCTL = 460h, DCV should be reset by now and 460h = 07h
603                  */
604                 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV)) {
605                         return;
606                 }
607         }
608         snd_printk(KERN_ERR "AC'97 write problem, reg = 0x%x, val = 0x%x\n", reg, val);
609 }
610 
611 static unsigned short snd_cs4281_ac97_read(ac97_t *ac97,
612                                             unsigned short reg)
613 {
614         cs4281_t *chip = snd_magic_cast(cs4281_t, ac97->private_data, return -ENXIO);
615         int count;
616         unsigned short result;
617         // FIXME: volatile is necessary in the following due to a bug of
618         // some gcc versions
619         volatile int ac97_num = ((volatile ac97_t *)ac97)->num;
620 
621         /*
622          *  1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
623          *  2. Write ACCDA = Command Data Register = 470h    for data to write to AC97 
624          *  3. Write ACCTL = Control Register = 460h for initiating the write
625          *  4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
626          *  5. if DCV not cleared, break and return error
627          *  6. Read ACSTS = Status Register = 464h, check VSTS bit
628          */
629 
630         snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
631 
632         /*
633          *  Setup the AC97 control registers on the CS461x to send the
634          *  appropriate command to the AC97 to perform the read.
635          *  ACCAD = Command Address Register = 46Ch
636          *  ACCDA = Command Data Register = 470h
637          *  ACCTL = Control Register = 460h
638          *  set DCV - will clear when process completed
639          *  set CRW - Read command
640          *  set VFRM - valid frame enabled
641          *  set ESYN - ASYNC generation enabled
642          *  set RSTN - ARST# inactive, AC97 codec not reset
643          */
644 
645         snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
646         snd_cs4281_pokeBA0(chip, BA0_ACCDA, 0);
647         snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_CRW |
648                                             BA0_ACCTL_VFRM | BA0_ACCTL_ESYN |
649                            (ac97_num ? BA0_ACCTL_TC : 0));
650 
651 
652         /*
653          *  Wait for the read to occur.
654          */
655         for (count = 0; count < 500; count++) {
656                 /*
657                  *  First, we want to wait for a short time.
658                  */
659                 udelay(10);
660                 /*
661                  *  Now, check to see if the read has completed.
662                  *  ACCTL = 460h, DCV should be reset by now and 460h = 17h
663                  */
664                 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV))
665                         goto __ok1;
666         }
667 
668         snd_printk(KERN_ERR "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
669         result = 0xffff;
670         goto __end;
671         
672       __ok1:
673         /*
674          *  Wait for the valid status bit to go active.
675          */
676         for (count = 0; count < 100; count++) {
677                 /*
678                  *  Read the AC97 status register.
679                  *  ACSTS = Status Register = 464h
680                  *  VSTS - Valid Status
681                  */
682                 if (snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSTS2 : BA0_ACSTS) & BA0_ACSTS_VSTS)
683                         goto __ok2;
684                 udelay(10);
685         }
686         
687         snd_printk(KERN_ERR "AC'97 read problem (ACSTS_VSTS), reg = 0x%x\n", reg);
688         result = 0xffff;
689         goto __end;
690 
691       __ok2:
692         /*
693          *  Read the data returned from the AC97 register.
694          *  ACSDA = Status Data Register = 474h
695          */
696         result = snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
697 
698       __end:
699         return result;
700 }
701 
702 /*
703  *  PCM part
704  */
705 
706 static int snd_cs4281_trigger(snd_pcm_substream_t *substream, int cmd)
707 {
708         cs4281_dma_t *dma = (cs4281_dma_t *)substream->runtime->private_data;
709         cs4281_t *chip = snd_pcm_substream_chip(substream);
710         unsigned long flags;
711 
712         spin_lock_irqsave(&chip->reg_lock, flags);
713         switch (cmd) {
714         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
715                 dma->valDCR |= BA0_DCR_MSK;
716                 dma->valFCR |= BA0_FCR_FEN;
717                 break;
718         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
719                 dma->valDCR &= ~BA0_DCR_MSK;
720                 dma->valFCR &= ~BA0_FCR_FEN;
721                 break;
722         case SNDRV_PCM_TRIGGER_START:
723         case SNDRV_PCM_TRIGGER_RESUME:
724                 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR & ~BA0_DMR_DMA);
725                 dma->valDMR |= BA0_DMR_DMA;
726                 dma->valDCR &= ~BA0_DCR_MSK;
727                 dma->valFCR |= BA0_FCR_FEN;
728                 break;
729         case SNDRV_PCM_TRIGGER_STOP:
730         case SNDRV_PCM_TRIGGER_SUSPEND:
731                 dma->valDMR &= ~(BA0_DMR_DMA|BA0_DMR_POLL);
732                 dma->valDCR |= BA0_DCR_MSK;
733                 dma->valFCR &= ~BA0_FCR_FEN;
734                 /* Leave wave playback FIFO enabled for FM */
735                 if (dma->regFCR != BA0_FCR0)
736                         dma->valFCR &= ~BA0_FCR_FEN;
737                 break;
738         default:
739                 spin_unlock_irqrestore(&chip->reg_lock, flags);
740                 return -EINVAL;
741         }
742         snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR);
743         snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR);
744         snd_cs4281_pokeBA0(chip, dma->regDCR, dma->valDCR);
745         spin_unlock_irqrestore(&chip->reg_lock, flags);
746         return 0;
747 }
748 
749 static unsigned int snd_cs4281_rate(unsigned int rate, unsigned int *real_rate)
750 {
751         unsigned int val = ~0;
752         
753         if (real_rate)
754                 *real_rate = rate;
755         /* special "hardcoded" rates */
756         switch (rate) {
757         case 8000:      return 5;
758         case 11025:     return 4;
759         case 16000:     return 3;
760         case 22050:     return 2;
761         case 44100:     return 1;
762         case 48000:     return 0;
763         default:
764                 goto __variable;
765         }
766       __variable:
767         val = 1536000 / rate;
768         if (real_rate)
769                 *real_rate = 1536000 / val;
770         return val;
771 }
772 
773 static void snd_cs4281_mode(cs4281_t *chip, cs4281_dma_t *dma, snd_pcm_runtime_t *runtime, int capture, int src)
774 {
775         int rec_mono;
776 
777         dma->valDMR = BA0_DMR_TYPE_SINGLE | BA0_DMR_AUTO |
778                       (capture ? BA0_DMR_TR_WRITE : BA0_DMR_TR_READ);
779         if (runtime->channels == 1)
780                 dma->valDMR |= BA0_DMR_MONO;
781         if (snd_pcm_format_unsigned(runtime->format) > 0)
782                 dma->valDMR |= BA0_DMR_USIGN;
783         if (snd_pcm_format_big_endian(runtime->format) > 0)
784                 dma->valDMR |= BA0_DMR_BEND;
785         switch (snd_pcm_format_width(runtime->format)) {
786         case 8: dma->valDMR |= BA0_DMR_SIZE8;
787                 if (runtime->channels == 1)
788                         dma->valDMR |= BA0_DMR_SWAPC;
789                 break;
790         case 32: dma->valDMR |= BA0_DMR_SIZE20; break;
791         }
792         dma->frag = 0;  /* for workaround */
793         dma->valDCR = BA0_DCR_TCIE | BA0_DCR_MSK;
794         if (runtime->buffer_size != runtime->period_size)
795                 dma->valDCR |= BA0_DCR_HTCIE;
796         /* Initialize DMA */
797         snd_cs4281_pokeBA0(chip, dma->regDBA, runtime->dma_addr);
798         snd_cs4281_pokeBA0(chip, dma->regDBC, runtime->buffer_size - 1);
799         rec_mono = (chip->dma[1].valDMR & BA0_DMR_MONO) == BA0_DMR_MONO;
800         snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
801                                             (chip->src_right_play_slot << 8) |
802                                             (chip->src_left_rec_slot << 16) |
803                                             ((rec_mono ? 31 : chip->src_right_rec_slot) << 24));
804         if (!src)
805                 goto __skip_src;
806         if (!capture) {
807                 if (dma->left_slot == chip->src_left_play_slot) {
808                         unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
809                         snd_assert(dma->right_slot == chip->src_right_play_slot, );
810                         snd_cs4281_pokeBA0(chip, BA0_DACSR, val);
811                 }
812         } else {
813                 if (dma->left_slot == chip->src_left_rec_slot) {
814                         unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
815                         snd_assert(dma->right_slot == chip->src_right_rec_slot, );
816                         snd_cs4281_pokeBA0(chip, BA0_ADCSR, val);
817                 }
818         }
819       __skip_src:
820         /* Deactivate wave playback FIFO before changing slot assignments */
821         if (dma->regFCR == BA0_FCR0)
822                 snd_cs4281_pokeBA0(chip, dma->regFCR, snd_cs4281_peekBA0(chip, dma->regFCR) & ~BA0_FCR_FEN);
823         /* Initialize FIFO */
824         dma->valFCR = BA0_FCR_LS(dma->left_slot) |
825                       BA0_FCR_RS(capture && (dma->valDMR & BA0_DMR_MONO) ? 31 : dma->right_slot) |
826                       BA0_FCR_SZ(CS4281_FIFO_SIZE) |
827                       BA0_FCR_OF(dma->fifo_offset);
828         snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | (capture ? BA0_FCR_PSH : 0));
829         /* Activate FIFO again for FM playback */
830         if (dma->regFCR == BA0_FCR0)
831                 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | BA0_FCR_FEN);
832         /* Clear FIFO Status and Interrupt Control Register */
833         snd_cs4281_pokeBA0(chip, dma->regFSIC, 0);
834 }
835 
836 static int snd_cs4281_hw_params(snd_pcm_substream_t * substream,
837                                 snd_pcm_hw_params_t * hw_params)
838 {
839         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
840 }
841 
842 static int snd_cs4281_hw_free(snd_pcm_substream_t * substream)
843 {
844         return snd_pcm_lib_free_pages(substream);
845 }
846 
847 static int snd_cs4281_playback_prepare(snd_pcm_substream_t * substream)
848 {
849         snd_pcm_runtime_t *runtime = substream->runtime;
850         cs4281_dma_t *dma = (cs4281_dma_t *)runtime->private_data;
851         cs4281_t *chip = snd_pcm_substream_chip(substream);
852         unsigned long flags;
853 
854         spin_lock_irqsave(&chip->reg_lock, flags);
855         snd_cs4281_mode(chip, dma, runtime, 0, 1);
856         spin_unlock_irqrestore(&chip->reg_lock, flags);
857         return 0;
858 }
859 
860 static int snd_cs4281_capture_prepare(snd_pcm_substream_t * substream)
861 {
862         snd_pcm_runtime_t *runtime = substream->runtime;
863         cs4281_dma_t *dma = (cs4281_dma_t *)runtime->private_data;
864         cs4281_t *chip = snd_pcm_substream_chip(substream);
865         unsigned long flags;
866 
867         spin_lock_irqsave(&chip->reg_lock, flags);
868         snd_cs4281_mode(chip, dma, runtime, 1, 1);
869         spin_unlock_irqrestore(&chip->reg_lock, flags);
870         return 0;
871 }
872 
873 static snd_pcm_uframes_t snd_cs4281_pointer(snd_pcm_substream_t * substream)
874 {
875         snd_pcm_runtime_t *runtime = substream->runtime;
876         cs4281_dma_t *dma = (cs4281_dma_t *)runtime->private_data;
877         cs4281_t *chip = snd_pcm_substream_chip(substream);
878 
879         // printk("DCC = 0x%x, buffer_size = 0x%x, jiffies = %li\n", snd_cs4281_peekBA0(chip, dma->regDCC), runtime->buffer_size, jiffies);
880         return runtime->buffer_size -
881                snd_cs4281_peekBA0(chip, dma->regDCC) - 1;
882 }
883 
884 static snd_pcm_hardware_t snd_cs4281_playback =
885 {
886         .info =                 (SNDRV_PCM_INFO_MMAP |
887                                  SNDRV_PCM_INFO_INTERLEAVED |
888                                  SNDRV_PCM_INFO_MMAP_VALID |
889                                  SNDRV_PCM_INFO_PAUSE |
890                                  SNDRV_PCM_INFO_RESUME |
891                                  SNDRV_PCM_INFO_SYNC_START),
892         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
893                                 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
894                                 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
895                                 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
896                                 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
897         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
898         .rate_min =             4000,
899         .rate_max =             48000,
900         .channels_min =         1,
901         .channels_max =         2,
902         .buffer_bytes_max =     (512*1024),
903         .period_bytes_min =     64,
904         .period_bytes_max =     (512*1024),
905         .periods_min =          1,
906         .periods_max =          2,
907         .fifo_size =            CS4281_FIFO_SIZE,
908 };
909 
910 static snd_pcm_hardware_t snd_cs4281_capture =
911 {
912         .info =                 (SNDRV_PCM_INFO_MMAP |
913                                  SNDRV_PCM_INFO_INTERLEAVED |
914                                  SNDRV_PCM_INFO_MMAP_VALID |
915                                  SNDRV_PCM_INFO_PAUSE |
916                                  SNDRV_PCM_INFO_RESUME |
917                                  SNDRV_PCM_INFO_SYNC_START),
918         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
919                                 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
920                                 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
921                                 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
922                                 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
923         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
924         .rate_min =             4000,
925         .rate_max =             48000,
926         .channels_min =         1,
927         .channels_max =         2,
928         .buffer_bytes_max =     (512*1024),
929         .period_bytes_min =     64,
930         .period_bytes_max =     (512*1024),
931         .periods_min =          1,
932         .periods_max =          2,
933         .fifo_size =            CS4281_FIFO_SIZE,
934 };
935 
936 static int snd_cs4281_playback_open(snd_pcm_substream_t * substream)
937 {
938         cs4281_t *chip = snd_pcm_substream_chip(substream);
939         snd_pcm_runtime_t *runtime = substream->runtime;
940         cs4281_dma_t *dma;
941 
942         dma = &chip->dma[0];
943         dma->substream = substream;
944         dma->left_slot = 0;
945         dma->right_slot = 1;
946         runtime->private_data = dma;
947         runtime->hw = snd_cs4281_playback;
948         snd_pcm_set_sync(substream);
949         /* should be detected from the AC'97 layer, but it seems
950            that although CS4297A rev B reports 18-bit ADC resolution,
951            samples are 20-bit */
952         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
953         return 0;
954 }
955 
956 static int snd_cs4281_capture_open(snd_pcm_substream_t * substream)
957 {
958         cs4281_t *chip = snd_pcm_substream_chip(substream);
959         snd_pcm_runtime_t *runtime = substream->runtime;
960         cs4281_dma_t *dma;
961 
962         dma = &chip->dma[1];
963         dma->substream = substream;
964         dma->left_slot = 10;
965         dma->right_slot = 11;
966         runtime->private_data = dma;
967         runtime->hw = snd_cs4281_capture;
968         snd_pcm_set_sync(substream);
969         /* should be detected from the AC'97 layer, but it seems
970            that although CS4297A rev B reports 18-bit ADC resolution,
971            samples are 20-bit */
972         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
973         return 0;
974 }
975 
976 static int snd_cs4281_playback_close(snd_pcm_substream_t * substream)
977 {
978         cs4281_dma_t *dma = (cs4281_dma_t *)substream->runtime->private_data;
979 
980         dma->substream = NULL;
981         return 0;
982 }
983 
984 static int snd_cs4281_capture_close(snd_pcm_substream_t * substream)
985 {
986         cs4281_dma_t *dma = (cs4281_dma_t *)substream->runtime->private_data;
987 
988         dma->substream = NULL;
989         return 0;
990 }
991 
992 static snd_pcm_ops_t snd_cs4281_playback_ops = {
993         .open =         snd_cs4281_playback_open,
994         .close =        snd_cs4281_playback_close,
995         .ioctl =        snd_pcm_lib_ioctl,
996         .hw_params =    snd_cs4281_hw_params,
997         .hw_free =      snd_cs4281_hw_free,
998         .prepare =      snd_cs4281_playback_prepare,
999         .trigger =      snd_cs4281_trigger,
1000         .pointer =      snd_cs4281_pointer,
1001 };
1002 
1003 static snd_pcm_ops_t snd_cs4281_capture_ops = {
1004         .open =         snd_cs4281_capture_open,
1005         .close =        snd_cs4281_capture_close,
1006         .ioctl =        snd_pcm_lib_ioctl,
1007         .hw_params =    snd_cs4281_hw_params,
1008         .hw_free =      snd_cs4281_hw_free,
1009         .prepare =      snd_cs4281_capture_prepare,
1010         .trigger =      snd_cs4281_trigger,
1011         .pointer =      snd_cs4281_pointer,
1012 };
1013 
1014 static void snd_cs4281_pcm_free(snd_pcm_t *pcm)
1015 {
1016         cs4281_t *chip = snd_magic_cast(cs4281_t, pcm->private_data, return);
1017         chip->pcm = NULL;
1018         snd_pcm_lib_preallocate_free_for_all(pcm);
1019 }
1020 
1021 static int __devinit snd_cs4281_pcm(cs4281_t * chip, int device, snd_pcm_t ** rpcm)
1022 {
1023         snd_pcm_t *pcm;
1024         int err;
1025 
1026         if (rpcm)
1027                 *rpcm = NULL;
1028         err = snd_pcm_new(chip->card, "CS4281", device, 1, 1, &pcm);
1029         if (err < 0)
1030                 return err;
1031 
1032         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4281_playback_ops);
1033         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4281_capture_ops);
1034 
1035         pcm->private_data = chip;
1036         pcm->private_free = snd_cs4281_pcm_free;
1037         pcm->info_flags = 0;
1038         strcpy(pcm->name, "CS4281");
1039         chip->pcm = pcm;
1040 
1041         snd_pcm_lib_preallocate_pci_pages_for_all(chip->pci, pcm, 64*1024, 512*1024);
1042 
1043         if (rpcm)
1044                 *rpcm = pcm;
1045         return 0;
1046 }
1047 
1048 /*
1049  *  Mixer section
1050  */
1051 
1052 #define CS_VOL_MASK     0x1f
1053 
1054 static int snd_cs4281_info_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_info_t * uinfo)
1055 {
1056         uinfo->type              = SNDRV_CTL_ELEM_TYPE_INTEGER;
1057         uinfo->count             = 2;
1058         uinfo->value.integer.min = 0;
1059         uinfo->value.integer.max = CS_VOL_MASK;
1060         return 0;
1061 }
1062  
1063 static int snd_cs4281_get_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1064 {
1065         cs4281_t *chip = snd_kcontrol_chip(kcontrol);
1066         int regL = (kcontrol->private_value >> 16) & 0xffff;
1067         int regR = kcontrol->private_value & 0xffff;
1068         int volL, volR;
1069 
1070         volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
1071         volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
1072 
1073         ucontrol->value.integer.value[0] = volL;
1074         ucontrol->value.integer.value[1] = volR;
1075         return 0;
1076 }
1077 
1078 static int snd_cs4281_put_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1079 {
1080         cs4281_t *chip = snd_kcontrol_chip(kcontrol);
1081         int change = 0;
1082         int regL = (kcontrol->private_value >> 16) & 0xffff;
1083         int regR = kcontrol->private_value & 0xffff;
1084         int volL, volR;
1085 
1086         volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
1087         volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
1088 
1089         if (ucontrol->value.integer.value[0] != volL) {
1090                 volL = CS_VOL_MASK - (ucontrol->value.integer.value[0] & CS_VOL_MASK);
1091                 snd_cs4281_pokeBA0(chip, regL, volL);
1092                 change = 1;
1093         }
1094         if (ucontrol->value.integer.value[0] != volL) {
1095                 volR = CS_VOL_MASK - (ucontrol->value.integer.value[1] & CS_VOL_MASK);
1096                 snd_cs4281_pokeBA0(chip, regR, volR);
1097                 change = 1;
1098         }
1099         return change;
1100 }
1101 
1102 static snd_kcontrol_new_t snd_cs4281_fm_vol = 
1103 {
1104         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1105         .name = "Synth Playback Volume",
1106         .info = snd_cs4281_info_volume, 
1107         .get = snd_cs4281_get_volume,
1108         .put = snd_cs4281_put_volume, 
1109         .private_value = ((BA0_FMLVC << 16) | BA0_FMRVC),
1110 };
1111 
1112 static snd_kcontrol_new_t snd_cs4281_pcm_vol = 
1113 {
1114         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1115         .name = "PCM Stream Playback Volume",
1116         .info = snd_cs4281_info_volume, 
1117         .get = snd_cs4281_get_volume,
1118         .put = snd_cs4281_put_volume, 
1119         .private_value = ((BA0_PPLVC << 16) | BA0_PPRVC),
1120 };
1121 
1122 static void snd_cs4281_mixer_free_ac97(ac97_t *ac97)
1123 {
1124         cs4281_t *chip = snd_magic_cast(cs4281_t, ac97->private_data, return);
1125         if (ac97->num)
1126                 chip->ac97_secondary = NULL;
1127         else
1128                 chip->ac97 = NULL;
1129 }
1130 
1131 static int __devinit snd_cs4281_mixer(cs4281_t * chip)
1132 {
1133         snd_card_t *card = chip->card;
1134         ac97_t ac97;
1135         int err;
1136 
1137         memset(&ac97, 0, sizeof(ac97));
1138         ac97.write = snd_cs4281_ac97_write;
1139         ac97.read = snd_cs4281_ac97_read;
1140         ac97.private_data = chip;
1141         ac97.private_free = snd_cs4281_mixer_free_ac97;
1142         if ((err = snd_ac97_mixer(card, &ac97, &chip->ac97)) < 0)
1143                 return err;
1144         if (chip->dual_codec) {
1145                 ac97.num = 1;
1146                 if ((err = snd_ac97_mixer(card, &ac97, &chip->ac97_secondary)) < 0)
1147                         return err;
1148         }
1149         if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_fm_vol, chip))) < 0)
1150                 return err;
1151         if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_pcm_vol, chip))) < 0)
1152                 return err;
1153         return 0;
1154 }
1155 
1156 
1157 /*
1158  * proc interface
1159  */
1160 
1161 static void snd_cs4281_proc_read(snd_info_entry_t *entry, 
1162                                   snd_info_buffer_t * buffer)
1163 {
1164         cs4281_t *chip = snd_magic_cast(cs4281_t, entry->private_data, return);
1165 
1166         snd_iprintf(buffer, "Cirrus Logic CS4281\n\n");
1167         snd_iprintf(buffer, "Spurious half IRQs   : %u\n", chip->spurious_dhtc_irq);
1168         snd_iprintf(buffer, "Spurious end IRQs    : %u\n", chip->spurious_dtc_irq);
1169 }
1170 
1171 static long snd_cs4281_BA0_read(snd_info_entry_t *entry, void *file_private_data,
1172                                 struct file *file, char *buf, long count)
1173 {
1174         long size;
1175         cs4281_t *chip = snd_magic_cast(cs4281_t, entry->private_data, return -ENXIO);
1176         
1177         size = count;
1178         if (file->f_pos + size > CS4281_BA0_SIZE)
1179                 size = (long)CS4281_BA0_SIZE - file->f_pos;
1180         if (size > 0) {
1181                 char *tmp;
1182                 long res;
1183                 unsigned long virt;
1184                 if ((tmp = kmalloc(size, GFP_KERNEL)) == NULL)
1185                         return -ENOMEM;
1186                 virt = chip->ba0 + file->f_pos;
1187                 memcpy_fromio(tmp, virt, size);
1188                 if (copy_to_user(buf, tmp, size))
1189                         res = -EFAULT;
1190                 else {
1191                         res = size;
1192                         file->f_pos += size;
1193                 }
1194                 kfree(tmp);
1195                 return res;
1196         }
1197         return 0;
1198 }
1199 
1200 static long snd_cs4281_BA1_read(snd_info_entry_t *entry, void *file_private_data,
1201                                 struct file *file, char *buf, long count)
1202 {
1203         long size;
1204         cs4281_t *chip = snd_magic_cast(cs4281_t, entry->private_data, return -ENXIO);
1205         
1206         size = count;
1207         if (file->f_pos + size > CS4281_BA1_SIZE)
1208                 size = (long)CS4281_BA1_SIZE - file->f_pos;
1209         if (size > 0) {
1210                 char *tmp;
1211                 long res;
1212                 unsigned long virt;
1213                 if ((tmp = kmalloc(size, GFP_KERNEL)) == NULL)
1214                         return -ENOMEM;
1215                 virt = chip->ba1 + file->f_pos;
1216                 memcpy_fromio(tmp, virt, size);
1217                 if (copy_to_user(buf, tmp, size))
1218                         res = -EFAULT;
1219                 else {
1220                         res = size;
1221                         file->f_pos += size;
1222                 }
1223                 kfree(tmp);
1224                 return res;
1225         }
1226         return 0;
1227 }
1228 
1229 static struct snd_info_entry_ops snd_cs4281_proc_ops_BA0 = {
1230         .read = snd_cs4281_BA0_read,
1231 };
1232 
1233 static struct snd_info_entry_ops snd_cs4281_proc_ops_BA1 = {
1234         .read = snd_cs4281_BA1_read,
1235 };
1236 
1237 static void __devinit snd_cs4281_proc_init(cs4281_t * chip)
1238 {
1239         snd_info_entry_t *entry;
1240 
1241         if (! snd_card_proc_new(chip->card, "cs4281", &entry))
1242                 snd_info_set_text_ops(entry, chip, snd_cs4281_proc_read);
1243         if (! snd_card_proc_new(chip->card, "cs4281_BA0", &entry)) {
1244                 entry->content = SNDRV_INFO_CONTENT_DATA;
1245                 entry->private_data = chip;
1246                 entry->c.ops = &snd_cs4281_proc_ops_BA0;
1247                 entry->size = CS4281_BA0_SIZE;
1248         }
1249         if (! snd_card_proc_new(chip->card, "cs4281_BA1", &entry)) {
1250                 entry->content = SNDRV_INFO_CONTENT_DATA;
1251                 entry->private_data = chip;
1252                 entry->c.ops = &snd_cs4281_proc_ops_BA1;
1253                 entry->size = CS4281_BA1_SIZE;
1254         }
1255 }
1256 
1257 /*
1258  * joystick support
1259  */
1260 
1261 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
1262 
1263 typedef struct snd_cs4281_gameport {
1264         struct gameport info;
1265         cs4281_t *chip;
1266 } cs4281_gameport_t;
1267 
1268 static void snd_cs4281_gameport_trigger(struct gameport *gameport)
1269 {
1270         cs4281_gameport_t *gp = (cs4281_gameport_t *)gameport;
1271         cs4281_t *chip;
1272         snd_assert(gp, return);
1273         chip = snd_magic_cast(cs4281_t, gp->chip, return);
1274         snd_cs4281_pokeBA0(chip, BA0_JSPT, 0xff);
1275 }
1276 
1277 static unsigned char snd_cs4281_gameport_read(struct gameport *gameport)
1278 {
1279         cs4281_gameport_t *gp = (cs4281_gameport_t *)gameport;
1280         cs4281_t *chip;
1281         snd_assert(gp, return 0);
1282         chip = snd_magic_cast(cs4281_t, gp->chip, return 0);
1283         return snd_cs4281_peekBA0(chip, BA0_JSPT);
1284 }
1285 
1286 #ifdef COOKED_MODE
1287 static int snd_cs4281_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons)
1288 {
1289         cs4281_gameport_t *gp = (cs4281_gameport_t *)gameport;
1290         cs4281_t *chip;
1291         unsigned js1, js2, jst;
1292         
1293         snd_assert(gp, return 0);
1294         chip = snd_magic_cast(cs4281_t, gp->chip, return 0);
1295 
1296         js1 = snd_cs4281_peekBA0(chip, BA0_JSC1);
1297         js2 = snd_cs4281_peekBA0(chip, BA0_JSC2);
1298         jst = snd_cs4281_peekBA0(chip, BA0_JSPT);
1299         
1300         *buttons = (~jst >> 4) & 0x0F; 
1301         
1302         axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
1303         axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
1304         axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
1305         axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
1306 
1307         for(jst=0;jst<4;++jst)
1308                 if(axes[jst]==0xFFFF) axes[jst] = -1;
1309         return 0;
1310 }
1311 #endif
1312 
1313 static int snd_cs4281_gameport_open(struct gameport *gameport, int mode)
1314 {
1315         switch (mode) {
1316 #ifdef COOKED_MODE
1317         case GAMEPORT_MODE_COOKED:
1318                 return 0;
1319 #endif
1320         case GAMEPORT_MODE_RAW:
1321                 return 0;
1322         default:
1323                 return -1;
1324         }
1325         return 0;
1326 }
1327 
1328 static void __devinit snd_cs4281_gameport(cs4281_t *chip)
1329 {
1330         cs4281_gameport_t *gp;
1331         gp = kmalloc(sizeof(*gp), GFP_KERNEL);
1332         if (! gp) {
1333                 snd_printk(KERN_ERR "cannot allocate gameport area\n");
1334                 return;
1335         }
1336         memset(gp, 0, sizeof(*gp));
1337         gp->info.open = snd_cs4281_gameport_open;
1338         gp->info.read = snd_cs4281_gameport_read;
1339         gp->info.trigger = snd_cs4281_gameport_trigger;
1340 #ifdef COOKED_MODE
1341         gp->info.cooked_read = snd_cs4281_gameport_cooked_read;
1342 #endif
1343         gp->chip = chip;
1344         chip->gameport = gp;
1345 
1346         snd_cs4281_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
1347         snd_cs4281_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
1348         gameport_register_port(&gp->info);
1349 }
1350 
1351 #else
1352 #define snd_cs4281_gameport(chip) /*NOP*/
1353 #endif /* CONFIG_GAMEPORT || (MODULE && CONFIG_GAMEPORT_MODULE) */
1354 
1355 
1356 /*
1357 
1358  */
1359 
1360 static int snd_cs4281_free(cs4281_t *chip)
1361 {
1362 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
1363         if (chip->gameport) {
1364                 gameport_unregister_port(&chip->gameport->info);
1365                 kfree(chip->gameport);
1366         }
1367 #endif
1368         if (chip->irq >= 0)
1369                 synchronize_irq(chip->irq);
1370 
1371         /* Mask interrupts */
1372         snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff);
1373         /* Stop the DLL Clock logic. */
1374         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1375         /* Sound System Power Management - Turn Everything OFF */
1376         snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
1377         /* PCI interface - D3 state */
1378         pci_set_power_state(chip->pci, 3);
1379 
1380         if (chip->ba0)
1381                 iounmap((void *) chip->ba0);
1382         if (chip->ba1)
1383                 iounmap((void *) chip->ba1);
1384         if (chip->ba0_res) {
1385                 release_resource(chip->ba0_res);
1386                 kfree_nocheck(chip->ba0_res);
1387         }
1388         if (chip->ba1_res) {
1389                 release_resource(chip->ba1_res);
1390                 kfree_nocheck(chip->ba1_res);
1391         }
1392         if (chip->irq >= 0)
1393                 free_irq(chip->irq, (void *)chip);
1394 
1395         snd_magic_kfree(chip);
1396         return 0;
1397 }
1398 
1399 static int snd_cs4281_dev_free(snd_device_t *device)
1400 {
1401         cs4281_t *chip = snd_magic_cast(cs4281_t, device->device_data, return -ENXIO);
1402         return snd_cs4281_free(chip);
1403 }
1404 
1405 static int snd_cs4281_chip_init(cs4281_t *chip); /* defined below */
1406 #ifdef CONFIG_PM
1407 static int snd_cs4281_set_power_state(snd_card_t *card, unsigned int power_state);
1408 #endif
1409 
1410 static int __devinit snd_cs4281_create(snd_card_t * card,
1411                                        struct pci_dev *pci,
1412                                        cs4281_t ** rchip,
1413                                        int dual_codec)
1414 {
1415         cs4281_t *chip;
1416         unsigned int tmp;
1417         int err;
1418         static snd_device_ops_t ops = {
1419                 .dev_free =     snd_cs4281_dev_free,
1420         };
1421 
1422         *rchip = NULL;
1423         if ((err = pci_enable_device(pci)) < 0)
1424                 return err;
1425         chip = snd_magic_kcalloc(cs4281_t, 0, GFP_KERNEL);
1426         if (chip == NULL)
1427                 return -ENOMEM;
1428         spin_lock_init(&chip->reg_lock);
1429         chip->card = card;
1430         chip->pci = pci;
1431         chip->irq = -1;
1432         chip->ba0_addr = pci_resource_start(pci, 0);
1433         chip->ba1_addr = pci_resource_start(pci, 1);
1434         pci_set_master(pci);
1435         if (dual_codec < 0 || dual_codec > 3) {
1436                 snd_printk(KERN_ERR "invalid dual_codec option %d\n", dual_codec);
1437                 dual_codec = 0;
1438         }
1439         chip->dual_codec = dual_codec;
1440 
1441         if ((chip->ba0_res = request_mem_region(chip->ba0_addr, CS4281_BA0_SIZE, "CS4281 BA0")) == NULL) {
1442                 snd_printk(KERN_ERR "unable to grab memory region 0x%lx-0x%lx\n", chip->ba0_addr, chip->ba0_addr + CS4281_BA0_SIZE - 1);
1443                 snd_cs4281_free(chip);
1444                 return -ENOMEM;
1445         }
1446         if ((chip->ba1_res = request_mem_region(chip->ba1_addr, CS4281_BA1_SIZE, "CS4281 BA1")) == NULL) {
1447                 snd_printk(KERN_ERR "unable to grab memory region 0x%lx-0x%lx\n", chip->ba1_addr, chip->ba1_addr + CS4281_BA1_SIZE - 1);
1448                 snd_cs4281_free(chip);
1449                 return -ENOMEM;
1450         }
1451         if (request_irq(pci->irq, snd_cs4281_interrupt, SA_INTERRUPT|SA_SHIRQ, "CS4281", (void *)chip)) {
1452                 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1453                 snd_cs4281_free(chip);
1454                 return -ENOMEM;
1455         }
1456         chip->irq = pci->irq;
1457 
1458         chip->ba0 = (unsigned long) ioremap_nocache(chip->ba0_addr, CS4281_BA0_SIZE);
1459         chip->ba1 = (unsigned long) ioremap_nocache(chip->ba1_addr, CS4281_BA1_SIZE);
1460         if (!chip->ba0 || !chip->ba1) {
1461                 snd_cs4281_free(chip);
1462                 return -ENOMEM;
1463         }
1464         
1465         tmp = snd_cs4281_chip_init(chip);
1466         if (tmp) {
1467                 snd_cs4281_free(chip);
1468                 return tmp;
1469         }
1470 
1471         snd_cs4281_proc_init(chip);
1472 
1473 #ifdef CONFIG_PM
1474         card->set_power_state = snd_cs4281_set_power_state;
1475         card->power_state_private_data = chip;
1476 #endif
1477 
1478         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1479                 snd_cs4281_free(chip);
1480                 return err;
1481         }
1482 
1483         *rchip = chip;
1484         return 0;
1485 }
1486 
1487 static int snd_cs4281_chip_init(cs4281_t *chip)
1488 {
1489         unsigned int tmp;
1490         int timeout;
1491 
1492         tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1493         if (tmp != BA0_CFLR_DEFAULT) {
1494                 snd_cs4281_pokeBA0(chip, BA0_CFLR, BA0_CFLR_DEFAULT);
1495                 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1496                 if (tmp != BA0_CFLR_DEFAULT) {
1497                         snd_printk(KERN_ERR "CFLR setup failed (0x%x)\n", tmp);
1498                         return -EIO;
1499                 }
1500         }
1501 
1502         /* Set the 'Configuration Write Protect' register
1503          * to 4281h.  Allows vendor-defined configuration
1504          * space between 0e4h and 0ffh to be written. */        
1505         snd_cs4281_pokeBA0(chip, BA0_CWPR, 0x4281);
1506         
1507         if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC1)) != (BA0_SERC1_SO1EN | BA0_SERC1_AC97)) {
1508                 snd_printk(KERN_ERR "SERC1 AC'97 check failed (0x%x)\n", tmp);
1509                 return -EIO;
1510         }
1511         if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC2)) != (BA0_SERC2_SI1EN | BA0_SERC2_AC97)) {
1512                 snd_printk(KERN_ERR "SERC2 AC'97 check failed (0x%x)\n", tmp);
1513                 return -EIO;
1514         }
1515 
1516         /* Sound System Power Management */
1517         snd_cs4281_pokeBA0(chip, BA0_SSPM, BA0_SSPM_MIXEN | BA0_SSPM_CSRCEN |
1518                                            BA0_SSPM_PSRCEN | BA0_SSPM_JSEN |
1519                                            BA0_SSPM_ACLEN | BA0_SSPM_FMEN);
1520 
1521         /* Serial Port Power Management */
1522         /* Blast the clock control register to zero so that the
1523          * PLL starts out in a known state, and blast the master serial
1524          * port control register to zero so that the serial ports also
1525          * start out in a known state. */
1526         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1527         snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
1528 
1529         /* Make ESYN go to zero to turn off
1530          * the Sync pulse on the AC97 link. */
1531         snd_cs4281_pokeBA0(chip, BA0_ACCTL, 0);
1532         udelay(50);
1533                 
1534         /*  Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
1535          *  spec) and then drive it high.  This is done for non AC97 modes since
1536          *  there might be logic external to the CS4281 that uses the ARST# line
1537          *  for a reset. */
1538         snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
1539         udelay(50);
1540         snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN);
1541         snd_cs4281_delay(50000);
1542 
1543         if (chip->dual_codec)
1544                 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN | BA0_SPMC_ASDI2E);
1545 
1546         /*
1547          *  Set the serial port timing configuration.
1548          */
1549         snd_cs4281_pokeBA0(chip, BA0_SERMC,
1550                            (chip->dual_codec ? BA0_SERMC_TCID(chip->dual_codec) : BA0_SERMC_TCID(1)) |
1551                            BA0_SERMC_PTC_AC97 | BA0_SERMC_MSPE);
1552 
1553         /*
1554          *  Start the DLL Clock logic.
1555          */
1556         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_DLLP);
1557         snd_cs4281_delay(50000);
1558         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_SWCE | BA0_CLKCR1_DLLP);
1559 
1560         /*
1561          * Wait for the DLL ready signal from the clock logic.
1562          */
1563         timeout = HZ;
1564         do {
1565                 /*
1566                  *  Read the AC97 status register to see if we've seen a CODEC
1567                  *  signal from the AC97 codec.
1568                  */
1569                 if (snd_cs4281_peekBA0(chip, BA0_CLKCR1) & BA0_CLKCR1_DLLRDY)
1570                         goto __ok0;
1571                 snd_cs4281_delay_long();
1572         } while (timeout-- > 0);
1573 
1574         snd_printk(KERN_ERR "DLLRDY not seen\n");
1575         return -EIO;
1576 
1577       __ok0:
1578 
1579         /*
1580          *  The first thing we do here is to enable sync generation.  As soon
1581          *  as we start receiving bit clock, we'll start producing the SYNC
1582          *  signal.
1583          */
1584         snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_ESYN);
1585 
1586         /*
1587          * Wait for the codec ready signal from the AC97 codec.
1588          */
1589         timeout = HZ;
1590         do {
1591                 /*
1592                  *  Read the AC97 status register to see if we've seen a CODEC
1593                  *  signal from the AC97 codec.
1594                  */
1595                 if (snd_cs4281_peekBA0(chip, BA0_ACSTS) & BA0_ACSTS_CRDY)
1596                         goto __ok1;
1597                 snd_cs4281_delay_long();
1598         } while (timeout-- > 0);
1599 
1600         snd_printk(KERN_ERR "never read codec ready from AC'97 (0x%x)\n", snd_cs4281_peekBA0(chip, BA0_ACSTS));
1601         return -EIO;
1602 
1603       __ok1:
1604         if (chip->dual_codec) {
1605                 timeout = HZ;
1606                 do {
1607                         if (snd_cs4281_peekBA0(chip, BA0_ACSTS2) & BA0_ACSTS_CRDY)
1608                                 goto __codec2_ok;
1609                         snd_cs4281_delay_long();
1610                 } while (timeout-- > 0);
1611                 snd_printk(KERN_INFO "secondary codec doesn't respond. disable it...\n");
1612                 chip->dual_codec = 0;
1613         __codec2_ok: ;
1614         }
1615 
1616         /*
1617          *  Assert the valid frame signal so that we can start sending commands
1618          *  to the AC97 codec.
1619          */
1620 
1621         snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_VFRM | BA0_ACCTL_ESYN);
1622 
1623         /*
1624          *  Wait until we've sampled input slots 3 and 4 as valid, meaning that
1625          *  the codec is pumping ADC data across the AC-link.
1626          */
1627 
1628         timeout = HZ;
1629         do {
1630                 /*
1631                  *  Read the input slot valid register and see if input slots 3
1632                  *  4 are valid yet.
1633                  */
1634                 if ((snd_cs4281_peekBA0(chip, BA0_ACISV) & (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) == (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4)))
1635                         goto __ok2;
1636                 snd_cs4281_delay_long();
1637         } while (timeout-- > 0);
1638 
1639         snd_printk(KERN_ERR "never read ISV3 and ISV4 from AC'97\n");
1640         return -EIO;
1641 
1642       __ok2:
1643 
1644         /*
1645          *  Now, assert valid frame and the slot 3 and 4 valid bits.  This will
1646          *  commense the transfer of digital audio data to the AC97 codec.
1647          */
1648         snd_cs4281_pokeBA0(chip, BA0_ACOSV, BA0_ACOSV_SLV(3) | BA0_ACOSV_SLV(4));
1649 
1650         /*
1651          *  Initialize DMA structures
1652          */
1653         for (tmp = 0; tmp < 4; tmp++) {
1654                 cs4281_dma_t *dma = &chip->dma[tmp];
1655                 dma->regDBA = BA0_DBA0 + (tmp * 0x10);
1656                 dma->regDCA = BA0_DCA0 + (tmp * 0x10);
1657                 dma->regDBC = BA0_DBC0 + (tmp * 0x10);
1658                 dma->regDCC = BA0_DCC0 + (tmp * 0x10);
1659                 dma->regDMR = BA0_DMR0 + (tmp * 8);
1660                 dma->regDCR = BA0_DCR0 + (tmp * 8);
1661                 dma->regHDSR = BA0_HDSR0 + (tmp * 4);
1662                 dma->regFCR = BA0_FCR0 + (tmp * 4);
1663                 dma->regFSIC = BA0_FSIC0 + (tmp * 4);
1664                 dma->fifo_offset = tmp * CS4281_FIFO_SIZE;
1665                 snd_cs4281_pokeBA0(chip, dma->regFCR,
1666                                    BA0_FCR_LS(31) |
1667                                    BA0_FCR_RS(31) |
1668                                    BA0_FCR_SZ(CS4281_FIFO_SIZE) |
1669                                    BA0_FCR_OF(dma->fifo_offset));
1670         }
1671 
1672         chip->src_left_play_slot = 0;   /* AC'97 left PCM playback (3) */
1673         chip->src_right_play_slot = 1;  /* AC'97 right PCM playback (4) */
1674         chip->src_left_rec_slot = 10;   /* AC'97 left PCM record (3) */
1675         chip->src_right_rec_slot = 11;  /* AC'97 right PCM record (4) */
1676 
1677         /* Activate wave playback FIFO for FM playback */
1678         chip->dma[0].valFCR = BA0_FCR_FEN | BA0_FCR_LS(0) |
1679                               BA0_FCR_RS(1) |
1680                               BA0_FCR_SZ(CS4281_FIFO_SIZE) |
1681                               BA0_FCR_OF(chip->dma[0].fifo_offset);
1682         snd_cs4281_pokeBA0(chip, chip->dma[0].regFCR, chip->dma[0].valFCR);
1683         snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
1684                                             (chip->src_right_play_slot << 8) |
1685                                             (chip->src_left_rec_slot << 16) |
1686                                             (chip->src_right_rec_slot << 24));
1687 
1688         /* Initialize digital volume */
1689         snd_cs4281_pokeBA0(chip, BA0_PPLVC, 0);
1690         snd_cs4281_pokeBA0(chip, BA0_PPRVC, 0);
1691 
1692         /* Enable IRQs */
1693         snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1694         /* Unmask interrupts */
1695         snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff & ~(
1696                                         BA0_HISR_MIDI |
1697                                         BA0_HISR_DMAI |
1698                                         BA0_HISR_DMA(0) |
1699                                         BA0_HISR_DMA(1) |
1700                                         BA0_HISR_DMA(2) |
1701                                         BA0_HISR_DMA(3)));
1702         synchronize_irq(chip->irq);
1703 
1704         return 0;
1705 }
1706 
1707 /*
1708  *  MIDI section
1709  */
1710 
1711 static void snd_cs4281_midi_reset(cs4281_t *chip)
1712 {
1713         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr | BA0_MIDCR_MRST);
1714         udelay(100);
1715         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1716 }
1717 
1718 static int snd_cs4281_midi_input_open(snd_rawmidi_substream_t * substream)
1719 {
1720         unsigned long flags;
1721         cs4281_t *chip = snd_magic_cast(cs4281_t, substream->rmidi->private_data, return -ENXIO);
1722 
1723         spin_lock_irqsave(&chip->reg_lock, flags);
1724         chip->midcr |= BA0_MIDCR_RXE;
1725         chip->midi_input = substream;
1726         if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
1727                 snd_cs4281_midi_reset(chip);
1728         } else {
1729                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1730         }
1731         spin_unlock_irqrestore(&chip->reg_lock, flags);
1732         return 0;
1733 }
1734 
1735 static int snd_cs4281_midi_input_close(snd_rawmidi_substream_t * substream)
1736 {
1737         unsigned long flags;
1738         cs4281_t *chip = snd_magic_cast(cs4281_t, substream->rmidi->private_data, return -ENXIO);
1739 
1740         spin_lock_irqsave(&chip->reg_lock, flags);
1741         chip->midcr &= ~(BA0_MIDCR_RXE | BA0_MIDCR_RIE);
1742         chip->midi_input = NULL;
1743         if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
1744                 snd_cs4281_midi_reset(chip);
1745         } else {
1746                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1747         }
1748         chip->uartm &= ~CS4281_MODE_INPUT;
1749         spin_unlock_irqrestore(&chip->reg_lock, flags);
1750         return 0;
1751 }
1752 
1753 static int snd_cs4281_midi_output_open(snd_rawmidi_substream_t * substream)
1754 {
1755         unsigned long flags;
1756         cs4281_t *chip = snd_magic_cast(cs4281_t, substream->rmidi->private_data, return -ENXIO);
1757 
1758         spin_lock_irqsave(&chip->reg_lock, flags);
1759         chip->uartm |= CS4281_MODE_OUTPUT;
1760         chip->midcr |= BA0_MIDCR_TXE;
1761         chip->midi_output = substream;
1762         if (!(chip->uartm & CS4281_MODE_INPUT)) {
1763                 snd_cs4281_midi_reset(chip);
1764         } else {
1765                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1766         }
1767         spin_unlock_irqrestore(&chip->reg_lock, flags);
1768         return 0;
1769 }
1770 
1771 static int snd_cs4281_midi_output_close(snd_rawmidi_substream_t * substream)
1772 {
1773         unsigned long flags;
1774         cs4281_t *chip = snd_magic_cast(cs4281_t, substream->rmidi->private_data, return -ENXIO);
1775 
1776         spin_lock_irqsave(&chip->reg_lock, flags);
1777         chip->midcr &= ~(BA0_MIDCR_TXE | BA0_MIDCR_TIE);
1778         chip->midi_output = NULL;
1779         if (!(chip->uartm & CS4281_MODE_INPUT)) {
1780                 snd_cs4281_midi_reset(chip);
1781         } else {
1782                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1783         }
1784         chip->uartm &= ~CS4281_MODE_OUTPUT;
1785         spin_unlock_irqrestore(&chip->reg_lock, flags);
1786         return 0;
1787 }
1788 
1789 static void snd_cs4281_midi_input_trigger(snd_rawmidi_substream_t * substream, int up)
1790 {
1791         unsigned long flags;
1792         cs4281_t *chip = snd_magic_cast(cs4281_t, substream->rmidi->private_data, return);
1793 
1794         spin_lock_irqsave(&chip->reg_lock, flags);
1795         if (up) {
1796                 if ((chip->midcr & BA0_MIDCR_RIE) == 0) {
1797                         chip->midcr |= BA0_MIDCR_RIE;
1798                         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1799                 }
1800         } else {
1801                 if (chip->midcr & BA0_MIDCR_RIE) {
1802                         chip->midcr &= ~BA0_MIDCR_RIE;
1803                         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1804                 }
1805         }
1806         spin_unlock_irqrestore(&chip->reg_lock, flags);
1807 }
1808 
1809 static void snd_cs4281_midi_output_trigger(snd_rawmidi_substream_t * substream, int up)
1810 {
1811         unsigned long flags;
1812         cs4281_t *chip = snd_magic_cast(cs4281_t, substream->rmidi->private_data, return);
1813         unsigned char byte;
1814 
1815         spin_lock_irqsave(&chip->reg_lock, flags);
1816         if (up) {
1817                 if ((chip->midcr & BA0_MIDCR_TIE) == 0) {
1818                         chip->midcr |= BA0_MIDCR_TIE;
1819                         /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
1820                         while ((chip->midcr & BA0_MIDCR_TIE) &&
1821                                (snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
1822                                 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
1823                                         chip->midcr &= ~BA0_MIDCR_TIE;
1824                                 } else {
1825                                         snd_cs4281_pokeBA0(chip, BA0_MIDWP, byte);
1826                                 }
1827                         }
1828                         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1829                 }
1830         } else {
1831                 if (chip->midcr & BA0_MIDCR_TIE) {
1832                         chip->midcr &= ~BA0_MIDCR_TIE;
1833                         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1834                 }
1835         }
1836         spin_unlock_irqrestore(&chip->reg_lock, flags);
1837 }
1838 
1839 static snd_rawmidi_ops_t snd_cs4281_midi_output =
1840 {
1841         .open =         snd_cs4281_midi_output_open,
1842         .close =        snd_cs4281_midi_output_close,
1843         .trigger =      snd_cs4281_midi_output_trigger,
1844 };
1845 
1846 static snd_rawmidi_ops_t snd_cs4281_midi_input =
1847 {
1848         .open =         snd_cs4281_midi_input_open,
1849         .close =        snd_cs4281_midi_input_close,
1850         .trigger =      snd_cs4281_midi_input_trigger,
1851 };
1852 
1853 static int __devinit snd_cs4281_midi(cs4281_t * chip, int device, snd_rawmidi_t **rrawmidi)
1854 {
1855         snd_rawmidi_t *rmidi;
1856         int err;
1857 
1858         if (rrawmidi)
1859                 *rrawmidi = NULL;
1860         if ((err = snd_rawmidi_new(chip->card, "CS4281", device, 1, 1, &rmidi)) < 0)
1861                 return err;
1862         strcpy(rmidi->name, "CS4281");
1863         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs4281_midi_output);
1864         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs4281_midi_input);
1865         rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
1866         rmidi->private_data = chip;
1867         chip->rmidi = rmidi;
1868         if (rrawmidi)
1869                 *rrawmidi = rmidi;
1870         return 0;
1871 }
1872 
1873 /*
1874  *  Interrupt handler
1875  */
1876 
1877 static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1878 {
1879         cs4281_t *chip = snd_magic_cast(cs4281_t, dev_id, return IRQ_NONE);
1880         unsigned int status, dma, val;
1881         cs4281_dma_t *cdma;
1882 
1883         if (chip == NULL)
1884                 return IRQ_NONE;
1885         status = snd_cs4281_peekBA0(chip, BA0_HISR);
1886         if ((status & 0x7fffffff) == 0) {
1887                 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1888                 return IRQ_NONE;
1889         }
1890 
1891         if (status & (BA0_HISR_DMA(0)|BA0_HISR_DMA(1)|BA0_HISR_DMA(2)|BA0_HISR_DMA(3))) {
1892                 for (dma = 0; dma < 4; dma++)
1893                         if (status & BA0_HISR_DMA(dma)) {
1894                                 cdma = &chip->dma[dma];
1895                                 spin_lock(&chip->reg_lock);
1896                                 /* ack DMA IRQ */
1897                                 val = snd_cs4281_peekBA0(chip, cdma->regHDSR);
1898                                 /* workaround, sometimes CS4281 acknowledges */
1899                                 /* end or middle transfer position twice */
1900                                 cdma->frag++;
1901                                 if ((val & BA0_HDSR_DHTC) && !(cdma->frag & 1)) {
1902                                         cdma->frag--;
1903                                         chip->spurious_dhtc_irq++;
1904                                         spin_unlock(&chip->reg_lock);
1905                                         continue;
1906                                 }
1907                                 if ((val & BA0_HDSR_DTC) && (cdma->frag & 1)) {
1908                                         cdma->frag--;
1909                                         chip->spurious_dtc_irq++;
1910                                         spin_unlock(&chip->reg_lock);
1911                                         continue;
1912                                 }
1913                                 spin_unlock(&chip->reg_lock);
1914                                 snd_pcm_period_elapsed(cdma->substream);
1915                         }
1916         }
1917 
1918         if ((status & BA0_HISR_MIDI) && chip->rmidi) {
1919                 unsigned char c;
1920                 
1921                 spin_lock(&chip->reg_lock);
1922                 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_RBE) == 0) {
1923                         c = snd_cs4281_peekBA0(chip, BA0_MIDRP);
1924                         if ((chip->midcr & BA0_MIDCR_RIE) == 0)
1925                                 continue;
1926                         snd_rawmidi_receive(chip->midi_input, &c, 1);
1927                 }
1928                 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
1929                         if ((chip->midcr & BA0_MIDCR_TIE) == 0)
1930                                 break;
1931                         if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1932                                 chip->midcr &= ~BA0_MIDCR_TIE;
1933                                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1934                                 break;
1935                         }
1936                         snd_cs4281_pokeBA0(chip, BA0_MIDWP, c);
1937                 }
1938                 spin_unlock(&chip->reg_lock);
1939         }
1940 
1941         /* EOI to the PCI part... reenables interrupts */
1942         snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1943 
1944         return IRQ_HANDLED;
1945 }
1946 
1947 
1948 static int __devinit snd_cs4281_probe(struct pci_dev *pci,
1949                                       const struct pci_device_id *pci_id)
1950 {
1951         static int dev;
1952         snd_card_t *card;
1953         cs4281_t *chip;
1954         opl3_t *opl3;
1955         int err;
1956 
1957         if (dev >= SNDRV_CARDS)
1958                 return -ENODEV;
1959         if (!enable[dev]) {
1960                 dev++;
1961                 return -ENOENT;
1962         }
1963 
1964         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
1965         if (card == NULL)
1966                 return -ENOMEM;
1967 
1968         if ((err = snd_cs4281_create(card, pci, &chip, dual_codec[dev])) < 0) {
1969                 snd_card_free(card);
1970                 return err;
1971         }
1972 
1973         if ((err = snd_cs4281_mixer(chip)) < 0) {
1974                 snd_card_free(card);
1975                 return err;
1976         }
1977         if ((err = snd_cs4281_pcm(chip, 0, NULL)) < 0) {
1978                 snd_card_free(card);
1979                 return err;
1980         }
1981         if ((err = snd_cs4281_midi(chip, 0, NULL)) < 0) {
1982                 snd_card_free(card);
1983                 return err;
1984         }
1985         if ((err = snd_opl3_create(card,
1986                                    (chip->ba0 + BA0_B0AP) >> 2,
1987                                    (chip->ba0 + BA0_B1AP) >> 2,
1988                                    OPL3_HW_OPL3_CS4281, 1, &opl3)) < 0) {
1989                 snd_card_free(card);
1990                 return err;
1991         }
1992         if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
1993                 snd_card_free(card);
1994                 return err;
1995         }
1996         snd_cs4281_gameport(chip);
1997         strcpy(card->driver, "CS4281");
1998         strcpy(card->shortname, "Cirrus Logic CS4281");
1999         sprintf(card->longname, "%s at 0x%lx, irq %d",
2000                 card->shortname,
2001                 chip->ba0_addr,
2002                 chip->irq);
2003 
2004         if ((err = snd_card_register(card)) < 0) {
2005                 snd_card_free(card);
2006                 return err;
2007         }
2008 
2009         pci_set_drvdata(pci, chip);
2010         dev++;
2011         return 0;
2012 }
2013 
2014 static void __devexit snd_cs4281_remove(struct pci_dev *pci)
2015 {
2016         cs4281_t *chip = pci_get_drvdata(pci);
2017         snd_card_free(chip->card);
2018         pci_set_drvdata(pci, NULL);
2019 }
2020 
2021 /*
2022  * Power Management
2023  */
2024 #ifdef CONFIG_PM
2025 
2026 static int saved_regs[SUSPEND_REGISTERS] = {
2027         BA0_JSCTL,
2028         BA0_GPIOR,
2029         BA0_SSCR,
2030         BA0_MIDCR,
2031         BA0_SRCSA,
2032         BA0_PASR,
2033         BA0_CASR,
2034         BA0_DACSR,
2035         BA0_ADCSR,
2036         BA0_FMLVC,
2037         BA0_FMRVC,
2038         BA0_PPLVC,
2039         BA0_PPRVC,
2040 };
2041 
2042 #define number_of(array)        (sizeof(array) / sizeof(array[0]))
2043 
2044 #define CLKCR1_CKRA                             0x00010000L
2045 
2046 static void cs4281_suspend(cs4281_t *chip)
2047 {
2048         snd_card_t *card = chip->card;
2049         u32 ulCLK;
2050         unsigned int i;
2051 
2052         if (card->power_state == SNDRV_CTL_POWER_D3hot)
2053                 return;
2054 
2055         snd_pcm_suspend_all(chip->pcm);
2056 
2057         ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2058         ulCLK |= CLKCR1_CKRA;
2059         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2060 
2061         /* Disable interrupts. */
2062         snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_CHGM);
2063 
2064         /* remember the status registers */
2065         for (i = 0; i < number_of(saved_regs); i++)
2066                 if (saved_regs[i])
2067                         chip->suspend_regs[i] = snd_cs4281_peekBA0(chip, saved_regs[i]);
2068 
2069         /* Turn off the serial ports. */
2070         snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
2071 
2072         /* Power off FM, Joystick, AC link, */
2073         snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
2074 
2075         /* DLL off. */
2076         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
2077 
2078         /* AC link off. */
2079         snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
2080 
2081         ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2082         ulCLK &= ~CLKCR1_CKRA;
2083         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2084 
2085         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2086 }
2087 
2088 static void cs4281_resume(cs4281_t *chip)
2089 {
2090         snd_card_t *card = chip->card;
2091         unsigned int i;
2092         u32 ulCLK;
2093 
2094         if (card->power_state == SNDRV_CTL_POWER_D0)
2095                 return;
2096 
2097         pci_enable_device(chip->pci);
2098 
2099         ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2100         ulCLK |= CLKCR1_CKRA;
2101         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2102 
2103         snd_cs4281_chip_init(chip);
2104 
2105         /* restore the status registers */
2106         for (i = 0; i < number_of(saved_regs); i++)
2107                 if (saved_regs[i])
2108                         snd_cs4281_pokeBA0(chip, saved_regs[i], chip->suspend_regs[i]);
2109 
2110         if (chip->ac97)
2111                 snd_ac97_resume(chip->ac97);
2112         if (chip->ac97_secondary)
2113                 snd_ac97_resume(chip->ac97_secondary);
2114 
2115         ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2116         ulCLK &= ~CLKCR1_CKRA;
2117         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2118 
2119         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2120 }
2121 
2122 static int snd_cs4281_suspend(struct pci_dev *dev, u32 state)
2123 {
2124         cs4281_t *chip = snd_magic_cast(cs4281_t, pci_get_drvdata(dev), return -ENXIO);
2125         cs4281_suspend(chip);
2126         return 0;
2127 }
2128 static int snd_cs4281_resume(struct pci_dev *dev)
2129 {
2130         cs4281_t *chip = snd_magic_cast(cs4281_t, pci_get_drvdata(dev), return -ENXIO);
2131         cs4281_resume(chip);
2132         return 0;
2133 }
2134 
2135 /* callback */
2136 static int snd_cs4281_set_power_state(snd_card_t *card, unsigned int power_state)
2137 {
2138         cs4281_t *chip = snd_magic_cast(cs4281_t, card->power_state_private_data, return -ENXIO);
2139         switch (power_state) {
2140         case SNDRV_CTL_POWER_D0:
2141         case SNDRV_CTL_POWER_D1:
2142         case SNDRV_CTL_POWER_D2:
2143                 cs4281_resume(chip);
2144                 break;
2145         case SNDRV_CTL_POWER_D3hot:
2146         case SNDRV_CTL_POWER_D3cold:
2147                 cs4281_suspend(chip);
2148                 break;
2149         default:
2150                 return -EINVAL;
2151         }
2152         return 0;
2153 }
2154 
2155 #endif /* CONFIG_PM */
2156 
2157 static struct pci_driver driver = {
2158         .name = "CS4281",
2159         .id_table = snd_cs4281_ids,
2160         .probe = snd_cs4281_probe,
2161         .remove = __devexit_p(snd_cs4281_remove),
2162 #ifdef CONFIG_PM
2163         .suspend = snd_cs4281_suspend,
2164         .resume = snd_cs4281_resume,
2165 #endif
2166 };
2167         
2168 static int __init alsa_card_cs4281_init(void)
2169 {
2170         int err;
2171 
2172         if ((err = pci_module_init(&driver)) < 0) {
2173 #ifdef MODULE
2174                 printk(KERN_ERR "CS4281 soundcard not found or device busy\n");
2175 #endif
2176                 return err;
2177         }
2178         return 0;
2179 }
2180 
2181 static void __exit alsa_card_cs4281_exit(void)
2182 {
2183         pci_unregister_driver(&driver);
2184 }
2185 
2186 module_init(alsa_card_cs4281_init)
2187 module_exit(alsa_card_cs4281_exit)
2188 
2189 #ifndef MODULE
2190 
2191 /* format is: snd-cs4281=enable,index,id */
2192 
2193 static int __init alsa_card_cs4281_setup(char *str)
2194 {
2195         static unsigned __initdata nr_dev = 0;
2196 
2197         if (nr_dev >= SNDRV_CARDS)
2198                 return 0;
2199         (void)(get_option(&str,&enable[nr_dev]) == 2 &&
2200                get_option(&str,&index[nr_dev]) == 2 &&
2201                get_id(&str,&id[nr_dev]) == 2);
2202         nr_dev++;
2203         return 1;
2204 }
2205 
2206 __setup("snd-cs4281=", alsa_card_cs4281_setup);
2207 
2208 #endif /* ifndef MODULE */
2209 

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