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TOMOYO Linux Cross Reference
Linux/sound/pci/cs4281.c

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  1 // SPDX-License-Identifier: GPL-2.0-or-later
  2 /*
  3  *  Driver for Cirrus Logic CS4281 based PCI soundcard
  4  *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
  5  */
  6 
  7 #include <linux/io.h>
  8 #include <linux/delay.h>
  9 #include <linux/interrupt.h>
 10 #include <linux/init.h>
 11 #include <linux/pci.h>
 12 #include <linux/slab.h>
 13 #include <linux/gameport.h>
 14 #include <linux/module.h>
 15 #include <sound/core.h>
 16 #include <sound/control.h>
 17 #include <sound/pcm.h>
 18 #include <sound/rawmidi.h>
 19 #include <sound/ac97_codec.h>
 20 #include <sound/tlv.h>
 21 #include <sound/opl3.h>
 22 #include <sound/initval.h>
 23 
 24 
 25 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
 26 MODULE_DESCRIPTION("Cirrus Logic CS4281");
 27 MODULE_LICENSE("GPL");
 28 
 29 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
 30 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
 31 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;     /* Enable switches */
 32 static bool dual_codec[SNDRV_CARDS];    /* dual codec */
 33 
 34 module_param_array(index, int, NULL, 0444);
 35 MODULE_PARM_DESC(index, "Index value for CS4281 soundcard.");
 36 module_param_array(id, charp, NULL, 0444);
 37 MODULE_PARM_DESC(id, "ID string for CS4281 soundcard.");
 38 module_param_array(enable, bool, NULL, 0444);
 39 MODULE_PARM_DESC(enable, "Enable CS4281 soundcard.");
 40 module_param_array(dual_codec, bool, NULL, 0444);
 41 MODULE_PARM_DESC(dual_codec, "Secondary Codec ID (0 = disabled).");
 42 
 43 /*
 44  *  Direct registers
 45  */
 46 
 47 #define CS4281_BA0_SIZE         0x1000
 48 #define CS4281_BA1_SIZE         0x10000
 49 
 50 /*
 51  *  BA0 registers
 52  */
 53 #define BA0_HISR                0x0000  /* Host Interrupt Status Register */
 54 #define BA0_HISR_INTENA         (1<<31) /* Internal Interrupt Enable Bit */
 55 #define BA0_HISR_MIDI           (1<<22) /* MIDI port interrupt */
 56 #define BA0_HISR_FIFOI          (1<<20) /* FIFO polled interrupt */
 57 #define BA0_HISR_DMAI           (1<<18) /* DMA interrupt (half or end) */
 58 #define BA0_HISR_FIFO(c)        (1<<(12+(c))) /* FIFO channel interrupt */
 59 #define BA0_HISR_DMA(c)         (1<<(8+(c)))  /* DMA channel interrupt */
 60 #define BA0_HISR_GPPI           (1<<5)  /* General Purpose Input (Primary chip) */
 61 #define BA0_HISR_GPSI           (1<<4)  /* General Purpose Input (Secondary chip) */
 62 #define BA0_HISR_GP3I           (1<<3)  /* GPIO3 pin Interrupt */
 63 #define BA0_HISR_GP1I           (1<<2)  /* GPIO1 pin Interrupt */
 64 #define BA0_HISR_VUPI           (1<<1)  /* VOLUP pin Interrupt */
 65 #define BA0_HISR_VDNI           (1<<0)  /* VOLDN pin Interrupt */
 66 
 67 #define BA0_HICR                0x0008  /* Host Interrupt Control Register */
 68 #define BA0_HICR_CHGM           (1<<1)  /* INTENA Change Mask */
 69 #define BA0_HICR_IEV            (1<<0)  /* INTENA Value */
 70 #define BA0_HICR_EOI            (3<<0)  /* End of Interrupt command */
 71 
 72 #define BA0_HIMR                0x000c  /* Host Interrupt Mask Register */
 73                                         /* Use same contants as for BA0_HISR */
 74 
 75 #define BA0_IIER                0x0010  /* ISA Interrupt Enable Register */
 76 
 77 #define BA0_HDSR0               0x00f0  /* Host DMA Engine 0 Status Register */
 78 #define BA0_HDSR1               0x00f4  /* Host DMA Engine 1 Status Register */
 79 #define BA0_HDSR2               0x00f8  /* Host DMA Engine 2 Status Register */
 80 #define BA0_HDSR3               0x00fc  /* Host DMA Engine 3 Status Register */
 81 
 82 #define BA0_HDSR_CH1P           (1<<25) /* Channel 1 Pending */
 83 #define BA0_HDSR_CH2P           (1<<24) /* Channel 2 Pending */
 84 #define BA0_HDSR_DHTC           (1<<17) /* DMA Half Terminal Count */
 85 #define BA0_HDSR_DTC            (1<<16) /* DMA Terminal Count */
 86 #define BA0_HDSR_DRUN           (1<<15) /* DMA Running */
 87 #define BA0_HDSR_RQ             (1<<7)  /* Pending Request */
 88 
 89 #define BA0_DCA0                0x0110  /* Host DMA Engine 0 Current Address */
 90 #define BA0_DCC0                0x0114  /* Host DMA Engine 0 Current Count */
 91 #define BA0_DBA0                0x0118  /* Host DMA Engine 0 Base Address */
 92 #define BA0_DBC0                0x011c  /* Host DMA Engine 0 Base Count */
 93 #define BA0_DCA1                0x0120  /* Host DMA Engine 1 Current Address */
 94 #define BA0_DCC1                0x0124  /* Host DMA Engine 1 Current Count */
 95 #define BA0_DBA1                0x0128  /* Host DMA Engine 1 Base Address */
 96 #define BA0_DBC1                0x012c  /* Host DMA Engine 1 Base Count */
 97 #define BA0_DCA2                0x0130  /* Host DMA Engine 2 Current Address */
 98 #define BA0_DCC2                0x0134  /* Host DMA Engine 2 Current Count */
 99 #define BA0_DBA2                0x0138  /* Host DMA Engine 2 Base Address */
100 #define BA0_DBC2                0x013c  /* Host DMA Engine 2 Base Count */
101 #define BA0_DCA3                0x0140  /* Host DMA Engine 3 Current Address */
102 #define BA0_DCC3                0x0144  /* Host DMA Engine 3 Current Count */
103 #define BA0_DBA3                0x0148  /* Host DMA Engine 3 Base Address */
104 #define BA0_DBC3                0x014c  /* Host DMA Engine 3 Base Count */
105 #define BA0_DMR0                0x0150  /* Host DMA Engine 0 Mode */
106 #define BA0_DCR0                0x0154  /* Host DMA Engine 0 Command */
107 #define BA0_DMR1                0x0158  /* Host DMA Engine 1 Mode */
108 #define BA0_DCR1                0x015c  /* Host DMA Engine 1 Command */
109 #define BA0_DMR2                0x0160  /* Host DMA Engine 2 Mode */
110 #define BA0_DCR2                0x0164  /* Host DMA Engine 2 Command */
111 #define BA0_DMR3                0x0168  /* Host DMA Engine 3 Mode */
112 #define BA0_DCR3                0x016c  /* Host DMA Engine 3 Command */
113 
114 #define BA0_DMR_DMA             (1<<29) /* Enable DMA mode */
115 #define BA0_DMR_POLL            (1<<28) /* Enable poll mode */
116 #define BA0_DMR_TBC             (1<<25) /* Transfer By Channel */
117 #define BA0_DMR_CBC             (1<<24) /* Count By Channel (0 = frame resolution) */
118 #define BA0_DMR_SWAPC           (1<<22) /* Swap Left/Right Channels */
119 #define BA0_DMR_SIZE20          (1<<20) /* Sample is 20-bit */
120 #define BA0_DMR_USIGN           (1<<19) /* Unsigned */
121 #define BA0_DMR_BEND            (1<<18) /* Big Endian */
122 #define BA0_DMR_MONO            (1<<17) /* Mono */
123 #define BA0_DMR_SIZE8           (1<<16) /* Sample is 8-bit */
124 #define BA0_DMR_TYPE_DEMAND     (0<<6)
125 #define BA0_DMR_TYPE_SINGLE     (1<<6)
126 #define BA0_DMR_TYPE_BLOCK      (2<<6)
127 #define BA0_DMR_TYPE_CASCADE    (3<<6)  /* Not supported */
128 #define BA0_DMR_DEC             (1<<5)  /* Access Increment (0) or Decrement (1) */
129 #define BA0_DMR_AUTO            (1<<4)  /* Auto-Initialize */
130 #define BA0_DMR_TR_VERIFY       (0<<2)  /* Verify Transfer */
131 #define BA0_DMR_TR_WRITE        (1<<2)  /* Write Transfer */
132 #define BA0_DMR_TR_READ         (2<<2)  /* Read Transfer */
133 
134 #define BA0_DCR_HTCIE           (1<<17) /* Half Terminal Count Interrupt */
135 #define BA0_DCR_TCIE            (1<<16) /* Terminal Count Interrupt */
136 #define BA0_DCR_MSK             (1<<0)  /* DMA Mask bit */
137 
138 #define BA0_FCR0                0x0180  /* FIFO Control 0 */
139 #define BA0_FCR1                0x0184  /* FIFO Control 1 */
140 #define BA0_FCR2                0x0188  /* FIFO Control 2 */
141 #define BA0_FCR3                0x018c  /* FIFO Control 3 */
142 
143 #define BA0_FCR_FEN             (1<<31) /* FIFO Enable bit */
144 #define BA0_FCR_DACZ            (1<<30) /* DAC Zero */
145 #define BA0_FCR_PSH             (1<<29) /* Previous Sample Hold */
146 #define BA0_FCR_RS(x)           (((x)&0x1f)<<24) /* Right Slot Mapping */
147 #define BA0_FCR_LS(x)           (((x)&0x1f)<<16) /* Left Slot Mapping */
148 #define BA0_FCR_SZ(x)           (((x)&0x7f)<<8) /* FIFO buffer size (in samples) */
149 #define BA0_FCR_OF(x)           (((x)&0x7f)<<0) /* FIFO starting offset (in samples) */
150 
151 #define BA0_FPDR0               0x0190  /* FIFO Polled Data 0 */
152 #define BA0_FPDR1               0x0194  /* FIFO Polled Data 1 */
153 #define BA0_FPDR2               0x0198  /* FIFO Polled Data 2 */
154 #define BA0_FPDR3               0x019c  /* FIFO Polled Data 3 */
155 
156 #define BA0_FCHS                0x020c  /* FIFO Channel Status */
157 #define BA0_FCHS_RCO(x)         (1<<(7+(((x)&3)<<3))) /* Right Channel Out */
158 #define BA0_FCHS_LCO(x)         (1<<(6+(((x)&3)<<3))) /* Left Channel Out */
159 #define BA0_FCHS_MRP(x)         (1<<(5+(((x)&3)<<3))) /* Move Read Pointer */
160 #define BA0_FCHS_FE(x)          (1<<(4+(((x)&3)<<3))) /* FIFO Empty */
161 #define BA0_FCHS_FF(x)          (1<<(3+(((x)&3)<<3))) /* FIFO Full */
162 #define BA0_FCHS_IOR(x)         (1<<(2+(((x)&3)<<3))) /* Internal Overrun Flag */
163 #define BA0_FCHS_RCI(x)         (1<<(1+(((x)&3)<<3))) /* Right Channel In */
164 #define BA0_FCHS_LCI(x)         (1<<(0+(((x)&3)<<3))) /* Left Channel In */
165 
166 #define BA0_FSIC0               0x0210  /* FIFO Status and Interrupt Control 0 */
167 #define BA0_FSIC1               0x0214  /* FIFO Status and Interrupt Control 1 */
168 #define BA0_FSIC2               0x0218  /* FIFO Status and Interrupt Control 2 */
169 #define BA0_FSIC3               0x021c  /* FIFO Status and Interrupt Control 3 */
170 
171 #define BA0_FSIC_FIC(x)         (((x)&0x7f)<<24) /* FIFO Interrupt Count */
172 #define BA0_FSIC_FORIE          (1<<23) /* FIFO OverRun Interrupt Enable */
173 #define BA0_FSIC_FURIE          (1<<22) /* FIFO UnderRun Interrupt Enable */
174 #define BA0_FSIC_FSCIE          (1<<16) /* FIFO Sample Count Interrupt Enable */
175 #define BA0_FSIC_FSC(x)         (((x)&0x7f)<<8) /* FIFO Sample Count */
176 #define BA0_FSIC_FOR            (1<<7)  /* FIFO OverRun */
177 #define BA0_FSIC_FUR            (1<<6)  /* FIFO UnderRun */
178 #define BA0_FSIC_FSCR           (1<<0)  /* FIFO Sample Count Reached */
179 
180 #define BA0_PMCS                0x0344  /* Power Management Control/Status */
181 #define BA0_CWPR                0x03e0  /* Configuration Write Protect */
182 
183 #define BA0_EPPMC               0x03e4  /* Extended PCI Power Management Control */
184 #define BA0_EPPMC_FPDN          (1<<14) /* Full Power DowN */
185 
186 #define BA0_GPIOR               0x03e8  /* GPIO Pin Interface Register */
187 
188 #define BA0_SPMC                0x03ec  /* Serial Port Power Management Control (& ASDIN2 enable) */
189 #define BA0_SPMC_GIPPEN         (1<<15) /* GP INT Primary PME# Enable */
190 #define BA0_SPMC_GISPEN         (1<<14) /* GP INT Secondary PME# Enable */
191 #define BA0_SPMC_EESPD          (1<<9)  /* EEPROM Serial Port Disable */
192 #define BA0_SPMC_ASDI2E         (1<<8)  /* ASDIN2 Enable */
193 #define BA0_SPMC_ASDO           (1<<7)  /* Asynchronous ASDOUT Assertion */
194 #define BA0_SPMC_WUP2           (1<<3)  /* Wakeup for Secondary Input */
195 #define BA0_SPMC_WUP1           (1<<2)  /* Wakeup for Primary Input */
196 #define BA0_SPMC_ASYNC          (1<<1)  /* Asynchronous ASYNC Assertion */
197 #define BA0_SPMC_RSTN           (1<<0)  /* Reset Not! */
198 
199 #define BA0_CFLR                0x03f0  /* Configuration Load Register (EEPROM or BIOS) */
200 #define BA0_CFLR_DEFAULT        0x00000001 /* CFLR must be in AC97 link mode */
201 #define BA0_IISR                0x03f4  /* ISA Interrupt Select */
202 #define BA0_TMS                 0x03f8  /* Test Register */
203 #define BA0_SSVID               0x03fc  /* Subsystem ID register */
204 
205 #define BA0_CLKCR1              0x0400  /* Clock Control Register 1 */
206 #define BA0_CLKCR1_CLKON        (1<<25) /* Read Only */
207 #define BA0_CLKCR1_DLLRDY       (1<<24) /* DLL Ready */
208 #define BA0_CLKCR1_DLLOS        (1<<6)  /* DLL Output Select */
209 #define BA0_CLKCR1_SWCE         (1<<5)  /* Clock Enable */
210 #define BA0_CLKCR1_DLLP         (1<<4)  /* DLL PowerUp */
211 #define BA0_CLKCR1_DLLSS        (((x)&3)<<3) /* DLL Source Select */
212 
213 #define BA0_FRR                 0x0410  /* Feature Reporting Register */
214 #define BA0_SLT12O              0x041c  /* Slot 12 GPIO Output Register for AC-Link */
215 
216 #define BA0_SERMC               0x0420  /* Serial Port Master Control */
217 #define BA0_SERMC_FCRN          (1<<27) /* Force Codec Ready Not */
218 #define BA0_SERMC_ODSEN2        (1<<25) /* On-Demand Support Enable ASDIN2 */
219 #define BA0_SERMC_ODSEN1        (1<<24) /* On-Demand Support Enable ASDIN1 */
220 #define BA0_SERMC_SXLB          (1<<21) /* ASDIN2 to ASDOUT Loopback */
221 #define BA0_SERMC_SLB           (1<<20) /* ASDOUT to ASDIN2 Loopback */
222 #define BA0_SERMC_LOVF          (1<<19) /* Loopback Output Valid Frame bit */
223 #define BA0_SERMC_TCID(x)       (((x)&3)<<16) /* Target Secondary Codec ID */
224 #define BA0_SERMC_PXLB          (5<<1)  /* Primary Port External Loopback */
225 #define BA0_SERMC_PLB           (4<<1)  /* Primary Port Internal Loopback */
226 #define BA0_SERMC_PTC           (7<<1)  /* Port Timing Configuration */
227 #define BA0_SERMC_PTC_AC97      (1<<1)  /* AC97 mode */
228 #define BA0_SERMC_MSPE          (1<<0)  /* Master Serial Port Enable */
229 
230 #define BA0_SERC1               0x0428  /* Serial Port Configuration 1 */
231 #define BA0_SERC1_SO1F(x)       (((x)&7)>>1) /* Primary Output Port Format */
232 #define BA0_SERC1_AC97          (1<<1)
233 #define BA0_SERC1_SO1EN         (1<<0)  /* Primary Output Port Enable */
234 
235 #define BA0_SERC2               0x042c  /* Serial Port Configuration 2 */
236 #define BA0_SERC2_SI1F(x)       (((x)&7)>>1) /* Primary Input Port Format */
237 #define BA0_SERC2_AC97          (1<<1)
238 #define BA0_SERC2_SI1EN         (1<<0)  /* Primary Input Port Enable */
239 
240 #define BA0_SLT12M              0x045c  /* Slot 12 Monitor Register for Primary AC-Link */
241 
242 #define BA0_ACCTL               0x0460  /* AC'97 Control */
243 #define BA0_ACCTL_TC            (1<<6)  /* Target Codec */
244 #define BA0_ACCTL_CRW           (1<<4)  /* 0=Write, 1=Read Command */
245 #define BA0_ACCTL_DCV           (1<<3)  /* Dynamic Command Valid */
246 #define BA0_ACCTL_VFRM          (1<<2)  /* Valid Frame */
247 #define BA0_ACCTL_ESYN          (1<<1)  /* Enable Sync */
248 
249 #define BA0_ACSTS               0x0464  /* AC'97 Status */
250 #define BA0_ACSTS_VSTS          (1<<1)  /* Valid Status */
251 #define BA0_ACSTS_CRDY          (1<<0)  /* Codec Ready */
252 
253 #define BA0_ACOSV               0x0468  /* AC'97 Output Slot Valid */
254 #define BA0_ACOSV_SLV(x)        (1<<((x)-3))
255 
256 #define BA0_ACCAD               0x046c  /* AC'97 Command Address */
257 #define BA0_ACCDA               0x0470  /* AC'97 Command Data */
258 
259 #define BA0_ACISV               0x0474  /* AC'97 Input Slot Valid */
260 #define BA0_ACISV_SLV(x)        (1<<((x)-3))
261 
262 #define BA0_ACSAD               0x0478  /* AC'97 Status Address */
263 #define BA0_ACSDA               0x047c  /* AC'97 Status Data */
264 #define BA0_JSPT                0x0480  /* Joystick poll/trigger */
265 #define BA0_JSCTL               0x0484  /* Joystick control */
266 #define BA0_JSC1                0x0488  /* Joystick control */
267 #define BA0_JSC2                0x048c  /* Joystick control */
268 #define BA0_JSIO                0x04a0
269 
270 #define BA0_MIDCR               0x0490  /* MIDI Control */
271 #define BA0_MIDCR_MRST          (1<<5)  /* Reset MIDI Interface */
272 #define BA0_MIDCR_MLB           (1<<4)  /* MIDI Loop Back Enable */
273 #define BA0_MIDCR_TIE           (1<<3)  /* MIDI Transmuit Interrupt Enable */
274 #define BA0_MIDCR_RIE           (1<<2)  /* MIDI Receive Interrupt Enable */
275 #define BA0_MIDCR_RXE           (1<<1)  /* MIDI Receive Enable */
276 #define BA0_MIDCR_TXE           (1<<0)  /* MIDI Transmit Enable */
277 
278 #define BA0_MIDCMD              0x0494  /* MIDI Command (wo) */
279 
280 #define BA0_MIDSR               0x0494  /* MIDI Status (ro) */
281 #define BA0_MIDSR_RDA           (1<<15) /* Sticky bit (RBE 1->0) */
282 #define BA0_MIDSR_TBE           (1<<14) /* Sticky bit (TBF 0->1) */
283 #define BA0_MIDSR_RBE           (1<<7)  /* Receive Buffer Empty */
284 #define BA0_MIDSR_TBF           (1<<6)  /* Transmit Buffer Full */
285 
286 #define BA0_MIDWP               0x0498  /* MIDI Write */
287 #define BA0_MIDRP               0x049c  /* MIDI Read (ro) */
288 
289 #define BA0_AODSD1              0x04a8  /* AC'97 On-Demand Slot Disable for primary link (ro) */
290 #define BA0_AODSD1_NDS(x)       (1<<((x)-3))
291 
292 #define BA0_AODSD2              0x04ac  /* AC'97 On-Demand Slot Disable for secondary link (ro) */
293 #define BA0_AODSD2_NDS(x)       (1<<((x)-3))
294 
295 #define BA0_CFGI                0x04b0  /* Configure Interface (EEPROM interface) */
296 #define BA0_SLT12M2             0x04dc  /* Slot 12 Monitor Register 2 for secondary AC-link */
297 #define BA0_ACSTS2              0x04e4  /* AC'97 Status Register 2 */
298 #define BA0_ACISV2              0x04f4  /* AC'97 Input Slot Valid Register 2 */
299 #define BA0_ACSAD2              0x04f8  /* AC'97 Status Address Register 2 */
300 #define BA0_ACSDA2              0x04fc  /* AC'97 Status Data Register 2 */
301 #define BA0_FMSR                0x0730  /* FM Synthesis Status (ro) */
302 #define BA0_B0AP                0x0730  /* FM Bank 0 Address Port (wo) */
303 #define BA0_FMDP                0x0734  /* FM Data Port */
304 #define BA0_B1AP                0x0738  /* FM Bank 1 Address Port */
305 #define BA0_B1DP                0x073c  /* FM Bank 1 Data Port */
306 
307 #define BA0_SSPM                0x0740  /* Sound System Power Management */
308 #define BA0_SSPM_MIXEN          (1<<6)  /* Playback SRC + FM/Wavetable MIX */
309 #define BA0_SSPM_CSRCEN         (1<<5)  /* Capture Sample Rate Converter Enable */
310 #define BA0_SSPM_PSRCEN         (1<<4)  /* Playback Sample Rate Converter Enable */
311 #define BA0_SSPM_JSEN           (1<<3)  /* Joystick Enable */
312 #define BA0_SSPM_ACLEN          (1<<2)  /* Serial Port Engine and AC-Link Enable */
313 #define BA0_SSPM_FMEN           (1<<1)  /* FM Synthesis Block Enable */
314 
315 #define BA0_DACSR               0x0744  /* DAC Sample Rate - Playback SRC */
316 #define BA0_ADCSR               0x0748  /* ADC Sample Rate - Capture SRC */
317 
318 #define BA0_SSCR                0x074c  /* Sound System Control Register */
319 #define BA0_SSCR_HVS1           (1<<23) /* Hardwave Volume Step (0=1,1=2) */
320 #define BA0_SSCR_MVCS           (1<<19) /* Master Volume Codec Select */
321 #define BA0_SSCR_MVLD           (1<<18) /* Master Volume Line Out Disable */
322 #define BA0_SSCR_MVAD           (1<<17) /* Master Volume Alternate Out Disable */
323 #define BA0_SSCR_MVMD           (1<<16) /* Master Volume Mono Out Disable */
324 #define BA0_SSCR_XLPSRC         (1<<8)  /* External SRC Loopback Mode */
325 #define BA0_SSCR_LPSRC          (1<<7)  /* SRC Loopback Mode */
326 #define BA0_SSCR_CDTX           (1<<5)  /* CD Transfer Data */
327 #define BA0_SSCR_HVC            (1<<3)  /* Harware Volume Control Enable */
328 
329 #define BA0_FMLVC               0x0754  /* FM Synthesis Left Volume Control */
330 #define BA0_FMRVC               0x0758  /* FM Synthesis Right Volume Control */
331 #define BA0_SRCSA               0x075c  /* SRC Slot Assignments */
332 #define BA0_PPLVC               0x0760  /* PCM Playback Left Volume Control */
333 #define BA0_PPRVC               0x0764  /* PCM Playback Right Volume Control */
334 #define BA0_PASR                0x0768  /* playback sample rate */
335 #define BA0_CASR                0x076C  /* capture sample rate */
336 
337 /* Source Slot Numbers - Playback */
338 #define SRCSLOT_LEFT_PCM_PLAYBACK               0
339 #define SRCSLOT_RIGHT_PCM_PLAYBACK              1
340 #define SRCSLOT_PHONE_LINE_1_DAC                2
341 #define SRCSLOT_CENTER_PCM_PLAYBACK             3
342 #define SRCSLOT_LEFT_SURROUND_PCM_PLAYBACK      4
343 #define SRCSLOT_RIGHT_SURROUND_PCM_PLAYBACK     5
344 #define SRCSLOT_LFE_PCM_PLAYBACK                6
345 #define SRCSLOT_PHONE_LINE_2_DAC                7
346 #define SRCSLOT_HEADSET_DAC                     8
347 #define SRCSLOT_LEFT_WT                         29  /* invalid for BA0_SRCSA */
348 #define SRCSLOT_RIGHT_WT                        30  /* invalid for BA0_SRCSA */
349 
350 /* Source Slot Numbers - Capture */
351 #define SRCSLOT_LEFT_PCM_RECORD                 10
352 #define SRCSLOT_RIGHT_PCM_RECORD                11
353 #define SRCSLOT_PHONE_LINE_1_ADC                12
354 #define SRCSLOT_MIC_ADC                         13
355 #define SRCSLOT_PHONE_LINE_2_ADC                17
356 #define SRCSLOT_HEADSET_ADC                     18
357 #define SRCSLOT_SECONDARY_LEFT_PCM_RECORD       20
358 #define SRCSLOT_SECONDARY_RIGHT_PCM_RECORD      21
359 #define SRCSLOT_SECONDARY_PHONE_LINE_1_ADC      22
360 #define SRCSLOT_SECONDARY_MIC_ADC               23
361 #define SRCSLOT_SECONDARY_PHONE_LINE_2_ADC      27
362 #define SRCSLOT_SECONDARY_HEADSET_ADC           28
363 
364 /* Source Slot Numbers - Others */
365 #define SRCSLOT_POWER_DOWN                      31
366 
367 /* MIDI modes */
368 #define CS4281_MODE_OUTPUT              (1<<0)
369 #define CS4281_MODE_INPUT               (1<<1)
370 
371 /* joystick bits */
372 /* Bits for JSPT */
373 #define JSPT_CAX                                0x00000001
374 #define JSPT_CAY                                0x00000002
375 #define JSPT_CBX                                0x00000004
376 #define JSPT_CBY                                0x00000008
377 #define JSPT_BA1                                0x00000010
378 #define JSPT_BA2                                0x00000020
379 #define JSPT_BB1                                0x00000040
380 #define JSPT_BB2                                0x00000080
381 
382 /* Bits for JSCTL */
383 #define JSCTL_SP_MASK                           0x00000003
384 #define JSCTL_SP_SLOW                           0x00000000
385 #define JSCTL_SP_MEDIUM_SLOW                    0x00000001
386 #define JSCTL_SP_MEDIUM_FAST                    0x00000002
387 #define JSCTL_SP_FAST                           0x00000003
388 #define JSCTL_ARE                               0x00000004
389 
390 /* Data register pairs masks */
391 #define JSC1_Y1V_MASK                           0x0000FFFF
392 #define JSC1_X1V_MASK                           0xFFFF0000
393 #define JSC1_Y1V_SHIFT                          0
394 #define JSC1_X1V_SHIFT                          16
395 #define JSC2_Y2V_MASK                           0x0000FFFF
396 #define JSC2_X2V_MASK                           0xFFFF0000
397 #define JSC2_Y2V_SHIFT                          0
398 #define JSC2_X2V_SHIFT                          16
399 
400 /* JS GPIO */
401 #define JSIO_DAX                                0x00000001
402 #define JSIO_DAY                                0x00000002
403 #define JSIO_DBX                                0x00000004
404 #define JSIO_DBY                                0x00000008
405 #define JSIO_AXOE                               0x00000010
406 #define JSIO_AYOE                               0x00000020
407 #define JSIO_BXOE                               0x00000040
408 #define JSIO_BYOE                               0x00000080
409 
410 /*
411  *
412  */
413 
414 struct cs4281_dma {
415         struct snd_pcm_substream *substream;
416         unsigned int regDBA;            /* offset to DBA register */
417         unsigned int regDCA;            /* offset to DCA register */
418         unsigned int regDBC;            /* offset to DBC register */
419         unsigned int regDCC;            /* offset to DCC register */
420         unsigned int regDMR;            /* offset to DMR register */
421         unsigned int regDCR;            /* offset to DCR register */
422         unsigned int regHDSR;           /* offset to HDSR register */
423         unsigned int regFCR;            /* offset to FCR register */
424         unsigned int regFSIC;           /* offset to FSIC register */
425         unsigned int valDMR;            /* DMA mode */
426         unsigned int valDCR;            /* DMA command */
427         unsigned int valFCR;            /* FIFO control */
428         unsigned int fifo_offset;       /* FIFO offset within BA1 */
429         unsigned char left_slot;        /* FIFO left slot */
430         unsigned char right_slot;       /* FIFO right slot */
431         int frag;                       /* period number */
432 };
433 
434 #define SUSPEND_REGISTERS       20
435 
436 struct cs4281 {
437         int irq;
438 
439         void __iomem *ba0;              /* virtual (accessible) address */
440         void __iomem *ba1;              /* virtual (accessible) address */
441         unsigned long ba0_addr;
442         unsigned long ba1_addr;
443 
444         int dual_codec;
445 
446         struct snd_ac97_bus *ac97_bus;
447         struct snd_ac97 *ac97;
448         struct snd_ac97 *ac97_secondary;
449 
450         struct pci_dev *pci;
451         struct snd_card *card;
452         struct snd_pcm *pcm;
453         struct snd_rawmidi *rmidi;
454         struct snd_rawmidi_substream *midi_input;
455         struct snd_rawmidi_substream *midi_output;
456 
457         struct cs4281_dma dma[4];
458 
459         unsigned char src_left_play_slot;
460         unsigned char src_right_play_slot;
461         unsigned char src_left_rec_slot;
462         unsigned char src_right_rec_slot;
463 
464         unsigned int spurious_dhtc_irq;
465         unsigned int spurious_dtc_irq;
466 
467         spinlock_t reg_lock;
468         unsigned int midcr;
469         unsigned int uartm;
470 
471         struct gameport *gameport;
472 
473 #ifdef CONFIG_PM_SLEEP
474         u32 suspend_regs[SUSPEND_REGISTERS];
475 #endif
476 
477 };
478 
479 static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id);
480 
481 static const struct pci_device_id snd_cs4281_ids[] = {
482         { PCI_VDEVICE(CIRRUS, 0x6005), 0, },    /* CS4281 */
483         { 0, }
484 };
485 
486 MODULE_DEVICE_TABLE(pci, snd_cs4281_ids);
487 
488 /*
489  *  constants
490  */
491 
492 #define CS4281_FIFO_SIZE        32
493 
494 /*
495  *  common I/O routines
496  */
497 
498 static inline void snd_cs4281_pokeBA0(struct cs4281 *chip, unsigned long offset,
499                                       unsigned int val)
500 {
501         writel(val, chip->ba0 + offset);
502 }
503 
504 static inline unsigned int snd_cs4281_peekBA0(struct cs4281 *chip, unsigned long offset)
505 {
506         return readl(chip->ba0 + offset);
507 }
508 
509 static void snd_cs4281_ac97_write(struct snd_ac97 *ac97,
510                                   unsigned short reg, unsigned short val)
511 {
512         /*
513          *  1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
514          *  2. Write ACCDA = Command Data Register = 470h    for data to write to AC97
515          *  3. Write ACCTL = Control Register = 460h for initiating the write
516          *  4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
517          *  5. if DCV not cleared, break and return error
518          */
519         struct cs4281 *chip = ac97->private_data;
520         int count;
521 
522         /*
523          *  Setup the AC97 control registers on the CS461x to send the
524          *  appropriate command to the AC97 to perform the read.
525          *  ACCAD = Command Address Register = 46Ch
526          *  ACCDA = Command Data Register = 470h
527          *  ACCTL = Control Register = 460h
528          *  set DCV - will clear when process completed
529          *  reset CRW - Write command
530          *  set VFRM - valid frame enabled
531          *  set ESYN - ASYNC generation enabled
532          *  set RSTN - ARST# inactive, AC97 codec not reset
533          */
534         snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
535         snd_cs4281_pokeBA0(chip, BA0_ACCDA, val);
536         snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_VFRM |
537                                             BA0_ACCTL_ESYN | (ac97->num ? BA0_ACCTL_TC : 0));
538         for (count = 0; count < 2000; count++) {
539                 /*
540                  *  First, we want to wait for a short time.
541                  */
542                 udelay(10);
543                 /*
544                  *  Now, check to see if the write has completed.
545                  *  ACCTL = 460h, DCV should be reset by now and 460h = 07h
546                  */
547                 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV)) {
548                         return;
549                 }
550         }
551         dev_err(chip->card->dev,
552                 "AC'97 write problem, reg = 0x%x, val = 0x%x\n", reg, val);
553 }
554 
555 static unsigned short snd_cs4281_ac97_read(struct snd_ac97 *ac97,
556                                            unsigned short reg)
557 {
558         struct cs4281 *chip = ac97->private_data;
559         int count;
560         unsigned short result;
561         // FIXME: volatile is necessary in the following due to a bug of
562         // some gcc versions
563         volatile int ac97_num = ((volatile struct snd_ac97 *)ac97)->num;
564 
565         /*
566          *  1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
567          *  2. Write ACCDA = Command Data Register = 470h    for data to write to AC97 
568          *  3. Write ACCTL = Control Register = 460h for initiating the write
569          *  4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
570          *  5. if DCV not cleared, break and return error
571          *  6. Read ACSTS = Status Register = 464h, check VSTS bit
572          */
573 
574         snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
575 
576         /*
577          *  Setup the AC97 control registers on the CS461x to send the
578          *  appropriate command to the AC97 to perform the read.
579          *  ACCAD = Command Address Register = 46Ch
580          *  ACCDA = Command Data Register = 470h
581          *  ACCTL = Control Register = 460h
582          *  set DCV - will clear when process completed
583          *  set CRW - Read command
584          *  set VFRM - valid frame enabled
585          *  set ESYN - ASYNC generation enabled
586          *  set RSTN - ARST# inactive, AC97 codec not reset
587          */
588 
589         snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
590         snd_cs4281_pokeBA0(chip, BA0_ACCDA, 0);
591         snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_CRW |
592                                             BA0_ACCTL_VFRM | BA0_ACCTL_ESYN |
593                            (ac97_num ? BA0_ACCTL_TC : 0));
594 
595 
596         /*
597          *  Wait for the read to occur.
598          */
599         for (count = 0; count < 500; count++) {
600                 /*
601                  *  First, we want to wait for a short time.
602                  */
603                 udelay(10);
604                 /*
605                  *  Now, check to see if the read has completed.
606                  *  ACCTL = 460h, DCV should be reset by now and 460h = 17h
607                  */
608                 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV))
609                         goto __ok1;
610         }
611 
612         dev_err(chip->card->dev,
613                 "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
614         result = 0xffff;
615         goto __end;
616         
617       __ok1:
618         /*
619          *  Wait for the valid status bit to go active.
620          */
621         for (count = 0; count < 100; count++) {
622                 /*
623                  *  Read the AC97 status register.
624                  *  ACSTS = Status Register = 464h
625                  *  VSTS - Valid Status
626                  */
627                 if (snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSTS2 : BA0_ACSTS) & BA0_ACSTS_VSTS)
628                         goto __ok2;
629                 udelay(10);
630         }
631         
632         dev_err(chip->card->dev,
633                 "AC'97 read problem (ACSTS_VSTS), reg = 0x%x\n", reg);
634         result = 0xffff;
635         goto __end;
636 
637       __ok2:
638         /*
639          *  Read the data returned from the AC97 register.
640          *  ACSDA = Status Data Register = 474h
641          */
642         result = snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
643 
644       __end:
645         return result;
646 }
647 
648 /*
649  *  PCM part
650  */
651 
652 static int snd_cs4281_trigger(struct snd_pcm_substream *substream, int cmd)
653 {
654         struct cs4281_dma *dma = substream->runtime->private_data;
655         struct cs4281 *chip = snd_pcm_substream_chip(substream);
656 
657         spin_lock(&chip->reg_lock);
658         switch (cmd) {
659         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
660                 dma->valDCR |= BA0_DCR_MSK;
661                 dma->valFCR |= BA0_FCR_FEN;
662                 break;
663         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
664                 dma->valDCR &= ~BA0_DCR_MSK;
665                 dma->valFCR &= ~BA0_FCR_FEN;
666                 break;
667         case SNDRV_PCM_TRIGGER_START:
668         case SNDRV_PCM_TRIGGER_RESUME:
669                 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR & ~BA0_DMR_DMA);
670                 dma->valDMR |= BA0_DMR_DMA;
671                 dma->valDCR &= ~BA0_DCR_MSK;
672                 dma->valFCR |= BA0_FCR_FEN;
673                 break;
674         case SNDRV_PCM_TRIGGER_STOP:
675         case SNDRV_PCM_TRIGGER_SUSPEND:
676                 dma->valDMR &= ~(BA0_DMR_DMA|BA0_DMR_POLL);
677                 dma->valDCR |= BA0_DCR_MSK;
678                 dma->valFCR &= ~BA0_FCR_FEN;
679                 /* Leave wave playback FIFO enabled for FM */
680                 if (dma->regFCR != BA0_FCR0)
681                         dma->valFCR &= ~BA0_FCR_FEN;
682                 break;
683         default:
684                 spin_unlock(&chip->reg_lock);
685                 return -EINVAL;
686         }
687         snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR);
688         snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR);
689         snd_cs4281_pokeBA0(chip, dma->regDCR, dma->valDCR);
690         spin_unlock(&chip->reg_lock);
691         return 0;
692 }
693 
694 static unsigned int snd_cs4281_rate(unsigned int rate, unsigned int *real_rate)
695 {
696         unsigned int val;
697         
698         if (real_rate)
699                 *real_rate = rate;
700         /* special "hardcoded" rates */
701         switch (rate) {
702         case 8000:      return 5;
703         case 11025:     return 4;
704         case 16000:     return 3;
705         case 22050:     return 2;
706         case 44100:     return 1;
707         case 48000:     return 0;
708         default:
709                 break;
710         }
711         val = 1536000 / rate;
712         if (real_rate)
713                 *real_rate = 1536000 / val;
714         return val;
715 }
716 
717 static void snd_cs4281_mode(struct cs4281 *chip, struct cs4281_dma *dma,
718                             struct snd_pcm_runtime *runtime,
719                             int capture, int src)
720 {
721         int rec_mono;
722 
723         dma->valDMR = BA0_DMR_TYPE_SINGLE | BA0_DMR_AUTO |
724                       (capture ? BA0_DMR_TR_WRITE : BA0_DMR_TR_READ);
725         if (runtime->channels == 1)
726                 dma->valDMR |= BA0_DMR_MONO;
727         if (snd_pcm_format_unsigned(runtime->format) > 0)
728                 dma->valDMR |= BA0_DMR_USIGN;
729         if (snd_pcm_format_big_endian(runtime->format) > 0)
730                 dma->valDMR |= BA0_DMR_BEND;
731         switch (snd_pcm_format_width(runtime->format)) {
732         case 8: dma->valDMR |= BA0_DMR_SIZE8;
733                 if (runtime->channels == 1)
734                         dma->valDMR |= BA0_DMR_SWAPC;
735                 break;
736         case 32: dma->valDMR |= BA0_DMR_SIZE20; break;
737         }
738         dma->frag = 0;  /* for workaround */
739         dma->valDCR = BA0_DCR_TCIE | BA0_DCR_MSK;
740         if (runtime->buffer_size != runtime->period_size)
741                 dma->valDCR |= BA0_DCR_HTCIE;
742         /* Initialize DMA */
743         snd_cs4281_pokeBA0(chip, dma->regDBA, runtime->dma_addr);
744         snd_cs4281_pokeBA0(chip, dma->regDBC, runtime->buffer_size - 1);
745         rec_mono = (chip->dma[1].valDMR & BA0_DMR_MONO) == BA0_DMR_MONO;
746         snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
747                                             (chip->src_right_play_slot << 8) |
748                                             (chip->src_left_rec_slot << 16) |
749                                             ((rec_mono ? 31 : chip->src_right_rec_slot) << 24));
750         if (!src)
751                 goto __skip_src;
752         if (!capture) {
753                 if (dma->left_slot == chip->src_left_play_slot) {
754                         unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
755                         snd_BUG_ON(dma->right_slot != chip->src_right_play_slot);
756                         snd_cs4281_pokeBA0(chip, BA0_DACSR, val);
757                 }
758         } else {
759                 if (dma->left_slot == chip->src_left_rec_slot) {
760                         unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
761                         snd_BUG_ON(dma->right_slot != chip->src_right_rec_slot);
762                         snd_cs4281_pokeBA0(chip, BA0_ADCSR, val);
763                 }
764         }
765       __skip_src:
766         /* Deactivate wave playback FIFO before changing slot assignments */
767         if (dma->regFCR == BA0_FCR0)
768                 snd_cs4281_pokeBA0(chip, dma->regFCR, snd_cs4281_peekBA0(chip, dma->regFCR) & ~BA0_FCR_FEN);
769         /* Initialize FIFO */
770         dma->valFCR = BA0_FCR_LS(dma->left_slot) |
771                       BA0_FCR_RS(capture && (dma->valDMR & BA0_DMR_MONO) ? 31 : dma->right_slot) |
772                       BA0_FCR_SZ(CS4281_FIFO_SIZE) |
773                       BA0_FCR_OF(dma->fifo_offset);
774         snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | (capture ? BA0_FCR_PSH : 0));
775         /* Activate FIFO again for FM playback */
776         if (dma->regFCR == BA0_FCR0)
777                 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | BA0_FCR_FEN);
778         /* Clear FIFO Status and Interrupt Control Register */
779         snd_cs4281_pokeBA0(chip, dma->regFSIC, 0);
780 }
781 
782 static int snd_cs4281_playback_prepare(struct snd_pcm_substream *substream)
783 {
784         struct snd_pcm_runtime *runtime = substream->runtime;
785         struct cs4281_dma *dma = runtime->private_data;
786         struct cs4281 *chip = snd_pcm_substream_chip(substream);
787 
788         spin_lock_irq(&chip->reg_lock);
789         snd_cs4281_mode(chip, dma, runtime, 0, 1);
790         spin_unlock_irq(&chip->reg_lock);
791         return 0;
792 }
793 
794 static int snd_cs4281_capture_prepare(struct snd_pcm_substream *substream)
795 {
796         struct snd_pcm_runtime *runtime = substream->runtime;
797         struct cs4281_dma *dma = runtime->private_data;
798         struct cs4281 *chip = snd_pcm_substream_chip(substream);
799 
800         spin_lock_irq(&chip->reg_lock);
801         snd_cs4281_mode(chip, dma, runtime, 1, 1);
802         spin_unlock_irq(&chip->reg_lock);
803         return 0;
804 }
805 
806 static snd_pcm_uframes_t snd_cs4281_pointer(struct snd_pcm_substream *substream)
807 {
808         struct snd_pcm_runtime *runtime = substream->runtime;
809         struct cs4281_dma *dma = runtime->private_data;
810         struct cs4281 *chip = snd_pcm_substream_chip(substream);
811 
812         /*
813         dev_dbg(chip->card->dev,
814                 "DCC = 0x%x, buffer_size = 0x%x, jiffies = %li\n",
815                 snd_cs4281_peekBA0(chip, dma->regDCC), runtime->buffer_size,
816                jiffies);
817         */
818         return runtime->buffer_size -
819                snd_cs4281_peekBA0(chip, dma->regDCC) - 1;
820 }
821 
822 static const struct snd_pcm_hardware snd_cs4281_playback =
823 {
824         .info =                 SNDRV_PCM_INFO_MMAP |
825                                 SNDRV_PCM_INFO_INTERLEAVED |
826                                 SNDRV_PCM_INFO_MMAP_VALID |
827                                 SNDRV_PCM_INFO_PAUSE |
828                                 SNDRV_PCM_INFO_RESUME,
829         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
830                                 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
831                                 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
832                                 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
833                                 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
834         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
835         .rate_min =             4000,
836         .rate_max =             48000,
837         .channels_min =         1,
838         .channels_max =         2,
839         .buffer_bytes_max =     (512*1024),
840         .period_bytes_min =     64,
841         .period_bytes_max =     (512*1024),
842         .periods_min =          1,
843         .periods_max =          2,
844         .fifo_size =            CS4281_FIFO_SIZE,
845 };
846 
847 static const struct snd_pcm_hardware snd_cs4281_capture =
848 {
849         .info =                 SNDRV_PCM_INFO_MMAP |
850                                 SNDRV_PCM_INFO_INTERLEAVED |
851                                 SNDRV_PCM_INFO_MMAP_VALID |
852                                 SNDRV_PCM_INFO_PAUSE |
853                                 SNDRV_PCM_INFO_RESUME,
854         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
855                                 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
856                                 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
857                                 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
858                                 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
859         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
860         .rate_min =             4000,
861         .rate_max =             48000,
862         .channels_min =         1,
863         .channels_max =         2,
864         .buffer_bytes_max =     (512*1024),
865         .period_bytes_min =     64,
866         .period_bytes_max =     (512*1024),
867         .periods_min =          1,
868         .periods_max =          2,
869         .fifo_size =            CS4281_FIFO_SIZE,
870 };
871 
872 static int snd_cs4281_playback_open(struct snd_pcm_substream *substream)
873 {
874         struct cs4281 *chip = snd_pcm_substream_chip(substream);
875         struct snd_pcm_runtime *runtime = substream->runtime;
876         struct cs4281_dma *dma;
877 
878         dma = &chip->dma[0];
879         dma->substream = substream;
880         dma->left_slot = 0;
881         dma->right_slot = 1;
882         runtime->private_data = dma;
883         runtime->hw = snd_cs4281_playback;
884         /* should be detected from the AC'97 layer, but it seems
885            that although CS4297A rev B reports 18-bit ADC resolution,
886            samples are 20-bit */
887         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
888         return 0;
889 }
890 
891 static int snd_cs4281_capture_open(struct snd_pcm_substream *substream)
892 {
893         struct cs4281 *chip = snd_pcm_substream_chip(substream);
894         struct snd_pcm_runtime *runtime = substream->runtime;
895         struct cs4281_dma *dma;
896 
897         dma = &chip->dma[1];
898         dma->substream = substream;
899         dma->left_slot = 10;
900         dma->right_slot = 11;
901         runtime->private_data = dma;
902         runtime->hw = snd_cs4281_capture;
903         /* should be detected from the AC'97 layer, but it seems
904            that although CS4297A rev B reports 18-bit ADC resolution,
905            samples are 20-bit */
906         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
907         return 0;
908 }
909 
910 static int snd_cs4281_playback_close(struct snd_pcm_substream *substream)
911 {
912         struct cs4281_dma *dma = substream->runtime->private_data;
913 
914         dma->substream = NULL;
915         return 0;
916 }
917 
918 static int snd_cs4281_capture_close(struct snd_pcm_substream *substream)
919 {
920         struct cs4281_dma *dma = substream->runtime->private_data;
921 
922         dma->substream = NULL;
923         return 0;
924 }
925 
926 static const struct snd_pcm_ops snd_cs4281_playback_ops = {
927         .open =         snd_cs4281_playback_open,
928         .close =        snd_cs4281_playback_close,
929         .prepare =      snd_cs4281_playback_prepare,
930         .trigger =      snd_cs4281_trigger,
931         .pointer =      snd_cs4281_pointer,
932 };
933 
934 static const struct snd_pcm_ops snd_cs4281_capture_ops = {
935         .open =         snd_cs4281_capture_open,
936         .close =        snd_cs4281_capture_close,
937         .prepare =      snd_cs4281_capture_prepare,
938         .trigger =      snd_cs4281_trigger,
939         .pointer =      snd_cs4281_pointer,
940 };
941 
942 static int snd_cs4281_pcm(struct cs4281 *chip, int device)
943 {
944         struct snd_pcm *pcm;
945         int err;
946 
947         err = snd_pcm_new(chip->card, "CS4281", device, 1, 1, &pcm);
948         if (err < 0)
949                 return err;
950 
951         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4281_playback_ops);
952         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4281_capture_ops);
953 
954         pcm->private_data = chip;
955         pcm->info_flags = 0;
956         strcpy(pcm->name, "CS4281");
957         chip->pcm = pcm;
958 
959         snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
960                                        64*1024, 512*1024);
961 
962         return 0;
963 }
964 
965 /*
966  *  Mixer section
967  */
968 
969 #define CS_VOL_MASK     0x1f
970 
971 static int snd_cs4281_info_volume(struct snd_kcontrol *kcontrol,
972                                   struct snd_ctl_elem_info *uinfo)
973 {
974         uinfo->type              = SNDRV_CTL_ELEM_TYPE_INTEGER;
975         uinfo->count             = 2;
976         uinfo->value.integer.min = 0;
977         uinfo->value.integer.max = CS_VOL_MASK;
978         return 0;
979 }
980  
981 static int snd_cs4281_get_volume(struct snd_kcontrol *kcontrol,
982                                  struct snd_ctl_elem_value *ucontrol)
983 {
984         struct cs4281 *chip = snd_kcontrol_chip(kcontrol);
985         int regL = (kcontrol->private_value >> 16) & 0xffff;
986         int regR = kcontrol->private_value & 0xffff;
987         int volL, volR;
988 
989         volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
990         volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
991 
992         ucontrol->value.integer.value[0] = volL;
993         ucontrol->value.integer.value[1] = volR;
994         return 0;
995 }
996 
997 static int snd_cs4281_put_volume(struct snd_kcontrol *kcontrol,
998                                  struct snd_ctl_elem_value *ucontrol)
999 {
1000         struct cs4281 *chip = snd_kcontrol_chip(kcontrol);
1001         int change = 0;
1002         int regL = (kcontrol->private_value >> 16) & 0xffff;
1003         int regR = kcontrol->private_value & 0xffff;
1004         int volL, volR;
1005 
1006         volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
1007         volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
1008 
1009         if (ucontrol->value.integer.value[0] != volL) {
1010                 volL = CS_VOL_MASK - (ucontrol->value.integer.value[0] & CS_VOL_MASK);
1011                 snd_cs4281_pokeBA0(chip, regL, volL);
1012                 change = 1;
1013         }
1014         if (ucontrol->value.integer.value[1] != volR) {
1015                 volR = CS_VOL_MASK - (ucontrol->value.integer.value[1] & CS_VOL_MASK);
1016                 snd_cs4281_pokeBA0(chip, regR, volR);
1017                 change = 1;
1018         }
1019         return change;
1020 }
1021 
1022 static const DECLARE_TLV_DB_SCALE(db_scale_dsp, -4650, 150, 0);
1023 
1024 static const struct snd_kcontrol_new snd_cs4281_fm_vol =
1025 {
1026         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1027         .name = "Synth Playback Volume",
1028         .info = snd_cs4281_info_volume, 
1029         .get = snd_cs4281_get_volume,
1030         .put = snd_cs4281_put_volume, 
1031         .private_value = ((BA0_FMLVC << 16) | BA0_FMRVC),
1032         .tlv = { .p = db_scale_dsp },
1033 };
1034 
1035 static const struct snd_kcontrol_new snd_cs4281_pcm_vol =
1036 {
1037         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1038         .name = "PCM Stream Playback Volume",
1039         .info = snd_cs4281_info_volume, 
1040         .get = snd_cs4281_get_volume,
1041         .put = snd_cs4281_put_volume, 
1042         .private_value = ((BA0_PPLVC << 16) | BA0_PPRVC),
1043         .tlv = { .p = db_scale_dsp },
1044 };
1045 
1046 static void snd_cs4281_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1047 {
1048         struct cs4281 *chip = bus->private_data;
1049         chip->ac97_bus = NULL;
1050 }
1051 
1052 static void snd_cs4281_mixer_free_ac97(struct snd_ac97 *ac97)
1053 {
1054         struct cs4281 *chip = ac97->private_data;
1055         if (ac97->num)
1056                 chip->ac97_secondary = NULL;
1057         else
1058                 chip->ac97 = NULL;
1059 }
1060 
1061 static int snd_cs4281_mixer(struct cs4281 *chip)
1062 {
1063         struct snd_card *card = chip->card;
1064         struct snd_ac97_template ac97;
1065         int err;
1066         static const struct snd_ac97_bus_ops ops = {
1067                 .write = snd_cs4281_ac97_write,
1068                 .read = snd_cs4281_ac97_read,
1069         };
1070 
1071         err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus);
1072         if (err < 0)
1073                 return err;
1074         chip->ac97_bus->private_free = snd_cs4281_mixer_free_ac97_bus;
1075 
1076         memset(&ac97, 0, sizeof(ac97));
1077         ac97.private_data = chip;
1078         ac97.private_free = snd_cs4281_mixer_free_ac97;
1079         err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97);
1080         if (err < 0)
1081                 return err;
1082         if (chip->dual_codec) {
1083                 ac97.num = 1;
1084                 err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97_secondary);
1085                 if (err < 0)
1086                         return err;
1087         }
1088         err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_fm_vol, chip));
1089         if (err < 0)
1090                 return err;
1091         err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_pcm_vol, chip));
1092         if (err < 0)
1093                 return err;
1094         return 0;
1095 }
1096 
1097 
1098 /*
1099  * proc interface
1100  */
1101 
1102 static void snd_cs4281_proc_read(struct snd_info_entry *entry, 
1103                                   struct snd_info_buffer *buffer)
1104 {
1105         struct cs4281 *chip = entry->private_data;
1106 
1107         snd_iprintf(buffer, "Cirrus Logic CS4281\n\n");
1108         snd_iprintf(buffer, "Spurious half IRQs   : %u\n", chip->spurious_dhtc_irq);
1109         snd_iprintf(buffer, "Spurious end IRQs    : %u\n", chip->spurious_dtc_irq);
1110 }
1111 
1112 static ssize_t snd_cs4281_BA0_read(struct snd_info_entry *entry,
1113                                    void *file_private_data,
1114                                    struct file *file, char __user *buf,
1115                                    size_t count, loff_t pos)
1116 {
1117         struct cs4281 *chip = entry->private_data;
1118         
1119         if (copy_to_user_fromio(buf, chip->ba0 + pos, count))
1120                 return -EFAULT;
1121         return count;
1122 }
1123 
1124 static ssize_t snd_cs4281_BA1_read(struct snd_info_entry *entry,
1125                                    void *file_private_data,
1126                                    struct file *file, char __user *buf,
1127                                    size_t count, loff_t pos)
1128 {
1129         struct cs4281 *chip = entry->private_data;
1130         
1131         if (copy_to_user_fromio(buf, chip->ba1 + pos, count))
1132                 return -EFAULT;
1133         return count;
1134 }
1135 
1136 static const struct snd_info_entry_ops snd_cs4281_proc_ops_BA0 = {
1137         .read = snd_cs4281_BA0_read,
1138 };
1139 
1140 static const struct snd_info_entry_ops snd_cs4281_proc_ops_BA1 = {
1141         .read = snd_cs4281_BA1_read,
1142 };
1143 
1144 static void snd_cs4281_proc_init(struct cs4281 *chip)
1145 {
1146         struct snd_info_entry *entry;
1147 
1148         snd_card_ro_proc_new(chip->card, "cs4281", chip, snd_cs4281_proc_read);
1149         if (! snd_card_proc_new(chip->card, "cs4281_BA0", &entry)) {
1150                 entry->content = SNDRV_INFO_CONTENT_DATA;
1151                 entry->private_data = chip;
1152                 entry->c.ops = &snd_cs4281_proc_ops_BA0;
1153                 entry->size = CS4281_BA0_SIZE;
1154         }
1155         if (! snd_card_proc_new(chip->card, "cs4281_BA1", &entry)) {
1156                 entry->content = SNDRV_INFO_CONTENT_DATA;
1157                 entry->private_data = chip;
1158                 entry->c.ops = &snd_cs4281_proc_ops_BA1;
1159                 entry->size = CS4281_BA1_SIZE;
1160         }
1161 }
1162 
1163 /*
1164  * joystick support
1165  */
1166 
1167 #if IS_REACHABLE(CONFIG_GAMEPORT)
1168 
1169 static void snd_cs4281_gameport_trigger(struct gameport *gameport)
1170 {
1171         struct cs4281 *chip = gameport_get_port_data(gameport);
1172 
1173         if (snd_BUG_ON(!chip))
1174                 return;
1175         snd_cs4281_pokeBA0(chip, BA0_JSPT, 0xff);
1176 }
1177 
1178 static unsigned char snd_cs4281_gameport_read(struct gameport *gameport)
1179 {
1180         struct cs4281 *chip = gameport_get_port_data(gameport);
1181 
1182         if (snd_BUG_ON(!chip))
1183                 return 0;
1184         return snd_cs4281_peekBA0(chip, BA0_JSPT);
1185 }
1186 
1187 #ifdef COOKED_MODE
1188 static int snd_cs4281_gameport_cooked_read(struct gameport *gameport,
1189                                            int *axes, int *buttons)
1190 {
1191         struct cs4281 *chip = gameport_get_port_data(gameport);
1192         unsigned js1, js2, jst;
1193         
1194         if (snd_BUG_ON(!chip))
1195                 return 0;
1196 
1197         js1 = snd_cs4281_peekBA0(chip, BA0_JSC1);
1198         js2 = snd_cs4281_peekBA0(chip, BA0_JSC2);
1199         jst = snd_cs4281_peekBA0(chip, BA0_JSPT);
1200         
1201         *buttons = (~jst >> 4) & 0x0F; 
1202         
1203         axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
1204         axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
1205         axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
1206         axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
1207 
1208         for (jst = 0; jst < 4; ++jst)
1209                 if (axes[jst] == 0xFFFF) axes[jst] = -1;
1210         return 0;
1211 }
1212 #else
1213 #define snd_cs4281_gameport_cooked_read NULL
1214 #endif
1215 
1216 static int snd_cs4281_gameport_open(struct gameport *gameport, int mode)
1217 {
1218         switch (mode) {
1219 #ifdef COOKED_MODE
1220         case GAMEPORT_MODE_COOKED:
1221                 return 0;
1222 #endif
1223         case GAMEPORT_MODE_RAW:
1224                 return 0;
1225         default:
1226                 return -1;
1227         }
1228         return 0;
1229 }
1230 
1231 static int snd_cs4281_create_gameport(struct cs4281 *chip)
1232 {
1233         struct gameport *gp;
1234 
1235         chip->gameport = gp = gameport_allocate_port();
1236         if (!gp) {
1237                 dev_err(chip->card->dev,
1238                         "cannot allocate memory for gameport\n");
1239                 return -ENOMEM;
1240         }
1241 
1242         gameport_set_name(gp, "CS4281 Gameport");
1243         gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
1244         gameport_set_dev_parent(gp, &chip->pci->dev);
1245         gp->open = snd_cs4281_gameport_open;
1246         gp->read = snd_cs4281_gameport_read;
1247         gp->trigger = snd_cs4281_gameport_trigger;
1248         gp->cooked_read = snd_cs4281_gameport_cooked_read;
1249         gameport_set_port_data(gp, chip);
1250 
1251         snd_cs4281_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
1252         snd_cs4281_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
1253 
1254         gameport_register_port(gp);
1255 
1256         return 0;
1257 }
1258 
1259 static void snd_cs4281_free_gameport(struct cs4281 *chip)
1260 {
1261         if (chip->gameport) {
1262                 gameport_unregister_port(chip->gameport);
1263                 chip->gameport = NULL;
1264         }
1265 }
1266 #else
1267 static inline int snd_cs4281_create_gameport(struct cs4281 *chip) { return -ENOSYS; }
1268 static inline void snd_cs4281_free_gameport(struct cs4281 *chip) { }
1269 #endif /* IS_REACHABLE(CONFIG_GAMEPORT) */
1270 
1271 static int snd_cs4281_free(struct cs4281 *chip)
1272 {
1273         snd_cs4281_free_gameport(chip);
1274 
1275         /* Mask interrupts */
1276         snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff);
1277         /* Stop the DLL Clock logic. */
1278         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1279         /* Sound System Power Management - Turn Everything OFF */
1280         snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
1281         /* PCI interface - D3 state */
1282         pci_set_power_state(chip->pci, PCI_D3hot);
1283 
1284         if (chip->irq >= 0)
1285                 free_irq(chip->irq, chip);
1286         iounmap(chip->ba0);
1287         iounmap(chip->ba1);
1288         pci_release_regions(chip->pci);
1289         pci_disable_device(chip->pci);
1290 
1291         kfree(chip);
1292         return 0;
1293 }
1294 
1295 static int snd_cs4281_dev_free(struct snd_device *device)
1296 {
1297         struct cs4281 *chip = device->device_data;
1298         return snd_cs4281_free(chip);
1299 }
1300 
1301 static int snd_cs4281_chip_init(struct cs4281 *chip); /* defined below */
1302 
1303 static int snd_cs4281_create(struct snd_card *card,
1304                              struct pci_dev *pci,
1305                              struct cs4281 **rchip,
1306                              int dual_codec)
1307 {
1308         struct cs4281 *chip;
1309         unsigned int tmp;
1310         int err;
1311         static const struct snd_device_ops ops = {
1312                 .dev_free =     snd_cs4281_dev_free,
1313         };
1314 
1315         *rchip = NULL;
1316         err = pci_enable_device(pci);
1317         if (err < 0)
1318                 return err;
1319         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1320         if (chip == NULL) {
1321                 pci_disable_device(pci);
1322                 return -ENOMEM;
1323         }
1324         spin_lock_init(&chip->reg_lock);
1325         chip->card = card;
1326         chip->pci = pci;
1327         chip->irq = -1;
1328         pci_set_master(pci);
1329         if (dual_codec < 0 || dual_codec > 3) {
1330                 dev_err(card->dev, "invalid dual_codec option %d\n", dual_codec);
1331                 dual_codec = 0;
1332         }
1333         chip->dual_codec = dual_codec;
1334 
1335         err = pci_request_regions(pci, "CS4281");
1336         if (err < 0) {
1337                 kfree(chip);
1338                 pci_disable_device(pci);
1339                 return err;
1340         }
1341         chip->ba0_addr = pci_resource_start(pci, 0);
1342         chip->ba1_addr = pci_resource_start(pci, 1);
1343 
1344         chip->ba0 = pci_ioremap_bar(pci, 0);
1345         chip->ba1 = pci_ioremap_bar(pci, 1);
1346         if (!chip->ba0 || !chip->ba1) {
1347                 snd_cs4281_free(chip);
1348                 return -ENOMEM;
1349         }
1350         
1351         if (request_irq(pci->irq, snd_cs4281_interrupt, IRQF_SHARED,
1352                         KBUILD_MODNAME, chip)) {
1353                 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
1354                 snd_cs4281_free(chip);
1355                 return -ENOMEM;
1356         }
1357         chip->irq = pci->irq;
1358         card->sync_irq = chip->irq;
1359 
1360         tmp = snd_cs4281_chip_init(chip);
1361         if (tmp) {
1362                 snd_cs4281_free(chip);
1363                 return tmp;
1364         }
1365 
1366         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1367         if (err < 0) {
1368                 snd_cs4281_free(chip);
1369                 return err;
1370         }
1371 
1372         snd_cs4281_proc_init(chip);
1373 
1374         *rchip = chip;
1375         return 0;
1376 }
1377 
1378 static int snd_cs4281_chip_init(struct cs4281 *chip)
1379 {
1380         unsigned int tmp;
1381         unsigned long end_time;
1382         int retry_count = 2;
1383 
1384         /* Having EPPMC.FPDN=1 prevent proper chip initialisation */
1385         tmp = snd_cs4281_peekBA0(chip, BA0_EPPMC);
1386         if (tmp & BA0_EPPMC_FPDN)
1387                 snd_cs4281_pokeBA0(chip, BA0_EPPMC, tmp & ~BA0_EPPMC_FPDN);
1388 
1389       __retry:
1390         tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1391         if (tmp != BA0_CFLR_DEFAULT) {
1392                 snd_cs4281_pokeBA0(chip, BA0_CFLR, BA0_CFLR_DEFAULT);
1393                 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1394                 if (tmp != BA0_CFLR_DEFAULT) {
1395                         dev_err(chip->card->dev,
1396                                 "CFLR setup failed (0x%x)\n", tmp);
1397                         return -EIO;
1398                 }
1399         }
1400 
1401         /* Set the 'Configuration Write Protect' register
1402          * to 4281h.  Allows vendor-defined configuration
1403          * space between 0e4h and 0ffh to be written. */        
1404         snd_cs4281_pokeBA0(chip, BA0_CWPR, 0x4281);
1405         
1406         tmp = snd_cs4281_peekBA0(chip, BA0_SERC1);
1407         if (tmp != (BA0_SERC1_SO1EN | BA0_SERC1_AC97)) {
1408                 dev_err(chip->card->dev,
1409                         "SERC1 AC'97 check failed (0x%x)\n", tmp);
1410                 return -EIO;
1411         }
1412         tmp = snd_cs4281_peekBA0(chip, BA0_SERC2);
1413         if (tmp != (BA0_SERC2_SI1EN | BA0_SERC2_AC97)) {
1414                 dev_err(chip->card->dev,
1415                         "SERC2 AC'97 check failed (0x%x)\n", tmp);
1416                 return -EIO;
1417         }
1418 
1419         /* Sound System Power Management */
1420         snd_cs4281_pokeBA0(chip, BA0_SSPM, BA0_SSPM_MIXEN | BA0_SSPM_CSRCEN |
1421                                            BA0_SSPM_PSRCEN | BA0_SSPM_JSEN |
1422                                            BA0_SSPM_ACLEN | BA0_SSPM_FMEN);
1423 
1424         /* Serial Port Power Management */
1425         /* Blast the clock control register to zero so that the
1426          * PLL starts out in a known state, and blast the master serial
1427          * port control register to zero so that the serial ports also
1428          * start out in a known state. */
1429         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1430         snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
1431 
1432         /* Make ESYN go to zero to turn off
1433          * the Sync pulse on the AC97 link. */
1434         snd_cs4281_pokeBA0(chip, BA0_ACCTL, 0);
1435         udelay(50);
1436                 
1437         /*  Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
1438          *  spec) and then drive it high.  This is done for non AC97 modes since
1439          *  there might be logic external to the CS4281 that uses the ARST# line
1440          *  for a reset. */
1441         snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
1442         udelay(50);
1443         snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN);
1444         msleep(50);
1445 
1446         if (chip->dual_codec)
1447                 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN | BA0_SPMC_ASDI2E);
1448 
1449         /*
1450          *  Set the serial port timing configuration.
1451          */
1452         snd_cs4281_pokeBA0(chip, BA0_SERMC,
1453                            (chip->dual_codec ? BA0_SERMC_TCID(chip->dual_codec) : BA0_SERMC_TCID(1)) |
1454                            BA0_SERMC_PTC_AC97 | BA0_SERMC_MSPE);
1455 
1456         /*
1457          *  Start the DLL Clock logic.
1458          */
1459         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_DLLP);
1460         msleep(50);
1461         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_SWCE | BA0_CLKCR1_DLLP);
1462 
1463         /*
1464          * Wait for the DLL ready signal from the clock logic.
1465          */
1466         end_time = jiffies + HZ;
1467         do {
1468                 /*
1469                  *  Read the AC97 status register to see if we've seen a CODEC
1470                  *  signal from the AC97 codec.
1471                  */
1472                 if (snd_cs4281_peekBA0(chip, BA0_CLKCR1) & BA0_CLKCR1_DLLRDY)
1473                         goto __ok0;
1474                 schedule_timeout_uninterruptible(1);
1475         } while (time_after_eq(end_time, jiffies));
1476 
1477         dev_err(chip->card->dev, "DLLRDY not seen\n");
1478         return -EIO;
1479 
1480       __ok0:
1481 
1482         /*
1483          *  The first thing we do here is to enable sync generation.  As soon
1484          *  as we start receiving bit clock, we'll start producing the SYNC
1485          *  signal.
1486          */
1487         snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_ESYN);
1488 
1489         /*
1490          * Wait for the codec ready signal from the AC97 codec.
1491          */
1492         end_time = jiffies + HZ;
1493         do {
1494                 /*
1495                  *  Read the AC97 status register to see if we've seen a CODEC
1496                  *  signal from the AC97 codec.
1497                  */
1498                 if (snd_cs4281_peekBA0(chip, BA0_ACSTS) & BA0_ACSTS_CRDY)
1499                         goto __ok1;
1500                 schedule_timeout_uninterruptible(1);
1501         } while (time_after_eq(end_time, jiffies));
1502 
1503         dev_err(chip->card->dev,
1504                 "never read codec ready from AC'97 (0x%x)\n",
1505                 snd_cs4281_peekBA0(chip, BA0_ACSTS));
1506         return -EIO;
1507 
1508       __ok1:
1509         if (chip->dual_codec) {
1510                 end_time = jiffies + HZ;
1511                 do {
1512                         if (snd_cs4281_peekBA0(chip, BA0_ACSTS2) & BA0_ACSTS_CRDY)
1513                                 goto __codec2_ok;
1514                         schedule_timeout_uninterruptible(1);
1515                 } while (time_after_eq(end_time, jiffies));
1516                 dev_info(chip->card->dev,
1517                          "secondary codec doesn't respond. disable it...\n");
1518                 chip->dual_codec = 0;
1519         __codec2_ok: ;
1520         }
1521 
1522         /*
1523          *  Assert the valid frame signal so that we can start sending commands
1524          *  to the AC97 codec.
1525          */
1526 
1527         snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_VFRM | BA0_ACCTL_ESYN);
1528 
1529         /*
1530          *  Wait until we've sampled input slots 3 and 4 as valid, meaning that
1531          *  the codec is pumping ADC data across the AC-link.
1532          */
1533 
1534         end_time = jiffies + HZ;
1535         do {
1536                 /*
1537                  *  Read the input slot valid register and see if input slots 3
1538                  *  4 are valid yet.
1539                  */
1540                 if ((snd_cs4281_peekBA0(chip, BA0_ACISV) & (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) == (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4)))
1541                         goto __ok2;
1542                 schedule_timeout_uninterruptible(1);
1543         } while (time_after_eq(end_time, jiffies));
1544 
1545         if (--retry_count > 0)
1546                 goto __retry;
1547         dev_err(chip->card->dev, "never read ISV3 and ISV4 from AC'97\n");
1548         return -EIO;
1549 
1550       __ok2:
1551 
1552         /*
1553          *  Now, assert valid frame and the slot 3 and 4 valid bits.  This will
1554          *  commense the transfer of digital audio data to the AC97 codec.
1555          */
1556         snd_cs4281_pokeBA0(chip, BA0_ACOSV, BA0_ACOSV_SLV(3) | BA0_ACOSV_SLV(4));
1557 
1558         /*
1559          *  Initialize DMA structures
1560          */
1561         for (tmp = 0; tmp < 4; tmp++) {
1562                 struct cs4281_dma *dma = &chip->dma[tmp];
1563                 dma->regDBA = BA0_DBA0 + (tmp * 0x10);
1564                 dma->regDCA = BA0_DCA0 + (tmp * 0x10);
1565                 dma->regDBC = BA0_DBC0 + (tmp * 0x10);
1566                 dma->regDCC = BA0_DCC0 + (tmp * 0x10);
1567                 dma->regDMR = BA0_DMR0 + (tmp * 8);
1568                 dma->regDCR = BA0_DCR0 + (tmp * 8);
1569                 dma->regHDSR = BA0_HDSR0 + (tmp * 4);
1570                 dma->regFCR = BA0_FCR0 + (tmp * 4);
1571                 dma->regFSIC = BA0_FSIC0 + (tmp * 4);
1572                 dma->fifo_offset = tmp * CS4281_FIFO_SIZE;
1573                 snd_cs4281_pokeBA0(chip, dma->regFCR,
1574                                    BA0_FCR_LS(31) |
1575                                    BA0_FCR_RS(31) |
1576                                    BA0_FCR_SZ(CS4281_FIFO_SIZE) |
1577                                    BA0_FCR_OF(dma->fifo_offset));
1578         }
1579 
1580         chip->src_left_play_slot = 0;   /* AC'97 left PCM playback (3) */
1581         chip->src_right_play_slot = 1;  /* AC'97 right PCM playback (4) */
1582         chip->src_left_rec_slot = 10;   /* AC'97 left PCM record (3) */
1583         chip->src_right_rec_slot = 11;  /* AC'97 right PCM record (4) */
1584 
1585         /* Activate wave playback FIFO for FM playback */
1586         chip->dma[0].valFCR = BA0_FCR_FEN | BA0_FCR_LS(0) |
1587                               BA0_FCR_RS(1) |
1588                               BA0_FCR_SZ(CS4281_FIFO_SIZE) |
1589                               BA0_FCR_OF(chip->dma[0].fifo_offset);
1590         snd_cs4281_pokeBA0(chip, chip->dma[0].regFCR, chip->dma[0].valFCR);
1591         snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
1592                                             (chip->src_right_play_slot << 8) |
1593                                             (chip->src_left_rec_slot << 16) |
1594                                             (chip->src_right_rec_slot << 24));
1595 
1596         /* Initialize digital volume */
1597         snd_cs4281_pokeBA0(chip, BA0_PPLVC, 0);
1598         snd_cs4281_pokeBA0(chip, BA0_PPRVC, 0);
1599 
1600         /* Enable IRQs */
1601         snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1602         /* Unmask interrupts */
1603         snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff & ~(
1604                                         BA0_HISR_MIDI |
1605                                         BA0_HISR_DMAI |
1606                                         BA0_HISR_DMA(0) |
1607                                         BA0_HISR_DMA(1) |
1608                                         BA0_HISR_DMA(2) |
1609                                         BA0_HISR_DMA(3)));
1610 
1611         return 0;
1612 }
1613 
1614 /*
1615  *  MIDI section
1616  */
1617 
1618 static void snd_cs4281_midi_reset(struct cs4281 *chip)
1619 {
1620         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr | BA0_MIDCR_MRST);
1621         udelay(100);
1622         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1623 }
1624 
1625 static int snd_cs4281_midi_input_open(struct snd_rawmidi_substream *substream)
1626 {
1627         struct cs4281 *chip = substream->rmidi->private_data;
1628 
1629         spin_lock_irq(&chip->reg_lock);
1630         chip->midcr |= BA0_MIDCR_RXE;
1631         chip->midi_input = substream;
1632         if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
1633                 snd_cs4281_midi_reset(chip);
1634         } else {
1635                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1636         }
1637         spin_unlock_irq(&chip->reg_lock);
1638         return 0;
1639 }
1640 
1641 static int snd_cs4281_midi_input_close(struct snd_rawmidi_substream *substream)
1642 {
1643         struct cs4281 *chip = substream->rmidi->private_data;
1644 
1645         spin_lock_irq(&chip->reg_lock);
1646         chip->midcr &= ~(BA0_MIDCR_RXE | BA0_MIDCR_RIE);
1647         chip->midi_input = NULL;
1648         if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
1649                 snd_cs4281_midi_reset(chip);
1650         } else {
1651                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1652         }
1653         chip->uartm &= ~CS4281_MODE_INPUT;
1654         spin_unlock_irq(&chip->reg_lock);
1655         return 0;
1656 }
1657 
1658 static int snd_cs4281_midi_output_open(struct snd_rawmidi_substream *substream)
1659 {
1660         struct cs4281 *chip = substream->rmidi->private_data;
1661 
1662         spin_lock_irq(&chip->reg_lock);
1663         chip->uartm |= CS4281_MODE_OUTPUT;
1664         chip->midcr |= BA0_MIDCR_TXE;
1665         chip->midi_output = substream;
1666         if (!(chip->uartm & CS4281_MODE_INPUT)) {
1667                 snd_cs4281_midi_reset(chip);
1668         } else {
1669                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1670         }
1671         spin_unlock_irq(&chip->reg_lock);
1672         return 0;
1673 }
1674 
1675 static int snd_cs4281_midi_output_close(struct snd_rawmidi_substream *substream)
1676 {
1677         struct cs4281 *chip = substream->rmidi->private_data;
1678 
1679         spin_lock_irq(&chip->reg_lock);
1680         chip->midcr &= ~(BA0_MIDCR_TXE | BA0_MIDCR_TIE);
1681         chip->midi_output = NULL;
1682         if (!(chip->uartm & CS4281_MODE_INPUT)) {
1683                 snd_cs4281_midi_reset(chip);
1684         } else {
1685                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1686         }
1687         chip->uartm &= ~CS4281_MODE_OUTPUT;
1688         spin_unlock_irq(&chip->reg_lock);
1689         return 0;
1690 }
1691 
1692 static void snd_cs4281_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1693 {
1694         unsigned long flags;
1695         struct cs4281 *chip = substream->rmidi->private_data;
1696 
1697         spin_lock_irqsave(&chip->reg_lock, flags);
1698         if (up) {
1699                 if ((chip->midcr & BA0_MIDCR_RIE) == 0) {
1700                         chip->midcr |= BA0_MIDCR_RIE;
1701                         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1702                 }
1703         } else {
1704                 if (chip->midcr & BA0_MIDCR_RIE) {
1705                         chip->midcr &= ~BA0_MIDCR_RIE;
1706                         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1707                 }
1708         }
1709         spin_unlock_irqrestore(&chip->reg_lock, flags);
1710 }
1711 
1712 static void snd_cs4281_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1713 {
1714         unsigned long flags;
1715         struct cs4281 *chip = substream->rmidi->private_data;
1716         unsigned char byte;
1717 
1718         spin_lock_irqsave(&chip->reg_lock, flags);
1719         if (up) {
1720                 if ((chip->midcr & BA0_MIDCR_TIE) == 0) {
1721                         chip->midcr |= BA0_MIDCR_TIE;
1722                         /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
1723                         while ((chip->midcr & BA0_MIDCR_TIE) &&
1724                                (snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
1725                                 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
1726                                         chip->midcr &= ~BA0_MIDCR_TIE;
1727                                 } else {
1728                                         snd_cs4281_pokeBA0(chip, BA0_MIDWP, byte);
1729                                 }
1730                         }
1731                         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1732                 }
1733         } else {
1734                 if (chip->midcr & BA0_MIDCR_TIE) {
1735                         chip->midcr &= ~BA0_MIDCR_TIE;
1736                         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1737                 }
1738         }
1739         spin_unlock_irqrestore(&chip->reg_lock, flags);
1740 }
1741 
1742 static const struct snd_rawmidi_ops snd_cs4281_midi_output =
1743 {
1744         .open =         snd_cs4281_midi_output_open,
1745         .close =        snd_cs4281_midi_output_close,
1746         .trigger =      snd_cs4281_midi_output_trigger,
1747 };
1748 
1749 static const struct snd_rawmidi_ops snd_cs4281_midi_input =
1750 {
1751         .open =         snd_cs4281_midi_input_open,
1752         .close =        snd_cs4281_midi_input_close,
1753         .trigger =      snd_cs4281_midi_input_trigger,
1754 };
1755 
1756 static int snd_cs4281_midi(struct cs4281 *chip, int device)
1757 {
1758         struct snd_rawmidi *rmidi;
1759         int err;
1760 
1761         err = snd_rawmidi_new(chip->card, "CS4281", device, 1, 1, &rmidi);
1762         if (err < 0)
1763                 return err;
1764         strcpy(rmidi->name, "CS4281");
1765         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs4281_midi_output);
1766         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs4281_midi_input);
1767         rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
1768         rmidi->private_data = chip;
1769         chip->rmidi = rmidi;
1770         return 0;
1771 }
1772 
1773 /*
1774  *  Interrupt handler
1775  */
1776 
1777 static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id)
1778 {
1779         struct cs4281 *chip = dev_id;
1780         unsigned int status, dma, val;
1781         struct cs4281_dma *cdma;
1782 
1783         if (chip == NULL)
1784                 return IRQ_NONE;
1785         status = snd_cs4281_peekBA0(chip, BA0_HISR);
1786         if ((status & 0x7fffffff) == 0) {
1787                 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1788                 return IRQ_NONE;
1789         }
1790 
1791         if (status & (BA0_HISR_DMA(0)|BA0_HISR_DMA(1)|BA0_HISR_DMA(2)|BA0_HISR_DMA(3))) {
1792                 for (dma = 0; dma < 4; dma++)
1793                         if (status & BA0_HISR_DMA(dma)) {
1794                                 cdma = &chip->dma[dma];
1795                                 spin_lock(&chip->reg_lock);
1796                                 /* ack DMA IRQ */
1797                                 val = snd_cs4281_peekBA0(chip, cdma->regHDSR);
1798                                 /* workaround, sometimes CS4281 acknowledges */
1799                                 /* end or middle transfer position twice */
1800                                 cdma->frag++;
1801                                 if ((val & BA0_HDSR_DHTC) && !(cdma->frag & 1)) {
1802                                         cdma->frag--;
1803                                         chip->spurious_dhtc_irq++;
1804                                         spin_unlock(&chip->reg_lock);
1805                                         continue;
1806                                 }
1807                                 if ((val & BA0_HDSR_DTC) && (cdma->frag & 1)) {
1808                                         cdma->frag--;
1809                                         chip->spurious_dtc_irq++;
1810                                         spin_unlock(&chip->reg_lock);
1811                                         continue;
1812                                 }
1813                                 spin_unlock(&chip->reg_lock);
1814                                 snd_pcm_period_elapsed(cdma->substream);
1815                         }
1816         }
1817 
1818         if ((status & BA0_HISR_MIDI) && chip->rmidi) {
1819                 unsigned char c;
1820                 
1821                 spin_lock(&chip->reg_lock);
1822                 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_RBE) == 0) {
1823                         c = snd_cs4281_peekBA0(chip, BA0_MIDRP);
1824                         if ((chip->midcr & BA0_MIDCR_RIE) == 0)
1825                                 continue;
1826                         snd_rawmidi_receive(chip->midi_input, &c, 1);
1827                 }
1828                 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
1829                         if ((chip->midcr & BA0_MIDCR_TIE) == 0)
1830                                 break;
1831                         if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1832                                 chip->midcr &= ~BA0_MIDCR_TIE;
1833                                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1834                                 break;
1835                         }
1836                         snd_cs4281_pokeBA0(chip, BA0_MIDWP, c);
1837                 }
1838                 spin_unlock(&chip->reg_lock);
1839         }
1840 
1841         /* EOI to the PCI part... reenables interrupts */
1842         snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1843 
1844         return IRQ_HANDLED;
1845 }
1846 
1847 
1848 /*
1849  * OPL3 command
1850  */
1851 static void snd_cs4281_opl3_command(struct snd_opl3 *opl3, unsigned short cmd,
1852                                     unsigned char val)
1853 {
1854         unsigned long flags;
1855         struct cs4281 *chip = opl3->private_data;
1856         void __iomem *port;
1857 
1858         if (cmd & OPL3_RIGHT)
1859                 port = chip->ba0 + BA0_B1AP; /* right port */
1860         else
1861                 port = chip->ba0 + BA0_B0AP; /* left port */
1862 
1863         spin_lock_irqsave(&opl3->reg_lock, flags);
1864 
1865         writel((unsigned int)cmd, port);
1866         udelay(10);
1867 
1868         writel((unsigned int)val, port + 4);
1869         udelay(30);
1870 
1871         spin_unlock_irqrestore(&opl3->reg_lock, flags);
1872 }
1873 
1874 static int snd_cs4281_probe(struct pci_dev *pci,
1875                             const struct pci_device_id *pci_id)
1876 {
1877         static int dev;
1878         struct snd_card *card;
1879         struct cs4281 *chip;
1880         struct snd_opl3 *opl3;
1881         int err;
1882 
1883         if (dev >= SNDRV_CARDS)
1884                 return -ENODEV;
1885         if (!enable[dev]) {
1886                 dev++;
1887                 return -ENOENT;
1888         }
1889 
1890         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1891                            0, &card);
1892         if (err < 0)
1893                 return err;
1894 
1895         err = snd_cs4281_create(card, pci, &chip, dual_codec[dev]);
1896         if (err < 0) {
1897                 snd_card_free(card);
1898                 return err;
1899         }
1900         card->private_data = chip;
1901 
1902         err = snd_cs4281_mixer(chip);
1903         if (err < 0) {
1904                 snd_card_free(card);
1905                 return err;
1906         }
1907         err = snd_cs4281_pcm(chip, 0);
1908         if (err < 0) {
1909                 snd_card_free(card);
1910                 return err;
1911         }
1912         err = snd_cs4281_midi(chip, 0);
1913         if (err < 0) {
1914                 snd_card_free(card);
1915                 return err;
1916         }
1917         err = snd_opl3_new(card, OPL3_HW_OPL3_CS4281, &opl3);
1918         if (err < 0) {
1919                 snd_card_free(card);
1920                 return err;
1921         }
1922         opl3->private_data = chip;
1923         opl3->command = snd_cs4281_opl3_command;
1924         snd_opl3_init(opl3);
1925         err = snd_opl3_hwdep_new(opl3, 0, 1, NULL);
1926         if (err < 0) {
1927                 snd_card_free(card);
1928                 return err;
1929         }
1930         snd_cs4281_create_gameport(chip);
1931         strcpy(card->driver, "CS4281");
1932         strcpy(card->shortname, "Cirrus Logic CS4281");
1933         sprintf(card->longname, "%s at 0x%lx, irq %d",
1934                 card->shortname,
1935                 chip->ba0_addr,
1936                 chip->irq);
1937 
1938         err = snd_card_register(card);
1939         if (err < 0) {
1940                 snd_card_free(card);
1941                 return err;
1942         }
1943 
1944         pci_set_drvdata(pci, card);
1945         dev++;
1946         return 0;
1947 }
1948 
1949 static void snd_cs4281_remove(struct pci_dev *pci)
1950 {
1951         snd_card_free(pci_get_drvdata(pci));
1952 }
1953 
1954 /*
1955  * Power Management
1956  */
1957 #ifdef CONFIG_PM_SLEEP
1958 
1959 static const int saved_regs[SUSPEND_REGISTERS] = {
1960         BA0_JSCTL,
1961         BA0_GPIOR,
1962         BA0_SSCR,
1963         BA0_MIDCR,
1964         BA0_SRCSA,
1965         BA0_PASR,
1966         BA0_CASR,
1967         BA0_DACSR,
1968         BA0_ADCSR,
1969         BA0_FMLVC,
1970         BA0_FMRVC,
1971         BA0_PPLVC,
1972         BA0_PPRVC,
1973 };
1974 
1975 #define CLKCR1_CKRA                             0x00010000L
1976 
1977 static int cs4281_suspend(struct device *dev)
1978 {
1979         struct snd_card *card = dev_get_drvdata(dev);
1980         struct cs4281 *chip = card->private_data;
1981         u32 ulCLK;
1982         unsigned int i;
1983 
1984         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1985         snd_ac97_suspend(chip->ac97);
1986         snd_ac97_suspend(chip->ac97_secondary);
1987 
1988         ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
1989         ulCLK |= CLKCR1_CKRA;
1990         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
1991 
1992         /* Disable interrupts. */
1993         snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_CHGM);
1994 
1995         /* remember the status registers */
1996         for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
1997                 if (saved_regs[i])
1998                         chip->suspend_regs[i] = snd_cs4281_peekBA0(chip, saved_regs[i]);
1999 
2000         /* Turn off the serial ports. */
2001         snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
2002 
2003         /* Power off FM, Joystick, AC link, */
2004         snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
2005 
2006         /* DLL off. */
2007         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
2008 
2009         /* AC link off. */
2010         snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
2011 
2012         ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2013         ulCLK &= ~CLKCR1_CKRA;
2014         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2015         return 0;
2016 }
2017 
2018 static int cs4281_resume(struct device *dev)
2019 {
2020         struct snd_card *card = dev_get_drvdata(dev);
2021         struct cs4281 *chip = card->private_data;
2022         unsigned int i;
2023         u32 ulCLK;
2024 
2025         ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2026         ulCLK |= CLKCR1_CKRA;
2027         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2028 
2029         snd_cs4281_chip_init(chip);
2030 
2031         /* restore the status registers */
2032         for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
2033                 if (saved_regs[i])
2034                         snd_cs4281_pokeBA0(chip, saved_regs[i], chip->suspend_regs[i]);
2035 
2036         snd_ac97_resume(chip->ac97);
2037         snd_ac97_resume(chip->ac97_secondary);
2038 
2039         ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2040         ulCLK &= ~CLKCR1_CKRA;
2041         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2042 
2043         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2044         return 0;
2045 }
2046 
2047 static SIMPLE_DEV_PM_OPS(cs4281_pm, cs4281_suspend, cs4281_resume);
2048 #define CS4281_PM_OPS   &cs4281_pm
2049 #else
2050 #define CS4281_PM_OPS   NULL
2051 #endif /* CONFIG_PM_SLEEP */
2052 
2053 static struct pci_driver cs4281_driver = {
2054         .name = KBUILD_MODNAME,
2055         .id_table = snd_cs4281_ids,
2056         .probe = snd_cs4281_probe,
2057         .remove = snd_cs4281_remove,
2058         .driver = {
2059                 .pm = CS4281_PM_OPS,
2060         },
2061 };
2062         
2063 module_pci_driver(cs4281_driver);
2064 

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