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TOMOYO Linux Cross Reference
Linux/sound/pci/emu10k1/emu10k1_main.c

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  1 /*
  2  *  Copyright (c) by Jaroslav Kysela <perex@suse.cz>
  3  *                   Creative Labs, Inc.
  4  *  Routines for control of EMU10K1 chips
  5  *
  6  *  BUGS:
  7  *    --
  8  *
  9  *  TODO:
 10  *    --
 11  *
 12  *   This program is free software; you can redistribute it and/or modify
 13  *   it under the terms of the GNU General Public License as published by
 14  *   the Free Software Foundation; either version 2 of the License, or
 15  *   (at your option) any later version.
 16  *
 17  *   This program is distributed in the hope that it will be useful,
 18  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 19  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 20  *   GNU General Public License for more details.
 21  *
 22  *   You should have received a copy of the GNU General Public License
 23  *   along with this program; if not, write to the Free Software
 24  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 25  *
 26  */
 27 
 28 #include <sound/driver.h>
 29 #include <linux/delay.h>
 30 #include <linux/init.h>
 31 #include <linux/interrupt.h>
 32 #include <linux/pci.h>
 33 #include <linux/slab.h>
 34 #include <linux/vmalloc.h>
 35 
 36 #include <sound/core.h>
 37 #include <sound/emu10k1.h>
 38 
 39 #if 0
 40 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>, Creative Labs, Inc.");
 41 MODULE_DESCRIPTION("Routines for control of EMU10K1 chips");
 42 MODULE_LICENSE("GPL");
 43 #endif
 44 
 45 /*************************************************************************
 46  * EMU10K1 init / done
 47  *************************************************************************/
 48 
 49 void snd_emu10k1_voice_init(emu10k1_t * emu, int ch)
 50 {
 51         snd_emu10k1_ptr_write(emu, DCYSUSV, ch, 0);
 52         snd_emu10k1_ptr_write(emu, IP, ch, 0);
 53         snd_emu10k1_ptr_write(emu, VTFT, ch, 0xffff);
 54         snd_emu10k1_ptr_write(emu, CVCF, ch, 0xffff);
 55         snd_emu10k1_ptr_write(emu, PTRX, ch, 0);
 56         snd_emu10k1_ptr_write(emu, CPF, ch, 0);
 57         snd_emu10k1_ptr_write(emu, CCR, ch, 0);
 58 
 59         snd_emu10k1_ptr_write(emu, PSST, ch, 0);
 60         snd_emu10k1_ptr_write(emu, DSL, ch, 0x10);
 61         snd_emu10k1_ptr_write(emu, CCCA, ch, 0);
 62         snd_emu10k1_ptr_write(emu, Z1, ch, 0);
 63         snd_emu10k1_ptr_write(emu, Z2, ch, 0);
 64         snd_emu10k1_ptr_write(emu, FXRT, ch, 0x32100000);
 65 
 66         snd_emu10k1_ptr_write(emu, ATKHLDM, ch, 0);
 67         snd_emu10k1_ptr_write(emu, DCYSUSM, ch, 0);
 68         snd_emu10k1_ptr_write(emu, IFATN, ch, 0xffff);
 69         snd_emu10k1_ptr_write(emu, PEFE, ch, 0);
 70         snd_emu10k1_ptr_write(emu, FMMOD, ch, 0);
 71         snd_emu10k1_ptr_write(emu, TREMFRQ, ch, 24);    /* 1 Hz */
 72         snd_emu10k1_ptr_write(emu, FM2FRQ2, ch, 24);    /* 1 Hz */
 73         snd_emu10k1_ptr_write(emu, TEMPENV, ch, 0);
 74 
 75         /*** these are last so OFF prevents writing ***/
 76         snd_emu10k1_ptr_write(emu, LFOVAL2, ch, 0);
 77         snd_emu10k1_ptr_write(emu, LFOVAL1, ch, 0);
 78         snd_emu10k1_ptr_write(emu, ATKHLDV, ch, 0);
 79         snd_emu10k1_ptr_write(emu, ENVVOL, ch, 0);
 80         snd_emu10k1_ptr_write(emu, ENVVAL, ch, 0);
 81 
 82         /* Audigy extra stuffs */
 83         if (emu->audigy) {
 84                 snd_emu10k1_ptr_write(emu, 0x4c, ch, 0); /* ?? */
 85                 snd_emu10k1_ptr_write(emu, 0x4d, ch, 0); /* ?? */
 86                 snd_emu10k1_ptr_write(emu, 0x4e, ch, 0); /* ?? */
 87                 snd_emu10k1_ptr_write(emu, 0x4f, ch, 0); /* ?? */
 88                 snd_emu10k1_ptr_write(emu, A_FXRT1, ch, 0x03020100);
 89                 snd_emu10k1_ptr_write(emu, A_FXRT2, ch, 0x3f3f3f3f);
 90                 snd_emu10k1_ptr_write(emu, A_SENDAMOUNTS, ch, 0);
 91         }
 92 }
 93 
 94 static int __devinit snd_emu10k1_init(emu10k1_t * emu, int enable_ir)
 95 {
 96         int ch, idx, err;
 97         unsigned int silent_page;
 98 
 99         emu->fx8010.itram_size = (16 * 1024)/2;
100         emu->fx8010.etram_size = 0;
101 
102         /* disable audio and lock cache */
103         outl(HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | HCFG_MUTEBUTTONENABLE, emu->port + HCFG);
104 
105         /* reset recording buffers */
106         snd_emu10k1_ptr_write(emu, MICBS, 0, ADCBS_BUFSIZE_NONE);
107         snd_emu10k1_ptr_write(emu, MICBA, 0, 0);
108         snd_emu10k1_ptr_write(emu, FXBS, 0, ADCBS_BUFSIZE_NONE);
109         snd_emu10k1_ptr_write(emu, FXBA, 0, 0);
110         snd_emu10k1_ptr_write(emu, ADCBS, 0, ADCBS_BUFSIZE_NONE);
111         snd_emu10k1_ptr_write(emu, ADCBA, 0, 0);
112 
113         /* disable channel interrupt */
114         outl(0, emu->port + INTE);
115         snd_emu10k1_ptr_write(emu, CLIEL, 0, 0);
116         snd_emu10k1_ptr_write(emu, CLIEH, 0, 0);
117         snd_emu10k1_ptr_write(emu, SOLEL, 0, 0);
118         snd_emu10k1_ptr_write(emu, SOLEH, 0, 0);
119 
120         if (emu->audigy){
121                 snd_emu10k1_ptr_write(emu, 0x5e, 0, 0xf00); /* ?? */
122                 snd_emu10k1_ptr_write(emu, 0x5f, 0, 0x3); /* ?? */
123         }
124 
125         /* init envelope engine */
126         for (ch = 0; ch < NUM_G; ch++) {
127                 emu->voices[ch].emu = emu;
128                 emu->voices[ch].number = ch;
129                 snd_emu10k1_voice_init(emu, ch);
130         }
131 
132         /*
133          *  Init to 0x02109204 :
134          *  Clock accuracy    = 0     (1000ppm)
135          *  Sample Rate       = 2     (48kHz)
136          *  Audio Channel     = 1     (Left of 2)
137          *  Source Number     = 0     (Unspecified)
138          *  Generation Status = 1     (Original for Cat Code 12)
139          *  Cat Code          = 12    (Digital Signal Mixer)
140          *  Mode              = 0     (Mode 0)
141          *  Emphasis          = 0     (None)
142          *  CP                = 1     (Copyright unasserted)
143          *  AN                = 0     (Audio data)
144          *  P                 = 0     (Consumer)
145          */
146         snd_emu10k1_ptr_write(emu, SPCS0, 0,
147                         emu->spdif_bits[0] =
148                         SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 |
149                         SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC |
150                         SPCS_GENERATIONSTATUS | 0x00001200 |
151                         0x00000000 | SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT);
152         snd_emu10k1_ptr_write(emu, SPCS1, 0,
153                         emu->spdif_bits[1] =
154                         SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 |
155                         SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC |
156                         SPCS_GENERATIONSTATUS | 0x00001200 |
157                         0x00000000 | SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT);
158         snd_emu10k1_ptr_write(emu, SPCS2, 0,
159                         emu->spdif_bits[2] =
160                         SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 |
161                         SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC |
162                         SPCS_GENERATIONSTATUS | 0x00001200 |
163                         0x00000000 | SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT);
164 
165         if (emu->audigy && emu->revision == 4) { /* audigy2 */
166                 /* Hacks for Alice3 to work independent of haP16V driver */
167                 u32 tmp;
168 
169                 //Setup SRCMulti_I2S SamplingRate
170                 tmp = snd_emu10k1_ptr_read(emu, A_SPDIF_SAMPLERATE, 0);
171                 tmp &= 0xfffff1ff;
172                 tmp |= (0x2<<9);
173                 snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, 0, tmp);
174 
175                 /* Setup SRCSel (Enable Spdif,I2S SRCMulti) */
176                 outl(0x600000, emu->port + 0x20);
177                 outl(0x14, emu->port + 0x24);
178 
179                 /* Setup SRCMulti Input Audio Enable */
180                 outl(0x6E0000, emu->port + 0x20);
181                 outl(0xFF00FF00, emu->port + 0x24);
182         }
183 
184         /*
185          *  Clear page with silence & setup all pointers to this page
186          */
187         memset(emu->silent_page, 0, PAGE_SIZE);
188         silent_page = emu->silent_page_dmaaddr << 1;
189         for (idx = 0; idx < MAXPAGES; idx++)
190                 emu->ptb_pages[idx] = cpu_to_le32(silent_page | idx);
191         snd_emu10k1_ptr_write(emu, PTB, 0, emu->ptb_pages_dmaaddr);
192         snd_emu10k1_ptr_write(emu, TCB, 0, 0);  /* taken from original driver */
193         snd_emu10k1_ptr_write(emu, TCBS, 0, 4); /* taken from original driver */
194 
195         silent_page = (emu->silent_page_dmaaddr << 1) | MAP_PTI_MASK;
196         for (ch = 0; ch < NUM_G; ch++) {
197                 snd_emu10k1_ptr_write(emu, MAPA, ch, silent_page);
198                 snd_emu10k1_ptr_write(emu, MAPB, ch, silent_page);
199         }
200 
201         /*
202          *  Hokay, setup HCFG
203          *   Mute Disable Audio = 0
204          *   Lock Tank Memory = 1
205          *   Lock Sound Memory = 0
206          *   Auto Mute = 1
207          */
208         if (emu->audigy) {
209                 if (emu->revision == 4) /* audigy2 */
210                         outl(HCFG_AUDIOENABLE |
211                              HCFG_AC3ENABLE_CDSPDIF |
212                              HCFG_AC3ENABLE_GPSPDIF |
213                              HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG);
214                 else
215                         outl(HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG);
216         } else if (emu->model == 0x20 ||
217             emu->model == 0xc400 ||
218             (emu->model == 0x21 && emu->revision < 6))
219                 outl(HCFG_LOCKTANKCACHE_MASK | HCFG_AUTOMUTE, emu->port + HCFG);
220         else
221                 // With on-chip joystick
222                 outl(HCFG_LOCKTANKCACHE_MASK | HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG);
223 
224         if (enable_ir) {        /* enable IR for SB Live */
225                 if (emu->audigy) {
226                         unsigned int reg = inl(emu->port + A_IOCFG);
227                         outl(reg | A_IOCFG_GPOUT2, emu->port + A_IOCFG);
228                         udelay(500);
229                         outl(reg | A_IOCFG_GPOUT1 | A_IOCFG_GPOUT2, emu->port + A_IOCFG);
230                         udelay(100);
231                         outl(reg, emu->port + A_IOCFG);
232                 } else {
233                         unsigned int reg = inl(emu->port + HCFG);
234                         outl(reg | HCFG_GPOUT2, emu->port + HCFG);
235                         udelay(500);
236                         outl(reg | HCFG_GPOUT1 | HCFG_GPOUT2, emu->port + HCFG);
237                         udelay(100);
238                         outl(reg, emu->port + HCFG);
239                 }
240         }
241         
242         if (!emu->APS) {        /* enable analog output */
243                 if (!emu->audigy) {
244                         unsigned int reg = inl(emu->port + HCFG);
245                         outl(reg | HCFG_GPOUT0, emu->port + HCFG);
246                 } else {
247                         unsigned int reg = inl(emu->port + A_IOCFG);
248                         outl(reg | A_IOCFG_GPOUT0, emu->port + A_IOCFG);
249                 }
250         }
251 
252         /*
253          *  Initialize the effect engine
254          */
255         if ((err = snd_emu10k1_init_efx(emu)) < 0)
256                 return err;
257 
258         /*
259          *  Enable the audio bit
260          */
261         outl(inl(emu->port + HCFG) | HCFG_AUDIOENABLE, emu->port + HCFG);
262 
263         /* Enable analog/digital outs on audigy */
264         if (emu->audigy) {
265                 outl(inl(emu->port + A_IOCFG) & ~0x44, emu->port + A_IOCFG);
266  
267                 if (emu->revision == 4) { /* audigy2 */
268                         /* Unmute Analog now.  Set GPO6 to 1 for Apollo.
269                          * This has to be done after init ALice3 I2SOut beyond 48KHz.
270                          * So, sequence is important. */
271                         outl(inl(emu->port + A_IOCFG) | 0x0040, emu->port + A_IOCFG);
272                 }
273         }
274         
275 #if 0
276         {
277         unsigned int tmp;
278         /* FIXME: the following routine disables LiveDrive-II !! */
279         // TOSLink detection
280         emu->tos_link = 0;
281         tmp = inl(emu->port + HCFG);
282         if (tmp & (HCFG_GPINPUT0 | HCFG_GPINPUT1)) {
283                 outl(tmp|0x800, emu->port + HCFG);
284                 udelay(50);
285                 if (tmp != (inl(emu->port + HCFG) & ~0x800)) {
286                         emu->tos_link = 1;
287                         outl(tmp, emu->port + HCFG);
288                 }
289         }
290         }
291 #endif
292 
293         snd_emu10k1_intr_enable(emu, INTE_PCIERRORENABLE);
294 
295         emu->reserved_page = (emu10k1_memblk_t *)snd_emu10k1_synth_alloc(emu, 4096);
296         if (emu->reserved_page)
297                 emu->reserved_page->map_locked = 1;
298         
299         return 0;
300 }
301 
302 static int snd_emu10k1_done(emu10k1_t * emu)
303 {
304         int ch;
305 
306         outl(0, emu->port + INTE);
307 
308         /*
309          *  Shutdown the chip
310          */
311         for (ch = 0; ch < NUM_G; ch++)
312                 snd_emu10k1_ptr_write(emu, DCYSUSV, ch, 0);
313         for (ch = 0; ch < NUM_G; ch++) {
314                 snd_emu10k1_ptr_write(emu, VTFT, ch, 0);
315                 snd_emu10k1_ptr_write(emu, CVCF, ch, 0);
316                 snd_emu10k1_ptr_write(emu, PTRX, ch, 0);
317                 snd_emu10k1_ptr_write(emu, CPF, ch, 0);
318         }
319 
320         /* reset recording buffers */
321         snd_emu10k1_ptr_write(emu, MICBS, 0, 0);
322         snd_emu10k1_ptr_write(emu, MICBA, 0, 0);
323         snd_emu10k1_ptr_write(emu, FXBS, 0, 0);
324         snd_emu10k1_ptr_write(emu, FXBA, 0, 0);
325         snd_emu10k1_ptr_write(emu, FXWC, 0, 0);
326         snd_emu10k1_ptr_write(emu, ADCBS, 0, ADCBS_BUFSIZE_NONE);
327         snd_emu10k1_ptr_write(emu, ADCBA, 0, 0);
328         snd_emu10k1_ptr_write(emu, TCBS, 0, TCBS_BUFFSIZE_16K);
329         snd_emu10k1_ptr_write(emu, TCB, 0, 0);
330         if (emu->audigy)
331                 snd_emu10k1_ptr_write(emu, A_DBG, 0, A_DBG_SINGLE_STEP);
332         else
333                 snd_emu10k1_ptr_write(emu, DBG, 0, 0x8000);
334 
335         /* disable channel interrupt */
336         snd_emu10k1_ptr_write(emu, CLIEL, 0, 0);
337         snd_emu10k1_ptr_write(emu, CLIEH, 0, 0);
338         snd_emu10k1_ptr_write(emu, SOLEL, 0, 0);
339         snd_emu10k1_ptr_write(emu, SOLEH, 0, 0);
340 
341         /* remove reserved page */
342         if (emu->reserved_page != NULL) {
343                 snd_emu10k1_synth_free(emu, (snd_util_memblk_t *)emu->reserved_page);
344                 emu->reserved_page = NULL;
345         }
346 
347         /* disable audio and lock cache */
348         outl(HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | HCFG_MUTEBUTTONENABLE, emu->port + HCFG);
349         snd_emu10k1_ptr_write(emu, PTB, 0, 0);
350 
351         snd_emu10k1_free_efx(emu);
352 
353         return 0;
354 }
355 
356 /*************************************************************************
357  * ECARD functional implementation
358  *************************************************************************/
359 
360 /* In A1 Silicon, these bits are in the HC register */
361 #define HOOKN_BIT               (1L << 12)
362 #define HANDN_BIT               (1L << 11)
363 #define PULSEN_BIT              (1L << 10)
364 
365 #define EC_GDI1                 (1 << 13)
366 #define EC_GDI0                 (1 << 14)
367 
368 #define EC_NUM_CONTROL_BITS     20
369 
370 #define EC_AC3_DATA_SELN        0x0001L
371 #define EC_EE_DATA_SEL          0x0002L
372 #define EC_EE_CNTRL_SELN        0x0004L
373 #define EC_EECLK                0x0008L
374 #define EC_EECS                 0x0010L
375 #define EC_EESDO                0x0020L
376 #define EC_TRIM_CSN             0x0040L
377 #define EC_TRIM_SCLK            0x0080L
378 #define EC_TRIM_SDATA           0x0100L
379 #define EC_TRIM_MUTEN           0x0200L
380 #define EC_ADCCAL               0x0400L
381 #define EC_ADCRSTN              0x0800L
382 #define EC_DACCAL               0x1000L
383 #define EC_DACMUTEN             0x2000L
384 #define EC_LEDN                 0x4000L
385 
386 #define EC_SPDIF0_SEL_SHIFT     15
387 #define EC_SPDIF1_SEL_SHIFT     17
388 #define EC_SPDIF0_SEL_MASK      (0x3L << EC_SPDIF0_SEL_SHIFT)
389 #define EC_SPDIF1_SEL_MASK      (0x7L << EC_SPDIF1_SEL_SHIFT)
390 #define EC_SPDIF0_SELECT(_x)    (((_x) << EC_SPDIF0_SEL_SHIFT) & EC_SPDIF0_SEL_MASK)
391 #define EC_SPDIF1_SELECT(_x)    (((_x) << EC_SPDIF1_SEL_SHIFT) & EC_SPDIF1_SEL_MASK)
392 #define EC_CURRENT_PROM_VERSION 0x01    /* Self-explanatory.  This should
393                                          * be incremented any time the EEPROM's
394                                          * format is changed.  */
395 
396 #define EC_EEPROM_SIZE          0x40    /* ECARD EEPROM has 64 16-bit words */
397 
398 /* Addresses for special values stored in to EEPROM */
399 #define EC_PROM_VERSION_ADDR    0x20    /* Address of the current prom version */
400 #define EC_BOARDREV0_ADDR       0x21    /* LSW of board rev */
401 #define EC_BOARDREV1_ADDR       0x22    /* MSW of board rev */
402 
403 #define EC_LAST_PROMFILE_ADDR   0x2f
404 
405 #define EC_SERIALNUM_ADDR       0x30    /* First word of serial number.  The 
406                                          * can be up to 30 characters in length
407                                          * and is stored as a NULL-terminated
408                                          * ASCII string.  Any unused bytes must be
409                                          * filled with zeros */
410 #define EC_CHECKSUM_ADDR        0x3f    /* Location at which checksum is stored */
411 
412 
413 /* Most of this stuff is pretty self-evident.  According to the hardware 
414  * dudes, we need to leave the ADCCAL bit low in order to avoid a DC 
415  * offset problem.  Weird.
416  */
417 #define EC_RAW_RUN_MODE         (EC_DACMUTEN | EC_ADCRSTN | EC_TRIM_MUTEN | \
418                                  EC_TRIM_CSN)
419 
420 
421 #define EC_DEFAULT_ADC_GAIN     0xC4C4
422 #define EC_DEFAULT_SPDIF0_SEL   0x0
423 #define EC_DEFAULT_SPDIF1_SEL   0x4
424 
425 /**************************************************************************
426  * @func Clock bits into the Ecard's control latch.  The Ecard uses a
427  *  control latch will is loaded bit-serially by toggling the Modem control
428  *  lines from function 2 on the E8010.  This function hides these details
429  *  and presents the illusion that we are actually writing to a distinct
430  *  register.
431  */
432 
433 static void snd_emu10k1_ecard_write(emu10k1_t * emu, unsigned int value)
434 {
435         unsigned short count;
436         unsigned int data;
437         unsigned long hc_port;
438         unsigned int hc_value;
439 
440         hc_port = emu->port + HCFG;
441         hc_value = inl(hc_port) & ~(HOOKN_BIT | HANDN_BIT | PULSEN_BIT);
442         outl(hc_value, hc_port);
443 
444         for (count = 0; count < EC_NUM_CONTROL_BITS; count++) {
445 
446                 /* Set up the value */
447                 data = ((value & 0x1) ? PULSEN_BIT : 0);
448                 value >>= 1;
449 
450                 outl(hc_value | data, hc_port);
451 
452                 /* Clock the shift register */
453                 outl(hc_value | data | HANDN_BIT, hc_port);
454                 outl(hc_value | data, hc_port);
455         }
456 
457         /* Latch the bits */
458         outl(hc_value | HOOKN_BIT, hc_port);
459         outl(hc_value, hc_port);
460 }
461 
462 /**************************************************************************
463  * @func Set the gain of the ECARD's CS3310 Trim/gain controller.  The
464  * trim value consists of a 16bit value which is composed of two
465  * 8 bit gain/trim values, one for the left channel and one for the
466  * right channel.  The following table maps from the Gain/Attenuation
467  * value in decibels into the corresponding bit pattern for a single
468  * channel.
469  */
470 
471 static void snd_emu10k1_ecard_setadcgain(emu10k1_t * emu,
472                                          unsigned short gain)
473 {
474         unsigned int bit;
475 
476         /* Enable writing to the TRIM registers */
477         snd_emu10k1_ecard_write(emu, emu->ecard_ctrl & ~EC_TRIM_CSN);
478 
479         /* Do it again to insure that we meet hold time requirements */
480         snd_emu10k1_ecard_write(emu, emu->ecard_ctrl & ~EC_TRIM_CSN);
481 
482         for (bit = (1 << 15); bit; bit >>= 1) {
483                 unsigned int value;
484                 
485                 value = emu->ecard_ctrl & ~(EC_TRIM_CSN | EC_TRIM_SDATA);
486 
487                 if (gain & bit)
488                         value |= EC_TRIM_SDATA;
489 
490                 /* Clock the bit */
491                 snd_emu10k1_ecard_write(emu, value);
492                 snd_emu10k1_ecard_write(emu, value | EC_TRIM_SCLK);
493                 snd_emu10k1_ecard_write(emu, value);
494         }
495 
496         snd_emu10k1_ecard_write(emu, emu->ecard_ctrl);
497 }
498 
499 static int __devinit snd_emu10k1_ecard_init(emu10k1_t * emu)
500 {
501         unsigned int hc_value;
502 
503         /* Set up the initial settings */
504         emu->ecard_ctrl = EC_RAW_RUN_MODE |
505                           EC_SPDIF0_SELECT(EC_DEFAULT_SPDIF0_SEL) |
506                           EC_SPDIF1_SELECT(EC_DEFAULT_SPDIF1_SEL);
507 
508         /* Step 0: Set the codec type in the hardware control register 
509          * and enable audio output */
510         hc_value = inl(emu->port + HCFG);
511         outl(hc_value | HCFG_AUDIOENABLE | HCFG_CODECFORMAT_I2S, emu->port + HCFG);
512         inl(emu->port + HCFG);
513 
514         /* Step 1: Turn off the led and deassert TRIM_CS */
515         snd_emu10k1_ecard_write(emu, EC_ADCCAL | EC_LEDN | EC_TRIM_CSN);
516 
517         /* Step 2: Calibrate the ADC and DAC */
518         snd_emu10k1_ecard_write(emu, EC_DACCAL | EC_LEDN | EC_TRIM_CSN);
519 
520         /* Step 3: Wait for awhile;   XXX We can't get away with this
521          * under a real operating system; we'll need to block and wait that
522          * way. */
523         snd_emu10k1_wait(emu, 48000);
524 
525         /* Step 4: Switch off the DAC and ADC calibration.  Note
526          * That ADC_CAL is actually an inverted signal, so we assert
527          * it here to stop calibration.  */
528         snd_emu10k1_ecard_write(emu, EC_ADCCAL | EC_LEDN | EC_TRIM_CSN);
529 
530         /* Step 4: Switch into run mode */
531         snd_emu10k1_ecard_write(emu, emu->ecard_ctrl);
532 
533         /* Step 5: Set the analog input gain */
534         snd_emu10k1_ecard_setadcgain(emu, EC_DEFAULT_ADC_GAIN);
535 
536         return 0;
537 }
538 
539 /*
540  *  Create the EMU10K1 instance
541  */
542 
543 static int snd_emu10k1_free(emu10k1_t *emu)
544 {
545         if (emu->res_port != NULL) {    /* avoid access to already used hardware */
546                 snd_emu10k1_fx8010_tram_setup(emu, 0);
547                 snd_emu10k1_done(emu);
548         }
549         if (emu->memhdr)
550                 snd_util_memhdr_free(emu->memhdr);
551         if (emu->silent_page)
552                 snd_free_pci_pages(emu->pci, EMUPAGESIZE, emu->silent_page, emu->silent_page_dmaaddr);
553         if (emu->ptb_pages)
554                 snd_free_pci_pages(emu->pci, 32 * 1024, (void *)emu->ptb_pages, emu->ptb_pages_dmaaddr);
555         if (emu->page_ptr_table)
556                 vfree(emu->page_ptr_table);
557         if (emu->page_addr_table)
558                 vfree(emu->page_addr_table);
559         if (emu->res_port) {
560                 release_resource(emu->res_port);
561                 kfree_nocheck(emu->res_port);
562         }
563         if (emu->irq >= 0)
564                 free_irq(emu->irq, (void *)emu);
565         snd_magic_kfree(emu);
566         return 0;
567 }
568 
569 static int snd_emu10k1_dev_free(snd_device_t *device)
570 {
571         emu10k1_t *emu = snd_magic_cast(emu10k1_t, device->device_data, return -ENXIO);
572         return snd_emu10k1_free(emu);
573 }
574 
575 int __devinit snd_emu10k1_create(snd_card_t * card,
576                        struct pci_dev * pci,
577                        unsigned short extin_mask,
578                        unsigned short extout_mask,
579                        long max_cache_bytes,
580                        int enable_ir,
581                        emu10k1_t ** remu)
582 {
583         emu10k1_t *emu;
584         int err;
585         int is_audigy;
586         static snd_device_ops_t ops = {
587                 .dev_free =     snd_emu10k1_dev_free,
588         };
589         
590         *remu = NULL;
591 
592         // is_audigy = (int)pci->driver_data;
593         is_audigy = (pci->device == 0x0004);
594 
595         /* enable PCI device */
596         if ((err = pci_enable_device(pci)) < 0)
597                 return err;
598 
599         emu = snd_magic_kcalloc(emu10k1_t, 0, GFP_KERNEL);
600         if (emu == NULL)
601                 return -ENOMEM;
602         /* set the DMA transfer mask */
603         emu->dma_mask = is_audigy ? AUDIGY_DMA_MASK : EMU10K1_DMA_MASK;
604         if (pci_set_dma_mask(pci, emu->dma_mask) < 0) {
605                 snd_printk(KERN_ERR "architecture does not support PCI busmaster DMA with mask 0x%lx\n", emu->dma_mask);
606                 snd_magic_kfree(emu);
607                 return -ENXIO;
608         }
609         emu->card = card;
610         spin_lock_init(&emu->reg_lock);
611         spin_lock_init(&emu->emu_lock);
612         spin_lock_init(&emu->voice_lock);
613         spin_lock_init(&emu->synth_lock);
614         spin_lock_init(&emu->memblk_lock);
615         init_MUTEX(&emu->ptb_lock);
616         init_MUTEX(&emu->fx8010.lock);
617         INIT_LIST_HEAD(&emu->mapped_link_head);
618         INIT_LIST_HEAD(&emu->mapped_order_link_head);
619         emu->pci = pci;
620         emu->irq = -1;
621         emu->synth = NULL;
622         emu->get_synth_voice = NULL;
623         emu->port = pci_resource_start(pci, 0);
624 
625         emu->audigy = is_audigy;
626         if (is_audigy)
627                 emu->gpr_base = A_FXGPREGBASE;
628         else
629                 emu->gpr_base = FXGPREGBASE;
630 
631         if ((emu->res_port = request_region(emu->port, 0x20, "EMU10K1")) == NULL) {
632                 snd_emu10k1_free(emu);
633                 return -EBUSY;
634         }
635 
636         if (request_irq(pci->irq, snd_emu10k1_interrupt, SA_INTERRUPT|SA_SHIRQ, "EMU10K1", (void *)emu)) {
637                 snd_emu10k1_free(emu);
638                 return -EBUSY;
639         }
640         emu->irq = pci->irq;
641 
642         emu->max_cache_pages = max_cache_bytes >> PAGE_SHIFT;
643         emu->ptb_pages = snd_malloc_pci_pages(pci, 32 * 1024, &emu->ptb_pages_dmaaddr);
644         if (emu->ptb_pages == NULL) {
645                 snd_emu10k1_free(emu);
646                 return -ENOMEM;
647         }
648 
649         emu->page_ptr_table = (void **)vmalloc(emu->max_cache_pages * sizeof(void*));
650         emu->page_addr_table = (unsigned long*)vmalloc(emu->max_cache_pages * sizeof(unsigned long));
651         if (emu->page_ptr_table == NULL || emu->page_addr_table == NULL) {
652                 snd_emu10k1_free(emu);
653                 return -ENOMEM;
654         }
655 
656         emu->silent_page = snd_malloc_pci_pages(pci, EMUPAGESIZE, &emu->silent_page_dmaaddr);
657         if (emu->silent_page == NULL) {
658                 snd_emu10k1_free(emu);
659                 return -ENOMEM;
660         }
661         emu->memhdr = snd_util_memhdr_new(emu->max_cache_pages * PAGE_SIZE);
662         if (emu->memhdr == NULL) {
663                 snd_emu10k1_free(emu);
664                 return -ENOMEM;
665         }
666         emu->memhdr->block_extra_size = sizeof(emu10k1_memblk_t) - sizeof(snd_util_memblk_t);
667 
668         pci_set_master(pci);
669         /* read revision & serial */
670         pci_read_config_byte(pci, PCI_REVISION_ID, (char *)&emu->revision);
671         pci_read_config_dword(pci, PCI_SUBSYSTEM_VENDOR_ID, &emu->serial);
672         pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &emu->model);
673         emu->card_type = EMU10K1_CARD_CREATIVE;
674         if (emu->serial == 0x40011102) {
675                 emu->card_type = EMU10K1_CARD_EMUAPS;
676                 emu->APS = 1;
677                 emu->no_ac97 = 1; /* APS has no AC97 chip */
678         }
679         else if (emu->revision == 4 && emu->serial == 0x10051102) {
680                 /* Audigy 2 EX has apparently no effective AC97 controls
681                  * (for both input and output), so we skip the AC97 detections
682                  */
683                 snd_printdd(KERN_INFO "Audigy2 EX is detected. skpping ac97.\n");
684                 emu->no_ac97 = 1;
685         }
686         
687         emu->fx8010.fxbus_mask = 0x303f;
688         if (extin_mask == 0)
689                 extin_mask = 0x3fcf;
690         if (extout_mask == 0)
691                 extout_mask = 0x1fff;
692         emu->fx8010.extin_mask = extin_mask;
693         emu->fx8010.extout_mask = extout_mask;
694 
695         if (emu->APS) {
696                 if ((err = snd_emu10k1_ecard_init(emu)) < 0) {
697                         snd_emu10k1_free(emu);
698                         return err;
699                 }
700         } else {
701                 /* 5.1: Enable the additional AC97 Slots. If the emu10k1 version
702                         does not support this, it shouldn't do any harm */
703                 snd_emu10k1_ptr_write(emu, AC97SLOT, 0, AC97SLOT_CNTR|AC97SLOT_LFE);
704         }
705 
706         if ((err = snd_emu10k1_init(emu, enable_ir)) < 0) {
707                 snd_emu10k1_free(emu);
708                 return err;
709         }
710 
711         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, emu, &ops)) < 0) {
712                 snd_emu10k1_free(emu);
713                 return err;
714         }
715 
716         snd_emu10k1_proc_init(emu);
717 
718         *remu = emu;
719         return 0;
720 }
721 
722 /* memory.c */
723 EXPORT_SYMBOL(snd_emu10k1_synth_alloc);
724 EXPORT_SYMBOL(snd_emu10k1_synth_free);
725 EXPORT_SYMBOL(snd_emu10k1_synth_bzero);
726 EXPORT_SYMBOL(snd_emu10k1_synth_copy_from_user);
727 EXPORT_SYMBOL(snd_emu10k1_memblk_map);
728 /* voice.c */
729 EXPORT_SYMBOL(snd_emu10k1_voice_alloc);
730 EXPORT_SYMBOL(snd_emu10k1_voice_free);
731 /* io.c */
732 EXPORT_SYMBOL(snd_emu10k1_ptr_read);
733 EXPORT_SYMBOL(snd_emu10k1_ptr_write);
734 

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