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TOMOYO Linux Cross Reference
Linux/sound/pci/ens1370.c

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  1 /*
  2  *  Driver for Ensoniq ES1370/ES1371 AudioPCI soundcard
  3  *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
  4  *                   Thomas Sailer <sailer@ife.ee.ethz.ch>
  5  *
  6  *   This program is free software; you can redistribute it and/or modify
  7  *   it under the terms of the GNU General Public License as published by
  8  *   the Free Software Foundation; either version 2 of the License, or
  9  *   (at your option) any later version.
 10  *
 11  *   This program is distributed in the hope that it will be useful,
 12  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 13  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 14  *   GNU General Public License for more details.
 15  *
 16  *   You should have received a copy of the GNU General Public License
 17  *   along with this program; if not, write to the Free Software
 18  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 19  *
 20  */
 21 
 22 /* Power-Management-Code ( CONFIG_PM )
 23  * for ens1371 only ( FIXME )
 24  * derived from cs4281.c, atiixp.c and via82xx.c
 25  * using http://www.alsa-project.org/~tiwai/writing-an-alsa-driver/ 
 26  * by Kurt J. Bosch
 27  */
 28 
 29 #include <linux/io.h>
 30 #include <linux/delay.h>
 31 #include <linux/interrupt.h>
 32 #include <linux/init.h>
 33 #include <linux/pci.h>
 34 #include <linux/slab.h>
 35 #include <linux/gameport.h>
 36 #include <linux/module.h>
 37 #include <linux/mutex.h>
 38 
 39 #include <sound/core.h>
 40 #include <sound/control.h>
 41 #include <sound/pcm.h>
 42 #include <sound/rawmidi.h>
 43 #ifdef CHIP1371
 44 #include <sound/ac97_codec.h>
 45 #else
 46 #include <sound/ak4531_codec.h>
 47 #endif
 48 #include <sound/initval.h>
 49 #include <sound/asoundef.h>
 50 
 51 #ifndef CHIP1371
 52 #undef CHIP1370
 53 #define CHIP1370
 54 #endif
 55 
 56 #ifdef CHIP1370
 57 #define DRIVER_NAME "ENS1370"
 58 #define CHIP_NAME "ES1370" /* it can be ENS but just to keep compatibility... */
 59 #else
 60 #define DRIVER_NAME "ENS1371"
 61 #define CHIP_NAME "ES1371"
 62 #endif
 63 
 64 
 65 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>, Thomas Sailer <sailer@ife.ee.ethz.ch>");
 66 MODULE_LICENSE("GPL");
 67 #ifdef CHIP1370
 68 MODULE_DESCRIPTION("Ensoniq AudioPCI ES1370");
 69 MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI-97 ES1370},"
 70                 "{Creative Labs,SB PCI64/128 (ES1370)}}");
 71 #endif
 72 #ifdef CHIP1371
 73 MODULE_DESCRIPTION("Ensoniq/Creative AudioPCI ES1371+");
 74 MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI ES1371/73},"
 75                 "{Ensoniq,AudioPCI ES1373},"
 76                 "{Creative Labs,Ectiva EV1938},"
 77                 "{Creative Labs,SB PCI64/128 (ES1371/73)},"
 78                 "{Creative Labs,Vibra PCI128},"
 79                 "{Ectiva,EV1938}}");
 80 #endif
 81 
 82 #if IS_REACHABLE(CONFIG_GAMEPORT)
 83 #define SUPPORT_JOYSTICK
 84 #endif
 85 
 86 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
 87 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
 88 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;     /* Enable switches */
 89 #ifdef SUPPORT_JOYSTICK
 90 #ifdef CHIP1371
 91 static int joystick_port[SNDRV_CARDS];
 92 #else
 93 static bool joystick[SNDRV_CARDS];
 94 #endif
 95 #endif
 96 #ifdef CHIP1371
 97 static int spdif[SNDRV_CARDS];
 98 static int lineio[SNDRV_CARDS];
 99 #endif
100 
101 module_param_array(index, int, NULL, 0444);
102 MODULE_PARM_DESC(index, "Index value for Ensoniq AudioPCI soundcard.");
103 module_param_array(id, charp, NULL, 0444);
104 MODULE_PARM_DESC(id, "ID string for Ensoniq AudioPCI soundcard.");
105 module_param_array(enable, bool, NULL, 0444);
106 MODULE_PARM_DESC(enable, "Enable Ensoniq AudioPCI soundcard.");
107 #ifdef SUPPORT_JOYSTICK
108 #ifdef CHIP1371
109 module_param_hw_array(joystick_port, int, ioport, NULL, 0444);
110 MODULE_PARM_DESC(joystick_port, "Joystick port address.");
111 #else
112 module_param_array(joystick, bool, NULL, 0444);
113 MODULE_PARM_DESC(joystick, "Enable joystick.");
114 #endif
115 #endif /* SUPPORT_JOYSTICK */
116 #ifdef CHIP1371
117 module_param_array(spdif, int, NULL, 0444);
118 MODULE_PARM_DESC(spdif, "S/PDIF output (-1 = none, 0 = auto, 1 = force).");
119 module_param_array(lineio, int, NULL, 0444);
120 MODULE_PARM_DESC(lineio, "Line In to Rear Out (0 = auto, 1 = force).");
121 #endif
122 
123 /* ES1371 chip ID */
124 /* This is a little confusing because all ES1371 compatible chips have the
125    same DEVICE_ID, the only thing differentiating them is the REV_ID field.
126    This is only significant if you want to enable features on the later parts.
127    Yes, I know it's stupid and why didn't we use the sub IDs?
128 */
129 #define ES1371REV_ES1373_A  0x04
130 #define ES1371REV_ES1373_B  0x06
131 #define ES1371REV_CT5880_A  0x07
132 #define CT5880REV_CT5880_C  0x02
133 #define CT5880REV_CT5880_D  0x03        /* ??? -jk */
134 #define CT5880REV_CT5880_E  0x04        /* mw */
135 #define ES1371REV_ES1371_B  0x09
136 #define EV1938REV_EV1938_A  0x00
137 #define ES1371REV_ES1373_8  0x08
138 
139 /*
140  * Direct registers
141  */
142 
143 #define ES_REG(ensoniq, x) ((ensoniq)->port + ES_REG_##x)
144 
145 #define ES_REG_CONTROL  0x00    /* R/W: Interrupt/Chip select control register */
146 #define   ES_1370_ADC_STOP      (1<<31)         /* disable capture buffer transfers */
147 #define   ES_1370_XCTL1         (1<<30)         /* general purpose output bit */
148 #define   ES_1373_BYPASS_P1     (1<<31)         /* bypass SRC for PB1 */
149 #define   ES_1373_BYPASS_P2     (1<<30)         /* bypass SRC for PB2 */
150 #define   ES_1373_BYPASS_R      (1<<29)         /* bypass SRC for REC */
151 #define   ES_1373_TEST_BIT      (1<<28)         /* should be set to 0 for normal operation */
152 #define   ES_1373_RECEN_B       (1<<27)         /* mix record with playback for I2S/SPDIF out */
153 #define   ES_1373_SPDIF_THRU    (1<<26)         /* 0 = SPDIF thru mode, 1 = SPDIF == dig out */
154 #define   ES_1371_JOY_ASEL(o)   (((o)&0x03)<<24)/* joystick port mapping */
155 #define   ES_1371_JOY_ASELM     (0x03<<24)      /* mask for above */
156 #define   ES_1371_JOY_ASELI(i)  (((i)>>24)&0x03)
157 #define   ES_1371_GPIO_IN(i)    (((i)>>20)&0x0f)/* GPIO in [3:0] pins - R/O */
158 #define   ES_1370_PCLKDIVO(o)   (((o)&0x1fff)<<16)/* clock divide ratio for DAC2 */
159 #define   ES_1370_PCLKDIVM      ((0x1fff)<<16)  /* mask for above */
160 #define   ES_1370_PCLKDIVI(i)   (((i)>>16)&0x1fff)/* clock divide ratio for DAC2 */
161 #define   ES_1371_GPIO_OUT(o)   (((o)&0x0f)<<16)/* GPIO out [3:0] pins - W/R */
162 #define   ES_1371_GPIO_OUTM     (0x0f<<16)      /* mask for above */
163 #define   ES_MSFMTSEL           (1<<15)         /* MPEG serial data format; 0 = SONY, 1 = I2S */
164 #define   ES_1370_M_SBB         (1<<14)         /* clock source for DAC - 0 = clock generator; 1 = MPEG clocks */
165 #define   ES_1371_SYNC_RES      (1<<14)         /* Warm AC97 reset */
166 #define   ES_1370_WTSRSEL(o)    (((o)&0x03)<<12)/* fixed frequency clock for DAC1 */
167 #define   ES_1370_WTSRSELM      (0x03<<12)      /* mask for above */
168 #define   ES_1371_ADC_STOP      (1<<13)         /* disable CCB transfer capture information */
169 #define   ES_1371_PWR_INTRM     (1<<12)         /* power level change interrupts enable */
170 #define   ES_1370_DAC_SYNC      (1<<11)         /* DAC's are synchronous */
171 #define   ES_1371_M_CB          (1<<11)         /* capture clock source; 0 = AC'97 ADC; 1 = I2S */
172 #define   ES_CCB_INTRM          (1<<10)         /* CCB voice interrupts enable */
173 #define   ES_1370_M_CB          (1<<9)          /* capture clock source; 0 = ADC; 1 = MPEG */
174 #define   ES_1370_XCTL0         (1<<8)          /* generap purpose output bit */
175 #define   ES_1371_PDLEV(o)      (((o)&0x03)<<8) /* current power down level */
176 #define   ES_1371_PDLEVM        (0x03<<8)       /* mask for above */
177 #define   ES_BREQ               (1<<7)          /* memory bus request enable */
178 #define   ES_DAC1_EN            (1<<6)          /* DAC1 playback channel enable */
179 #define   ES_DAC2_EN            (1<<5)          /* DAC2 playback channel enable */
180 #define   ES_ADC_EN             (1<<4)          /* ADC capture channel enable */
181 #define   ES_UART_EN            (1<<3)          /* UART enable */
182 #define   ES_JYSTK_EN           (1<<2)          /* Joystick module enable */
183 #define   ES_1370_CDC_EN        (1<<1)          /* Codec interface enable */
184 #define   ES_1371_XTALCKDIS     (1<<1)          /* Xtal clock disable */
185 #define   ES_1370_SERR_DISABLE  (1<<0)          /* PCI serr signal disable */
186 #define   ES_1371_PCICLKDIS     (1<<0)          /* PCI clock disable */
187 #define ES_REG_STATUS   0x04    /* R/O: Interrupt/Chip select status register */
188 #define   ES_INTR               (1<<31)         /* Interrupt is pending */
189 #define   ES_1371_ST_AC97_RST   (1<<29)         /* CT5880 AC'97 Reset bit */
190 #define   ES_1373_REAR_BIT27    (1<<27)         /* rear bits: 000 - front, 010 - mirror, 101 - separate */
191 #define   ES_1373_REAR_BIT26    (1<<26)
192 #define   ES_1373_REAR_BIT24    (1<<24)
193 #define   ES_1373_GPIO_INT_EN(o)(((o)&0x0f)<<20)/* GPIO [3:0] pins - interrupt enable */
194 #define   ES_1373_SPDIF_EN      (1<<18)         /* SPDIF enable */
195 #define   ES_1373_SPDIF_TEST    (1<<17)         /* SPDIF test */
196 #define   ES_1371_TEST          (1<<16)         /* test ASIC */
197 #define   ES_1373_GPIO_INT(i)   (((i)&0x0f)>>12)/* GPIO [3:0] pins - interrupt pending */
198 #define   ES_1370_CSTAT         (1<<10)         /* CODEC is busy or register write in progress */
199 #define   ES_1370_CBUSY         (1<<9)          /* CODEC is busy */
200 #define   ES_1370_CWRIP         (1<<8)          /* CODEC register write in progress */
201 #define   ES_1371_SYNC_ERR      (1<<8)          /* CODEC synchronization error occurred */
202 #define   ES_1371_VC(i)         (((i)>>6)&0x03) /* voice code from CCB module */
203 #define   ES_1370_VC(i)         (((i)>>5)&0x03) /* voice code from CCB module */
204 #define   ES_1371_MPWR          (1<<5)          /* power level interrupt pending */
205 #define   ES_MCCB               (1<<4)          /* CCB interrupt pending */
206 #define   ES_UART               (1<<3)          /* UART interrupt pending */
207 #define   ES_DAC1               (1<<2)          /* DAC1 channel interrupt pending */
208 #define   ES_DAC2               (1<<1)          /* DAC2 channel interrupt pending */
209 #define   ES_ADC                (1<<0)          /* ADC channel interrupt pending */
210 #define ES_REG_UART_DATA 0x08   /* R/W: UART data register */
211 #define ES_REG_UART_STATUS 0x09 /* R/O: UART status register */
212 #define   ES_RXINT              (1<<7)          /* RX interrupt occurred */
213 #define   ES_TXINT              (1<<2)          /* TX interrupt occurred */
214 #define   ES_TXRDY              (1<<1)          /* transmitter ready */
215 #define   ES_RXRDY              (1<<0)          /* receiver ready */
216 #define ES_REG_UART_CONTROL 0x09        /* W/O: UART control register */
217 #define   ES_RXINTEN            (1<<7)          /* RX interrupt enable */
218 #define   ES_TXINTENO(o)        (((o)&0x03)<<5) /* TX interrupt enable */
219 #define   ES_TXINTENM           (0x03<<5)       /* mask for above */
220 #define   ES_TXINTENI(i)        (((i)>>5)&0x03)
221 #define   ES_CNTRL(o)           (((o)&0x03)<<0) /* control */
222 #define   ES_CNTRLM             (0x03<<0)       /* mask for above */
223 #define ES_REG_UART_RES 0x0a    /* R/W: UART reserver register */
224 #define   ES_TEST_MODE          (1<<0)          /* test mode enabled */
225 #define ES_REG_MEM_PAGE 0x0c    /* R/W: Memory page register */
226 #define   ES_MEM_PAGEO(o)       (((o)&0x0f)<<0) /* memory page select - out */
227 #define   ES_MEM_PAGEM          (0x0f<<0)       /* mask for above */
228 #define   ES_MEM_PAGEI(i)       (((i)>>0)&0x0f) /* memory page select - in */
229 #define ES_REG_1370_CODEC 0x10  /* W/O: Codec write register address */
230 #define   ES_1370_CODEC_WRITE(a,d) ((((a)&0xff)<<8)|(((d)&0xff)<<0))
231 #define ES_REG_1371_CODEC 0x14  /* W/R: Codec Read/Write register address */
232 #define   ES_1371_CODEC_RDY        (1<<31)      /* codec ready */
233 #define   ES_1371_CODEC_WIP        (1<<30)      /* codec register access in progress */
234 #define   EV_1938_CODEC_MAGIC      (1<<26)
235 #define   ES_1371_CODEC_PIRD       (1<<23)      /* codec read/write select register */
236 #define   ES_1371_CODEC_WRITE(a,d) ((((a)&0x7f)<<16)|(((d)&0xffff)<<0))
237 #define   ES_1371_CODEC_READS(a)   ((((a)&0x7f)<<16)|ES_1371_CODEC_PIRD)
238 #define   ES_1371_CODEC_READ(i)    (((i)>>0)&0xffff)
239 
240 #define ES_REG_1371_SMPRATE 0x10        /* W/R: Codec rate converter interface register */
241 #define   ES_1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25)/* address of the sample rate converter */
242 #define   ES_1371_SRC_RAM_ADDRM    (0x7f<<25)   /* mask for above */
243 #define   ES_1371_SRC_RAM_ADDRI(i) (((i)>>25)&0x7f)/* address of the sample rate converter */
244 #define   ES_1371_SRC_RAM_WE       (1<<24)      /* R/W: read/write control for sample rate converter */
245 #define   ES_1371_SRC_RAM_BUSY     (1<<23)      /* R/O: sample rate memory is busy */
246 #define   ES_1371_SRC_DISABLE      (1<<22)      /* sample rate converter disable */
247 #define   ES_1371_DIS_P1           (1<<21)      /* playback channel 1 accumulator update disable */
248 #define   ES_1371_DIS_P2           (1<<20)      /* playback channel 1 accumulator update disable */
249 #define   ES_1371_DIS_R1           (1<<19)      /* capture channel accumulator update disable */
250 #define   ES_1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0)/* current value of the sample rate converter */
251 #define   ES_1371_SRC_RAM_DATAM    (0xffff<<0)  /* mask for above */
252 #define   ES_1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff)/* current value of the sample rate converter */
253 
254 #define ES_REG_1371_LEGACY 0x18 /* W/R: Legacy control/status register */
255 #define   ES_1371_JFAST         (1<<31)         /* fast joystick timing */
256 #define   ES_1371_HIB           (1<<30)         /* host interrupt blocking enable */
257 #define   ES_1371_VSB           (1<<29)         /* SB; 0 = addr 0x220xH, 1 = 0x22FxH */
258 #define   ES_1371_VMPUO(o)      (((o)&0x03)<<27)/* base register address; 0 = 0x320xH; 1 = 0x330xH; 2 = 0x340xH; 3 = 0x350xH */
259 #define   ES_1371_VMPUM         (0x03<<27)      /* mask for above */
260 #define   ES_1371_VMPUI(i)      (((i)>>27)&0x03)/* base register address */
261 #define   ES_1371_VCDCO(o)      (((o)&0x03)<<25)/* CODEC; 0 = 0x530xH; 1 = undefined; 2 = 0xe80xH; 3 = 0xF40xH */
262 #define   ES_1371_VCDCM         (0x03<<25)      /* mask for above */
263 #define   ES_1371_VCDCI(i)      (((i)>>25)&0x03)/* CODEC address */
264 #define   ES_1371_FIRQ          (1<<24)         /* force an interrupt */
265 #define   ES_1371_SDMACAP       (1<<23)         /* enable event capture for slave DMA controller */
266 #define   ES_1371_SPICAP        (1<<22)         /* enable event capture for slave IRQ controller */
267 #define   ES_1371_MDMACAP       (1<<21)         /* enable event capture for master DMA controller */
268 #define   ES_1371_MPICAP        (1<<20)         /* enable event capture for master IRQ controller */
269 #define   ES_1371_ADCAP         (1<<19)         /* enable event capture for ADLIB register; 0x388xH */
270 #define   ES_1371_SVCAP         (1<<18)         /* enable event capture for SB registers */
271 #define   ES_1371_CDCCAP        (1<<17)         /* enable event capture for CODEC registers */
272 #define   ES_1371_BACAP         (1<<16)         /* enable event capture for SoundScape base address */
273 #define   ES_1371_EXI(i)        (((i)>>8)&0x07) /* event number */
274 #define   ES_1371_AI(i)         (((i)>>3)&0x1f) /* event significant I/O address */
275 #define   ES_1371_WR            (1<<2)  /* event capture; 0 = read; 1 = write */
276 #define   ES_1371_LEGINT        (1<<0)  /* interrupt for legacy events; 0 = interrupt did occur */
277 
278 #define ES_REG_CHANNEL_STATUS 0x1c /* R/W: first 32-bits from S/PDIF channel status block, es1373 */
279 
280 #define ES_REG_SERIAL   0x20    /* R/W: Serial interface control register */
281 #define   ES_1371_DAC_TEST      (1<<22)         /* DAC test mode enable */
282 #define   ES_P2_END_INCO(o)     (((o)&0x07)<<19)/* binary offset value to increment / loop end */
283 #define   ES_P2_END_INCM        (0x07<<19)      /* mask for above */
284 #define   ES_P2_END_INCI(i)     (((i)>>16)&0x07)/* binary offset value to increment / loop end */
285 #define   ES_P2_ST_INCO(o)      (((o)&0x07)<<16)/* binary offset value to increment / start */
286 #define   ES_P2_ST_INCM         (0x07<<16)      /* mask for above */
287 #define   ES_P2_ST_INCI(i)      (((i)<<16)&0x07)/* binary offset value to increment / start */
288 #define   ES_R1_LOOP_SEL        (1<<15)         /* ADC; 0 - loop mode; 1 = stop mode */
289 #define   ES_P2_LOOP_SEL        (1<<14)         /* DAC2; 0 - loop mode; 1 = stop mode */
290 #define   ES_P1_LOOP_SEL        (1<<13)         /* DAC1; 0 - loop mode; 1 = stop mode */
291 #define   ES_P2_PAUSE           (1<<12)         /* DAC2; 0 - play mode; 1 = pause mode */
292 #define   ES_P1_PAUSE           (1<<11)         /* DAC1; 0 - play mode; 1 = pause mode */
293 #define   ES_R1_INT_EN          (1<<10)         /* ADC interrupt enable */
294 #define   ES_P2_INT_EN          (1<<9)          /* DAC2 interrupt enable */
295 #define   ES_P1_INT_EN          (1<<8)          /* DAC1 interrupt enable */
296 #define   ES_P1_SCT_RLD         (1<<7)          /* force sample counter reload for DAC1 */
297 #define   ES_P2_DAC_SEN         (1<<6)          /* when stop mode: 0 - DAC2 play back zeros; 1 = DAC2 play back last sample */
298 #define   ES_R1_MODEO(o)        (((o)&0x03)<<4) /* ADC mode; 0 = 8-bit mono; 1 = 8-bit stereo; 2 = 16-bit mono; 3 = 16-bit stereo */
299 #define   ES_R1_MODEM           (0x03<<4)       /* mask for above */
300 #define   ES_R1_MODEI(i)        (((i)>>4)&0x03)
301 #define   ES_P2_MODEO(o)        (((o)&0x03)<<2) /* DAC2 mode; -- '' -- */
302 #define   ES_P2_MODEM           (0x03<<2)       /* mask for above */
303 #define   ES_P2_MODEI(i)        (((i)>>2)&0x03)
304 #define   ES_P1_MODEO(o)        (((o)&0x03)<<0) /* DAC1 mode; -- '' -- */
305 #define   ES_P1_MODEM           (0x03<<0)       /* mask for above */
306 #define   ES_P1_MODEI(i)        (((i)>>0)&0x03)
307 
308 #define ES_REG_DAC1_COUNT 0x24  /* R/W: DAC1 sample count register */
309 #define ES_REG_DAC2_COUNT 0x28  /* R/W: DAC2 sample count register */
310 #define ES_REG_ADC_COUNT  0x2c  /* R/W: ADC sample count register */
311 #define   ES_REG_CURR_COUNT(i)  (((i)>>16)&0xffff)
312 #define   ES_REG_COUNTO(o)      (((o)&0xffff)<<0)
313 #define   ES_REG_COUNTM         (0xffff<<0)
314 #define   ES_REG_COUNTI(i)      (((i)>>0)&0xffff)
315 
316 #define ES_REG_DAC1_FRAME 0x30  /* R/W: PAGE 0x0c; DAC1 frame address */
317 #define ES_REG_DAC1_SIZE  0x34  /* R/W: PAGE 0x0c; DAC1 frame size */
318 #define ES_REG_DAC2_FRAME 0x38  /* R/W: PAGE 0x0c; DAC2 frame address */
319 #define ES_REG_DAC2_SIZE  0x3c  /* R/W: PAGE 0x0c; DAC2 frame size */
320 #define ES_REG_ADC_FRAME  0x30  /* R/W: PAGE 0x0d; ADC frame address */
321 #define ES_REG_ADC_SIZE   0x34  /* R/W: PAGE 0x0d; ADC frame size */
322 #define   ES_REG_FCURR_COUNTO(o) (((o)&0xffff)<<16)
323 #define   ES_REG_FCURR_COUNTM    (0xffff<<16)
324 #define   ES_REG_FCURR_COUNTI(i) (((i)>>14)&0x3fffc)
325 #define   ES_REG_FSIZEO(o)       (((o)&0xffff)<<0)
326 #define   ES_REG_FSIZEM          (0xffff<<0)
327 #define   ES_REG_FSIZEI(i)       (((i)>>0)&0xffff)
328 #define ES_REG_PHANTOM_FRAME 0x38 /* R/W: PAGE 0x0d: phantom frame address */
329 #define ES_REG_PHANTOM_COUNT 0x3c /* R/W: PAGE 0x0d: phantom frame count */
330 
331 #define ES_REG_UART_FIFO  0x30  /* R/W: PAGE 0x0e; UART FIFO register */
332 #define   ES_REG_UF_VALID        (1<<8)
333 #define   ES_REG_UF_BYTEO(o)     (((o)&0xff)<<0)
334 #define   ES_REG_UF_BYTEM        (0xff<<0)
335 #define   ES_REG_UF_BYTEI(i)     (((i)>>0)&0xff)
336 
337 
338 /*
339  *  Pages
340  */
341 
342 #define ES_PAGE_DAC     0x0c
343 #define ES_PAGE_ADC     0x0d
344 #define ES_PAGE_UART    0x0e
345 #define ES_PAGE_UART1   0x0f
346 
347 /*
348  *  Sample rate converter addresses
349  */
350 
351 #define ES_SMPREG_DAC1          0x70
352 #define ES_SMPREG_DAC2          0x74
353 #define ES_SMPREG_ADC           0x78
354 #define ES_SMPREG_VOL_ADC       0x6c
355 #define ES_SMPREG_VOL_DAC1      0x7c
356 #define ES_SMPREG_VOL_DAC2      0x7e
357 #define ES_SMPREG_TRUNC_N       0x00
358 #define ES_SMPREG_INT_REGS      0x01
359 #define ES_SMPREG_ACCUM_FRAC    0x02
360 #define ES_SMPREG_VFREQ_FRAC    0x03
361 
362 /*
363  *  Some contants
364  */
365 
366 #define ES_1370_SRCLOCK    1411200
367 #define ES_1370_SRTODIV(x) (ES_1370_SRCLOCK/(x)-2)
368 
369 /*
370  *  Open modes
371  */
372 
373 #define ES_MODE_PLAY1   0x0001
374 #define ES_MODE_PLAY2   0x0002
375 #define ES_MODE_CAPTURE 0x0004
376 
377 #define ES_MODE_OUTPUT  0x0001  /* for MIDI */
378 #define ES_MODE_INPUT   0x0002  /* for MIDI */
379 
380 /*
381 
382  */
383 
384 struct ensoniq {
385         spinlock_t reg_lock;
386         struct mutex src_mutex;
387 
388         int irq;
389 
390         unsigned long playback1size;
391         unsigned long playback2size;
392         unsigned long capture3size;
393 
394         unsigned long port;
395         unsigned int mode;
396         unsigned int uartm;     /* UART mode */
397 
398         unsigned int ctrl;      /* control register */
399         unsigned int sctrl;     /* serial control register */
400         unsigned int cssr;      /* control status register */
401         unsigned int uartc;     /* uart control register */
402         unsigned int rev;       /* chip revision */
403 
404         union {
405 #ifdef CHIP1371
406                 struct {
407                         struct snd_ac97 *ac97;
408                 } es1371;
409 #else
410                 struct {
411                         int pclkdiv_lock;
412                         struct snd_ak4531 *ak4531;
413                 } es1370;
414 #endif
415         } u;
416 
417         struct pci_dev *pci;
418         struct snd_card *card;
419         struct snd_pcm *pcm1;   /* DAC1/ADC PCM */
420         struct snd_pcm *pcm2;   /* DAC2 PCM */
421         struct snd_pcm_substream *playback1_substream;
422         struct snd_pcm_substream *playback2_substream;
423         struct snd_pcm_substream *capture_substream;
424         unsigned int p1_dma_size;
425         unsigned int p2_dma_size;
426         unsigned int c_dma_size;
427         unsigned int p1_period_size;
428         unsigned int p2_period_size;
429         unsigned int c_period_size;
430         struct snd_rawmidi *rmidi;
431         struct snd_rawmidi_substream *midi_input;
432         struct snd_rawmidi_substream *midi_output;
433 
434         unsigned int spdif;
435         unsigned int spdif_default;
436         unsigned int spdif_stream;
437 
438 #ifdef CHIP1370
439         struct snd_dma_buffer dma_bug;
440 #endif
441 
442 #ifdef SUPPORT_JOYSTICK
443         struct gameport *gameport;
444 #endif
445 };
446 
447 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id);
448 
449 static const struct pci_device_id snd_audiopci_ids[] = {
450 #ifdef CHIP1370
451         { PCI_VDEVICE(ENSONIQ, 0x5000), 0, },   /* ES1370 */
452 #endif
453 #ifdef CHIP1371
454         { PCI_VDEVICE(ENSONIQ, 0x1371), 0, },   /* ES1371 */
455         { PCI_VDEVICE(ENSONIQ, 0x5880), 0, },   /* ES1373 - CT5880 */
456         { PCI_VDEVICE(ECTIVA, 0x8938), 0, },    /* Ectiva EV1938 */
457 #endif
458         { 0, }
459 };
460 
461 MODULE_DEVICE_TABLE(pci, snd_audiopci_ids);
462 
463 /*
464  *  constants
465  */
466 
467 #define POLL_COUNT      0xa000
468 
469 #ifdef CHIP1370
470 static const unsigned int snd_es1370_fixed_rates[] =
471         {5512, 11025, 22050, 44100};
472 static const struct snd_pcm_hw_constraint_list snd_es1370_hw_constraints_rates = {
473         .count = 4, 
474         .list = snd_es1370_fixed_rates,
475         .mask = 0,
476 };
477 static const struct snd_ratnum es1370_clock = {
478         .num = ES_1370_SRCLOCK,
479         .den_min = 29, 
480         .den_max = 353,
481         .den_step = 1,
482 };
483 static const struct snd_pcm_hw_constraint_ratnums snd_es1370_hw_constraints_clock = {
484         .nrats = 1,
485         .rats = &es1370_clock,
486 };
487 #else
488 static const struct snd_ratden es1371_dac_clock = {
489         .num_min = 3000 * (1 << 15),
490         .num_max = 48000 * (1 << 15),
491         .num_step = 3000,
492         .den = 1 << 15,
493 };
494 static const struct snd_pcm_hw_constraint_ratdens snd_es1371_hw_constraints_dac_clock = {
495         .nrats = 1,
496         .rats = &es1371_dac_clock,
497 };
498 static const struct snd_ratnum es1371_adc_clock = {
499         .num = 48000 << 15,
500         .den_min = 32768, 
501         .den_max = 393216,
502         .den_step = 1,
503 };
504 static const struct snd_pcm_hw_constraint_ratnums snd_es1371_hw_constraints_adc_clock = {
505         .nrats = 1,
506         .rats = &es1371_adc_clock,
507 };
508 #endif
509 static const unsigned int snd_ensoniq_sample_shift[] =
510         {0, 1, 1, 2};
511 
512 /*
513  *  common I/O routines
514  */
515 
516 #ifdef CHIP1371
517 
518 static unsigned int snd_es1371_wait_src_ready(struct ensoniq * ensoniq)
519 {
520         unsigned int t, r = 0;
521 
522         for (t = 0; t < POLL_COUNT; t++) {
523                 r = inl(ES_REG(ensoniq, 1371_SMPRATE));
524                 if ((r & ES_1371_SRC_RAM_BUSY) == 0)
525                         return r;
526                 cond_resched();
527         }
528         dev_err(ensoniq->card->dev, "wait src ready timeout 0x%lx [0x%x]\n",
529                    ES_REG(ensoniq, 1371_SMPRATE), r);
530         return 0;
531 }
532 
533 static unsigned int snd_es1371_src_read(struct ensoniq * ensoniq, unsigned short reg)
534 {
535         unsigned int temp, i, orig, r;
536 
537         /* wait for ready */
538         temp = orig = snd_es1371_wait_src_ready(ensoniq);
539 
540         /* expose the SRC state bits */
541         r = temp & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
542                     ES_1371_DIS_P2 | ES_1371_DIS_R1);
543         r |= ES_1371_SRC_RAM_ADDRO(reg) | 0x10000;
544         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
545 
546         /* now, wait for busy and the correct time to read */
547         temp = snd_es1371_wait_src_ready(ensoniq);
548         
549         if ((temp & 0x00870000) != 0x00010000) {
550                 /* wait for the right state */
551                 for (i = 0; i < POLL_COUNT; i++) {
552                         temp = inl(ES_REG(ensoniq, 1371_SMPRATE));
553                         if ((temp & 0x00870000) == 0x00010000)
554                                 break;
555                 }
556         }
557 
558         /* hide the state bits */       
559         r = orig & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
560                    ES_1371_DIS_P2 | ES_1371_DIS_R1);
561         r |= ES_1371_SRC_RAM_ADDRO(reg);
562         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
563         
564         return temp;
565 }
566 
567 static void snd_es1371_src_write(struct ensoniq * ensoniq,
568                                  unsigned short reg, unsigned short data)
569 {
570         unsigned int r;
571 
572         r = snd_es1371_wait_src_ready(ensoniq) &
573             (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
574              ES_1371_DIS_P2 | ES_1371_DIS_R1);
575         r |= ES_1371_SRC_RAM_ADDRO(reg) | ES_1371_SRC_RAM_DATAO(data);
576         outl(r | ES_1371_SRC_RAM_WE, ES_REG(ensoniq, 1371_SMPRATE));
577 }
578 
579 #endif /* CHIP1371 */
580 
581 #ifdef CHIP1370
582 
583 static void snd_es1370_codec_write(struct snd_ak4531 *ak4531,
584                                    unsigned short reg, unsigned short val)
585 {
586         struct ensoniq *ensoniq = ak4531->private_data;
587         unsigned long end_time = jiffies + HZ / 10;
588 
589 #if 0
590         dev_dbg(ensoniq->card->dev,
591                "CODEC WRITE: reg = 0x%x, val = 0x%x (0x%x), creg = 0x%x\n",
592                reg, val, ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
593 #endif
594         do {
595                 if (!(inl(ES_REG(ensoniq, STATUS)) & ES_1370_CSTAT)) {
596                         outw(ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
597                         return;
598                 }
599                 schedule_timeout_uninterruptible(1);
600         } while (time_after(end_time, jiffies));
601         dev_err(ensoniq->card->dev, "codec write timeout, status = 0x%x\n",
602                    inl(ES_REG(ensoniq, STATUS)));
603 }
604 
605 #endif /* CHIP1370 */
606 
607 #ifdef CHIP1371
608 
609 static inline bool is_ev1938(struct ensoniq *ensoniq)
610 {
611         return ensoniq->pci->device == 0x8938;
612 }
613 
614 static void snd_es1371_codec_write(struct snd_ac97 *ac97,
615                                    unsigned short reg, unsigned short val)
616 {
617         struct ensoniq *ensoniq = ac97->private_data;
618         unsigned int t, x, flag;
619 
620         flag = is_ev1938(ensoniq) ? EV_1938_CODEC_MAGIC : 0;
621         mutex_lock(&ensoniq->src_mutex);
622         for (t = 0; t < POLL_COUNT; t++) {
623                 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
624                         /* save the current state for latter */
625                         x = snd_es1371_wait_src_ready(ensoniq);
626                         outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
627                                    ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
628                              ES_REG(ensoniq, 1371_SMPRATE));
629                         /* wait for not busy (state 0) first to avoid
630                            transition states */
631                         for (t = 0; t < POLL_COUNT; t++) {
632                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
633                                     0x00000000)
634                                         break;
635                         }
636                         /* wait for a SAFE time to write addr/data and then do it, dammit */
637                         for (t = 0; t < POLL_COUNT; t++) {
638                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
639                                     0x00010000)
640                                         break;
641                         }
642                         outl(ES_1371_CODEC_WRITE(reg, val) | flag,
643                              ES_REG(ensoniq, 1371_CODEC));
644                         /* restore SRC reg */
645                         snd_es1371_wait_src_ready(ensoniq);
646                         outl(x, ES_REG(ensoniq, 1371_SMPRATE));
647                         mutex_unlock(&ensoniq->src_mutex);
648                         return;
649                 }
650         }
651         mutex_unlock(&ensoniq->src_mutex);
652         dev_err(ensoniq->card->dev, "codec write timeout at 0x%lx [0x%x]\n",
653                    ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
654 }
655 
656 static unsigned short snd_es1371_codec_read(struct snd_ac97 *ac97,
657                                             unsigned short reg)
658 {
659         struct ensoniq *ensoniq = ac97->private_data;
660         unsigned int t, x, flag, fail = 0;
661 
662         flag = is_ev1938(ensoniq) ? EV_1938_CODEC_MAGIC : 0;
663       __again:
664         mutex_lock(&ensoniq->src_mutex);
665         for (t = 0; t < POLL_COUNT; t++) {
666                 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
667                         /* save the current state for latter */
668                         x = snd_es1371_wait_src_ready(ensoniq);
669                         outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
670                                    ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
671                              ES_REG(ensoniq, 1371_SMPRATE));
672                         /* wait for not busy (state 0) first to avoid
673                            transition states */
674                         for (t = 0; t < POLL_COUNT; t++) {
675                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
676                                     0x00000000)
677                                         break;
678                         }
679                         /* wait for a SAFE time to write addr/data and then do it, dammit */
680                         for (t = 0; t < POLL_COUNT; t++) {
681                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
682                                     0x00010000)
683                                         break;
684                         }
685                         outl(ES_1371_CODEC_READS(reg) | flag,
686                              ES_REG(ensoniq, 1371_CODEC));
687                         /* restore SRC reg */
688                         snd_es1371_wait_src_ready(ensoniq);
689                         outl(x, ES_REG(ensoniq, 1371_SMPRATE));
690                         /* wait for WIP again */
691                         for (t = 0; t < POLL_COUNT; t++) {
692                                 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP))
693                                         break;          
694                         }
695                         /* now wait for the stinkin' data (RDY) */
696                         for (t = 0; t < POLL_COUNT; t++) {
697                                 if ((x = inl(ES_REG(ensoniq, 1371_CODEC))) & ES_1371_CODEC_RDY) {
698                                         if (is_ev1938(ensoniq)) {
699                                                 for (t = 0; t < 100; t++)
700                                                         inl(ES_REG(ensoniq, CONTROL));
701                                                 x = inl(ES_REG(ensoniq, 1371_CODEC));
702                                         }
703                                         mutex_unlock(&ensoniq->src_mutex);
704                                         return ES_1371_CODEC_READ(x);
705                                 }
706                         }
707                         mutex_unlock(&ensoniq->src_mutex);
708                         if (++fail > 10) {
709                                 dev_err(ensoniq->card->dev,
710                                         "codec read timeout (final) at 0x%lx, reg = 0x%x [0x%x]\n",
711                                            ES_REG(ensoniq, 1371_CODEC), reg,
712                                            inl(ES_REG(ensoniq, 1371_CODEC)));
713                                 return 0;
714                         }
715                         goto __again;
716                 }
717         }
718         mutex_unlock(&ensoniq->src_mutex);
719         dev_err(ensoniq->card->dev, "codec read timeout at 0x%lx [0x%x]\n",
720                    ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
721         return 0;
722 }
723 
724 static void snd_es1371_codec_wait(struct snd_ac97 *ac97)
725 {
726         msleep(750);
727         snd_es1371_codec_read(ac97, AC97_RESET);
728         snd_es1371_codec_read(ac97, AC97_VENDOR_ID1);
729         snd_es1371_codec_read(ac97, AC97_VENDOR_ID2);
730         msleep(50);
731 }
732 
733 static void snd_es1371_adc_rate(struct ensoniq * ensoniq, unsigned int rate)
734 {
735         unsigned int n, truncm, freq;
736 
737         mutex_lock(&ensoniq->src_mutex);
738         n = rate / 3000;
739         if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9)))
740                 n--;
741         truncm = (21 * n - 1) | 1;
742         freq = ((48000UL << 15) / rate) * n;
743         if (rate >= 24000) {
744                 if (truncm > 239)
745                         truncm = 239;
746                 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
747                                 (((239 - truncm) >> 1) << 9) | (n << 4));
748         } else {
749                 if (truncm > 119)
750                         truncm = 119;
751                 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
752                                 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4));
753         }
754         snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS,
755                              (snd_es1371_src_read(ensoniq, ES_SMPREG_ADC +
756                                                   ES_SMPREG_INT_REGS) & 0x00ff) |
757                              ((freq >> 5) & 0xfc00));
758         snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
759         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, n << 8);
760         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, n << 8);
761         mutex_unlock(&ensoniq->src_mutex);
762 }
763 
764 static void snd_es1371_dac1_rate(struct ensoniq * ensoniq, unsigned int rate)
765 {
766         unsigned int freq, r;
767 
768         mutex_lock(&ensoniq->src_mutex);
769         freq = ((rate << 15) + 1500) / 3000;
770         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
771                                                    ES_1371_DIS_P2 | ES_1371_DIS_R1)) |
772                 ES_1371_DIS_P1;
773         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
774         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS,
775                              (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC1 +
776                                                   ES_SMPREG_INT_REGS) & 0x00ff) |
777                              ((freq >> 5) & 0xfc00));
778         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
779         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
780                                                    ES_1371_DIS_P2 | ES_1371_DIS_R1));
781         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
782         mutex_unlock(&ensoniq->src_mutex);
783 }
784 
785 static void snd_es1371_dac2_rate(struct ensoniq * ensoniq, unsigned int rate)
786 {
787         unsigned int freq, r;
788 
789         mutex_lock(&ensoniq->src_mutex);
790         freq = ((rate << 15) + 1500) / 3000;
791         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
792                                                    ES_1371_DIS_P1 | ES_1371_DIS_R1)) |
793                 ES_1371_DIS_P2;
794         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
795         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS,
796                              (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC2 +
797                                                   ES_SMPREG_INT_REGS) & 0x00ff) |
798                              ((freq >> 5) & 0xfc00));
799         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_VFREQ_FRAC,
800                              freq & 0x7fff);
801         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
802                                                    ES_1371_DIS_P1 | ES_1371_DIS_R1));
803         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
804         mutex_unlock(&ensoniq->src_mutex);
805 }
806 
807 #endif /* CHIP1371 */
808 
809 static int snd_ensoniq_trigger(struct snd_pcm_substream *substream, int cmd)
810 {
811         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
812         switch (cmd) {
813         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
814         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
815         {
816                 unsigned int what = 0;
817                 struct snd_pcm_substream *s;
818                 snd_pcm_group_for_each_entry(s, substream) {
819                         if (s == ensoniq->playback1_substream) {
820                                 what |= ES_P1_PAUSE;
821                                 snd_pcm_trigger_done(s, substream);
822                         } else if (s == ensoniq->playback2_substream) {
823                                 what |= ES_P2_PAUSE;
824                                 snd_pcm_trigger_done(s, substream);
825                         } else if (s == ensoniq->capture_substream)
826                                 return -EINVAL;
827                 }
828                 spin_lock(&ensoniq->reg_lock);
829                 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
830                         ensoniq->sctrl |= what;
831                 else
832                         ensoniq->sctrl &= ~what;
833                 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
834                 spin_unlock(&ensoniq->reg_lock);
835                 break;
836         }
837         case SNDRV_PCM_TRIGGER_START:
838         case SNDRV_PCM_TRIGGER_STOP:
839         {
840                 unsigned int what = 0;
841                 struct snd_pcm_substream *s;
842                 snd_pcm_group_for_each_entry(s, substream) {
843                         if (s == ensoniq->playback1_substream) {
844                                 what |= ES_DAC1_EN;
845                                 snd_pcm_trigger_done(s, substream);
846                         } else if (s == ensoniq->playback2_substream) {
847                                 what |= ES_DAC2_EN;
848                                 snd_pcm_trigger_done(s, substream);
849                         } else if (s == ensoniq->capture_substream) {
850                                 what |= ES_ADC_EN;
851                                 snd_pcm_trigger_done(s, substream);
852                         }
853                 }
854                 spin_lock(&ensoniq->reg_lock);
855                 if (cmd == SNDRV_PCM_TRIGGER_START)
856                         ensoniq->ctrl |= what;
857                 else
858                         ensoniq->ctrl &= ~what;
859                 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
860                 spin_unlock(&ensoniq->reg_lock);
861                 break;
862         }
863         default:
864                 return -EINVAL;
865         }
866         return 0;
867 }
868 
869 /*
870  *  PCM part
871  */
872 
873 static int snd_ensoniq_hw_params(struct snd_pcm_substream *substream,
874                                  struct snd_pcm_hw_params *hw_params)
875 {
876         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
877 }
878 
879 static int snd_ensoniq_hw_free(struct snd_pcm_substream *substream)
880 {
881         return snd_pcm_lib_free_pages(substream);
882 }
883 
884 static int snd_ensoniq_playback1_prepare(struct snd_pcm_substream *substream)
885 {
886         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
887         struct snd_pcm_runtime *runtime = substream->runtime;
888         unsigned int mode = 0;
889 
890         ensoniq->p1_dma_size = snd_pcm_lib_buffer_bytes(substream);
891         ensoniq->p1_period_size = snd_pcm_lib_period_bytes(substream);
892         if (snd_pcm_format_width(runtime->format) == 16)
893                 mode |= 0x02;
894         if (runtime->channels > 1)
895                 mode |= 0x01;
896         spin_lock_irq(&ensoniq->reg_lock);
897         ensoniq->ctrl &= ~ES_DAC1_EN;
898 #ifdef CHIP1371
899         /* 48k doesn't need SRC (it breaks AC3-passthru) */
900         if (runtime->rate == 48000)
901                 ensoniq->ctrl |= ES_1373_BYPASS_P1;
902         else
903                 ensoniq->ctrl &= ~ES_1373_BYPASS_P1;
904 #endif
905         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
906         outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
907         outl(runtime->dma_addr, ES_REG(ensoniq, DAC1_FRAME));
908         outl((ensoniq->p1_dma_size >> 2) - 1, ES_REG(ensoniq, DAC1_SIZE));
909         ensoniq->sctrl &= ~(ES_P1_LOOP_SEL | ES_P1_PAUSE | ES_P1_SCT_RLD | ES_P1_MODEM);
910         ensoniq->sctrl |= ES_P1_INT_EN | ES_P1_MODEO(mode);
911         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
912         outl((ensoniq->p1_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
913              ES_REG(ensoniq, DAC1_COUNT));
914 #ifdef CHIP1370
915         ensoniq->ctrl &= ~ES_1370_WTSRSELM;
916         switch (runtime->rate) {
917         case 5512: ensoniq->ctrl |= ES_1370_WTSRSEL(0); break;
918         case 11025: ensoniq->ctrl |= ES_1370_WTSRSEL(1); break;
919         case 22050: ensoniq->ctrl |= ES_1370_WTSRSEL(2); break;
920         case 44100: ensoniq->ctrl |= ES_1370_WTSRSEL(3); break;
921         default: snd_BUG();
922         }
923 #endif
924         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
925         spin_unlock_irq(&ensoniq->reg_lock);
926 #ifndef CHIP1370
927         snd_es1371_dac1_rate(ensoniq, runtime->rate);
928 #endif
929         return 0;
930 }
931 
932 static int snd_ensoniq_playback2_prepare(struct snd_pcm_substream *substream)
933 {
934         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
935         struct snd_pcm_runtime *runtime = substream->runtime;
936         unsigned int mode = 0;
937 
938         ensoniq->p2_dma_size = snd_pcm_lib_buffer_bytes(substream);
939         ensoniq->p2_period_size = snd_pcm_lib_period_bytes(substream);
940         if (snd_pcm_format_width(runtime->format) == 16)
941                 mode |= 0x02;
942         if (runtime->channels > 1)
943                 mode |= 0x01;
944         spin_lock_irq(&ensoniq->reg_lock);
945         ensoniq->ctrl &= ~ES_DAC2_EN;
946         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
947         outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
948         outl(runtime->dma_addr, ES_REG(ensoniq, DAC2_FRAME));
949         outl((ensoniq->p2_dma_size >> 2) - 1, ES_REG(ensoniq, DAC2_SIZE));
950         ensoniq->sctrl &= ~(ES_P2_LOOP_SEL | ES_P2_PAUSE | ES_P2_DAC_SEN |
951                             ES_P2_END_INCM | ES_P2_ST_INCM | ES_P2_MODEM);
952         ensoniq->sctrl |= ES_P2_INT_EN | ES_P2_MODEO(mode) |
953                           ES_P2_END_INCO(mode & 2 ? 2 : 1) | ES_P2_ST_INCO(0);
954         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
955         outl((ensoniq->p2_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
956              ES_REG(ensoniq, DAC2_COUNT));
957 #ifdef CHIP1370
958         if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_CAPTURE)) {
959                 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
960                 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
961                 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_PLAY2;
962         }
963 #endif
964         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
965         spin_unlock_irq(&ensoniq->reg_lock);
966 #ifndef CHIP1370
967         snd_es1371_dac2_rate(ensoniq, runtime->rate);
968 #endif
969         return 0;
970 }
971 
972 static int snd_ensoniq_capture_prepare(struct snd_pcm_substream *substream)
973 {
974         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
975         struct snd_pcm_runtime *runtime = substream->runtime;
976         unsigned int mode = 0;
977 
978         ensoniq->c_dma_size = snd_pcm_lib_buffer_bytes(substream);
979         ensoniq->c_period_size = snd_pcm_lib_period_bytes(substream);
980         if (snd_pcm_format_width(runtime->format) == 16)
981                 mode |= 0x02;
982         if (runtime->channels > 1)
983                 mode |= 0x01;
984         spin_lock_irq(&ensoniq->reg_lock);
985         ensoniq->ctrl &= ~ES_ADC_EN;
986         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
987         outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
988         outl(runtime->dma_addr, ES_REG(ensoniq, ADC_FRAME));
989         outl((ensoniq->c_dma_size >> 2) - 1, ES_REG(ensoniq, ADC_SIZE));
990         ensoniq->sctrl &= ~(ES_R1_LOOP_SEL | ES_R1_MODEM);
991         ensoniq->sctrl |= ES_R1_INT_EN | ES_R1_MODEO(mode);
992         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
993         outl((ensoniq->c_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
994              ES_REG(ensoniq, ADC_COUNT));
995 #ifdef CHIP1370
996         if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_PLAY2)) {
997                 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
998                 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
999                 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_CAPTURE;
1000         }
1001 #endif
1002         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1003         spin_unlock_irq(&ensoniq->reg_lock);
1004 #ifndef CHIP1370
1005         snd_es1371_adc_rate(ensoniq, runtime->rate);
1006 #endif
1007         return 0;
1008 }
1009 
1010 static snd_pcm_uframes_t snd_ensoniq_playback1_pointer(struct snd_pcm_substream *substream)
1011 {
1012         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1013         size_t ptr;
1014 
1015         spin_lock(&ensoniq->reg_lock);
1016         if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC1_EN) {
1017                 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
1018                 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC1_SIZE)));
1019                 ptr = bytes_to_frames(substream->runtime, ptr);
1020         } else {
1021                 ptr = 0;
1022         }
1023         spin_unlock(&ensoniq->reg_lock);
1024         return ptr;
1025 }
1026 
1027 static snd_pcm_uframes_t snd_ensoniq_playback2_pointer(struct snd_pcm_substream *substream)
1028 {
1029         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1030         size_t ptr;
1031 
1032         spin_lock(&ensoniq->reg_lock);
1033         if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC2_EN) {
1034                 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
1035                 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC2_SIZE)));
1036                 ptr = bytes_to_frames(substream->runtime, ptr);
1037         } else {
1038                 ptr = 0;
1039         }
1040         spin_unlock(&ensoniq->reg_lock);
1041         return ptr;
1042 }
1043 
1044 static snd_pcm_uframes_t snd_ensoniq_capture_pointer(struct snd_pcm_substream *substream)
1045 {
1046         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1047         size_t ptr;
1048 
1049         spin_lock(&ensoniq->reg_lock);
1050         if (inl(ES_REG(ensoniq, CONTROL)) & ES_ADC_EN) {
1051                 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1052                 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, ADC_SIZE)));
1053                 ptr = bytes_to_frames(substream->runtime, ptr);
1054         } else {
1055                 ptr = 0;
1056         }
1057         spin_unlock(&ensoniq->reg_lock);
1058         return ptr;
1059 }
1060 
1061 static const struct snd_pcm_hardware snd_ensoniq_playback1 =
1062 {
1063         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1064                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1065                                  SNDRV_PCM_INFO_MMAP_VALID |
1066                                  SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
1067         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1068         .rates =
1069 #ifndef CHIP1370
1070                                 SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1071 #else
1072                                 (SNDRV_PCM_RATE_KNOT |  /* 5512Hz rate */
1073                                  SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_22050 | 
1074                                  SNDRV_PCM_RATE_44100),
1075 #endif
1076         .rate_min =             4000,
1077         .rate_max =             48000,
1078         .channels_min =         1,
1079         .channels_max =         2,
1080         .buffer_bytes_max =     (128*1024),
1081         .period_bytes_min =     64,
1082         .period_bytes_max =     (128*1024),
1083         .periods_min =          1,
1084         .periods_max =          1024,
1085         .fifo_size =            0,
1086 };
1087 
1088 static const struct snd_pcm_hardware snd_ensoniq_playback2 =
1089 {
1090         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1091                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1092                                  SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_PAUSE | 
1093                                  SNDRV_PCM_INFO_SYNC_START),
1094         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1095         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1096         .rate_min =             4000,
1097         .rate_max =             48000,
1098         .channels_min =         1,
1099         .channels_max =         2,
1100         .buffer_bytes_max =     (128*1024),
1101         .period_bytes_min =     64,
1102         .period_bytes_max =     (128*1024),
1103         .periods_min =          1,
1104         .periods_max =          1024,
1105         .fifo_size =            0,
1106 };
1107 
1108 static const struct snd_pcm_hardware snd_ensoniq_capture =
1109 {
1110         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1111                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1112                                  SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START),
1113         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1114         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1115         .rate_min =             4000,
1116         .rate_max =             48000,
1117         .channels_min =         1,
1118         .channels_max =         2,
1119         .buffer_bytes_max =     (128*1024),
1120         .period_bytes_min =     64,
1121         .period_bytes_max =     (128*1024),
1122         .periods_min =          1,
1123         .periods_max =          1024,
1124         .fifo_size =            0,
1125 };
1126 
1127 static int snd_ensoniq_playback1_open(struct snd_pcm_substream *substream)
1128 {
1129         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1130         struct snd_pcm_runtime *runtime = substream->runtime;
1131 
1132         ensoniq->mode |= ES_MODE_PLAY1;
1133         ensoniq->playback1_substream = substream;
1134         runtime->hw = snd_ensoniq_playback1;
1135         snd_pcm_set_sync(substream);
1136         spin_lock_irq(&ensoniq->reg_lock);
1137         if (ensoniq->spdif && ensoniq->playback2_substream == NULL)
1138                 ensoniq->spdif_stream = ensoniq->spdif_default;
1139         spin_unlock_irq(&ensoniq->reg_lock);
1140 #ifdef CHIP1370
1141         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1142                                    &snd_es1370_hw_constraints_rates);
1143 #else
1144         snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1145                                       &snd_es1371_hw_constraints_dac_clock);
1146 #endif
1147         return 0;
1148 }
1149 
1150 static int snd_ensoniq_playback2_open(struct snd_pcm_substream *substream)
1151 {
1152         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1153         struct snd_pcm_runtime *runtime = substream->runtime;
1154 
1155         ensoniq->mode |= ES_MODE_PLAY2;
1156         ensoniq->playback2_substream = substream;
1157         runtime->hw = snd_ensoniq_playback2;
1158         snd_pcm_set_sync(substream);
1159         spin_lock_irq(&ensoniq->reg_lock);
1160         if (ensoniq->spdif && ensoniq->playback1_substream == NULL)
1161                 ensoniq->spdif_stream = ensoniq->spdif_default;
1162         spin_unlock_irq(&ensoniq->reg_lock);
1163 #ifdef CHIP1370
1164         snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1165                                       &snd_es1370_hw_constraints_clock);
1166 #else
1167         snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1168                                       &snd_es1371_hw_constraints_dac_clock);
1169 #endif
1170         return 0;
1171 }
1172 
1173 static int snd_ensoniq_capture_open(struct snd_pcm_substream *substream)
1174 {
1175         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1176         struct snd_pcm_runtime *runtime = substream->runtime;
1177 
1178         ensoniq->mode |= ES_MODE_CAPTURE;
1179         ensoniq->capture_substream = substream;
1180         runtime->hw = snd_ensoniq_capture;
1181         snd_pcm_set_sync(substream);
1182 #ifdef CHIP1370
1183         snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1184                                       &snd_es1370_hw_constraints_clock);
1185 #else
1186         snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1187                                       &snd_es1371_hw_constraints_adc_clock);
1188 #endif
1189         return 0;
1190 }
1191 
1192 static int snd_ensoniq_playback1_close(struct snd_pcm_substream *substream)
1193 {
1194         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1195 
1196         ensoniq->playback1_substream = NULL;
1197         ensoniq->mode &= ~ES_MODE_PLAY1;
1198         return 0;
1199 }
1200 
1201 static int snd_ensoniq_playback2_close(struct snd_pcm_substream *substream)
1202 {
1203         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1204 
1205         ensoniq->playback2_substream = NULL;
1206         spin_lock_irq(&ensoniq->reg_lock);
1207 #ifdef CHIP1370
1208         ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_PLAY2;
1209 #endif
1210         ensoniq->mode &= ~ES_MODE_PLAY2;
1211         spin_unlock_irq(&ensoniq->reg_lock);
1212         return 0;
1213 }
1214 
1215 static int snd_ensoniq_capture_close(struct snd_pcm_substream *substream)
1216 {
1217         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1218 
1219         ensoniq->capture_substream = NULL;
1220         spin_lock_irq(&ensoniq->reg_lock);
1221 #ifdef CHIP1370
1222         ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_CAPTURE;
1223 #endif
1224         ensoniq->mode &= ~ES_MODE_CAPTURE;
1225         spin_unlock_irq(&ensoniq->reg_lock);
1226         return 0;
1227 }
1228 
1229 static const struct snd_pcm_ops snd_ensoniq_playback1_ops = {
1230         .open =         snd_ensoniq_playback1_open,
1231         .close =        snd_ensoniq_playback1_close,
1232         .ioctl =        snd_pcm_lib_ioctl,
1233         .hw_params =    snd_ensoniq_hw_params,
1234         .hw_free =      snd_ensoniq_hw_free,
1235         .prepare =      snd_ensoniq_playback1_prepare,
1236         .trigger =      snd_ensoniq_trigger,
1237         .pointer =      snd_ensoniq_playback1_pointer,
1238 };
1239 
1240 static const struct snd_pcm_ops snd_ensoniq_playback2_ops = {
1241         .open =         snd_ensoniq_playback2_open,
1242         .close =        snd_ensoniq_playback2_close,
1243         .ioctl =        snd_pcm_lib_ioctl,
1244         .hw_params =    snd_ensoniq_hw_params,
1245         .hw_free =      snd_ensoniq_hw_free,
1246         .prepare =      snd_ensoniq_playback2_prepare,
1247         .trigger =      snd_ensoniq_trigger,
1248         .pointer =      snd_ensoniq_playback2_pointer,
1249 };
1250 
1251 static const struct snd_pcm_ops snd_ensoniq_capture_ops = {
1252         .open =         snd_ensoniq_capture_open,
1253         .close =        snd_ensoniq_capture_close,
1254         .ioctl =        snd_pcm_lib_ioctl,
1255         .hw_params =    snd_ensoniq_hw_params,
1256         .hw_free =      snd_ensoniq_hw_free,
1257         .prepare =      snd_ensoniq_capture_prepare,
1258         .trigger =      snd_ensoniq_trigger,
1259         .pointer =      snd_ensoniq_capture_pointer,
1260 };
1261 
1262 static const struct snd_pcm_chmap_elem surround_map[] = {
1263         { .channels = 1,
1264           .map = { SNDRV_CHMAP_MONO } },
1265         { .channels = 2,
1266           .map = { SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
1267         { }
1268 };
1269 
1270 static int snd_ensoniq_pcm(struct ensoniq *ensoniq, int device)
1271 {
1272         struct snd_pcm *pcm;
1273         int err;
1274 
1275         err = snd_pcm_new(ensoniq->card, CHIP_NAME "/1", device, 1, 1, &pcm);
1276         if (err < 0)
1277                 return err;
1278 
1279 #ifdef CHIP1370
1280         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1281 #else
1282         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1283 #endif
1284         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ensoniq_capture_ops);
1285 
1286         pcm->private_data = ensoniq;
1287         pcm->info_flags = 0;
1288         strcpy(pcm->name, CHIP_NAME " DAC2/ADC");
1289         ensoniq->pcm1 = pcm;
1290 
1291         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1292                                               snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024);
1293 
1294 #ifdef CHIP1370
1295         err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1296                                      surround_map, 2, 0, NULL);
1297 #else
1298         err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1299                                      snd_pcm_std_chmaps, 2, 0, NULL);
1300 #endif
1301         return err;
1302 }
1303 
1304 static int snd_ensoniq_pcm2(struct ensoniq *ensoniq, int device)
1305 {
1306         struct snd_pcm *pcm;
1307         int err;
1308 
1309         err = snd_pcm_new(ensoniq->card, CHIP_NAME "/2", device, 1, 0, &pcm);
1310         if (err < 0)
1311                 return err;
1312 
1313 #ifdef CHIP1370
1314         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1315 #else
1316         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1317 #endif
1318         pcm->private_data = ensoniq;
1319         pcm->info_flags = 0;
1320         strcpy(pcm->name, CHIP_NAME " DAC1");
1321         ensoniq->pcm2 = pcm;
1322 
1323         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1324                                               snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024);
1325 
1326 #ifdef CHIP1370
1327         err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1328                                      snd_pcm_std_chmaps, 2, 0, NULL);
1329 #else
1330         err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1331                                      surround_map, 2, 0, NULL);
1332 #endif
1333         return err;
1334 }
1335 
1336 /*
1337  *  Mixer section
1338  */
1339 
1340 /*
1341  * ENS1371 mixer (including SPDIF interface)
1342  */
1343 #ifdef CHIP1371
1344 static int snd_ens1373_spdif_info(struct snd_kcontrol *kcontrol,
1345                                   struct snd_ctl_elem_info *uinfo)
1346 {
1347         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1348         uinfo->count = 1;
1349         return 0;
1350 }
1351 
1352 static int snd_ens1373_spdif_default_get(struct snd_kcontrol *kcontrol,
1353                                          struct snd_ctl_elem_value *ucontrol)
1354 {
1355         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1356         spin_lock_irq(&ensoniq->reg_lock);
1357         ucontrol->value.iec958.status[0] = (ensoniq->spdif_default >> 0) & 0xff;
1358         ucontrol->value.iec958.status[1] = (ensoniq->spdif_default >> 8) & 0xff;
1359         ucontrol->value.iec958.status[2] = (ensoniq->spdif_default >> 16) & 0xff;
1360         ucontrol->value.iec958.status[3] = (ensoniq->spdif_default >> 24) & 0xff;
1361         spin_unlock_irq(&ensoniq->reg_lock);
1362         return 0;
1363 }
1364 
1365 static int snd_ens1373_spdif_default_put(struct snd_kcontrol *kcontrol,
1366                                          struct snd_ctl_elem_value *ucontrol)
1367 {
1368         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1369         unsigned int val;
1370         int change;
1371 
1372         val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1373               ((u32)ucontrol->value.iec958.status[1] << 8) |
1374               ((u32)ucontrol->value.iec958.status[2] << 16) |
1375               ((u32)ucontrol->value.iec958.status[3] << 24);
1376         spin_lock_irq(&ensoniq->reg_lock);
1377         change = ensoniq->spdif_default != val;
1378         ensoniq->spdif_default = val;
1379         if (change && ensoniq->playback1_substream == NULL &&
1380             ensoniq->playback2_substream == NULL)
1381                 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1382         spin_unlock_irq(&ensoniq->reg_lock);
1383         return change;
1384 }
1385 
1386 static int snd_ens1373_spdif_mask_get(struct snd_kcontrol *kcontrol,
1387                                       struct snd_ctl_elem_value *ucontrol)
1388 {
1389         ucontrol->value.iec958.status[0] = 0xff;
1390         ucontrol->value.iec958.status[1] = 0xff;
1391         ucontrol->value.iec958.status[2] = 0xff;
1392         ucontrol->value.iec958.status[3] = 0xff;
1393         return 0;
1394 }
1395 
1396 static int snd_ens1373_spdif_stream_get(struct snd_kcontrol *kcontrol,
1397                                         struct snd_ctl_elem_value *ucontrol)
1398 {
1399         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1400         spin_lock_irq(&ensoniq->reg_lock);
1401         ucontrol->value.iec958.status[0] = (ensoniq->spdif_stream >> 0) & 0xff;
1402         ucontrol->value.iec958.status[1] = (ensoniq->spdif_stream >> 8) & 0xff;
1403         ucontrol->value.iec958.status[2] = (ensoniq->spdif_stream >> 16) & 0xff;
1404         ucontrol->value.iec958.status[3] = (ensoniq->spdif_stream >> 24) & 0xff;
1405         spin_unlock_irq(&ensoniq->reg_lock);
1406         return 0;
1407 }
1408 
1409 static int snd_ens1373_spdif_stream_put(struct snd_kcontrol *kcontrol,
1410                                         struct snd_ctl_elem_value *ucontrol)
1411 {
1412         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1413         unsigned int val;
1414         int change;
1415 
1416         val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1417               ((u32)ucontrol->value.iec958.status[1] << 8) |
1418               ((u32)ucontrol->value.iec958.status[2] << 16) |
1419               ((u32)ucontrol->value.iec958.status[3] << 24);
1420         spin_lock_irq(&ensoniq->reg_lock);
1421         change = ensoniq->spdif_stream != val;
1422         ensoniq->spdif_stream = val;
1423         if (change && (ensoniq->playback1_substream != NULL ||
1424                        ensoniq->playback2_substream != NULL))
1425                 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1426         spin_unlock_irq(&ensoniq->reg_lock);
1427         return change;
1428 }
1429 
1430 #define ES1371_SPDIF(xname) \
1431 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_es1371_spdif_info, \
1432   .get = snd_es1371_spdif_get, .put = snd_es1371_spdif_put }
1433 
1434 #define snd_es1371_spdif_info           snd_ctl_boolean_mono_info
1435 
1436 static int snd_es1371_spdif_get(struct snd_kcontrol *kcontrol,
1437                                 struct snd_ctl_elem_value *ucontrol)
1438 {
1439         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1440         
1441         spin_lock_irq(&ensoniq->reg_lock);
1442         ucontrol->value.integer.value[0] = ensoniq->ctrl & ES_1373_SPDIF_THRU ? 1 : 0;
1443         spin_unlock_irq(&ensoniq->reg_lock);
1444         return 0;
1445 }
1446 
1447 static int snd_es1371_spdif_put(struct snd_kcontrol *kcontrol,
1448                                 struct snd_ctl_elem_value *ucontrol)
1449 {
1450         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1451         unsigned int nval1, nval2;
1452         int change;
1453         
1454         nval1 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_THRU : 0;
1455         nval2 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_EN : 0;
1456         spin_lock_irq(&ensoniq->reg_lock);
1457         change = (ensoniq->ctrl & ES_1373_SPDIF_THRU) != nval1;
1458         ensoniq->ctrl &= ~ES_1373_SPDIF_THRU;
1459         ensoniq->ctrl |= nval1;
1460         ensoniq->cssr &= ~ES_1373_SPDIF_EN;
1461         ensoniq->cssr |= nval2;
1462         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1463         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1464         spin_unlock_irq(&ensoniq->reg_lock);
1465         return change;
1466 }
1467 
1468 
1469 /* spdif controls */
1470 static struct snd_kcontrol_new snd_es1371_mixer_spdif[] = {
1471         ES1371_SPDIF(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH)),
1472         {
1473                 .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1474                 .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1475                 .info =         snd_ens1373_spdif_info,
1476                 .get =          snd_ens1373_spdif_default_get,
1477                 .put =          snd_ens1373_spdif_default_put,
1478         },
1479         {
1480                 .access =       SNDRV_CTL_ELEM_ACCESS_READ,
1481                 .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1482                 .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
1483                 .info =         snd_ens1373_spdif_info,
1484                 .get =          snd_ens1373_spdif_mask_get
1485         },
1486         {
1487                 .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1488                 .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1489                 .info =         snd_ens1373_spdif_info,
1490                 .get =          snd_ens1373_spdif_stream_get,
1491                 .put =          snd_ens1373_spdif_stream_put
1492         },
1493 };
1494 
1495 
1496 #define snd_es1373_rear_info            snd_ctl_boolean_mono_info
1497 
1498 static int snd_es1373_rear_get(struct snd_kcontrol *kcontrol,
1499                                struct snd_ctl_elem_value *ucontrol)
1500 {
1501         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1502         int val = 0;
1503         
1504         spin_lock_irq(&ensoniq->reg_lock);
1505         if ((ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|
1506                               ES_1373_REAR_BIT24)) == ES_1373_REAR_BIT26)
1507                 val = 1;
1508         ucontrol->value.integer.value[0] = val;
1509         spin_unlock_irq(&ensoniq->reg_lock);
1510         return 0;
1511 }
1512 
1513 static int snd_es1373_rear_put(struct snd_kcontrol *kcontrol,
1514                                struct snd_ctl_elem_value *ucontrol)
1515 {
1516         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1517         unsigned int nval1;
1518         int change;
1519         
1520         nval1 = ucontrol->value.integer.value[0] ?
1521                 ES_1373_REAR_BIT26 : (ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1522         spin_lock_irq(&ensoniq->reg_lock);
1523         change = (ensoniq->cssr & (ES_1373_REAR_BIT27|
1524                                    ES_1373_REAR_BIT26|ES_1373_REAR_BIT24)) != nval1;
1525         ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24);
1526         ensoniq->cssr |= nval1;
1527         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1528         spin_unlock_irq(&ensoniq->reg_lock);
1529         return change;
1530 }
1531 
1532 static const struct snd_kcontrol_new snd_ens1373_rear =
1533 {
1534         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
1535         .name =         "AC97 2ch->4ch Copy Switch",
1536         .info =         snd_es1373_rear_info,
1537         .get =          snd_es1373_rear_get,
1538         .put =          snd_es1373_rear_put,
1539 };
1540 
1541 #define snd_es1373_line_info            snd_ctl_boolean_mono_info
1542 
1543 static int snd_es1373_line_get(struct snd_kcontrol *kcontrol,
1544                                struct snd_ctl_elem_value *ucontrol)
1545 {
1546         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1547         int val = 0;
1548         
1549         spin_lock_irq(&ensoniq->reg_lock);
1550         if (ensoniq->ctrl & ES_1371_GPIO_OUT(4))
1551                 val = 1;
1552         ucontrol->value.integer.value[0] = val;
1553         spin_unlock_irq(&ensoniq->reg_lock);
1554         return 0;
1555 }
1556 
1557 static int snd_es1373_line_put(struct snd_kcontrol *kcontrol,
1558                                struct snd_ctl_elem_value *ucontrol)
1559 {
1560         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1561         int changed;
1562         unsigned int ctrl;
1563         
1564         spin_lock_irq(&ensoniq->reg_lock);
1565         ctrl = ensoniq->ctrl;
1566         if (ucontrol->value.integer.value[0])
1567                 ensoniq->ctrl |= ES_1371_GPIO_OUT(4);   /* switch line-in -> rear out */
1568         else
1569                 ensoniq->ctrl &= ~ES_1371_GPIO_OUT(4);
1570         changed = (ctrl != ensoniq->ctrl);
1571         if (changed)
1572                 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1573         spin_unlock_irq(&ensoniq->reg_lock);
1574         return changed;
1575 }
1576 
1577 static const struct snd_kcontrol_new snd_ens1373_line =
1578 {
1579         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
1580         .name =         "Line In->Rear Out Switch",
1581         .info =         snd_es1373_line_info,
1582         .get =          snd_es1373_line_get,
1583         .put =          snd_es1373_line_put,
1584 };
1585 
1586 static void snd_ensoniq_mixer_free_ac97(struct snd_ac97 *ac97)
1587 {
1588         struct ensoniq *ensoniq = ac97->private_data;
1589         ensoniq->u.es1371.ac97 = NULL;
1590 }
1591 
1592 struct es1371_quirk {
1593         unsigned short vid;             /* vendor ID */
1594         unsigned short did;             /* device ID */
1595         unsigned char rev;              /* revision */
1596 };
1597 
1598 static int es1371_quirk_lookup(struct ensoniq *ensoniq,
1599                                 struct es1371_quirk *list)
1600 {
1601         while (list->vid != (unsigned short)PCI_ANY_ID) {
1602                 if (ensoniq->pci->vendor == list->vid &&
1603                     ensoniq->pci->device == list->did &&
1604                     ensoniq->rev == list->rev)
1605                         return 1;
1606                 list++;
1607         }
1608         return 0;
1609 }
1610 
1611 static struct es1371_quirk es1371_spdif_present[] = {
1612         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1613         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1614         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1615         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1616         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1617         { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1618 };
1619 
1620 static struct snd_pci_quirk ens1373_line_quirk[] = {
1621         SND_PCI_QUIRK_ID(0x1274, 0x2000), /* GA-7DXR */
1622         SND_PCI_QUIRK_ID(0x1458, 0xa000), /* GA-8IEXP */
1623         { } /* end */
1624 };
1625 
1626 static int snd_ensoniq_1371_mixer(struct ensoniq *ensoniq,
1627                                   int has_spdif, int has_line)
1628 {
1629         struct snd_card *card = ensoniq->card;
1630         struct snd_ac97_bus *pbus;
1631         struct snd_ac97_template ac97;
1632         int err;
1633         static struct snd_ac97_bus_ops ops = {
1634                 .write = snd_es1371_codec_write,
1635                 .read = snd_es1371_codec_read,
1636                 .wait = snd_es1371_codec_wait,
1637         };
1638 
1639         if ((err = snd_ac97_bus(card, 0, &ops, NULL, &pbus)) < 0)
1640                 return err;
1641 
1642         memset(&ac97, 0, sizeof(ac97));
1643         ac97.private_data = ensoniq;
1644         ac97.private_free = snd_ensoniq_mixer_free_ac97;
1645         ac97.pci = ensoniq->pci;
1646         ac97.scaps = AC97_SCAP_AUDIO;
1647         if ((err = snd_ac97_mixer(pbus, &ac97, &ensoniq->u.es1371.ac97)) < 0)
1648                 return err;
1649         if (has_spdif > 0 ||
1650             (!has_spdif && es1371_quirk_lookup(ensoniq, es1371_spdif_present))) {
1651                 struct snd_kcontrol *kctl;
1652                 int i, is_spdif = 0;
1653 
1654                 ensoniq->spdif_default = ensoniq->spdif_stream =
1655                         SNDRV_PCM_DEFAULT_CON_SPDIF;
1656                 outl(ensoniq->spdif_default, ES_REG(ensoniq, CHANNEL_STATUS));
1657 
1658                 if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SPDIF)
1659                         is_spdif++;
1660 
1661                 for (i = 0; i < ARRAY_SIZE(snd_es1371_mixer_spdif); i++) {
1662                         kctl = snd_ctl_new1(&snd_es1371_mixer_spdif[i], ensoniq);
1663                         if (!kctl)
1664                                 return -ENOMEM;
1665                         kctl->id.index = is_spdif;
1666                         err = snd_ctl_add(card, kctl);
1667                         if (err < 0)
1668                                 return err;
1669                 }
1670         }
1671         if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SDAC) {
1672                 /* mirror rear to front speakers */
1673                 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1674                 ensoniq->cssr |= ES_1373_REAR_BIT26;
1675                 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_rear, ensoniq));
1676                 if (err < 0)
1677                         return err;
1678         }
1679         if (has_line > 0 ||
1680             snd_pci_quirk_lookup(ensoniq->pci, ens1373_line_quirk)) {
1681                  err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_line,
1682                                                       ensoniq));
1683                  if (err < 0)
1684                          return err;
1685         }
1686 
1687         return 0;
1688 }
1689 
1690 #endif /* CHIP1371 */
1691 
1692 /* generic control callbacks for ens1370 */
1693 #ifdef CHIP1370
1694 #define ENSONIQ_CONTROL(xname, mask) \
1695 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, .name = xname, .info = snd_ensoniq_control_info, \
1696   .get = snd_ensoniq_control_get, .put = snd_ensoniq_control_put, \
1697   .private_value = mask }
1698 
1699 #define snd_ensoniq_control_info        snd_ctl_boolean_mono_info
1700 
1701 static int snd_ensoniq_control_get(struct snd_kcontrol *kcontrol,
1702                                    struct snd_ctl_elem_value *ucontrol)
1703 {
1704         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1705         int mask = kcontrol->private_value;
1706         
1707         spin_lock_irq(&ensoniq->reg_lock);
1708         ucontrol->value.integer.value[0] = ensoniq->ctrl & mask ? 1 : 0;
1709         spin_unlock_irq(&ensoniq->reg_lock);
1710         return 0;
1711 }
1712 
1713 static int snd_ensoniq_control_put(struct snd_kcontrol *kcontrol,
1714                                    struct snd_ctl_elem_value *ucontrol)
1715 {
1716         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1717         int mask = kcontrol->private_value;
1718         unsigned int nval;
1719         int change;
1720         
1721         nval = ucontrol->value.integer.value[0] ? mask : 0;
1722         spin_lock_irq(&ensoniq->reg_lock);
1723         change = (ensoniq->ctrl & mask) != nval;
1724         ensoniq->ctrl &= ~mask;
1725         ensoniq->ctrl |= nval;
1726         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1727         spin_unlock_irq(&ensoniq->reg_lock);
1728         return change;
1729 }
1730 
1731 /*
1732  * ENS1370 mixer
1733  */
1734 
1735 static struct snd_kcontrol_new snd_es1370_controls[2] = {
1736 ENSONIQ_CONTROL("PCM 0 Output also on Line-In Jack", ES_1370_XCTL0),
1737 ENSONIQ_CONTROL("Mic +5V bias", ES_1370_XCTL1)
1738 };
1739 
1740 #define ES1370_CONTROLS ARRAY_SIZE(snd_es1370_controls)
1741 
1742 static void snd_ensoniq_mixer_free_ak4531(struct snd_ak4531 *ak4531)
1743 {
1744         struct ensoniq *ensoniq = ak4531->private_data;
1745         ensoniq->u.es1370.ak4531 = NULL;
1746 }
1747 
1748 static int snd_ensoniq_1370_mixer(struct ensoniq *ensoniq)
1749 {
1750         struct snd_card *card = ensoniq->card;
1751         struct snd_ak4531 ak4531;
1752         unsigned int idx;
1753         int err;
1754 
1755         /* try reset AK4531 */
1756         outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
1757         inw(ES_REG(ensoniq, 1370_CODEC));
1758         udelay(100);
1759         outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
1760         inw(ES_REG(ensoniq, 1370_CODEC));
1761         udelay(100);
1762 
1763         memset(&ak4531, 0, sizeof(ak4531));
1764         ak4531.write = snd_es1370_codec_write;
1765         ak4531.private_data = ensoniq;
1766         ak4531.private_free = snd_ensoniq_mixer_free_ak4531;
1767         if ((err = snd_ak4531_mixer(card, &ak4531, &ensoniq->u.es1370.ak4531)) < 0)
1768                 return err;
1769         for (idx = 0; idx < ES1370_CONTROLS; idx++) {
1770                 err = snd_ctl_add(card, snd_ctl_new1(&snd_es1370_controls[idx], ensoniq));
1771                 if (err < 0)
1772                         return err;
1773         }
1774         return 0;
1775 }
1776 
1777 #endif /* CHIP1370 */
1778 
1779 #ifdef SUPPORT_JOYSTICK
1780 
1781 #ifdef CHIP1371
1782 static int snd_ensoniq_get_joystick_port(struct ensoniq *ensoniq, int dev)
1783 {
1784         switch (joystick_port[dev]) {
1785         case 0: /* disabled */
1786         case 1: /* auto-detect */
1787         case 0x200:
1788         case 0x208:
1789         case 0x210:
1790         case 0x218:
1791                 return joystick_port[dev];
1792 
1793         default:
1794                 dev_err(ensoniq->card->dev,
1795                         "invalid joystick port %#x", joystick_port[dev]);
1796                 return 0;
1797         }
1798 }
1799 #else
1800 static int snd_ensoniq_get_joystick_port(struct ensoniq *ensoniq, int dev)
1801 {
1802         return joystick[dev] ? 0x200 : 0;
1803 }
1804 #endif
1805 
1806 static int snd_ensoniq_create_gameport(struct ensoniq *ensoniq, int dev)
1807 {
1808         struct gameport *gp;
1809         int io_port;
1810 
1811         io_port = snd_ensoniq_get_joystick_port(ensoniq, dev);
1812 
1813         switch (io_port) {
1814         case 0:
1815                 return -ENOSYS;
1816 
1817         case 1: /* auto_detect */
1818                 for (io_port = 0x200; io_port <= 0x218; io_port += 8)
1819                         if (request_region(io_port, 8, "ens137x: gameport"))
1820                                 break;
1821                 if (io_port > 0x218) {
1822                         dev_warn(ensoniq->card->dev,
1823                                  "no gameport ports available\n");
1824                         return -EBUSY;
1825                 }
1826                 break;
1827 
1828         default:
1829                 if (!request_region(io_port, 8, "ens137x: gameport")) {
1830                         dev_warn(ensoniq->card->dev,
1831                                  "gameport io port %#x in use\n",
1832                                io_port);
1833                         return -EBUSY;
1834                 }
1835                 break;
1836         }
1837 
1838         ensoniq->gameport = gp = gameport_allocate_port();
1839         if (!gp) {
1840                 dev_err(ensoniq->card->dev,
1841                         "cannot allocate memory for gameport\n");
1842                 release_region(io_port, 8);
1843                 return -ENOMEM;
1844         }
1845 
1846         gameport_set_name(gp, "ES137x");
1847         gameport_set_phys(gp, "pci%s/gameport0", pci_name(ensoniq->pci));
1848         gameport_set_dev_parent(gp, &ensoniq->pci->dev);
1849         gp->io = io_port;
1850 
1851         ensoniq->ctrl |= ES_JYSTK_EN;
1852 #ifdef CHIP1371
1853         ensoniq->ctrl &= ~ES_1371_JOY_ASELM;
1854         ensoniq->ctrl |= ES_1371_JOY_ASEL((io_port - 0x200) / 8);
1855 #endif
1856         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1857 
1858         gameport_register_port(ensoniq->gameport);
1859 
1860         return 0;
1861 }
1862 
1863 static void snd_ensoniq_free_gameport(struct ensoniq *ensoniq)
1864 {
1865         if (ensoniq->gameport) {
1866                 int port = ensoniq->gameport->io;
1867 
1868                 gameport_unregister_port(ensoniq->gameport);
1869                 ensoniq->gameport = NULL;
1870                 ensoniq->ctrl &= ~ES_JYSTK_EN;
1871                 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1872                 release_region(port, 8);
1873         }
1874 }
1875 #else
1876 static inline int snd_ensoniq_create_gameport(struct ensoniq *ensoniq, long port) { return -ENOSYS; }
1877 static inline void snd_ensoniq_free_gameport(struct ensoniq *ensoniq) { }
1878 #endif /* SUPPORT_JOYSTICK */
1879 
1880 /*
1881 
1882  */
1883 
1884 static void snd_ensoniq_proc_read(struct snd_info_entry *entry, 
1885                                   struct snd_info_buffer *buffer)
1886 {
1887         struct ensoniq *ensoniq = entry->private_data;
1888 
1889         snd_iprintf(buffer, "Ensoniq AudioPCI " CHIP_NAME "\n\n");
1890         snd_iprintf(buffer, "Joystick enable  : %s\n",
1891                     ensoniq->ctrl & ES_JYSTK_EN ? "on" : "off");
1892 #ifdef CHIP1370
1893         snd_iprintf(buffer, "MIC +5V bias     : %s\n",
1894                     ensoniq->ctrl & ES_1370_XCTL1 ? "on" : "off");
1895         snd_iprintf(buffer, "Line In to AOUT  : %s\n",
1896                     ensoniq->ctrl & ES_1370_XCTL0 ? "on" : "off");
1897 #else
1898         snd_iprintf(buffer, "Joystick port    : 0x%x\n",
1899                     (ES_1371_JOY_ASELI(ensoniq->ctrl) * 8) + 0x200);
1900 #endif
1901 }
1902 
1903 static void snd_ensoniq_proc_init(struct ensoniq *ensoniq)
1904 {
1905         struct snd_info_entry *entry;
1906 
1907         if (! snd_card_proc_new(ensoniq->card, "audiopci", &entry))
1908                 snd_info_set_text_ops(entry, ensoniq, snd_ensoniq_proc_read);
1909 }
1910 
1911 /*
1912 
1913  */
1914 
1915 static int snd_ensoniq_free(struct ensoniq *ensoniq)
1916 {
1917         snd_ensoniq_free_gameport(ensoniq);
1918         if (ensoniq->irq < 0)
1919                 goto __hw_end;
1920 #ifdef CHIP1370
1921         outl(ES_1370_SERR_DISABLE, ES_REG(ensoniq, CONTROL));   /* switch everything off */
1922         outl(0, ES_REG(ensoniq, SERIAL));       /* clear serial interface */
1923 #else
1924         outl(0, ES_REG(ensoniq, CONTROL));      /* switch everything off */
1925         outl(0, ES_REG(ensoniq, SERIAL));       /* clear serial interface */
1926 #endif
1927         if (ensoniq->irq >= 0)
1928                 synchronize_irq(ensoniq->irq);
1929         pci_set_power_state(ensoniq->pci, PCI_D3hot);
1930       __hw_end:
1931 #ifdef CHIP1370
1932         if (ensoniq->dma_bug.area)
1933                 snd_dma_free_pages(&ensoniq->dma_bug);
1934 #endif
1935         if (ensoniq->irq >= 0)
1936                 free_irq(ensoniq->irq, ensoniq);
1937         pci_release_regions(ensoniq->pci);
1938         pci_disable_device(ensoniq->pci);
1939         kfree(ensoniq);
1940         return 0;
1941 }
1942 
1943 static int snd_ensoniq_dev_free(struct snd_device *device)
1944 {
1945         struct ensoniq *ensoniq = device->device_data;
1946         return snd_ensoniq_free(ensoniq);
1947 }
1948 
1949 #ifdef CHIP1371
1950 static struct snd_pci_quirk es1371_amplifier_hack[] = {
1951         SND_PCI_QUIRK_ID(0x107b, 0x2150),       /* Gateway Solo 2150 */
1952         SND_PCI_QUIRK_ID(0x13bd, 0x100c),       /* EV1938 on Mebius PC-MJ100V */
1953         SND_PCI_QUIRK_ID(0x1102, 0x5938),       /* Targa Xtender300 */
1954         SND_PCI_QUIRK_ID(0x1102, 0x8938),       /* IPC Topnote G notebook */
1955         { } /* end */
1956 };
1957 
1958 static struct es1371_quirk es1371_ac97_reset_hack[] = {
1959         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1960         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1961         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1962         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1963         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1964         { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1965 };
1966 #endif
1967 
1968 static void snd_ensoniq_chip_init(struct ensoniq *ensoniq)
1969 {
1970 #ifdef CHIP1371
1971         int idx;
1972 #endif
1973         /* this code was part of snd_ensoniq_create before intruduction
1974           * of suspend/resume
1975           */
1976 #ifdef CHIP1370
1977         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1978         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1979         outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1980         outl(ensoniq->dma_bug.addr, ES_REG(ensoniq, PHANTOM_FRAME));
1981         outl(0, ES_REG(ensoniq, PHANTOM_COUNT));
1982 #else
1983         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1984         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1985         outl(0, ES_REG(ensoniq, 1371_LEGACY));
1986         if (es1371_quirk_lookup(ensoniq, es1371_ac97_reset_hack)) {
1987             outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1988             /* need to delay around 20ms(bleech) to give
1989                some CODECs enough time to wakeup */
1990             msleep(20);
1991         }
1992         /* AC'97 warm reset to start the bitclk */
1993         outl(ensoniq->ctrl | ES_1371_SYNC_RES, ES_REG(ensoniq, CONTROL));
1994         inl(ES_REG(ensoniq, CONTROL));
1995         udelay(20);
1996         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1997         /* Init the sample rate converter */
1998         snd_es1371_wait_src_ready(ensoniq);     
1999         outl(ES_1371_SRC_DISABLE, ES_REG(ensoniq, 1371_SMPRATE));
2000         for (idx = 0; idx < 0x80; idx++)
2001                 snd_es1371_src_write(ensoniq, idx, 0);
2002         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_TRUNC_N, 16 << 4);
2003         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 16 << 10);
2004         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_TRUNC_N, 16 << 4);
2005         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 16 << 10);
2006         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, 1 << 12);
2007         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, 1 << 12);
2008         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1, 1 << 12);
2009         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1 + 1, 1 << 12);
2010         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2, 1 << 12);
2011         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2 + 1, 1 << 12);
2012         snd_es1371_adc_rate(ensoniq, 22050);
2013         snd_es1371_dac1_rate(ensoniq, 22050);
2014         snd_es1371_dac2_rate(ensoniq, 22050);
2015         /* WARNING:
2016          * enabling the sample rate converter without properly programming
2017          * its parameters causes the chip to lock up (the SRC busy bit will
2018          * be stuck high, and I've found no way to rectify this other than
2019          * power cycle) - Thomas Sailer
2020          */
2021         snd_es1371_wait_src_ready(ensoniq);
2022         outl(0, ES_REG(ensoniq, 1371_SMPRATE));
2023         /* try reset codec directly */
2024         outl(ES_1371_CODEC_WRITE(0, 0), ES_REG(ensoniq, 1371_CODEC));
2025 #endif
2026         outb(ensoniq->uartc = 0x00, ES_REG(ensoniq, UART_CONTROL));
2027         outb(0x00, ES_REG(ensoniq, UART_RES));
2028         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
2029         synchronize_irq(ensoniq->irq);
2030 }
2031 
2032 #ifdef CONFIG_PM_SLEEP
2033 static int snd_ensoniq_suspend(struct device *dev)
2034 {
2035         struct snd_card *card = dev_get_drvdata(dev);
2036         struct ensoniq *ensoniq = card->private_data;
2037         
2038         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2039 
2040         snd_pcm_suspend_all(ensoniq->pcm1);
2041         snd_pcm_suspend_all(ensoniq->pcm2);
2042         
2043 #ifdef CHIP1371 
2044         snd_ac97_suspend(ensoniq->u.es1371.ac97);
2045 #else
2046         /* try to reset AK4531 */
2047         outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
2048         inw(ES_REG(ensoniq, 1370_CODEC));
2049         udelay(100);
2050         outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
2051         inw(ES_REG(ensoniq, 1370_CODEC));
2052         udelay(100);
2053         snd_ak4531_suspend(ensoniq->u.es1370.ak4531);
2054 #endif  
2055         return 0;
2056 }
2057 
2058 static int snd_ensoniq_resume(struct device *dev)
2059 {
2060         struct snd_card *card = dev_get_drvdata(dev);
2061         struct ensoniq *ensoniq = card->private_data;
2062 
2063         snd_ensoniq_chip_init(ensoniq);
2064 
2065 #ifdef CHIP1371 
2066         snd_ac97_resume(ensoniq->u.es1371.ac97);
2067 #else
2068         snd_ak4531_resume(ensoniq->u.es1370.ak4531);
2069 #endif  
2070         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2071         return 0;
2072 }
2073 
2074 static SIMPLE_DEV_PM_OPS(snd_ensoniq_pm, snd_ensoniq_suspend, snd_ensoniq_resume);
2075 #define SND_ENSONIQ_PM_OPS      &snd_ensoniq_pm
2076 #else
2077 #define SND_ENSONIQ_PM_OPS      NULL
2078 #endif /* CONFIG_PM_SLEEP */
2079 
2080 static int snd_ensoniq_create(struct snd_card *card,
2081                               struct pci_dev *pci,
2082                               struct ensoniq **rensoniq)
2083 {
2084         struct ensoniq *ensoniq;
2085         int err;
2086         static struct snd_device_ops ops = {
2087                 .dev_free =     snd_ensoniq_dev_free,
2088         };
2089 
2090         *rensoniq = NULL;
2091         if ((err = pci_enable_device(pci)) < 0)
2092                 return err;
2093         ensoniq = kzalloc(sizeof(*ensoniq), GFP_KERNEL);
2094         if (ensoniq == NULL) {
2095                 pci_disable_device(pci);
2096                 return -ENOMEM;
2097         }
2098         spin_lock_init(&ensoniq->reg_lock);
2099         mutex_init(&ensoniq->src_mutex);
2100         ensoniq->card = card;
2101         ensoniq->pci = pci;
2102         ensoniq->irq = -1;
2103         if ((err = pci_request_regions(pci, "Ensoniq AudioPCI")) < 0) {
2104                 kfree(ensoniq);
2105                 pci_disable_device(pci);
2106                 return err;
2107         }
2108         ensoniq->port = pci_resource_start(pci, 0);
2109         if (request_irq(pci->irq, snd_audiopci_interrupt, IRQF_SHARED,
2110                         KBUILD_MODNAME, ensoniq)) {
2111                 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
2112                 snd_ensoniq_free(ensoniq);
2113                 return -EBUSY;
2114         }
2115         ensoniq->irq = pci->irq;
2116 #ifdef CHIP1370
2117         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
2118                                 16, &ensoniq->dma_bug) < 0) {
2119                 dev_err(card->dev, "unable to allocate space for phantom area - dma_bug\n");
2120                 snd_ensoniq_free(ensoniq);
2121                 return -EBUSY;
2122         }
2123 #endif
2124         pci_set_master(pci);
2125         ensoniq->rev = pci->revision;
2126 #ifdef CHIP1370
2127 #if 0
2128         ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_SERR_DISABLE |
2129                 ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
2130 #else   /* get microphone working */
2131         ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
2132 #endif
2133         ensoniq->sctrl = 0;
2134 #else
2135         ensoniq->ctrl = 0;
2136         ensoniq->sctrl = 0;
2137         ensoniq->cssr = 0;
2138         if (snd_pci_quirk_lookup(pci, es1371_amplifier_hack))
2139                 ensoniq->ctrl |= ES_1371_GPIO_OUT(1);   /* turn amplifier on */
2140 
2141         if (es1371_quirk_lookup(ensoniq, es1371_ac97_reset_hack))
2142                 ensoniq->cssr |= ES_1371_ST_AC97_RST;
2143 #endif
2144 
2145         snd_ensoniq_chip_init(ensoniq);
2146 
2147         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ensoniq, &ops)) < 0) {
2148                 snd_ensoniq_free(ensoniq);
2149                 return err;
2150         }
2151 
2152         snd_ensoniq_proc_init(ensoniq);
2153 
2154         *rensoniq = ensoniq;
2155         return 0;
2156 }
2157 
2158 /*
2159  *  MIDI section
2160  */
2161 
2162 static void snd_ensoniq_midi_interrupt(struct ensoniq * ensoniq)
2163 {
2164         struct snd_rawmidi *rmidi = ensoniq->rmidi;
2165         unsigned char status, mask, byte;
2166 
2167         if (rmidi == NULL)
2168                 return;
2169         /* do Rx at first */
2170         spin_lock(&ensoniq->reg_lock);
2171         mask = ensoniq->uartm & ES_MODE_INPUT ? ES_RXRDY : 0;
2172         while (mask) {
2173                 status = inb(ES_REG(ensoniq, UART_STATUS));
2174                 if ((status & mask) == 0)
2175                         break;
2176                 byte = inb(ES_REG(ensoniq, UART_DATA));
2177                 snd_rawmidi_receive(ensoniq->midi_input, &byte, 1);
2178         }
2179         spin_unlock(&ensoniq->reg_lock);
2180 
2181         /* do Tx at second */
2182         spin_lock(&ensoniq->reg_lock);
2183         mask = ensoniq->uartm & ES_MODE_OUTPUT ? ES_TXRDY : 0;
2184         while (mask) {
2185                 status = inb(ES_REG(ensoniq, UART_STATUS));
2186                 if ((status & mask) == 0)
2187                         break;
2188                 if (snd_rawmidi_transmit(ensoniq->midi_output, &byte, 1) != 1) {
2189                         ensoniq->uartc &= ~ES_TXINTENM;
2190                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2191                         mask &= ~ES_TXRDY;
2192                 } else {
2193                         outb(byte, ES_REG(ensoniq, UART_DATA));
2194                 }
2195         }
2196         spin_unlock(&ensoniq->reg_lock);
2197 }
2198 
2199 static int snd_ensoniq_midi_input_open(struct snd_rawmidi_substream *substream)
2200 {
2201         struct ensoniq *ensoniq = substream->rmidi->private_data;
2202 
2203         spin_lock_irq(&ensoniq->reg_lock);
2204         ensoniq->uartm |= ES_MODE_INPUT;
2205         ensoniq->midi_input = substream;
2206         if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2207                 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2208                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2209                 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2210         }
2211         spin_unlock_irq(&ensoniq->reg_lock);
2212         return 0;
2213 }
2214 
2215 static int snd_ensoniq_midi_input_close(struct snd_rawmidi_substream *substream)
2216 {
2217         struct ensoniq *ensoniq = substream->rmidi->private_data;
2218 
2219         spin_lock_irq(&ensoniq->reg_lock);
2220         if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2221                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2222                 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2223         } else {
2224                 outb(ensoniq->uartc &= ~ES_RXINTEN, ES_REG(ensoniq, UART_CONTROL));
2225         }
2226         ensoniq->midi_input = NULL;
2227         ensoniq->uartm &= ~ES_MODE_INPUT;
2228         spin_unlock_irq(&ensoniq->reg_lock);
2229         return 0;
2230 }
2231 
2232 static int snd_ensoniq_midi_output_open(struct snd_rawmidi_substream *substream)
2233 {
2234         struct ensoniq *ensoniq = substream->rmidi->private_data;
2235 
2236         spin_lock_irq(&ensoniq->reg_lock);
2237         ensoniq->uartm |= ES_MODE_OUTPUT;
2238         ensoniq->midi_output = substream;
2239         if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2240                 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2241                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2242                 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2243         }
2244         spin_unlock_irq(&ensoniq->reg_lock);
2245         return 0;
2246 }
2247 
2248 static int snd_ensoniq_midi_output_close(struct snd_rawmidi_substream *substream)
2249 {
2250         struct ensoniq *ensoniq = substream->rmidi->private_data;
2251 
2252         spin_lock_irq(&ensoniq->reg_lock);
2253         if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2254                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2255                 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2256         } else {
2257                 outb(ensoniq->uartc &= ~ES_TXINTENM, ES_REG(ensoniq, UART_CONTROL));
2258         }
2259         ensoniq->midi_output = NULL;
2260         ensoniq->uartm &= ~ES_MODE_OUTPUT;
2261         spin_unlock_irq(&ensoniq->reg_lock);
2262         return 0;
2263 }
2264 
2265 static void snd_ensoniq_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
2266 {
2267         unsigned long flags;
2268         struct ensoniq *ensoniq = substream->rmidi->private_data;
2269         int idx;
2270 
2271         spin_lock_irqsave(&ensoniq->reg_lock, flags);
2272         if (up) {
2273                 if ((ensoniq->uartc & ES_RXINTEN) == 0) {
2274                         /* empty input FIFO */
2275                         for (idx = 0; idx < 32; idx++)
2276                                 inb(ES_REG(ensoniq, UART_DATA));
2277                         ensoniq->uartc |= ES_RXINTEN;
2278                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2279                 }
2280         } else {
2281                 if (ensoniq->uartc & ES_RXINTEN) {
2282                         ensoniq->uartc &= ~ES_RXINTEN;
2283                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2284                 }
2285         }
2286         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2287 }
2288 
2289 static void snd_ensoniq_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
2290 {
2291         unsigned long flags;
2292         struct ensoniq *ensoniq = substream->rmidi->private_data;
2293         unsigned char byte;
2294 
2295         spin_lock_irqsave(&ensoniq->reg_lock, flags);
2296         if (up) {
2297                 if (ES_TXINTENI(ensoniq->uartc) == 0) {
2298                         ensoniq->uartc |= ES_TXINTENO(1);
2299                         /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2300                         while (ES_TXINTENI(ensoniq->uartc) == 1 &&
2301                                (inb(ES_REG(ensoniq, UART_STATUS)) & ES_TXRDY)) {
2302                                 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2303                                         ensoniq->uartc &= ~ES_TXINTENM;
2304                                 } else {
2305                                         outb(byte, ES_REG(ensoniq, UART_DATA));
2306                                 }
2307                         }
2308                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2309                 }
2310         } else {
2311                 if (ES_TXINTENI(ensoniq->uartc) == 1) {
2312                         ensoniq->uartc &= ~ES_TXINTENM;
2313                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2314                 }
2315         }
2316         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2317 }
2318 
2319 static const struct snd_rawmidi_ops snd_ensoniq_midi_output =
2320 {
2321         .open =         snd_ensoniq_midi_output_open,
2322         .close =        snd_ensoniq_midi_output_close,
2323         .trigger =      snd_ensoniq_midi_output_trigger,
2324 };
2325 
2326 static const struct snd_rawmidi_ops snd_ensoniq_midi_input =
2327 {
2328         .open =         snd_ensoniq_midi_input_open,
2329         .close =        snd_ensoniq_midi_input_close,
2330         .trigger =      snd_ensoniq_midi_input_trigger,
2331 };
2332 
2333 static int snd_ensoniq_midi(struct ensoniq *ensoniq, int device)
2334 {
2335         struct snd_rawmidi *rmidi;
2336         int err;
2337 
2338         if ((err = snd_rawmidi_new(ensoniq->card, "ES1370/1", device, 1, 1, &rmidi)) < 0)
2339                 return err;
2340         strcpy(rmidi->name, CHIP_NAME);
2341         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_ensoniq_midi_output);
2342         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_ensoniq_midi_input);
2343         rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT |
2344                 SNDRV_RAWMIDI_INFO_DUPLEX;
2345         rmidi->private_data = ensoniq;
2346         ensoniq->rmidi = rmidi;
2347         return 0;
2348 }
2349 
2350 /*
2351  *  Interrupt handler
2352  */
2353 
2354 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id)
2355 {
2356         struct ensoniq *ensoniq = dev_id;
2357         unsigned int status, sctrl;
2358 
2359         if (ensoniq == NULL)
2360                 return IRQ_NONE;
2361 
2362         status = inl(ES_REG(ensoniq, STATUS));
2363         if (!(status & ES_INTR))
2364                 return IRQ_NONE;
2365 
2366         spin_lock(&ensoniq->reg_lock);
2367         sctrl = ensoniq->sctrl;
2368         if (status & ES_DAC1)
2369                 sctrl &= ~ES_P1_INT_EN;
2370         if (status & ES_DAC2)
2371                 sctrl &= ~ES_P2_INT_EN;
2372         if (status & ES_ADC)
2373                 sctrl &= ~ES_R1_INT_EN;
2374         outl(sctrl, ES_REG(ensoniq, SERIAL));
2375         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
2376         spin_unlock(&ensoniq->reg_lock);
2377 
2378         if (status & ES_UART)
2379                 snd_ensoniq_midi_interrupt(ensoniq);
2380         if ((status & ES_DAC2) && ensoniq->playback2_substream)
2381                 snd_pcm_period_elapsed(ensoniq->playback2_substream);
2382         if ((status & ES_ADC) && ensoniq->capture_substream)
2383                 snd_pcm_period_elapsed(ensoniq->capture_substream);
2384         if ((status & ES_DAC1) && ensoniq->playback1_substream)
2385                 snd_pcm_period_elapsed(ensoniq->playback1_substream);
2386         return IRQ_HANDLED;
2387 }
2388 
2389 static int snd_audiopci_probe(struct pci_dev *pci,
2390                               const struct pci_device_id *pci_id)
2391 {
2392         static int dev;
2393         struct snd_card *card;
2394         struct ensoniq *ensoniq;
2395         int err;
2396 
2397         if (dev >= SNDRV_CARDS)
2398                 return -ENODEV;
2399         if (!enable[dev]) {
2400                 dev++;
2401                 return -ENOENT;
2402         }
2403 
2404         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2405                            0, &card);
2406         if (err < 0)
2407                 return err;
2408 
2409         if ((err = snd_ensoniq_create(card, pci, &ensoniq)) < 0) {
2410                 snd_card_free(card);
2411                 return err;
2412         }
2413         card->private_data = ensoniq;
2414 
2415 #ifdef CHIP1370
2416         if ((err = snd_ensoniq_1370_mixer(ensoniq)) < 0) {
2417                 snd_card_free(card);
2418                 return err;
2419         }
2420 #endif
2421 #ifdef CHIP1371
2422         if ((err = snd_ensoniq_1371_mixer(ensoniq, spdif[dev], lineio[dev])) < 0) {
2423                 snd_card_free(card);
2424                 return err;
2425         }
2426 #endif
2427         if ((err = snd_ensoniq_pcm(ensoniq, 0)) < 0) {
2428                 snd_card_free(card);
2429                 return err;
2430         }
2431         if ((err = snd_ensoniq_pcm2(ensoniq, 1)) < 0) {
2432                 snd_card_free(card);
2433                 return err;
2434         }
2435         if ((err = snd_ensoniq_midi(ensoniq, 0)) < 0) {
2436                 snd_card_free(card);
2437                 return err;
2438         }
2439 
2440         snd_ensoniq_create_gameport(ensoniq, dev);
2441 
2442         strcpy(card->driver, DRIVER_NAME);
2443 
2444         strcpy(card->shortname, "Ensoniq AudioPCI");
2445         sprintf(card->longname, "%s %s at 0x%lx, irq %i",
2446                 card->shortname,
2447                 card->driver,
2448                 ensoniq->port,
2449                 ensoniq->irq);
2450 
2451         if ((err = snd_card_register(card)) < 0) {
2452                 snd_card_free(card);
2453                 return err;
2454         }
2455 
2456         pci_set_drvdata(pci, card);
2457         dev++;
2458         return 0;
2459 }
2460 
2461 static void snd_audiopci_remove(struct pci_dev *pci)
2462 {
2463         snd_card_free(pci_get_drvdata(pci));
2464 }
2465 
2466 static struct pci_driver ens137x_driver = {
2467         .name = KBUILD_MODNAME,
2468         .id_table = snd_audiopci_ids,
2469         .probe = snd_audiopci_probe,
2470         .remove = snd_audiopci_remove,
2471         .driver = {
2472                 .pm = SND_ENSONIQ_PM_OPS,
2473         },
2474 };
2475         
2476 module_pci_driver(ens137x_driver);
2477 

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