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TOMOYO Linux Cross Reference
Linux/sound/pci/hda/hda_controller.c

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  1 /*
  2  *
  3  *  Implementation of primary alsa driver code base for Intel HD Audio.
  4  *
  5  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
  6  *
  7  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
  8  *                     PeiSen Hou <pshou@realtek.com.tw>
  9  *
 10  *  This program is free software; you can redistribute it and/or modify it
 11  *  under the terms of the GNU General Public License as published by the Free
 12  *  Software Foundation; either version 2 of the License, or (at your option)
 13  *  any later version.
 14  *
 15  *  This program is distributed in the hope that it will be useful, but WITHOUT
 16  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 17  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 18  *  more details.
 19  *
 20  *
 21  */
 22 
 23 #include <linux/clocksource.h>
 24 #include <linux/delay.h>
 25 #include <linux/interrupt.h>
 26 #include <linux/kernel.h>
 27 #include <linux/module.h>
 28 #include <linux/pm_runtime.h>
 29 #include <linux/slab.h>
 30 #include <sound/core.h>
 31 #include <sound/initval.h>
 32 #include "hda_priv.h"
 33 #include "hda_controller.h"
 34 
 35 #define CREATE_TRACE_POINTS
 36 #include "hda_intel_trace.h"
 37 
 38 /* DSP lock helpers */
 39 #ifdef CONFIG_SND_HDA_DSP_LOADER
 40 #define dsp_lock_init(dev)      mutex_init(&(dev)->dsp_mutex)
 41 #define dsp_lock(dev)           mutex_lock(&(dev)->dsp_mutex)
 42 #define dsp_unlock(dev)         mutex_unlock(&(dev)->dsp_mutex)
 43 #define dsp_is_locked(dev)      ((dev)->locked)
 44 #else
 45 #define dsp_lock_init(dev)      do {} while (0)
 46 #define dsp_lock(dev)           do {} while (0)
 47 #define dsp_unlock(dev)         do {} while (0)
 48 #define dsp_is_locked(dev)      0
 49 #endif
 50 
 51 /*
 52  * AZX stream operations.
 53  */
 54 
 55 /* start a stream */
 56 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
 57 {
 58         /*
 59          * Before stream start, initialize parameter
 60          */
 61         azx_dev->insufficient = 1;
 62 
 63         /* enable SIE */
 64         azx_writel(chip, INTCTL,
 65                    azx_readl(chip, INTCTL) | (1 << azx_dev->index));
 66         /* set DMA start and interrupt mask */
 67         azx_sd_writeb(chip, azx_dev, SD_CTL,
 68                       azx_sd_readb(chip, azx_dev, SD_CTL) |
 69                       SD_CTL_DMA_START | SD_INT_MASK);
 70 }
 71 
 72 /* stop DMA */
 73 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
 74 {
 75         azx_sd_writeb(chip, azx_dev, SD_CTL,
 76                       azx_sd_readb(chip, azx_dev, SD_CTL) &
 77                       ~(SD_CTL_DMA_START | SD_INT_MASK));
 78         azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
 79 }
 80 
 81 /* stop a stream */
 82 void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
 83 {
 84         azx_stream_clear(chip, azx_dev);
 85         /* disable SIE */
 86         azx_writel(chip, INTCTL,
 87                    azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
 88 }
 89 EXPORT_SYMBOL_GPL(azx_stream_stop);
 90 
 91 /* reset stream */
 92 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
 93 {
 94         unsigned char val;
 95         int timeout;
 96 
 97         azx_stream_clear(chip, azx_dev);
 98 
 99         azx_sd_writeb(chip, azx_dev, SD_CTL,
100                       azx_sd_readb(chip, azx_dev, SD_CTL) |
101                       SD_CTL_STREAM_RESET);
102         udelay(3);
103         timeout = 300;
104         while (!((val = azx_sd_readb(chip, azx_dev, SD_CTL)) &
105                  SD_CTL_STREAM_RESET) && --timeout)
106                 ;
107         val &= ~SD_CTL_STREAM_RESET;
108         azx_sd_writeb(chip, azx_dev, SD_CTL, val);
109         udelay(3);
110 
111         timeout = 300;
112         /* waiting for hardware to report that the stream is out of reset */
113         while (((val = azx_sd_readb(chip, azx_dev, SD_CTL)) &
114                 SD_CTL_STREAM_RESET) && --timeout)
115                 ;
116 
117         /* reset first position - may not be synced with hw at this time */
118         *azx_dev->posbuf = 0;
119 }
120 
121 /*
122  * set up the SD for streaming
123  */
124 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
125 {
126         unsigned int val;
127         /* make sure the run bit is zero for SD */
128         azx_stream_clear(chip, azx_dev);
129         /* program the stream_tag */
130         val = azx_sd_readl(chip, azx_dev, SD_CTL);
131         val = (val & ~SD_CTL_STREAM_TAG_MASK) |
132                 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
133         if (!azx_snoop(chip))
134                 val |= SD_CTL_TRAFFIC_PRIO;
135         azx_sd_writel(chip, azx_dev, SD_CTL, val);
136 
137         /* program the length of samples in cyclic buffer */
138         azx_sd_writel(chip, azx_dev, SD_CBL, azx_dev->bufsize);
139 
140         /* program the stream format */
141         /* this value needs to be the same as the one programmed */
142         azx_sd_writew(chip, azx_dev, SD_FORMAT, azx_dev->format_val);
143 
144         /* program the stream LVI (last valid index) of the BDL */
145         azx_sd_writew(chip, azx_dev, SD_LVI, azx_dev->frags - 1);
146 
147         /* program the BDL address */
148         /* lower BDL address */
149         azx_sd_writel(chip, azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
150         /* upper BDL address */
151         azx_sd_writel(chip, azx_dev, SD_BDLPU,
152                       upper_32_bits(azx_dev->bdl.addr));
153 
154         /* enable the position buffer */
155         if (chip->position_fix[0] != POS_FIX_LPIB ||
156             chip->position_fix[1] != POS_FIX_LPIB) {
157                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
158                         azx_writel(chip, DPLBASE,
159                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
160         }
161 
162         /* set the interrupt enable bits in the descriptor control register */
163         azx_sd_writel(chip, azx_dev, SD_CTL,
164                       azx_sd_readl(chip, azx_dev, SD_CTL) | SD_INT_MASK);
165 
166         return 0;
167 }
168 
169 /* assign a stream for the PCM */
170 static inline struct azx_dev *
171 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
172 {
173         int dev, i, nums;
174         struct azx_dev *res = NULL;
175         /* make a non-zero unique key for the substream */
176         int key = (substream->pcm->device << 16) | (substream->number << 2) |
177                 (substream->stream + 1);
178 
179         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
180                 dev = chip->playback_index_offset;
181                 nums = chip->playback_streams;
182         } else {
183                 dev = chip->capture_index_offset;
184                 nums = chip->capture_streams;
185         }
186         for (i = 0; i < nums; i++, dev++) {
187                 struct azx_dev *azx_dev = &chip->azx_dev[dev];
188                 dsp_lock(azx_dev);
189                 if (!azx_dev->opened && !dsp_is_locked(azx_dev)) {
190                         if (azx_dev->assigned_key == key) {
191                                 azx_dev->opened = 1;
192                                 azx_dev->assigned_key = key;
193                                 dsp_unlock(azx_dev);
194                                 return azx_dev;
195                         }
196                         if (!res ||
197                             (chip->driver_caps & AZX_DCAPS_REVERSE_ASSIGN))
198                                 res = azx_dev;
199                 }
200                 dsp_unlock(azx_dev);
201         }
202         if (res) {
203                 dsp_lock(res);
204                 res->opened = 1;
205                 res->assigned_key = key;
206                 dsp_unlock(res);
207         }
208         return res;
209 }
210 
211 /* release the assigned stream */
212 static inline void azx_release_device(struct azx_dev *azx_dev)
213 {
214         azx_dev->opened = 0;
215 }
216 
217 static cycle_t azx_cc_read(const struct cyclecounter *cc)
218 {
219         struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc);
220         struct snd_pcm_substream *substream = azx_dev->substream;
221         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
222         struct azx *chip = apcm->chip;
223 
224         return azx_readl(chip, WALLCLK);
225 }
226 
227 static void azx_timecounter_init(struct snd_pcm_substream *substream,
228                                 bool force, cycle_t last)
229 {
230         struct azx_dev *azx_dev = get_azx_dev(substream);
231         struct timecounter *tc = &azx_dev->azx_tc;
232         struct cyclecounter *cc = &azx_dev->azx_cc;
233         u64 nsec;
234 
235         cc->read = azx_cc_read;
236         cc->mask = CLOCKSOURCE_MASK(32);
237 
238         /*
239          * Converting from 24 MHz to ns means applying a 125/3 factor.
240          * To avoid any saturation issues in intermediate operations,
241          * the 125 factor is applied first. The division is applied
242          * last after reading the timecounter value.
243          * Applying the 1/3 factor as part of the multiplication
244          * requires at least 20 bits for a decent precision, however
245          * overflows occur after about 4 hours or less, not a option.
246          */
247 
248         cc->mult = 125; /* saturation after 195 years */
249         cc->shift = 0;
250 
251         nsec = 0; /* audio time is elapsed time since trigger */
252         timecounter_init(tc, cc, nsec);
253         if (force)
254                 /*
255                  * force timecounter to use predefined value,
256                  * used for synchronized starts
257                  */
258                 tc->cycle_last = last;
259 }
260 
261 static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream,
262                                 u64 nsec)
263 {
264         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
265         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
266         u64 codec_frames, codec_nsecs;
267 
268         if (!hinfo->ops.get_delay)
269                 return nsec;
270 
271         codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream);
272         codec_nsecs = div_u64(codec_frames * 1000000000LL,
273                               substream->runtime->rate);
274 
275         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
276                 return nsec + codec_nsecs;
277 
278         return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
279 }
280 
281 /*
282  * set up a BDL entry
283  */
284 static int setup_bdle(struct azx *chip,
285                       struct snd_dma_buffer *dmab,
286                       struct azx_dev *azx_dev, u32 **bdlp,
287                       int ofs, int size, int with_ioc)
288 {
289         u32 *bdl = *bdlp;
290 
291         while (size > 0) {
292                 dma_addr_t addr;
293                 int chunk;
294 
295                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
296                         return -EINVAL;
297 
298                 addr = snd_sgbuf_get_addr(dmab, ofs);
299                 /* program the address field of the BDL entry */
300                 bdl[0] = cpu_to_le32((u32)addr);
301                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
302                 /* program the size field of the BDL entry */
303                 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
304                 /* one BDLE cannot cross 4K boundary on CTHDA chips */
305                 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
306                         u32 remain = 0x1000 - (ofs & 0xfff);
307                         if (chunk > remain)
308                                 chunk = remain;
309                 }
310                 bdl[2] = cpu_to_le32(chunk);
311                 /* program the IOC to enable interrupt
312                  * only when the whole fragment is processed
313                  */
314                 size -= chunk;
315                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
316                 bdl += 4;
317                 azx_dev->frags++;
318                 ofs += chunk;
319         }
320         *bdlp = bdl;
321         return ofs;
322 }
323 
324 /*
325  * set up BDL entries
326  */
327 static int azx_setup_periods(struct azx *chip,
328                              struct snd_pcm_substream *substream,
329                              struct azx_dev *azx_dev)
330 {
331         u32 *bdl;
332         int i, ofs, periods, period_bytes;
333         int pos_adj = 0;
334 
335         /* reset BDL address */
336         azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
337         azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
338 
339         period_bytes = azx_dev->period_bytes;
340         periods = azx_dev->bufsize / period_bytes;
341 
342         /* program the initial BDL entries */
343         bdl = (u32 *)azx_dev->bdl.area;
344         ofs = 0;
345         azx_dev->frags = 0;
346 
347         if (chip->bdl_pos_adj)
348                 pos_adj = chip->bdl_pos_adj[chip->dev_index];
349         if (!azx_dev->no_period_wakeup && pos_adj > 0) {
350                 struct snd_pcm_runtime *runtime = substream->runtime;
351                 int pos_align = pos_adj;
352                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
353                 if (!pos_adj)
354                         pos_adj = pos_align;
355                 else
356                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
357                                 pos_align;
358                 pos_adj = frames_to_bytes(runtime, pos_adj);
359                 if (pos_adj >= period_bytes) {
360                         dev_warn(chip->card->dev,"Too big adjustment %d\n",
361                                  pos_adj);
362                         pos_adj = 0;
363                 } else {
364                         ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
365                                          azx_dev,
366                                          &bdl, ofs, pos_adj, true);
367                         if (ofs < 0)
368                                 goto error;
369                 }
370         } else
371                 pos_adj = 0;
372 
373         for (i = 0; i < periods; i++) {
374                 if (i == periods - 1 && pos_adj)
375                         ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
376                                          azx_dev, &bdl, ofs,
377                                          period_bytes - pos_adj, 0);
378                 else
379                         ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
380                                          azx_dev, &bdl, ofs,
381                                          period_bytes,
382                                          !azx_dev->no_period_wakeup);
383                 if (ofs < 0)
384                         goto error;
385         }
386         return 0;
387 
388  error:
389         dev_err(chip->card->dev, "Too many BDL entries: buffer=%d, period=%d\n",
390                 azx_dev->bufsize, period_bytes);
391         return -EINVAL;
392 }
393 
394 /*
395  * PCM ops
396  */
397 
398 static int azx_pcm_close(struct snd_pcm_substream *substream)
399 {
400         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
401         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
402         struct azx *chip = apcm->chip;
403         struct azx_dev *azx_dev = get_azx_dev(substream);
404         unsigned long flags;
405 
406         mutex_lock(&chip->open_mutex);
407         spin_lock_irqsave(&chip->reg_lock, flags);
408         azx_dev->substream = NULL;
409         azx_dev->running = 0;
410         spin_unlock_irqrestore(&chip->reg_lock, flags);
411         azx_release_device(azx_dev);
412         hinfo->ops.close(hinfo, apcm->codec, substream);
413         snd_hda_power_down(apcm->codec);
414         mutex_unlock(&chip->open_mutex);
415         return 0;
416 }
417 
418 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
419                              struct snd_pcm_hw_params *hw_params)
420 {
421         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
422         struct azx *chip = apcm->chip;
423         int ret;
424 
425         dsp_lock(get_azx_dev(substream));
426         if (dsp_is_locked(get_azx_dev(substream))) {
427                 ret = -EBUSY;
428                 goto unlock;
429         }
430 
431         ret = chip->ops->substream_alloc_pages(chip, substream,
432                                           params_buffer_bytes(hw_params));
433 unlock:
434         dsp_unlock(get_azx_dev(substream));
435         return ret;
436 }
437 
438 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
439 {
440         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
441         struct azx_dev *azx_dev = get_azx_dev(substream);
442         struct azx *chip = apcm->chip;
443         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
444         int err;
445 
446         /* reset BDL address */
447         dsp_lock(azx_dev);
448         if (!dsp_is_locked(azx_dev)) {
449                 azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
450                 azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
451                 azx_sd_writel(chip, azx_dev, SD_CTL, 0);
452                 azx_dev->bufsize = 0;
453                 azx_dev->period_bytes = 0;
454                 azx_dev->format_val = 0;
455         }
456 
457         snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
458 
459         err = chip->ops->substream_free_pages(chip, substream);
460         azx_dev->prepared = 0;
461         dsp_unlock(azx_dev);
462         return err;
463 }
464 
465 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
466 {
467         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
468         struct azx *chip = apcm->chip;
469         struct azx_dev *azx_dev = get_azx_dev(substream);
470         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
471         struct snd_pcm_runtime *runtime = substream->runtime;
472         unsigned int bufsize, period_bytes, format_val, stream_tag;
473         int err;
474         struct hda_spdif_out *spdif =
475                 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
476         unsigned short ctls = spdif ? spdif->ctls : 0;
477 
478         dsp_lock(azx_dev);
479         if (dsp_is_locked(azx_dev)) {
480                 err = -EBUSY;
481                 goto unlock;
482         }
483 
484         azx_stream_reset(chip, azx_dev);
485         format_val = snd_hda_calc_stream_format(runtime->rate,
486                                                 runtime->channels,
487                                                 runtime->format,
488                                                 hinfo->maxbps,
489                                                 ctls);
490         if (!format_val) {
491                 dev_err(chip->card->dev,
492                         "invalid format_val, rate=%d, ch=%d, format=%d\n",
493                         runtime->rate, runtime->channels, runtime->format);
494                 err = -EINVAL;
495                 goto unlock;
496         }
497 
498         bufsize = snd_pcm_lib_buffer_bytes(substream);
499         period_bytes = snd_pcm_lib_period_bytes(substream);
500 
501         dev_dbg(chip->card->dev, "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
502                 bufsize, format_val);
503 
504         if (bufsize != azx_dev->bufsize ||
505             period_bytes != azx_dev->period_bytes ||
506             format_val != azx_dev->format_val ||
507             runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
508                 azx_dev->bufsize = bufsize;
509                 azx_dev->period_bytes = period_bytes;
510                 azx_dev->format_val = format_val;
511                 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
512                 err = azx_setup_periods(chip, substream, azx_dev);
513                 if (err < 0)
514                         goto unlock;
515         }
516 
517         /* when LPIB delay correction gives a small negative value,
518          * we ignore it; currently set the threshold statically to
519          * 64 frames
520          */
521         if (runtime->period_size > 64)
522                 azx_dev->delay_negative_threshold = -frames_to_bytes(runtime, 64);
523         else
524                 azx_dev->delay_negative_threshold = 0;
525 
526         /* wallclk has 24Mhz clock source */
527         azx_dev->period_wallclk = (((runtime->period_size * 24000) /
528                                                 runtime->rate) * 1000);
529         azx_setup_controller(chip, azx_dev);
530         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
531                 azx_dev->fifo_size =
532                         azx_sd_readw(chip, azx_dev, SD_FIFOSIZE) + 1;
533         else
534                 azx_dev->fifo_size = 0;
535 
536         stream_tag = azx_dev->stream_tag;
537         /* CA-IBG chips need the playback stream starting from 1 */
538         if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
539             stream_tag > chip->capture_streams)
540                 stream_tag -= chip->capture_streams;
541         err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
542                                      azx_dev->format_val, substream);
543 
544  unlock:
545         if (!err)
546                 azx_dev->prepared = 1;
547         dsp_unlock(azx_dev);
548         return err;
549 }
550 
551 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
552 {
553         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
554         struct azx *chip = apcm->chip;
555         struct azx_dev *azx_dev;
556         struct snd_pcm_substream *s;
557         int rstart = 0, start, nsync = 0, sbits = 0;
558         int nwait, timeout;
559 
560         azx_dev = get_azx_dev(substream);
561         trace_azx_pcm_trigger(chip, azx_dev, cmd);
562 
563         if (dsp_is_locked(azx_dev) || !azx_dev->prepared)
564                 return -EPIPE;
565 
566         switch (cmd) {
567         case SNDRV_PCM_TRIGGER_START:
568                 rstart = 1;
569         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
570         case SNDRV_PCM_TRIGGER_RESUME:
571                 start = 1;
572                 break;
573         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
574         case SNDRV_PCM_TRIGGER_SUSPEND:
575         case SNDRV_PCM_TRIGGER_STOP:
576                 start = 0;
577                 break;
578         default:
579                 return -EINVAL;
580         }
581 
582         snd_pcm_group_for_each_entry(s, substream) {
583                 if (s->pcm->card != substream->pcm->card)
584                         continue;
585                 azx_dev = get_azx_dev(s);
586                 sbits |= 1 << azx_dev->index;
587                 nsync++;
588                 snd_pcm_trigger_done(s, substream);
589         }
590 
591         spin_lock(&chip->reg_lock);
592 
593         /* first, set SYNC bits of corresponding streams */
594         if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
595                 azx_writel(chip, OLD_SSYNC,
596                         azx_readl(chip, OLD_SSYNC) | sbits);
597         else
598                 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
599 
600         snd_pcm_group_for_each_entry(s, substream) {
601                 if (s->pcm->card != substream->pcm->card)
602                         continue;
603                 azx_dev = get_azx_dev(s);
604                 if (start) {
605                         azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
606                         if (!rstart)
607                                 azx_dev->start_wallclk -=
608                                                 azx_dev->period_wallclk;
609                         azx_stream_start(chip, azx_dev);
610                 } else {
611                         azx_stream_stop(chip, azx_dev);
612                 }
613                 azx_dev->running = start;
614         }
615         spin_unlock(&chip->reg_lock);
616         if (start) {
617                 /* wait until all FIFOs get ready */
618                 for (timeout = 5000; timeout; timeout--) {
619                         nwait = 0;
620                         snd_pcm_group_for_each_entry(s, substream) {
621                                 if (s->pcm->card != substream->pcm->card)
622                                         continue;
623                                 azx_dev = get_azx_dev(s);
624                                 if (!(azx_sd_readb(chip, azx_dev, SD_STS) &
625                                       SD_STS_FIFO_READY))
626                                         nwait++;
627                         }
628                         if (!nwait)
629                                 break;
630                         cpu_relax();
631                 }
632         } else {
633                 /* wait until all RUN bits are cleared */
634                 for (timeout = 5000; timeout; timeout--) {
635                         nwait = 0;
636                         snd_pcm_group_for_each_entry(s, substream) {
637                                 if (s->pcm->card != substream->pcm->card)
638                                         continue;
639                                 azx_dev = get_azx_dev(s);
640                                 if (azx_sd_readb(chip, azx_dev, SD_CTL) &
641                                     SD_CTL_DMA_START)
642                                         nwait++;
643                         }
644                         if (!nwait)
645                                 break;
646                         cpu_relax();
647                 }
648         }
649         spin_lock(&chip->reg_lock);
650         /* reset SYNC bits */
651         if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
652                 azx_writel(chip, OLD_SSYNC,
653                         azx_readl(chip, OLD_SSYNC) & ~sbits);
654         else
655                 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
656         if (start) {
657                 azx_timecounter_init(substream, 0, 0);
658                 if (nsync > 1) {
659                         cycle_t cycle_last;
660 
661                         /* same start cycle for master and group */
662                         azx_dev = get_azx_dev(substream);
663                         cycle_last = azx_dev->azx_tc.cycle_last;
664 
665                         snd_pcm_group_for_each_entry(s, substream) {
666                                 if (s->pcm->card != substream->pcm->card)
667                                         continue;
668                                 azx_timecounter_init(s, 1, cycle_last);
669                         }
670                 }
671         }
672         spin_unlock(&chip->reg_lock);
673         return 0;
674 }
675 
676 /* get the current DMA position with correction on VIA chips */
677 static unsigned int azx_via_get_position(struct azx *chip,
678                                          struct azx_dev *azx_dev)
679 {
680         unsigned int link_pos, mini_pos, bound_pos;
681         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
682         unsigned int fifo_size;
683 
684         link_pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
685         if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
686                 /* Playback, no problem using link position */
687                 return link_pos;
688         }
689 
690         /* Capture */
691         /* For new chipset,
692          * use mod to get the DMA position just like old chipset
693          */
694         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
695         mod_dma_pos %= azx_dev->period_bytes;
696 
697         /* azx_dev->fifo_size can't get FIFO size of in stream.
698          * Get from base address + offset.
699          */
700         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
701 
702         if (azx_dev->insufficient) {
703                 /* Link position never gather than FIFO size */
704                 if (link_pos <= fifo_size)
705                         return 0;
706 
707                 azx_dev->insufficient = 0;
708         }
709 
710         if (link_pos <= fifo_size)
711                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
712         else
713                 mini_pos = link_pos - fifo_size;
714 
715         /* Find nearest previous boudary */
716         mod_mini_pos = mini_pos % azx_dev->period_bytes;
717         mod_link_pos = link_pos % azx_dev->period_bytes;
718         if (mod_link_pos >= fifo_size)
719                 bound_pos = link_pos - mod_link_pos;
720         else if (mod_dma_pos >= mod_mini_pos)
721                 bound_pos = mini_pos - mod_mini_pos;
722         else {
723                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
724                 if (bound_pos >= azx_dev->bufsize)
725                         bound_pos = 0;
726         }
727 
728         /* Calculate real DMA position we want */
729         return bound_pos + mod_dma_pos;
730 }
731 
732 unsigned int azx_get_position(struct azx *chip,
733                               struct azx_dev *azx_dev,
734                               bool with_check)
735 {
736         struct snd_pcm_substream *substream = azx_dev->substream;
737         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
738         unsigned int pos;
739         int stream = substream->stream;
740         struct hda_pcm_stream *hinfo = apcm->hinfo[stream];
741         int delay = 0;
742 
743         switch (chip->position_fix[stream]) {
744         case POS_FIX_LPIB:
745                 /* read LPIB */
746                 pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
747                 break;
748         case POS_FIX_VIACOMBO:
749                 pos = azx_via_get_position(chip, azx_dev);
750                 break;
751         default:
752                 /* use the position buffer */
753                 pos = le32_to_cpu(*azx_dev->posbuf);
754                 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
755                         if (!pos || pos == (u32)-1) {
756                                 dev_info(chip->card->dev,
757                                          "Invalid position buffer, using LPIB read method instead.\n");
758                                 chip->position_fix[stream] = POS_FIX_LPIB;
759                                 pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
760                         } else
761                                 chip->position_fix[stream] = POS_FIX_POSBUF;
762                 }
763                 break;
764         }
765 
766         if (pos >= azx_dev->bufsize)
767                 pos = 0;
768 
769         /* calculate runtime delay from LPIB */
770         if (substream->runtime &&
771             chip->position_fix[stream] == POS_FIX_POSBUF &&
772             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
773                 unsigned int lpib_pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
774                 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
775                         delay = pos - lpib_pos;
776                 else
777                         delay = lpib_pos - pos;
778                 if (delay < 0) {
779                         if (delay >= azx_dev->delay_negative_threshold)
780                                 delay = 0;
781                         else
782                                 delay += azx_dev->bufsize;
783                 }
784                 if (delay >= azx_dev->period_bytes) {
785                         dev_info(chip->card->dev,
786                                  "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
787                                  delay, azx_dev->period_bytes);
788                         delay = 0;
789                         chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
790                 }
791                 delay = bytes_to_frames(substream->runtime, delay);
792         }
793 
794         if (substream->runtime) {
795                 if (hinfo->ops.get_delay)
796                         delay += hinfo->ops.get_delay(hinfo, apcm->codec,
797                                                       substream);
798                 substream->runtime->delay = delay;
799         }
800 
801         trace_azx_get_position(chip, azx_dev, pos, delay);
802         return pos;
803 }
804 EXPORT_SYMBOL_GPL(azx_get_position);
805 
806 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
807 {
808         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
809         struct azx *chip = apcm->chip;
810         struct azx_dev *azx_dev = get_azx_dev(substream);
811         return bytes_to_frames(substream->runtime,
812                                azx_get_position(chip, azx_dev, false));
813 }
814 
815 static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream,
816                                 struct timespec *ts)
817 {
818         struct azx_dev *azx_dev = get_azx_dev(substream);
819         u64 nsec;
820 
821         nsec = timecounter_read(&azx_dev->azx_tc);
822         nsec = div_u64(nsec, 3); /* can be optimized */
823         nsec = azx_adjust_codec_delay(substream, nsec);
824 
825         *ts = ns_to_timespec(nsec);
826 
827         return 0;
828 }
829 
830 static struct snd_pcm_hardware azx_pcm_hw = {
831         .info =                 (SNDRV_PCM_INFO_MMAP |
832                                  SNDRV_PCM_INFO_INTERLEAVED |
833                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
834                                  SNDRV_PCM_INFO_MMAP_VALID |
835                                  /* No full-resume yet implemented */
836                                  /* SNDRV_PCM_INFO_RESUME |*/
837                                  SNDRV_PCM_INFO_PAUSE |
838                                  SNDRV_PCM_INFO_SYNC_START |
839                                  SNDRV_PCM_INFO_HAS_WALL_CLOCK |
840                                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
841         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
842         .rates =                SNDRV_PCM_RATE_48000,
843         .rate_min =             48000,
844         .rate_max =             48000,
845         .channels_min =         2,
846         .channels_max =         2,
847         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
848         .period_bytes_min =     128,
849         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
850         .periods_min =          2,
851         .periods_max =          AZX_MAX_FRAG,
852         .fifo_size =            0,
853 };
854 
855 static int azx_pcm_open(struct snd_pcm_substream *substream)
856 {
857         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
858         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
859         struct azx *chip = apcm->chip;
860         struct azx_dev *azx_dev;
861         struct snd_pcm_runtime *runtime = substream->runtime;
862         unsigned long flags;
863         int err;
864         int buff_step;
865 
866         mutex_lock(&chip->open_mutex);
867         azx_dev = azx_assign_device(chip, substream);
868         if (azx_dev == NULL) {
869                 mutex_unlock(&chip->open_mutex);
870                 return -EBUSY;
871         }
872         runtime->hw = azx_pcm_hw;
873         runtime->hw.channels_min = hinfo->channels_min;
874         runtime->hw.channels_max = hinfo->channels_max;
875         runtime->hw.formats = hinfo->formats;
876         runtime->hw.rates = hinfo->rates;
877         snd_pcm_limit_hw_rates(runtime);
878         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
879 
880         /* avoid wrap-around with wall-clock */
881         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
882                                      20,
883                                      178000000);
884 
885         if (chip->align_buffer_size)
886                 /* constrain buffer sizes to be multiple of 128
887                    bytes. This is more efficient in terms of memory
888                    access but isn't required by the HDA spec and
889                    prevents users from specifying exact period/buffer
890                    sizes. For example for 44.1kHz, a period size set
891                    to 20ms will be rounded to 19.59ms. */
892                 buff_step = 128;
893         else
894                 /* Don't enforce steps on buffer sizes, still need to
895                    be multiple of 4 bytes (HDA spec). Tested on Intel
896                    HDA controllers, may not work on all devices where
897                    option needs to be disabled */
898                 buff_step = 4;
899 
900         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
901                                    buff_step);
902         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
903                                    buff_step);
904         snd_hda_power_up_d3wait(apcm->codec);
905         err = hinfo->ops.open(hinfo, apcm->codec, substream);
906         if (err < 0) {
907                 azx_release_device(azx_dev);
908                 snd_hda_power_down(apcm->codec);
909                 mutex_unlock(&chip->open_mutex);
910                 return err;
911         }
912         snd_pcm_limit_hw_rates(runtime);
913         /* sanity check */
914         if (snd_BUG_ON(!runtime->hw.channels_min) ||
915             snd_BUG_ON(!runtime->hw.channels_max) ||
916             snd_BUG_ON(!runtime->hw.formats) ||
917             snd_BUG_ON(!runtime->hw.rates)) {
918                 azx_release_device(azx_dev);
919                 hinfo->ops.close(hinfo, apcm->codec, substream);
920                 snd_hda_power_down(apcm->codec);
921                 mutex_unlock(&chip->open_mutex);
922                 return -EINVAL;
923         }
924 
925         /* disable WALLCLOCK timestamps for capture streams
926            until we figure out how to handle digital inputs */
927         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
928                 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK;
929 
930         spin_lock_irqsave(&chip->reg_lock, flags);
931         azx_dev->substream = substream;
932         azx_dev->running = 0;
933         spin_unlock_irqrestore(&chip->reg_lock, flags);
934 
935         runtime->private_data = azx_dev;
936         snd_pcm_set_sync(substream);
937         mutex_unlock(&chip->open_mutex);
938         return 0;
939 }
940 
941 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
942                         struct vm_area_struct *area)
943 {
944         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
945         struct azx *chip = apcm->chip;
946         if (chip->ops->pcm_mmap_prepare)
947                 chip->ops->pcm_mmap_prepare(substream, area);
948         return snd_pcm_lib_default_mmap(substream, area);
949 }
950 
951 static struct snd_pcm_ops azx_pcm_ops = {
952         .open = azx_pcm_open,
953         .close = azx_pcm_close,
954         .ioctl = snd_pcm_lib_ioctl,
955         .hw_params = azx_pcm_hw_params,
956         .hw_free = azx_pcm_hw_free,
957         .prepare = azx_pcm_prepare,
958         .trigger = azx_pcm_trigger,
959         .pointer = azx_pcm_pointer,
960         .wall_clock =  azx_get_wallclock_tstamp,
961         .mmap = azx_pcm_mmap,
962         .page = snd_pcm_sgbuf_ops_page,
963 };
964 
965 static void azx_pcm_free(struct snd_pcm *pcm)
966 {
967         struct azx_pcm *apcm = pcm->private_data;
968         if (apcm) {
969                 list_del(&apcm->list);
970                 kfree(apcm);
971         }
972 }
973 
974 #define MAX_PREALLOC_SIZE       (32 * 1024 * 1024)
975 
976 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
977                                  struct hda_pcm *cpcm)
978 {
979         struct azx *chip = bus->private_data;
980         struct snd_pcm *pcm;
981         struct azx_pcm *apcm;
982         int pcm_dev = cpcm->device;
983         unsigned int size;
984         int s, err;
985 
986         list_for_each_entry(apcm, &chip->pcm_list, list) {
987                 if (apcm->pcm->device == pcm_dev) {
988                         dev_err(chip->card->dev, "PCM %d already exists\n",
989                                 pcm_dev);
990                         return -EBUSY;
991                 }
992         }
993         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
994                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
995                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
996                           &pcm);
997         if (err < 0)
998                 return err;
999         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
1000         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1001         if (apcm == NULL) {
1002                 snd_device_free(chip->card, pcm);
1003                 return -ENOMEM;
1004         }
1005         apcm->chip = chip;
1006         apcm->pcm = pcm;
1007         apcm->codec = codec;
1008         pcm->private_data = apcm;
1009         pcm->private_free = azx_pcm_free;
1010         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
1011                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
1012         list_add_tail(&apcm->list, &chip->pcm_list);
1013         cpcm->pcm = pcm;
1014         for (s = 0; s < 2; s++) {
1015                 apcm->hinfo[s] = &cpcm->stream[s];
1016                 if (cpcm->stream[s].substreams)
1017                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
1018         }
1019         /* buffer pre-allocation */
1020         size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
1021         if (size > MAX_PREALLOC_SIZE)
1022                 size = MAX_PREALLOC_SIZE;
1023         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1024                                               chip->card->dev,
1025                                               size, MAX_PREALLOC_SIZE);
1026         /* link to codec */
1027         pcm->dev = &codec->dev;
1028         return 0;
1029 }
1030 
1031 /*
1032  * CORB / RIRB interface
1033  */
1034 static int azx_alloc_cmd_io(struct azx *chip)
1035 {
1036         int err;
1037 
1038         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
1039         err = chip->ops->dma_alloc_pages(chip, SNDRV_DMA_TYPE_DEV,
1040                                          PAGE_SIZE, &chip->rb);
1041         if (err < 0)
1042                 dev_err(chip->card->dev, "cannot allocate CORB/RIRB\n");
1043         return err;
1044 }
1045 
1046 static void azx_init_cmd_io(struct azx *chip)
1047 {
1048         int timeout;
1049 
1050         spin_lock_irq(&chip->reg_lock);
1051         /* CORB set up */
1052         chip->corb.addr = chip->rb.addr;
1053         chip->corb.buf = (u32 *)chip->rb.area;
1054         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
1055         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
1056 
1057         /* set the corb size to 256 entries (ULI requires explicitly) */
1058         azx_writeb(chip, CORBSIZE, 0x02);
1059         /* set the corb write pointer to 0 */
1060         azx_writew(chip, CORBWP, 0);
1061 
1062         /* reset the corb hw read pointer */
1063         azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
1064         if (!(chip->driver_caps & AZX_DCAPS_CORBRP_SELF_CLEAR)) {
1065                 for (timeout = 1000; timeout > 0; timeout--) {
1066                         if ((azx_readw(chip, CORBRP) & ICH6_CORBRP_RST) == ICH6_CORBRP_RST)
1067                                 break;
1068                         udelay(1);
1069                 }
1070                 if (timeout <= 0)
1071                         dev_err(chip->card->dev, "CORB reset timeout#1, CORBRP = %d\n",
1072                                 azx_readw(chip, CORBRP));
1073 
1074                 azx_writew(chip, CORBRP, 0);
1075                 for (timeout = 1000; timeout > 0; timeout--) {
1076                         if (azx_readw(chip, CORBRP) == 0)
1077                                 break;
1078                         udelay(1);
1079                 }
1080                 if (timeout <= 0)
1081                         dev_err(chip->card->dev, "CORB reset timeout#2, CORBRP = %d\n",
1082                                 azx_readw(chip, CORBRP));
1083         }
1084 
1085         /* enable corb dma */
1086         azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
1087 
1088         /* RIRB set up */
1089         chip->rirb.addr = chip->rb.addr + 2048;
1090         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
1091         chip->rirb.wp = chip->rirb.rp = 0;
1092         memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
1093         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
1094         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
1095 
1096         /* set the rirb size to 256 entries (ULI requires explicitly) */
1097         azx_writeb(chip, RIRBSIZE, 0x02);
1098         /* reset the rirb hw write pointer */
1099         azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
1100         /* set N=1, get RIRB response interrupt for new entry */
1101         if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
1102                 azx_writew(chip, RINTCNT, 0xc0);
1103         else
1104                 azx_writew(chip, RINTCNT, 1);
1105         /* enable rirb dma and response irq */
1106         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
1107         spin_unlock_irq(&chip->reg_lock);
1108 }
1109 
1110 static void azx_free_cmd_io(struct azx *chip)
1111 {
1112         spin_lock_irq(&chip->reg_lock);
1113         /* disable ringbuffer DMAs */
1114         azx_writeb(chip, RIRBCTL, 0);
1115         azx_writeb(chip, CORBCTL, 0);
1116         spin_unlock_irq(&chip->reg_lock);
1117 }
1118 
1119 static unsigned int azx_command_addr(u32 cmd)
1120 {
1121         unsigned int addr = cmd >> 28;
1122 
1123         if (addr >= AZX_MAX_CODECS) {
1124                 snd_BUG();
1125                 addr = 0;
1126         }
1127 
1128         return addr;
1129 }
1130 
1131 /* send a command */
1132 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
1133 {
1134         struct azx *chip = bus->private_data;
1135         unsigned int addr = azx_command_addr(val);
1136         unsigned int wp, rp;
1137 
1138         spin_lock_irq(&chip->reg_lock);
1139 
1140         /* add command to corb */
1141         wp = azx_readw(chip, CORBWP);
1142         if (wp == 0xffff) {
1143                 /* something wrong, controller likely turned to D3 */
1144                 spin_unlock_irq(&chip->reg_lock);
1145                 return -EIO;
1146         }
1147         wp++;
1148         wp %= ICH6_MAX_CORB_ENTRIES;
1149 
1150         rp = azx_readw(chip, CORBRP);
1151         if (wp == rp) {
1152                 /* oops, it's full */
1153                 spin_unlock_irq(&chip->reg_lock);
1154                 return -EAGAIN;
1155         }
1156 
1157         chip->rirb.cmds[addr]++;
1158         chip->corb.buf[wp] = cpu_to_le32(val);
1159         azx_writew(chip, CORBWP, wp);
1160 
1161         spin_unlock_irq(&chip->reg_lock);
1162 
1163         return 0;
1164 }
1165 
1166 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
1167 
1168 /* retrieve RIRB entry - called from interrupt handler */
1169 static void azx_update_rirb(struct azx *chip)
1170 {
1171         unsigned int rp, wp;
1172         unsigned int addr;
1173         u32 res, res_ex;
1174 
1175         wp = azx_readw(chip, RIRBWP);
1176         if (wp == 0xffff) {
1177                 /* something wrong, controller likely turned to D3 */
1178                 return;
1179         }
1180 
1181         if (wp == chip->rirb.wp)
1182                 return;
1183         chip->rirb.wp = wp;
1184 
1185         while (chip->rirb.rp != wp) {
1186                 chip->rirb.rp++;
1187                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
1188 
1189                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
1190                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
1191                 res = le32_to_cpu(chip->rirb.buf[rp]);
1192                 addr = res_ex & 0xf;
1193                 if ((addr >= AZX_MAX_CODECS) || !(chip->codec_mask & (1 << addr))) {
1194                         dev_err(chip->card->dev, "spurious response %#x:%#x, rp = %d, wp = %d",
1195                                 res, res_ex,
1196                                 chip->rirb.rp, wp);
1197                         snd_BUG();
1198                 }
1199                 else if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
1200                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
1201                 else if (chip->rirb.cmds[addr]) {
1202                         chip->rirb.res[addr] = res;
1203                         smp_wmb();
1204                         chip->rirb.cmds[addr]--;
1205                 } else if (printk_ratelimit()) {
1206                         dev_err(chip->card->dev, "spurious response %#x:%#x, last cmd=%#08x\n",
1207                                 res, res_ex,
1208                                 chip->last_cmd[addr]);
1209                 }
1210         }
1211 }
1212 
1213 /* receive a response */
1214 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
1215                                           unsigned int addr)
1216 {
1217         struct azx *chip = bus->private_data;
1218         unsigned long timeout;
1219         unsigned long loopcounter;
1220         int do_poll = 0;
1221 
1222  again:
1223         timeout = jiffies + msecs_to_jiffies(1000);
1224 
1225         for (loopcounter = 0;; loopcounter++) {
1226                 if (chip->polling_mode || do_poll) {
1227                         spin_lock_irq(&chip->reg_lock);
1228                         azx_update_rirb(chip);
1229                         spin_unlock_irq(&chip->reg_lock);
1230                 }
1231                 if (!chip->rirb.cmds[addr]) {
1232                         smp_rmb();
1233                         bus->rirb_error = 0;
1234 
1235                         if (!do_poll)
1236                                 chip->poll_count = 0;
1237                         return chip->rirb.res[addr]; /* the last value */
1238                 }
1239                 if (time_after(jiffies, timeout))
1240                         break;
1241                 if (bus->needs_damn_long_delay || loopcounter > 3000)
1242                         msleep(2); /* temporary workaround */
1243                 else {
1244                         udelay(10);
1245                         cond_resched();
1246                 }
1247         }
1248 
1249         if (bus->no_response_fallback)
1250                 return -1;
1251 
1252         if (!chip->polling_mode && chip->poll_count < 2) {
1253                 dev_dbg(chip->card->dev,
1254                         "azx_get_response timeout, polling the codec once: last cmd=0x%08x\n",
1255                         chip->last_cmd[addr]);
1256                 do_poll = 1;
1257                 chip->poll_count++;
1258                 goto again;
1259         }
1260 
1261 
1262         if (!chip->polling_mode) {
1263                 dev_warn(chip->card->dev,
1264                          "azx_get_response timeout, switching to polling mode: last cmd=0x%08x\n",
1265                          chip->last_cmd[addr]);
1266                 chip->polling_mode = 1;
1267                 goto again;
1268         }
1269 
1270         if (chip->msi) {
1271                 dev_warn(chip->card->dev,
1272                          "No response from codec, disabling MSI: last cmd=0x%08x\n",
1273                          chip->last_cmd[addr]);
1274                 if (chip->ops->disable_msi_reset_irq(chip) &&
1275                     chip->ops->disable_msi_reset_irq(chip) < 0) {
1276                         bus->rirb_error = 1;
1277                         return -1;
1278                 }
1279                 goto again;
1280         }
1281 
1282         if (chip->probing) {
1283                 /* If this critical timeout happens during the codec probing
1284                  * phase, this is likely an access to a non-existing codec
1285                  * slot.  Better to return an error and reset the system.
1286                  */
1287                 return -1;
1288         }
1289 
1290         /* a fatal communication error; need either to reset or to fallback
1291          * to the single_cmd mode
1292          */
1293         bus->rirb_error = 1;
1294         if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
1295                 bus->response_reset = 1;
1296                 return -1; /* give a chance to retry */
1297         }
1298 
1299         dev_err(chip->card->dev,
1300                 "azx_get_response timeout, switching to single_cmd mode: last cmd=0x%08x\n",
1301                 chip->last_cmd[addr]);
1302         chip->single_cmd = 1;
1303         bus->response_reset = 0;
1304         /* release CORB/RIRB */
1305         azx_free_cmd_io(chip);
1306         /* disable unsolicited responses */
1307         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
1308         return -1;
1309 }
1310 
1311 /*
1312  * Use the single immediate command instead of CORB/RIRB for simplicity
1313  *
1314  * Note: according to Intel, this is not preferred use.  The command was
1315  *       intended for the BIOS only, and may get confused with unsolicited
1316  *       responses.  So, we shouldn't use it for normal operation from the
1317  *       driver.
1318  *       I left the codes, however, for debugging/testing purposes.
1319  */
1320 
1321 /* receive a response */
1322 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
1323 {
1324         int timeout = 50;
1325 
1326         while (timeout--) {
1327                 /* check IRV busy bit */
1328                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
1329                         /* reuse rirb.res as the response return value */
1330                         chip->rirb.res[addr] = azx_readl(chip, IR);
1331                         return 0;
1332                 }
1333                 udelay(1);
1334         }
1335         if (printk_ratelimit())
1336                 dev_dbg(chip->card->dev, "get_response timeout: IRS=0x%x\n",
1337                         azx_readw(chip, IRS));
1338         chip->rirb.res[addr] = -1;
1339         return -EIO;
1340 }
1341 
1342 /* send a command */
1343 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1344 {
1345         struct azx *chip = bus->private_data;
1346         unsigned int addr = azx_command_addr(val);
1347         int timeout = 50;
1348 
1349         bus->rirb_error = 0;
1350         while (timeout--) {
1351                 /* check ICB busy bit */
1352                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1353                         /* Clear IRV valid bit */
1354                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
1355                                    ICH6_IRS_VALID);
1356                         azx_writel(chip, IC, val);
1357                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
1358                                    ICH6_IRS_BUSY);
1359                         return azx_single_wait_for_response(chip, addr);
1360                 }
1361                 udelay(1);
1362         }
1363         if (printk_ratelimit())
1364                 dev_dbg(chip->card->dev,
1365                         "send_cmd timeout: IRS=0x%x, val=0x%x\n",
1366                         azx_readw(chip, IRS), val);
1367         return -EIO;
1368 }
1369 
1370 /* receive a response */
1371 static unsigned int azx_single_get_response(struct hda_bus *bus,
1372                                             unsigned int addr)
1373 {
1374         struct azx *chip = bus->private_data;
1375         return chip->rirb.res[addr];
1376 }
1377 
1378 /*
1379  * The below are the main callbacks from hda_codec.
1380  *
1381  * They are just the skeleton to call sub-callbacks according to the
1382  * current setting of chip->single_cmd.
1383  */
1384 
1385 /* send a command */
1386 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
1387 {
1388         struct azx *chip = bus->private_data;
1389 
1390         if (chip->disabled)
1391                 return 0;
1392         chip->last_cmd[azx_command_addr(val)] = val;
1393         if (chip->single_cmd)
1394                 return azx_single_send_cmd(bus, val);
1395         else
1396                 return azx_corb_send_cmd(bus, val);
1397 }
1398 
1399 /* get a response */
1400 static unsigned int azx_get_response(struct hda_bus *bus,
1401                                      unsigned int addr)
1402 {
1403         struct azx *chip = bus->private_data;
1404         if (chip->disabled)
1405                 return 0;
1406         if (chip->single_cmd)
1407                 return azx_single_get_response(bus, addr);
1408         else
1409                 return azx_rirb_get_response(bus, addr);
1410 }
1411 
1412 #ifdef CONFIG_SND_HDA_DSP_LOADER
1413 /*
1414  * DSP loading code (e.g. for CA0132)
1415  */
1416 
1417 /* use the first stream for loading DSP */
1418 static struct azx_dev *
1419 azx_get_dsp_loader_dev(struct azx *chip)
1420 {
1421         return &chip->azx_dev[chip->playback_index_offset];
1422 }
1423 
1424 static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
1425                                 unsigned int byte_size,
1426                                 struct snd_dma_buffer *bufp)
1427 {
1428         u32 *bdl;
1429         struct azx *chip = bus->private_data;
1430         struct azx_dev *azx_dev;
1431         int err;
1432 
1433         azx_dev = azx_get_dsp_loader_dev(chip);
1434 
1435         dsp_lock(azx_dev);
1436         spin_lock_irq(&chip->reg_lock);
1437         if (azx_dev->running || azx_dev->locked) {
1438                 spin_unlock_irq(&chip->reg_lock);
1439                 err = -EBUSY;
1440                 goto unlock;
1441         }
1442         azx_dev->prepared = 0;
1443         chip->saved_azx_dev = *azx_dev;
1444         azx_dev->locked = 1;
1445         spin_unlock_irq(&chip->reg_lock);
1446 
1447         err = chip->ops->dma_alloc_pages(chip, SNDRV_DMA_TYPE_DEV_SG,
1448                                          byte_size, bufp);
1449         if (err < 0)
1450                 goto err_alloc;
1451 
1452         azx_dev->bufsize = byte_size;
1453         azx_dev->period_bytes = byte_size;
1454         azx_dev->format_val = format;
1455 
1456         azx_stream_reset(chip, azx_dev);
1457 
1458         /* reset BDL address */
1459         azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
1460         azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
1461 
1462         azx_dev->frags = 0;
1463         bdl = (u32 *)azx_dev->bdl.area;
1464         err = setup_bdle(chip, bufp, azx_dev, &bdl, 0, byte_size, 0);
1465         if (err < 0)
1466                 goto error;
1467 
1468         azx_setup_controller(chip, azx_dev);
1469         dsp_unlock(azx_dev);
1470         return azx_dev->stream_tag;
1471 
1472  error:
1473         chip->ops->dma_free_pages(chip, bufp);
1474  err_alloc:
1475         spin_lock_irq(&chip->reg_lock);
1476         if (azx_dev->opened)
1477                 *azx_dev = chip->saved_azx_dev;
1478         azx_dev->locked = 0;
1479         spin_unlock_irq(&chip->reg_lock);
1480  unlock:
1481         dsp_unlock(azx_dev);
1482         return err;
1483 }
1484 
1485 static void azx_load_dsp_trigger(struct hda_bus *bus, bool start)
1486 {
1487         struct azx *chip = bus->private_data;
1488         struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
1489 
1490         if (start)
1491                 azx_stream_start(chip, azx_dev);
1492         else
1493                 azx_stream_stop(chip, azx_dev);
1494         azx_dev->running = start;
1495 }
1496 
1497 static void azx_load_dsp_cleanup(struct hda_bus *bus,
1498                                  struct snd_dma_buffer *dmab)
1499 {
1500         struct azx *chip = bus->private_data;
1501         struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
1502 
1503         if (!dmab->area || !azx_dev->locked)
1504                 return;
1505 
1506         dsp_lock(azx_dev);
1507         /* reset BDL address */
1508         azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
1509         azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
1510         azx_sd_writel(chip, azx_dev, SD_CTL, 0);
1511         azx_dev->bufsize = 0;
1512         azx_dev->period_bytes = 0;
1513         azx_dev->format_val = 0;
1514 
1515         chip->ops->dma_free_pages(chip, dmab);
1516         dmab->area = NULL;
1517 
1518         spin_lock_irq(&chip->reg_lock);
1519         if (azx_dev->opened)
1520                 *azx_dev = chip->saved_azx_dev;
1521         azx_dev->locked = 0;
1522         spin_unlock_irq(&chip->reg_lock);
1523         dsp_unlock(azx_dev);
1524 }
1525 #endif /* CONFIG_SND_HDA_DSP_LOADER */
1526 
1527 int azx_alloc_stream_pages(struct azx *chip)
1528 {
1529         int i, err;
1530         struct snd_card *card = chip->card;
1531 
1532         for (i = 0; i < chip->num_streams; i++) {
1533                 dsp_lock_init(&chip->azx_dev[i]);
1534                 /* allocate memory for the BDL for each stream */
1535                 err = chip->ops->dma_alloc_pages(chip, SNDRV_DMA_TYPE_DEV,
1536                                                  BDL_SIZE,
1537                                                  &chip->azx_dev[i].bdl);
1538                 if (err < 0) {
1539                         dev_err(card->dev, "cannot allocate BDL\n");
1540                         return -ENOMEM;
1541                 }
1542         }
1543         /* allocate memory for the position buffer */
1544         err = chip->ops->dma_alloc_pages(chip, SNDRV_DMA_TYPE_DEV,
1545                                          chip->num_streams * 8, &chip->posbuf);
1546         if (err < 0) {
1547                 dev_err(card->dev, "cannot allocate posbuf\n");
1548                 return -ENOMEM;
1549         }
1550 
1551         /* allocate CORB/RIRB */
1552         err = azx_alloc_cmd_io(chip);
1553         if (err < 0)
1554                 return err;
1555         return 0;
1556 }
1557 EXPORT_SYMBOL_GPL(azx_alloc_stream_pages);
1558 
1559 void azx_free_stream_pages(struct azx *chip)
1560 {
1561         int i;
1562         if (chip->azx_dev) {
1563                 for (i = 0; i < chip->num_streams; i++)
1564                         if (chip->azx_dev[i].bdl.area)
1565                                 chip->ops->dma_free_pages(
1566                                         chip, &chip->azx_dev[i].bdl);
1567         }
1568         if (chip->rb.area)
1569                 chip->ops->dma_free_pages(chip, &chip->rb);
1570         if (chip->posbuf.area)
1571                 chip->ops->dma_free_pages(chip, &chip->posbuf);
1572 }
1573 EXPORT_SYMBOL_GPL(azx_free_stream_pages);
1574 
1575 /*
1576  * Lowlevel interface
1577  */
1578 
1579 /* enter link reset */
1580 void azx_enter_link_reset(struct azx *chip)
1581 {
1582         unsigned long timeout;
1583 
1584         /* reset controller */
1585         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1586 
1587         timeout = jiffies + msecs_to_jiffies(100);
1588         while ((azx_readb(chip, GCTL) & ICH6_GCTL_RESET) &&
1589                         time_before(jiffies, timeout))
1590                 usleep_range(500, 1000);
1591 }
1592 EXPORT_SYMBOL_GPL(azx_enter_link_reset);
1593 
1594 /* exit link reset */
1595 static void azx_exit_link_reset(struct azx *chip)
1596 {
1597         unsigned long timeout;
1598 
1599         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1600 
1601         timeout = jiffies + msecs_to_jiffies(100);
1602         while (!azx_readb(chip, GCTL) &&
1603                         time_before(jiffies, timeout))
1604                 usleep_range(500, 1000);
1605 }
1606 
1607 /* reset codec link */
1608 static int azx_reset(struct azx *chip, bool full_reset)
1609 {
1610         if (!full_reset)
1611                 goto __skip;
1612 
1613         /* clear STATESTS */
1614         azx_writew(chip, STATESTS, STATESTS_INT_MASK);
1615 
1616         /* reset controller */
1617         azx_enter_link_reset(chip);
1618 
1619         /* delay for >= 100us for codec PLL to settle per spec
1620          * Rev 0.9 section 5.5.1
1621          */
1622         usleep_range(500, 1000);
1623 
1624         /* Bring controller out of reset */
1625         azx_exit_link_reset(chip);
1626 
1627         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1628         usleep_range(1000, 1200);
1629 
1630       __skip:
1631         /* check to see if controller is ready */
1632         if (!azx_readb(chip, GCTL)) {
1633                 dev_dbg(chip->card->dev, "azx_reset: controller not ready!\n");
1634                 return -EBUSY;
1635         }
1636 
1637         /* Accept unsolicited responses */
1638         if (!chip->single_cmd)
1639                 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1640                            ICH6_GCTL_UNSOL);
1641 
1642         /* detect codecs */
1643         if (!chip->codec_mask) {
1644                 chip->codec_mask = azx_readw(chip, STATESTS);
1645                 dev_dbg(chip->card->dev, "codec_mask = 0x%x\n",
1646                         chip->codec_mask);
1647         }
1648 
1649         return 0;
1650 }
1651 
1652 /* enable interrupts */
1653 static void azx_int_enable(struct azx *chip)
1654 {
1655         /* enable controller CIE and GIE */
1656         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1657                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1658 }
1659 
1660 /* disable interrupts */
1661 static void azx_int_disable(struct azx *chip)
1662 {
1663         int i;
1664 
1665         /* disable interrupts in stream descriptor */
1666         for (i = 0; i < chip->num_streams; i++) {
1667                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1668                 azx_sd_writeb(chip, azx_dev, SD_CTL,
1669                               azx_sd_readb(chip, azx_dev, SD_CTL) &
1670                                         ~SD_INT_MASK);
1671         }
1672 
1673         /* disable SIE for all streams */
1674         azx_writeb(chip, INTCTL, 0);
1675 
1676         /* disable controller CIE and GIE */
1677         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1678                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1679 }
1680 
1681 /* clear interrupts */
1682 static void azx_int_clear(struct azx *chip)
1683 {
1684         int i;
1685 
1686         /* clear stream status */
1687         for (i = 0; i < chip->num_streams; i++) {
1688                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1689                 azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK);
1690         }
1691 
1692         /* clear STATESTS */
1693         azx_writew(chip, STATESTS, STATESTS_INT_MASK);
1694 
1695         /* clear rirb status */
1696         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1697 
1698         /* clear int status */
1699         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1700 }
1701 
1702 /*
1703  * reset and start the controller registers
1704  */
1705 void azx_init_chip(struct azx *chip, bool full_reset)
1706 {
1707         if (chip->initialized)
1708                 return;
1709 
1710         /* reset controller */
1711         azx_reset(chip, full_reset);
1712 
1713         /* initialize interrupts */
1714         azx_int_clear(chip);
1715         azx_int_enable(chip);
1716 
1717         /* initialize the codec command I/O */
1718         if (!chip->single_cmd)
1719                 azx_init_cmd_io(chip);
1720 
1721         /* program the position buffer */
1722         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1723         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1724 
1725         chip->initialized = 1;
1726 }
1727 EXPORT_SYMBOL_GPL(azx_init_chip);
1728 
1729 void azx_stop_chip(struct azx *chip)
1730 {
1731         if (!chip->initialized)
1732                 return;
1733 
1734         /* disable interrupts */
1735         azx_int_disable(chip);
1736         azx_int_clear(chip);
1737 
1738         /* disable CORB/RIRB */
1739         azx_free_cmd_io(chip);
1740 
1741         /* disable position buffer */
1742         azx_writel(chip, DPLBASE, 0);
1743         azx_writel(chip, DPUBASE, 0);
1744 
1745         chip->initialized = 0;
1746 }
1747 EXPORT_SYMBOL_GPL(azx_stop_chip);
1748 
1749 /*
1750  * interrupt handler
1751  */
1752 irqreturn_t azx_interrupt(int irq, void *dev_id)
1753 {
1754         struct azx *chip = dev_id;
1755         struct azx_dev *azx_dev;
1756         u32 status;
1757         u8 sd_status;
1758         int i;
1759 
1760 #ifdef CONFIG_PM_RUNTIME
1761         if (chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
1762                 if (!pm_runtime_active(chip->card->dev))
1763                         return IRQ_NONE;
1764 #endif
1765 
1766         spin_lock(&chip->reg_lock);
1767 
1768         if (chip->disabled) {
1769                 spin_unlock(&chip->reg_lock);
1770                 return IRQ_NONE;
1771         }
1772 
1773         status = azx_readl(chip, INTSTS);
1774         if (status == 0 || status == 0xffffffff) {
1775                 spin_unlock(&chip->reg_lock);
1776                 return IRQ_NONE;
1777         }
1778 
1779         for (i = 0; i < chip->num_streams; i++) {
1780                 azx_dev = &chip->azx_dev[i];
1781                 if (status & azx_dev->sd_int_sta_mask) {
1782                         sd_status = azx_sd_readb(chip, azx_dev, SD_STS);
1783                         azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK);
1784                         if (!azx_dev->substream || !azx_dev->running ||
1785                             !(sd_status & SD_INT_COMPLETE))
1786                                 continue;
1787                         /* check whether this IRQ is really acceptable */
1788                         if (!chip->ops->position_check ||
1789                             chip->ops->position_check(chip, azx_dev)) {
1790                                 spin_unlock(&chip->reg_lock);
1791                                 snd_pcm_period_elapsed(azx_dev->substream);
1792                                 spin_lock(&chip->reg_lock);
1793                         }
1794                 }
1795         }
1796 
1797         /* clear rirb int */
1798         status = azx_readb(chip, RIRBSTS);
1799         if (status & RIRB_INT_MASK) {
1800                 if (status & RIRB_INT_RESPONSE) {
1801                         if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1802                                 udelay(80);
1803                         azx_update_rirb(chip);
1804                 }
1805                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1806         }
1807 
1808         spin_unlock(&chip->reg_lock);
1809 
1810         return IRQ_HANDLED;
1811 }
1812 EXPORT_SYMBOL_GPL(azx_interrupt);
1813 
1814 /*
1815  * Codec initerface
1816  */
1817 
1818 /*
1819  * Probe the given codec address
1820  */
1821 static int probe_codec(struct azx *chip, int addr)
1822 {
1823         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1824                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1825         unsigned int res;
1826 
1827         mutex_lock(&chip->bus->cmd_mutex);
1828         chip->probing = 1;
1829         azx_send_cmd(chip->bus, cmd);
1830         res = azx_get_response(chip->bus, addr);
1831         chip->probing = 0;
1832         mutex_unlock(&chip->bus->cmd_mutex);
1833         if (res == -1)
1834                 return -EIO;
1835         dev_dbg(chip->card->dev, "codec #%d probed OK\n", addr);
1836         return 0;
1837 }
1838 
1839 static void azx_bus_reset(struct hda_bus *bus)
1840 {
1841         struct azx *chip = bus->private_data;
1842 
1843         bus->in_reset = 1;
1844         azx_stop_chip(chip);
1845         azx_init_chip(chip, true);
1846 #ifdef CONFIG_PM
1847         if (chip->initialized) {
1848                 struct azx_pcm *p;
1849                 list_for_each_entry(p, &chip->pcm_list, list)
1850                         snd_pcm_suspend_all(p->pcm);
1851                 snd_hda_suspend(chip->bus);
1852                 snd_hda_resume(chip->bus);
1853         }
1854 #endif
1855         bus->in_reset = 0;
1856 }
1857 
1858 #ifdef CONFIG_PM
1859 /* power-up/down the controller */
1860 static void azx_power_notify(struct hda_bus *bus, bool power_up)
1861 {
1862         struct azx *chip = bus->private_data;
1863 
1864         if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
1865                 return;
1866 
1867         if (power_up)
1868                 pm_runtime_get_sync(chip->card->dev);
1869         else
1870                 pm_runtime_put_sync(chip->card->dev);
1871 }
1872 #endif
1873 
1874 static int get_jackpoll_interval(struct azx *chip)
1875 {
1876         int i;
1877         unsigned int j;
1878 
1879         if (!chip->jackpoll_ms)
1880                 return 0;
1881 
1882         i = chip->jackpoll_ms[chip->dev_index];
1883         if (i == 0)
1884                 return 0;
1885         if (i < 50 || i > 60000)
1886                 j = 0;
1887         else
1888                 j = msecs_to_jiffies(i);
1889         if (j == 0)
1890                 dev_warn(chip->card->dev,
1891                          "jackpoll_ms value out of range: %d\n", i);
1892         return j;
1893 }
1894 
1895 /* Codec initialization */
1896 int azx_codec_create(struct azx *chip, const char *model,
1897                      unsigned int max_slots,
1898                      int *power_save_to)
1899 {
1900         struct hda_bus_template bus_temp;
1901         int c, codecs, err;
1902 
1903         memset(&bus_temp, 0, sizeof(bus_temp));
1904         bus_temp.private_data = chip;
1905         bus_temp.modelname = model;
1906         bus_temp.pci = chip->pci;
1907         bus_temp.ops.command = azx_send_cmd;
1908         bus_temp.ops.get_response = azx_get_response;
1909         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1910         bus_temp.ops.bus_reset = azx_bus_reset;
1911 #ifdef CONFIG_PM
1912         bus_temp.power_save = power_save_to;
1913         bus_temp.ops.pm_notify = azx_power_notify;
1914 #endif
1915 #ifdef CONFIG_SND_HDA_DSP_LOADER
1916         bus_temp.ops.load_dsp_prepare = azx_load_dsp_prepare;
1917         bus_temp.ops.load_dsp_trigger = azx_load_dsp_trigger;
1918         bus_temp.ops.load_dsp_cleanup = azx_load_dsp_cleanup;
1919 #endif
1920 
1921         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1922         if (err < 0)
1923                 return err;
1924 
1925         if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1926                 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1927                 chip->bus->needs_damn_long_delay = 1;
1928         }
1929 
1930         codecs = 0;
1931         if (!max_slots)
1932                 max_slots = AZX_DEFAULT_CODECS;
1933 
1934         /* First try to probe all given codec slots */
1935         for (c = 0; c < max_slots; c++) {
1936                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1937                         if (probe_codec(chip, c) < 0) {
1938                                 /* Some BIOSen give you wrong codec addresses
1939                                  * that don't exist
1940                                  */
1941                                 dev_warn(chip->card->dev,
1942                                          "Codec #%d probe error; disabling it...\n", c);
1943                                 chip->codec_mask &= ~(1 << c);
1944                                 /* More badly, accessing to a non-existing
1945                                  * codec often screws up the controller chip,
1946                                  * and disturbs the further communications.
1947                                  * Thus if an error occurs during probing,
1948                                  * better to reset the controller chip to
1949                                  * get back to the sanity state.
1950                                  */
1951                                 azx_stop_chip(chip);
1952                                 azx_init_chip(chip, true);
1953                         }
1954                 }
1955         }
1956 
1957         /* AMD chipsets often cause the communication stalls upon certain
1958          * sequence like the pin-detection.  It seems that forcing the synced
1959          * access works around the stall.  Grrr...
1960          */
1961         if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1962                 dev_dbg(chip->card->dev, "Enable sync_write for stable communication\n");
1963                 chip->bus->sync_write = 1;
1964                 chip->bus->allow_bus_reset = 1;
1965         }
1966 
1967         /* Then create codec instances */
1968         for (c = 0; c < max_slots; c++) {
1969                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1970                         struct hda_codec *codec;
1971                         err = snd_hda_codec_new(chip->bus, c, &codec);
1972                         if (err < 0)
1973                                 continue;
1974                         codec->jackpoll_interval = get_jackpoll_interval(chip);
1975                         codec->beep_mode = chip->beep_mode;
1976                         codecs++;
1977                 }
1978         }
1979         if (!codecs) {
1980                 dev_err(chip->card->dev, "no codecs initialized\n");
1981                 return -ENXIO;
1982         }
1983         return 0;
1984 }
1985 EXPORT_SYMBOL_GPL(azx_codec_create);
1986 
1987 /* configure each codec instance */
1988 int azx_codec_configure(struct azx *chip)
1989 {
1990         struct hda_codec *codec;
1991         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1992                 snd_hda_codec_configure(codec);
1993         }
1994         return 0;
1995 }
1996 EXPORT_SYMBOL_GPL(azx_codec_configure);
1997 
1998 /* mixer creation - all stuff is implemented in hda module */
1999 int azx_mixer_create(struct azx *chip)
2000 {
2001         return snd_hda_build_controls(chip->bus);
2002 }
2003 EXPORT_SYMBOL_GPL(azx_mixer_create);
2004 
2005 
2006 /* initialize SD streams */
2007 int azx_init_stream(struct azx *chip)
2008 {
2009         int i;
2010 
2011         /* initialize each stream (aka device)
2012          * assign the starting bdl address to each stream (device)
2013          * and initialize
2014          */
2015         for (i = 0; i < chip->num_streams; i++) {
2016                 struct azx_dev *azx_dev = &chip->azx_dev[i];
2017                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2018                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2019                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2020                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2021                 azx_dev->sd_int_sta_mask = 1 << i;
2022                 /* stream tag: must be non-zero and unique */
2023                 azx_dev->index = i;
2024                 azx_dev->stream_tag = i + 1;
2025         }
2026 
2027         return 0;
2028 }
2029 EXPORT_SYMBOL_GPL(azx_init_stream);
2030 
2031 MODULE_LICENSE("GPL");
2032 MODULE_DESCRIPTION("Common HDA driver funcitons");
2033 

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