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TOMOYO Linux Cross Reference
Linux/sound/pci/hda/hda_intel.c

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  1 /*
  2  *
  3  *  hda_intel.c - Implementation of primary alsa driver code base
  4  *                for Intel HD Audio.
  5  *
  6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
  7  *
  8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
  9  *                     PeiSen Hou <pshou@realtek.com.tw>
 10  *
 11  *  This program is free software; you can redistribute it and/or modify it
 12  *  under the terms of the GNU General Public License as published by the Free
 13  *  Software Foundation; either version 2 of the License, or (at your option)
 14  *  any later version.
 15  *
 16  *  This program is distributed in the hope that it will be useful, but WITHOUT
 17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 19  *  more details.
 20  *
 21  *  You should have received a copy of the GNU General Public License along with
 22  *  this program; if not, write to the Free Software Foundation, Inc., 59
 23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 24  *
 25  *  CONTACTS:
 26  *
 27  *  Matt Jared          matt.jared@intel.com
 28  *  Andy Kopp           andy.kopp@intel.com
 29  *  Dan Kogan           dan.d.kogan@intel.com
 30  *
 31  *  CHANGES:
 32  *
 33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
 34  * 
 35  */
 36 
 37 #include <asm/io.h>
 38 #include <linux/delay.h>
 39 #include <linux/interrupt.h>
 40 #include <linux/kernel.h>
 41 #include <linux/module.h>
 42 #include <linux/dma-mapping.h>
 43 #include <linux/moduleparam.h>
 44 #include <linux/init.h>
 45 #include <linux/slab.h>
 46 #include <linux/pci.h>
 47 #include <linux/mutex.h>
 48 #include <linux/reboot.h>
 49 #include <sound/core.h>
 50 #include <sound/initval.h>
 51 #include "hda_codec.h"
 52 
 53 
 54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
 55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
 56 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
 57 static char *model[SNDRV_CARDS];
 58 static int position_fix[SNDRV_CARDS];
 59 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 60 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 61 static int probe_only[SNDRV_CARDS];
 62 static int single_cmd;
 63 static int enable_msi = -1;
 64 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 65 static char *patch[SNDRV_CARDS];
 66 #endif
 67 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 68 static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
 69                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
 70 #endif
 71 
 72 module_param_array(index, int, NULL, 0444);
 73 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
 74 module_param_array(id, charp, NULL, 0444);
 75 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
 76 module_param_array(enable, bool, NULL, 0444);
 77 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
 78 module_param_array(model, charp, NULL, 0444);
 79 MODULE_PARM_DESC(model, "Use the given board model.");
 80 module_param_array(position_fix, int, NULL, 0444);
 81 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
 82                  "(0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO).");
 83 module_param_array(bdl_pos_adj, int, NULL, 0644);
 84 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
 85 module_param_array(probe_mask, int, NULL, 0444);
 86 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
 87 module_param_array(probe_only, int, NULL, 0444);
 88 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
 89 module_param(single_cmd, bool, 0444);
 90 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
 91                  "(for debugging only).");
 92 module_param(enable_msi, int, 0444);
 93 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 94 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 95 module_param_array(patch, charp, NULL, 0444);
 96 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 97 #endif
 98 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 99 module_param_array(beep_mode, int, NULL, 0444);
100 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
101                             "(0=off, 1=on, 2=mute switch on/off) (default=1).");
102 #endif
103 
104 #ifdef CONFIG_SND_HDA_POWER_SAVE
105 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
106 module_param(power_save, int, 0644);
107 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
108                  "(in second, 0 = disable).");
109 
110 /* reset the HD-audio controller in power save mode.
111  * this may give more power-saving, but will take longer time to
112  * wake up.
113  */
114 static int power_save_controller = 1;
115 module_param(power_save_controller, bool, 0644);
116 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
117 #endif
118 
119 MODULE_LICENSE("GPL");
120 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
121                          "{Intel, ICH6M},"
122                          "{Intel, ICH7},"
123                          "{Intel, ESB2},"
124                          "{Intel, ICH8},"
125                          "{Intel, ICH9},"
126                          "{Intel, ICH10},"
127                          "{Intel, PCH},"
128                          "{Intel, CPT},"
129                          "{Intel, PPT},"
130                          "{Intel, PBG},"
131                          "{Intel, SCH},"
132                          "{ATI, SB450},"
133                          "{ATI, SB600},"
134                          "{ATI, RS600},"
135                          "{ATI, RS690},"
136                          "{ATI, RS780},"
137                          "{ATI, R600},"
138                          "{ATI, RV630},"
139                          "{ATI, RV610},"
140                          "{ATI, RV670},"
141                          "{ATI, RV635},"
142                          "{ATI, RV620},"
143                          "{ATI, RV770},"
144                          "{VIA, VT8251},"
145                          "{VIA, VT8237A},"
146                          "{SiS, SIS966},"
147                          "{ULI, M5461}}");
148 MODULE_DESCRIPTION("Intel HDA driver");
149 
150 #ifdef CONFIG_SND_VERBOSE_PRINTK
151 #define SFX     /* nop */
152 #else
153 #define SFX     "hda-intel: "
154 #endif
155 
156 /*
157  * registers
158  */
159 #define ICH6_REG_GCAP                   0x00
160 #define   ICH6_GCAP_64OK        (1 << 0)   /* 64bit address support */
161 #define   ICH6_GCAP_NSDO        (3 << 1)   /* # of serial data out signals */
162 #define   ICH6_GCAP_BSS         (31 << 3)  /* # of bidirectional streams */
163 #define   ICH6_GCAP_ISS         (15 << 8)  /* # of input streams */
164 #define   ICH6_GCAP_OSS         (15 << 12) /* # of output streams */
165 #define ICH6_REG_VMIN                   0x02
166 #define ICH6_REG_VMAJ                   0x03
167 #define ICH6_REG_OUTPAY                 0x04
168 #define ICH6_REG_INPAY                  0x06
169 #define ICH6_REG_GCTL                   0x08
170 #define   ICH6_GCTL_RESET       (1 << 0)   /* controller reset */
171 #define   ICH6_GCTL_FCNTRL      (1 << 1)   /* flush control */
172 #define   ICH6_GCTL_UNSOL       (1 << 8)   /* accept unsol. response enable */
173 #define ICH6_REG_WAKEEN                 0x0c
174 #define ICH6_REG_STATESTS               0x0e
175 #define ICH6_REG_GSTS                   0x10
176 #define   ICH6_GSTS_FSTS        (1 << 1)   /* flush status */
177 #define ICH6_REG_INTCTL                 0x20
178 #define ICH6_REG_INTSTS                 0x24
179 #define ICH6_REG_WALLCLK                0x30    /* 24Mhz source */
180 #define ICH6_REG_SYNC                   0x34    
181 #define ICH6_REG_CORBLBASE              0x40
182 #define ICH6_REG_CORBUBASE              0x44
183 #define ICH6_REG_CORBWP                 0x48
184 #define ICH6_REG_CORBRP                 0x4a
185 #define   ICH6_CORBRP_RST       (1 << 15)  /* read pointer reset */
186 #define ICH6_REG_CORBCTL                0x4c
187 #define   ICH6_CORBCTL_RUN      (1 << 1)   /* enable DMA */
188 #define   ICH6_CORBCTL_CMEIE    (1 << 0)   /* enable memory error irq */
189 #define ICH6_REG_CORBSTS                0x4d
190 #define   ICH6_CORBSTS_CMEI     (1 << 0)   /* memory error indication */
191 #define ICH6_REG_CORBSIZE               0x4e
192 
193 #define ICH6_REG_RIRBLBASE              0x50
194 #define ICH6_REG_RIRBUBASE              0x54
195 #define ICH6_REG_RIRBWP                 0x58
196 #define   ICH6_RIRBWP_RST       (1 << 15)  /* write pointer reset */
197 #define ICH6_REG_RINTCNT                0x5a
198 #define ICH6_REG_RIRBCTL                0x5c
199 #define   ICH6_RBCTL_IRQ_EN     (1 << 0)   /* enable IRQ */
200 #define   ICH6_RBCTL_DMA_EN     (1 << 1)   /* enable DMA */
201 #define   ICH6_RBCTL_OVERRUN_EN (1 << 2)   /* enable overrun irq */
202 #define ICH6_REG_RIRBSTS                0x5d
203 #define   ICH6_RBSTS_IRQ        (1 << 0)   /* response irq */
204 #define   ICH6_RBSTS_OVERRUN    (1 << 2)   /* overrun irq */
205 #define ICH6_REG_RIRBSIZE               0x5e
206 
207 #define ICH6_REG_IC                     0x60
208 #define ICH6_REG_IR                     0x64
209 #define ICH6_REG_IRS                    0x68
210 #define   ICH6_IRS_VALID        (1<<1)
211 #define   ICH6_IRS_BUSY         (1<<0)
212 
213 #define ICH6_REG_DPLBASE                0x70
214 #define ICH6_REG_DPUBASE                0x74
215 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
216 
217 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
218 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
219 
220 /* stream register offsets from stream base */
221 #define ICH6_REG_SD_CTL                 0x00
222 #define ICH6_REG_SD_STS                 0x03
223 #define ICH6_REG_SD_LPIB                0x04
224 #define ICH6_REG_SD_CBL                 0x08
225 #define ICH6_REG_SD_LVI                 0x0c
226 #define ICH6_REG_SD_FIFOW               0x0e
227 #define ICH6_REG_SD_FIFOSIZE            0x10
228 #define ICH6_REG_SD_FORMAT              0x12
229 #define ICH6_REG_SD_BDLPL               0x18
230 #define ICH6_REG_SD_BDLPU               0x1c
231 
232 /* PCI space */
233 #define ICH6_PCIREG_TCSEL       0x44
234 
235 /*
236  * other constants
237  */
238 
239 /* max number of SDs */
240 /* ICH, ATI and VIA have 4 playback and 4 capture */
241 #define ICH6_NUM_CAPTURE        4
242 #define ICH6_NUM_PLAYBACK       4
243 
244 /* ULI has 6 playback and 5 capture */
245 #define ULI_NUM_CAPTURE         5
246 #define ULI_NUM_PLAYBACK        6
247 
248 /* ATI HDMI has 1 playback and 0 capture */
249 #define ATIHDMI_NUM_CAPTURE     0
250 #define ATIHDMI_NUM_PLAYBACK    1
251 
252 /* TERA has 4 playback and 3 capture */
253 #define TERA_NUM_CAPTURE        3
254 #define TERA_NUM_PLAYBACK       4
255 
256 /* this number is statically defined for simplicity */
257 #define MAX_AZX_DEV             16
258 
259 /* max number of fragments - we may use more if allocating more pages for BDL */
260 #define BDL_SIZE                4096
261 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
262 #define AZX_MAX_FRAG            32
263 /* max buffer size - no h/w limit, you can increase as you like */
264 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
265 
266 /* RIRB int mask: overrun[2], response[0] */
267 #define RIRB_INT_RESPONSE       0x01
268 #define RIRB_INT_OVERRUN        0x04
269 #define RIRB_INT_MASK           0x05
270 
271 /* STATESTS int mask: S3,SD2,SD1,SD0 */
272 #define AZX_MAX_CODECS          8
273 #define AZX_DEFAULT_CODECS      4
274 #define STATESTS_INT_MASK       ((1 << AZX_MAX_CODECS) - 1)
275 
276 /* SD_CTL bits */
277 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
278 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
279 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
280 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
281 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
282 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
283 #define SD_CTL_STREAM_TAG_SHIFT 20
284 
285 /* SD_CTL and SD_STS */
286 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
287 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
288 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
289 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
290                                  SD_INT_COMPLETE)
291 
292 /* SD_STS */
293 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
294 
295 /* INTCTL and INTSTS */
296 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
297 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
298 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
299 
300 /* below are so far hardcoded - should read registers in future */
301 #define ICH6_MAX_CORB_ENTRIES   256
302 #define ICH6_MAX_RIRB_ENTRIES   256
303 
304 /* position fix mode */
305 enum {
306         POS_FIX_AUTO,
307         POS_FIX_LPIB,
308         POS_FIX_POSBUF,
309         POS_FIX_VIACOMBO,
310 };
311 
312 /* Defines for ATI HD Audio support in SB450 south bridge */
313 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
314 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
315 
316 /* Defines for Nvidia HDA support */
317 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
318 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
319 #define NVIDIA_HDA_ISTRM_COH          0x4d
320 #define NVIDIA_HDA_OSTRM_COH          0x4c
321 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
322 
323 /* Defines for Intel SCH HDA snoop control */
324 #define INTEL_SCH_HDA_DEVC      0x78
325 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
326 
327 /* Define IN stream 0 FIFO size offset in VIA controller */
328 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
329 /* Define VIA HD Audio Device ID*/
330 #define VIA_HDAC_DEVICE_ID              0x3288
331 
332 /* HD Audio class code */
333 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
334 
335 /*
336  */
337 
338 struct azx_dev {
339         struct snd_dma_buffer bdl; /* BDL buffer */
340         u32 *posbuf;            /* position buffer pointer */
341 
342         unsigned int bufsize;   /* size of the play buffer in bytes */
343         unsigned int period_bytes; /* size of the period in bytes */
344         unsigned int frags;     /* number for period in the play buffer */
345         unsigned int fifo_size; /* FIFO size */
346         unsigned long start_wallclk;    /* start + minimum wallclk */
347         unsigned long period_wallclk;   /* wallclk for period */
348 
349         void __iomem *sd_addr;  /* stream descriptor pointer */
350 
351         u32 sd_int_sta_mask;    /* stream int status mask */
352 
353         /* pcm support */
354         struct snd_pcm_substream *substream;    /* assigned substream,
355                                                  * set in PCM open
356                                                  */
357         unsigned int format_val;        /* format value to be set in the
358                                          * controller and the codec
359                                          */
360         unsigned char stream_tag;       /* assigned stream */
361         unsigned char index;            /* stream index */
362         int device;                     /* last device number assigned to */
363 
364         unsigned int opened :1;
365         unsigned int running :1;
366         unsigned int irq_pending :1;
367         /*
368          * For VIA:
369          *  A flag to ensure DMA position is 0
370          *  when link position is not greater than FIFO size
371          */
372         unsigned int insufficient :1;
373 };
374 
375 /* CORB/RIRB */
376 struct azx_rb {
377         u32 *buf;               /* CORB/RIRB buffer
378                                  * Each CORB entry is 4byte, RIRB is 8byte
379                                  */
380         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
381         /* for RIRB */
382         unsigned short rp, wp;  /* read/write pointers */
383         int cmds[AZX_MAX_CODECS];       /* number of pending requests */
384         u32 res[AZX_MAX_CODECS];        /* last read value */
385 };
386 
387 struct azx {
388         struct snd_card *card;
389         struct pci_dev *pci;
390         int dev_index;
391 
392         /* chip type specific */
393         int driver_type;
394         unsigned int driver_caps;
395         int playback_streams;
396         int playback_index_offset;
397         int capture_streams;
398         int capture_index_offset;
399         int num_streams;
400 
401         /* pci resources */
402         unsigned long addr;
403         void __iomem *remap_addr;
404         int irq;
405 
406         /* locks */
407         spinlock_t reg_lock;
408         struct mutex open_mutex;
409 
410         /* streams (x num_streams) */
411         struct azx_dev *azx_dev;
412 
413         /* PCM */
414         struct snd_pcm *pcm[HDA_MAX_PCMS];
415 
416         /* HD codec */
417         unsigned short codec_mask;
418         int  codec_probe_mask; /* copied from probe_mask option */
419         struct hda_bus *bus;
420         unsigned int beep_mode;
421 
422         /* CORB/RIRB */
423         struct azx_rb corb;
424         struct azx_rb rirb;
425 
426         /* CORB/RIRB and position buffers */
427         struct snd_dma_buffer rb;
428         struct snd_dma_buffer posbuf;
429 
430         /* flags */
431         int position_fix[2]; /* for both playback/capture streams */
432         int poll_count;
433         unsigned int running :1;
434         unsigned int initialized :1;
435         unsigned int single_cmd :1;
436         unsigned int polling_mode :1;
437         unsigned int msi :1;
438         unsigned int irq_pending_warned :1;
439         unsigned int probing :1; /* codec probing phase */
440 
441         /* for debugging */
442         unsigned int last_cmd[AZX_MAX_CODECS];
443 
444         /* for pending irqs */
445         struct work_struct irq_pending_work;
446 
447         /* reboot notifier (for mysterious hangup problem at power-down) */
448         struct notifier_block reboot_notifier;
449 };
450 
451 /* driver types */
452 enum {
453         AZX_DRIVER_ICH,
454         AZX_DRIVER_PCH,
455         AZX_DRIVER_SCH,
456         AZX_DRIVER_ATI,
457         AZX_DRIVER_ATIHDMI,
458         AZX_DRIVER_VIA,
459         AZX_DRIVER_SIS,
460         AZX_DRIVER_ULI,
461         AZX_DRIVER_NVIDIA,
462         AZX_DRIVER_TERA,
463         AZX_DRIVER_CTX,
464         AZX_DRIVER_GENERIC,
465         AZX_NUM_DRIVERS, /* keep this as last entry */
466 };
467 
468 /* driver quirks (capabilities) */
469 /* bits 0-7 are used for indicating driver type */
470 #define AZX_DCAPS_NO_TCSEL      (1 << 8)        /* No Intel TCSEL bit */
471 #define AZX_DCAPS_NO_MSI        (1 << 9)        /* No MSI support */
472 #define AZX_DCAPS_ATI_SNOOP     (1 << 10)       /* ATI snoop enable */
473 #define AZX_DCAPS_NVIDIA_SNOOP  (1 << 11)       /* Nvidia snoop enable */
474 #define AZX_DCAPS_SCH_SNOOP     (1 << 12)       /* SCH/PCH snoop enable */
475 #define AZX_DCAPS_RIRB_DELAY    (1 << 13)       /* Long delay in read loop */
476 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14)      /* Put a delay before read */
477 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15)      /* X-Fi workaround */
478 #define AZX_DCAPS_POSFIX_LPIB   (1 << 16)       /* Use LPIB as default */
479 #define AZX_DCAPS_POSFIX_VIA    (1 << 17)       /* Use VIACOMBO as default */
480 #define AZX_DCAPS_NO_64BIT      (1 << 18)       /* No 64bit address */
481 #define AZX_DCAPS_SYNC_WRITE    (1 << 19)       /* sync each cmd write */
482 
483 /* quirks for ATI SB / AMD Hudson */
484 #define AZX_DCAPS_PRESET_ATI_SB \
485         (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
486          AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
487 
488 /* quirks for ATI/AMD HDMI */
489 #define AZX_DCAPS_PRESET_ATI_HDMI \
490         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
491 
492 /* quirks for Nvidia */
493 #define AZX_DCAPS_PRESET_NVIDIA \
494         (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI)
495 
496 static char *driver_short_names[] __devinitdata = {
497         [AZX_DRIVER_ICH] = "HDA Intel",
498         [AZX_DRIVER_PCH] = "HDA Intel PCH",
499         [AZX_DRIVER_SCH] = "HDA Intel MID",
500         [AZX_DRIVER_ATI] = "HDA ATI SB",
501         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
502         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
503         [AZX_DRIVER_SIS] = "HDA SIS966",
504         [AZX_DRIVER_ULI] = "HDA ULI M5461",
505         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
506         [AZX_DRIVER_TERA] = "HDA Teradici", 
507         [AZX_DRIVER_CTX] = "HDA Creative", 
508         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
509 };
510 
511 /*
512  * macros for easy use
513  */
514 #define azx_writel(chip,reg,value) \
515         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
516 #define azx_readl(chip,reg) \
517         readl((chip)->remap_addr + ICH6_REG_##reg)
518 #define azx_writew(chip,reg,value) \
519         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
520 #define azx_readw(chip,reg) \
521         readw((chip)->remap_addr + ICH6_REG_##reg)
522 #define azx_writeb(chip,reg,value) \
523         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
524 #define azx_readb(chip,reg) \
525         readb((chip)->remap_addr + ICH6_REG_##reg)
526 
527 #define azx_sd_writel(dev,reg,value) \
528         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
529 #define azx_sd_readl(dev,reg) \
530         readl((dev)->sd_addr + ICH6_REG_##reg)
531 #define azx_sd_writew(dev,reg,value) \
532         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
533 #define azx_sd_readw(dev,reg) \
534         readw((dev)->sd_addr + ICH6_REG_##reg)
535 #define azx_sd_writeb(dev,reg,value) \
536         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
537 #define azx_sd_readb(dev,reg) \
538         readb((dev)->sd_addr + ICH6_REG_##reg)
539 
540 /* for pcm support */
541 #define get_azx_dev(substream) (substream->runtime->private_data)
542 
543 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
544 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
545 /*
546  * Interface for HD codec
547  */
548 
549 /*
550  * CORB / RIRB interface
551  */
552 static int azx_alloc_cmd_io(struct azx *chip)
553 {
554         int err;
555 
556         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
557         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
558                                   snd_dma_pci_data(chip->pci),
559                                   PAGE_SIZE, &chip->rb);
560         if (err < 0) {
561                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
562                 return err;
563         }
564         return 0;
565 }
566 
567 static void azx_init_cmd_io(struct azx *chip)
568 {
569         spin_lock_irq(&chip->reg_lock);
570         /* CORB set up */
571         chip->corb.addr = chip->rb.addr;
572         chip->corb.buf = (u32 *)chip->rb.area;
573         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
574         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
575 
576         /* set the corb size to 256 entries (ULI requires explicitly) */
577         azx_writeb(chip, CORBSIZE, 0x02);
578         /* set the corb write pointer to 0 */
579         azx_writew(chip, CORBWP, 0);
580         /* reset the corb hw read pointer */
581         azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
582         /* enable corb dma */
583         azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
584 
585         /* RIRB set up */
586         chip->rirb.addr = chip->rb.addr + 2048;
587         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
588         chip->rirb.wp = chip->rirb.rp = 0;
589         memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
590         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
591         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
592 
593         /* set the rirb size to 256 entries (ULI requires explicitly) */
594         azx_writeb(chip, RIRBSIZE, 0x02);
595         /* reset the rirb hw write pointer */
596         azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
597         /* set N=1, get RIRB response interrupt for new entry */
598         if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
599                 azx_writew(chip, RINTCNT, 0xc0);
600         else
601                 azx_writew(chip, RINTCNT, 1);
602         /* enable rirb dma and response irq */
603         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
604         spin_unlock_irq(&chip->reg_lock);
605 }
606 
607 static void azx_free_cmd_io(struct azx *chip)
608 {
609         spin_lock_irq(&chip->reg_lock);
610         /* disable ringbuffer DMAs */
611         azx_writeb(chip, RIRBCTL, 0);
612         azx_writeb(chip, CORBCTL, 0);
613         spin_unlock_irq(&chip->reg_lock);
614 }
615 
616 static unsigned int azx_command_addr(u32 cmd)
617 {
618         unsigned int addr = cmd >> 28;
619 
620         if (addr >= AZX_MAX_CODECS) {
621                 snd_BUG();
622                 addr = 0;
623         }
624 
625         return addr;
626 }
627 
628 static unsigned int azx_response_addr(u32 res)
629 {
630         unsigned int addr = res & 0xf;
631 
632         if (addr >= AZX_MAX_CODECS) {
633                 snd_BUG();
634                 addr = 0;
635         }
636 
637         return addr;
638 }
639 
640 /* send a command */
641 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
642 {
643         struct azx *chip = bus->private_data;
644         unsigned int addr = azx_command_addr(val);
645         unsigned int wp;
646 
647         spin_lock_irq(&chip->reg_lock);
648 
649         /* add command to corb */
650         wp = azx_readb(chip, CORBWP);
651         wp++;
652         wp %= ICH6_MAX_CORB_ENTRIES;
653 
654         chip->rirb.cmds[addr]++;
655         chip->corb.buf[wp] = cpu_to_le32(val);
656         azx_writel(chip, CORBWP, wp);
657 
658         spin_unlock_irq(&chip->reg_lock);
659 
660         return 0;
661 }
662 
663 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
664 
665 /* retrieve RIRB entry - called from interrupt handler */
666 static void azx_update_rirb(struct azx *chip)
667 {
668         unsigned int rp, wp;
669         unsigned int addr;
670         u32 res, res_ex;
671 
672         wp = azx_readb(chip, RIRBWP);
673         if (wp == chip->rirb.wp)
674                 return;
675         chip->rirb.wp = wp;
676 
677         while (chip->rirb.rp != wp) {
678                 chip->rirb.rp++;
679                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
680 
681                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
682                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
683                 res = le32_to_cpu(chip->rirb.buf[rp]);
684                 addr = azx_response_addr(res_ex);
685                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
686                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
687                 else if (chip->rirb.cmds[addr]) {
688                         chip->rirb.res[addr] = res;
689                         smp_wmb();
690                         chip->rirb.cmds[addr]--;
691                 } else
692                         snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
693                                    "last cmd=%#08x\n",
694                                    res, res_ex,
695                                    chip->last_cmd[addr]);
696         }
697 }
698 
699 /* receive a response */
700 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
701                                           unsigned int addr)
702 {
703         struct azx *chip = bus->private_data;
704         unsigned long timeout;
705         unsigned long loopcounter;
706         int do_poll = 0;
707 
708  again:
709         timeout = jiffies + msecs_to_jiffies(1000);
710 
711         for (loopcounter = 0;; loopcounter++) {
712                 if (chip->polling_mode || do_poll) {
713                         spin_lock_irq(&chip->reg_lock);
714                         azx_update_rirb(chip);
715                         spin_unlock_irq(&chip->reg_lock);
716                 }
717                 if (!chip->rirb.cmds[addr]) {
718                         smp_rmb();
719                         bus->rirb_error = 0;
720 
721                         if (!do_poll)
722                                 chip->poll_count = 0;
723                         return chip->rirb.res[addr]; /* the last value */
724                 }
725                 if (time_after(jiffies, timeout))
726                         break;
727                 if (bus->needs_damn_long_delay || loopcounter > 3000)
728                         msleep(2); /* temporary workaround */
729                 else {
730                         udelay(10);
731                         cond_resched();
732                 }
733         }
734 
735         if (!chip->polling_mode && chip->poll_count < 2) {
736                 snd_printdd(SFX "azx_get_response timeout, "
737                            "polling the codec once: last cmd=0x%08x\n",
738                            chip->last_cmd[addr]);
739                 do_poll = 1;
740                 chip->poll_count++;
741                 goto again;
742         }
743 
744 
745         if (!chip->polling_mode) {
746                 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
747                            "switching to polling mode: last cmd=0x%08x\n",
748                            chip->last_cmd[addr]);
749                 chip->polling_mode = 1;
750                 goto again;
751         }
752 
753         if (chip->msi) {
754                 snd_printk(KERN_WARNING SFX "No response from codec, "
755                            "disabling MSI: last cmd=0x%08x\n",
756                            chip->last_cmd[addr]);
757                 free_irq(chip->irq, chip);
758                 chip->irq = -1;
759                 pci_disable_msi(chip->pci);
760                 chip->msi = 0;
761                 if (azx_acquire_irq(chip, 1) < 0) {
762                         bus->rirb_error = 1;
763                         return -1;
764                 }
765                 goto again;
766         }
767 
768         if (chip->probing) {
769                 /* If this critical timeout happens during the codec probing
770                  * phase, this is likely an access to a non-existing codec
771                  * slot.  Better to return an error and reset the system.
772                  */
773                 return -1;
774         }
775 
776         /* a fatal communication error; need either to reset or to fallback
777          * to the single_cmd mode
778          */
779         bus->rirb_error = 1;
780         if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
781                 bus->response_reset = 1;
782                 return -1; /* give a chance to retry */
783         }
784 
785         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
786                    "switching to single_cmd mode: last cmd=0x%08x\n",
787                    chip->last_cmd[addr]);
788         chip->single_cmd = 1;
789         bus->response_reset = 0;
790         /* release CORB/RIRB */
791         azx_free_cmd_io(chip);
792         /* disable unsolicited responses */
793         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
794         return -1;
795 }
796 
797 /*
798  * Use the single immediate command instead of CORB/RIRB for simplicity
799  *
800  * Note: according to Intel, this is not preferred use.  The command was
801  *       intended for the BIOS only, and may get confused with unsolicited
802  *       responses.  So, we shouldn't use it for normal operation from the
803  *       driver.
804  *       I left the codes, however, for debugging/testing purposes.
805  */
806 
807 /* receive a response */
808 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
809 {
810         int timeout = 50;
811 
812         while (timeout--) {
813                 /* check IRV busy bit */
814                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
815                         /* reuse rirb.res as the response return value */
816                         chip->rirb.res[addr] = azx_readl(chip, IR);
817                         return 0;
818                 }
819                 udelay(1);
820         }
821         if (printk_ratelimit())
822                 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
823                            azx_readw(chip, IRS));
824         chip->rirb.res[addr] = -1;
825         return -EIO;
826 }
827 
828 /* send a command */
829 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
830 {
831         struct azx *chip = bus->private_data;
832         unsigned int addr = azx_command_addr(val);
833         int timeout = 50;
834 
835         bus->rirb_error = 0;
836         while (timeout--) {
837                 /* check ICB busy bit */
838                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
839                         /* Clear IRV valid bit */
840                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
841                                    ICH6_IRS_VALID);
842                         azx_writel(chip, IC, val);
843                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
844                                    ICH6_IRS_BUSY);
845                         return azx_single_wait_for_response(chip, addr);
846                 }
847                 udelay(1);
848         }
849         if (printk_ratelimit())
850                 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
851                            azx_readw(chip, IRS), val);
852         return -EIO;
853 }
854 
855 /* receive a response */
856 static unsigned int azx_single_get_response(struct hda_bus *bus,
857                                             unsigned int addr)
858 {
859         struct azx *chip = bus->private_data;
860         return chip->rirb.res[addr];
861 }
862 
863 /*
864  * The below are the main callbacks from hda_codec.
865  *
866  * They are just the skeleton to call sub-callbacks according to the
867  * current setting of chip->single_cmd.
868  */
869 
870 /* send a command */
871 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
872 {
873         struct azx *chip = bus->private_data;
874 
875         chip->last_cmd[azx_command_addr(val)] = val;
876         if (chip->single_cmd)
877                 return azx_single_send_cmd(bus, val);
878         else
879                 return azx_corb_send_cmd(bus, val);
880 }
881 
882 /* get a response */
883 static unsigned int azx_get_response(struct hda_bus *bus,
884                                      unsigned int addr)
885 {
886         struct azx *chip = bus->private_data;
887         if (chip->single_cmd)
888                 return azx_single_get_response(bus, addr);
889         else
890                 return azx_rirb_get_response(bus, addr);
891 }
892 
893 #ifdef CONFIG_SND_HDA_POWER_SAVE
894 static void azx_power_notify(struct hda_bus *bus);
895 #endif
896 
897 /* reset codec link */
898 static int azx_reset(struct azx *chip, int full_reset)
899 {
900         int count;
901 
902         if (!full_reset)
903                 goto __skip;
904 
905         /* clear STATESTS */
906         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
907 
908         /* reset controller */
909         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
910 
911         count = 50;
912         while (azx_readb(chip, GCTL) && --count)
913                 msleep(1);
914 
915         /* delay for >= 100us for codec PLL to settle per spec
916          * Rev 0.9 section 5.5.1
917          */
918         msleep(1);
919 
920         /* Bring controller out of reset */
921         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
922 
923         count = 50;
924         while (!azx_readb(chip, GCTL) && --count)
925                 msleep(1);
926 
927         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
928         msleep(1);
929 
930       __skip:
931         /* check to see if controller is ready */
932         if (!azx_readb(chip, GCTL)) {
933                 snd_printd(SFX "azx_reset: controller not ready!\n");
934                 return -EBUSY;
935         }
936 
937         /* Accept unsolicited responses */
938         if (!chip->single_cmd)
939                 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
940                            ICH6_GCTL_UNSOL);
941 
942         /* detect codecs */
943         if (!chip->codec_mask) {
944                 chip->codec_mask = azx_readw(chip, STATESTS);
945                 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
946         }
947 
948         return 0;
949 }
950 
951 
952 /*
953  * Lowlevel interface
954  */  
955 
956 /* enable interrupts */
957 static void azx_int_enable(struct azx *chip)
958 {
959         /* enable controller CIE and GIE */
960         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
961                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
962 }
963 
964 /* disable interrupts */
965 static void azx_int_disable(struct azx *chip)
966 {
967         int i;
968 
969         /* disable interrupts in stream descriptor */
970         for (i = 0; i < chip->num_streams; i++) {
971                 struct azx_dev *azx_dev = &chip->azx_dev[i];
972                 azx_sd_writeb(azx_dev, SD_CTL,
973                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
974         }
975 
976         /* disable SIE for all streams */
977         azx_writeb(chip, INTCTL, 0);
978 
979         /* disable controller CIE and GIE */
980         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
981                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
982 }
983 
984 /* clear interrupts */
985 static void azx_int_clear(struct azx *chip)
986 {
987         int i;
988 
989         /* clear stream status */
990         for (i = 0; i < chip->num_streams; i++) {
991                 struct azx_dev *azx_dev = &chip->azx_dev[i];
992                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
993         }
994 
995         /* clear STATESTS */
996         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
997 
998         /* clear rirb status */
999         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1000 
1001         /* clear int status */
1002         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1003 }
1004 
1005 /* start a stream */
1006 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1007 {
1008         /*
1009          * Before stream start, initialize parameter
1010          */
1011         azx_dev->insufficient = 1;
1012 
1013         /* enable SIE */
1014         azx_writel(chip, INTCTL,
1015                    azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1016         /* set DMA start and interrupt mask */
1017         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1018                       SD_CTL_DMA_START | SD_INT_MASK);
1019 }
1020 
1021 /* stop DMA */
1022 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1023 {
1024         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1025                       ~(SD_CTL_DMA_START | SD_INT_MASK));
1026         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1027 }
1028 
1029 /* stop a stream */
1030 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1031 {
1032         azx_stream_clear(chip, azx_dev);
1033         /* disable SIE */
1034         azx_writel(chip, INTCTL,
1035                    azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1036 }
1037 
1038 
1039 /*
1040  * reset and start the controller registers
1041  */
1042 static void azx_init_chip(struct azx *chip, int full_reset)
1043 {
1044         if (chip->initialized)
1045                 return;
1046 
1047         /* reset controller */
1048         azx_reset(chip, full_reset);
1049 
1050         /* initialize interrupts */
1051         azx_int_clear(chip);
1052         azx_int_enable(chip);
1053 
1054         /* initialize the codec command I/O */
1055         if (!chip->single_cmd)
1056                 azx_init_cmd_io(chip);
1057 
1058         /* program the position buffer */
1059         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1060         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1061 
1062         chip->initialized = 1;
1063 }
1064 
1065 /*
1066  * initialize the PCI registers
1067  */
1068 /* update bits in a PCI register byte */
1069 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1070                             unsigned char mask, unsigned char val)
1071 {
1072         unsigned char data;
1073 
1074         pci_read_config_byte(pci, reg, &data);
1075         data &= ~mask;
1076         data |= (val & mask);
1077         pci_write_config_byte(pci, reg, data);
1078 }
1079 
1080 static void azx_init_pci(struct azx *chip)
1081 {
1082         unsigned short snoop;
1083 
1084         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1085          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1086          * Ensuring these bits are 0 clears playback static on some HD Audio
1087          * codecs.
1088          * The PCI register TCSEL is defined in the Intel manuals.
1089          */
1090         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1091                 snd_printdd(SFX "Clearing TCSEL\n");
1092                 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1093         }
1094 
1095         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1096          * we need to enable snoop.
1097          */
1098         if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1099                 snd_printdd(SFX "Enabling ATI snoop\n");
1100                 update_pci_byte(chip->pci,
1101                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 
1102                                 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
1103         }
1104 
1105         /* For NVIDIA HDA, enable snoop */
1106         if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1107                 snd_printdd(SFX "Enabling Nvidia snoop\n");
1108                 update_pci_byte(chip->pci,
1109                                 NVIDIA_HDA_TRANSREG_ADDR,
1110                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1111                 update_pci_byte(chip->pci,
1112                                 NVIDIA_HDA_ISTRM_COH,
1113                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1114                 update_pci_byte(chip->pci,
1115                                 NVIDIA_HDA_OSTRM_COH,
1116                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1117         }
1118 
1119         /* Enable SCH/PCH snoop if needed */
1120         if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1121                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1122                 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
1123                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC,
1124                                 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
1125                         pci_read_config_word(chip->pci,
1126                                 INTEL_SCH_HDA_DEVC, &snoop);
1127                         snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n",
1128                                 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1129                                 ? "Failed" : "OK");
1130                 }
1131         }
1132 }
1133 
1134 
1135 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1136 
1137 /*
1138  * interrupt handler
1139  */
1140 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1141 {
1142         struct azx *chip = dev_id;
1143         struct azx_dev *azx_dev;
1144         u32 status;
1145         u8 sd_status;
1146         int i, ok;
1147 
1148         spin_lock(&chip->reg_lock);
1149 
1150         status = azx_readl(chip, INTSTS);
1151         if (status == 0) {
1152                 spin_unlock(&chip->reg_lock);
1153                 return IRQ_NONE;
1154         }
1155         
1156         for (i = 0; i < chip->num_streams; i++) {
1157                 azx_dev = &chip->azx_dev[i];
1158                 if (status & azx_dev->sd_int_sta_mask) {
1159                         sd_status = azx_sd_readb(azx_dev, SD_STS);
1160                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1161                         if (!azx_dev->substream || !azx_dev->running ||
1162                             !(sd_status & SD_INT_COMPLETE))
1163                                 continue;
1164                         /* check whether this IRQ is really acceptable */
1165                         ok = azx_position_ok(chip, azx_dev);
1166                         if (ok == 1) {
1167                                 azx_dev->irq_pending = 0;
1168                                 spin_unlock(&chip->reg_lock);
1169                                 snd_pcm_period_elapsed(azx_dev->substream);
1170                                 spin_lock(&chip->reg_lock);
1171                         } else if (ok == 0 && chip->bus && chip->bus->workq) {
1172                                 /* bogus IRQ, process it later */
1173                                 azx_dev->irq_pending = 1;
1174                                 queue_work(chip->bus->workq,
1175                                            &chip->irq_pending_work);
1176                         }
1177                 }
1178         }
1179 
1180         /* clear rirb int */
1181         status = azx_readb(chip, RIRBSTS);
1182         if (status & RIRB_INT_MASK) {
1183                 if (status & RIRB_INT_RESPONSE) {
1184                         if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1185                                 udelay(80);
1186                         azx_update_rirb(chip);
1187                 }
1188                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1189         }
1190 
1191 #if 0
1192         /* clear state status int */
1193         if (azx_readb(chip, STATESTS) & 0x04)
1194                 azx_writeb(chip, STATESTS, 0x04);
1195 #endif
1196         spin_unlock(&chip->reg_lock);
1197         
1198         return IRQ_HANDLED;
1199 }
1200 
1201 
1202 /*
1203  * set up a BDL entry
1204  */
1205 static int setup_bdle(struct snd_pcm_substream *substream,
1206                       struct azx_dev *azx_dev, u32 **bdlp,
1207                       int ofs, int size, int with_ioc)
1208 {
1209         u32 *bdl = *bdlp;
1210 
1211         while (size > 0) {
1212                 dma_addr_t addr;
1213                 int chunk;
1214 
1215                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1216                         return -EINVAL;
1217 
1218                 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1219                 /* program the address field of the BDL entry */
1220                 bdl[0] = cpu_to_le32((u32)addr);
1221                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1222                 /* program the size field of the BDL entry */
1223                 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1224                 bdl[2] = cpu_to_le32(chunk);
1225                 /* program the IOC to enable interrupt
1226                  * only when the whole fragment is processed
1227                  */
1228                 size -= chunk;
1229                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1230                 bdl += 4;
1231                 azx_dev->frags++;
1232                 ofs += chunk;
1233         }
1234         *bdlp = bdl;
1235         return ofs;
1236 }
1237 
1238 /*
1239  * set up BDL entries
1240  */
1241 static int azx_setup_periods(struct azx *chip,
1242                              struct snd_pcm_substream *substream,
1243                              struct azx_dev *azx_dev)
1244 {
1245         u32 *bdl;
1246         int i, ofs, periods, period_bytes;
1247         int pos_adj;
1248 
1249         /* reset BDL address */
1250         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1251         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1252 
1253         period_bytes = azx_dev->period_bytes;
1254         periods = azx_dev->bufsize / period_bytes;
1255 
1256         /* program the initial BDL entries */
1257         bdl = (u32 *)azx_dev->bdl.area;
1258         ofs = 0;
1259         azx_dev->frags = 0;
1260         pos_adj = bdl_pos_adj[chip->dev_index];
1261         if (pos_adj > 0) {
1262                 struct snd_pcm_runtime *runtime = substream->runtime;
1263                 int pos_align = pos_adj;
1264                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1265                 if (!pos_adj)
1266                         pos_adj = pos_align;
1267                 else
1268                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1269                                 pos_align;
1270                 pos_adj = frames_to_bytes(runtime, pos_adj);
1271                 if (pos_adj >= period_bytes) {
1272                         snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1273                                    bdl_pos_adj[chip->dev_index]);
1274                         pos_adj = 0;
1275                 } else {
1276                         ofs = setup_bdle(substream, azx_dev,
1277                                          &bdl, ofs, pos_adj,
1278                                          !substream->runtime->no_period_wakeup);
1279                         if (ofs < 0)
1280                                 goto error;
1281                 }
1282         } else
1283                 pos_adj = 0;
1284         for (i = 0; i < periods; i++) {
1285                 if (i == periods - 1 && pos_adj)
1286                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1287                                          period_bytes - pos_adj, 0);
1288                 else
1289                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1290                                          period_bytes,
1291                                          !substream->runtime->no_period_wakeup);
1292                 if (ofs < 0)
1293                         goto error;
1294         }
1295         return 0;
1296 
1297  error:
1298         snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1299                    azx_dev->bufsize, period_bytes);
1300         return -EINVAL;
1301 }
1302 
1303 /* reset stream */
1304 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1305 {
1306         unsigned char val;
1307         int timeout;
1308 
1309         azx_stream_clear(chip, azx_dev);
1310 
1311         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1312                       SD_CTL_STREAM_RESET);
1313         udelay(3);
1314         timeout = 300;
1315         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1316                --timeout)
1317                 ;
1318         val &= ~SD_CTL_STREAM_RESET;
1319         azx_sd_writeb(azx_dev, SD_CTL, val);
1320         udelay(3);
1321 
1322         timeout = 300;
1323         /* waiting for hardware to report that the stream is out of reset */
1324         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1325                --timeout)
1326                 ;
1327 
1328         /* reset first position - may not be synced with hw at this time */
1329         *azx_dev->posbuf = 0;
1330 }
1331 
1332 /*
1333  * set up the SD for streaming
1334  */
1335 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1336 {
1337         /* make sure the run bit is zero for SD */
1338         azx_stream_clear(chip, azx_dev);
1339         /* program the stream_tag */
1340         azx_sd_writel(azx_dev, SD_CTL,
1341                       (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1342                       (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1343 
1344         /* program the length of samples in cyclic buffer */
1345         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1346 
1347         /* program the stream format */
1348         /* this value needs to be the same as the one programmed */
1349         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1350 
1351         /* program the stream LVI (last valid index) of the BDL */
1352         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1353 
1354         /* program the BDL address */
1355         /* lower BDL address */
1356         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1357         /* upper BDL address */
1358         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1359 
1360         /* enable the position buffer */
1361         if (chip->position_fix[0] != POS_FIX_LPIB ||
1362             chip->position_fix[1] != POS_FIX_LPIB) {
1363                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1364                         azx_writel(chip, DPLBASE,
1365                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1366         }
1367 
1368         /* set the interrupt enable bits in the descriptor control register */
1369         azx_sd_writel(azx_dev, SD_CTL,
1370                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1371 
1372         return 0;
1373 }
1374 
1375 /*
1376  * Probe the given codec address
1377  */
1378 static int probe_codec(struct azx *chip, int addr)
1379 {
1380         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1381                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1382         unsigned int res;
1383 
1384         mutex_lock(&chip->bus->cmd_mutex);
1385         chip->probing = 1;
1386         azx_send_cmd(chip->bus, cmd);
1387         res = azx_get_response(chip->bus, addr);
1388         chip->probing = 0;
1389         mutex_unlock(&chip->bus->cmd_mutex);
1390         if (res == -1)
1391                 return -EIO;
1392         snd_printdd(SFX "codec #%d probed OK\n", addr);
1393         return 0;
1394 }
1395 
1396 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1397                                  struct hda_pcm *cpcm);
1398 static void azx_stop_chip(struct azx *chip);
1399 
1400 static void azx_bus_reset(struct hda_bus *bus)
1401 {
1402         struct azx *chip = bus->private_data;
1403 
1404         bus->in_reset = 1;
1405         azx_stop_chip(chip);
1406         azx_init_chip(chip, 1);
1407 #ifdef CONFIG_PM
1408         if (chip->initialized) {
1409                 int i;
1410 
1411                 for (i = 0; i < HDA_MAX_PCMS; i++)
1412                         snd_pcm_suspend_all(chip->pcm[i]);
1413                 snd_hda_suspend(chip->bus);
1414                 snd_hda_resume(chip->bus);
1415         }
1416 #endif
1417         bus->in_reset = 0;
1418 }
1419 
1420 /*
1421  * Codec initialization
1422  */
1423 
1424 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1425 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1426         [AZX_DRIVER_NVIDIA] = 8,
1427         [AZX_DRIVER_TERA] = 1,
1428 };
1429 
1430 static int __devinit azx_codec_create(struct azx *chip, const char *model)
1431 {
1432         struct hda_bus_template bus_temp;
1433         int c, codecs, err;
1434         int max_slots;
1435 
1436         memset(&bus_temp, 0, sizeof(bus_temp));
1437         bus_temp.private_data = chip;
1438         bus_temp.modelname = model;
1439         bus_temp.pci = chip->pci;
1440         bus_temp.ops.command = azx_send_cmd;
1441         bus_temp.ops.get_response = azx_get_response;
1442         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1443         bus_temp.ops.bus_reset = azx_bus_reset;
1444 #ifdef CONFIG_SND_HDA_POWER_SAVE
1445         bus_temp.power_save = &power_save;
1446         bus_temp.ops.pm_notify = azx_power_notify;
1447 #endif
1448 
1449         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1450         if (err < 0)
1451                 return err;
1452 
1453         if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1454                 snd_printd(SFX "Enable delay in RIRB handling\n");
1455                 chip->bus->needs_damn_long_delay = 1;
1456         }
1457 
1458         codecs = 0;
1459         max_slots = azx_max_codecs[chip->driver_type];
1460         if (!max_slots)
1461                 max_slots = AZX_DEFAULT_CODECS;
1462 
1463         /* First try to probe all given codec slots */
1464         for (c = 0; c < max_slots; c++) {
1465                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1466                         if (probe_codec(chip, c) < 0) {
1467                                 /* Some BIOSen give you wrong codec addresses
1468                                  * that don't exist
1469                                  */
1470                                 snd_printk(KERN_WARNING SFX
1471                                            "Codec #%d probe error; "
1472                                            "disabling it...\n", c);
1473                                 chip->codec_mask &= ~(1 << c);
1474                                 /* More badly, accessing to a non-existing
1475                                  * codec often screws up the controller chip,
1476                                  * and disturbs the further communications.
1477                                  * Thus if an error occurs during probing,
1478                                  * better to reset the controller chip to
1479                                  * get back to the sanity state.
1480                                  */
1481                                 azx_stop_chip(chip);
1482                                 azx_init_chip(chip, 1);
1483                         }
1484                 }
1485         }
1486 
1487         /* AMD chipsets often cause the communication stalls upon certain
1488          * sequence like the pin-detection.  It seems that forcing the synced
1489          * access works around the stall.  Grrr...
1490          */
1491         if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1492                 snd_printd(SFX "Enable sync_write for stable communication\n");
1493                 chip->bus->sync_write = 1;
1494                 chip->bus->allow_bus_reset = 1;
1495         }
1496 
1497         /* Then create codec instances */
1498         for (c = 0; c < max_slots; c++) {
1499                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1500                         struct hda_codec *codec;
1501                         err = snd_hda_codec_new(chip->bus, c, &codec);
1502                         if (err < 0)
1503                                 continue;
1504                         codec->beep_mode = chip->beep_mode;
1505                         codecs++;
1506                 }
1507         }
1508         if (!codecs) {
1509                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1510                 return -ENXIO;
1511         }
1512         return 0;
1513 }
1514 
1515 /* configure each codec instance */
1516 static int __devinit azx_codec_configure(struct azx *chip)
1517 {
1518         struct hda_codec *codec;
1519         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1520                 snd_hda_codec_configure(codec);
1521         }
1522         return 0;
1523 }
1524 
1525 
1526 /*
1527  * PCM support
1528  */
1529 
1530 /* assign a stream for the PCM */
1531 static inline struct azx_dev *
1532 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1533 {
1534         int dev, i, nums;
1535         struct azx_dev *res = NULL;
1536 
1537         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1538                 dev = chip->playback_index_offset;
1539                 nums = chip->playback_streams;
1540         } else {
1541                 dev = chip->capture_index_offset;
1542                 nums = chip->capture_streams;
1543         }
1544         for (i = 0; i < nums; i++, dev++)
1545                 if (!chip->azx_dev[dev].opened) {
1546                         res = &chip->azx_dev[dev];
1547                         if (res->device == substream->pcm->device)
1548                                 break;
1549                 }
1550         if (res) {
1551                 res->opened = 1;
1552                 res->device = substream->pcm->device;
1553         }
1554         return res;
1555 }
1556 
1557 /* release the assigned stream */
1558 static inline void azx_release_device(struct azx_dev *azx_dev)
1559 {
1560         azx_dev->opened = 0;
1561 }
1562 
1563 static struct snd_pcm_hardware azx_pcm_hw = {
1564         .info =                 (SNDRV_PCM_INFO_MMAP |
1565                                  SNDRV_PCM_INFO_INTERLEAVED |
1566                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1567                                  SNDRV_PCM_INFO_MMAP_VALID |
1568                                  /* No full-resume yet implemented */
1569                                  /* SNDRV_PCM_INFO_RESUME |*/
1570                                  SNDRV_PCM_INFO_PAUSE |
1571                                  SNDRV_PCM_INFO_SYNC_START |
1572                                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1573         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1574         .rates =                SNDRV_PCM_RATE_48000,
1575         .rate_min =             48000,
1576         .rate_max =             48000,
1577         .channels_min =         2,
1578         .channels_max =         2,
1579         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1580         .period_bytes_min =     128,
1581         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1582         .periods_min =          2,
1583         .periods_max =          AZX_MAX_FRAG,
1584         .fifo_size =            0,
1585 };
1586 
1587 struct azx_pcm {
1588         struct azx *chip;
1589         struct hda_codec *codec;
1590         struct hda_pcm_stream *hinfo[2];
1591 };
1592 
1593 static int azx_pcm_open(struct snd_pcm_substream *substream)
1594 {
1595         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1596         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1597         struct azx *chip = apcm->chip;
1598         struct azx_dev *azx_dev;
1599         struct snd_pcm_runtime *runtime = substream->runtime;
1600         unsigned long flags;
1601         int err;
1602 
1603         mutex_lock(&chip->open_mutex);
1604         azx_dev = azx_assign_device(chip, substream);
1605         if (azx_dev == NULL) {
1606                 mutex_unlock(&chip->open_mutex);
1607                 return -EBUSY;
1608         }
1609         runtime->hw = azx_pcm_hw;
1610         runtime->hw.channels_min = hinfo->channels_min;
1611         runtime->hw.channels_max = hinfo->channels_max;
1612         runtime->hw.formats = hinfo->formats;
1613         runtime->hw.rates = hinfo->rates;
1614         snd_pcm_limit_hw_rates(runtime);
1615         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1616         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1617                                    128);
1618         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1619                                    128);
1620         snd_hda_power_up(apcm->codec);
1621         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1622         if (err < 0) {
1623                 azx_release_device(azx_dev);
1624                 snd_hda_power_down(apcm->codec);
1625                 mutex_unlock(&chip->open_mutex);
1626                 return err;
1627         }
1628         snd_pcm_limit_hw_rates(runtime);
1629         /* sanity check */
1630         if (snd_BUG_ON(!runtime->hw.channels_min) ||
1631             snd_BUG_ON(!runtime->hw.channels_max) ||
1632             snd_BUG_ON(!runtime->hw.formats) ||
1633             snd_BUG_ON(!runtime->hw.rates)) {
1634                 azx_release_device(azx_dev);
1635                 hinfo->ops.close(hinfo, apcm->codec, substream);
1636                 snd_hda_power_down(apcm->codec);
1637                 mutex_unlock(&chip->open_mutex);
1638                 return -EINVAL;
1639         }
1640         spin_lock_irqsave(&chip->reg_lock, flags);
1641         azx_dev->substream = substream;
1642         azx_dev->running = 0;
1643         spin_unlock_irqrestore(&chip->reg_lock, flags);
1644 
1645         runtime->private_data = azx_dev;
1646         snd_pcm_set_sync(substream);
1647         mutex_unlock(&chip->open_mutex);
1648         return 0;
1649 }
1650 
1651 static int azx_pcm_close(struct snd_pcm_substream *substream)
1652 {
1653         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1654         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1655         struct azx *chip = apcm->chip;
1656         struct azx_dev *azx_dev = get_azx_dev(substream);
1657         unsigned long flags;
1658 
1659         mutex_lock(&chip->open_mutex);
1660         spin_lock_irqsave(&chip->reg_lock, flags);
1661         azx_dev->substream = NULL;
1662         azx_dev->running = 0;
1663         spin_unlock_irqrestore(&chip->reg_lock, flags);
1664         azx_release_device(azx_dev);
1665         hinfo->ops.close(hinfo, apcm->codec, substream);
1666         snd_hda_power_down(apcm->codec);
1667         mutex_unlock(&chip->open_mutex);
1668         return 0;
1669 }
1670 
1671 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1672                              struct snd_pcm_hw_params *hw_params)
1673 {
1674         struct azx_dev *azx_dev = get_azx_dev(substream);
1675 
1676         azx_dev->bufsize = 0;
1677         azx_dev->period_bytes = 0;
1678         azx_dev->format_val = 0;
1679         return snd_pcm_lib_malloc_pages(substream,
1680                                         params_buffer_bytes(hw_params));
1681 }
1682 
1683 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1684 {
1685         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1686         struct azx_dev *azx_dev = get_azx_dev(substream);
1687         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1688 
1689         /* reset BDL address */
1690         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1691         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1692         azx_sd_writel(azx_dev, SD_CTL, 0);
1693         azx_dev->bufsize = 0;
1694         azx_dev->period_bytes = 0;
1695         azx_dev->format_val = 0;
1696 
1697         snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1698 
1699         return snd_pcm_lib_free_pages(substream);
1700 }
1701 
1702 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1703 {
1704         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1705         struct azx *chip = apcm->chip;
1706         struct azx_dev *azx_dev = get_azx_dev(substream);
1707         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1708         struct snd_pcm_runtime *runtime = substream->runtime;
1709         unsigned int bufsize, period_bytes, format_val, stream_tag;
1710         int err;
1711 
1712         azx_stream_reset(chip, azx_dev);
1713         format_val = snd_hda_calc_stream_format(runtime->rate,
1714                                                 runtime->channels,
1715                                                 runtime->format,
1716                                                 hinfo->maxbps,
1717                                                 apcm->codec->spdif_ctls);
1718         if (!format_val) {
1719                 snd_printk(KERN_ERR SFX
1720                            "invalid format_val, rate=%d, ch=%d, format=%d\n",
1721                            runtime->rate, runtime->channels, runtime->format);
1722                 return -EINVAL;
1723         }
1724 
1725         bufsize = snd_pcm_lib_buffer_bytes(substream);
1726         period_bytes = snd_pcm_lib_period_bytes(substream);
1727 
1728         snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1729                     bufsize, format_val);
1730 
1731         if (bufsize != azx_dev->bufsize ||
1732             period_bytes != azx_dev->period_bytes ||
1733             format_val != azx_dev->format_val) {
1734                 azx_dev->bufsize = bufsize;
1735                 azx_dev->period_bytes = period_bytes;
1736                 azx_dev->format_val = format_val;
1737                 err = azx_setup_periods(chip, substream, azx_dev);
1738                 if (err < 0)
1739                         return err;
1740         }
1741 
1742         /* wallclk has 24Mhz clock source */
1743         azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1744                                                 runtime->rate) * 1000);
1745         azx_setup_controller(chip, azx_dev);
1746         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1747                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1748         else
1749                 azx_dev->fifo_size = 0;
1750 
1751         stream_tag = azx_dev->stream_tag;
1752         /* CA-IBG chips need the playback stream starting from 1 */
1753         if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
1754             stream_tag > chip->capture_streams)
1755                 stream_tag -= chip->capture_streams;
1756         return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
1757                                      azx_dev->format_val, substream);
1758 }
1759 
1760 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1761 {
1762         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1763         struct azx *chip = apcm->chip;
1764         struct azx_dev *azx_dev;
1765         struct snd_pcm_substream *s;
1766         int rstart = 0, start, nsync = 0, sbits = 0;
1767         int nwait, timeout;
1768 
1769         switch (cmd) {
1770         case SNDRV_PCM_TRIGGER_START:
1771                 rstart = 1;
1772         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1773         case SNDRV_PCM_TRIGGER_RESUME:
1774                 start = 1;
1775                 break;
1776         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1777         case SNDRV_PCM_TRIGGER_SUSPEND:
1778         case SNDRV_PCM_TRIGGER_STOP:
1779                 start = 0;
1780                 break;
1781         default:
1782                 return -EINVAL;
1783         }
1784 
1785         snd_pcm_group_for_each_entry(s, substream) {
1786                 if (s->pcm->card != substream->pcm->card)
1787                         continue;
1788                 azx_dev = get_azx_dev(s);
1789                 sbits |= 1 << azx_dev->index;
1790                 nsync++;
1791                 snd_pcm_trigger_done(s, substream);
1792         }
1793 
1794         spin_lock(&chip->reg_lock);
1795         if (nsync > 1) {
1796                 /* first, set SYNC bits of corresponding streams */
1797                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1798         }
1799         snd_pcm_group_for_each_entry(s, substream) {
1800                 if (s->pcm->card != substream->pcm->card)
1801                         continue;
1802                 azx_dev = get_azx_dev(s);
1803                 if (start) {
1804                         azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
1805                         if (!rstart)
1806                                 azx_dev->start_wallclk -=
1807                                                 azx_dev->period_wallclk;
1808                         azx_stream_start(chip, azx_dev);
1809                 } else {
1810                         azx_stream_stop(chip, azx_dev);
1811                 }
1812                 azx_dev->running = start;
1813         }
1814         spin_unlock(&chip->reg_lock);
1815         if (start) {
1816                 if (nsync == 1)
1817                         return 0;
1818                 /* wait until all FIFOs get ready */
1819                 for (timeout = 5000; timeout; timeout--) {
1820                         nwait = 0;
1821                         snd_pcm_group_for_each_entry(s, substream) {
1822                                 if (s->pcm->card != substream->pcm->card)
1823                                         continue;
1824                                 azx_dev = get_azx_dev(s);
1825                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
1826                                       SD_STS_FIFO_READY))
1827                                         nwait++;
1828                         }
1829                         if (!nwait)
1830                                 break;
1831                         cpu_relax();
1832                 }
1833         } else {
1834                 /* wait until all RUN bits are cleared */
1835                 for (timeout = 5000; timeout; timeout--) {
1836                         nwait = 0;
1837                         snd_pcm_group_for_each_entry(s, substream) {
1838                                 if (s->pcm->card != substream->pcm->card)
1839                                         continue;
1840                                 azx_dev = get_azx_dev(s);
1841                                 if (azx_sd_readb(azx_dev, SD_CTL) &
1842                                     SD_CTL_DMA_START)
1843                                         nwait++;
1844                         }
1845                         if (!nwait)
1846                                 break;
1847                         cpu_relax();
1848                 }
1849         }
1850         if (nsync > 1) {
1851                 spin_lock(&chip->reg_lock);
1852                 /* reset SYNC bits */
1853                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1854                 spin_unlock(&chip->reg_lock);
1855         }
1856         return 0;
1857 }
1858 
1859 /* get the current DMA position with correction on VIA chips */
1860 static unsigned int azx_via_get_position(struct azx *chip,
1861                                          struct azx_dev *azx_dev)
1862 {
1863         unsigned int link_pos, mini_pos, bound_pos;
1864         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1865         unsigned int fifo_size;
1866 
1867         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1868         if (azx_dev->index >= 4) {
1869                 /* Playback, no problem using link position */
1870                 return link_pos;
1871         }
1872 
1873         /* Capture */
1874         /* For new chipset,
1875          * use mod to get the DMA position just like old chipset
1876          */
1877         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1878         mod_dma_pos %= azx_dev->period_bytes;
1879 
1880         /* azx_dev->fifo_size can't get FIFO size of in stream.
1881          * Get from base address + offset.
1882          */
1883         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1884 
1885         if (azx_dev->insufficient) {
1886                 /* Link position never gather than FIFO size */
1887                 if (link_pos <= fifo_size)
1888                         return 0;
1889 
1890                 azx_dev->insufficient = 0;
1891         }
1892 
1893         if (link_pos <= fifo_size)
1894                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1895         else
1896                 mini_pos = link_pos - fifo_size;
1897 
1898         /* Find nearest previous boudary */
1899         mod_mini_pos = mini_pos % azx_dev->period_bytes;
1900         mod_link_pos = link_pos % azx_dev->period_bytes;
1901         if (mod_link_pos >= fifo_size)
1902                 bound_pos = link_pos - mod_link_pos;
1903         else if (mod_dma_pos >= mod_mini_pos)
1904                 bound_pos = mini_pos - mod_mini_pos;
1905         else {
1906                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1907                 if (bound_pos >= azx_dev->bufsize)
1908                         bound_pos = 0;
1909         }
1910 
1911         /* Calculate real DMA position we want */
1912         return bound_pos + mod_dma_pos;
1913 }
1914 
1915 static unsigned int azx_get_position(struct azx *chip,
1916                                      struct azx_dev *azx_dev)
1917 {
1918         unsigned int pos;
1919         int stream = azx_dev->substream->stream;
1920 
1921         switch (chip->position_fix[stream]) {
1922         case POS_FIX_LPIB:
1923                 /* read LPIB */
1924                 pos = azx_sd_readl(azx_dev, SD_LPIB);
1925                 break;
1926         case POS_FIX_VIACOMBO:
1927                 pos = azx_via_get_position(chip, azx_dev);
1928                 break;
1929         default:
1930                 /* use the position buffer */
1931                 pos = le32_to_cpu(*azx_dev->posbuf);
1932         }
1933 
1934         if (pos >= azx_dev->bufsize)
1935                 pos = 0;
1936         return pos;
1937 }
1938 
1939 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1940 {
1941         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1942         struct azx *chip = apcm->chip;
1943         struct azx_dev *azx_dev = get_azx_dev(substream);
1944         return bytes_to_frames(substream->runtime,
1945                                azx_get_position(chip, azx_dev));
1946 }
1947 
1948 /*
1949  * Check whether the current DMA position is acceptable for updating
1950  * periods.  Returns non-zero if it's OK.
1951  *
1952  * Many HD-audio controllers appear pretty inaccurate about
1953  * the update-IRQ timing.  The IRQ is issued before actually the
1954  * data is processed.  So, we need to process it afterwords in a
1955  * workqueue.
1956  */
1957 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1958 {
1959         u32 wallclk;
1960         unsigned int pos;
1961         int stream;
1962 
1963         wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
1964         if (wallclk < (azx_dev->period_wallclk * 2) / 3)
1965                 return -1;      /* bogus (too early) interrupt */
1966 
1967         stream = azx_dev->substream->stream;
1968         pos = azx_get_position(chip, azx_dev);
1969         if (chip->position_fix[stream] == POS_FIX_AUTO) {
1970                 if (!pos) {
1971                         printk(KERN_WARNING
1972                                "hda-intel: Invalid position buffer, "
1973                                "using LPIB read method instead.\n");
1974                         chip->position_fix[stream] = POS_FIX_LPIB;
1975                         pos = azx_get_position(chip, azx_dev);
1976                 } else
1977                         chip->position_fix[stream] = POS_FIX_POSBUF;
1978         }
1979 
1980         if (WARN_ONCE(!azx_dev->period_bytes,
1981                       "hda-intel: zero azx_dev->period_bytes"))
1982                 return -1; /* this shouldn't happen! */
1983         if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
1984             pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1985                 /* NG - it's below the first next period boundary */
1986                 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
1987         azx_dev->start_wallclk += wallclk;
1988         return 1; /* OK, it's fine */
1989 }
1990 
1991 /*
1992  * The work for pending PCM period updates.
1993  */
1994 static void azx_irq_pending_work(struct work_struct *work)
1995 {
1996         struct azx *chip = container_of(work, struct azx, irq_pending_work);
1997         int i, pending, ok;
1998 
1999         if (!chip->irq_pending_warned) {
2000                 printk(KERN_WARNING
2001                        "hda-intel: IRQ timing workaround is activated "
2002                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2003                        chip->card->number);
2004                 chip->irq_pending_warned = 1;
2005         }
2006 
2007         for (;;) {
2008                 pending = 0;
2009                 spin_lock_irq(&chip->reg_lock);
2010                 for (i = 0; i < chip->num_streams; i++) {
2011                         struct azx_dev *azx_dev = &chip->azx_dev[i];
2012                         if (!azx_dev->irq_pending ||
2013                             !azx_dev->substream ||
2014                             !azx_dev->running)
2015                                 continue;
2016                         ok = azx_position_ok(chip, azx_dev);
2017                         if (ok > 0) {
2018                                 azx_dev->irq_pending = 0;
2019                                 spin_unlock(&chip->reg_lock);
2020                                 snd_pcm_period_elapsed(azx_dev->substream);
2021                                 spin_lock(&chip->reg_lock);
2022                         } else if (ok < 0) {
2023                                 pending = 0;    /* too early */
2024                         } else
2025                                 pending++;
2026                 }
2027                 spin_unlock_irq(&chip->reg_lock);
2028                 if (!pending)
2029                         return;
2030                 msleep(1);
2031         }
2032 }
2033 
2034 /* clear irq_pending flags and assure no on-going workq */
2035 static void azx_clear_irq_pending(struct azx *chip)
2036 {
2037         int i;
2038 
2039         spin_lock_irq(&chip->reg_lock);
2040         for (i = 0; i < chip->num_streams; i++)
2041                 chip->azx_dev[i].irq_pending = 0;
2042         spin_unlock_irq(&chip->reg_lock);
2043 }
2044 
2045 static struct snd_pcm_ops azx_pcm_ops = {
2046         .open = azx_pcm_open,
2047         .close = azx_pcm_close,
2048         .ioctl = snd_pcm_lib_ioctl,
2049         .hw_params = azx_pcm_hw_params,
2050         .hw_free = azx_pcm_hw_free,
2051         .prepare = azx_pcm_prepare,
2052         .trigger = azx_pcm_trigger,
2053         .pointer = azx_pcm_pointer,
2054         .page = snd_pcm_sgbuf_ops_page,
2055 };
2056 
2057 static void azx_pcm_free(struct snd_pcm *pcm)
2058 {
2059         struct azx_pcm *apcm = pcm->private_data;
2060         if (apcm) {
2061                 apcm->chip->pcm[pcm->device] = NULL;
2062                 kfree(apcm);
2063         }
2064 }
2065 
2066 static int
2067 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2068                       struct hda_pcm *cpcm)
2069 {
2070         struct azx *chip = bus->private_data;
2071         struct snd_pcm *pcm;
2072         struct azx_pcm *apcm;
2073         int pcm_dev = cpcm->device;
2074         int s, err;
2075 
2076         if (pcm_dev >= HDA_MAX_PCMS) {
2077                 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
2078                            pcm_dev);
2079                 return -EINVAL;
2080         }
2081         if (chip->pcm[pcm_dev]) {
2082                 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2083                 return -EBUSY;
2084         }
2085         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2086                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2087                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2088                           &pcm);
2089         if (err < 0)
2090                 return err;
2091         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2092         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2093         if (apcm == NULL)
2094                 return -ENOMEM;
2095         apcm->chip = chip;
2096         apcm->codec = codec;
2097         pcm->private_data = apcm;
2098         pcm->private_free = azx_pcm_free;
2099         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2100                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2101         chip->pcm[pcm_dev] = pcm;
2102         cpcm->pcm = pcm;
2103         for (s = 0; s < 2; s++) {
2104                 apcm->hinfo[s] = &cpcm->stream[s];
2105                 if (cpcm->stream[s].substreams)
2106                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2107         }
2108         /* buffer pre-allocation */
2109         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2110                                               snd_dma_pci_data(chip->pci),
2111                                               1024 * 64, 32 * 1024 * 1024);
2112         return 0;
2113 }
2114 
2115 /*
2116  * mixer creation - all stuff is implemented in hda module
2117  */
2118 static int __devinit azx_mixer_create(struct azx *chip)
2119 {
2120         return snd_hda_build_controls(chip->bus);
2121 }
2122 
2123 
2124 /*
2125  * initialize SD streams
2126  */
2127 static int __devinit azx_init_stream(struct azx *chip)
2128 {
2129         int i;
2130 
2131         /* initialize each stream (aka device)
2132          * assign the starting bdl address to each stream (device)
2133          * and initialize
2134          */
2135         for (i = 0; i < chip->num_streams; i++) {
2136                 struct azx_dev *azx_dev = &chip->azx_dev[i];
2137                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2138                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2139                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2140                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2141                 azx_dev->sd_int_sta_mask = 1 << i;
2142                 /* stream tag: must be non-zero and unique */
2143                 azx_dev->index = i;
2144                 azx_dev->stream_tag = i + 1;
2145         }
2146 
2147         return 0;
2148 }
2149 
2150 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2151 {
2152         if (request_irq(chip->pci->irq, azx_interrupt,
2153                         chip->msi ? 0 : IRQF_SHARED,
2154                         "hda_intel", chip)) {
2155                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2156                        "disabling device\n", chip->pci->irq);
2157                 if (do_disconnect)
2158                         snd_card_disconnect(chip->card);
2159                 return -1;
2160         }
2161         chip->irq = chip->pci->irq;
2162         pci_intx(chip->pci, !chip->msi);
2163         return 0;
2164 }
2165 
2166 
2167 static void azx_stop_chip(struct azx *chip)
2168 {
2169         if (!chip->initialized)
2170                 return;
2171 
2172         /* disable interrupts */
2173         azx_int_disable(chip);
2174         azx_int_clear(chip);
2175 
2176         /* disable CORB/RIRB */
2177         azx_free_cmd_io(chip);
2178 
2179         /* disable position buffer */
2180         azx_writel(chip, DPLBASE, 0);
2181         azx_writel(chip, DPUBASE, 0);
2182 
2183         chip->initialized = 0;
2184 }
2185 
2186 #ifdef CONFIG_SND_HDA_POWER_SAVE
2187 /* power-up/down the controller */
2188 static void azx_power_notify(struct hda_bus *bus)
2189 {
2190         struct azx *chip = bus->private_data;
2191         struct hda_codec *c;
2192         int power_on = 0;
2193 
2194         list_for_each_entry(c, &bus->codec_list, list) {
2195                 if (c->power_on) {
2196                         power_on = 1;
2197                         break;
2198                 }
2199         }
2200         if (power_on)
2201                 azx_init_chip(chip, 1);
2202         else if (chip->running && power_save_controller &&
2203                  !bus->power_keep_link_on)
2204                 azx_stop_chip(chip);
2205 }
2206 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2207 
2208 #ifdef CONFIG_PM
2209 /*
2210  * power management
2211  */
2212 
2213 static int snd_hda_codecs_inuse(struct hda_bus *bus)
2214 {
2215         struct hda_codec *codec;
2216 
2217         list_for_each_entry(codec, &bus->codec_list, list) {
2218                 if (snd_hda_codec_needs_resume(codec))
2219                         return 1;
2220         }
2221         return 0;
2222 }
2223 
2224 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
2225 {
2226         struct snd_card *card = pci_get_drvdata(pci);
2227         struct azx *chip = card->private_data;
2228         int i;
2229 
2230         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2231         azx_clear_irq_pending(chip);
2232         for (i = 0; i < HDA_MAX_PCMS; i++)
2233                 snd_pcm_suspend_all(chip->pcm[i]);
2234         if (chip->initialized)
2235                 snd_hda_suspend(chip->bus);
2236         azx_stop_chip(chip);
2237         if (chip->irq >= 0) {
2238                 free_irq(chip->irq, chip);
2239                 chip->irq = -1;
2240         }
2241         if (chip->msi)
2242                 pci_disable_msi(chip->pci);
2243         pci_disable_device(pci);
2244         pci_save_state(pci);
2245         pci_set_power_state(pci, pci_choose_state(pci, state));
2246         return 0;
2247 }
2248 
2249 static int azx_resume(struct pci_dev *pci)
2250 {
2251         struct snd_card *card = pci_get_drvdata(pci);
2252         struct azx *chip = card->private_data;
2253 
2254         pci_set_power_state(pci, PCI_D0);
2255         pci_restore_state(pci);
2256         if (pci_enable_device(pci) < 0) {
2257                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2258                        "disabling device\n");
2259                 snd_card_disconnect(card);
2260                 return -EIO;
2261         }
2262         pci_set_master(pci);
2263         if (chip->msi)
2264                 if (pci_enable_msi(pci) < 0)
2265                         chip->msi = 0;
2266         if (azx_acquire_irq(chip, 1) < 0)
2267                 return -EIO;
2268         azx_init_pci(chip);
2269 
2270         if (snd_hda_codecs_inuse(chip->bus))
2271                 azx_init_chip(chip, 1);
2272 
2273         snd_hda_resume(chip->bus);
2274         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2275         return 0;
2276 }
2277 #endif /* CONFIG_PM */
2278 
2279 
2280 /*
2281  * reboot notifier for hang-up problem at power-down
2282  */
2283 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2284 {
2285         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2286         snd_hda_bus_reboot_notify(chip->bus);
2287         azx_stop_chip(chip);
2288         return NOTIFY_OK;
2289 }
2290 
2291 static void azx_notifier_register(struct azx *chip)
2292 {
2293         chip->reboot_notifier.notifier_call = azx_halt;
2294         register_reboot_notifier(&chip->reboot_notifier);
2295 }
2296 
2297 static void azx_notifier_unregister(struct azx *chip)
2298 {
2299         if (chip->reboot_notifier.notifier_call)
2300                 unregister_reboot_notifier(&chip->reboot_notifier);
2301 }
2302 
2303 /*
2304  * destructor
2305  */
2306 static int azx_free(struct azx *chip)
2307 {
2308         int i;
2309 
2310         azx_notifier_unregister(chip);
2311 
2312         if (chip->initialized) {
2313                 azx_clear_irq_pending(chip);
2314                 for (i = 0; i < chip->num_streams; i++)
2315                         azx_stream_stop(chip, &chip->azx_dev[i]);
2316                 azx_stop_chip(chip);
2317         }
2318 
2319         if (chip->irq >= 0)
2320                 free_irq(chip->irq, (void*)chip);
2321         if (chip->msi)
2322                 pci_disable_msi(chip->pci);
2323         if (chip->remap_addr)
2324                 iounmap(chip->remap_addr);
2325 
2326         if (chip->azx_dev) {
2327                 for (i = 0; i < chip->num_streams; i++)
2328                         if (chip->azx_dev[i].bdl.area)
2329                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2330         }
2331         if (chip->rb.area)
2332                 snd_dma_free_pages(&chip->rb);
2333         if (chip->posbuf.area)
2334                 snd_dma_free_pages(&chip->posbuf);
2335         pci_release_regions(chip->pci);
2336         pci_disable_device(chip->pci);
2337         kfree(chip->azx_dev);
2338         kfree(chip);
2339 
2340         return 0;
2341 }
2342 
2343 static int azx_dev_free(struct snd_device *device)
2344 {
2345         return azx_free(device->device_data);
2346 }
2347 
2348 /*
2349  * white/black-listing for position_fix
2350  */
2351 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2352         SND_PCI_QUIRK(0x1025, 0x009f, "Acer Aspire 5110", POS_FIX_LPIB),
2353         SND_PCI_QUIRK(0x1025, 0x026f, "Acer Aspire 5538", POS_FIX_LPIB),
2354         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2355         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2356         SND_PCI_QUIRK(0x1028, 0x01f6, "Dell Latitude 131L", POS_FIX_LPIB),
2357         SND_PCI_QUIRK(0x1028, 0x02c6, "Dell Inspiron 1010", POS_FIX_LPIB),
2358         SND_PCI_QUIRK(0x1028, 0x0470, "Dell Inspiron 1120", POS_FIX_LPIB),
2359         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2360         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2361         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
2362         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
2363         SND_PCI_QUIRK(0x1043, 0x8410, "ASUS", POS_FIX_LPIB),
2364         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
2365         SND_PCI_QUIRK(0x1106, 0x3288, "ASUS M2V-MX SE", POS_FIX_LPIB),
2366         SND_PCI_QUIRK(0x1179, 0xff10, "Toshiba A100-259", POS_FIX_LPIB),
2367         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
2368         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
2369         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2370         SND_PCI_QUIRK(0x1565, 0x820f, "Biostar Microtech", POS_FIX_LPIB),
2371         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
2372         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
2373         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
2374         SND_PCI_QUIRK(0x8086, 0xd601, "eMachines T5212", POS_FIX_LPIB),
2375         {}
2376 };
2377 
2378 static int __devinit check_position_fix(struct azx *chip, int fix)
2379 {
2380         const struct snd_pci_quirk *q;
2381 
2382         switch (fix) {
2383         case POS_FIX_LPIB:
2384         case POS_FIX_POSBUF:
2385         case POS_FIX_VIACOMBO:
2386                 return fix;
2387         }
2388 
2389         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2390         if (q) {
2391                 printk(KERN_INFO
2392                        "hda_intel: position_fix set to %d "
2393                        "for device %04x:%04x\n",
2394                        q->value, q->subvendor, q->subdevice);
2395                 return q->value;
2396         }
2397 
2398         /* Check VIA/ATI HD Audio Controller exist */
2399         if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
2400                 snd_printd(SFX "Using VIACOMBO position fix\n");
2401                 return POS_FIX_VIACOMBO;
2402         }
2403         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
2404                 snd_printd(SFX "Using LPIB position fix\n");
2405                 return POS_FIX_LPIB;
2406         }
2407         return POS_FIX_AUTO;
2408 }
2409 
2410 /*
2411  * black-lists for probe_mask
2412  */
2413 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2414         /* Thinkpad often breaks the controller communication when accessing
2415          * to the non-working (or non-existing) modem codec slot.
2416          */
2417         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2418         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2419         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2420         /* broken BIOS */
2421         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2422         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2423         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2424         /* forced codec slots */
2425         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2426         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2427         {}
2428 };
2429 
2430 #define AZX_FORCE_CODEC_MASK    0x100
2431 
2432 static void __devinit check_probe_mask(struct azx *chip, int dev)
2433 {
2434         const struct snd_pci_quirk *q;
2435 
2436         chip->codec_probe_mask = probe_mask[dev];
2437         if (chip->codec_probe_mask == -1) {
2438                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2439                 if (q) {
2440                         printk(KERN_INFO
2441                                "hda_intel: probe_mask set to 0x%x "
2442                                "for device %04x:%04x\n",
2443                                q->value, q->subvendor, q->subdevice);
2444                         chip->codec_probe_mask = q->value;
2445                 }
2446         }
2447 
2448         /* check forced option */
2449         if (chip->codec_probe_mask != -1 &&
2450             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2451                 chip->codec_mask = chip->codec_probe_mask & 0xff;
2452                 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2453                        chip->codec_mask);
2454         }
2455 }
2456 
2457 /*
2458  * white/black-list for enable_msi
2459  */
2460 static struct snd_pci_quirk msi_black_list[] __devinitdata = {
2461         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
2462         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
2463         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
2464         SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
2465         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
2466         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
2467         {}
2468 };
2469 
2470 static void __devinit check_msi(struct azx *chip)
2471 {
2472         const struct snd_pci_quirk *q;
2473 
2474         if (enable_msi >= 0) {
2475                 chip->msi = !!enable_msi;
2476                 return;
2477         }
2478         chip->msi = 1;  /* enable MSI as default */
2479         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
2480         if (q) {
2481                 printk(KERN_INFO
2482                        "hda_intel: msi for device %04x:%04x set to %d\n",
2483                        q->subvendor, q->subdevice, q->value);
2484                 chip->msi = q->value;
2485                 return;
2486         }
2487 
2488         /* NVidia chipsets seem to cause troubles with MSI */
2489         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
2490                 printk(KERN_INFO "hda_intel: Disabling MSI\n");
2491                 chip->msi = 0;
2492         }
2493 }
2494 
2495 
2496 /*
2497  * constructor
2498  */
2499 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2500                                 int dev, unsigned int driver_caps,
2501                                 struct azx **rchip)
2502 {
2503         struct azx *chip;
2504         int i, err;
2505         unsigned short gcap;
2506         static struct snd_device_ops ops = {
2507                 .dev_free = azx_dev_free,
2508         };
2509 
2510         *rchip = NULL;
2511 
2512         err = pci_enable_device(pci);
2513         if (err < 0)
2514                 return err;
2515 
2516         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2517         if (!chip) {
2518                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2519                 pci_disable_device(pci);
2520                 return -ENOMEM;
2521         }
2522 
2523         spin_lock_init(&chip->reg_lock);
2524         mutex_init(&chip->open_mutex);
2525         chip->card = card;
2526         chip->pci = pci;
2527         chip->irq = -1;
2528         chip->driver_caps = driver_caps;
2529         chip->driver_type = driver_caps & 0xff;
2530         check_msi(chip);
2531         chip->dev_index = dev;
2532         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2533 
2534         chip->position_fix[0] = chip->position_fix[1] =
2535                 check_position_fix(chip, position_fix[dev]);
2536         check_probe_mask(chip, dev);
2537 
2538         chip->single_cmd = single_cmd;
2539 
2540         if (bdl_pos_adj[dev] < 0) {
2541                 switch (chip->driver_type) {
2542                 case AZX_DRIVER_ICH:
2543                 case AZX_DRIVER_PCH:
2544                         bdl_pos_adj[dev] = 1;
2545                         break;
2546                 default:
2547                         bdl_pos_adj[dev] = 32;
2548                         break;
2549                 }
2550         }
2551 
2552 #if BITS_PER_LONG != 64
2553         /* Fix up base address on ULI M5461 */
2554         if (chip->driver_type == AZX_DRIVER_ULI) {
2555                 u16 tmp3;
2556                 pci_read_config_word(pci, 0x40, &tmp3);
2557                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2558                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2559         }
2560 #endif
2561 
2562         err = pci_request_regions(pci, "ICH HD audio");
2563         if (err < 0) {
2564                 kfree(chip);
2565                 pci_disable_device(pci);
2566                 return err;
2567         }
2568 
2569         chip->addr = pci_resource_start(pci, 0);
2570         chip->remap_addr = pci_ioremap_bar(pci, 0);
2571         if (chip->remap_addr == NULL) {
2572                 snd_printk(KERN_ERR SFX "ioremap error\n");
2573                 err = -ENXIO;
2574                 goto errout;
2575         }
2576 
2577         if (chip->msi)
2578                 if (pci_enable_msi(pci) < 0)
2579                         chip->msi = 0;
2580 
2581         if (azx_acquire_irq(chip, 0) < 0) {
2582                 err = -EBUSY;
2583                 goto errout;
2584         }
2585 
2586         pci_set_master(pci);
2587         synchronize_irq(chip->irq);
2588 
2589         gcap = azx_readw(chip, GCAP);
2590         snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
2591 
2592         /* disable SB600 64bit support for safety */
2593         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
2594                 struct pci_dev *p_smbus;
2595                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2596                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2597                                          NULL);
2598                 if (p_smbus) {
2599                         if (p_smbus->revision < 0x30)
2600                                 gcap &= ~ICH6_GCAP_64OK;
2601                         pci_dev_put(p_smbus);
2602                 }
2603         }
2604 
2605         /* disable 64bit DMA address on some devices */
2606         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
2607                 snd_printd(SFX "Disabling 64bit DMA\n");
2608                 gcap &= ~ICH6_GCAP_64OK;
2609         }
2610 
2611         /* allow 64bit DMA address if supported by H/W */
2612         if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2613                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2614         else {
2615                 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2616                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2617         }
2618 
2619         /* read number of streams from GCAP register instead of using
2620          * hardcoded value
2621          */
2622         chip->capture_streams = (gcap >> 8) & 0x0f;
2623         chip->playback_streams = (gcap >> 12) & 0x0f;
2624         if (!chip->playback_streams && !chip->capture_streams) {
2625                 /* gcap didn't give any info, switching to old method */
2626 
2627                 switch (chip->driver_type) {
2628                 case AZX_DRIVER_ULI:
2629                         chip->playback_streams = ULI_NUM_PLAYBACK;
2630                         chip->capture_streams = ULI_NUM_CAPTURE;
2631                         break;
2632                 case AZX_DRIVER_ATIHDMI:
2633                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2634                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2635                         break;
2636                 case AZX_DRIVER_GENERIC:
2637                 default:
2638                         chip->playback_streams = ICH6_NUM_PLAYBACK;
2639                         chip->capture_streams = ICH6_NUM_CAPTURE;
2640                         break;
2641                 }
2642         }
2643         chip->capture_index_offset = 0;
2644         chip->playback_index_offset = chip->capture_streams;
2645         chip->num_streams = chip->playback_streams + chip->capture_streams;
2646         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2647                                 GFP_KERNEL);
2648         if (!chip->azx_dev) {
2649                 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
2650                 goto errout;
2651         }
2652 
2653         for (i = 0; i < chip->num_streams; i++) {
2654                 /* allocate memory for the BDL for each stream */
2655                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2656                                           snd_dma_pci_data(chip->pci),
2657                                           BDL_SIZE, &chip->azx_dev[i].bdl);
2658                 if (err < 0) {
2659                         snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2660                         goto errout;
2661                 }
2662         }
2663         /* allocate memory for the position buffer */
2664         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2665                                   snd_dma_pci_data(chip->pci),
2666                                   chip->num_streams * 8, &chip->posbuf);
2667         if (err < 0) {
2668                 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2669                 goto errout;
2670         }
2671         /* allocate CORB/RIRB */
2672         err = azx_alloc_cmd_io(chip);
2673         if (err < 0)
2674                 goto errout;
2675 
2676         /* initialize streams */
2677         azx_init_stream(chip);
2678 
2679         /* initialize chip */
2680         azx_init_pci(chip);
2681         azx_init_chip(chip, (probe_only[dev] & 2) == 0);
2682 
2683         /* codec detection */
2684         if (!chip->codec_mask) {
2685                 snd_printk(KERN_ERR SFX "no codecs found!\n");
2686                 err = -ENODEV;
2687                 goto errout;
2688         }
2689 
2690         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2691         if (err <0) {
2692                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2693                 goto errout;
2694         }
2695 
2696         strcpy(card->driver, "HDA-Intel");
2697         strlcpy(card->shortname, driver_short_names[chip->driver_type],
2698                 sizeof(card->shortname));
2699         snprintf(card->longname, sizeof(card->longname),
2700                  "%s at 0x%lx irq %i",
2701                  card->shortname, chip->addr, chip->irq);
2702 
2703         *rchip = chip;
2704         return 0;
2705 
2706  errout:
2707         azx_free(chip);
2708         return err;
2709 }
2710 
2711 static void power_down_all_codecs(struct azx *chip)
2712 {
2713 #ifdef CONFIG_SND_HDA_POWER_SAVE
2714         /* The codecs were powered up in snd_hda_codec_new().
2715          * Now all initialization done, so turn them down if possible
2716          */
2717         struct hda_codec *codec;
2718         list_for_each_entry(codec, &chip->bus->codec_list, list) {
2719                 snd_hda_power_down(codec);
2720         }
2721 #endif
2722 }
2723 
2724 static int __devinit azx_probe(struct pci_dev *pci,
2725                                const struct pci_device_id *pci_id)
2726 {
2727         static int dev;
2728         struct snd_card *card;
2729         struct azx *chip;
2730         int err;
2731 
2732         if (dev >= SNDRV_CARDS)
2733                 return -ENODEV;
2734         if (!enable[dev]) {
2735                 dev++;
2736                 return -ENOENT;
2737         }
2738 
2739         err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2740         if (err < 0) {
2741                 snd_printk(KERN_ERR SFX "Error creating card!\n");
2742                 return err;
2743         }
2744 
2745         /* set this here since it's referred in snd_hda_load_patch() */
2746         snd_card_set_dev(card, &pci->dev);
2747 
2748         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2749         if (err < 0)
2750                 goto out_free;
2751         card->private_data = chip;
2752 
2753 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2754         chip->beep_mode = beep_mode[dev];
2755 #endif
2756 
2757         /* create codec instances */
2758         err = azx_codec_create(chip, model[dev]);
2759         if (err < 0)
2760                 goto out_free;
2761 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2762         if (patch[dev] && *patch[dev]) {
2763                 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
2764                            patch[dev]);
2765                 err = snd_hda_load_patch(chip->bus, patch[dev]);
2766                 if (err < 0)
2767                         goto out_free;
2768         }
2769 #endif
2770         if ((probe_only[dev] & 1) == 0) {
2771                 err = azx_codec_configure(chip);
2772                 if (err < 0)
2773                         goto out_free;
2774         }
2775 
2776         /* create PCM streams */
2777         err = snd_hda_build_pcms(chip->bus);
2778         if (err < 0)
2779                 goto out_free;
2780 
2781         /* create mixer controls */
2782         err = azx_mixer_create(chip);
2783         if (err < 0)
2784                 goto out_free;
2785 
2786         err = snd_card_register(card);
2787         if (err < 0)
2788                 goto out_free;
2789 
2790         pci_set_drvdata(pci, card);
2791         chip->running = 1;
2792         power_down_all_codecs(chip);
2793         azx_notifier_register(chip);
2794 
2795         dev++;
2796         return err;
2797 out_free:
2798         snd_card_free(card);
2799         return err;
2800 }
2801 
2802 static void __devexit azx_remove(struct pci_dev *pci)
2803 {
2804         snd_card_free(pci_get_drvdata(pci));
2805         pci_set_drvdata(pci, NULL);
2806 }
2807 
2808 /* PCI IDs */
2809 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
2810         /* CPT */
2811         { PCI_DEVICE(0x8086, 0x1c20),
2812           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP },
2813         /* PBG */
2814         { PCI_DEVICE(0x8086, 0x1d20),
2815           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP },
2816         /* Panther Point */
2817         { PCI_DEVICE(0x8086, 0x1e20),
2818           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP },
2819         /* SCH */
2820         { PCI_DEVICE(0x8086, 0x811b),
2821           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP },
2822         /* Generic Intel */
2823         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2824           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2825           .class_mask = 0xffffff,
2826           .driver_data = AZX_DRIVER_ICH },
2827         /* ATI SB 450/600/700/800/900 */
2828         { PCI_DEVICE(0x1002, 0x437b),
2829           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2830         { PCI_DEVICE(0x1002, 0x4383),
2831           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2832         /* AMD Hudson */
2833         { PCI_DEVICE(0x1022, 0x780d),
2834           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2835         /* ATI HDMI */
2836         { PCI_DEVICE(0x1002, 0x793b),
2837           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2838         { PCI_DEVICE(0x1002, 0x7919),
2839           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2840         { PCI_DEVICE(0x1002, 0x960f),
2841           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2842         { PCI_DEVICE(0x1002, 0x970f),
2843           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2844         { PCI_DEVICE(0x1002, 0xaa00),
2845           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2846         { PCI_DEVICE(0x1002, 0xaa08),
2847           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2848         { PCI_DEVICE(0x1002, 0xaa10),
2849           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2850         { PCI_DEVICE(0x1002, 0xaa18),
2851           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2852         { PCI_DEVICE(0x1002, 0xaa20),
2853           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2854         { PCI_DEVICE(0x1002, 0xaa28),
2855           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2856         { PCI_DEVICE(0x1002, 0xaa30),
2857           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2858         { PCI_DEVICE(0x1002, 0xaa38),
2859           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2860         { PCI_DEVICE(0x1002, 0xaa40),
2861           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2862         { PCI_DEVICE(0x1002, 0xaa48),
2863           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2864         /* VIA VT8251/VT8237A */
2865         { PCI_DEVICE(0x1106, 0x3288),
2866           .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
2867         /* SIS966 */
2868         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2869         /* ULI M5461 */
2870         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2871         /* NVIDIA MCP */
2872         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2873           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2874           .class_mask = 0xffffff,
2875           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2876         /* Teradici */
2877         { PCI_DEVICE(0x6549, 0x1200),
2878           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2879         /* Creative X-Fi (CA0110-IBG) */
2880 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
2881         /* the following entry conflicts with snd-ctxfi driver,
2882          * as ctxfi driver mutates from HD-audio to native mode with
2883          * a special command sequence.
2884          */
2885         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2886           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2887           .class_mask = 0xffffff,
2888           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2889           AZX_DCAPS_RIRB_PRE_DELAY },
2890 #else
2891         /* this entry seems still valid -- i.e. without emu20kx chip */
2892         { PCI_DEVICE(0x1102, 0x0009),
2893           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2894           AZX_DCAPS_RIRB_PRE_DELAY },
2895 #endif
2896         /* Vortex86MX */
2897         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2898         /* VMware HDAudio */
2899         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2900         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2901         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2902           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2903           .class_mask = 0xffffff,
2904           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2905         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2906           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2907           .class_mask = 0xffffff,
2908           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2909         { 0, }
2910 };
2911 MODULE_DEVICE_TABLE(pci, azx_ids);
2912 
2913 /* pci_driver definition */
2914 static struct pci_driver driver = {
2915         .name = "HDA Intel",
2916         .id_table = azx_ids,
2917         .probe = azx_probe,
2918         .remove = __devexit_p(azx_remove),
2919 #ifdef CONFIG_PM
2920         .suspend = azx_suspend,
2921         .resume = azx_resume,
2922 #endif
2923 };
2924 
2925 static int __init alsa_card_azx_init(void)
2926 {
2927         return pci_register_driver(&driver);
2928 }
2929 
2930 static void __exit alsa_card_azx_exit(void)
2931 {
2932         pci_unregister_driver(&driver);
2933 }
2934 
2935 module_init(alsa_card_azx_init)
2936 module_exit(alsa_card_azx_exit)
2937 

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