1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 *
4 * hda_intel.c - Implementation of primary alsa driver code base
5 * for Intel HD Audio.
6 *
7 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 *
9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
10 * PeiSen Hou <pshou@realtek.com.tw>
11 *
12 * CONTACTS:
13 *
14 * Matt Jared matt.jared@intel.com
15 * Andy Kopp andy.kopp@intel.com
16 * Dan Kogan dan.d.kogan@intel.com
17 *
18 * CHANGES:
19 *
20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
21 */
22
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/moduleparam.h>
29 #include <linux/init.h>
30 #include <linux/slab.h>
31 #include <linux/pci.h>
32 #include <linux/mutex.h>
33 #include <linux/io.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/clocksource.h>
36 #include <linux/time.h>
37 #include <linux/completion.h>
38 #include <linux/acpi.h>
39 #include <linux/pgtable.h>
40
41 #ifdef CONFIG_X86
42 /* for snoop control */
43 #include <asm/set_memory.h>
44 #include <asm/cpufeature.h>
45 #endif
46 #include <sound/core.h>
47 #include <sound/initval.h>
48 #include <sound/hdaudio.h>
49 #include <sound/hda_i915.h>
50 #include <sound/intel-dsp-config.h>
51 #include <linux/vgaarb.h>
52 #include <linux/vga_switcheroo.h>
53 #include <linux/firmware.h>
54 #include <sound/hda_codec.h>
55 #include "hda_controller.h"
56 #include "hda_intel.h"
57
58 #define CREATE_TRACE_POINTS
59 #include "hda_intel_trace.h"
60
61 /* position fix mode */
62 enum {
63 POS_FIX_AUTO,
64 POS_FIX_LPIB,
65 POS_FIX_POSBUF,
66 POS_FIX_VIACOMBO,
67 POS_FIX_COMBO,
68 POS_FIX_SKL,
69 POS_FIX_FIFO,
70 };
71
72 /* Defines for ATI HD Audio support in SB450 south bridge */
73 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
74 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
75
76 /* Defines for Nvidia HDA support */
77 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
78 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
79 #define NVIDIA_HDA_ISTRM_COH 0x4d
80 #define NVIDIA_HDA_OSTRM_COH 0x4c
81 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
82
83 /* Defines for Intel SCH HDA snoop control */
84 #define INTEL_HDA_CGCTL 0x48
85 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
86 #define INTEL_SCH_HDA_DEVC 0x78
87 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
88
89 /* Define VIA HD Audio Device ID*/
90 #define VIA_HDAC_DEVICE_ID 0x3288
91
92 /* max number of SDs */
93 /* ICH, ATI and VIA have 4 playback and 4 capture */
94 #define ICH6_NUM_CAPTURE 4
95 #define ICH6_NUM_PLAYBACK 4
96
97 /* ULI has 6 playback and 5 capture */
98 #define ULI_NUM_CAPTURE 5
99 #define ULI_NUM_PLAYBACK 6
100
101 /* ATI HDMI may have up to 8 playbacks and 0 capture */
102 #define ATIHDMI_NUM_CAPTURE 0
103 #define ATIHDMI_NUM_PLAYBACK 8
104
105 /* TERA has 4 playback and 3 capture */
106 #define TERA_NUM_CAPTURE 3
107 #define TERA_NUM_PLAYBACK 4
108
109
110 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
111 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
112 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
113 static char *model[SNDRV_CARDS];
114 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
115 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
116 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
117 static int probe_only[SNDRV_CARDS];
118 static int jackpoll_ms[SNDRV_CARDS];
119 static int single_cmd = -1;
120 static int enable_msi = -1;
121 #ifdef CONFIG_SND_HDA_PATCH_LOADER
122 static char *patch[SNDRV_CARDS];
123 #endif
124 #ifdef CONFIG_SND_HDA_INPUT_BEEP
125 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
126 CONFIG_SND_HDA_INPUT_BEEP_MODE};
127 #endif
128 static bool dmic_detect = 1;
129
130 module_param_array(index, int, NULL, 0444);
131 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
132 module_param_array(id, charp, NULL, 0444);
133 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
134 module_param_array(enable, bool, NULL, 0444);
135 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
136 module_param_array(model, charp, NULL, 0444);
137 MODULE_PARM_DESC(model, "Use the given board model.");
138 module_param_array(position_fix, int, NULL, 0444);
139 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
140 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO).");
141 module_param_array(bdl_pos_adj, int, NULL, 0644);
142 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
143 module_param_array(probe_mask, int, NULL, 0444);
144 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
145 module_param_array(probe_only, int, NULL, 0444);
146 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
147 module_param_array(jackpoll_ms, int, NULL, 0444);
148 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
149 module_param(single_cmd, bint, 0444);
150 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
151 "(for debugging only).");
152 module_param(enable_msi, bint, 0444);
153 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
154 #ifdef CONFIG_SND_HDA_PATCH_LOADER
155 module_param_array(patch, charp, NULL, 0444);
156 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
157 #endif
158 #ifdef CONFIG_SND_HDA_INPUT_BEEP
159 module_param_array(beep_mode, bool, NULL, 0444);
160 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
161 "(0=off, 1=on) (default=1).");
162 #endif
163 module_param(dmic_detect, bool, 0444);
164 MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) "
165 "(0=off, 1=on) (default=1); "
166 "deprecated, use snd-intel-dspcfg.dsp_driver option instead");
167
168 #ifdef CONFIG_PM
169 static int param_set_xint(const char *val, const struct kernel_param *kp);
170 static const struct kernel_param_ops param_ops_xint = {
171 .set = param_set_xint,
172 .get = param_get_int,
173 };
174 #define param_check_xint param_check_int
175
176 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
177 module_param(power_save, xint, 0644);
178 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
179 "(in second, 0 = disable).");
180
181 static bool pm_blacklist = true;
182 module_param(pm_blacklist, bool, 0644);
183 MODULE_PARM_DESC(pm_blacklist, "Enable power-management denylist");
184
185 /* reset the HD-audio controller in power save mode.
186 * this may give more power-saving, but will take longer time to
187 * wake up.
188 */
189 static bool power_save_controller = 1;
190 module_param(power_save_controller, bool, 0644);
191 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
192 #else
193 #define power_save 0
194 #endif /* CONFIG_PM */
195
196 static int align_buffer_size = -1;
197 module_param(align_buffer_size, bint, 0644);
198 MODULE_PARM_DESC(align_buffer_size,
199 "Force buffer and period sizes to be multiple of 128 bytes.");
200
201 #ifdef CONFIG_X86
202 static int hda_snoop = -1;
203 module_param_named(snoop, hda_snoop, bint, 0444);
204 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
205 #else
206 #define hda_snoop true
207 #endif
208
209
210 MODULE_LICENSE("GPL");
211 MODULE_DESCRIPTION("Intel HDA driver");
212
213 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
214 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
215 #define SUPPORT_VGA_SWITCHEROO
216 #endif
217 #endif
218
219
220 /*
221 */
222
223 /* driver types */
224 enum {
225 AZX_DRIVER_ICH,
226 AZX_DRIVER_PCH,
227 AZX_DRIVER_SCH,
228 AZX_DRIVER_SKL,
229 AZX_DRIVER_HDMI,
230 AZX_DRIVER_ATI,
231 AZX_DRIVER_ATIHDMI,
232 AZX_DRIVER_ATIHDMI_NS,
233 AZX_DRIVER_VIA,
234 AZX_DRIVER_SIS,
235 AZX_DRIVER_ULI,
236 AZX_DRIVER_NVIDIA,
237 AZX_DRIVER_TERA,
238 AZX_DRIVER_CTX,
239 AZX_DRIVER_CTHDA,
240 AZX_DRIVER_CMEDIA,
241 AZX_DRIVER_ZHAOXIN,
242 AZX_DRIVER_GENERIC,
243 AZX_NUM_DRIVERS, /* keep this as last entry */
244 };
245
246 #define azx_get_snoop_type(chip) \
247 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
248 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
249
250 /* quirks for old Intel chipsets */
251 #define AZX_DCAPS_INTEL_ICH \
252 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
253
254 /* quirks for Intel PCH */
255 #define AZX_DCAPS_INTEL_PCH_BASE \
256 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
257 AZX_DCAPS_SNOOP_TYPE(SCH))
258
259 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
260 #define AZX_DCAPS_INTEL_PCH_NOPM \
261 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
262
263 /* PCH for HSW/BDW; with runtime PM */
264 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
265 #define AZX_DCAPS_INTEL_PCH \
266 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
267
268 /* HSW HDMI */
269 #define AZX_DCAPS_INTEL_HASWELL \
270 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
271 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
272 AZX_DCAPS_SNOOP_TYPE(SCH))
273
274 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
275 #define AZX_DCAPS_INTEL_BROADWELL \
276 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
277 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
278 AZX_DCAPS_SNOOP_TYPE(SCH))
279
280 #define AZX_DCAPS_INTEL_BAYTRAIL \
281 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
282
283 #define AZX_DCAPS_INTEL_BRASWELL \
284 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
285 AZX_DCAPS_I915_COMPONENT)
286
287 #define AZX_DCAPS_INTEL_SKYLAKE \
288 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
289 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
290
291 #define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE
292
293 /* quirks for ATI SB / AMD Hudson */
294 #define AZX_DCAPS_PRESET_ATI_SB \
295 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB |\
296 AZX_DCAPS_SNOOP_TYPE(ATI))
297
298 /* quirks for ATI/AMD HDMI */
299 #define AZX_DCAPS_PRESET_ATI_HDMI \
300 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB|\
301 AZX_DCAPS_NO_MSI64)
302
303 /* quirks for ATI HDMI with snoop off */
304 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
305 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
306
307 /* quirks for AMD SB */
308 #define AZX_DCAPS_PRESET_AMD_SB \
309 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_AMD_WORKAROUND |\
310 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME |\
311 AZX_DCAPS_RETRY_PROBE)
312
313 /* quirks for Nvidia */
314 #define AZX_DCAPS_PRESET_NVIDIA \
315 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
316 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
317
318 #define AZX_DCAPS_PRESET_CTHDA \
319 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
320 AZX_DCAPS_NO_64BIT |\
321 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
322
323 /*
324 * vga_switcheroo support
325 */
326 #ifdef SUPPORT_VGA_SWITCHEROO
327 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
328 #define needs_eld_notify_link(chip) ((chip)->bus.keep_power)
329 #else
330 #define use_vga_switcheroo(chip) 0
331 #define needs_eld_notify_link(chip) false
332 #endif
333
334 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
335 ((pci)->device == 0x0c0c) || \
336 ((pci)->device == 0x0d0c) || \
337 ((pci)->device == 0x160c) || \
338 ((pci)->device == 0x490d))
339
340 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
341
342 static const char * const driver_short_names[] = {
343 [AZX_DRIVER_ICH] = "HDA Intel",
344 [AZX_DRIVER_PCH] = "HDA Intel PCH",
345 [AZX_DRIVER_SCH] = "HDA Intel MID",
346 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
347 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
348 [AZX_DRIVER_ATI] = "HDA ATI SB",
349 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
350 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
351 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
352 [AZX_DRIVER_SIS] = "HDA SIS966",
353 [AZX_DRIVER_ULI] = "HDA ULI M5461",
354 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
355 [AZX_DRIVER_TERA] = "HDA Teradici",
356 [AZX_DRIVER_CTX] = "HDA Creative",
357 [AZX_DRIVER_CTHDA] = "HDA Creative",
358 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
359 [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin",
360 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
361 };
362
363 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
364 static void set_default_power_save(struct azx *chip);
365
366 /*
367 * initialize the PCI registers
368 */
369 /* update bits in a PCI register byte */
370 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
371 unsigned char mask, unsigned char val)
372 {
373 unsigned char data;
374
375 pci_read_config_byte(pci, reg, &data);
376 data &= ~mask;
377 data |= (val & mask);
378 pci_write_config_byte(pci, reg, data);
379 }
380
381 static void azx_init_pci(struct azx *chip)
382 {
383 int snoop_type = azx_get_snoop_type(chip);
384
385 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
386 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
387 * Ensuring these bits are 0 clears playback static on some HD Audio
388 * codecs.
389 * The PCI register TCSEL is defined in the Intel manuals.
390 */
391 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
392 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
393 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
394 }
395
396 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
397 * we need to enable snoop.
398 */
399 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
400 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
401 azx_snoop(chip));
402 update_pci_byte(chip->pci,
403 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
404 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
405 }
406
407 /* For NVIDIA HDA, enable snoop */
408 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
409 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
410 azx_snoop(chip));
411 update_pci_byte(chip->pci,
412 NVIDIA_HDA_TRANSREG_ADDR,
413 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
414 update_pci_byte(chip->pci,
415 NVIDIA_HDA_ISTRM_COH,
416 0x01, NVIDIA_HDA_ENABLE_COHBIT);
417 update_pci_byte(chip->pci,
418 NVIDIA_HDA_OSTRM_COH,
419 0x01, NVIDIA_HDA_ENABLE_COHBIT);
420 }
421
422 /* Enable SCH/PCH snoop if needed */
423 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
424 unsigned short snoop;
425 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
426 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
427 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
428 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
429 if (!azx_snoop(chip))
430 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
431 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
432 pci_read_config_word(chip->pci,
433 INTEL_SCH_HDA_DEVC, &snoop);
434 }
435 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
436 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
437 "Disabled" : "Enabled");
438 }
439 }
440
441 /*
442 * In BXT-P A0, HD-Audio DMA requests is later than expected,
443 * and makes an audio stream sensitive to system latencies when
444 * 24/32 bits are playing.
445 * Adjusting threshold of DMA fifo to force the DMA request
446 * sooner to improve latency tolerance at the expense of power.
447 */
448 static void bxt_reduce_dma_latency(struct azx *chip)
449 {
450 u32 val;
451
452 val = azx_readl(chip, VS_EM4L);
453 val &= (0x3 << 20);
454 azx_writel(chip, VS_EM4L, val);
455 }
456
457 /*
458 * ML_LCAP bits:
459 * bit 0: 6 MHz Supported
460 * bit 1: 12 MHz Supported
461 * bit 2: 24 MHz Supported
462 * bit 3: 48 MHz Supported
463 * bit 4: 96 MHz Supported
464 * bit 5: 192 MHz Supported
465 */
466 static int intel_get_lctl_scf(struct azx *chip)
467 {
468 struct hdac_bus *bus = azx_bus(chip);
469 static const int preferred_bits[] = { 2, 3, 1, 4, 5 };
470 u32 val, t;
471 int i;
472
473 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
474
475 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
476 t = preferred_bits[i];
477 if (val & (1 << t))
478 return t;
479 }
480
481 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
482 return 0;
483 }
484
485 static int intel_ml_lctl_set_power(struct azx *chip, int state)
486 {
487 struct hdac_bus *bus = azx_bus(chip);
488 u32 val;
489 int timeout;
490
491 /*
492 * the codecs are sharing the first link setting by default
493 * If other links are enabled for stream, they need similar fix
494 */
495 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
496 val &= ~AZX_MLCTL_SPA;
497 val |= state << AZX_MLCTL_SPA_SHIFT;
498 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
499 /* wait for CPA */
500 timeout = 50;
501 while (timeout) {
502 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
503 AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
504 return 0;
505 timeout--;
506 udelay(10);
507 }
508
509 return -1;
510 }
511
512 static void intel_init_lctl(struct azx *chip)
513 {
514 struct hdac_bus *bus = azx_bus(chip);
515 u32 val;
516 int ret;
517
518 /* 0. check lctl register value is correct or not */
519 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
520 /* if SCF is already set, let's use it */
521 if ((val & ML_LCTL_SCF_MASK) != 0)
522 return;
523
524 /*
525 * Before operating on SPA, CPA must match SPA.
526 * Any deviation may result in undefined behavior.
527 */
528 if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
529 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
530 return;
531
532 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
533 ret = intel_ml_lctl_set_power(chip, 0);
534 udelay(100);
535 if (ret)
536 goto set_spa;
537
538 /* 2. update SCF to select a properly audio clock*/
539 val &= ~ML_LCTL_SCF_MASK;
540 val |= intel_get_lctl_scf(chip);
541 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
542
543 set_spa:
544 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
545 intel_ml_lctl_set_power(chip, 1);
546 udelay(100);
547 }
548
549 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
550 {
551 struct hdac_bus *bus = azx_bus(chip);
552 struct pci_dev *pci = chip->pci;
553 u32 val;
554
555 snd_hdac_set_codec_wakeup(bus, true);
556 if (chip->driver_type == AZX_DRIVER_SKL) {
557 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
558 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
559 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
560 }
561 azx_init_chip(chip, full_reset);
562 if (chip->driver_type == AZX_DRIVER_SKL) {
563 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
564 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
565 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
566 }
567
568 snd_hdac_set_codec_wakeup(bus, false);
569
570 /* reduce dma latency to avoid noise */
571 if (IS_BXT(pci))
572 bxt_reduce_dma_latency(chip);
573
574 if (bus->mlcap != NULL)
575 intel_init_lctl(chip);
576 }
577
578 /* calculate runtime delay from LPIB */
579 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
580 unsigned int pos)
581 {
582 struct snd_pcm_substream *substream = azx_dev->core.substream;
583 int stream = substream->stream;
584 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
585 int delay;
586
587 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
588 delay = pos - lpib_pos;
589 else
590 delay = lpib_pos - pos;
591 if (delay < 0) {
592 if (delay >= azx_dev->core.delay_negative_threshold)
593 delay = 0;
594 else
595 delay += azx_dev->core.bufsize;
596 }
597
598 if (delay >= azx_dev->core.period_bytes) {
599 dev_info(chip->card->dev,
600 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
601 delay, azx_dev->core.period_bytes);
602 delay = 0;
603 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
604 chip->get_delay[stream] = NULL;
605 }
606
607 return bytes_to_frames(substream->runtime, delay);
608 }
609
610 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
611
612 /* called from IRQ */
613 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
614 {
615 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
616 int ok;
617
618 ok = azx_position_ok(chip, azx_dev);
619 if (ok == 1) {
620 azx_dev->irq_pending = 0;
621 return ok;
622 } else if (ok == 0) {
623 /* bogus IRQ, process it later */
624 azx_dev->irq_pending = 1;
625 schedule_work(&hda->irq_pending_work);
626 }
627 return 0;
628 }
629
630 #define display_power(chip, enable) \
631 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
632
633 /*
634 * Check whether the current DMA position is acceptable for updating
635 * periods. Returns non-zero if it's OK.
636 *
637 * Many HD-audio controllers appear pretty inaccurate about
638 * the update-IRQ timing. The IRQ is issued before actually the
639 * data is processed. So, we need to process it afterwords in a
640 * workqueue.
641 *
642 * Returns 1 if OK to proceed, 0 for delay handling, -1 for skipping update
643 */
644 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
645 {
646 struct snd_pcm_substream *substream = azx_dev->core.substream;
647 struct snd_pcm_runtime *runtime = substream->runtime;
648 int stream = substream->stream;
649 u32 wallclk;
650 unsigned int pos;
651 snd_pcm_uframes_t hwptr, target;
652
653 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
654 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
655 return -1; /* bogus (too early) interrupt */
656
657 if (chip->get_position[stream])
658 pos = chip->get_position[stream](chip, azx_dev);
659 else { /* use the position buffer as default */
660 pos = azx_get_pos_posbuf(chip, azx_dev);
661 if (!pos || pos == (u32)-1) {
662 dev_info(chip->card->dev,
663 "Invalid position buffer, using LPIB read method instead.\n");
664 chip->get_position[stream] = azx_get_pos_lpib;
665 if (chip->get_position[0] == azx_get_pos_lpib &&
666 chip->get_position[1] == azx_get_pos_lpib)
667 azx_bus(chip)->use_posbuf = false;
668 pos = azx_get_pos_lpib(chip, azx_dev);
669 chip->get_delay[stream] = NULL;
670 } else {
671 chip->get_position[stream] = azx_get_pos_posbuf;
672 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
673 chip->get_delay[stream] = azx_get_delay_from_lpib;
674 }
675 }
676
677 if (pos >= azx_dev->core.bufsize)
678 pos = 0;
679
680 if (WARN_ONCE(!azx_dev->core.period_bytes,
681 "hda-intel: zero azx_dev->period_bytes"))
682 return -1; /* this shouldn't happen! */
683 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
684 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
685 /* NG - it's below the first next period boundary */
686 return chip->bdl_pos_adj ? 0 : -1;
687 azx_dev->core.start_wallclk += wallclk;
688
689 if (azx_dev->core.no_period_wakeup)
690 return 1; /* OK, no need to check period boundary */
691
692 if (runtime->hw_ptr_base != runtime->hw_ptr_interrupt)
693 return 1; /* OK, already in hwptr updating process */
694
695 /* check whether the period gets really elapsed */
696 pos = bytes_to_frames(runtime, pos);
697 hwptr = runtime->hw_ptr_base + pos;
698 if (hwptr < runtime->status->hw_ptr)
699 hwptr += runtime->buffer_size;
700 target = runtime->hw_ptr_interrupt + runtime->period_size;
701 if (hwptr < target) {
702 /* too early wakeup, process it later */
703 return chip->bdl_pos_adj ? 0 : -1;
704 }
705
706 return 1; /* OK, it's fine */
707 }
708
709 /*
710 * The work for pending PCM period updates.
711 */
712 static void azx_irq_pending_work(struct work_struct *work)
713 {
714 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
715 struct azx *chip = &hda->chip;
716 struct hdac_bus *bus = azx_bus(chip);
717 struct hdac_stream *s;
718 int pending, ok;
719
720 if (!hda->irq_pending_warned) {
721 dev_info(chip->card->dev,
722 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
723 chip->card->number);
724 hda->irq_pending_warned = 1;
725 }
726
727 for (;;) {
728 pending = 0;
729 spin_lock_irq(&bus->reg_lock);
730 list_for_each_entry(s, &bus->stream_list, list) {
731 struct azx_dev *azx_dev = stream_to_azx_dev(s);
732 if (!azx_dev->irq_pending ||
733 !s->substream ||
734 !s->running)
735 continue;
736 ok = azx_position_ok(chip, azx_dev);
737 if (ok > 0) {
738 azx_dev->irq_pending = 0;
739 spin_unlock(&bus->reg_lock);
740 snd_pcm_period_elapsed(s->substream);
741 spin_lock(&bus->reg_lock);
742 } else if (ok < 0) {
743 pending = 0; /* too early */
744 } else
745 pending++;
746 }
747 spin_unlock_irq(&bus->reg_lock);
748 if (!pending)
749 return;
750 msleep(1);
751 }
752 }
753
754 /* clear irq_pending flags and assure no on-going workq */
755 static void azx_clear_irq_pending(struct azx *chip)
756 {
757 struct hdac_bus *bus = azx_bus(chip);
758 struct hdac_stream *s;
759
760 spin_lock_irq(&bus->reg_lock);
761 list_for_each_entry(s, &bus->stream_list, list) {
762 struct azx_dev *azx_dev = stream_to_azx_dev(s);
763 azx_dev->irq_pending = 0;
764 }
765 spin_unlock_irq(&bus->reg_lock);
766 }
767
768 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
769 {
770 struct hdac_bus *bus = azx_bus(chip);
771
772 if (request_irq(chip->pci->irq, azx_interrupt,
773 chip->msi ? 0 : IRQF_SHARED,
774 chip->card->irq_descr, chip)) {
775 dev_err(chip->card->dev,
776 "unable to grab IRQ %d, disabling device\n",
777 chip->pci->irq);
778 if (do_disconnect)
779 snd_card_disconnect(chip->card);
780 return -1;
781 }
782 bus->irq = chip->pci->irq;
783 chip->card->sync_irq = bus->irq;
784 pci_intx(chip->pci, !chip->msi);
785 return 0;
786 }
787
788 /* get the current DMA position with correction on VIA chips */
789 static unsigned int azx_via_get_position(struct azx *chip,
790 struct azx_dev *azx_dev)
791 {
792 unsigned int link_pos, mini_pos, bound_pos;
793 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
794 unsigned int fifo_size;
795
796 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
797 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
798 /* Playback, no problem using link position */
799 return link_pos;
800 }
801
802 /* Capture */
803 /* For new chipset,
804 * use mod to get the DMA position just like old chipset
805 */
806 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
807 mod_dma_pos %= azx_dev->core.period_bytes;
808
809 fifo_size = azx_stream(azx_dev)->fifo_size - 1;
810
811 if (azx_dev->insufficient) {
812 /* Link position never gather than FIFO size */
813 if (link_pos <= fifo_size)
814 return 0;
815
816 azx_dev->insufficient = 0;
817 }
818
819 if (link_pos <= fifo_size)
820 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
821 else
822 mini_pos = link_pos - fifo_size;
823
824 /* Find nearest previous boudary */
825 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
826 mod_link_pos = link_pos % azx_dev->core.period_bytes;
827 if (mod_link_pos >= fifo_size)
828 bound_pos = link_pos - mod_link_pos;
829 else if (mod_dma_pos >= mod_mini_pos)
830 bound_pos = mini_pos - mod_mini_pos;
831 else {
832 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
833 if (bound_pos >= azx_dev->core.bufsize)
834 bound_pos = 0;
835 }
836
837 /* Calculate real DMA position we want */
838 return bound_pos + mod_dma_pos;
839 }
840
841 #define AMD_FIFO_SIZE 32
842
843 /* get the current DMA position with FIFO size correction */
844 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev)
845 {
846 struct snd_pcm_substream *substream = azx_dev->core.substream;
847 struct snd_pcm_runtime *runtime = substream->runtime;
848 unsigned int pos, delay;
849
850 pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
851 if (!runtime)
852 return pos;
853
854 runtime->delay = AMD_FIFO_SIZE;
855 delay = frames_to_bytes(runtime, AMD_FIFO_SIZE);
856 if (azx_dev->insufficient) {
857 if (pos < delay) {
858 delay = pos;
859 runtime->delay = bytes_to_frames(runtime, pos);
860 } else {
861 azx_dev->insufficient = 0;
862 }
863 }
864
865 /* correct the DMA position for capture stream */
866 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
867 if (pos < delay)
868 pos += azx_dev->core.bufsize;
869 pos -= delay;
870 }
871
872 return pos;
873 }
874
875 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev,
876 unsigned int pos)
877 {
878 struct snd_pcm_substream *substream = azx_dev->core.substream;
879
880 /* just read back the calculated value in the above */
881 return substream->runtime->delay;
882 }
883
884 static void __azx_shutdown_chip(struct azx *chip, bool skip_link_reset)
885 {
886 azx_stop_chip(chip);
887 if (!skip_link_reset)
888 azx_enter_link_reset(chip);
889 azx_clear_irq_pending(chip);
890 display_power(chip, false);
891 }
892
893 #ifdef CONFIG_PM
894 static DEFINE_MUTEX(card_list_lock);
895 static LIST_HEAD(card_list);
896
897 static void azx_shutdown_chip(struct azx *chip)
898 {
899 __azx_shutdown_chip(chip, false);
900 }
901
902 static void azx_add_card_list(struct azx *chip)
903 {
904 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
905 mutex_lock(&card_list_lock);
906 list_add(&hda->list, &card_list);
907 mutex_unlock(&card_list_lock);
908 }
909
910 static void azx_del_card_list(struct azx *chip)
911 {
912 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
913 mutex_lock(&card_list_lock);
914 list_del_init(&hda->list);
915 mutex_unlock(&card_list_lock);
916 }
917
918 /* trigger power-save check at writing parameter */
919 static int param_set_xint(const char *val, const struct kernel_param *kp)
920 {
921 struct hda_intel *hda;
922 struct azx *chip;
923 int prev = power_save;
924 int ret = param_set_int(val, kp);
925
926 if (ret || prev == power_save)
927 return ret;
928
929 mutex_lock(&card_list_lock);
930 list_for_each_entry(hda, &card_list, list) {
931 chip = &hda->chip;
932 if (!hda->probe_continued || chip->disabled)
933 continue;
934 snd_hda_set_power_save(&chip->bus, power_save * 1000);
935 }
936 mutex_unlock(&card_list_lock);
937 return 0;
938 }
939
940 /*
941 * power management
942 */
943 static bool azx_is_pm_ready(struct snd_card *card)
944 {
945 struct azx *chip;
946 struct hda_intel *hda;
947
948 if (!card)
949 return false;
950 chip = card->private_data;
951 hda = container_of(chip, struct hda_intel, chip);
952 if (chip->disabled || hda->init_failed || !chip->running)
953 return false;
954 return true;
955 }
956
957 static void __azx_runtime_resume(struct azx *chip)
958 {
959 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
960 struct hdac_bus *bus = azx_bus(chip);
961 struct hda_codec *codec;
962 int status;
963
964 display_power(chip, true);
965 if (hda->need_i915_power)
966 snd_hdac_i915_set_bclk(bus);
967
968 /* Read STATESTS before controller reset */
969 status = azx_readw(chip, STATESTS);
970
971 azx_init_pci(chip);
972 hda_intel_init_chip(chip, true);
973
974 /* Avoid codec resume if runtime resume is for system suspend */
975 if (!chip->pm_prepared) {
976 list_for_each_codec(codec, &chip->bus) {
977 if (codec->relaxed_resume)
978 continue;
979
980 if (codec->forced_resume || (status & (1 << codec->addr)))
981 pm_request_resume(hda_codec_dev(codec));
982 }
983 }
984
985 /* power down again for link-controlled chips */
986 if (!hda->need_i915_power)
987 display_power(chip, false);
988 }
989
990 #ifdef CONFIG_PM_SLEEP
991 static int azx_prepare(struct device *dev)
992 {
993 struct snd_card *card = dev_get_drvdata(dev);
994 struct azx *chip;
995
996 if (!azx_is_pm_ready(card))
997 return 0;
998
999 chip = card->private_data;
1000 chip->pm_prepared = 1;
1001 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1002
1003 flush_work(&azx_bus(chip)->unsol_work);
1004
1005 /* HDA controller always requires different WAKEEN for runtime suspend
1006 * and system suspend, so don't use direct-complete here.
1007 */
1008 return 0;
1009 }
1010
1011 static void azx_complete(struct device *dev)
1012 {
1013 struct snd_card *card = dev_get_drvdata(dev);
1014 struct azx *chip;
1015
1016 if (!azx_is_pm_ready(card))
1017 return;
1018
1019 chip = card->private_data;
1020 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1021 chip->pm_prepared = 0;
1022 }
1023
1024 static int azx_suspend(struct device *dev)
1025 {
1026 struct snd_card *card = dev_get_drvdata(dev);
1027 struct azx *chip;
1028 struct hdac_bus *bus;
1029
1030 if (!azx_is_pm_ready(card))
1031 return 0;
1032
1033 chip = card->private_data;
1034 bus = azx_bus(chip);
1035 azx_shutdown_chip(chip);
1036 if (bus->irq >= 0) {
1037 free_irq(bus->irq, chip);
1038 bus->irq = -1;
1039 chip->card->sync_irq = -1;
1040 }
1041
1042 if (chip->msi)
1043 pci_disable_msi(chip->pci);
1044
1045 trace_azx_suspend(chip);
1046 return 0;
1047 }
1048
1049 static int azx_resume(struct device *dev)
1050 {
1051 struct snd_card *card = dev_get_drvdata(dev);
1052 struct azx *chip;
1053
1054 if (!azx_is_pm_ready(card))
1055 return 0;
1056
1057 chip = card->private_data;
1058 if (chip->msi)
1059 if (pci_enable_msi(chip->pci) < 0)
1060 chip->msi = 0;
1061 if (azx_acquire_irq(chip, 1) < 0)
1062 return -EIO;
1063
1064 __azx_runtime_resume(chip);
1065
1066 trace_azx_resume(chip);
1067 return 0;
1068 }
1069
1070 /* put codec down to D3 at hibernation for Intel SKL+;
1071 * otherwise BIOS may still access the codec and screw up the driver
1072 */
1073 static int azx_freeze_noirq(struct device *dev)
1074 {
1075 struct snd_card *card = dev_get_drvdata(dev);
1076 struct azx *chip = card->private_data;
1077 struct pci_dev *pci = to_pci_dev(dev);
1078
1079 if (!azx_is_pm_ready(card))
1080 return 0;
1081 if (chip->driver_type == AZX_DRIVER_SKL)
1082 pci_set_power_state(pci, PCI_D3hot);
1083
1084 return 0;
1085 }
1086
1087 static int azx_thaw_noirq(struct device *dev)
1088 {
1089 struct snd_card *card = dev_get_drvdata(dev);
1090 struct azx *chip = card->private_data;
1091 struct pci_dev *pci = to_pci_dev(dev);
1092
1093 if (!azx_is_pm_ready(card))
1094 return 0;
1095 if (chip->driver_type == AZX_DRIVER_SKL)
1096 pci_set_power_state(pci, PCI_D0);
1097
1098 return 0;
1099 }
1100 #endif /* CONFIG_PM_SLEEP */
1101
1102 static int azx_runtime_suspend(struct device *dev)
1103 {
1104 struct snd_card *card = dev_get_drvdata(dev);
1105 struct azx *chip;
1106
1107 if (!azx_is_pm_ready(card))
1108 return 0;
1109 chip = card->private_data;
1110
1111 /* enable controller wake up event */
1112 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | STATESTS_INT_MASK);
1113
1114 azx_shutdown_chip(chip);
1115 trace_azx_runtime_suspend(chip);
1116 return 0;
1117 }
1118
1119 static int azx_runtime_resume(struct device *dev)
1120 {
1121 struct snd_card *card = dev_get_drvdata(dev);
1122 struct azx *chip;
1123
1124 if (!azx_is_pm_ready(card))
1125 return 0;
1126 chip = card->private_data;
1127 __azx_runtime_resume(chip);
1128
1129 /* disable controller Wake Up event*/
1130 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & ~STATESTS_INT_MASK);
1131
1132 trace_azx_runtime_resume(chip);
1133 return 0;
1134 }
1135
1136 static int azx_runtime_idle(struct device *dev)
1137 {
1138 struct snd_card *card = dev_get_drvdata(dev);
1139 struct azx *chip;
1140 struct hda_intel *hda;
1141
1142 if (!card)
1143 return 0;
1144
1145 chip = card->private_data;
1146 hda = container_of(chip, struct hda_intel, chip);
1147 if (chip->disabled || hda->init_failed)
1148 return 0;
1149
1150 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1151 azx_bus(chip)->codec_powered || !chip->running)
1152 return -EBUSY;
1153
1154 /* ELD notification gets broken when HD-audio bus is off */
1155 if (needs_eld_notify_link(chip))
1156 return -EBUSY;
1157
1158 return 0;
1159 }
1160
1161 static const struct dev_pm_ops azx_pm = {
1162 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1163 #ifdef CONFIG_PM_SLEEP
1164 .prepare = azx_prepare,
1165 .complete = azx_complete,
1166 .freeze_noirq = azx_freeze_noirq,
1167 .thaw_noirq = azx_thaw_noirq,
1168 #endif
1169 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1170 };
1171
1172 #define AZX_PM_OPS &azx_pm
1173 #else
1174 #define azx_add_card_list(chip) /* NOP */
1175 #define azx_del_card_list(chip) /* NOP */
1176 #define AZX_PM_OPS NULL
1177 #endif /* CONFIG_PM */
1178
1179
1180 static int azx_probe_continue(struct azx *chip);
1181
1182 #ifdef SUPPORT_VGA_SWITCHEROO
1183 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1184
1185 static void azx_vs_set_state(struct pci_dev *pci,
1186 enum vga_switcheroo_state state)
1187 {
1188 struct snd_card *card = pci_get_drvdata(pci);
1189 struct azx *chip = card->private_data;
1190 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1191 struct hda_codec *codec;
1192 bool disabled;
1193
1194 wait_for_completion(&hda->probe_wait);
1195 if (hda->init_failed)
1196 return;
1197
1198 disabled = (state == VGA_SWITCHEROO_OFF);
1199 if (chip->disabled == disabled)
1200 return;
1201
1202 if (!hda->probe_continued) {
1203 chip->disabled = disabled;
1204 if (!disabled) {
1205 dev_info(chip->card->dev,
1206 "Start delayed initialization\n");
1207 if (azx_probe_continue(chip) < 0)
1208 dev_err(chip->card->dev, "initialization error\n");
1209 }
1210 } else {
1211 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1212 disabled ? "Disabling" : "Enabling");
1213 if (disabled) {
1214 list_for_each_codec(codec, &chip->bus) {
1215 pm_runtime_suspend(hda_codec_dev(codec));
1216 pm_runtime_disable(hda_codec_dev(codec));
1217 }
1218 pm_runtime_suspend(card->dev);
1219 pm_runtime_disable(card->dev);
1220 /* when we get suspended by vga_switcheroo we end up in D3cold,
1221 * however we have no ACPI handle, so pci/acpi can't put us there,
1222 * put ourselves there */
1223 pci->current_state = PCI_D3cold;
1224 chip->disabled = true;
1225 if (snd_hda_lock_devices(&chip->bus))
1226 dev_warn(chip->card->dev,
1227 "Cannot lock devices!\n");
1228 } else {
1229 snd_hda_unlock_devices(&chip->bus);
1230 chip->disabled = false;
1231 pm_runtime_enable(card->dev);
1232 list_for_each_codec(codec, &chip->bus) {
1233 pm_runtime_enable(hda_codec_dev(codec));
1234 pm_runtime_resume(hda_codec_dev(codec));
1235 }
1236 }
1237 }
1238 }
1239
1240 static bool azx_vs_can_switch(struct pci_dev *pci)
1241 {
1242 struct snd_card *card = pci_get_drvdata(pci);
1243 struct azx *chip = card->private_data;
1244 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1245
1246 wait_for_completion(&hda->probe_wait);
1247 if (hda->init_failed)
1248 return false;
1249 if (chip->disabled || !hda->probe_continued)
1250 return true;
1251 if (snd_hda_lock_devices(&chip->bus))
1252 return false;
1253 snd_hda_unlock_devices(&chip->bus);
1254 return true;
1255 }
1256
1257 /*
1258 * The discrete GPU cannot power down unless the HDA controller runtime
1259 * suspends, so activate runtime PM on codecs even if power_save == 0.
1260 */
1261 static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1262 {
1263 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1264 struct hda_codec *codec;
1265
1266 if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) {
1267 list_for_each_codec(codec, &chip->bus)
1268 codec->auto_runtime_pm = 1;
1269 /* reset the power save setup */
1270 if (chip->running)
1271 set_default_power_save(chip);
1272 }
1273 }
1274
1275 static void azx_vs_gpu_bound(struct pci_dev *pci,
1276 enum vga_switcheroo_client_id client_id)
1277 {
1278 struct snd_card *card = pci_get_drvdata(pci);
1279 struct azx *chip = card->private_data;
1280
1281 if (client_id == VGA_SWITCHEROO_DIS)
1282 chip->bus.keep_power = 0;
1283 setup_vga_switcheroo_runtime_pm(chip);
1284 }
1285
1286 static void init_vga_switcheroo(struct azx *chip)
1287 {
1288 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1289 struct pci_dev *p = get_bound_vga(chip->pci);
1290 struct pci_dev *parent;
1291 if (p) {
1292 dev_info(chip->card->dev,
1293 "Handle vga_switcheroo audio client\n");
1294 hda->use_vga_switcheroo = 1;
1295
1296 /* cleared in either gpu_bound op or codec probe, or when its
1297 * upstream port has _PR3 (i.e. dGPU).
1298 */
1299 parent = pci_upstream_bridge(p);
1300 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1;
1301 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1302 pci_dev_put(p);
1303 }
1304 }
1305
1306 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1307 .set_gpu_state = azx_vs_set_state,
1308 .can_switch = azx_vs_can_switch,
1309 .gpu_bound = azx_vs_gpu_bound,
1310 };
1311
1312 static int register_vga_switcheroo(struct azx *chip)
1313 {
1314 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1315 struct pci_dev *p;
1316 int err;
1317
1318 if (!hda->use_vga_switcheroo)
1319 return 0;
1320
1321 p = get_bound_vga(chip->pci);
1322 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1323 pci_dev_put(p);
1324
1325 if (err < 0)
1326 return err;
1327 hda->vga_switcheroo_registered = 1;
1328
1329 return 0;
1330 }
1331 #else
1332 #define init_vga_switcheroo(chip) /* NOP */
1333 #define register_vga_switcheroo(chip) 0
1334 #define check_hdmi_disabled(pci) false
1335 #define setup_vga_switcheroo_runtime_pm(chip) /* NOP */
1336 #endif /* SUPPORT_VGA_SWITCHER */
1337
1338 /*
1339 * destructor
1340 */
1341 static void azx_free(struct azx *chip)
1342 {
1343 struct pci_dev *pci = chip->pci;
1344 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1345 struct hdac_bus *bus = azx_bus(chip);
1346
1347 if (hda->freed)
1348 return;
1349
1350 if (azx_has_pm_runtime(chip) && chip->running)
1351 pm_runtime_get_noresume(&pci->dev);
1352 chip->running = 0;
1353
1354 azx_del_card_list(chip);
1355
1356 hda->init_failed = 1; /* to be sure */
1357 complete_all(&hda->probe_wait);
1358
1359 if (use_vga_switcheroo(hda)) {
1360 if (chip->disabled && hda->probe_continued)
1361 snd_hda_unlock_devices(&chip->bus);
1362 if (hda->vga_switcheroo_registered)
1363 vga_switcheroo_unregister_client(chip->pci);
1364 }
1365
1366 if (bus->chip_init) {
1367 azx_clear_irq_pending(chip);
1368 azx_stop_all_streams(chip);
1369 azx_stop_chip(chip);
1370 }
1371
1372 if (bus->irq >= 0)
1373 free_irq(bus->irq, (void*)chip);
1374 if (chip->msi)
1375 pci_disable_msi(chip->pci);
1376 iounmap(bus->remap_addr);
1377
1378 azx_free_stream_pages(chip);
1379 azx_free_streams(chip);
1380 snd_hdac_bus_exit(bus);
1381
1382 if (chip->region_requested)
1383 pci_release_regions(chip->pci);
1384
1385 pci_disable_device(chip->pci);
1386 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1387 release_firmware(chip->fw);
1388 #endif
1389 display_power(chip, false);
1390
1391 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1392 snd_hdac_i915_exit(bus);
1393
1394 hda->freed = 1;
1395 }
1396
1397 static int azx_dev_disconnect(struct snd_device *device)
1398 {
1399 struct azx *chip = device->device_data;
1400 struct hdac_bus *bus = azx_bus(chip);
1401
1402 chip->bus.shutdown = 1;
1403 cancel_work_sync(&bus->unsol_work);
1404
1405 return 0;
1406 }
1407
1408 static int azx_dev_free(struct snd_device *device)
1409 {
1410 azx_free(device->device_data);
1411 return 0;
1412 }
1413
1414 #ifdef SUPPORT_VGA_SWITCHEROO
1415 #ifdef CONFIG_ACPI
1416 /* ATPX is in the integrated GPU's namespace */
1417 static bool atpx_present(void)
1418 {
1419 struct pci_dev *pdev = NULL;
1420 acpi_handle dhandle, atpx_handle;
1421 acpi_status status;
1422
1423 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
1424 dhandle = ACPI_HANDLE(&pdev->dev);
1425 if (dhandle) {
1426 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
1427 if (ACPI_SUCCESS(status)) {
1428 pci_dev_put(pdev);
1429 return true;
1430 }
1431 }
1432 }
1433 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
1434 dhandle = ACPI_HANDLE(&pdev->dev);
1435 if (dhandle) {
1436 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
1437 if (ACPI_SUCCESS(status)) {
1438 pci_dev_put(pdev);
1439 return true;
1440 }
1441 }
1442 }
1443 return false;
1444 }
1445 #else
1446 static bool atpx_present(void)
1447 {
1448 return false;
1449 }
1450 #endif
1451
1452 /*
1453 * Check of disabled HDMI controller by vga_switcheroo
1454 */
1455 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1456 {
1457 struct pci_dev *p;
1458
1459 /* check only discrete GPU */
1460 switch (pci->vendor) {
1461 case PCI_VENDOR_ID_ATI:
1462 case PCI_VENDOR_ID_AMD:
1463 if (pci->devfn == 1) {
1464 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1465 pci->bus->number, 0);
1466 if (p) {
1467 /* ATPX is in the integrated GPU's ACPI namespace
1468 * rather than the dGPU's namespace. However,
1469 * the dGPU is the one who is involved in
1470 * vgaswitcheroo.
1471 */
1472 if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) &&
1473 atpx_present())
1474 return p;
1475 pci_dev_put(p);
1476 }
1477 }
1478 break;
1479 case PCI_VENDOR_ID_NVIDIA:
1480 if (pci->devfn == 1) {
1481 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1482 pci->bus->number, 0);
1483 if (p) {
1484 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
1485 return p;
1486 pci_dev_put(p);
1487 }
1488 }
1489 break;
1490 }
1491 return NULL;
1492 }
1493
1494 static bool check_hdmi_disabled(struct pci_dev *pci)
1495 {
1496 bool vga_inactive = false;
1497 struct pci_dev *p = get_bound_vga(pci);
1498
1499 if (p) {
1500 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1501 vga_inactive = true;
1502 pci_dev_put(p);
1503 }
1504 return vga_inactive;
1505 }
1506 #endif /* SUPPORT_VGA_SWITCHEROO */
1507
1508 /*
1509 * allow/deny-listing for position_fix
1510 */
1511 static const struct snd_pci_quirk position_fix_list[] = {
1512 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1513 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1514 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1515 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1516 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1517 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1518 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1519 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1520 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1521 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1522 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1523 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1524 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1525 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1526 {}
1527 };
1528
1529 static int check_position_fix(struct azx *chip, int fix)
1530 {
1531 const struct snd_pci_quirk *q;
1532
1533 switch (fix) {
1534 case POS_FIX_AUTO:
1535 case POS_FIX_LPIB:
1536 case POS_FIX_POSBUF:
1537 case POS_FIX_VIACOMBO:
1538 case POS_FIX_COMBO:
1539 case POS_FIX_SKL:
1540 case POS_FIX_FIFO:
1541 return fix;
1542 }
1543
1544 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1545 if (q) {
1546 dev_info(chip->card->dev,
1547 "position_fix set to %d for device %04x:%04x\n",
1548 q->value, q->subvendor, q->subdevice);
1549 return q->value;
1550 }
1551
1552 /* Check VIA/ATI HD Audio Controller exist */
1553 if (chip->driver_type == AZX_DRIVER_VIA) {
1554 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1555 return POS_FIX_VIACOMBO;
1556 }
1557 if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) {
1558 dev_dbg(chip->card->dev, "Using FIFO position fix\n");
1559 return POS_FIX_FIFO;
1560 }
1561 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1562 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1563 return POS_FIX_LPIB;
1564 }
1565 if (chip->driver_type == AZX_DRIVER_SKL) {
1566 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1567 return POS_FIX_SKL;
1568 }
1569 return POS_FIX_AUTO;
1570 }
1571
1572 static void assign_position_fix(struct azx *chip, int fix)
1573 {
1574 static const azx_get_pos_callback_t callbacks[] = {
1575 [POS_FIX_AUTO] = NULL,
1576 [POS_FIX_LPIB] = azx_get_pos_lpib,
1577 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1578 [POS_FIX_VIACOMBO] = azx_via_get_position,
1579 [POS_FIX_COMBO] = azx_get_pos_lpib,
1580 [POS_FIX_SKL] = azx_get_pos_posbuf,
1581 [POS_FIX_FIFO] = azx_get_pos_fifo,
1582 };
1583
1584 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1585
1586 /* combo mode uses LPIB only for playback */
1587 if (fix == POS_FIX_COMBO)
1588 chip->get_position[1] = NULL;
1589
1590 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1591 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1592 chip->get_delay[0] = chip->get_delay[1] =
1593 azx_get_delay_from_lpib;
1594 }
1595
1596 if (fix == POS_FIX_FIFO)
1597 chip->get_delay[0] = chip->get_delay[1] =
1598 azx_get_delay_from_fifo;
1599 }
1600
1601 /*
1602 * deny-lists for probe_mask
1603 */
1604 static const struct snd_pci_quirk probe_mask_list[] = {
1605 /* Thinkpad often breaks the controller communication when accessing
1606 * to the non-working (or non-existing) modem codec slot.
1607 */
1608 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1609 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1610 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1611 /* broken BIOS */
1612 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1613 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1614 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1615 /* forced codec slots */
1616 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1617 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1618 /* WinFast VP200 H (Teradici) user reported broken communication */
1619 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1620 {}
1621 };
1622
1623 #define AZX_FORCE_CODEC_MASK 0x100
1624
1625 static void check_probe_mask(struct azx *chip, int dev)
1626 {
1627 const struct snd_pci_quirk *q;
1628
1629 chip->codec_probe_mask = probe_mask[dev];
1630 if (chip->codec_probe_mask == -1) {
1631 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1632 if (q) {
1633 dev_info(chip->card->dev,
1634 "probe_mask set to 0x%x for device %04x:%04x\n",
1635 q->value, q->subvendor, q->subdevice);
1636 chip->codec_probe_mask = q->value;
1637 }
1638 }
1639
1640 /* check forced option */
1641 if (chip->codec_probe_mask != -1 &&
1642 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1643 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1644 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1645 (int)azx_bus(chip)->codec_mask);
1646 }
1647 }
1648
1649 /*
1650 * allow/deny-list for enable_msi
1651 */
1652 static const struct snd_pci_quirk msi_deny_list[] = {
1653 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1654 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1655 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1656 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1657 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1658 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1659 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1660 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1661 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1662 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1663 {}
1664 };
1665
1666 static void check_msi(struct azx *chip)
1667 {
1668 const struct snd_pci_quirk *q;
1669
1670 if (enable_msi >= 0) {
1671 chip->msi = !!enable_msi;
1672 return;
1673 }
1674 chip->msi = 1; /* enable MSI as default */
1675 q = snd_pci_quirk_lookup(chip->pci, msi_deny_list);
1676 if (q) {
1677 dev_info(chip->card->dev,
1678 "msi for device %04x:%04x set to %d\n",
1679 q->subvendor, q->subdevice, q->value);
1680 chip->msi = q->value;
1681 return;
1682 }
1683
1684 /* NVidia chipsets seem to cause troubles with MSI */
1685 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1686 dev_info(chip->card->dev, "Disabling MSI\n");
1687 chip->msi = 0;
1688 }
1689 }
1690
1691 /* check the snoop mode availability */
1692 static void azx_check_snoop_available(struct azx *chip)
1693 {
1694 int snoop = hda_snoop;
1695
1696 if (snoop >= 0) {
1697 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1698 snoop ? "snoop" : "non-snoop");
1699 chip->snoop = snoop;
1700 chip->uc_buffer = !snoop;
1701 return;
1702 }
1703
1704 snoop = true;
1705 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1706 chip->driver_type == AZX_DRIVER_VIA) {
1707 /* force to non-snoop mode for a new VIA controller
1708 * when BIOS is set
1709 */
1710 u8 val;
1711 pci_read_config_byte(chip->pci, 0x42, &val);
1712 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1713 chip->pci->revision == 0x20))
1714 snoop = false;
1715 }
1716
1717 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1718 snoop = false;
1719
1720 chip->snoop = snoop;
1721 if (!snoop) {
1722 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1723 /* C-Media requires non-cached pages only for CORB/RIRB */
1724 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1725 chip->uc_buffer = true;
1726 }
1727 }
1728
1729 static void azx_probe_work(struct work_struct *work)
1730 {
1731 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work.work);
1732 azx_probe_continue(&hda->chip);
1733 }
1734
1735 static int default_bdl_pos_adj(struct azx *chip)
1736 {
1737 /* some exceptions: Atoms seem problematic with value 1 */
1738 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1739 switch (chip->pci->device) {
1740 case 0x0f04: /* Baytrail */
1741 case 0x2284: /* Braswell */
1742 return 32;
1743 }
1744 }
1745
1746 switch (chip->driver_type) {
1747 case AZX_DRIVER_ICH:
1748 case AZX_DRIVER_PCH:
1749 return 1;
1750 default:
1751 return 32;
1752 }
1753 }
1754
1755 /*
1756 * constructor
1757 */
1758 static const struct hda_controller_ops pci_hda_ops;
1759
1760 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1761 int dev, unsigned int driver_caps,
1762 struct azx **rchip)
1763 {
1764 static const struct snd_device_ops ops = {
1765 .dev_disconnect = azx_dev_disconnect,
1766 .dev_free = azx_dev_free,
1767 };
1768 struct hda_intel *hda;
1769 struct azx *chip;
1770 int err;
1771
1772 *rchip = NULL;
1773
1774 err = pci_enable_device(pci);
1775 if (err < 0)
1776 return err;
1777
1778 hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL);
1779 if (!hda) {
1780 pci_disable_device(pci);
1781 return -ENOMEM;
1782 }
1783
1784 chip = &hda->chip;
1785 mutex_init(&chip->open_mutex);
1786 chip->card = card;
1787 chip->pci = pci;
1788 chip->ops = &pci_hda_ops;
1789 chip->driver_caps = driver_caps;
1790 chip->driver_type = driver_caps & 0xff;
1791 check_msi(chip);
1792 chip->dev_index = dev;
1793 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1794 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
1795 INIT_LIST_HEAD(&chip->pcm_list);
1796 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1797 INIT_LIST_HEAD(&hda->list);
1798 init_vga_switcheroo(chip);
1799 init_completion(&hda->probe_wait);
1800
1801 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1802
1803 check_probe_mask(chip, dev);
1804
1805 if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1806 chip->fallback_to_single_cmd = 1;
1807 else /* explicitly set to single_cmd or not */
1808 chip->single_cmd = single_cmd;
1809
1810 azx_check_snoop_available(chip);
1811
1812 if (bdl_pos_adj[dev] < 0)
1813 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1814 else
1815 chip->bdl_pos_adj = bdl_pos_adj[dev];
1816
1817 err = azx_bus_init(chip, model[dev]);
1818 if (err < 0) {
1819 pci_disable_device(pci);
1820 return err;
1821 }
1822
1823 /* use the non-cached pages in non-snoop mode */
1824 if (!azx_snoop(chip))
1825 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_UC;
1826
1827 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1828 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1829 chip->bus.core.needs_damn_long_delay = 1;
1830 }
1831
1832 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1833 if (err < 0) {
1834 dev_err(card->dev, "Error creating device [card]!\n");
1835 azx_free(chip);
1836 return err;
1837 }
1838
1839 /* continue probing in work context as may trigger request module */
1840 INIT_DELAYED_WORK(&hda->probe_work, azx_probe_work);
1841
1842 *rchip = chip;
1843
1844 return 0;
1845 }
1846
1847 static int azx_first_init(struct azx *chip)
1848 {
1849 int dev = chip->dev_index;
1850 struct pci_dev *pci = chip->pci;
1851 struct snd_card *card = chip->card;
1852 struct hdac_bus *bus = azx_bus(chip);
1853 int err;
1854 unsigned short gcap;
1855 unsigned int dma_bits = 64;
1856
1857 #if BITS_PER_LONG != 64
1858 /* Fix up base address on ULI M5461 */
1859 if (chip->driver_type == AZX_DRIVER_ULI) {
1860 u16 tmp3;
1861 pci_read_config_word(pci, 0x40, &tmp3);
1862 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1863 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1864 }
1865 #endif
1866
1867 err = pci_request_regions(pci, "ICH HD audio");
1868 if (err < 0)
1869 return err;
1870 chip->region_requested = 1;
1871
1872 bus->addr = pci_resource_start(pci, 0);
1873 bus->remap_addr = pci_ioremap_bar(pci, 0);
1874 if (bus->remap_addr == NULL) {
1875 dev_err(card->dev, "ioremap error\n");
1876 return -ENXIO;
1877 }
1878
1879 if (chip->driver_type == AZX_DRIVER_SKL)
1880 snd_hdac_bus_parse_capabilities(bus);
1881
1882 /*
1883 * Some Intel CPUs has always running timer (ART) feature and
1884 * controller may have Global time sync reporting capability, so
1885 * check both of these before declaring synchronized time reporting
1886 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1887 */
1888 chip->gts_present = false;
1889
1890 #ifdef CONFIG_X86
1891 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1892 chip->gts_present = true;
1893 #endif
1894
1895 if (chip->msi) {
1896 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1897 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1898 pci->no_64bit_msi = true;
1899 }
1900 if (pci_enable_msi(pci) < 0)
1901 chip->msi = 0;
1902 }
1903
1904 pci_set_master(pci);
1905
1906 gcap = azx_readw(chip, GCAP);
1907 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1908
1909 /* AMD devices support 40 or 48bit DMA, take the safe one */
1910 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1911 dma_bits = 40;
1912
1913 /* disable SB600 64bit support for safety */
1914 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1915 struct pci_dev *p_smbus;
1916 dma_bits = 40;
1917 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1918 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1919 NULL);
1920 if (p_smbus) {
1921 if (p_smbus->revision < 0x30)
1922 gcap &= ~AZX_GCAP_64OK;
1923 pci_dev_put(p_smbus);
1924 }
1925 }
1926
1927 /* NVidia hardware normally only supports up to 40 bits of DMA */
1928 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1929 dma_bits = 40;
1930
1931 /* disable 64bit DMA address on some devices */
1932 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1933 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1934 gcap &= ~AZX_GCAP_64OK;
1935 }
1936
1937 /* disable buffer size rounding to 128-byte multiples if supported */
1938 if (align_buffer_size >= 0)
1939 chip->align_buffer_size = !!align_buffer_size;
1940 else {
1941 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1942 chip->align_buffer_size = 0;
1943 else
1944 chip->align_buffer_size = 1;
1945 }
1946
1947 /* allow 64bit DMA address if supported by H/W */
1948 if (!(gcap & AZX_GCAP_64OK))
1949 dma_bits = 32;
1950 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(dma_bits)))
1951 dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32));
1952
1953 /* read number of streams from GCAP register instead of using
1954 * hardcoded value
1955 */
1956 chip->capture_streams = (gcap >> 8) & 0x0f;
1957 chip->playback_streams = (gcap >> 12) & 0x0f;
1958 if (!chip->playback_streams && !chip->capture_streams) {
1959 /* gcap didn't give any info, switching to old method */
1960
1961 switch (chip->driver_type) {
1962 case AZX_DRIVER_ULI:
1963 chip->playback_streams = ULI_NUM_PLAYBACK;
1964 chip->capture_streams = ULI_NUM_CAPTURE;
1965 break;
1966 case AZX_DRIVER_ATIHDMI:
1967 case AZX_DRIVER_ATIHDMI_NS:
1968 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1969 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1970 break;
1971 case AZX_DRIVER_GENERIC:
1972 default:
1973 chip->playback_streams = ICH6_NUM_PLAYBACK;
1974 chip->capture_streams = ICH6_NUM_CAPTURE;
1975 break;
1976 }
1977 }
1978 chip->capture_index_offset = 0;
1979 chip->playback_index_offset = chip->capture_streams;
1980 chip->num_streams = chip->playback_streams + chip->capture_streams;
1981
1982 /* sanity check for the SDxCTL.STRM field overflow */
1983 if (chip->num_streams > 15 &&
1984 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1985 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1986 "forcing separate stream tags", chip->num_streams);
1987 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1988 }
1989
1990 /* initialize streams */
1991 err = azx_init_streams(chip);
1992 if (err < 0)
1993 return err;
1994
1995 err = azx_alloc_stream_pages(chip);
1996 if (err < 0)
1997 return err;
1998
1999 /* initialize chip */
2000 azx_init_pci(chip);
2001
2002 snd_hdac_i915_set_bclk(bus);
2003
2004 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
2005
2006 /* codec detection */
2007 if (!azx_bus(chip)->codec_mask) {
2008 dev_err(card->dev, "no codecs found!\n");
2009 /* keep running the rest for the runtime PM */
2010 }
2011
2012 if (azx_acquire_irq(chip, 0) < 0)
2013 return -EBUSY;
2014
2015 strcpy(card->driver, "HDA-Intel");
2016 strscpy(card->shortname, driver_short_names[chip->driver_type],
2017 sizeof(card->shortname));
2018 snprintf(card->longname, sizeof(card->longname),
2019 "%s at 0x%lx irq %i",
2020 card->shortname, bus->addr, bus->irq);
2021
2022 return 0;
2023 }
2024
2025 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2026 /* callback from request_firmware_nowait() */
2027 static void azx_firmware_cb(const struct firmware *fw, void *context)
2028 {
2029 struct snd_card *card = context;
2030 struct azx *chip = card->private_data;
2031
2032 if (fw)
2033 chip->fw = fw;
2034 else
2035 dev_err(card->dev, "Cannot load firmware, continue without patching\n");
2036 if (!chip->disabled) {
2037 /* continue probing */
2038 azx_probe_continue(chip);
2039 }
2040 }
2041 #endif
2042
2043 static int disable_msi_reset_irq(struct azx *chip)
2044 {
2045 struct hdac_bus *bus = azx_bus(chip);
2046 int err;
2047
2048 free_irq(bus->irq, chip);
2049 bus->irq = -1;
2050 chip->card->sync_irq = -1;
2051 pci_disable_msi(chip->pci);
2052 chip->msi = 0;
2053 err = azx_acquire_irq(chip, 1);
2054 if (err < 0)
2055 return err;
2056
2057 return 0;
2058 }
2059
2060 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2061 struct vm_area_struct *area)
2062 {
2063 #ifdef CONFIG_X86
2064 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2065 struct azx *chip = apcm->chip;
2066 if (chip->uc_buffer)
2067 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2068 #endif
2069 }
2070
2071 /* Denylist for skipping the whole probe:
2072 * some HD-audio PCI entries are exposed without any codecs, and such devices
2073 * should be ignored from the beginning.
2074 */
2075 static const struct pci_device_id driver_denylist[] = {
2076 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */
2077 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */
2078 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */
2079 {}
2080 };
2081
2082 static const struct hda_controller_ops pci_hda_ops = {
2083 .disable_msi_reset_irq = disable_msi_reset_irq,
2084 .pcm_mmap_prepare = pcm_mmap_prepare,
2085 .position_check = azx_position_check,
2086 };
2087
2088 static int azx_probe(struct pci_dev *pci,
2089 const struct pci_device_id *pci_id)
2090 {
2091 static int dev;
2092 struct snd_card *card;
2093 struct hda_intel *hda;
2094 struct azx *chip;
2095 bool schedule_probe;
2096 int err;
2097
2098 if (pci_match_id(driver_denylist, pci)) {
2099 dev_info(&pci->dev, "Skipping the device on the denylist\n");
2100 return -ENODEV;
2101 }
2102
2103 if (dev >= SNDRV_CARDS)
2104 return -ENODEV;
2105 if (!enable[dev]) {
2106 dev++;
2107 return -ENOENT;
2108 }
2109
2110 /*
2111 * stop probe if another Intel's DSP driver should be activated
2112 */
2113 if (dmic_detect) {
2114 err = snd_intel_dsp_driver_probe(pci);
2115 if (err != SND_INTEL_DSP_DRIVER_ANY && err != SND_INTEL_DSP_DRIVER_LEGACY) {
2116 dev_dbg(&pci->dev, "HDAudio driver not selected, aborting probe\n");
2117 return -ENODEV;
2118 }
2119 } else {
2120 dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n");
2121 }
2122
2123 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2124 0, &card);
2125 if (err < 0) {
2126 dev_err(&pci->dev, "Error creating card!\n");
2127 return err;
2128 }
2129
2130 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2131 if (err < 0)
2132 goto out_free;
2133 card->private_data = chip;
2134 hda = container_of(chip, struct hda_intel, chip);
2135
2136 pci_set_drvdata(pci, card);
2137
2138 err = register_vga_switcheroo(chip);
2139 if (err < 0) {
2140 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2141 goto out_free;
2142 }
2143
2144 if (check_hdmi_disabled(pci)) {
2145 dev_info(card->dev, "VGA controller is disabled\n");
2146 dev_info(card->dev, "Delaying initialization\n");
2147 chip->disabled = true;
2148 }
2149
2150 schedule_probe = !chip->disabled;
2151
2152 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2153 if (patch[dev] && *patch[dev]) {
2154 dev_info(card->dev, "Applying patch firmware '%s'\n",
2155 patch[dev]);
2156 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2157 &pci->dev, GFP_KERNEL, card,
2158 azx_firmware_cb);
2159 if (err < 0)
2160 goto out_free;
2161 schedule_probe = false; /* continued in azx_firmware_cb() */
2162 }
2163 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2164
2165 #ifndef CONFIG_SND_HDA_I915
2166 if (CONTROLLER_IN_GPU(pci))
2167 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2168 #endif
2169
2170 if (schedule_probe)
2171 schedule_delayed_work(&hda->probe_work, 0);
2172
2173 dev++;
2174 if (chip->disabled)
2175 complete_all(&hda->probe_wait);
2176 return 0;
2177
2178 out_free:
2179 snd_card_free(card);
2180 return err;
2181 }
2182
2183 #ifdef CONFIG_PM
2184 /* On some boards setting power_save to a non 0 value leads to clicking /
2185 * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2186 * figure out how to avoid these sounds, but that is not always feasible.
2187 * So we keep a list of devices where we disable powersaving as its known
2188 * to causes problems on these devices.
2189 */
2190 static const struct snd_pci_quirk power_save_denylist[] = {
2191 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2192 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2193 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2194 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2195 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2196 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2197 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2198 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2199 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2200 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2201 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2202 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2203 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
2204 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2205 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
2206 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2207 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
2208 /* https://bugs.launchpad.net/bugs/1821663 */
2209 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
2210 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2211 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
2212 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2213 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2214 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2215 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2216 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2217 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2218 /* https://bugs.launchpad.net/bugs/1821663 */
2219 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
2220 {}
2221 };
2222 #endif /* CONFIG_PM */
2223
2224 static void set_default_power_save(struct azx *chip)
2225 {
2226 int val = power_save;
2227
2228 #ifdef CONFIG_PM
2229 if (pm_blacklist) {
2230 const struct snd_pci_quirk *q;
2231
2232 q = snd_pci_quirk_lookup(chip->pci, power_save_denylist);
2233 if (q && val) {
2234 dev_info(chip->card->dev, "device %04x:%04x is on the power_save denylist, forcing power_save to 0\n",
2235 q->subvendor, q->subdevice);
2236 val = 0;
2237 }
2238 }
2239 #endif /* CONFIG_PM */
2240 snd_hda_set_power_save(&chip->bus, val * 1000);
2241 }
2242
2243 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2244 static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2245 [AZX_DRIVER_NVIDIA] = 8,
2246 [AZX_DRIVER_TERA] = 1,
2247 };
2248
2249 static int azx_probe_continue(struct azx *chip)
2250 {
2251 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2252 struct hdac_bus *bus = azx_bus(chip);
2253 struct pci_dev *pci = chip->pci;
2254 int dev = chip->dev_index;
2255 int err;
2256
2257 if (chip->disabled || hda->init_failed)
2258 return -EIO;
2259 if (hda->probe_retry)
2260 goto probe_retry;
2261
2262 to_hda_bus(bus)->bus_probing = 1;
2263 hda->probe_continued = 1;
2264
2265 /* bind with i915 if needed */
2266 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2267 err = snd_hdac_i915_init(bus);
2268 if (err < 0) {
2269 /* if the controller is bound only with HDMI/DP
2270 * (for HSW and BDW), we need to abort the probe;
2271 * for other chips, still continue probing as other
2272 * codecs can be on the same link.
2273 */
2274 if (CONTROLLER_IN_GPU(pci)) {
2275 dev_err(chip->card->dev,
2276 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2277 goto out_free;
2278 } else {
2279 /* don't bother any longer */
2280 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
2281 }
2282 }
2283
2284 /* HSW/BDW controllers need this power */
2285 if (CONTROLLER_IN_GPU(pci))
2286 hda->need_i915_power = true;
2287 }
2288
2289 /* Request display power well for the HDA controller or codec. For
2290 * Haswell/Broadwell, both the display HDA controller and codec need
2291 * this power. For other platforms, like Baytrail/Braswell, only the
2292 * display codec needs the power and it can be released after probe.
2293 */
2294 display_power(chip, true);
2295
2296 err = azx_first_init(chip);
2297 if (err < 0)
2298 goto out_free;
2299
2300 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2301 chip->beep_mode = beep_mode[dev];
2302 #endif
2303
2304 /* create codec instances */
2305 if (bus->codec_mask) {
2306 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2307 if (err < 0)
2308 goto out_free;
2309 }
2310
2311 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2312 if (chip->fw) {
2313 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2314 chip->fw->data);
2315 if (err < 0)
2316 goto out_free;
2317 #ifndef CONFIG_PM
2318 release_firmware(chip->fw); /* no longer needed */
2319 chip->fw = NULL;
2320 #endif
2321 }
2322 #endif
2323
2324 probe_retry:
2325 if (bus->codec_mask && !(probe_only[dev] & 1)) {
2326 err = azx_codec_configure(chip);
2327 if (err) {
2328 if ((chip->driver_caps & AZX_DCAPS_RETRY_PROBE) &&
2329 ++hda->probe_retry < 60) {
2330 schedule_delayed_work(&hda->probe_work,
2331 msecs_to_jiffies(1000));
2332 return 0; /* keep things up */
2333 }
2334 dev_err(chip->card->dev, "Cannot probe codecs, giving up\n");
2335 goto out_free;
2336 }
2337 }
2338
2339 err = snd_card_register(chip->card);
2340 if (err < 0)
2341 goto out_free;
2342
2343 setup_vga_switcheroo_runtime_pm(chip);
2344
2345 chip->running = 1;
2346 azx_add_card_list(chip);
2347
2348 set_default_power_save(chip);
2349
2350 if (azx_has_pm_runtime(chip)) {
2351 pm_runtime_use_autosuspend(&pci->dev);
2352 pm_runtime_allow(&pci->dev);
2353 pm_runtime_put_autosuspend(&pci->dev);
2354 }
2355
2356 out_free:
2357 if (err < 0) {
2358 pci_set_drvdata(pci, NULL);
2359 snd_card_free(chip->card);
2360 return err;
2361 }
2362
2363 if (!hda->need_i915_power)
2364 display_power(chip, false);
2365 complete_all(&hda->probe_wait);
2366 to_hda_bus(bus)->bus_probing = 0;
2367 hda->probe_retry = 0;
2368 return 0;
2369 }
2370
2371 static void azx_remove(struct pci_dev *pci)
2372 {
2373 struct snd_card *card = pci_get_drvdata(pci);
2374 struct azx *chip;
2375 struct hda_intel *hda;
2376
2377 if (card) {
2378 /* cancel the pending probing work */
2379 chip = card->private_data;
2380 hda = container_of(chip, struct hda_intel, chip);
2381 /* FIXME: below is an ugly workaround.
2382 * Both device_release_driver() and driver_probe_device()
2383 * take *both* the device's and its parent's lock before
2384 * calling the remove() and probe() callbacks. The codec
2385 * probe takes the locks of both the codec itself and its
2386 * parent, i.e. the PCI controller dev. Meanwhile, when
2387 * the PCI controller is unbound, it takes its lock, too
2388 * ==> ouch, a deadlock!
2389 * As a workaround, we unlock temporarily here the controller
2390 * device during cancel_work_sync() call.
2391 */
2392 device_unlock(&pci->dev);
2393 cancel_delayed_work_sync(&hda->probe_work);
2394 device_lock(&pci->dev);
2395
2396 snd_card_free(card);
2397 }
2398 }
2399
2400 static void azx_shutdown(struct pci_dev *pci)
2401 {
2402 struct snd_card *card = pci_get_drvdata(pci);
2403 struct azx *chip;
2404
2405 if (!card)
2406 return;
2407 chip = card->private_data;
2408 if (chip && chip->running)
2409 __azx_shutdown_chip(chip, true);
2410 }
2411
2412 /* PCI IDs */
2413 static const struct pci_device_id azx_ids[] = {
2414 /* CPT */
2415 { PCI_DEVICE(0x8086, 0x1c20),
2416 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2417 /* PBG */
2418 { PCI_DEVICE(0x8086, 0x1d20),
2419 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2420 /* Panther Point */
2421 { PCI_DEVICE(0x8086, 0x1e20),
2422 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2423 /* Lynx Point */
2424 { PCI_DEVICE(0x8086, 0x8c20),
2425 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2426 /* 9 Series */
2427 { PCI_DEVICE(0x8086, 0x8ca0),
2428 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2429 /* Wellsburg */
2430 { PCI_DEVICE(0x8086, 0x8d20),
2431 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2432 { PCI_DEVICE(0x8086, 0x8d21),
2433 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2434 /* Lewisburg */
2435 { PCI_DEVICE(0x8086, 0xa1f0),
2436 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2437 { PCI_DEVICE(0x8086, 0xa270),
2438 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2439 /* Lynx Point-LP */
2440 { PCI_DEVICE(0x8086, 0x9c20),
2441 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2442 /* Lynx Point-LP */
2443 { PCI_DEVICE(0x8086, 0x9c21),
2444 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2445 /* Wildcat Point-LP */
2446 { PCI_DEVICE(0x8086, 0x9ca0),
2447 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2448 /* Sunrise Point */
2449 { PCI_DEVICE(0x8086, 0xa170),
2450 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2451 /* Sunrise Point-LP */
2452 { PCI_DEVICE(0x8086, 0x9d70),
2453 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2454 /* Kabylake */
2455 { PCI_DEVICE(0x8086, 0xa171),
2456 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2457 /* Kabylake-LP */
2458 { PCI_DEVICE(0x8086, 0x9d71),
2459 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2460 /* Kabylake-H */
2461 { PCI_DEVICE(0x8086, 0xa2f0),
2462 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2463 /* Coffelake */
2464 { PCI_DEVICE(0x8086, 0xa348),
2465 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2466 /* Cannonlake */
2467 { PCI_DEVICE(0x8086, 0x9dc8),
2468 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2469 /* CometLake-LP */
2470 { PCI_DEVICE(0x8086, 0x02C8),
2471 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2472 /* CometLake-H */
2473 { PCI_DEVICE(0x8086, 0x06C8),
2474 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2475 { PCI_DEVICE(0x8086, 0xf1c8),
2476 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2477 /* CometLake-S */
2478 { PCI_DEVICE(0x8086, 0xa3f0),
2479 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2480 /* CometLake-R */
2481 { PCI_DEVICE(0x8086, 0xf0c8),
2482 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2483 /* Icelake */
2484 { PCI_DEVICE(0x8086, 0x34c8),
2485 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2486 /* Icelake-H */
2487 { PCI_DEVICE(0x8086, 0x3dc8),
2488 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2489 /* Jasperlake */
2490 { PCI_DEVICE(0x8086, 0x38c8),
2491 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2492 { PCI_DEVICE(0x8086, 0x4dc8),
2493 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2494 /* Tigerlake */
2495 { PCI_DEVICE(0x8086, 0xa0c8),
2496 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2497 /* Tigerlake-H */
2498 { PCI_DEVICE(0x8086, 0x43c8),
2499 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2500 /* DG1 */
2501 { PCI_DEVICE(0x8086, 0x490d),
2502 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2503 /* Alderlake-S */
2504 { PCI_DEVICE(0x8086, 0x7ad0),
2505 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2506 /* Alderlake-P */
2507 { PCI_DEVICE(0x8086, 0x51c8),
2508 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2509 /* Alderlake-M */
2510 { PCI_DEVICE(0x8086, 0x51cc),
2511 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2512 /* Elkhart Lake */
2513 { PCI_DEVICE(0x8086, 0x4b55),
2514 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2515 { PCI_DEVICE(0x8086, 0x4b58),
2516 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2517 /* Broxton-P(Apollolake) */
2518 { PCI_DEVICE(0x8086, 0x5a98),
2519 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2520 /* Broxton-T */
2521 { PCI_DEVICE(0x8086, 0x1a98),
2522 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2523 /* Gemini-Lake */
2524 { PCI_DEVICE(0x8086, 0x3198),
2525 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2526 /* Haswell */
2527 { PCI_DEVICE(0x8086, 0x0a0c),
2528 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2529 { PCI_DEVICE(0x8086, 0x0c0c),
2530 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2531 { PCI_DEVICE(0x8086, 0x0d0c),
2532 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2533 /* Broadwell */
2534 { PCI_DEVICE(0x8086, 0x160c),
2535 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2536 /* 5 Series/3400 */
2537 { PCI_DEVICE(0x8086, 0x3b56),
2538 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2539 /* Poulsbo */
2540 { PCI_DEVICE(0x8086, 0x811b),
2541 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2542 /* Oaktrail */
2543 { PCI_DEVICE(0x8086, 0x080a),
2544 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2545 /* BayTrail */
2546 { PCI_DEVICE(0x8086, 0x0f04),
2547 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2548 /* Braswell */
2549 { PCI_DEVICE(0x8086, 0x2284),
2550 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2551 /* ICH6 */
2552 { PCI_DEVICE(0x8086, 0x2668),
2553 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2554 /* ICH7 */
2555 { PCI_DEVICE(0x8086, 0x27d8),
2556 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2557 /* ESB2 */
2558 { PCI_DEVICE(0x8086, 0x269a),
2559 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2560 /* ICH8 */
2561 { PCI_DEVICE(0x8086, 0x284b),
2562 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2563 /* ICH9 */
2564 { PCI_DEVICE(0x8086, 0x293e),
2565 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2566 /* ICH9 */
2567 { PCI_DEVICE(0x8086, 0x293f),
2568 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2569 /* ICH10 */
2570 { PCI_DEVICE(0x8086, 0x3a3e),
2571 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2572 /* ICH10 */
2573 { PCI_DEVICE(0x8086, 0x3a6e),
2574 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2575 /* Generic Intel */
2576 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2577 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2578 .class_mask = 0xffffff,
2579 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2580 /* ATI SB 450/600/700/800/900 */
2581 { PCI_DEVICE(0x1002, 0x437b),
2582 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2583 { PCI_DEVICE(0x1002, 0x4383),
2584 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2585 /* AMD Hudson */
2586 { PCI_DEVICE(0x1022, 0x780d),
2587 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2588 /* AMD, X370 & co */
2589 { PCI_DEVICE(0x1022, 0x1457),
2590 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2591 /* AMD, X570 & co */
2592 { PCI_DEVICE(0x1022, 0x1487),
2593 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2594 /* AMD Stoney */
2595 { PCI_DEVICE(0x1022, 0x157a),
2596 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2597 AZX_DCAPS_PM_RUNTIME },
2598 /* AMD Raven */
2599 { PCI_DEVICE(0x1022, 0x15e3),
2600 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2601 /* ATI HDMI */
2602 { PCI_DEVICE(0x1002, 0x0002),
2603 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2604 AZX_DCAPS_PM_RUNTIME },
2605 { PCI_DEVICE(0x1002, 0x1308),
2606 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2607 { PCI_DEVICE(0x1002, 0x157a),
2608 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2609 { PCI_DEVICE(0x1002, 0x15b3),
2610 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2611 { PCI_DEVICE(0x1002, 0x793b),
2612 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2613 { PCI_DEVICE(0x1002, 0x7919),
2614 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2615 { PCI_DEVICE(0x1002, 0x960f),
2616 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2617 { PCI_DEVICE(0x1002, 0x970f),
2618 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2619 { PCI_DEVICE(0x1002, 0x9840),
2620 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2621 { PCI_DEVICE(0x1002, 0xaa00),
2622 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2623 { PCI_DEVICE(0x1002, 0xaa08),
2624 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2625 { PCI_DEVICE(0x1002, 0xaa10),
2626 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2627 { PCI_DEVICE(0x1002, 0xaa18),
2628 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2629 { PCI_DEVICE(0x1002, 0xaa20),
2630 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2631 { PCI_DEVICE(0x1002, 0xaa28),
2632 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2633 { PCI_DEVICE(0x1002, 0xaa30),
2634 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2635 { PCI_DEVICE(0x1002, 0xaa38),
2636 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2637 { PCI_DEVICE(0x1002, 0xaa40),
2638 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2639 { PCI_DEVICE(0x1002, 0xaa48),
2640 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2641 { PCI_DEVICE(0x1002, 0xaa50),
2642 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2643 { PCI_DEVICE(0x1002, 0xaa58),
2644 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2645 { PCI_DEVICE(0x1002, 0xaa60),
2646 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2647 { PCI_DEVICE(0x1002, 0xaa68),
2648 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2649 { PCI_DEVICE(0x1002, 0xaa80),
2650 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2651 { PCI_DEVICE(0x1002, 0xaa88),
2652 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2653 { PCI_DEVICE(0x1002, 0xaa90),
2654 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2655 { PCI_DEVICE(0x1002, 0xaa98),
2656 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2657 { PCI_DEVICE(0x1002, 0x9902),
2658 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2659 { PCI_DEVICE(0x1002, 0xaaa0),
2660 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2661 { PCI_DEVICE(0x1002, 0xaaa8),
2662 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2663 { PCI_DEVICE(0x1002, 0xaab0),
2664 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2665 { PCI_DEVICE(0x1002, 0xaac0),
2666 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2667 AZX_DCAPS_PM_RUNTIME },
2668 { PCI_DEVICE(0x1002, 0xaac8),
2669 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2670 AZX_DCAPS_PM_RUNTIME },
2671 { PCI_DEVICE(0x1002, 0xaad8),
2672 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2673 AZX_DCAPS_PM_RUNTIME },
2674 { PCI_DEVICE(0x1002, 0xaae0),
2675 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2676 AZX_DCAPS_PM_RUNTIME },
2677 { PCI_DEVICE(0x1002, 0xaae8),
2678 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2679 AZX_DCAPS_PM_RUNTIME },
2680 { PCI_DEVICE(0x1002, 0xaaf0),
2681 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2682 AZX_DCAPS_PM_RUNTIME },
2683 { PCI_DEVICE(0x1002, 0xaaf8),
2684 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2685 AZX_DCAPS_PM_RUNTIME },
2686 { PCI_DEVICE(0x1002, 0xab00),
2687 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2688 AZX_DCAPS_PM_RUNTIME },
2689 { PCI_DEVICE(0x1002, 0xab08),
2690 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2691 AZX_DCAPS_PM_RUNTIME },
2692 { PCI_DEVICE(0x1002, 0xab10),
2693 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2694 AZX_DCAPS_PM_RUNTIME },
2695 { PCI_DEVICE(0x1002, 0xab18),
2696 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2697 AZX_DCAPS_PM_RUNTIME },
2698 { PCI_DEVICE(0x1002, 0xab20),
2699 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2700 AZX_DCAPS_PM_RUNTIME },
2701 { PCI_DEVICE(0x1002, 0xab28),
2702 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2703 AZX_DCAPS_PM_RUNTIME },
2704 { PCI_DEVICE(0x1002, 0xab38),
2705 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2706 AZX_DCAPS_PM_RUNTIME },
2707 /* VIA VT8251/VT8237A */
2708 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2709 /* VIA GFX VT7122/VX900 */
2710 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2711 /* VIA GFX VT6122/VX11 */
2712 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2713 /* SIS966 */
2714 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2715 /* ULI M5461 */
2716 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2717 /* NVIDIA MCP */
2718 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2719 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2720 .class_mask = 0xffffff,
2721 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2722 /* Teradici */
2723 { PCI_DEVICE(0x6549, 0x1200),
2724 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2725 { PCI_DEVICE(0x6549, 0x2200),
2726 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2727 /* Creative X-Fi (CA0110-IBG) */
2728 /* CTHDA chips */
2729 { PCI_DEVICE(0x1102, 0x0010),
2730 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2731 { PCI_DEVICE(0x1102, 0x0012),
2732 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2733 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2734 /* the following entry conflicts with snd-ctxfi driver,
2735 * as ctxfi driver mutates from HD-audio to native mode with
2736 * a special command sequence.
2737 */
2738 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2739 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2740 .class_mask = 0xffffff,
2741 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2742 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2743 #else
2744 /* this entry seems still valid -- i.e. without emu20kx chip */
2745 { PCI_DEVICE(0x1102, 0x0009),
2746 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2747 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2748 #endif
2749 /* CM8888 */
2750 { PCI_DEVICE(0x13f6, 0x5011),
2751 .driver_data = AZX_DRIVER_CMEDIA |
2752 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2753 /* Vortex86MX */
2754 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2755 /* VMware HDAudio */
2756 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2757 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2758 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2759 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2760 .class_mask = 0xffffff,
2761 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2762 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2763 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2764 .class_mask = 0xffffff,
2765 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2766 /* Zhaoxin */
2767 { PCI_DEVICE(0x1d17, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN },
2768 { 0, }
2769 };
2770 MODULE_DEVICE_TABLE(pci, azx_ids);
2771
2772 /* pci_driver definition */
2773 static struct pci_driver azx_driver = {
2774 .name = KBUILD_MODNAME,
2775 .id_table = azx_ids,
2776 .probe = azx_probe,
2777 .remove = azx_remove,
2778 .shutdown = azx_shutdown,
2779 .driver = {
2780 .pm = AZX_PM_OPS,
2781 },
2782 };
2783
2784 module_pci_driver(azx_driver);
2785
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