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TOMOYO Linux Cross Reference
Linux/sound/pci/ice1712/quartet.c

Version: ~ [ linux-5.10-rc1 ] ~ [ linux-5.9.1 ] ~ [ linux-5.8.16 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.72 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.152 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.202 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.240 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.240 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.19.8 ] ~ [ linux-3.18.140 ] ~ [ linux-3.17.8 ] ~ [ linux-3.16.85 ] ~ [ linux-3.15.10 ] ~ [ linux-3.14.79 ] ~ [ linux-3.13.11 ] ~ [ linux-3.12.74 ] ~ [ linux-3.11.10 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.5 ] ~ [ policy-sample ] ~
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  1 /*
  2  *   ALSA driver for ICEnsemble VT1724 (Envy24HT)
  3  *
  4  *   Lowlevel functions for Infrasonic Quartet
  5  *
  6  *      Copyright (c) 2009 Pavel Hofman <pavel.hofman@ivitera.com>
  7  *
  8  *
  9  *   This program is free software; you can redistribute it and/or modify
 10  *   it under the terms of the GNU General Public License as published by
 11  *   the Free Software Foundation; either version 2 of the License, or
 12  *   (at your option) any later version.
 13  *
 14  *   This program is distributed in the hope that it will be useful,
 15  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 16  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 17  *   GNU General Public License for more details.
 18  *
 19  *   You should have received a copy of the GNU General Public License
 20  *   along with this program; if not, write to the Free Software
 21  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 22  *
 23  */
 24 
 25 #include <linux/delay.h>
 26 #include <linux/interrupt.h>
 27 #include <linux/init.h>
 28 #include <linux/slab.h>
 29 #include <linux/string.h>
 30 #include <sound/core.h>
 31 #include <sound/tlv.h>
 32 #include <sound/info.h>
 33 
 34 #include "ice1712.h"
 35 #include "envy24ht.h"
 36 #include <sound/ak4113.h>
 37 #include "quartet.h"
 38 
 39 struct qtet_spec {
 40         struct ak4113 *ak4113;
 41         unsigned int scr;       /* system control register */
 42         unsigned int mcr;       /* monitoring control register */
 43         unsigned int cpld;      /* cpld register */
 44 };
 45 
 46 struct qtet_kcontrol_private {
 47         unsigned int bit;
 48         void (*set_register)(struct snd_ice1712 *ice, unsigned int val);
 49         unsigned int (*get_register)(struct snd_ice1712 *ice);
 50         const char * const texts[2];
 51 };
 52 
 53 enum {
 54         IN12_SEL = 0,
 55         IN34_SEL,
 56         AIN34_SEL,
 57         COAX_OUT,
 58         IN12_MON12,
 59         IN12_MON34,
 60         IN34_MON12,
 61         IN34_MON34,
 62         OUT12_MON34,
 63         OUT34_MON12,
 64 };
 65 
 66 static const char * const ext_clock_names[3] = {"IEC958 In", "Word Clock 1xFS",
 67         "Word Clock 256xFS"};
 68 
 69 /* chip address on I2C bus */
 70 #define AK4113_ADDR             0x26    /* S/PDIF receiver */
 71 
 72 /* chip address on SPI bus */
 73 #define AK4620_ADDR             0x02    /* ADC/DAC */
 74 
 75 
 76 /*
 77  * GPIO pins
 78  */
 79 
 80 /* GPIO0 - O - DATA0, def. 0 */
 81 #define GPIO_D0                 (1<<0)
 82 /* GPIO1 - I/O - DATA1, Jack Detect Input0 (0:present, 1:missing), def. 1 */
 83 #define GPIO_D1_JACKDTC0        (1<<1)
 84 /* GPIO2 - I/O - DATA2, Jack Detect Input1 (0:present, 1:missing), def. 1 */
 85 #define GPIO_D2_JACKDTC1        (1<<2)
 86 /* GPIO3 - I/O - DATA3, def. 1 */
 87 #define GPIO_D3                 (1<<3)
 88 /* GPIO4 - I/O - DATA4, SPI CDTO, def. 1 */
 89 #define GPIO_D4_SPI_CDTO        (1<<4)
 90 /* GPIO5 - I/O - DATA5, SPI CCLK, def. 1 */
 91 #define GPIO_D5_SPI_CCLK        (1<<5)
 92 /* GPIO6 - I/O - DATA6, Cable Detect Input (0:detected, 1:not detected */
 93 #define GPIO_D6_CD              (1<<6)
 94 /* GPIO7 - I/O - DATA7, Device Detect Input (0:detected, 1:not detected */
 95 #define GPIO_D7_DD              (1<<7)
 96 /* GPIO8 - O - CPLD Chip Select, def. 1 */
 97 #define GPIO_CPLD_CSN           (1<<8)
 98 /* GPIO9 - O - CPLD register read/write (0:write, 1:read), def. 0 */
 99 #define GPIO_CPLD_RW            (1<<9)
100 /* GPIO10 - O - SPI Chip Select for CODEC#0, def. 1 */
101 #define GPIO_SPI_CSN0           (1<<10)
102 /* GPIO11 - O - SPI Chip Select for CODEC#1, def. 1 */
103 #define GPIO_SPI_CSN1           (1<<11)
104 /* GPIO12 - O - Ex. Register Output Enable (0:enable, 1:disable), def. 1,
105  * init 0 */
106 #define GPIO_EX_GPIOE           (1<<12)
107 /* GPIO13 - O - Ex. Register0 Chip Select for System Control Register,
108  * def. 1 */
109 #define GPIO_SCR                (1<<13)
110 /* GPIO14 - O - Ex. Register1 Chip Select for Monitor Control Register,
111  * def. 1 */
112 #define GPIO_MCR                (1<<14)
113 
114 #define GPIO_SPI_ALL            (GPIO_D4_SPI_CDTO | GPIO_D5_SPI_CCLK |\
115                 GPIO_SPI_CSN0 | GPIO_SPI_CSN1)
116 
117 #define GPIO_DATA_MASK          (GPIO_D0 | GPIO_D1_JACKDTC0 | \
118                 GPIO_D2_JACKDTC1 | GPIO_D3 | \
119                 GPIO_D4_SPI_CDTO | GPIO_D5_SPI_CCLK | \
120                 GPIO_D6_CD | GPIO_D7_DD)
121 
122 /* System Control Register GPIO_SCR data bits */
123 /* Mic/Line select relay (0:line, 1:mic) */
124 #define SCR_RELAY               GPIO_D0
125 /* Phantom power drive control (0:5V, 1:48V) */
126 #define SCR_PHP_V               GPIO_D1_JACKDTC0
127 /* H/W mute control (0:Normal, 1:Mute) */
128 #define SCR_MUTE                GPIO_D2_JACKDTC1
129 /* Phantom power control (0:Phantom on, 1:off) */
130 #define SCR_PHP                 GPIO_D3
131 /* Analog input 1/2 Source Select */
132 #define SCR_AIN12_SEL0          GPIO_D4_SPI_CDTO
133 #define SCR_AIN12_SEL1          GPIO_D5_SPI_CCLK
134 /* Analog input 3/4 Source Select (0:line, 1:hi-z) */
135 #define SCR_AIN34_SEL           GPIO_D6_CD
136 /* Codec Power Down (0:power down, 1:normal) */
137 #define SCR_CODEC_PDN           GPIO_D7_DD
138 
139 #define SCR_AIN12_LINE          (0)
140 #define SCR_AIN12_MIC           (SCR_AIN12_SEL0)
141 #define SCR_AIN12_LOWCUT        (SCR_AIN12_SEL1 | SCR_AIN12_SEL0)
142 
143 /* Monitor Control Register GPIO_MCR data bits */
144 /* Input 1/2 to Monitor 1/2 (0:off, 1:on) */
145 #define MCR_IN12_MON12          GPIO_D0
146 /* Input 1/2 to Monitor 3/4 (0:off, 1:on) */
147 #define MCR_IN12_MON34          GPIO_D1_JACKDTC0
148 /* Input 3/4 to Monitor 1/2 (0:off, 1:on) */
149 #define MCR_IN34_MON12          GPIO_D2_JACKDTC1
150 /* Input 3/4 to Monitor 3/4 (0:off, 1:on) */
151 #define MCR_IN34_MON34          GPIO_D3
152 /* Output to Monitor 1/2 (0:off, 1:on) */
153 #define MCR_OUT34_MON12         GPIO_D4_SPI_CDTO
154 /* Output to Monitor 3/4 (0:off, 1:on) */
155 #define MCR_OUT12_MON34         GPIO_D5_SPI_CCLK
156 
157 /* CPLD Register DATA bits */
158 /* Clock Rate Select */
159 #define CPLD_CKS0               GPIO_D0
160 #define CPLD_CKS1               GPIO_D1_JACKDTC0
161 #define CPLD_CKS2               GPIO_D2_JACKDTC1
162 /* Sync Source Select (0:Internal, 1:External) */
163 #define CPLD_SYNC_SEL           GPIO_D3
164 /* Word Clock FS Select (0:FS, 1:256FS) */
165 #define CPLD_WORD_SEL           GPIO_D4_SPI_CDTO
166 /* Coaxial Output Source (IS-Link) (0:SPDIF, 1:I2S) */
167 #define CPLD_COAX_OUT           GPIO_D5_SPI_CCLK
168 /* Input 1/2 Source Select (0:Analog12, 1:An34) */
169 #define CPLD_IN12_SEL           GPIO_D6_CD
170 /* Input 3/4 Source Select (0:Analog34, 1:Digital In) */
171 #define CPLD_IN34_SEL           GPIO_D7_DD
172 
173 /* internal clock (CPLD_SYNC_SEL = 0) options */
174 #define CPLD_CKS_44100HZ        (0)
175 #define CPLD_CKS_48000HZ        (CPLD_CKS0)
176 #define CPLD_CKS_88200HZ        (CPLD_CKS1)
177 #define CPLD_CKS_96000HZ        (CPLD_CKS1 | CPLD_CKS0)
178 #define CPLD_CKS_176400HZ       (CPLD_CKS2)
179 #define CPLD_CKS_192000HZ       (CPLD_CKS2 | CPLD_CKS0)
180 
181 #define CPLD_CKS_MASK           (CPLD_CKS0 | CPLD_CKS1 | CPLD_CKS2)
182 
183 /* external clock (CPLD_SYNC_SEL = 1) options */
184 /* external clock - SPDIF */
185 #define CPLD_EXT_SPDIF  (0 | CPLD_SYNC_SEL)
186 /* external clock - WordClock 1xfs */
187 #define CPLD_EXT_WORDCLOCK_1FS  (CPLD_CKS1 | CPLD_SYNC_SEL)
188 /* external clock - WordClock 256xfs */
189 #define CPLD_EXT_WORDCLOCK_256FS        (CPLD_CKS1 | CPLD_WORD_SEL |\
190                 CPLD_SYNC_SEL)
191 
192 #define EXT_SPDIF_TYPE                  0
193 #define EXT_WORDCLOCK_1FS_TYPE          1
194 #define EXT_WORDCLOCK_256FS_TYPE        2
195 
196 #define AK4620_DFS0             (1<<0)
197 #define AK4620_DFS1             (1<<1)
198 #define AK4620_CKS0             (1<<2)
199 #define AK4620_CKS1             (1<<3)
200 /* Clock and Format Control register */
201 #define AK4620_DFS_REG          0x02
202 
203 /* Deem and Volume Control register */
204 #define AK4620_DEEMVOL_REG      0x03
205 #define AK4620_SMUTE            (1<<7)
206 
207 /*
208  * Conversion from int value to its binary form. Used for debugging.
209  * The output buffer must be allocated prior to calling the function.
210  */
211 static char *get_binary(char *buffer, int value)
212 {
213         int i, j, pos;
214         pos = 0;
215         for (i = 0; i < 4; ++i) {
216                 for (j = 0; j < 8; ++j) {
217                         if (value & (1 << (31-(i*8 + j))))
218                                 buffer[pos] = '1';
219                         else
220                                 buffer[pos] = '';
221                         pos++;
222                 }
223                 if (i < 3) {
224                         buffer[pos] = ' ';
225                         pos++;
226                 }
227         }
228         buffer[pos] = '\0';
229         return buffer;
230 }
231 
232 /*
233  * Initial setup of the conversion array GPIO <-> rate
234  */
235 static const unsigned int qtet_rates[] = {
236         44100, 48000, 88200,
237         96000, 176400, 192000,
238 };
239 
240 static const unsigned int cks_vals[] = {
241         CPLD_CKS_44100HZ, CPLD_CKS_48000HZ, CPLD_CKS_88200HZ,
242         CPLD_CKS_96000HZ, CPLD_CKS_176400HZ, CPLD_CKS_192000HZ,
243 };
244 
245 static const struct snd_pcm_hw_constraint_list qtet_rates_info = {
246         .count = ARRAY_SIZE(qtet_rates),
247         .list = qtet_rates,
248         .mask = 0,
249 };
250 
251 static void qtet_ak4113_write(void *private_data, unsigned char reg,
252                 unsigned char val)
253 {
254         snd_vt1724_write_i2c((struct snd_ice1712 *)private_data, AK4113_ADDR,
255                         reg, val);
256 }
257 
258 static unsigned char qtet_ak4113_read(void *private_data, unsigned char reg)
259 {
260         return snd_vt1724_read_i2c((struct snd_ice1712 *)private_data,
261                         AK4113_ADDR, reg);
262 }
263 
264 
265 /*
266  * AK4620 section
267  */
268 
269 /*
270  * Write data to addr register of ak4620
271  */
272 static void qtet_akm_write(struct snd_akm4xxx *ak, int chip,
273                 unsigned char addr, unsigned char data)
274 {
275         unsigned int tmp, orig_dir;
276         int idx;
277         unsigned int addrdata;
278         struct snd_ice1712 *ice = ak->private_data[0];
279 
280         if (snd_BUG_ON(chip < 0 || chip >= 4))
281                 return;
282         /*dev_dbg(ice->card->dev, "Writing to AK4620: chip=%d, addr=0x%x,
283           data=0x%x\n", chip, addr, data);*/
284         orig_dir = ice->gpio.get_dir(ice);
285         ice->gpio.set_dir(ice, orig_dir | GPIO_SPI_ALL);
286         /* set mask - only SPI bits */
287         ice->gpio.set_mask(ice, ~GPIO_SPI_ALL);
288 
289         tmp = ice->gpio.get_data(ice);
290         /* high all */
291         tmp |= GPIO_SPI_ALL;
292         ice->gpio.set_data(ice, tmp);
293         udelay(100);
294         /* drop chip select */
295         if (chip)
296                 /* CODEC 1 */
297                 tmp &= ~GPIO_SPI_CSN1;
298         else
299                 tmp &= ~GPIO_SPI_CSN0;
300         ice->gpio.set_data(ice, tmp);
301         udelay(100);
302 
303         /* build I2C address + data byte */
304         addrdata = (AK4620_ADDR << 6) | 0x20 | (addr & 0x1f);
305         addrdata = (addrdata << 8) | data;
306         for (idx = 15; idx >= 0; idx--) {
307                 /* drop clock */
308                 tmp &= ~GPIO_D5_SPI_CCLK;
309                 ice->gpio.set_data(ice, tmp);
310                 udelay(100);
311                 /* set data */
312                 if (addrdata & (1 << idx))
313                         tmp |= GPIO_D4_SPI_CDTO;
314                 else
315                         tmp &= ~GPIO_D4_SPI_CDTO;
316                 ice->gpio.set_data(ice, tmp);
317                 udelay(100);
318                 /* raise clock */
319                 tmp |= GPIO_D5_SPI_CCLK;
320                 ice->gpio.set_data(ice, tmp);
321                 udelay(100);
322         }
323         /* all back to 1 */
324         tmp |= GPIO_SPI_ALL;
325         ice->gpio.set_data(ice, tmp);
326         udelay(100);
327 
328         /* return all gpios to non-writable */
329         ice->gpio.set_mask(ice, 0xffffff);
330         /* restore GPIOs direction */
331         ice->gpio.set_dir(ice, orig_dir);
332 }
333 
334 static void qtet_akm_set_regs(struct snd_akm4xxx *ak, unsigned char addr,
335                 unsigned char mask, unsigned char value)
336 {
337         unsigned char tmp;
338         int chip;
339         for (chip = 0; chip < ak->num_chips; chip++) {
340                 tmp = snd_akm4xxx_get(ak, chip, addr);
341                 /* clear the bits */
342                 tmp &= ~mask;
343                 /* set the new bits */
344                 tmp |= value;
345                 snd_akm4xxx_write(ak, chip, addr, tmp);
346         }
347 }
348 
349 /*
350  * change the rate of AK4620
351  */
352 static void qtet_akm_set_rate_val(struct snd_akm4xxx *ak, unsigned int rate)
353 {
354         unsigned char ak4620_dfs;
355 
356         if (rate == 0)  /* no hint - S/PDIF input is master or the new spdif
357                            input rate undetected, simply return */
358                 return;
359 
360         /* adjust DFS on codecs - see datasheet */
361         if (rate > 108000)
362                 ak4620_dfs = AK4620_DFS1 | AK4620_CKS1;
363         else if (rate > 54000)
364                 ak4620_dfs = AK4620_DFS0 | AK4620_CKS0;
365         else
366                 ak4620_dfs = 0;
367 
368         /* set new value */
369         qtet_akm_set_regs(ak, AK4620_DFS_REG, AK4620_DFS0 | AK4620_DFS1 |
370                         AK4620_CKS0 | AK4620_CKS1, ak4620_dfs);
371 }
372 
373 #define AK_CONTROL(xname, xch)  { .name = xname, .num_channels = xch }
374 
375 #define PCM_12_PLAYBACK_VOLUME  "PCM 1/2 Playback Volume"
376 #define PCM_34_PLAYBACK_VOLUME  "PCM 3/4 Playback Volume"
377 #define PCM_12_CAPTURE_VOLUME   "PCM 1/2 Capture Volume"
378 #define PCM_34_CAPTURE_VOLUME   "PCM 3/4 Capture Volume"
379 
380 static const struct snd_akm4xxx_dac_channel qtet_dac[] = {
381         AK_CONTROL(PCM_12_PLAYBACK_VOLUME, 2),
382         AK_CONTROL(PCM_34_PLAYBACK_VOLUME, 2),
383 };
384 
385 static const struct snd_akm4xxx_adc_channel qtet_adc[] = {
386         AK_CONTROL(PCM_12_CAPTURE_VOLUME, 2),
387         AK_CONTROL(PCM_34_CAPTURE_VOLUME, 2),
388 };
389 
390 static const struct snd_akm4xxx akm_qtet_dac = {
391         .type = SND_AK4620,
392         .num_dacs = 4,  /* DAC1 - Output 12
393         */
394         .num_adcs = 4,  /* ADC1 - Input 12
395         */
396         .ops = {
397                 .write = qtet_akm_write,
398                 .set_rate_val = qtet_akm_set_rate_val,
399         },
400         .dac_info = qtet_dac,
401         .adc_info = qtet_adc,
402 };
403 
404 /* Communication routines with the CPLD */
405 
406 
407 /* Writes data to external register reg, both reg and data are
408  * GPIO representations */
409 static void reg_write(struct snd_ice1712 *ice, unsigned int reg,
410                 unsigned int data)
411 {
412         unsigned int tmp;
413 
414         mutex_lock(&ice->gpio_mutex);
415         /* set direction of used GPIOs*/
416         /* all outputs */
417         tmp = 0x00ffff;
418         ice->gpio.set_dir(ice, tmp);
419         /* mask - writable bits */
420         ice->gpio.set_mask(ice, ~(tmp));
421         /* write the data */
422         tmp = ice->gpio.get_data(ice);
423         tmp &= ~GPIO_DATA_MASK;
424         tmp |= data;
425         ice->gpio.set_data(ice, tmp);
426         udelay(100);
427         /* drop output enable */
428         tmp &=  ~GPIO_EX_GPIOE;
429         ice->gpio.set_data(ice, tmp);
430         udelay(100);
431         /* drop the register gpio */
432         tmp &= ~reg;
433         ice->gpio.set_data(ice, tmp);
434         udelay(100);
435         /* raise the register GPIO */
436         tmp |= reg;
437         ice->gpio.set_data(ice, tmp);
438         udelay(100);
439 
440         /* raise all data gpios */
441         tmp |= GPIO_DATA_MASK;
442         ice->gpio.set_data(ice, tmp);
443         /* mask - immutable bits */
444         ice->gpio.set_mask(ice, 0xffffff);
445         /* outputs only 8-15 */
446         ice->gpio.set_dir(ice, 0x00ff00);
447         mutex_unlock(&ice->gpio_mutex);
448 }
449 
450 static unsigned int get_scr(struct snd_ice1712 *ice)
451 {
452         struct qtet_spec *spec = ice->spec;
453         return spec->scr;
454 }
455 
456 static unsigned int get_mcr(struct snd_ice1712 *ice)
457 {
458         struct qtet_spec *spec = ice->spec;
459         return spec->mcr;
460 }
461 
462 static unsigned int get_cpld(struct snd_ice1712 *ice)
463 {
464         struct qtet_spec *spec = ice->spec;
465         return spec->cpld;
466 }
467 
468 static void set_scr(struct snd_ice1712 *ice, unsigned int val)
469 {
470         struct qtet_spec *spec = ice->spec;
471         reg_write(ice, GPIO_SCR, val);
472         spec->scr = val;
473 }
474 
475 static void set_mcr(struct snd_ice1712 *ice, unsigned int val)
476 {
477         struct qtet_spec *spec = ice->spec;
478         reg_write(ice, GPIO_MCR, val);
479         spec->mcr = val;
480 }
481 
482 static void set_cpld(struct snd_ice1712 *ice, unsigned int val)
483 {
484         struct qtet_spec *spec = ice->spec;
485         reg_write(ice, GPIO_CPLD_CSN, val);
486         spec->cpld = val;
487 }
488 
489 static void proc_regs_read(struct snd_info_entry *entry,
490                 struct snd_info_buffer *buffer)
491 {
492         struct snd_ice1712 *ice = entry->private_data;
493         char bin_buffer[36];
494 
495         snd_iprintf(buffer, "SCR:       %s\n", get_binary(bin_buffer,
496                                 get_scr(ice)));
497         snd_iprintf(buffer, "MCR:       %s\n", get_binary(bin_buffer,
498                                 get_mcr(ice)));
499         snd_iprintf(buffer, "CPLD:      %s\n", get_binary(bin_buffer,
500                                 get_cpld(ice)));
501 }
502 
503 static void proc_init(struct snd_ice1712 *ice)
504 {
505         struct snd_info_entry *entry;
506         if (!snd_card_proc_new(ice->card, "quartet", &entry))
507                 snd_info_set_text_ops(entry, ice, proc_regs_read);
508 }
509 
510 static int qtet_mute_get(struct snd_kcontrol *kcontrol,
511                 struct snd_ctl_elem_value *ucontrol)
512 {
513         struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
514         unsigned int val;
515         val = get_scr(ice) & SCR_MUTE;
516         ucontrol->value.integer.value[0] = (val) ? 0 : 1;
517         return 0;
518 }
519 
520 static int qtet_mute_put(struct snd_kcontrol *kcontrol,
521                 struct snd_ctl_elem_value *ucontrol)
522 {
523         struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
524         unsigned int old, new, smute;
525         old = get_scr(ice) & SCR_MUTE;
526         if (ucontrol->value.integer.value[0]) {
527                 /* unmute */
528                 new = 0;
529                 /* un-smuting DAC */
530                 smute = 0;
531         } else {
532                 /* mute */
533                 new = SCR_MUTE;
534                 /* smuting DAC */
535                 smute = AK4620_SMUTE;
536         }
537         if (old != new) {
538                 struct snd_akm4xxx *ak = ice->akm;
539                 set_scr(ice, (get_scr(ice) & ~SCR_MUTE) | new);
540                 /* set smute */
541                 qtet_akm_set_regs(ak, AK4620_DEEMVOL_REG, AK4620_SMUTE, smute);
542                 return 1;
543         }
544         /* no change */
545         return 0;
546 }
547 
548 static int qtet_ain12_enum_info(struct snd_kcontrol *kcontrol,
549                 struct snd_ctl_elem_info *uinfo)
550 {
551         static const char * const texts[3] =
552                 {"Line In 1/2", "Mic", "Mic + Low-cut"};
553         return snd_ctl_enum_info(uinfo, 1, ARRAY_SIZE(texts), texts);
554 }
555 
556 static int qtet_ain12_sw_get(struct snd_kcontrol *kcontrol,
557                 struct snd_ctl_elem_value *ucontrol)
558 {
559         struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
560         unsigned int val, result;
561         val = get_scr(ice) & (SCR_AIN12_SEL1 | SCR_AIN12_SEL0);
562         switch (val) {
563         case SCR_AIN12_LINE:
564                 result = 0;
565                 break;
566         case SCR_AIN12_MIC:
567                 result = 1;
568                 break;
569         case SCR_AIN12_LOWCUT:
570                 result = 2;
571                 break;
572         default:
573                 /* BUG - no other combinations allowed */
574                 snd_BUG();
575                 result = 0;
576         }
577         ucontrol->value.integer.value[0] = result;
578         return 0;
579 }
580 
581 static int qtet_ain12_sw_put(struct snd_kcontrol *kcontrol,
582                 struct snd_ctl_elem_value *ucontrol)
583 {
584         struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
585         unsigned int old, new, tmp, masked_old;
586         old = new = get_scr(ice);
587         masked_old = old & (SCR_AIN12_SEL1 | SCR_AIN12_SEL0);
588         tmp = ucontrol->value.integer.value[0];
589         if (tmp == 2)
590                 tmp = 3;        /* binary 10 is not supported */
591         tmp <<= 4;      /* shifting to SCR_AIN12_SEL0 */
592         if (tmp != masked_old) {
593                 /* change requested */
594                 switch (tmp) {
595                 case SCR_AIN12_LINE:
596                         new = old & ~(SCR_AIN12_SEL1 | SCR_AIN12_SEL0);
597                         set_scr(ice, new);
598                         /* turn off relay */
599                         new &= ~SCR_RELAY;
600                         set_scr(ice, new);
601                         break;
602                 case SCR_AIN12_MIC:
603                         /* turn on relay */
604                         new = old | SCR_RELAY;
605                         set_scr(ice, new);
606                         new = (new & ~SCR_AIN12_SEL1) | SCR_AIN12_SEL0;
607                         set_scr(ice, new);
608                         break;
609                 case SCR_AIN12_LOWCUT:
610                         /* turn on relay */
611                         new = old | SCR_RELAY;
612                         set_scr(ice, new);
613                         new |= SCR_AIN12_SEL1 | SCR_AIN12_SEL0;
614                         set_scr(ice, new);
615                         break;
616                 default:
617                         snd_BUG();
618                 }
619                 return 1;
620         }
621         /* no change */
622         return 0;
623 }
624 
625 static int qtet_php_get(struct snd_kcontrol *kcontrol,
626                 struct snd_ctl_elem_value *ucontrol)
627 {
628         struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
629         unsigned int val;
630         /* if phantom voltage =48V, phantom on */
631         val = get_scr(ice) & SCR_PHP_V;
632         ucontrol->value.integer.value[0] = val ? 1 : 0;
633         return 0;
634 }
635 
636 static int qtet_php_put(struct snd_kcontrol *kcontrol,
637                 struct snd_ctl_elem_value *ucontrol)
638 {
639         struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
640         unsigned int old, new;
641         old = new = get_scr(ice);
642         if (ucontrol->value.integer.value[0] /* phantom on requested */
643                         && (~old & SCR_PHP_V)) /* 0 = voltage 5V */ {
644                 /* is off, turn on */
645                 /* turn voltage on first, = 1 */
646                 new = old | SCR_PHP_V;
647                 set_scr(ice, new);
648                 /* turn phantom on, = 0 */
649                 new &= ~SCR_PHP;
650                 set_scr(ice, new);
651         } else if (!ucontrol->value.integer.value[0] && (old & SCR_PHP_V)) {
652                 /* phantom off requested and 1 = voltage 48V */
653                 /* is on, turn off */
654                 /* turn voltage off first, = 0 */
655                 new = old & ~SCR_PHP_V;
656                 set_scr(ice, new);
657                 /* turn phantom off, = 1 */
658                 new |= SCR_PHP;
659                 set_scr(ice, new);
660         }
661         if (old != new)
662                 return 1;
663         /* no change */
664         return 0;
665 }
666 
667 #define PRIV_SW(xid, xbit, xreg)        [xid] = {.bit = xbit,\
668         .set_register = set_##xreg,\
669         .get_register = get_##xreg, }
670 
671 
672 #define PRIV_ENUM2(xid, xbit, xreg, xtext1, xtext2)     [xid] = {.bit = xbit,\
673         .set_register = set_##xreg,\
674         .get_register = get_##xreg,\
675         .texts = {xtext1, xtext2} }
676 
677 static struct qtet_kcontrol_private qtet_privates[] = {
678         PRIV_ENUM2(IN12_SEL, CPLD_IN12_SEL, cpld, "An In 1/2", "An In 3/4"),
679         PRIV_ENUM2(IN34_SEL, CPLD_IN34_SEL, cpld, "An In 3/4", "IEC958 In"),
680         PRIV_ENUM2(AIN34_SEL, SCR_AIN34_SEL, scr, "Line In 3/4", "Hi-Z"),
681         PRIV_ENUM2(COAX_OUT, CPLD_COAX_OUT, cpld, "IEC958", "I2S"),
682         PRIV_SW(IN12_MON12, MCR_IN12_MON12, mcr),
683         PRIV_SW(IN12_MON34, MCR_IN12_MON34, mcr),
684         PRIV_SW(IN34_MON12, MCR_IN34_MON12, mcr),
685         PRIV_SW(IN34_MON34, MCR_IN34_MON34, mcr),
686         PRIV_SW(OUT12_MON34, MCR_OUT12_MON34, mcr),
687         PRIV_SW(OUT34_MON12, MCR_OUT34_MON12, mcr),
688 };
689 
690 static int qtet_enum_info(struct snd_kcontrol *kcontrol,
691                 struct snd_ctl_elem_info *uinfo)
692 {
693         struct qtet_kcontrol_private private =
694                 qtet_privates[kcontrol->private_value];
695         return snd_ctl_enum_info(uinfo, 1, ARRAY_SIZE(private.texts),
696                                  private.texts);
697 }
698 
699 static int qtet_sw_get(struct snd_kcontrol *kcontrol,
700                 struct snd_ctl_elem_value *ucontrol)
701 {
702         struct qtet_kcontrol_private private =
703                 qtet_privates[kcontrol->private_value];
704         struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
705         ucontrol->value.integer.value[0] =
706                 (private.get_register(ice) & private.bit) ? 1 : 0;
707         return 0;
708 }
709 
710 static int qtet_sw_put(struct snd_kcontrol *kcontrol,
711                 struct snd_ctl_elem_value *ucontrol)
712 {
713         struct qtet_kcontrol_private private =
714                 qtet_privates[kcontrol->private_value];
715         struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
716         unsigned int old, new;
717         old = private.get_register(ice);
718         if (ucontrol->value.integer.value[0])
719                 new = old | private.bit;
720         else
721                 new = old & ~private.bit;
722         if (old != new) {
723                 private.set_register(ice, new);
724                 return 1;
725         }
726         /* no change */
727         return 0;
728 }
729 
730 #define qtet_sw_info    snd_ctl_boolean_mono_info
731 
732 #define QTET_CONTROL(xname, xtype, xpriv)       \
733         {.iface = SNDRV_CTL_ELEM_IFACE_MIXER,\
734         .name = xname,\
735         .info = qtet_##xtype##_info,\
736         .get = qtet_sw_get,\
737         .put = qtet_sw_put,\
738         .private_value = xpriv }
739 
740 static struct snd_kcontrol_new qtet_controls[] = {
741         {
742                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
743                 .name = "Master Playback Switch",
744                 .info = qtet_sw_info,
745                 .get = qtet_mute_get,
746                 .put = qtet_mute_put,
747                 .private_value = 0
748         },
749         {
750                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
751                 .name = "Phantom Power",
752                 .info = qtet_sw_info,
753                 .get = qtet_php_get,
754                 .put = qtet_php_put,
755                 .private_value = 0
756         },
757         {
758                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
759                 .name = "Analog In 1/2 Capture Switch",
760                 .info = qtet_ain12_enum_info,
761                 .get = qtet_ain12_sw_get,
762                 .put = qtet_ain12_sw_put,
763                 .private_value = 0
764         },
765         QTET_CONTROL("Analog In 3/4 Capture Switch", enum, AIN34_SEL),
766         QTET_CONTROL("PCM In 1/2 Capture Switch", enum, IN12_SEL),
767         QTET_CONTROL("PCM In 3/4 Capture Switch", enum, IN34_SEL),
768         QTET_CONTROL("Coax Output Source", enum, COAX_OUT),
769         QTET_CONTROL("Analog In 1/2 to Monitor 1/2", sw, IN12_MON12),
770         QTET_CONTROL("Analog In 1/2 to Monitor 3/4", sw, IN12_MON34),
771         QTET_CONTROL("Analog In 3/4 to Monitor 1/2", sw, IN34_MON12),
772         QTET_CONTROL("Analog In 3/4 to Monitor 3/4", sw, IN34_MON34),
773         QTET_CONTROL("Output 1/2 to Monitor 3/4", sw, OUT12_MON34),
774         QTET_CONTROL("Output 3/4 to Monitor 1/2", sw, OUT34_MON12),
775 };
776 
777 static char *slave_vols[] = {
778         PCM_12_PLAYBACK_VOLUME,
779         PCM_34_PLAYBACK_VOLUME,
780         NULL
781 };
782 
783 static
784 DECLARE_TLV_DB_SCALE(qtet_master_db_scale, -6350, 50, 1);
785 
786 static struct snd_kcontrol *ctl_find(struct snd_card *card,
787                                      const char *name)
788 {
789         struct snd_ctl_elem_id sid = {0};
790 
791         strlcpy(sid.name, name, sizeof(sid.name));
792         sid.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
793         return snd_ctl_find_id(card, &sid);
794 }
795 
796 static void add_slaves(struct snd_card *card,
797                        struct snd_kcontrol *master, char * const *list)
798 {
799         for (; *list; list++) {
800                 struct snd_kcontrol *slave = ctl_find(card, *list);
801                 if (slave)
802                         snd_ctl_add_slave(master, slave);
803         }
804 }
805 
806 static int qtet_add_controls(struct snd_ice1712 *ice)
807 {
808         struct qtet_spec *spec = ice->spec;
809         int err, i;
810         struct snd_kcontrol *vmaster;
811         err = snd_ice1712_akm4xxx_build_controls(ice);
812         if (err < 0)
813                 return err;
814         for (i = 0; i < ARRAY_SIZE(qtet_controls); i++) {
815                 err = snd_ctl_add(ice->card,
816                                 snd_ctl_new1(&qtet_controls[i], ice));
817                 if (err < 0)
818                         return err;
819         }
820 
821         /* Create virtual master control */
822         vmaster = snd_ctl_make_virtual_master("Master Playback Volume",
823                         qtet_master_db_scale);
824         if (!vmaster)
825                 return -ENOMEM;
826         add_slaves(ice->card, vmaster, slave_vols);
827         err = snd_ctl_add(ice->card, vmaster);
828         if (err < 0)
829                 return err;
830         /* only capture SPDIF over AK4113 */
831         return snd_ak4113_build(spec->ak4113,
832                         ice->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
833 }
834 
835 static inline int qtet_is_spdif_master(struct snd_ice1712 *ice)
836 {
837         /* CPLD_SYNC_SEL: 0 = internal, 1 = external (i.e. spdif master) */
838         return (get_cpld(ice) & CPLD_SYNC_SEL) ? 1 : 0;
839 }
840 
841 static unsigned int qtet_get_rate(struct snd_ice1712 *ice)
842 {
843         int i;
844         unsigned char result;
845 
846         result =  get_cpld(ice) & CPLD_CKS_MASK;
847         for (i = 0; i < ARRAY_SIZE(cks_vals); i++)
848                 if (cks_vals[i] == result)
849                         return qtet_rates[i];
850         return 0;
851 }
852 
853 static int get_cks_val(int rate)
854 {
855         int i;
856         for (i = 0; i < ARRAY_SIZE(qtet_rates); i++)
857                 if (qtet_rates[i] == rate)
858                         return cks_vals[i];
859         return 0;
860 }
861 
862 /* setting new rate */
863 static void qtet_set_rate(struct snd_ice1712 *ice, unsigned int rate)
864 {
865         unsigned int new;
866         unsigned char val;
867         /* switching ice1724 to external clock - supplied by ext. circuits */
868         val = inb(ICEMT1724(ice, RATE));
869         outb(val | VT1724_SPDIF_MASTER, ICEMT1724(ice, RATE));
870 
871         new =  (get_cpld(ice) & ~CPLD_CKS_MASK) | get_cks_val(rate);
872         /* switch to internal clock, drop CPLD_SYNC_SEL */
873         new &= ~CPLD_SYNC_SEL;
874         /* dev_dbg(ice->card->dev, "QT - set_rate: old %x, new %x\n",
875            get_cpld(ice), new); */
876         set_cpld(ice, new);
877 }
878 
879 static inline unsigned char qtet_set_mclk(struct snd_ice1712 *ice,
880                 unsigned int rate)
881 {
882         /* no change in master clock */
883         return 0;
884 }
885 
886 /* setting clock to external - SPDIF */
887 static int qtet_set_spdif_clock(struct snd_ice1712 *ice, int type)
888 {
889         unsigned int old, new;
890 
891         old = new = get_cpld(ice);
892         new &= ~(CPLD_CKS_MASK | CPLD_WORD_SEL);
893         switch (type) {
894         case EXT_SPDIF_TYPE:
895                 new |= CPLD_EXT_SPDIF;
896                 break;
897         case EXT_WORDCLOCK_1FS_TYPE:
898                 new |= CPLD_EXT_WORDCLOCK_1FS;
899                 break;
900         case EXT_WORDCLOCK_256FS_TYPE:
901                 new |= CPLD_EXT_WORDCLOCK_256FS;
902                 break;
903         default:
904                 snd_BUG();
905         }
906         if (old != new) {
907                 set_cpld(ice, new);
908                 /* changed */
909                 return 1;
910         }
911         return 0;
912 }
913 
914 static int qtet_get_spdif_master_type(struct snd_ice1712 *ice)
915 {
916         unsigned int val;
917         int result;
918         val = get_cpld(ice);
919         /* checking only rate/clock-related bits */
920         val &= (CPLD_CKS_MASK | CPLD_WORD_SEL | CPLD_SYNC_SEL);
921         if (!(val & CPLD_SYNC_SEL)) {
922                 /* switched to internal clock, is not any external type */
923                 result = -1;
924         } else {
925                 switch (val) {
926                 case (CPLD_EXT_SPDIF):
927                         result = EXT_SPDIF_TYPE;
928                         break;
929                 case (CPLD_EXT_WORDCLOCK_1FS):
930                         result = EXT_WORDCLOCK_1FS_TYPE;
931                         break;
932                 case (CPLD_EXT_WORDCLOCK_256FS):
933                         result = EXT_WORDCLOCK_256FS_TYPE;
934                         break;
935                 default:
936                         /* undefined combination of external clock setup */
937                         snd_BUG();
938                         result = 0;
939                 }
940         }
941         return result;
942 }
943 
944 /* Called when ak4113 detects change in the input SPDIF stream */
945 static void qtet_ak4113_change(struct ak4113 *ak4113, unsigned char c0,
946                 unsigned char c1)
947 {
948         struct snd_ice1712 *ice = ak4113->change_callback_private;
949         int rate;
950         if ((qtet_get_spdif_master_type(ice) == EXT_SPDIF_TYPE) &&
951                         c1) {
952                 /* only for SPDIF master mode, rate was changed */
953                 rate = snd_ak4113_external_rate(ak4113);
954                 /* dev_dbg(ice->card->dev, "ak4113 - input rate changed to %d\n",
955                    rate); */
956                 qtet_akm_set_rate_val(ice->akm, rate);
957         }
958 }
959 
960 /*
961  * If clock slaved to SPDIF-IN, setting runtime rate
962  * to the detected external rate
963  */
964 static void qtet_spdif_in_open(struct snd_ice1712 *ice,
965                 struct snd_pcm_substream *substream)
966 {
967         struct qtet_spec *spec = ice->spec;
968         struct snd_pcm_runtime *runtime = substream->runtime;
969         int rate;
970 
971         if (qtet_get_spdif_master_type(ice) != EXT_SPDIF_TYPE)
972                 /* not external SPDIF, no rate limitation */
973                 return;
974         /* only external SPDIF can detect incoming sample rate */
975         rate = snd_ak4113_external_rate(spec->ak4113);
976         if (rate >= runtime->hw.rate_min && rate <= runtime->hw.rate_max) {
977                 runtime->hw.rate_min = rate;
978                 runtime->hw.rate_max = rate;
979         }
980 }
981 
982 /*
983  * initialize the chip
984  */
985 static int qtet_init(struct snd_ice1712 *ice)
986 {
987         static const unsigned char ak4113_init_vals[] = {
988                 /* AK4113_REG_PWRDN */  AK4113_RST | AK4113_PWN |
989                         AK4113_OCKS0 | AK4113_OCKS1,
990                 /* AK4113_REQ_FORMAT */ AK4113_DIF_I24I2S | AK4113_VTX |
991                         AK4113_DEM_OFF | AK4113_DEAU,
992                 /* AK4113_REG_IO0 */    AK4113_OPS2 | AK4113_TXE |
993                         AK4113_XTL_24_576M,
994                 /* AK4113_REG_IO1 */    AK4113_EFH_1024LRCLK | AK4113_IPS(0),
995                 /* AK4113_REG_INT0_MASK */      0,
996                 /* AK4113_REG_INT1_MASK */      0,
997                 /* AK4113_REG_DATDTS */         0,
998         };
999         int err;
1000         struct qtet_spec *spec;
1001         struct snd_akm4xxx *ak;
1002         unsigned char val;
1003 
1004         /* switching ice1724 to external clock - supplied by ext. circuits */
1005         val = inb(ICEMT1724(ice, RATE));
1006         outb(val | VT1724_SPDIF_MASTER, ICEMT1724(ice, RATE));
1007 
1008         spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1009         if (!spec)
1010                 return -ENOMEM;
1011         /* qtet is clocked by Xilinx array */
1012         ice->hw_rates = &qtet_rates_info;
1013         ice->is_spdif_master = qtet_is_spdif_master;
1014         ice->get_rate = qtet_get_rate;
1015         ice->set_rate = qtet_set_rate;
1016         ice->set_mclk = qtet_set_mclk;
1017         ice->set_spdif_clock = qtet_set_spdif_clock;
1018         ice->get_spdif_master_type = qtet_get_spdif_master_type;
1019         ice->ext_clock_names = ext_clock_names;
1020         ice->ext_clock_count = ARRAY_SIZE(ext_clock_names);
1021         /* since Qtet can detect correct SPDIF-in rate, all streams can be
1022          * limited to this specific rate */
1023         ice->spdif.ops.open = ice->pro_open = qtet_spdif_in_open;
1024         ice->spec = spec;
1025 
1026         /* Mute Off */
1027         /* SCR Initialize*/
1028         /* keep codec power down first */
1029         set_scr(ice, SCR_PHP);
1030         udelay(1);
1031         /* codec power up */
1032         set_scr(ice, SCR_PHP | SCR_CODEC_PDN);
1033 
1034         /* MCR Initialize */
1035         set_mcr(ice, 0);
1036 
1037         /* CPLD Initialize */
1038         set_cpld(ice, 0);
1039 
1040 
1041         ice->num_total_dacs = 2;
1042         ice->num_total_adcs = 2;
1043 
1044         ice->akm = kcalloc(2, sizeof(struct snd_akm4xxx), GFP_KERNEL);
1045         ak = ice->akm;
1046         if (!ak)
1047                 return -ENOMEM;
1048         /* only one codec with two chips */
1049         ice->akm_codecs = 1;
1050         err = snd_ice1712_akm4xxx_init(ak, &akm_qtet_dac, NULL, ice);
1051         if (err < 0)
1052                 return err;
1053         err = snd_ak4113_create(ice->card,
1054                         qtet_ak4113_read,
1055                         qtet_ak4113_write,
1056                         ak4113_init_vals,
1057                         ice, &spec->ak4113);
1058         if (err < 0)
1059                 return err;
1060         /* callback for codecs rate setting */
1061         spec->ak4113->change_callback = qtet_ak4113_change;
1062         spec->ak4113->change_callback_private = ice;
1063         /* AK41143 in Quartet can detect external rate correctly
1064          * (i.e. check_flags = 0) */
1065         spec->ak4113->check_flags = 0;
1066 
1067         proc_init(ice);
1068 
1069         qtet_set_rate(ice, 44100);
1070         return 0;
1071 }
1072 
1073 static unsigned char qtet_eeprom[] = {
1074         [ICE_EEP2_SYSCONF]     = 0x28,  /* clock 256(24MHz), mpu401, 1xADC,
1075                                            1xDACs, SPDIF in */
1076         [ICE_EEP2_ACLINK]      = 0x80,  /* I2S */
1077         [ICE_EEP2_I2S]         = 0x78,  /* 96k, 24bit, 192k */
1078         [ICE_EEP2_SPDIF]       = 0xc3,  /* out-en, out-int, in, out-ext */
1079         [ICE_EEP2_GPIO_DIR]    = 0x00,  /* 0-7 inputs, switched to output
1080                                            only during output operations */
1081         [ICE_EEP2_GPIO_DIR1]   = 0xff,  /* 8-15 outputs */
1082         [ICE_EEP2_GPIO_DIR2]   = 0x00,
1083         [ICE_EEP2_GPIO_MASK]   = 0xff,  /* changed only for OUT operations */
1084         [ICE_EEP2_GPIO_MASK1]  = 0x00,
1085         [ICE_EEP2_GPIO_MASK2]  = 0xff,
1086 
1087         [ICE_EEP2_GPIO_STATE]  = 0x00, /* inputs */
1088         [ICE_EEP2_GPIO_STATE1] = 0x7d, /* all 1, but GPIO_CPLD_RW
1089                                           and GPIO15 always zero */
1090         [ICE_EEP2_GPIO_STATE2] = 0x00, /* inputs */
1091 };
1092 
1093 /* entry point */
1094 struct snd_ice1712_card_info snd_vt1724_qtet_cards[] = {
1095         {
1096                 .subvendor = VT1724_SUBDEVICE_QTET,
1097                 .name = "Infrasonic Quartet",
1098                 .model = "quartet",
1099                 .chip_init = qtet_init,
1100                 .build_controls = qtet_add_controls,
1101                 .eeprom_size = sizeof(qtet_eeprom),
1102                 .eeprom_data = qtet_eeprom,
1103         },
1104         { } /* terminator */
1105 };
1106 

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