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TOMOYO Linux Cross Reference
Linux/sound/pci/intel8x0.c

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  1 /*
  2  *   ALSA driver for Intel ICH (i8x0) chipsets
  3  *
  4  *      Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
  5  *
  6  *
  7  *   This code also contains alpha support for SiS 735 chipsets provided
  8  *   by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
  9  *   for SiS735, so the code is not fully functional.
 10  *
 11  *
 12  *   This program is free software; you can redistribute it and/or modify
 13  *   it under the terms of the GNU General Public License as published by
 14  *   the Free Software Foundation; either version 2 of the License, or
 15  *   (at your option) any later version.
 16  *
 17  *   This program is distributed in the hope that it will be useful,
 18  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 19  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 20  *   GNU General Public License for more details.
 21  *
 22  *   You should have received a copy of the GNU General Public License
 23  *   along with this program; if not, write to the Free Software
 24  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 25 
 26  *
 27  */      
 28 
 29 #include <sound/driver.h>
 30 #include <asm/io.h>
 31 #include <linux/delay.h>
 32 #include <linux/interrupt.h>
 33 #include <linux/init.h>
 34 #include <linux/pci.h>
 35 #include <linux/slab.h>
 36 #include <sound/core.h>
 37 #include <sound/pcm.h>
 38 #include <sound/ac97_codec.h>
 39 #include <sound/info.h>
 40 #include <sound/mpu401.h>
 41 #define SNDRV_GET_ID
 42 #include <sound/initval.h>
 43 
 44 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
 45 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
 46 MODULE_LICENSE("GPL");
 47 MODULE_CLASSES("{sound}");
 48 MODULE_DEVICES("{{Intel,82801AA-ICH},"
 49                 "{Intel,82901AB-ICH0},"
 50                 "{Intel,82801BA-ICH2},"
 51                 "{Intel,82801CA-ICH3},"
 52                 "{Intel,82801DB-ICH4},"
 53                 "{Intel,ICH5},"
 54                 "{Intel,MX440},"
 55                 "{SiS,SI7012},"
 56                 "{NVidia,nForce Audio},"
 57                 "{NVidia,nForce2 Audio},"
 58                 "{AMD,AMD768},"
 59                 "{AMD,AMD8111},"
 60                 "{ALI,M5455}}");
 61 
 62 #define SUPPORT_JOYSTICK 1
 63 #define SUPPORT_MIDI 1
 64 
 65 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
 66 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
 67 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;      /* Enable this card */
 68 static int ac97_clock[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 0};
 69 #ifdef SUPPORT_JOYSTICK
 70 static int joystick_port[SNDRV_CARDS] =
 71 #ifdef CONFIG_ISA
 72         {0x200};        /* enable as default */
 73 #else
 74         {0};    /* disabled */
 75 #endif
 76 #endif
 77 #ifdef SUPPORT_MIDI
 78 static int mpu_port[SNDRV_CARDS]; /* disabled */
 79 #endif
 80 
 81 MODULE_PARM(index, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
 82 MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
 83 MODULE_PARM_SYNTAX(index, SNDRV_INDEX_DESC);
 84 MODULE_PARM(id, "1-" __MODULE_STRING(SNDRV_CARDS) "s");
 85 MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
 86 MODULE_PARM_SYNTAX(id, SNDRV_ID_DESC);
 87 MODULE_PARM(enable, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
 88 MODULE_PARM_DESC(enable, "Enable Intel i8x0 soundcard.");
 89 MODULE_PARM_SYNTAX(enable, SNDRV_ENABLE_DESC);
 90 MODULE_PARM(ac97_clock, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
 91 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect).");
 92 MODULE_PARM_SYNTAX(ac97_clock, SNDRV_ENABLED ",default:0");
 93 #ifdef SUPPORT_JOYSTICK
 94 MODULE_PARM(joystick_port, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
 95 MODULE_PARM_DESC(joystick_port, "Joystick port address for Intel i8x0 soundcard. (0 = disabled)");
 96 MODULE_PARM_SYNTAX(joystick_port, SNDRV_ENABLED ",allows:{{0},{0x200}},dialog:list");
 97 #endif
 98 #ifdef SUPPORT_MIDI
 99 MODULE_PARM(mpu_port, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
100 MODULE_PARM_DESC(mpu_port, "MPU401 port # for Intel i8x0 driver.");
101 MODULE_PARM_SYNTAX(mpu_port, SNDRV_ENABLED ",allows:{{0},{0x330},{0x300}},dialog:list");
102 #endif
103 
104 /*
105  *  Direct registers
106  */
107 
108 #ifndef PCI_DEVICE_ID_INTEL_82801
109 #define PCI_DEVICE_ID_INTEL_82801       0x2415
110 #endif
111 #ifndef PCI_DEVICE_ID_INTEL_82901
112 #define PCI_DEVICE_ID_INTEL_82901       0x2425
113 #endif
114 #ifndef PCI_DEVICE_ID_INTEL_82801BA
115 #define PCI_DEVICE_ID_INTEL_82801BA     0x2445
116 #endif
117 #ifndef PCI_DEVICE_ID_INTEL_440MX
118 #define PCI_DEVICE_ID_INTEL_440MX       0x7195
119 #endif
120 #ifndef PCI_DEVICE_ID_INTEL_ICH3
121 #define PCI_DEVICE_ID_INTEL_ICH3        0x2485
122 #endif
123 #ifndef PCI_DEVICE_ID_INTEL_ICH4
124 #define PCI_DEVICE_ID_INTEL_ICH4        0x24c5
125 #endif
126 #ifndef PCI_DEVICE_ID_INTEL_ICH5
127 #define PCI_DEVICE_ID_INTEL_ICH5        0x24d5
128 #endif
129 #ifndef PCI_DEVICE_ID_SI_7012
130 #define PCI_DEVICE_ID_SI_7012           0x7012
131 #endif
132 #ifndef PCI_DEVICE_ID_NVIDIA_MCP_AUDIO
133 #define PCI_DEVICE_ID_NVIDIA_MCP_AUDIO  0x01b1
134 #endif
135 #ifndef PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO
136 #define PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO 0x006a
137 #endif
138 #ifndef PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO
139 #define PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO 0x00da
140 #endif
141 
142 enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
143 
144 #define ICHREG(x) ICH_REG_##x
145 
146 #define DEFINE_REGSET(name,base) \
147 enum { \
148         ICH_REG_##name##_BDBAR  = base + 0x0,   /* dword - buffer descriptor list base address */ \
149         ICH_REG_##name##_CIV    = base + 0x04,  /* byte - current index value */ \
150         ICH_REG_##name##_LVI    = base + 0x05,  /* byte - last valid index */ \
151         ICH_REG_##name##_SR     = base + 0x06,  /* byte - status register */ \
152         ICH_REG_##name##_PICB   = base + 0x08,  /* word - position in current buffer */ \
153         ICH_REG_##name##_PIV    = base + 0x0a,  /* byte - prefetched index value */ \
154         ICH_REG_##name##_CR     = base + 0x0b,  /* byte - control register */ \
155 };
156 
157 /* busmaster blocks */
158 DEFINE_REGSET(OFF, 0);          /* offset */
159 DEFINE_REGSET(PI, 0x00);        /* PCM in */
160 DEFINE_REGSET(PO, 0x10);        /* PCM out */
161 DEFINE_REGSET(MC, 0x20);        /* Mic in */
162 
163 /* ICH4 busmaster blocks */
164 DEFINE_REGSET(MC2, 0x40);       /* Mic in 2 */
165 DEFINE_REGSET(PI2, 0x50);       /* PCM in 2 */
166 DEFINE_REGSET(SP, 0x60);        /* SPDIF out */
167 
168 /* values for each busmaster block */
169 
170 /* LVI */
171 #define ICH_REG_LVI_MASK                0x1f
172 
173 /* SR */
174 #define ICH_FIFOE                       0x10    /* FIFO error */
175 #define ICH_BCIS                        0x08    /* buffer completion interrupt status */
176 #define ICH_LVBCI                       0x04    /* last valid buffer completion interrupt */
177 #define ICH_CELV                        0x02    /* current equals last valid */
178 #define ICH_DCH                         0x01    /* DMA controller halted */
179 
180 /* PIV */
181 #define ICH_REG_PIV_MASK                0x1f    /* mask */
182 
183 /* CR */
184 #define ICH_IOCE                        0x10    /* interrupt on completion enable */
185 #define ICH_FEIE                        0x08    /* fifo error interrupt enable */
186 #define ICH_LVBIE                       0x04    /* last valid buffer interrupt enable */
187 #define ICH_RESETREGS                   0x02    /* reset busmaster registers */
188 #define ICH_STARTBM                     0x01    /* start busmaster operation */
189 
190 
191 /* global block */
192 #define ICH_REG_GLOB_CNT                0x2c    /* dword - global control */
193 #define   ICH_PCM_20BIT         0x00400000      /* 20-bit samples (ICH4) */
194 #define   ICH_PCM_246_MASK      0x00300000      /* 6 channels (not all chips) */
195 #define   ICH_PCM_6             0x00200000      /* 6 channels (not all chips) */
196 #define   ICH_PCM_4             0x00100000      /* 4 channels (not all chips) */
197 #define   ICH_PCM_2             0x00000000      /* 2 channels (stereo) */
198 #define   ICH_SIS_PCM_246_MASK  0x000000c0      /* 6 channels (SIS7012) */
199 #define   ICH_SIS_PCM_6         0x00000080      /* 6 channels (SIS7012) */
200 #define   ICH_SIS_PCM_4         0x00000040      /* 4 channels (SIS7012) */
201 #define   ICH_SIS_PCM_2         0x00000000      /* 2 channels (SIS7012) */
202 #define   ICH_TRIE              0x00000040      /* tertiary resume interrupt enable */
203 #define   ICH_SRIE              0x00000020      /* secondary resume interrupt enable */
204 #define   ICH_PRIE              0x00000010      /* primary resume interrupt enable */
205 #define   ICH_ACLINK            0x00000008      /* AClink shut off */
206 #define   ICH_AC97WARM          0x00000004      /* AC'97 warm reset */
207 #define   ICH_AC97COLD          0x00000002      /* AC'97 cold reset */
208 #define   ICH_GIE               0x00000001      /* GPI interrupt enable */
209 #define ICH_REG_GLOB_STA                0x30    /* dword - global status */
210 #define   ICH_TRI               0x20000000      /* ICH4: tertiary (AC_SDIN2) resume interrupt */
211 #define   ICH_TCR               0x10000000      /* ICH4: tertiary (AC_SDIN2) codec ready */
212 #define   ICH_BCS               0x08000000      /* ICH4: bit clock stopped */
213 #define   ICH_SPINT             0x04000000      /* ICH4: S/PDIF interrupt */
214 #define   ICH_P2INT             0x02000000      /* ICH4: PCM2-In interrupt */
215 #define   ICH_M2INT             0x01000000      /* ICH4: Mic2-In interrupt */
216 #define   ICH_SAMPLE_CAP        0x00c00000      /* ICH4: sample capability bits (RO) */
217 #define   ICH_MULTICHAN_CAP     0x00300000      /* ICH4: multi-channel capability bits (RO) */
218 #define   ICH_MD3               0x00020000      /* modem power down semaphore */
219 #define   ICH_AD3               0x00010000      /* audio power down semaphore */
220 #define   ICH_RCS               0x00008000      /* read completion status */
221 #define   ICH_BIT3              0x00004000      /* bit 3 slot 12 */
222 #define   ICH_BIT2              0x00002000      /* bit 2 slot 12 */
223 #define   ICH_BIT1              0x00001000      /* bit 1 slot 12 */
224 #define   ICH_SRI               0x00000800      /* secondary (AC_SDIN1) resume interrupt */
225 #define   ICH_PRI               0x00000400      /* primary (AC_SDIN0) resume interrupt */
226 #define   ICH_SCR               0x00000200      /* secondary (AC_SDIN1) codec ready */
227 #define   ICH_PCR               0x00000100      /* primary (AC_SDIN0) codec ready */
228 #define   ICH_MCINT             0x00000080      /* MIC capture interrupt */
229 #define   ICH_POINT             0x00000040      /* playback interrupt */
230 #define   ICH_PIINT             0x00000020      /* capture interrupt */
231 #define   ICH_NVSPINT           0x00000010      /* nforce spdif interrupt */
232 #define   ICH_MOINT             0x00000004      /* modem playback interrupt */
233 #define   ICH_MIINT             0x00000002      /* modem capture interrupt */
234 #define   ICH_GSCI              0x00000001      /* GPI status change interrupt */
235 #define ICH_REG_ACC_SEMA                0x34    /* byte - codec write semaphore */
236 #define   ICH_CAS               0x01            /* codec access semaphore */
237 #define ICH_REG_SDM             0x80
238 #define   ICH_DI2L_MASK         0x000000c0      /* PCM In 2, Mic In 2 data in line */
239 #define   ICH_DI2L_SHIFT        6
240 #define   ICH_DI1L_MASK         0x00000030      /* PCM In 1, Mic In 1 data in line */
241 #define   ICH_DI1L_SHIFT        4
242 #define   ICH_SE                0x00000008      /* steer enable */
243 #define   ICH_LDI_MASK          0x00000003      /* last codec read data input */
244 
245 #define ICH_MAX_FRAGS           32              /* max hw frags */
246 
247 
248 /*
249  * registers for Ali5455
250  */
251 
252 /* ALi 5455 busmaster blocks */
253 DEFINE_REGSET(AL_PI, 0x40);     /* ALi PCM in */
254 DEFINE_REGSET(AL_PO, 0x50);     /* Ali PCM out */
255 DEFINE_REGSET(AL_MC, 0x60);     /* Ali Mic in */
256 DEFINE_REGSET(AL_CDC_SPO, 0x70);        /* Ali Codec SPDIF out */
257 DEFINE_REGSET(AL_CENTER, 0x80);         /* Ali center out */
258 DEFINE_REGSET(AL_LFE, 0x90);            /* Ali center out */
259 DEFINE_REGSET(AL_CLR_SPI, 0xa0);        /* Ali Controller SPDIF in */
260 DEFINE_REGSET(AL_CLR_SPO, 0xb0);        /* Ali Controller SPDIF out */
261 DEFINE_REGSET(AL_I2S, 0xc0);    /* Ali I2S in */
262 DEFINE_REGSET(AL_PI2, 0xd0);    /* Ali PCM2 in */
263 DEFINE_REGSET(AL_MC2, 0xe0);    /* Ali Mic2 in */
264 
265 enum {
266         ICH_REG_ALI_SCR = 0x00,         /* System Control Register */
267         ICH_REG_ALI_SSR = 0x04,         /* System Status Register  */
268         ICH_REG_ALI_DMACR = 0x08,       /* DMA Control Register    */
269         ICH_REG_ALI_FIFOCR1 = 0x0c,     /* FIFO Control Register 1  */
270         ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
271         ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
272         ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt  Status Register */
273         ICH_REG_ALI_FIFOCR2 = 0x1c,     /* FIFO Control Register 2   */
274         ICH_REG_ALI_CPR = 0x20,         /* Command Port Register     */
275         ICH_REG_ALI_CPR_ADDR = 0x22,    /* ac97 addr write */
276         ICH_REG_ALI_SPR = 0x24,         /* Status Port Register      */
277         ICH_REG_ALI_SPR_ADDR = 0x26,    /* ac97 addr read */
278         ICH_REG_ALI_FIFOCR3 = 0x2c,     /* FIFO Control Register 3  */
279         ICH_REG_ALI_TTSR = 0x30,        /* Transmit Tag Slot Register */
280         ICH_REG_ALI_RTSR = 0x34,        /* Receive Tag Slot  Register */
281         ICH_REG_ALI_CSPSR = 0x38,       /* Command/Status Port Status Register */
282         ICH_REG_ALI_CAS = 0x3c,         /* Codec Write Semaphore Register */
283         ICH_REG_ALI_HWVOL = 0xf0,       /* hardware volume control/status */
284         ICH_REG_ALI_I2SCR = 0xf4,       /* I2S control/status */
285         ICH_REG_ALI_SPDIFCSR = 0xf8,    /* spdif channel status register  */
286         ICH_REG_ALI_SPDIFICS = 0xfc,    /* spdif interface control/status  */
287 };
288 
289 #define ALI_CAS_SEM_BUSY        0x80000000
290 #define ALI_CPR_ADDR_SECONDARY  0x100
291 #define ALI_CPR_ADDR_READ       0x80
292 #define ALI_CSPSR_CODEC_READY   0x08
293 #define ALI_CSPSR_READ_OK       0x02
294 #define ALI_CSPSR_WRITE_OK      0x01
295 
296 /* interrupts for the whole chip by interrupt status register finish */
297  
298 #define ALI_INT_MICIN2          (1<<26)
299 #define ALI_INT_PCMIN2          (1<<25)
300 #define ALI_INT_I2SIN           (1<<24)
301 #define ALI_INT_SPDIFOUT        (1<<23) /* controller spdif out INTERRUPT */
302 #define ALI_INT_SPDIFIN         (1<<22)
303 #define ALI_INT_LFEOUT          (1<<21)
304 #define ALI_INT_CENTEROUT       (1<<20)
305 #define ALI_INT_CODECSPDIFOUT   (1<<19)
306 #define ALI_INT_MICIN           (1<<18)
307 #define ALI_INT_PCMOUT          (1<<17)
308 #define ALI_INT_PCMIN           (1<<16)
309 #define ALI_INT_CPRAIS          (1<<7)  /* command port available */
310 #define ALI_INT_SPRAIS          (1<<5)  /* status port available */
311 #define ALI_INT_GPIO            (1<<1)
312 #define ALI_INT_MASK            (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
313 
314 #define ICH_ALI_SC_RESET        (1<<31) /* master reset */
315 #define ICH_ALI_SC_AC97_DBL     (1<<30)
316 #define ICH_ALI_SC_CODEC_SPDF   (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
317 #define ICH_ALI_SC_IN_BITS      (3<<18)
318 #define ICH_ALI_SC_OUT_BITS     (3<<16)
319 #define ICH_ALI_SC_6CH_CFG      (3<<14)
320 #define ICH_ALI_SC_PCM_4        (1<<8)
321 #define ICH_ALI_SC_PCM_6        (2<<8)
322 #define ICH_ALI_SC_PCM_246_MASK (3<<8)
323 
324 #define ICH_ALI_SS_SEC_ID       (3<<5)
325 #define ICH_ALI_SS_PRI_ID       (3<<3)
326 
327 #define ICH_ALI_IF_AC97SP       (1<<21)
328 #define ICH_ALI_IF_MC           (1<<20)
329 #define ICH_ALI_IF_PI           (1<<19)
330 #define ICH_ALI_IF_MC2          (1<<18)
331 #define ICH_ALI_IF_PI2          (1<<17)
332 #define ICH_ALI_IF_LINE_SRC     (1<<15) /* 0/1 = slot 3/6 */
333 #define ICH_ALI_IF_MIC_SRC      (1<<14) /* 0/1 = slot 3/6 */
334 #define ICH_ALI_IF_SPDF_SRC     (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
335 #define ICH_ALI_IF_AC97_OUT     (3<<8)  /* 00 = PCM, 10 = spdif-in, 11 = i2s */
336 #define ICH_ALI_IF_PO_SPDF      (1<<3)
337 #define ICH_ALI_IF_PO           (1<<1)
338 
339 /*
340  *  
341  */
342 
343 enum { ICHD_PCMIN, ICHD_PCMOUT, ICHD_MIC, ICHD_MIC2, ICHD_PCM2IN, ICHD_SPBAR, ICHD_LAST = ICHD_SPBAR };
344 enum { NVD_PCMIN, NVD_PCMOUT, NVD_MIC, NVD_SPBAR, NVD_LAST = NVD_SPBAR };
345 enum { ALID_PCMIN, ALID_PCMOUT, ALID_MIC, ALID_AC97SPDIFOUT, ALID_SPDIFIN, ALID_SPDIFOUT, ALID_LAST = ALID_SPDIFOUT };
346 
347 #define get_ichdev(substream) (ichdev_t *)(substream->runtime->private_data)
348 
349 typedef struct {
350         unsigned int ichd;                      /* ich device number */
351         unsigned long reg_offset;               /* offset to bmaddr */
352         u32 *bdbar;                             /* CPU address (32bit) */
353         unsigned int bdbar_addr;                /* PCI bus address (32bit) */
354         snd_pcm_substream_t *substream;
355         unsigned int physbuf;                   /* physical address (32bit) */
356         unsigned int size;
357         unsigned int fragsize;
358         unsigned int fragsize1;
359         unsigned int position;
360         int frags;
361         int lvi;
362         int lvi_frag;
363         int civ;
364         int ack;
365         int ack_reload;
366         unsigned int ack_bit;
367         unsigned int roff_sr;
368         unsigned int roff_picb;
369         unsigned int int_sta_mask;              /* interrupt status mask */
370         unsigned int ali_slot;                  /* ALI DMA slot */
371         ac97_t *ac97;
372         unsigned short ac97_rate_regs[3];
373         int ac97_rates_idx;
374 } ichdev_t;
375 
376 typedef struct _snd_intel8x0 intel8x0_t;
377 #define chip_t intel8x0_t
378 
379 struct _snd_intel8x0 {
380         unsigned int device_type;
381         char ac97_name[32];
382         char ctrl_name[32];
383 
384         int irq;
385 
386         unsigned int mmio;
387         unsigned long addr;
388         unsigned long remap_addr;
389         struct resource *res;
390         unsigned int bm_mmio;
391         unsigned long bmaddr;
392         unsigned long remap_bmaddr;
393         struct resource *res_bm;
394 
395         struct pci_dev *pci;
396         snd_card_t *card;
397 
398         int pcm_devs;
399         snd_pcm_t *pcm[6];
400         ichdev_t ichd[6];
401 
402         int multi4: 1,
403             multi6: 1,
404             smp20bit: 1;
405         int in_ac97_init: 1,
406             in_sdin_init: 1;
407 
408         ac97_t *ac97[3];
409         unsigned int ac97_sdin[3];
410 
411         snd_rawmidi_t *rmidi;
412 
413         spinlock_t reg_lock;
414         spinlock_t ac97_lock;
415         
416         u32 bdbars_count;
417         u32 *bdbars;
418         dma_addr_t bdbars_addr;
419         u32 int_sta_reg;                /* interrupt status register */
420         u32 int_sta_mask;               /* interrupt status mask */
421         unsigned int pcm_pos_shift;
422         
423 #ifdef CONFIG_PM
424         int in_suspend;
425 #endif
426 };
427 
428 static struct pci_device_id snd_intel8x0_ids[] = {
429         { 0x8086, 0x2415, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */
430         { 0x8086, 0x2425, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */
431         { 0x8086, 0x2445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */
432         { 0x8086, 0x2485, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */
433         { 0x8086, 0x24c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH4 */
434         { 0x8086, 0x24d5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH5 */
435         { 0x8086, 0x7195, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */
436         { 0x1039, 0x7012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS },   /* SI7012 */
437         { 0x10de, 0x01b1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* NFORCE */
438         { 0x10de, 0x006a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* NFORCE2 */
439         { 0x10de, 0x00da, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* NFORCE3 */
440         { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */
441         { 0x1022, 0x7445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */
442         { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI },   /* Ali5455 */
443         { 0, }
444 };
445 
446 MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
447 
448 /*
449  *  Lowlevel I/O - busmaster
450  */
451 
452 static u8 igetbyte(intel8x0_t *chip, u32 offset)
453 {
454         if (chip->bm_mmio)
455                 return readb(chip->remap_bmaddr + offset);
456         else
457                 return inb(chip->bmaddr + offset);
458 }
459 
460 static u16 igetword(intel8x0_t *chip, u32 offset)
461 {
462         if (chip->bm_mmio)
463                 return readw(chip->remap_bmaddr + offset);
464         else
465                 return inw(chip->bmaddr + offset);
466 }
467 
468 static u32 igetdword(intel8x0_t *chip, u32 offset)
469 {
470         if (chip->bm_mmio)
471                 return readl(chip->remap_bmaddr + offset);
472         else
473                 return inl(chip->bmaddr + offset);
474 }
475 
476 static void iputbyte(intel8x0_t *chip, u32 offset, u8 val)
477 {
478         if (chip->bm_mmio)
479                 writeb(val, chip->remap_bmaddr + offset);
480         else
481                 outb(val, chip->bmaddr + offset);
482 }
483 
484 static void iputword(intel8x0_t *chip, u32 offset, u16 val)
485 {
486         if (chip->bm_mmio)
487                 writew(val, chip->remap_bmaddr + offset);
488         else
489                 outw(val, chip->bmaddr + offset);
490 }
491 
492 static void iputdword(intel8x0_t *chip, u32 offset, u32 val)
493 {
494         if (chip->bm_mmio)
495                 writel(val, chip->remap_bmaddr + offset);
496         else
497                 outl(val, chip->bmaddr + offset);
498 }
499 
500 /*
501  *  Lowlevel I/O - AC'97 registers
502  */
503 
504 static u16 iagetword(intel8x0_t *chip, u32 offset)
505 {
506         if (chip->mmio)
507                 return readw(chip->remap_addr + offset);
508         else
509                 return inw(chip->addr + offset);
510 }
511 
512 static void iaputword(intel8x0_t *chip, u32 offset, u16 val)
513 {
514         if (chip->mmio)
515                 writew(val, chip->remap_addr + offset);
516         else
517                 outw(val, chip->addr + offset);
518 }
519 
520 /*
521  *  Basic I/O
522  */
523 
524 /*
525  * access to AC97 codec via normal i/o (for ICH and SIS7012)
526  */
527 
528 /* return the GLOB_STA bit for the corresponding codec */
529 static unsigned int get_ich_codec_bit(intel8x0_t *chip, unsigned int codec)
530 {
531         static unsigned int codec_bit[3] = {
532                 ICH_PCR, ICH_SCR, ICH_TCR
533         };
534         snd_assert(codec < 3, return ICH_PCR);
535         if (chip->device_type == DEVICE_INTEL_ICH4)
536                 codec = chip->ac97_sdin[codec];
537         return codec_bit[codec];
538 }
539 
540 static int snd_intel8x0_codec_semaphore(intel8x0_t *chip, unsigned int codec)
541 {
542         int time;
543         
544         if (codec > 2)
545                 return -EIO;
546         if (chip->in_sdin_init) {
547                 /* we don't know the ready bit assignment at the moment */
548                 /* so we check any */
549                 codec = ICH_PCR | ICH_SCR | ICH_TCR;
550         } else {
551                 codec = get_ich_codec_bit(chip, codec);
552         }
553 
554         /* codec ready ? */
555         if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
556                 return -EIO;
557 
558         /* Anyone holding a semaphore for 1 msec should be shot... */
559         time = 100;
560         do {
561                 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
562                         return 0;
563                 udelay(10);
564         } while (time--);
565 
566         /* access to some forbidden (non existant) ac97 registers will not
567          * reset the semaphore. So even if you don't get the semaphore, still
568          * continue the access. We don't need the semaphore anyway. */
569         snd_printk("codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
570                         igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
571         iagetword(chip, 0);     /* clear semaphore flag */
572         /* I don't care about the semaphore */
573         return -EBUSY;
574 }
575  
576 static void snd_intel8x0_codec_write(ac97_t *ac97,
577                                      unsigned short reg,
578                                      unsigned short val)
579 {
580         intel8x0_t *chip = snd_magic_cast(intel8x0_t, ac97->private_data, return);
581         
582         spin_lock(&chip->ac97_lock);
583         if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
584                 if (! chip->in_ac97_init)
585                         snd_printk("codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
586         }
587         iaputword(chip, reg + ac97->num * 0x80, val);
588         spin_unlock(&chip->ac97_lock);
589 }
590 
591 static unsigned short snd_intel8x0_codec_read(ac97_t *ac97,
592                                               unsigned short reg)
593 {
594         intel8x0_t *chip = snd_magic_cast(intel8x0_t, ac97->private_data, return ~0);
595         unsigned short res;
596         unsigned int tmp;
597 
598         spin_lock(&chip->ac97_lock);
599         if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
600                 if (! chip->in_ac97_init)
601                         snd_printk("codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
602                 res = 0xffff;
603         } else {
604                 res = iagetword(chip, reg + ac97->num * 0x80);
605                 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
606                         /* reset RCS and preserve other R/WC bits */
607                         iputdword(chip, ICHREG(GLOB_STA), tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
608                         if (! chip->in_ac97_init)
609                                 snd_printk("codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
610                         res = 0xffff;
611                 }
612         }
613         spin_unlock(&chip->ac97_lock);
614         return res;
615 }
616 
617 /*
618  * access to AC97 for Ali5455
619  */
620 static int snd_intel8x0_ali_codec_ready(intel8x0_t *chip, int mask)
621 {
622         int count = 0;
623         for (count = 0; count < 0x7f; count++) {
624                 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
625                 if (val & mask)
626                         return 0;
627         }
628         snd_printd(KERN_WARNING "intel8x0: AC97 codec ready timeout.\n");
629         return -EBUSY;
630 }
631 
632 static int snd_intel8x0_ali_codec_semaphore(intel8x0_t *chip)
633 {
634         int time = 100;
635         while (time-- && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
636                 udelay(1);
637         if (! time)
638                 snd_printk(KERN_WARNING "ali_codec_semaphore timeout\n");
639         return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
640 }
641 
642 static unsigned short snd_intel8x0_ali_codec_read(ac97_t *ac97, unsigned short reg)
643 {
644         intel8x0_t *chip = snd_magic_cast(intel8x0_t, ac97->private_data, return ~0);
645         unsigned short data = 0xffff;
646 
647         spin_lock(&chip->ac97_lock);
648         if (snd_intel8x0_ali_codec_semaphore(chip))
649                 goto __err;
650         reg |= ALI_CPR_ADDR_READ;
651         if (ac97->num)
652                 reg |= ALI_CPR_ADDR_SECONDARY;
653         iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
654         if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
655                 goto __err;
656         data = igetword(chip, ICHREG(ALI_SPR));
657  __err:
658         spin_unlock(&chip->ac97_lock);
659         return data;
660 }
661 
662 static void snd_intel8x0_ali_codec_write(ac97_t *ac97, unsigned short reg, unsigned short val)
663 {
664         intel8x0_t *chip = snd_magic_cast(intel8x0_t, ac97->private_data, return);
665 
666         spin_lock(&chip->ac97_lock);
667         if (snd_intel8x0_ali_codec_semaphore(chip)) {
668                 spin_unlock(&chip->ac97_lock);
669                 return;
670         }
671         iputword(chip, ICHREG(ALI_CPR), val);
672         if (ac97->num)
673                 reg |= ALI_CPR_ADDR_SECONDARY;
674         iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
675         snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
676         spin_unlock(&chip->ac97_lock);
677 }
678 
679 
680 /*
681  * DMA I/O
682  */
683 static void snd_intel8x0_setup_periods(intel8x0_t *chip, ichdev_t *ichdev) 
684 {
685         int idx;
686         u32 *bdbar = ichdev->bdbar;
687         unsigned long port = ichdev->reg_offset;
688 
689         iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
690         if (ichdev->size == ichdev->fragsize) {
691                 ichdev->ack_reload = ichdev->ack = 2;
692                 ichdev->fragsize1 = ichdev->fragsize >> 1;
693                 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
694                         bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
695                         bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
696                                                      ichdev->fragsize1 >> chip->pcm_pos_shift);
697                         bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
698                         bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
699                                                      ichdev->fragsize1 >> chip->pcm_pos_shift);
700                 }
701                 ichdev->frags = 2;
702         } else {
703                 ichdev->ack_reload = ichdev->ack = 1;
704                 ichdev->fragsize1 = ichdev->fragsize;
705                 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
706                         bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + (((idx >> 1) * ichdev->fragsize) % ichdev->size));
707                         bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
708                                                      ichdev->fragsize >> chip->pcm_pos_shift);
709                         // printk("bdbar[%i] = 0x%x [0x%x]\n", idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
710                 }
711                 ichdev->frags = ichdev->size / ichdev->fragsize;
712         }
713         iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
714         ichdev->civ = 0;
715         iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
716         ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
717         ichdev->position = 0;
718 #if 0
719         printk("lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
720                         ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, ichdev->fragsize1);
721 #endif
722         /* clear interrupts */
723         iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
724 }
725 
726 /*
727  *  Interrupt handler
728  */
729 
730 static inline void snd_intel8x0_update(intel8x0_t *chip, ichdev_t *ichdev)
731 {
732         unsigned long port = ichdev->reg_offset;
733         int civ, i, step;
734         int ack = 0;
735 
736         civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
737         if (civ == ichdev->civ) {
738                 // snd_printd("civ same %d\n", civ);
739                 step = 1;
740                 ichdev->civ++;
741                 ichdev->civ &= ICH_REG_LVI_MASK;
742         } else {
743                 step = civ - ichdev->civ;
744                 if (step < 0)
745                         step += ICH_REG_LVI_MASK + 1;
746                 // if (step != 1)
747                 //      snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
748                 ichdev->civ = civ;
749         }
750 
751         ichdev->position += step * ichdev->fragsize1;
752         ichdev->position %= ichdev->size;
753         ichdev->lvi += step;
754         ichdev->lvi &= ICH_REG_LVI_MASK;
755         iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
756         for (i = 0; i < step; i++) {
757                 ichdev->lvi_frag++;
758                 ichdev->lvi_frag %= ichdev->frags;
759                 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
760         // printk("new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n", ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2], ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port), inl(port + 4), inb(port + ICH_REG_OFF_CR));
761                 if (--ichdev->ack == 0) {
762                         ichdev->ack = ichdev->ack_reload;
763                         ack = 1;
764                 }
765         }
766         if (ack && ichdev->substream) {
767                 spin_unlock(&chip->reg_lock);
768                 snd_pcm_period_elapsed(ichdev->substream);
769                 spin_lock(&chip->reg_lock);
770         }
771         iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
772 }
773 
774 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id, struct pt_regs *regs)
775 {
776         intel8x0_t *chip = snd_magic_cast(intel8x0_t, dev_id, return IRQ_NONE);
777         ichdev_t *ichdev;
778         unsigned int status;
779         unsigned int i;
780 
781         spin_lock(&chip->reg_lock);
782         status = igetdword(chip, chip->int_sta_reg);
783         if ((status & chip->int_sta_mask) == 0) {
784                 if (status)
785                         iputdword(chip, chip->int_sta_reg, status);
786                 spin_unlock(&chip->reg_lock);
787                 return IRQ_NONE;
788         }
789 
790         for (i = 0; i < chip->bdbars_count; i++) {
791                 ichdev = &chip->ichd[i];
792                 if (status & ichdev->int_sta_mask)
793                         snd_intel8x0_update(chip, ichdev);
794         }
795 
796         /* ack them */
797         iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
798         spin_unlock(&chip->reg_lock);
799         
800         return IRQ_HANDLED;
801 }
802 
803 /*
804  *  PCM part
805  */
806 
807 static int snd_intel8x0_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
808 {
809         intel8x0_t *chip = snd_pcm_substream_chip(substream);
810         ichdev_t *ichdev = get_ichdev(substream);
811         unsigned char val = 0;
812         unsigned long port = ichdev->reg_offset;
813 
814         switch (cmd) {
815         case SNDRV_PCM_TRIGGER_START:
816         case SNDRV_PCM_TRIGGER_RESUME:
817                 val = ICH_IOCE | ICH_STARTBM;
818                 break;
819         case SNDRV_PCM_TRIGGER_STOP:
820         case SNDRV_PCM_TRIGGER_SUSPEND:
821                 val = 0;
822                 break;
823         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
824                 val = ICH_IOCE;
825                 break;
826         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
827                 val = ICH_IOCE | ICH_STARTBM;
828                 break;
829         default:
830                 return -EINVAL;
831         }
832         iputbyte(chip, port + ICH_REG_OFF_CR, val);
833         if (cmd == SNDRV_PCM_TRIGGER_STOP) {
834                 /* wait until DMA stopped */
835                 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
836                 /* reset whole DMA things */
837                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
838         }
839         return 0;
840 }
841 
842 static int snd_intel8x0_ali_trigger(snd_pcm_substream_t *substream, int cmd)
843 {
844         intel8x0_t *chip = snd_pcm_substream_chip(substream);
845         ichdev_t *ichdev = get_ichdev(substream);
846         unsigned long port = ichdev->reg_offset;
847         static int fiforeg[] = { ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3) };
848         unsigned int val, fifo;
849 
850         val = igetdword(chip, ICHREG(ALI_DMACR));
851         switch (cmd) {
852         case SNDRV_PCM_TRIGGER_START:
853         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
854         case SNDRV_PCM_TRIGGER_RESUME:
855                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
856                         /* clear FIFO for synchronization of channels */
857                         fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
858                         fifo &= ~(0xff << (ichdev->ali_slot % 4));  
859                         fifo |= 0x83 << (ichdev->ali_slot % 4); 
860                         iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
861                 }
862                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
863                 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
864                 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot)); /* start DMA */
865                 break;
866         case SNDRV_PCM_TRIGGER_STOP:
867         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
868         case SNDRV_PCM_TRIGGER_SUSPEND:
869                 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16))); /* pause */
870                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
871                 while (igetbyte(chip, port + ICH_REG_OFF_CR))
872                         ;
873                 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
874                         break;
875                 /* reset whole DMA things */
876                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
877                 /* clear interrupts */
878                 iputbyte(chip, port + ICH_REG_OFF_SR, igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
879                 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
880                           igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
881                 break;
882         default:
883                 return -EINVAL;
884         }
885         return 0;
886 }
887 
888 static int snd_intel8x0_hw_params(snd_pcm_substream_t * substream,
889                                   snd_pcm_hw_params_t * hw_params)
890 {
891         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
892 }
893 
894 static int snd_intel8x0_hw_free(snd_pcm_substream_t * substream)
895 {
896         return snd_pcm_lib_free_pages(substream);
897 }
898 
899 static void snd_intel8x0_setup_multi_channels(intel8x0_t *chip, int channels)
900 {
901         unsigned int cnt;
902         switch (chip->device_type) {
903         case DEVICE_ALI:
904                 cnt = igetdword(chip, ICHREG(ALI_SCR));
905                 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
906                 if (chip->multi4 && channels == 4)
907                         cnt |= ICH_ALI_SC_PCM_4;
908                 else if (chip->multi6 && channels == 6)
909                         cnt |= ICH_ALI_SC_PCM_6;
910                 iputdword(chip, ICHREG(ALI_SCR), cnt);
911                 break;
912         case DEVICE_SIS:
913                 cnt = igetdword(chip, ICHREG(GLOB_CNT));
914                 cnt &= ~ICH_SIS_PCM_246_MASK;
915                 if (chip->multi4 && channels == 4)
916                         cnt |= ICH_SIS_PCM_4;
917                 else if (chip->multi6 && channels == 6)
918                         cnt |= ICH_SIS_PCM_6;
919                 iputdword(chip, ICHREG(GLOB_CNT), cnt);
920                 break;
921         default:
922                 cnt = igetdword(chip, ICHREG(GLOB_CNT));
923                 cnt &= ~ICH_PCM_246_MASK;
924                 if (chip->multi4 && channels == 4)
925                         cnt |= ICH_PCM_4;
926                 else if (chip->multi6 && channels == 6)
927                         cnt |= ICH_PCM_6;
928                 iputdword(chip, ICHREG(GLOB_CNT), cnt);
929                 break;
930         }
931 }
932 
933 static int snd_intel8x0_pcm_prepare(snd_pcm_substream_t * substream)
934 {
935         intel8x0_t *chip = snd_pcm_substream_chip(substream);
936         snd_pcm_runtime_t *runtime = substream->runtime;
937         ichdev_t *ichdev = get_ichdev(substream);
938         int i;
939 
940         ichdev->physbuf = runtime->dma_addr;
941         ichdev->size = snd_pcm_lib_buffer_bytes(substream);
942         ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
943         if (ichdev->ichd == ICHD_PCMOUT) {
944                 spin_lock(&chip->reg_lock);
945                 snd_intel8x0_setup_multi_channels(chip, runtime->channels);
946                 spin_unlock(&chip->reg_lock);
947         }
948         if (ichdev->ac97) {
949                 for (i = 0; i < 3; i++)
950                         if (ichdev->ac97_rate_regs[i])
951                                 snd_ac97_set_rate(ichdev->ac97, ichdev->ac97_rate_regs[i], runtime->rate);
952                 /* FIXME: hack to enable spdif support */
953                 if (ichdev->ichd == ICHD_PCMOUT && chip->device_type == DEVICE_SIS)
954                         snd_ac97_set_rate(ichdev->ac97, AC97_SPDIF, runtime->rate);
955         }
956         snd_intel8x0_setup_periods(chip, ichdev);
957         return 0;
958 }
959 
960 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(snd_pcm_substream_t * substream)
961 {
962         intel8x0_t *chip = snd_pcm_substream_chip(substream);
963         ichdev_t *ichdev = get_ichdev(substream);
964         size_t ptr1, ptr;
965 
966         ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << chip->pcm_pos_shift;
967         if (ptr1 != 0)
968                 ptr = ichdev->fragsize1 - ptr1;
969         else
970                 ptr = 0;
971         ptr += ichdev->position;
972         if (ptr >= ichdev->size)
973                 return 0;
974         return bytes_to_frames(substream->runtime, ptr);
975 }
976 
977 static snd_pcm_hardware_t snd_intel8x0_stream =
978 {
979         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
980                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
981                                  SNDRV_PCM_INFO_MMAP_VALID |
982                                  SNDRV_PCM_INFO_PAUSE |
983                                  SNDRV_PCM_INFO_RESUME),
984         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
985         .rates =                SNDRV_PCM_RATE_48000,
986         .rate_min =             48000,
987         .rate_max =             48000,
988         .channels_min =         2,
989         .channels_max =         2,
990         .buffer_bytes_max =     128 * 1024,
991         .period_bytes_min =     32,
992         .period_bytes_max =     128 * 1024,
993         .periods_min =          1,
994         .periods_max =          1024,
995         .fifo_size =            0,
996 };
997 
998 static unsigned int channels4[] = {
999         2, 4,
1000 };
1001 
1002 #define CHANNELS4 sizeof(channels4) / sizeof(channels4[0])
1003 
1004 static snd_pcm_hw_constraint_list_t hw_constraints_channels4 = {
1005         .count = CHANNELS4,
1006         .list = channels4,
1007         .mask = 0,
1008 };
1009 
1010 static unsigned int channels6[] = {
1011         2, 4, 6,
1012 };
1013 
1014 #define CHANNELS6 sizeof(channels6) / sizeof(channels6[0])
1015 
1016 static snd_pcm_hw_constraint_list_t hw_constraints_channels6 = {
1017         .count = CHANNELS6,
1018         .list = channels6,
1019         .mask = 0,
1020 };
1021 
1022 static int snd_intel8x0_pcm_open(snd_pcm_substream_t * substream, ichdev_t *ichdev)
1023 {
1024         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1025         snd_pcm_runtime_t *runtime = substream->runtime;
1026         static unsigned int i, rates[] = {
1027                 /* ATTENTION: these values depend on the definition in pcm.h! */
1028                 5512, 8000, 11025, 16000, 22050, 32000, 44100, 48000
1029         };
1030         int err;
1031 
1032         ichdev->substream = substream;
1033         runtime->hw = snd_intel8x0_stream;
1034         if (ichdev->ac97 && ichdev->ac97_rates_idx >= 0) {
1035                 runtime->hw.rates = ichdev->ac97->rates[ichdev->ac97_rates_idx];
1036                 for (i = 0; i < ARRAY_SIZE(rates); i++) {
1037                         if (runtime->hw.rates & (1 << i)) {
1038                                 runtime->hw.rate_min = rates[i];
1039                                 break;
1040                         }
1041                 }
1042         }
1043         if (chip->device_type == DEVICE_SIS) {
1044                 runtime->hw.buffer_bytes_max = 64*1024;
1045                 runtime->hw.period_bytes_max = 64*1024;
1046         }
1047         if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1048                 return err;
1049         runtime->private_data = ichdev;
1050         return 0;
1051 }
1052 
1053 static int snd_intel8x0_playback_open(snd_pcm_substream_t * substream)
1054 {
1055         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1056         snd_pcm_runtime_t *runtime = substream->runtime;
1057         int err;
1058 
1059         err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1060         if (chip->multi6) {
1061                 runtime->hw.channels_max = 6;
1062                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels6);
1063         } else if (chip->multi4) {
1064                 runtime->hw.channels_max = 4;
1065                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels4);
1066         }
1067         return 0;
1068 }
1069 
1070 static int snd_intel8x0_playback_close(snd_pcm_substream_t * substream)
1071 {
1072         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1073 
1074         chip->ichd[ICHD_PCMOUT].substream = NULL;
1075         return 0;
1076 }
1077 
1078 static int snd_intel8x0_capture_open(snd_pcm_substream_t * substream)
1079 {
1080         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1081 
1082         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1083 }
1084 
1085 static int snd_intel8x0_capture_close(snd_pcm_substream_t * substream)
1086 {
1087         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1088 
1089         chip->ichd[ICHD_PCMIN].substream = NULL;
1090         return 0;
1091 }
1092 
1093 static int snd_intel8x0_mic_open(snd_pcm_substream_t * substream)
1094 {
1095         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1096 
1097         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1098 }
1099 
1100 static int snd_intel8x0_mic_close(snd_pcm_substream_t * substream)
1101 {
1102         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1103 
1104         chip->ichd[ICHD_MIC].substream = NULL;
1105         return 0;
1106 }
1107 
1108 static int snd_intel8x0_mic2_open(snd_pcm_substream_t * substream)
1109 {
1110         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1111 
1112         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1113 }
1114 
1115 static int snd_intel8x0_mic2_close(snd_pcm_substream_t * substream)
1116 {
1117         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1118 
1119         chip->ichd[ICHD_MIC2].substream = NULL;
1120         return 0;
1121 }
1122 
1123 static int snd_intel8x0_capture2_open(snd_pcm_substream_t * substream)
1124 {
1125         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1126 
1127         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1128 }
1129 
1130 static int snd_intel8x0_capture2_close(snd_pcm_substream_t * substream)
1131 {
1132         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1133 
1134         chip->ichd[ICHD_PCM2IN].substream = NULL;
1135         return 0;
1136 }
1137 
1138 static int snd_intel8x0_spdif_open(snd_pcm_substream_t * substream)
1139 {
1140         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1141         int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1142 
1143         return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1144 }
1145 
1146 static int snd_intel8x0_spdif_close(snd_pcm_substream_t * substream)
1147 {
1148         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1149         int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1150 
1151         chip->ichd[idx].substream = NULL;
1152         return 0;
1153 }
1154 
1155 static int snd_intel8x0_ali_ac97spdifout_open(snd_pcm_substream_t * substream)
1156 {
1157         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1158         unsigned long flags;
1159         unsigned int val;
1160 
1161         spin_lock_irqsave(&chip->reg_lock, flags);
1162         val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1163         val |= ICH_ALI_IF_AC97SP;
1164         /* also needs to set ALI_SC_CODEC_SPDF correctly */
1165         spin_unlock_irqrestore(&chip->reg_lock, flags);
1166 
1167         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1168 }
1169 
1170 static int snd_intel8x0_ali_ac97spdifout_close(snd_pcm_substream_t * substream)
1171 {
1172         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1173         unsigned long flags;
1174         unsigned int val;
1175 
1176         chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1177         spin_lock_irqsave(&chip->reg_lock, flags);
1178         val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1179         val &= ~ICH_ALI_IF_AC97SP;
1180         spin_unlock_irqrestore(&chip->reg_lock, flags);
1181 
1182         return 0;
1183 }
1184 
1185 static int snd_intel8x0_ali_spdifin_open(snd_pcm_substream_t * substream)
1186 {
1187         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1188 
1189         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1190 }
1191 
1192 static int snd_intel8x0_ali_spdifin_close(snd_pcm_substream_t * substream)
1193 {
1194         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1195 
1196         chip->ichd[ALID_SPDIFIN].substream = NULL;
1197         return 0;
1198 }
1199 
1200 #if 0 // NYI
1201 static int snd_intel8x0_ali_spdifout_open(snd_pcm_substream_t * substream)
1202 {
1203         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1204 
1205         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1206 }
1207 
1208 static int snd_intel8x0_ali_spdifout_close(snd_pcm_substream_t * substream)
1209 {
1210         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1211 
1212         chip->ichd[ALID_SPDIFOUT].substream = NULL;
1213         return 0;
1214 }
1215 #endif
1216 
1217 static snd_pcm_ops_t snd_intel8x0_playback_ops = {
1218         .open =         snd_intel8x0_playback_open,
1219         .close =        snd_intel8x0_playback_close,
1220         .ioctl =        snd_pcm_lib_ioctl,
1221         .hw_params =    snd_intel8x0_hw_params,
1222         .hw_free =      snd_intel8x0_hw_free,
1223         .prepare =      snd_intel8x0_pcm_prepare,
1224         .trigger =      snd_intel8x0_pcm_trigger,
1225         .pointer =      snd_intel8x0_pcm_pointer,
1226 };
1227 
1228 static snd_pcm_ops_t snd_intel8x0_capture_ops = {
1229         .open =         snd_intel8x0_capture_open,
1230         .close =        snd_intel8x0_capture_close,
1231         .ioctl =        snd_pcm_lib_ioctl,
1232         .hw_params =    snd_intel8x0_hw_params,
1233         .hw_free =      snd_intel8x0_hw_free,
1234         .prepare =      snd_intel8x0_pcm_prepare,
1235         .trigger =      snd_intel8x0_pcm_trigger,
1236         .pointer =      snd_intel8x0_pcm_pointer,
1237 };
1238 
1239 static snd_pcm_ops_t snd_intel8x0_capture_mic_ops = {
1240         .open =         snd_intel8x0_mic_open,
1241         .close =        snd_intel8x0_mic_close,
1242         .ioctl =        snd_pcm_lib_ioctl,
1243         .hw_params =    snd_intel8x0_hw_params,
1244         .hw_free =      snd_intel8x0_hw_free,
1245         .prepare =      snd_intel8x0_pcm_prepare,
1246         .trigger =      snd_intel8x0_pcm_trigger,
1247         .pointer =      snd_intel8x0_pcm_pointer,
1248 };
1249 
1250 static snd_pcm_ops_t snd_intel8x0_capture_mic2_ops = {
1251         .open =         snd_intel8x0_mic2_open,
1252         .close =        snd_intel8x0_mic2_close,
1253         .ioctl =        snd_pcm_lib_ioctl,
1254         .hw_params =    snd_intel8x0_hw_params,
1255         .hw_free =      snd_intel8x0_hw_free,
1256         .prepare =      snd_intel8x0_pcm_prepare,
1257         .trigger =      snd_intel8x0_pcm_trigger,
1258         .pointer =      snd_intel8x0_pcm_pointer,
1259 };
1260 
1261 static snd_pcm_ops_t snd_intel8x0_capture2_ops = {
1262         .open =         snd_intel8x0_capture2_open,
1263         .close =        snd_intel8x0_capture2_close,
1264         .ioctl =        snd_pcm_lib_ioctl,
1265         .hw_params =    snd_intel8x0_hw_params,
1266         .hw_free =      snd_intel8x0_hw_free,
1267         .prepare =      snd_intel8x0_pcm_prepare,
1268         .trigger =      snd_intel8x0_pcm_trigger,
1269         .pointer =      snd_intel8x0_pcm_pointer,
1270 };
1271 
1272 static snd_pcm_ops_t snd_intel8x0_spdif_ops = {
1273         .open =         snd_intel8x0_spdif_open,
1274         .close =        snd_intel8x0_spdif_close,
1275         .ioctl =        snd_pcm_lib_ioctl,
1276         .hw_params =    snd_intel8x0_hw_params,
1277         .hw_free =      snd_intel8x0_hw_free,
1278         .prepare =      snd_intel8x0_pcm_prepare,
1279         .trigger =      snd_intel8x0_pcm_trigger,
1280         .pointer =      snd_intel8x0_pcm_pointer,
1281 };
1282 
1283 static snd_pcm_ops_t snd_intel8x0_ali_playback_ops = {
1284         .open =         snd_intel8x0_playback_open,
1285         .close =        snd_intel8x0_playback_close,
1286         .ioctl =        snd_pcm_lib_ioctl,
1287         .hw_params =    snd_intel8x0_hw_params,
1288         .hw_free =      snd_intel8x0_hw_free,
1289         .prepare =      snd_intel8x0_pcm_prepare,
1290         .trigger =      snd_intel8x0_ali_trigger,
1291         .pointer =      snd_intel8x0_pcm_pointer,
1292 };
1293 
1294 static snd_pcm_ops_t snd_intel8x0_ali_capture_ops = {
1295         .open =         snd_intel8x0_capture_open,
1296         .close =        snd_intel8x0_capture_close,
1297         .ioctl =        snd_pcm_lib_ioctl,
1298         .hw_params =    snd_intel8x0_hw_params,
1299         .hw_free =      snd_intel8x0_hw_free,
1300         .prepare =      snd_intel8x0_pcm_prepare,
1301         .trigger =      snd_intel8x0_ali_trigger,
1302         .pointer =      snd_intel8x0_pcm_pointer,
1303 };
1304 
1305 static snd_pcm_ops_t snd_intel8x0_ali_capture_mic_ops = {
1306         .open =         snd_intel8x0_mic_open,
1307         .close =        snd_intel8x0_mic_close,
1308         .ioctl =        snd_pcm_lib_ioctl,
1309         .hw_params =    snd_intel8x0_hw_params,
1310         .hw_free =      snd_intel8x0_hw_free,
1311         .prepare =      snd_intel8x0_pcm_prepare,
1312         .trigger =      snd_intel8x0_ali_trigger,
1313         .pointer =      snd_intel8x0_pcm_pointer,
1314 };
1315 
1316 static snd_pcm_ops_t snd_intel8x0_ali_ac97spdifout_ops = {
1317         .open =         snd_intel8x0_ali_ac97spdifout_open,
1318         .close =        snd_intel8x0_ali_ac97spdifout_close,
1319         .ioctl =        snd_pcm_lib_ioctl,
1320         .hw_params =    snd_intel8x0_hw_params,
1321         .hw_free =      snd_intel8x0_hw_free,
1322         .prepare =      snd_intel8x0_pcm_prepare,
1323         .trigger =      snd_intel8x0_ali_trigger,
1324         .pointer =      snd_intel8x0_pcm_pointer,
1325 };
1326 
1327 static snd_pcm_ops_t snd_intel8x0_ali_spdifin_ops = {
1328         .open =         snd_intel8x0_ali_spdifin_open,
1329         .close =        snd_intel8x0_ali_spdifin_close,
1330         .ioctl =        snd_pcm_lib_ioctl,
1331         .hw_params =    snd_intel8x0_hw_params,
1332         .hw_free =      snd_intel8x0_hw_free,
1333         .prepare =      snd_intel8x0_pcm_prepare,
1334         .trigger =      snd_intel8x0_pcm_trigger,
1335         .pointer =      snd_intel8x0_pcm_pointer,
1336 };
1337 
1338 #if 0 // NYI
1339 static snd_pcm_ops_t snd_intel8x0_ali_spdifout_ops = {
1340         .open =         snd_intel8x0_ali_spdifout_open,
1341         .close =        snd_intel8x0_ali_spdifout_close,
1342         .ioctl =        snd_pcm_lib_ioctl,
1343         .hw_params =    snd_intel8x0_hw_params,
1344         .hw_free =      snd_intel8x0_hw_free,
1345         .prepare =      snd_intel8x0_pcm_prepare,
1346         .trigger =      snd_intel8x0_pcm_trigger,
1347         .pointer =      snd_intel8x0_pcm_pointer,
1348 };
1349 #endif // NYI
1350 
1351 struct ich_pcm_table {
1352         char *suffix;
1353         snd_pcm_ops_t *playback_ops;
1354         snd_pcm_ops_t *capture_ops;
1355         size_t prealloc_size;
1356         size_t prealloc_max_size;
1357         int ac97_idx;
1358 };
1359 
1360 static int __devinit snd_intel8x0_pcm1(intel8x0_t *chip, int device, struct ich_pcm_table *rec)
1361 {
1362         snd_pcm_t *pcm;
1363         int err;
1364         char name[32];
1365 
1366         if (rec->suffix)
1367                 sprintf(name, "Intel ICH - %s", rec->suffix);
1368         else
1369                 strcpy(name, "Intel ICH");
1370         err = snd_pcm_new(chip->card, name, device,
1371                           rec->playback_ops ? 1 : 0,
1372                           rec->capture_ops ? 1 : 0, &pcm);
1373         if (err < 0)
1374                 return err;
1375 
1376         if (rec->playback_ops)
1377                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1378         if (rec->capture_ops)
1379                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1380 
1381         pcm->private_data = chip;
1382         pcm->info_flags = 0;
1383         if (rec->suffix)
1384                 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1385         else
1386                 strcpy(pcm->name, chip->card->shortname);
1387         chip->pcm[device] = pcm;
1388 
1389         snd_pcm_lib_preallocate_pci_pages_for_all(chip->pci, pcm, rec->prealloc_size,
1390                                                   rec->prealloc_max_size);
1391 
1392         return 0;
1393 }
1394 
1395 static struct ich_pcm_table intel_pcms[] __devinitdata = {
1396         {
1397                 .playback_ops = &snd_intel8x0_playback_ops,
1398                 .capture_ops = &snd_intel8x0_capture_ops,
1399                 .prealloc_size = 64 * 1024,
1400                 .prealloc_max_size = 128 * 1024,
1401         },
1402         {
1403                 .suffix = "MIC ADC",
1404                 .capture_ops = &snd_intel8x0_capture_mic_ops,
1405                 .prealloc_size = 0,
1406                 .prealloc_max_size = 128 * 1024,
1407                 .ac97_idx = ICHD_MIC,
1408         },
1409         {
1410                 .suffix = "MIC2 ADC",
1411                 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1412                 .prealloc_size = 0,
1413                 .prealloc_max_size = 128 * 1024,
1414                 .ac97_idx = ICHD_MIC2,
1415         },
1416         {
1417                 .suffix = "ADC2",
1418                 .capture_ops = &snd_intel8x0_capture2_ops,
1419                 .prealloc_size = 0,
1420                 .prealloc_max_size = 128 * 1024,
1421                 .ac97_idx = ICHD_PCM2IN,
1422         },
1423         {
1424                 .suffix = "IEC958",
1425                 .playback_ops = &snd_intel8x0_spdif_ops,
1426                 .prealloc_size = 64 * 1024,
1427                 .prealloc_max_size = 128 * 1024,
1428                 .ac97_idx = ICHD_SPBAR,
1429         },
1430 };
1431 
1432 static struct ich_pcm_table nforce_pcms[] __devinitdata = {
1433         {
1434                 .playback_ops = &snd_intel8x0_playback_ops,
1435                 .capture_ops = &snd_intel8x0_capture_ops,
1436                 .prealloc_size = 64 * 1024,
1437                 .prealloc_max_size = 128 * 1024,
1438         },
1439         {
1440                 .suffix = "MIC ADC",
1441                 .capture_ops = &snd_intel8x0_capture_mic_ops,
1442                 .prealloc_size = 0,
1443                 .prealloc_max_size = 128 * 1024,
1444                 .ac97_idx = NVD_MIC,
1445         },
1446         {
1447                 .suffix = "IEC958",
1448                 .playback_ops = &snd_intel8x0_spdif_ops,
1449                 .prealloc_size = 64 * 1024,
1450                 .prealloc_max_size = 128 * 1024,
1451                 .ac97_idx = NVD_SPBAR,
1452         },
1453 };
1454 
1455 static struct ich_pcm_table ali_pcms[] __devinitdata = {
1456         {
1457                 .playback_ops = &snd_intel8x0_ali_playback_ops,
1458                 .capture_ops = &snd_intel8x0_ali_capture_ops,
1459                 .prealloc_size = 64 * 1024,
1460                 .prealloc_max_size = 128 * 1024,
1461         },
1462         {
1463                 .suffix = "MIC ADC",
1464                 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1465                 .prealloc_size = 0,
1466                 .prealloc_max_size = 128 * 1024,
1467                 .ac97_idx = ALID_MIC,
1468         },
1469         {
1470                 .suffix = "IEC958",
1471                 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1472                 .capture_ops = &snd_intel8x0_ali_spdifin_ops,
1473                 .prealloc_size = 64 * 1024,
1474                 .prealloc_max_size = 128 * 1024,
1475                 .ac97_idx = ALID_AC97SPDIFOUT,
1476         },
1477 #if 0 // NYI
1478         {
1479                 .suffix = "HW IEC958",
1480                 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1481                 .prealloc_size = 64 * 1024,
1482                 .prealloc_max_size = 128 * 1024,
1483         },
1484 #endif
1485 };
1486 
1487 static int __devinit snd_intel8x0_pcm(intel8x0_t *chip)
1488 {
1489         int i, tblsize, device, err;
1490         struct ich_pcm_table *tbl, *rec;
1491 
1492         switch (chip->device_type) {
1493         case DEVICE_INTEL_ICH4:
1494                 tbl = intel_pcms;
1495                 tblsize = ARRAY_SIZE(intel_pcms);
1496                 break;
1497         case DEVICE_NFORCE:
1498                 tbl = nforce_pcms;
1499                 tblsize = ARRAY_SIZE(nforce_pcms);
1500                 break;
1501         case DEVICE_ALI:
1502                 tbl = ali_pcms;
1503                 tblsize = ARRAY_SIZE(ali_pcms);
1504                 break;
1505         default:
1506                 tbl = intel_pcms;
1507                 tblsize = 2;
1508                 break;
1509         }
1510 
1511         device = 0;
1512         for (i = 0; i < tblsize; i++) {
1513                 rec = tbl + i;
1514                 if (i > 0 && rec->ac97_idx) {
1515                         /* activate PCM only when associated AC'97 codec */
1516                         if (! chip->ichd[rec->ac97_idx].ac97)
1517                                 continue;
1518                 }
1519                 err = snd_intel8x0_pcm1(chip, device, rec);
1520                 if (err < 0)
1521                         return err;
1522                 device++;
1523         }
1524 
1525         chip->pcm_devs = device;
1526         return 0;
1527 }
1528         
1529 
1530 /*
1531  *  Mixer part
1532  */
1533 
1534 static void snd_intel8x0_mixer_free_ac97(ac97_t *ac97)
1535 {
1536         intel8x0_t *chip = snd_magic_cast(intel8x0_t, ac97->private_data, return);
1537         chip->ac97[ac97->num] = NULL;
1538 }
1539 
1540 struct _ac97_rate_regs {
1541         unsigned int ichd;
1542         unsigned short regs[3];
1543         short rates_idx;
1544 };
1545 
1546 static struct _ac97_rate_regs intel_ac97_rate_regs[] __devinitdata = {
1547         { ICHD_PCMOUT, { AC97_PCM_FRONT_DAC_RATE, AC97_PCM_SURR_DAC_RATE, AC97_PCM_LFE_DAC_RATE }, AC97_RATES_FRONT_DAC },
1548         { ICHD_PCMIN, { AC97_PCM_LR_ADC_RATE, 0, 0 }, AC97_RATES_ADC },
1549         { ICHD_MIC, { AC97_PCM_MIC_ADC_RATE, 0, 0 }, AC97_RATES_MIC_ADC },
1550         { ICHD_MIC2, { AC97_PCM_MIC_ADC_RATE, 0, 0 }, AC97_RATES_MIC_ADC },
1551         { ICHD_PCM2IN, { AC97_PCM_LR_ADC_RATE, 0, 0 }, AC97_RATES_ADC },
1552         { ICHD_SPBAR, { AC97_SPDIF, 0, 0 }, AC97_RATES_SPDIF },
1553 };
1554 
1555 static struct _ac97_rate_regs nforce_ac97_rate_regs[] __devinitdata = {
1556         { NVD_PCMOUT, { AC97_PCM_FRONT_DAC_RATE, AC97_PCM_SURR_DAC_RATE, AC97_PCM_LFE_DAC_RATE }, AC97_RATES_FRONT_DAC },
1557         { NVD_PCMIN, { AC97_PCM_LR_ADC_RATE, 0, 0 }, AC97_RATES_ADC },
1558         { NVD_MIC, { AC97_PCM_MIC_ADC_RATE, 0, 0 }, AC97_RATES_MIC_ADC },
1559         { NVD_SPBAR, { AC97_SPDIF, AC97_PCM_FRONT_DAC_RATE, 0 }, -1 }, /* spdif is 48k only */
1560 };
1561 
1562 static struct _ac97_rate_regs ali_ac97_rate_regs[] __devinitdata = {
1563 #if 0 /* FIXME: my test board doens't work well with VRA... */
1564         { ALID_PCMOUT, { AC97_PCM_FRONT_DAC_RATE, AC97_PCM_SURR_DAC_RATE, AC97_PCM_LFE_DAC_RATE }, AC97_RATES_FRONT_DAC },
1565         { ALID_PCMIN, { AC97_PCM_LR_ADC_RATE, 0, 0 }, AC97_RATES_ADC },
1566         { ALID_MIC, { AC97_PCM_MIC_ADC_RATE, 0, 0 }, AC97_RATES_MIC_ADC },
1567         { ALID_AC97SPDIFOUT, { AC97_SPDIF, 0, 0 }, AC97_RATES_SPDIF },
1568         { ALID_SPDIFOUT, { 0, 0, 0 }, -1 },
1569         { ALID_SPDIFIN, { 0, 0, 0 }, -1 },
1570 #else
1571         { ALID_PCMOUT, { AC97_PCM_FRONT_DAC_RATE }, -1 },
1572         { ALID_PCMIN, { AC97_PCM_LR_ADC_RATE }, -1 },
1573         { ALID_MIC, { AC97_PCM_MIC_ADC_RATE }, -1 },
1574         { ALID_AC97SPDIFOUT, { AC97_SPDIF }, -1 },
1575         { ALID_SPDIFOUT, { }, -1 },
1576         { ALID_SPDIFIN, { }, -1 },
1577 #endif
1578 };
1579 
1580 static struct ac97_quirk ac97_quirks[] __devinitdata = {
1581         {
1582                 .vendor = 0x1028,
1583                 .device = 0x00d8,
1584                 .name = "Dell Precision 530",
1585                 .type = AC97_TUNE_HP_ONLY
1586         },
1587         {
1588                 .vendor = 0x1028,
1589                 .device = 0x0126,
1590                 .name = "Dell Optiplex GX260",
1591                 .type = AC97_TUNE_HP_ONLY
1592         },
1593         {
1594                 .vendor = 0x1028,
1595                 .device = 0x0157,
1596                 .name = "Dell Dimension 8300",
1597                 .type = AC97_TUNE_SWAP_SURROUND
1598         },
1599         {
1600                 .vendor = 0x1043,
1601                 .device =0x80b0,
1602                 .name = "ASUS P4PE Mobo",
1603                 .type = AC97_TUNE_SWAP_SURROUND
1604         },
1605         {
1606                 .vendor = 0x1043,
1607                 .device = 0x80f3,
1608                 .name = "ASUS ICH5/AD1985",
1609                 .type = AC97_TUNE_AD_SHARING
1610         },
1611         {
1612                 .vendor = 0x10f1,
1613                 .device = 0x2665,
1614                 .name = "Fujitsu-Siemens Celcius",
1615                 .type = AC97_TUNE_HP_ONLY
1616         },
1617         {
1618                 .vendor = 0x110a,
1619                 .device = 0x0056,
1620                 .name = "Fujitsu-Siemens Scenic",
1621                 .type = AC97_TUNE_HP_ONLY
1622         },
1623         {
1624                 .vendor = 0x11d4,
1625                 .device = 0x5375,
1626                 .name = "ADI AD1985 (discrete)",
1627                 .type = AC97_TUNE_HP_ONLY
1628         },
1629         {
1630                 .vendor = 0x1734,
1631                 .device = 0x0088,
1632                 .name = "Fujitsu-Siemens D1522",
1633                 .type = AC97_TUNE_HP_ONLY
1634         },
1635 #if 0
1636         /* FIXME: this seems invalid */
1637         {
1638                 .vendor = 0x4144,
1639                 .device = 0x5360,
1640                 .type = "AMD64 Motherboard",
1641                 .name = AC97_TUNE_HP_ONLY
1642         },
1643 #endif
1644         {
1645                 .vendor = 0x8086,
1646                 .device = 0x2000,
1647                 .mask = 0xfff0,
1648                 .name = "Intel ICH5/AD1985 (discrete)",
1649                 .type = AC97_TUNE_HP_ONLY
1650         },
1651         {
1652                 .vendor = 0x8086,
1653                 .device = 0x4000,
1654                 .mask = 0xfff0,
1655                 .name = "Intel ICH5/AD1985",
1656                 .type = AC97_TUNE_AD_SHARING
1657         },
1658         {
1659                 .vendor = 0x8086,
1660                 .device = 0x4d44,
1661                 .name = "Intel D850EMV2",
1662                 .type = AC97_TUNE_HP_ONLY
1663         },
1664         {
1665                 .vendor = 0x8086,
1666                 .device = 0x6000,
1667                 .mask = 0xfff0,
1668                 .name = "Intel ICH5/AD1985",
1669                 .type = AC97_TUNE_AD_SHARING
1670         },
1671         {
1672                 .vendor = 0x8086,
1673                 .device = 0xe000,
1674                 .mask = 0xfff0,
1675                 .name = "Intel ICH5/AD1985",
1676                 .type = AC97_TUNE_AD_SHARING
1677         },
1678         {
1679                 .vendor = 0x8086,
1680                 .device = 0xa000,
1681                 .mask = 0xfff0,
1682                 .name = "Intel ICH5/AD1985 (discrete)",
1683                 .type = AC97_TUNE_HP_ONLY
1684         },
1685         {
1686                 .vendor = 0x103c,
1687                 .device = 0x00c3,
1688                 .name = "Hewlett-Packard onboard",
1689                 .type = AC97_TUNE_HP_ONLY
1690         },
1691         { } /* terminator */
1692 };
1693 
1694 static int __devinit snd_intel8x0_mixer(intel8x0_t *chip, int ac97_clock)
1695 {
1696         ac97_t ac97, *x97;
1697         ichdev_t *ichdev;
1698         int err;
1699         unsigned int i, num, codecs, _codecs;
1700         unsigned int glob_sta = 0;
1701         struct _ac97_rate_regs *tbl;
1702         int spdif_idx = -1; /* disabled */
1703 
1704         switch (chip->device_type) {
1705         case DEVICE_NFORCE:
1706                 tbl = nforce_ac97_rate_regs;
1707                 spdif_idx = NVD_SPBAR;
1708                 break;
1709         case DEVICE_ALI:
1710                 tbl = ali_ac97_rate_regs;
1711                 spdif_idx = ALID_AC97SPDIFOUT;
1712                 break;
1713         default:
1714                 tbl = intel_ac97_rate_regs;
1715                 if (chip->device_type == DEVICE_INTEL_ICH4)
1716                         spdif_idx = ICHD_SPBAR;
1717                 break;
1718         };
1719         for (i = 0; i < chip->bdbars_count; i++) {
1720                 struct _ac97_rate_regs *aregs = tbl + i;
1721                 ichdev = &chip->ichd[aregs->ichd];
1722                 ichdev->ac97_rate_regs[0] = aregs->regs[0];
1723                 ichdev->ac97_rate_regs[1] = aregs->regs[1];
1724                 ichdev->ac97_rate_regs[2] = aregs->regs[2];
1725                 ichdev->ac97_rates_idx = aregs->rates_idx;
1726         }
1727 
1728         chip->in_ac97_init = 1;
1729         memset(&ac97, 0, sizeof(ac97));
1730         ac97.private_data = chip;
1731         ac97.private_free = snd_intel8x0_mixer_free_ac97;
1732         if (ac97_clock >= 8000 && ac97_clock <= 48000)
1733                 ac97.clock = ac97_clock;
1734         else
1735                 ac97.clock = 48000;
1736         if (chip->device_type != DEVICE_ALI) {
1737                 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
1738                 ac97.write = snd_intel8x0_codec_write;
1739                 ac97.read = snd_intel8x0_codec_read;
1740                 if (chip->device_type == DEVICE_INTEL_ICH4) {
1741                         codecs = 0;
1742                         if (glob_sta & ICH_PCR)
1743                                 codecs++;
1744                         if (glob_sta & ICH_SCR)
1745                                 codecs++;
1746                         if (glob_sta & ICH_TCR)
1747                                 codecs++;
1748                         chip->in_sdin_init = 1;
1749                         for (i = 0; i < codecs; i++) {
1750                                 ac97.num = i;
1751                                 snd_intel8x0_codec_read(&ac97, 0);
1752                                 chip->ac97_sdin[i] = igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
1753                         }
1754                         ac97.num = 0;
1755                         chip->in_sdin_init = 0;
1756                 } else {
1757                         codecs = glob_sta & ICH_SCR ? 2 : 1;
1758                 }
1759         } else {
1760                 ac97.write = snd_intel8x0_ali_codec_write;
1761                 ac97.read = snd_intel8x0_ali_codec_read;
1762                 codecs = 1;
1763                 /* detect the secondary codec */
1764                 for (i = 0; i < 100; i++) {
1765                         unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
1766                         if (reg & 0x40) {
1767                                 codecs = 2;
1768                                 break;
1769                         }
1770                         iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
1771                         udelay(1);
1772                 }
1773         }
1774         ac97.pci = chip->pci;
1775         if ((err = snd_ac97_mixer(chip->card, &ac97, &x97)) < 0) {
1776                 /* clear the cold-reset bit for the next chance */
1777                 if (chip->device_type != DEVICE_ALI)
1778                         iputdword(chip, ICHREG(GLOB_CNT), igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
1779                 return err;
1780         }
1781         chip->ac97[0] = x97;
1782         /* tune up the primary codec */
1783         snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks);
1784         /* the following three entries are common among all devices */
1785         chip->ichd[ICHD_PCMOUT].ac97 = x97;
1786         chip->ichd[ICHD_PCMIN].ac97 = x97;
1787         if (x97->ext_id & AC97_EI_VRM)
1788                 chip->ichd[ICHD_MIC].ac97 = x97;
1789         /* spdif */
1790         if ((x97->ext_id & AC97_EI_SPDIF) && spdif_idx >= 0)
1791                 chip->ichd[spdif_idx].ac97 = x97;
1792         /* make sure, that we have DACs at right slot for rev2.2 */
1793         if (ac97_is_rev22(x97))
1794                 snd_ac97_update_bits(x97, AC97_EXTENDED_ID, AC97_EI_DACS_SLOT_MASK, 0);
1795         /* AnalogDevices CNR boards uses special codec chaining */
1796         /* skip standard test method for secondary codecs in this case */
1797         if (x97->flags & AC97_AD_MULTI)
1798                 codecs = 1;
1799         if (codecs < 2)
1800                 goto __skip_secondary;
1801         for (i = 1, num = 1, _codecs = codecs; num < _codecs; num++) {
1802                 ac97.num = num;
1803                 if ((err = snd_ac97_mixer(chip->card, &ac97, &x97)) < 0) {
1804                         snd_printk("Unable to initialize codec #%i [device = %i, GLOB_STA = 0x%x]\n", i, chip->device_type, glob_sta);
1805                         codecs--;
1806                         continue;
1807                 }
1808                 chip->ac97[i++] = x97;
1809                 if (!ac97_is_audio(x97))
1810                         continue;
1811                 switch (chip->device_type) {
1812                 case DEVICE_INTEL_ICH4:
1813                         if (chip->ichd[ICHD_PCM2IN].ac97 == NULL)
1814                                 chip->ichd[ICHD_PCM2IN].ac97 = x97;
1815                         if (x97->ext_id & AC97_EI_VRM) {
1816                                 if (chip->ichd[ICHD_MIC].ac97 == NULL)
1817                                         chip->ichd[ICHD_MIC].ac97 = x97;
1818                                 else if (chip->ichd[ICHD_MIC2].ac97 == NULL &&
1819                                          chip->ichd[ICHD_PCM2IN].ac97 == x97)
1820                                         chip->ichd[ICHD_MIC2].ac97 = x97;
1821                         }
1822                         break;
1823                 default:
1824                         if (x97->ext_id & AC97_EI_VRM) {
1825                                 if (chip->ichd[ICHD_MIC].ac97 == NULL)
1826                                         chip->ichd[ICHD_MIC].ac97 = x97;
1827                         }
1828                         break;
1829                 }
1830                 if ((x97->ext_id & AC97_EI_SPDIF) && spdif_idx >= 0) {
1831                         if (chip->ichd[spdif_idx].ac97 == NULL)
1832                                 chip->ichd[spdif_idx].ac97 = x97;
1833                 }
1834         }
1835         
1836       __skip_secondary:
1837         if (chip->device_type == DEVICE_INTEL_ICH4) {
1838                 u8 tmp = igetbyte(chip, ICHREG(SDM));
1839                 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
1840                 if (chip->ichd[ICHD_PCM2IN].ac97) {
1841                         tmp |= ICH_SE;  /* steer enable for multiple SDINs */
1842                         tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
1843                         tmp |= chip->ac97_sdin[chip->ichd[ICHD_PCM2IN].ac97->num] << ICH_DI2L_SHIFT;
1844                 } else {
1845                         tmp &= ~ICH_SE;
1846                 }
1847                 iputbyte(chip, ICHREG(SDM), tmp);
1848         }
1849         for (i = 0; i < codecs; i++) {
1850                 x97 = chip->ac97[i];
1851                 if (!ac97_is_audio(x97))
1852                         continue;
1853                 if (x97->scaps & AC97_SCAP_SURROUND_DAC)
1854                         chip->multi4 = 1;
1855         }
1856         for (i = 0; i < codecs && chip->multi4; i++) {
1857                 x97 = chip->ac97[i];
1858                 if (!ac97_is_audio(x97))
1859                         continue;
1860                 if (x97->scaps & AC97_SCAP_CENTER_LFE_DAC)
1861                         chip->multi6 = 1;
1862         }
1863         if (chip->device_type == DEVICE_ALI && chip->ac97[1]) {
1864                 /* set secondary codec id */
1865                 iputdword(chip, ICHREG(ALI_SSR),
1866                           (igetdword(chip, ICHREG(ALI_SSR)) & ~ICH_ALI_SS_SEC_ID) |
1867                           (chip->ac97[1]->addr << 5));
1868         }
1869         if (codecs > 1 && !chip->multi6) {
1870                 /* assign right slots for rev2.2 codecs */
1871                 i = 1;
1872                 for ( ; i < codecs && !chip->multi4; i++) {
1873                         x97 = chip->ac97[i];
1874                         if (!ac97_is_audio(x97))
1875                                 continue;
1876                         if (ac97_is_rev22(x97)) {
1877                                 snd_ac97_update_bits(x97, AC97_EXTENDED_ID, AC97_EI_DACS_SLOT_MASK, 1);
1878                                 chip->multi4 = 1;
1879                         }
1880                 }
1881                 for ( ; i < codecs && chip->multi4; i++) {
1882                         x97 = chip->ac97[i];
1883                         if (!ac97_is_audio(x97))
1884                                 continue;
1885                         if (ac97_is_rev22(x97)) {
1886                                 snd_ac97_update_bits(x97, AC97_EXTENDED_ID, AC97_EI_DACS_SLOT_MASK, 2);
1887                                 chip->multi6 = 1;
1888                                 break;
1889                         }
1890                 }
1891                 /* ok, some older codecs might support only AMAP */
1892                 if (!chip->multi4) {
1893                         int cnums = 0;
1894                         for (i = 1; i < codecs; i++) {
1895                                 x97 = chip->ac97[i];
1896                                 if (!ac97_is_audio(x97))
1897                                         continue;
1898                                 if (ac97_can_amap(x97)) {
1899                                         if (x97->addr > 0)
1900                                                 cnums++;
1901                                 }
1902                         }
1903                         if (cnums >= 2)
1904                                 chip->multi6 = 1;
1905                         if (cnums >= 1)
1906                                 chip->multi4 = 1;
1907                 }
1908         }
1909         chip->in_ac97_init = 0;
1910         return 0;
1911 }
1912 
1913 
1914 /*
1915  *
1916  */
1917 
1918 static void do_ali_reset(intel8x0_t *chip)
1919 {
1920         iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
1921         iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
1922         iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
1923         iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
1924         iputdword(chip, ICHREG(ALI_INTERFACECR),
1925                   ICH_ALI_IF_MC|ICH_ALI_IF_PI|ICH_ALI_IF_PO);
1926         iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
1927         iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
1928 }
1929 
1930 #define do_delay(chip) do {\
1931         set_current_state(TASK_UNINTERRUPTIBLE);\
1932         schedule_timeout(1);\
1933 } while (0)
1934 
1935 static int snd_intel8x0_ich_chip_init(intel8x0_t *chip, int probing)
1936 {
1937         unsigned long end_time;
1938         unsigned int cnt, status, nstatus;
1939         
1940         /* put logic to right state */
1941         /* first clear status bits */
1942         status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
1943         if (chip->device_type == DEVICE_NFORCE)
1944                 status |= ICH_NVSPINT;
1945         cnt = igetdword(chip, ICHREG(GLOB_STA));
1946         iputdword(chip, ICHREG(GLOB_STA), cnt & status);
1947 
1948         /* ACLink on, 2 channels */
1949         cnt = igetdword(chip, ICHREG(GLOB_CNT));
1950         cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
1951         /* finish cold or do warm reset */
1952         cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
1953         iputdword(chip, ICHREG(GLOB_CNT), cnt);
1954         end_time = (jiffies + (HZ / 4)) + 1;
1955         do {
1956                 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
1957                         goto __ok;
1958                 do_delay(chip);
1959         } while (time_after_eq(end_time, jiffies));
1960         snd_printk("AC'97 warm reset still in progress? [0x%x]\n", igetdword(chip, ICHREG(GLOB_CNT)));
1961         return -EIO;
1962 
1963       __ok:
1964         if (probing) {
1965                 /* wait for any codec ready status.
1966                  * Once it becomes ready it should remain ready
1967                  * as long as we do not disable the ac97 link.
1968                  */
1969                 end_time = jiffies + HZ;
1970                 do {
1971                         status = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
1972                         if (status)
1973                                 break;
1974                         do_delay(chip);
1975                 } while (time_after_eq(end_time, jiffies));
1976                 if (! status) {
1977                         /* no codec is found */
1978                         snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n", igetdword(chip, ICHREG(GLOB_STA)));
1979                         return -EIO;
1980                 }
1981 
1982                 if (chip->device_type == DEVICE_INTEL_ICH4)
1983                         /* ICH4 can have three codecs */
1984                         nstatus = ICH_PCR | ICH_SCR | ICH_TCR;
1985                 else
1986                         /* others up to two codecs */
1987                         nstatus = ICH_PCR | ICH_SCR;
1988 
1989                 /* wait for other codecs ready status. */
1990                 end_time = jiffies + HZ / 4;
1991                 while (status != nstatus && time_after_eq(end_time, jiffies)) {
1992                         do_delay(chip);
1993                         status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus;
1994                 }
1995 
1996         } else {
1997                 /* resume phase */
1998                 int i;
1999                 status = 0;
2000                 for (i = 0; i < 3; i++)
2001                         if (chip->ac97[i])
2002                                 status |= get_ich_codec_bit(chip, i);
2003                 /* wait until all the probed codecs are ready */
2004                 end_time = jiffies + HZ;
2005                 do {
2006                         nstatus = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
2007                         if (status == nstatus)
2008                                 break;
2009                         do_delay(chip);
2010                 } while (time_after_eq(end_time, jiffies));
2011         }
2012 
2013         if (chip->device_type == DEVICE_SIS) {
2014                 /* unmute the output on SIS7012 */
2015                 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2016         }
2017         if (chip->device_type == DEVICE_NFORCE) {
2018                 /* enable SPDIF interrupt */
2019                 unsigned int val;
2020                 pci_read_config_dword(chip->pci, 0x4c, &val);
2021                 val |= 0x1000000;
2022                 pci_write_config_dword(chip->pci, 0x4c, val);
2023         }
2024         return 0;
2025 }
2026 
2027 static int snd_intel8x0_ali_chip_init(intel8x0_t *chip, int probing)
2028 {
2029         u32 reg;
2030         int i = 0;
2031 
2032         reg = igetdword(chip, ICHREG(ALI_SCR));
2033         if ((reg & 2) == 0)     /* Cold required */
2034                 reg |= 2;
2035         else
2036                 reg |= 1;       /* Warm */
2037         reg &= ~0x80000000;     /* ACLink on */
2038         iputdword(chip, ICHREG(ALI_SCR), reg);
2039 
2040         for (i = 0; i < HZ / 2; i++) {
2041                 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2042                         goto __ok;
2043                 do_delay(chip);
2044         }
2045         snd_printk(KERN_ERR "AC'97 reset failed.\n");
2046         if (probing)
2047                 return -EIO;
2048 
2049  __ok:
2050         for (i = 0; i < HZ / 2; i++) {
2051                 reg = igetdword(chip, ICHREG(ALI_RTSR));
2052                 if (reg & 0x80) /* primary codec */
2053                         break;
2054                 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2055                 do_delay(chip);
2056         }
2057 
2058         do_ali_reset(chip);
2059         return 0;
2060 }
2061 
2062 static int snd_intel8x0_chip_init(intel8x0_t *chip, int probing)
2063 {
2064         unsigned int i;
2065         int err;
2066         
2067         if (chip->device_type != DEVICE_ALI) {
2068                 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2069                         return err;
2070                 iagetword(chip, 0);     /* clear semaphore flag */
2071         } else {
2072                 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2073                         return err;
2074         }
2075 
2076         /* disable interrupts */
2077         for (i = 0; i < chip->bdbars_count; i++)
2078                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2079         /* reset channels */
2080         for (i = 0; i < chip->bdbars_count; i++)
2081                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2082         /* initialize Buffer Descriptor Lists */
2083         for (i = 0; i < chip->bdbars_count; i++)
2084                 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr);
2085         return 0;
2086 }
2087 
2088 static int snd_intel8x0_free(intel8x0_t *chip)
2089 {
2090         unsigned int i;
2091 
2092         if (chip->irq < 0)
2093                 goto __hw_end;
2094         /* disable interrupts */
2095         for (i = 0; i < chip->bdbars_count; i++)
2096                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2097         /* reset channels */
2098         for (i = 0; i < chip->bdbars_count; i++)
2099                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2100         if (chip->device_type == DEVICE_NFORCE) {
2101                 /* stop the spdif interrupt */
2102                 unsigned int val;
2103                 pci_read_config_dword(chip->pci, 0x4c, &val);
2104                 val &= ~0x1000000;
2105                 pci_write_config_dword(chip->pci, 0x4c, val);
2106         }
2107         /* --- */
2108         synchronize_irq(chip->irq);
2109       __hw_end:
2110         if (chip->bdbars)
2111                 snd_free_pci_pages(chip->pci, chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2, chip->bdbars, chip->bdbars_addr);
2112         if (chip->remap_addr)
2113                 iounmap((void *) chip->remap_addr);
2114         if (chip->remap_bmaddr)
2115                 iounmap((void *) chip->remap_bmaddr);
2116         if (chip->res) {
2117                 release_resource(chip->res);
2118                 kfree_nocheck(chip->res);
2119         }
2120         if (chip->res_bm) {
2121                 release_resource(chip->res_bm);
2122                 kfree_nocheck(chip->res_bm);
2123         }
2124         if (chip->irq >= 0)
2125                 free_irq(chip->irq, (void *)chip);
2126         snd_magic_kfree(chip);
2127         return 0;
2128 }
2129 
2130 #ifdef CONFIG_PM
2131 /*
2132  * power management
2133  */
2134 static void intel8x0_suspend(intel8x0_t *chip)
2135 {
2136         snd_card_t *card = chip->card;
2137         int i;
2138 
2139         if (chip->in_suspend ||
2140             card->power_state == SNDRV_CTL_POWER_D3hot)
2141                 return;
2142 
2143         chip->in_suspend = 1;
2144         for (i = 0; i < chip->pcm_devs; i++)
2145                 snd_pcm_suspend_all(chip->pcm[i]);
2146         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2147 }
2148 
2149 static void intel8x0_resume(intel8x0_t *chip)
2150 {
2151         snd_card_t *card = chip->card;
2152         int i;
2153 
2154         if (! chip->in_suspend ||
2155             card->power_state == SNDRV_CTL_POWER_D0)
2156                 return;
2157 
2158         pci_enable_device(chip->pci);
2159         pci_set_master(chip->pci);
2160         snd_intel8x0_chip_init(chip, 0);
2161         for (i = 0; i < 3; i++)
2162                 if (chip->ac97[i])
2163                         snd_ac97_resume(chip->ac97[i]);
2164 
2165         chip->in_suspend = 0;
2166         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2167 }
2168 
2169 static int snd_intel8x0_suspend(struct pci_dev *dev, u32 state)
2170 {
2171         intel8x0_t *chip = snd_magic_cast(intel8x0_t, pci_get_drvdata(dev), return -ENXIO);
2172         intel8x0_suspend(chip);
2173         return 0;
2174 }
2175 static int snd_intel8x0_resume(struct pci_dev *dev)
2176 {
2177         intel8x0_t *chip = snd_magic_cast(intel8x0_t, pci_get_drvdata(dev), return -ENXIO);
2178         intel8x0_resume(chip);
2179         return 0;
2180 }
2181 
2182 /* callback */
2183 static int snd_intel8x0_set_power_state(snd_card_t *card, unsigned int power_state)
2184 {
2185         intel8x0_t *chip = snd_magic_cast(intel8x0_t, card->power_state_private_data, return -ENXIO);
2186         switch (power_state) {
2187         case SNDRV_CTL_POWER_D0:
2188         case SNDRV_CTL_POWER_D1:
2189         case SNDRV_CTL_POWER_D2:
2190                 intel8x0_resume(chip);
2191                 break;
2192         case SNDRV_CTL_POWER_D3hot:
2193         case SNDRV_CTL_POWER_D3cold:
2194                 intel8x0_suspend(chip);
2195                 break;
2196         default:
2197                 return -EINVAL;
2198         }
2199         return 0;
2200 }
2201 
2202 #endif /* CONFIG_PM */
2203 
2204 #define INTEL8X0_TESTBUF_SIZE   32768   /* enough large for one shot */
2205 
2206 static void __devinit intel8x0_measure_ac97_clock(intel8x0_t *chip)
2207 {
2208         snd_pcm_substream_t *subs;
2209         ichdev_t *ichdev;
2210         unsigned long port;
2211         unsigned long pos, t;
2212         unsigned long flags;
2213         struct timeval start_time, stop_time;
2214 
2215         if (chip->ac97[0]->clock != 48000)
2216                 return; /* specified in module option */
2217 
2218         subs = chip->pcm[0]->streams[0].substream;
2219         if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2220                 snd_printk("no playback buffer allocated - aborting measure ac97 clock\n");
2221                 return;
2222         }
2223         ichdev = &chip->ichd[ICHD_PCMOUT];
2224         ichdev->physbuf = subs->dma_buffer.addr;
2225         ichdev->size = chip->ichd[ICHD_PCMOUT].fragsize = INTEL8X0_TESTBUF_SIZE;
2226         ichdev->substream = NULL; /* don't process interrupts */
2227 
2228         /* set rate */
2229         if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2230                 snd_printk(KERN_ERR "cannot set ac97 rate: clock = %d\n", chip->ac97[0]->clock);
2231                 return;
2232         }
2233         snd_intel8x0_setup_periods(chip, ichdev);
2234         port = ichdev->reg_offset;
2235         spin_lock_irqsave(&chip->reg_lock, flags);
2236         /* trigger */
2237         if (chip->device_type != DEVICE_ALI)
2238                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2239         else {
2240                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2241                 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2242         }
2243         do_gettimeofday(&start_time);
2244         spin_unlock_irqrestore(&chip->reg_lock, flags);
2245 #if 0
2246         set_current_state(TASK_UNINTERRUPTIBLE);
2247         schedule_timeout(HZ / 20);
2248 #else
2249         /* FIXME: schedule() can take too long time and overlap the boundary.. */
2250         mdelay(50);
2251 #endif
2252         spin_lock_irqsave(&chip->reg_lock, flags);
2253         /* check the position */
2254         pos = ichdev->fragsize1;
2255         pos -= igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << chip->pcm_pos_shift;
2256         pos += ichdev->position;
2257         do_gettimeofday(&stop_time);
2258         /* stop */
2259         if (chip->device_type == DEVICE_ALI) {
2260                 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 8));
2261                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2262                 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2263                         ;
2264         } else {
2265                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2266                 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2267                         ;
2268         }
2269         iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2270         spin_unlock_irqrestore(&chip->reg_lock, flags);
2271 
2272         t = stop_time.tv_sec - start_time.tv_sec;
2273         t *= 1000000;
2274         if (stop_time.tv_usec < start_time.tv_usec)
2275                 t -= start_time.tv_usec - stop_time.tv_usec;
2276         else
2277                 t += stop_time.tv_usec - start_time.tv_usec;
2278         if (t == 0) {
2279                 snd_printk(KERN_ERR "?? calculation error..\n");
2280                 return;
2281         }
2282         pos = (pos / 4) * 1000;
2283         pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2284         if (pos < 40000 || pos >= 60000) 
2285                 /* abnormal value. hw problem? */
2286                 printk(KERN_INFO "intel8x0: measured clock %ld rejected\n", pos);
2287         else if (pos < 47500 || pos > 48500)
2288                 /* not 48000Hz, tuning the clock.. */
2289                 chip->ac97[0]->clock = (chip->ac97[0]->clock * 48000) / pos;
2290         printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97[0]->clock);
2291 }
2292 
2293 static void snd_intel8x0_proc_read(snd_info_entry_t * entry,
2294                                    snd_info_buffer_t * buffer)
2295 {
2296         intel8x0_t *chip = snd_magic_cast(intel8x0_t, entry->private_data, return);
2297         unsigned int tmp;
2298 
2299         snd_iprintf(buffer, "Intel8x0\n\n");
2300         if (chip->device_type == DEVICE_ALI)
2301                 return;
2302         tmp = igetdword(chip, ICHREG(GLOB_STA));
2303         snd_iprintf(buffer, "Global control        : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2304         snd_iprintf(buffer, "Global status         : 0x%08x\n", tmp);
2305         if (chip->device_type == DEVICE_INTEL_ICH4)
2306                 snd_iprintf(buffer, "SDM                   : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2307         snd_iprintf(buffer, "AC'97 codecs ready    :%s%s%s%s\n",
2308                         tmp & ICH_PCR ? " primary" : "",
2309                         tmp & ICH_SCR ? " secondary" : "",
2310                         tmp & ICH_TCR ? " tertiary" : "",
2311                         (tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : "");
2312         if (chip->device_type == DEVICE_INTEL_ICH4)
2313                 snd_iprintf(buffer, "AC'97 codecs SDIN     : %i %i %i\n",
2314                         chip->ac97_sdin[0],
2315                         chip->ac97_sdin[1],
2316                         chip->ac97_sdin[2]);
2317 }
2318 
2319 static void __devinit snd_intel8x0_proc_init(intel8x0_t * chip)
2320 {
2321         snd_info_entry_t *entry;
2322 
2323         if (! snd_card_proc_new(chip->card, "intel8x0", &entry))
2324                 snd_info_set_text_ops(entry, chip, snd_intel8x0_proc_read);
2325 }
2326 
2327 static int snd_intel8x0_dev_free(snd_device_t *device)
2328 {
2329         intel8x0_t *chip = snd_magic_cast(intel8x0_t, device->device_data, return -ENXIO);
2330         return snd_intel8x0_free(chip);
2331 }
2332 
2333 struct ich_reg_info {
2334         unsigned int int_sta_mask;
2335         unsigned int offset;
2336 };
2337 
2338 static int __devinit snd_intel8x0_create(snd_card_t * card,
2339                                          struct pci_dev *pci,
2340                                          unsigned long device_type,
2341                                          intel8x0_t ** r_intel8x0)
2342 {
2343         intel8x0_t *chip;
2344         int err;
2345         unsigned int i;
2346         unsigned int int_sta_masks;
2347         ichdev_t *ichdev;
2348         static snd_device_ops_t ops = {
2349                 .dev_free =     snd_intel8x0_dev_free,
2350         };
2351 
2352         static unsigned int bdbars[] = {
2353                 3, /* DEVICE_INTEL */
2354                 6, /* DEVICE_INTEL_ICH4 */
2355                 3, /* DEVICE_SIS */
2356                 6, /* DEVICE_ALI */
2357                 4, /* DEVICE_NFORCE */
2358         };
2359         static struct ich_reg_info intel_regs[6] = {
2360                 { ICH_PIINT, 0 },
2361                 { ICH_POINT, 0x10 },
2362                 { ICH_MCINT, 0x20 },
2363                 { ICH_M2INT, 0x40 },
2364                 { ICH_P2INT, 0x50 },
2365                 { ICH_SPINT, 0x60 },
2366         };
2367         static struct ich_reg_info nforce_regs[4] = {
2368                 { ICH_PIINT, 0 },
2369                 { ICH_POINT, 0x10 },
2370                 { ICH_MCINT, 0x20 },
2371                 { ICH_NVSPINT, 0x70 },
2372         };
2373         static struct ich_reg_info ali_regs[6] = {
2374                 { ALI_INT_PCMIN, 0x40 },
2375                 { ALI_INT_PCMOUT, 0x50 },
2376                 { ALI_INT_MICIN, 0x60 },
2377                 { ALI_INT_CODECSPDIFOUT, 0x70 },
2378                 { ALI_INT_SPDIFIN, 0xa0 },
2379                 { ALI_INT_SPDIFOUT, 0xb0 },
2380         };
2381         struct ich_reg_info *tbl;
2382 
2383         *r_intel8x0 = NULL;
2384 
2385         if ((err = pci_enable_device(pci)) < 0)
2386                 return err;
2387 
2388         chip = snd_magic_kcalloc(intel8x0_t, 0, GFP_KERNEL);
2389         if (chip == NULL)
2390                 return -ENOMEM;
2391         spin_lock_init(&chip->reg_lock);
2392         spin_lock_init(&chip->ac97_lock);
2393         chip->device_type = device_type;
2394         chip->card = card;
2395         chip->pci = pci;
2396         chip->irq = -1;
2397         snd_intel8x0_proc_init(chip);
2398         sprintf(chip->ac97_name, "%s - AC'97", card->shortname);
2399         sprintf(chip->ctrl_name, "%s - Controller", card->shortname);
2400         if (device_type == DEVICE_ALI) {
2401                 /* ALI5455 has no ac97 region */
2402                 chip->bmaddr = pci_resource_start(pci, 0);
2403                 if ((chip->res_bm = request_region(chip->bmaddr, 256, chip->ctrl_name)) == NULL) {
2404                         snd_printk("unable to grab ports 0x%lx-0x%lx\n", chip->bmaddr, chip->bmaddr + 64 - 1);
2405                         snd_intel8x0_free(chip);
2406                         return -EBUSY;
2407                 }
2408                 goto port_inited;
2409         }
2410 
2411         if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) {      /* ICH4 and Nforce */
2412                 chip->mmio = 1;
2413                 chip->addr = pci_resource_start(pci, 2);
2414                 if ((chip->res = request_mem_region(chip->addr, 512, chip->ac97_name)) == NULL) {
2415                         snd_printk("unable to grab I/O memory 0x%lx-0x%lx\n", chip->addr, chip->addr + 512 - 1);
2416                         snd_intel8x0_free(chip);
2417                         return -EBUSY;
2418                 }
2419                 chip->remap_addr = (unsigned long) ioremap_nocache(chip->addr, 512);
2420                 if (chip->remap_addr == 0) {
2421                         snd_printk("AC'97 space ioremap problem\n");
2422                         snd_intel8x0_free(chip);
2423                         return -EIO;
2424                 }
2425         } else {
2426                 chip->addr = pci_resource_start(pci, 0);
2427                 if ((chip->res = request_region(chip->addr, 256, chip->ac97_name)) == NULL) {
2428                         snd_printk("unable to grab ports 0x%lx-0x%lx\n", chip->addr, chip->addr + 256 - 1);
2429                         snd_intel8x0_free(chip);
2430                         return -EBUSY;
2431                 }
2432         }
2433         if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) {      /* ICH4 */
2434                 chip->bm_mmio = 1;
2435                 chip->bmaddr = pci_resource_start(pci, 3);
2436                 if ((chip->res_bm = request_mem_region(chip->bmaddr, 256, chip->ctrl_name)) == NULL) {
2437                         snd_printk("unable to grab I/O memory 0x%lx-0x%lx\n", chip->bmaddr, chip->bmaddr + 512 - 1);
2438                         snd_intel8x0_free(chip);
2439                         return -EBUSY;
2440                 }
2441                 chip->remap_bmaddr = (unsigned long) ioremap_nocache(chip->bmaddr, 256);
2442                 if (chip->remap_bmaddr == 0) {
2443                         snd_printk("Controller space ioremap problem\n");
2444                         snd_intel8x0_free(chip);
2445                         return -EIO;
2446                 }
2447         } else {
2448                 chip->bmaddr = pci_resource_start(pci, 1);
2449                 if ((chip->res_bm = request_region(chip->bmaddr, 64, chip->ctrl_name)) == NULL) {
2450                         snd_printk("unable to grab ports 0x%lx-0x%lx\n", chip->bmaddr, chip->bmaddr + 64 - 1);
2451                         snd_intel8x0_free(chip);
2452                         return -EBUSY;
2453                 }
2454         }
2455 
2456  port_inited:
2457         if (request_irq(pci->irq, snd_intel8x0_interrupt, SA_INTERRUPT|SA_SHIRQ, card->shortname, (void *)chip)) {
2458                 snd_printk("unable to grab IRQ %d\n", pci->irq);
2459                 snd_intel8x0_free(chip);
2460                 return -EBUSY;
2461         }
2462         chip->irq = pci->irq;
2463         pci_set_master(pci);
2464         synchronize_irq(chip->irq);
2465 
2466         chip->bdbars_count = bdbars[device_type];
2467 
2468         /* initialize offsets */
2469         switch (device_type) {
2470         case DEVICE_NFORCE:
2471                 tbl = nforce_regs;
2472                 break;
2473         case DEVICE_ALI:
2474                 tbl = ali_regs;
2475                 break;
2476         default:
2477                 tbl = intel_regs;
2478                 break;
2479         }
2480         for (i = 0; i < chip->bdbars_count; i++) {
2481                 ichdev = &chip->ichd[i];
2482                 ichdev->ichd = i;
2483                 ichdev->reg_offset = tbl[i].offset;
2484                 ichdev->int_sta_mask = tbl[i].int_sta_mask;
2485                 if (device_type == DEVICE_SIS) {
2486                         /* SiS 7012 swaps the registers */
2487                         ichdev->roff_sr = ICH_REG_OFF_PICB;
2488                         ichdev->roff_picb = ICH_REG_OFF_SR;
2489                 } else {
2490                         ichdev->roff_sr = ICH_REG_OFF_SR;
2491                         ichdev->roff_picb = ICH_REG_OFF_PICB;
2492                 }
2493                 if (device_type == DEVICE_ALI)
2494                         ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
2495         }
2496         /* SIS7012 handles the pcm data in bytes, others are in words */
2497         chip->pcm_pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
2498 
2499         /* allocate buffer descriptor lists */
2500         /* the start of each lists must be aligned to 8 bytes */
2501         chip->bdbars = (u32 *)snd_malloc_pci_pages(pci, chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2, &chip->bdbars_addr);
2502         if (chip->bdbars == NULL) {
2503                 snd_intel8x0_free(chip);
2504                 return -ENOMEM;
2505         }
2506         /* tables must be aligned to 8 bytes here, but the kernel pages
2507            are much bigger, so we don't care (on i386) */
2508         int_sta_masks = 0;
2509         for (i = 0; i < chip->bdbars_count; i++) {
2510                 ichdev = &chip->ichd[i];
2511                 ichdev->bdbar = chip->bdbars + (i * ICH_MAX_FRAGS * 2);
2512                 ichdev->bdbar_addr = chip->bdbars_addr + (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
2513                 int_sta_masks |= ichdev->int_sta_mask;
2514         }
2515         chip->int_sta_reg = device_type == DEVICE_ALI ? ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
2516         chip->int_sta_mask = int_sta_masks;
2517 
2518         if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
2519                 snd_intel8x0_free(chip);
2520                 return err;
2521         }
2522 
2523 #ifdef CONFIG_PM
2524         card->set_power_state = snd_intel8x0_set_power_state;
2525         card->power_state_private_data = chip;
2526 #endif
2527 
2528         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2529                 snd_intel8x0_free(chip);
2530                 return err;
2531         }
2532 
2533         *r_intel8x0 = chip;
2534         return 0;
2535 }
2536 
2537 static struct shortname_table {
2538         unsigned int id;
2539         const char *s;
2540 } shortnames[] __devinitdata = {
2541         { PCI_DEVICE_ID_INTEL_82801, "Intel 82801AA-ICH" },
2542         { PCI_DEVICE_ID_INTEL_82901, "Intel 82901AB-ICH0" },
2543         { PCI_DEVICE_ID_INTEL_82801BA, "Intel 82801BA-ICH2" },
2544         { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
2545         { PCI_DEVICE_ID_INTEL_ICH3, "Intel 82801CA-ICH3" },
2546         { PCI_DEVICE_ID_INTEL_ICH4, "Intel 82801DB-ICH4" },
2547         { PCI_DEVICE_ID_INTEL_ICH5, "Intel ICH5" },
2548         { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
2549         { PCI_DEVICE_ID_NVIDIA_MCP_AUDIO, "NVidia nForce" },
2550         { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
2551         { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
2552         { 0x746d, "AMD AMD8111" },
2553         { 0x7445, "AMD AMD768" },
2554         { 0x5455, "ALi M5455" },
2555         { 0, 0 },
2556 };
2557 
2558 static int __devinit snd_intel8x0_probe(struct pci_dev *pci,
2559                                         const struct pci_device_id *pci_id)
2560 {
2561         static int dev;
2562         snd_card_t *card;
2563         intel8x0_t *chip;
2564         int err;
2565         struct shortname_table *name;
2566 
2567         if (dev >= SNDRV_CARDS)
2568                 return -ENODEV;
2569         if (!enable[dev]) {
2570                 dev++;
2571                 return -ENOENT;
2572         }
2573 
2574         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2575         if (card == NULL)
2576                 return -ENOMEM;
2577 
2578         switch (pci_id->driver_data) {
2579         case DEVICE_NFORCE:
2580                 strcpy(card->driver, "NFORCE");
2581                 break;
2582         default:
2583                 strcpy(card->driver, "ICH");
2584                 break;
2585         }
2586 
2587         strcpy(card->shortname, "Intel ICH");
2588         for (name = shortnames; name->id; name++) {
2589                 if (pci->device == name->id) {
2590                         strcpy(card->shortname, name->s);
2591                         break;
2592                 }
2593         }
2594 
2595         if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data, &chip)) < 0) {
2596                 snd_card_free(card);
2597                 return err;
2598         }
2599 
2600         if ((err = snd_intel8x0_mixer(chip, ac97_clock[dev])) < 0) {
2601                 snd_card_free(card);
2602                 return err;
2603         }
2604         if ((err = snd_intel8x0_pcm(chip)) < 0) {
2605                 snd_card_free(card);
2606                 return err;
2607         }
2608         
2609         if (mpu_port[dev] == 0x300 || mpu_port[dev] == 0x330) {
2610                 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_INTEL8X0,
2611                                                mpu_port[dev], 0,
2612                                                -1, 0, &chip->rmidi)) < 0) {
2613                         printk(KERN_ERR "intel8x0: no UART401 device at 0x%x, skipping.\n", mpu_port[dev]);
2614                         mpu_port[dev] = 0;
2615                 }
2616         } else
2617                 mpu_port[dev] = 0;
2618 
2619         sprintf(card->longname, "%s at 0x%lx, irq %i",
2620                 card->shortname, chip->addr, chip->irq);
2621 
2622         if (! ac97_clock[dev])
2623                 intel8x0_measure_ac97_clock(chip);
2624 
2625         if ((err = snd_card_register(card)) < 0) {
2626                 snd_card_free(card);
2627                 return err;
2628         }
2629         pci_set_drvdata(pci, chip);
2630         dev++;
2631         return 0;
2632 }
2633 
2634 static void __devexit snd_intel8x0_remove(struct pci_dev *pci)
2635 {
2636         intel8x0_t *chip = snd_magic_cast(intel8x0_t, pci_get_drvdata(pci), return);
2637         if (chip)
2638                 snd_card_free(chip->card);
2639         pci_set_drvdata(pci, NULL);
2640 }
2641 
2642 static struct pci_driver driver = {
2643         .name = "Intel ICH",
2644         .id_table = snd_intel8x0_ids,
2645         .probe = snd_intel8x0_probe,
2646         .remove = __devexit_p(snd_intel8x0_remove),
2647 #ifdef CONFIG_PM
2648         .suspend = snd_intel8x0_suspend,
2649         .resume = snd_intel8x0_resume,
2650 #endif
2651 };
2652 
2653 
2654 #if defined(SUPPORT_JOYSTICK) || defined(SUPPORT_MIDI)
2655 /*
2656  * initialize joystick/midi addresses
2657  */
2658 
2659 static int __devinit snd_intel8x0_joystick_probe(struct pci_dev *pci,
2660                                                  const struct pci_device_id *id)
2661 {
2662         static int dev;
2663         if (dev >= SNDRV_CARDS)
2664                 return -ENODEV;
2665         if (!enable[dev]) {
2666                 dev++;
2667                 return -ENOENT;
2668         }
2669 
2670         if (joystick_port[dev] > 0 || mpu_port[dev] > 0) {
2671                 u16 val;
2672                 pci_read_config_word(pci, 0xe6, &val);
2673                 if (joystick_port[dev] > 0)
2674                         val |= 0x100;
2675                 if (mpu_port[dev] == 0x300 || mpu_port[dev] == 0x330)
2676                         val |= 0x20;
2677                 pci_write_config_word(pci, 0xe6, val | 0x100);
2678 
2679                 if (mpu_port[dev] == 0x300 || mpu_port[dev] == 0x330) {
2680                         u8 b;
2681                         pci_read_config_byte(pci, 0xe2, &b);
2682                         if (mpu_port[dev] == 0x300)
2683                                 b |= 0x08;
2684                         else
2685                                 b &= ~0x08;
2686                         pci_write_config_byte(pci, 0xe2, b);
2687                 }
2688         }
2689         return 0;
2690 }
2691 
2692 static struct pci_device_id snd_intel8x0_joystick_ids[] = {
2693         { 0x8086, 0x2410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },    /* 82801AA */
2694         { 0x8086, 0x2420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },    /* 82901AB */
2695         { 0x8086, 0x2440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ICH2 */
2696         { 0x8086, 0x244c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ICH2M */
2697         { 0x8086, 0x248c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },    /* ICH3 */
2698         // { 0x8086, 0x7195, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* 440MX */
2699         // { 0x1039, 0x7012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* SI7012 */
2700         { 0x10de, 0x01b2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },    /* NFORCE */
2701         { 0x10de, 0x006b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },    /* NFORCE2 */
2702         { 0x10de, 0x00db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },    /* NFORCE3 */
2703         { 0, }
2704 };
2705 
2706 static struct pci_driver joystick_driver = {
2707         .name = "Intel ICH Joystick",
2708         .id_table = snd_intel8x0_joystick_ids,
2709         .probe = snd_intel8x0_joystick_probe,
2710 };
2711 
2712 static int have_joystick;
2713 #endif
2714 
2715 static int __init alsa_card_intel8x0_init(void)
2716 {
2717         int err;
2718 
2719         if ((err = pci_module_init(&driver)) < 0) {
2720 #ifdef MODULE
2721                 printk(KERN_ERR "Intel ICH soundcard not found or device busy\n");
2722 #endif
2723                 return err;
2724         }
2725 #if defined(SUPPORT_JOYSTICK) || defined(SUPPORT_MIDI)
2726         if (pci_module_init(&joystick_driver) < 0) {
2727                 snd_printdd(KERN_INFO "no joystick found\n");
2728                 have_joystick = 0;
2729         } else {
2730                 snd_printdd(KERN_INFO "joystick(s) found\n");
2731                 have_joystick = 1;
2732         }
2733 #endif
2734         return 0;
2735 
2736 }
2737 
2738 static void __exit alsa_card_intel8x0_exit(void)
2739 {
2740         pci_unregister_driver(&driver);
2741 #if defined(SUPPORT_JOYSTICK) || defined(SUPPORT_MIDI)
2742         if (have_joystick)
2743                 pci_unregister_driver(&joystick_driver);
2744 #endif
2745 }
2746 
2747 module_init(alsa_card_intel8x0_init)
2748 module_exit(alsa_card_intel8x0_exit)
2749 
2750 #ifndef MODULE
2751 
2752 /* format is: snd-intel8x0=enable,index,id,ac97_clock */
2753 
2754 static int __init alsa_card_intel8x0_setup(char *str)
2755 {
2756         static unsigned __initdata nr_dev = 0;
2757 
2758         if (nr_dev >= SNDRV_CARDS)
2759                 return 0;
2760         (void)(get_option(&str,&enable[nr_dev]) == 2 &&
2761                get_option(&str,&index[nr_dev]) == 2 &&
2762                get_id(&str,&id[nr_dev]) == 2 &&
2763                get_option(&str,&ac97_clock[nr_dev]) == 2);
2764         nr_dev++;
2765         return 1;
2766 }
2767 
2768 __setup("snd-intel8x0=", alsa_card_intel8x0_setup);
2769 
2770 #endif /* ifndef MODULE */
2771 

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