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TOMOYO Linux Cross Reference
Linux/sound/pci/intel8x0.c

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  1 /*
  2  *   ALSA driver for Intel ICH (i8x0) chipsets
  3  *
  4  *      Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
  5  *
  6  *
  7  *   This code also contains alpha support for SiS 735 chipsets provided
  8  *   by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
  9  *   for SiS735, so the code is not fully functional.
 10  *
 11  *
 12  *   This program is free software; you can redistribute it and/or modify
 13  *   it under the terms of the GNU General Public License as published by
 14  *   the Free Software Foundation; either version 2 of the License, or
 15  *   (at your option) any later version.
 16  *
 17  *   This program is distributed in the hope that it will be useful,
 18  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 19  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 20  *   GNU General Public License for more details.
 21  *
 22  *   You should have received a copy of the GNU General Public License
 23  *   along with this program; if not, write to the Free Software
 24  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 25 
 26  *
 27  */      
 28 
 29 #include <linux/io.h>
 30 #include <linux/delay.h>
 31 #include <linux/interrupt.h>
 32 #include <linux/init.h>
 33 #include <linux/pci.h>
 34 #include <linux/slab.h>
 35 #include <linux/module.h>
 36 #include <sound/core.h>
 37 #include <sound/pcm.h>
 38 #include <sound/ac97_codec.h>
 39 #include <sound/info.h>
 40 #include <sound/initval.h>
 41 /* for 440MX workaround */
 42 #include <asm/pgtable.h>
 43 #ifdef CONFIG_X86
 44 #include <asm/set_memory.h>
 45 #endif
 46 
 47 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
 48 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
 49 MODULE_LICENSE("GPL");
 50 MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
 51                 "{Intel,82901AB-ICH0},"
 52                 "{Intel,82801BA-ICH2},"
 53                 "{Intel,82801CA-ICH3},"
 54                 "{Intel,82801DB-ICH4},"
 55                 "{Intel,ICH5},"
 56                 "{Intel,ICH6},"
 57                 "{Intel,ICH7},"
 58                 "{Intel,6300ESB},"
 59                 "{Intel,ESB2},"
 60                 "{Intel,MX440},"
 61                 "{SiS,SI7012},"
 62                 "{NVidia,nForce Audio},"
 63                 "{NVidia,nForce2 Audio},"
 64                 "{NVidia,nForce3 Audio},"
 65                 "{NVidia,MCP04},"
 66                 "{NVidia,MCP501},"
 67                 "{NVidia,CK804},"
 68                 "{NVidia,CK8},"
 69                 "{NVidia,CK8S},"
 70                 "{AMD,AMD768},"
 71                 "{AMD,AMD8111},"
 72                 "{ALI,M5455}}");
 73 
 74 static int index = SNDRV_DEFAULT_IDX1;  /* Index 0-MAX */
 75 static char *id = SNDRV_DEFAULT_STR1;   /* ID for this card */
 76 static int ac97_clock;
 77 static char *ac97_quirk;
 78 static bool buggy_semaphore;
 79 static int buggy_irq = -1; /* auto-check */
 80 static bool xbox;
 81 static int spdif_aclink = -1;
 82 static int inside_vm = -1;
 83 
 84 module_param(index, int, 0444);
 85 MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
 86 module_param(id, charp, 0444);
 87 MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
 88 module_param(ac97_clock, int, 0444);
 89 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = whitelist + auto-detect, 1 = force autodetect).");
 90 module_param(ac97_quirk, charp, 0444);
 91 MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
 92 module_param(buggy_semaphore, bool, 0444);
 93 MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores.");
 94 module_param(buggy_irq, bint, 0444);
 95 MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
 96 module_param(xbox, bool, 0444);
 97 MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
 98 module_param(spdif_aclink, int, 0444);
 99 MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
100 module_param(inside_vm, bint, 0444);
101 MODULE_PARM_DESC(inside_vm, "KVM/Parallels optimization.");
102 
103 /* just for backward compatibility */
104 static bool enable;
105 module_param(enable, bool, 0444);
106 static int joystick;
107 module_param(joystick, int, 0444);
108 
109 /*
110  *  Direct registers
111  */
112 enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
113 
114 #define ICHREG(x) ICH_REG_##x
115 
116 #define DEFINE_REGSET(name,base) \
117 enum { \
118         ICH_REG_##name##_BDBAR  = base + 0x0,   /* dword - buffer descriptor list base address */ \
119         ICH_REG_##name##_CIV    = base + 0x04,  /* byte - current index value */ \
120         ICH_REG_##name##_LVI    = base + 0x05,  /* byte - last valid index */ \
121         ICH_REG_##name##_SR     = base + 0x06,  /* byte - status register */ \
122         ICH_REG_##name##_PICB   = base + 0x08,  /* word - position in current buffer */ \
123         ICH_REG_##name##_PIV    = base + 0x0a,  /* byte - prefetched index value */ \
124         ICH_REG_##name##_CR     = base + 0x0b,  /* byte - control register */ \
125 };
126 
127 /* busmaster blocks */
128 DEFINE_REGSET(OFF, 0);          /* offset */
129 DEFINE_REGSET(PI, 0x00);        /* PCM in */
130 DEFINE_REGSET(PO, 0x10);        /* PCM out */
131 DEFINE_REGSET(MC, 0x20);        /* Mic in */
132 
133 /* ICH4 busmaster blocks */
134 DEFINE_REGSET(MC2, 0x40);       /* Mic in 2 */
135 DEFINE_REGSET(PI2, 0x50);       /* PCM in 2 */
136 DEFINE_REGSET(SP, 0x60);        /* SPDIF out */
137 
138 /* values for each busmaster block */
139 
140 /* LVI */
141 #define ICH_REG_LVI_MASK                0x1f
142 
143 /* SR */
144 #define ICH_FIFOE                       0x10    /* FIFO error */
145 #define ICH_BCIS                        0x08    /* buffer completion interrupt status */
146 #define ICH_LVBCI                       0x04    /* last valid buffer completion interrupt */
147 #define ICH_CELV                        0x02    /* current equals last valid */
148 #define ICH_DCH                         0x01    /* DMA controller halted */
149 
150 /* PIV */
151 #define ICH_REG_PIV_MASK                0x1f    /* mask */
152 
153 /* CR */
154 #define ICH_IOCE                        0x10    /* interrupt on completion enable */
155 #define ICH_FEIE                        0x08    /* fifo error interrupt enable */
156 #define ICH_LVBIE                       0x04    /* last valid buffer interrupt enable */
157 #define ICH_RESETREGS                   0x02    /* reset busmaster registers */
158 #define ICH_STARTBM                     0x01    /* start busmaster operation */
159 
160 
161 /* global block */
162 #define ICH_REG_GLOB_CNT                0x2c    /* dword - global control */
163 #define   ICH_PCM_SPDIF_MASK    0xc0000000      /* s/pdif pcm slot mask (ICH4) */
164 #define   ICH_PCM_SPDIF_NONE    0x00000000      /* reserved - undefined */
165 #define   ICH_PCM_SPDIF_78      0x40000000      /* s/pdif pcm on slots 7&8 */
166 #define   ICH_PCM_SPDIF_69      0x80000000      /* s/pdif pcm on slots 6&9 */
167 #define   ICH_PCM_SPDIF_1011    0xc0000000      /* s/pdif pcm on slots 10&11 */
168 #define   ICH_PCM_20BIT         0x00400000      /* 20-bit samples (ICH4) */
169 #define   ICH_PCM_246_MASK      0x00300000      /* chan mask (not all chips) */
170 #define   ICH_PCM_8             0x00300000      /* 8 channels (not all chips) */
171 #define   ICH_PCM_6             0x00200000      /* 6 channels (not all chips) */
172 #define   ICH_PCM_4             0x00100000      /* 4 channels (not all chips) */
173 #define   ICH_PCM_2             0x00000000      /* 2 channels (stereo) */
174 #define   ICH_SIS_PCM_246_MASK  0x000000c0      /* 6 channels (SIS7012) */
175 #define   ICH_SIS_PCM_6         0x00000080      /* 6 channels (SIS7012) */
176 #define   ICH_SIS_PCM_4         0x00000040      /* 4 channels (SIS7012) */
177 #define   ICH_SIS_PCM_2         0x00000000      /* 2 channels (SIS7012) */
178 #define   ICH_TRIE              0x00000040      /* tertiary resume interrupt enable */
179 #define   ICH_SRIE              0x00000020      /* secondary resume interrupt enable */
180 #define   ICH_PRIE              0x00000010      /* primary resume interrupt enable */
181 #define   ICH_ACLINK            0x00000008      /* AClink shut off */
182 #define   ICH_AC97WARM          0x00000004      /* AC'97 warm reset */
183 #define   ICH_AC97COLD          0x00000002      /* AC'97 cold reset */
184 #define   ICH_GIE               0x00000001      /* GPI interrupt enable */
185 #define ICH_REG_GLOB_STA                0x30    /* dword - global status */
186 #define   ICH_TRI               0x20000000      /* ICH4: tertiary (AC_SDIN2) resume interrupt */
187 #define   ICH_TCR               0x10000000      /* ICH4: tertiary (AC_SDIN2) codec ready */
188 #define   ICH_BCS               0x08000000      /* ICH4: bit clock stopped */
189 #define   ICH_SPINT             0x04000000      /* ICH4: S/PDIF interrupt */
190 #define   ICH_P2INT             0x02000000      /* ICH4: PCM2-In interrupt */
191 #define   ICH_M2INT             0x01000000      /* ICH4: Mic2-In interrupt */
192 #define   ICH_SAMPLE_CAP        0x00c00000      /* ICH4: sample capability bits (RO) */
193 #define   ICH_SAMPLE_16_20      0x00400000      /* ICH4: 16- and 20-bit samples */
194 #define   ICH_MULTICHAN_CAP     0x00300000      /* ICH4: multi-channel capability bits (RO) */
195 #define   ICH_SIS_TRI           0x00080000      /* SIS: tertiary resume irq */
196 #define   ICH_SIS_TCR           0x00040000      /* SIS: tertiary codec ready */
197 #define   ICH_MD3               0x00020000      /* modem power down semaphore */
198 #define   ICH_AD3               0x00010000      /* audio power down semaphore */
199 #define   ICH_RCS               0x00008000      /* read completion status */
200 #define   ICH_BIT3              0x00004000      /* bit 3 slot 12 */
201 #define   ICH_BIT2              0x00002000      /* bit 2 slot 12 */
202 #define   ICH_BIT1              0x00001000      /* bit 1 slot 12 */
203 #define   ICH_SRI               0x00000800      /* secondary (AC_SDIN1) resume interrupt */
204 #define   ICH_PRI               0x00000400      /* primary (AC_SDIN0) resume interrupt */
205 #define   ICH_SCR               0x00000200      /* secondary (AC_SDIN1) codec ready */
206 #define   ICH_PCR               0x00000100      /* primary (AC_SDIN0) codec ready */
207 #define   ICH_MCINT             0x00000080      /* MIC capture interrupt */
208 #define   ICH_POINT             0x00000040      /* playback interrupt */
209 #define   ICH_PIINT             0x00000020      /* capture interrupt */
210 #define   ICH_NVSPINT           0x00000010      /* nforce spdif interrupt */
211 #define   ICH_MOINT             0x00000004      /* modem playback interrupt */
212 #define   ICH_MIINT             0x00000002      /* modem capture interrupt */
213 #define   ICH_GSCI              0x00000001      /* GPI status change interrupt */
214 #define ICH_REG_ACC_SEMA                0x34    /* byte - codec write semaphore */
215 #define   ICH_CAS               0x01            /* codec access semaphore */
216 #define ICH_REG_SDM             0x80
217 #define   ICH_DI2L_MASK         0x000000c0      /* PCM In 2, Mic In 2 data in line */
218 #define   ICH_DI2L_SHIFT        6
219 #define   ICH_DI1L_MASK         0x00000030      /* PCM In 1, Mic In 1 data in line */
220 #define   ICH_DI1L_SHIFT        4
221 #define   ICH_SE                0x00000008      /* steer enable */
222 #define   ICH_LDI_MASK          0x00000003      /* last codec read data input */
223 
224 #define ICH_MAX_FRAGS           32              /* max hw frags */
225 
226 
227 /*
228  * registers for Ali5455
229  */
230 
231 /* ALi 5455 busmaster blocks */
232 DEFINE_REGSET(AL_PI, 0x40);     /* ALi PCM in */
233 DEFINE_REGSET(AL_PO, 0x50);     /* Ali PCM out */
234 DEFINE_REGSET(AL_MC, 0x60);     /* Ali Mic in */
235 DEFINE_REGSET(AL_CDC_SPO, 0x70);        /* Ali Codec SPDIF out */
236 DEFINE_REGSET(AL_CENTER, 0x80);         /* Ali center out */
237 DEFINE_REGSET(AL_LFE, 0x90);            /* Ali center out */
238 DEFINE_REGSET(AL_CLR_SPI, 0xa0);        /* Ali Controller SPDIF in */
239 DEFINE_REGSET(AL_CLR_SPO, 0xb0);        /* Ali Controller SPDIF out */
240 DEFINE_REGSET(AL_I2S, 0xc0);    /* Ali I2S in */
241 DEFINE_REGSET(AL_PI2, 0xd0);    /* Ali PCM2 in */
242 DEFINE_REGSET(AL_MC2, 0xe0);    /* Ali Mic2 in */
243 
244 enum {
245         ICH_REG_ALI_SCR = 0x00,         /* System Control Register */
246         ICH_REG_ALI_SSR = 0x04,         /* System Status Register  */
247         ICH_REG_ALI_DMACR = 0x08,       /* DMA Control Register    */
248         ICH_REG_ALI_FIFOCR1 = 0x0c,     /* FIFO Control Register 1  */
249         ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
250         ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
251         ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt  Status Register */
252         ICH_REG_ALI_FIFOCR2 = 0x1c,     /* FIFO Control Register 2   */
253         ICH_REG_ALI_CPR = 0x20,         /* Command Port Register     */
254         ICH_REG_ALI_CPR_ADDR = 0x22,    /* ac97 addr write */
255         ICH_REG_ALI_SPR = 0x24,         /* Status Port Register      */
256         ICH_REG_ALI_SPR_ADDR = 0x26,    /* ac97 addr read */
257         ICH_REG_ALI_FIFOCR3 = 0x2c,     /* FIFO Control Register 3  */
258         ICH_REG_ALI_TTSR = 0x30,        /* Transmit Tag Slot Register */
259         ICH_REG_ALI_RTSR = 0x34,        /* Receive Tag Slot  Register */
260         ICH_REG_ALI_CSPSR = 0x38,       /* Command/Status Port Status Register */
261         ICH_REG_ALI_CAS = 0x3c,         /* Codec Write Semaphore Register */
262         ICH_REG_ALI_HWVOL = 0xf0,       /* hardware volume control/status */
263         ICH_REG_ALI_I2SCR = 0xf4,       /* I2S control/status */
264         ICH_REG_ALI_SPDIFCSR = 0xf8,    /* spdif channel status register  */
265         ICH_REG_ALI_SPDIFICS = 0xfc,    /* spdif interface control/status  */
266 };
267 
268 #define ALI_CAS_SEM_BUSY        0x80000000
269 #define ALI_CPR_ADDR_SECONDARY  0x100
270 #define ALI_CPR_ADDR_READ       0x80
271 #define ALI_CSPSR_CODEC_READY   0x08
272 #define ALI_CSPSR_READ_OK       0x02
273 #define ALI_CSPSR_WRITE_OK      0x01
274 
275 /* interrupts for the whole chip by interrupt status register finish */
276  
277 #define ALI_INT_MICIN2          (1<<26)
278 #define ALI_INT_PCMIN2          (1<<25)
279 #define ALI_INT_I2SIN           (1<<24)
280 #define ALI_INT_SPDIFOUT        (1<<23) /* controller spdif out INTERRUPT */
281 #define ALI_INT_SPDIFIN         (1<<22)
282 #define ALI_INT_LFEOUT          (1<<21)
283 #define ALI_INT_CENTEROUT       (1<<20)
284 #define ALI_INT_CODECSPDIFOUT   (1<<19)
285 #define ALI_INT_MICIN           (1<<18)
286 #define ALI_INT_PCMOUT          (1<<17)
287 #define ALI_INT_PCMIN           (1<<16)
288 #define ALI_INT_CPRAIS          (1<<7)  /* command port available */
289 #define ALI_INT_SPRAIS          (1<<5)  /* status port available */
290 #define ALI_INT_GPIO            (1<<1)
291 #define ALI_INT_MASK            (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\
292                                  ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
293 
294 #define ICH_ALI_SC_RESET        (1<<31) /* master reset */
295 #define ICH_ALI_SC_AC97_DBL     (1<<30)
296 #define ICH_ALI_SC_CODEC_SPDF   (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
297 #define ICH_ALI_SC_IN_BITS      (3<<18)
298 #define ICH_ALI_SC_OUT_BITS     (3<<16)
299 #define ICH_ALI_SC_6CH_CFG      (3<<14)
300 #define ICH_ALI_SC_PCM_4        (1<<8)
301 #define ICH_ALI_SC_PCM_6        (2<<8)
302 #define ICH_ALI_SC_PCM_246_MASK (3<<8)
303 
304 #define ICH_ALI_SS_SEC_ID       (3<<5)
305 #define ICH_ALI_SS_PRI_ID       (3<<3)
306 
307 #define ICH_ALI_IF_AC97SP       (1<<21)
308 #define ICH_ALI_IF_MC           (1<<20)
309 #define ICH_ALI_IF_PI           (1<<19)
310 #define ICH_ALI_IF_MC2          (1<<18)
311 #define ICH_ALI_IF_PI2          (1<<17)
312 #define ICH_ALI_IF_LINE_SRC     (1<<15) /* 0/1 = slot 3/6 */
313 #define ICH_ALI_IF_MIC_SRC      (1<<14) /* 0/1 = slot 3/6 */
314 #define ICH_ALI_IF_SPDF_SRC     (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
315 #define ICH_ALI_IF_AC97_OUT     (3<<8)  /* 00 = PCM, 10 = spdif-in, 11 = i2s */
316 #define ICH_ALI_IF_PO_SPDF      (1<<3)
317 #define ICH_ALI_IF_PO           (1<<1)
318 
319 /*
320  *  
321  */
322 
323 enum {
324         ICHD_PCMIN,
325         ICHD_PCMOUT,
326         ICHD_MIC,
327         ICHD_MIC2,
328         ICHD_PCM2IN,
329         ICHD_SPBAR,
330         ICHD_LAST = ICHD_SPBAR
331 };
332 enum {
333         NVD_PCMIN,
334         NVD_PCMOUT,
335         NVD_MIC,
336         NVD_SPBAR,
337         NVD_LAST = NVD_SPBAR
338 };
339 enum {
340         ALID_PCMIN,
341         ALID_PCMOUT,
342         ALID_MIC,
343         ALID_AC97SPDIFOUT,
344         ALID_SPDIFIN,
345         ALID_SPDIFOUT,
346         ALID_LAST = ALID_SPDIFOUT
347 };
348 
349 #define get_ichdev(substream) (substream->runtime->private_data)
350 
351 struct ichdev {
352         unsigned int ichd;                      /* ich device number */
353         unsigned long reg_offset;               /* offset to bmaddr */
354         u32 *bdbar;                             /* CPU address (32bit) */
355         unsigned int bdbar_addr;                /* PCI bus address (32bit) */
356         struct snd_pcm_substream *substream;
357         unsigned int physbuf;                   /* physical address (32bit) */
358         unsigned int size;
359         unsigned int fragsize;
360         unsigned int fragsize1;
361         unsigned int position;
362         unsigned int pos_shift;
363         unsigned int last_pos;
364         int frags;
365         int lvi;
366         int lvi_frag;
367         int civ;
368         int ack;
369         int ack_reload;
370         unsigned int ack_bit;
371         unsigned int roff_sr;
372         unsigned int roff_picb;
373         unsigned int int_sta_mask;              /* interrupt status mask */
374         unsigned int ali_slot;                  /* ALI DMA slot */
375         struct ac97_pcm *pcm;
376         int pcm_open_flag;
377         unsigned int page_attr_changed: 1;
378         unsigned int suspended: 1;
379 };
380 
381 struct intel8x0 {
382         unsigned int device_type;
383 
384         int irq;
385 
386         void __iomem *addr;
387         void __iomem *bmaddr;
388 
389         struct pci_dev *pci;
390         struct snd_card *card;
391 
392         int pcm_devs;
393         struct snd_pcm *pcm[6];
394         struct ichdev ichd[6];
395 
396         unsigned multi4: 1,
397                  multi6: 1,
398                  multi8 :1,
399                  dra: 1,
400                  smp20bit: 1;
401         unsigned in_ac97_init: 1,
402                  in_sdin_init: 1;
403         unsigned in_measurement: 1;     /* during ac97 clock measurement */
404         unsigned fix_nocache: 1;        /* workaround for 440MX */
405         unsigned buggy_irq: 1;          /* workaround for buggy mobos */
406         unsigned xbox: 1;               /* workaround for Xbox AC'97 detection */
407         unsigned buggy_semaphore: 1;    /* workaround for buggy codec semaphore */
408         unsigned inside_vm: 1;          /* enable VM optimization */
409 
410         int spdif_idx;  /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
411         unsigned int sdm_saved; /* SDM reg value */
412 
413         struct snd_ac97_bus *ac97_bus;
414         struct snd_ac97 *ac97[3];
415         unsigned int ac97_sdin[3];
416         unsigned int max_codecs, ncodecs;
417         unsigned int *codec_bit;
418         unsigned int codec_isr_bits;
419         unsigned int codec_ready_bits;
420 
421         spinlock_t reg_lock;
422         
423         u32 bdbars_count;
424         struct snd_dma_buffer bdbars;
425         u32 int_sta_reg;                /* interrupt status register */
426         u32 int_sta_mask;               /* interrupt status mask */
427 };
428 
429 static const struct pci_device_id snd_intel8x0_ids[] = {
430         { PCI_VDEVICE(INTEL, 0x2415), DEVICE_INTEL },   /* 82801AA */
431         { PCI_VDEVICE(INTEL, 0x2425), DEVICE_INTEL },   /* 82901AB */
432         { PCI_VDEVICE(INTEL, 0x2445), DEVICE_INTEL },   /* 82801BA */
433         { PCI_VDEVICE(INTEL, 0x2485), DEVICE_INTEL },   /* ICH3 */
434         { PCI_VDEVICE(INTEL, 0x24c5), DEVICE_INTEL_ICH4 }, /* ICH4 */
435         { PCI_VDEVICE(INTEL, 0x24d5), DEVICE_INTEL_ICH4 }, /* ICH5 */
436         { PCI_VDEVICE(INTEL, 0x25a6), DEVICE_INTEL_ICH4 }, /* ESB */
437         { PCI_VDEVICE(INTEL, 0x266e), DEVICE_INTEL_ICH4 }, /* ICH6 */
438         { PCI_VDEVICE(INTEL, 0x27de), DEVICE_INTEL_ICH4 }, /* ICH7 */
439         { PCI_VDEVICE(INTEL, 0x2698), DEVICE_INTEL_ICH4 }, /* ESB2 */
440         { PCI_VDEVICE(INTEL, 0x7195), DEVICE_INTEL },   /* 440MX */
441         { PCI_VDEVICE(SI, 0x7012), DEVICE_SIS },        /* SI7012 */
442         { PCI_VDEVICE(NVIDIA, 0x01b1), DEVICE_NFORCE }, /* NFORCE */
443         { PCI_VDEVICE(NVIDIA, 0x003a), DEVICE_NFORCE }, /* MCP04 */
444         { PCI_VDEVICE(NVIDIA, 0x006a), DEVICE_NFORCE }, /* NFORCE2 */
445         { PCI_VDEVICE(NVIDIA, 0x0059), DEVICE_NFORCE }, /* CK804 */
446         { PCI_VDEVICE(NVIDIA, 0x008a), DEVICE_NFORCE }, /* CK8 */
447         { PCI_VDEVICE(NVIDIA, 0x00da), DEVICE_NFORCE }, /* NFORCE3 */
448         { PCI_VDEVICE(NVIDIA, 0x00ea), DEVICE_NFORCE }, /* CK8S */
449         { PCI_VDEVICE(NVIDIA, 0x026b), DEVICE_NFORCE }, /* MCP51 */
450         { PCI_VDEVICE(AMD, 0x746d), DEVICE_INTEL },     /* AMD8111 */
451         { PCI_VDEVICE(AMD, 0x7445), DEVICE_INTEL },     /* AMD768 */
452         { PCI_VDEVICE(AL, 0x5455), DEVICE_ALI },   /* Ali5455 */
453         { 0, }
454 };
455 
456 MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
457 
458 /*
459  *  Lowlevel I/O - busmaster
460  */
461 
462 static inline u8 igetbyte(struct intel8x0 *chip, u32 offset)
463 {
464         return ioread8(chip->bmaddr + offset);
465 }
466 
467 static inline u16 igetword(struct intel8x0 *chip, u32 offset)
468 {
469         return ioread16(chip->bmaddr + offset);
470 }
471 
472 static inline u32 igetdword(struct intel8x0 *chip, u32 offset)
473 {
474         return ioread32(chip->bmaddr + offset);
475 }
476 
477 static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val)
478 {
479         iowrite8(val, chip->bmaddr + offset);
480 }
481 
482 static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val)
483 {
484         iowrite16(val, chip->bmaddr + offset);
485 }
486 
487 static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val)
488 {
489         iowrite32(val, chip->bmaddr + offset);
490 }
491 
492 /*
493  *  Lowlevel I/O - AC'97 registers
494  */
495 
496 static inline u16 iagetword(struct intel8x0 *chip, u32 offset)
497 {
498         return ioread16(chip->addr + offset);
499 }
500 
501 static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val)
502 {
503         iowrite16(val, chip->addr + offset);
504 }
505 
506 /*
507  *  Basic I/O
508  */
509 
510 /*
511  * access to AC97 codec via normal i/o (for ICH and SIS7012)
512  */
513 
514 static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec)
515 {
516         int time;
517         
518         if (codec > 2)
519                 return -EIO;
520         if (chip->in_sdin_init) {
521                 /* we don't know the ready bit assignment at the moment */
522                 /* so we check any */
523                 codec = chip->codec_isr_bits;
524         } else {
525                 codec = chip->codec_bit[chip->ac97_sdin[codec]];
526         }
527 
528         /* codec ready ? */
529         if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
530                 return -EIO;
531 
532         if (chip->buggy_semaphore)
533                 return 0; /* just ignore ... */
534 
535         /* Anyone holding a semaphore for 1 msec should be shot... */
536         time = 100;
537         do {
538                 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
539                         return 0;
540                 udelay(10);
541         } while (time--);
542 
543         /* access to some forbidden (non existent) ac97 registers will not
544          * reset the semaphore. So even if you don't get the semaphore, still
545          * continue the access. We don't need the semaphore anyway. */
546         dev_err(chip->card->dev,
547                 "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
548                         igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
549         iagetword(chip, 0);     /* clear semaphore flag */
550         /* I don't care about the semaphore */
551         return -EBUSY;
552 }
553  
554 static void snd_intel8x0_codec_write(struct snd_ac97 *ac97,
555                                      unsigned short reg,
556                                      unsigned short val)
557 {
558         struct intel8x0 *chip = ac97->private_data;
559         
560         if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
561                 if (! chip->in_ac97_init)
562                         dev_err(chip->card->dev,
563                                 "codec_write %d: semaphore is not ready for register 0x%x\n",
564                                 ac97->num, reg);
565         }
566         iaputword(chip, reg + ac97->num * 0x80, val);
567 }
568 
569 static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97,
570                                               unsigned short reg)
571 {
572         struct intel8x0 *chip = ac97->private_data;
573         unsigned short res;
574         unsigned int tmp;
575 
576         if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
577                 if (! chip->in_ac97_init)
578                         dev_err(chip->card->dev,
579                                 "codec_read %d: semaphore is not ready for register 0x%x\n",
580                                 ac97->num, reg);
581                 res = 0xffff;
582         } else {
583                 res = iagetword(chip, reg + ac97->num * 0x80);
584                 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
585                         /* reset RCS and preserve other R/WC bits */
586                         iputdword(chip, ICHREG(GLOB_STA), tmp &
587                                   ~(chip->codec_ready_bits | ICH_GSCI));
588                         if (! chip->in_ac97_init)
589                                 dev_err(chip->card->dev,
590                                         "codec_read %d: read timeout for register 0x%x\n",
591                                         ac97->num, reg);
592                         res = 0xffff;
593                 }
594         }
595         return res;
596 }
597 
598 static void snd_intel8x0_codec_read_test(struct intel8x0 *chip,
599                                          unsigned int codec)
600 {
601         unsigned int tmp;
602 
603         if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
604                 iagetword(chip, codec * 0x80);
605                 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
606                         /* reset RCS and preserve other R/WC bits */
607                         iputdword(chip, ICHREG(GLOB_STA), tmp &
608                                   ~(chip->codec_ready_bits | ICH_GSCI));
609                 }
610         }
611 }
612 
613 /*
614  * access to AC97 for Ali5455
615  */
616 static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask)
617 {
618         int count = 0;
619         for (count = 0; count < 0x7f; count++) {
620                 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
621                 if (val & mask)
622                         return 0;
623         }
624         if (! chip->in_ac97_init)
625                 dev_warn(chip->card->dev, "AC97 codec ready timeout.\n");
626         return -EBUSY;
627 }
628 
629 static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip)
630 {
631         int time = 100;
632         if (chip->buggy_semaphore)
633                 return 0; /* just ignore ... */
634         while (--time && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
635                 udelay(1);
636         if (! time && ! chip->in_ac97_init)
637                 dev_warn(chip->card->dev, "ali_codec_semaphore timeout\n");
638         return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
639 }
640 
641 static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg)
642 {
643         struct intel8x0 *chip = ac97->private_data;
644         unsigned short data = 0xffff;
645 
646         if (snd_intel8x0_ali_codec_semaphore(chip))
647                 goto __err;
648         reg |= ALI_CPR_ADDR_READ;
649         if (ac97->num)
650                 reg |= ALI_CPR_ADDR_SECONDARY;
651         iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
652         if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
653                 goto __err;
654         data = igetword(chip, ICHREG(ALI_SPR));
655  __err:
656         return data;
657 }
658 
659 static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg,
660                                          unsigned short val)
661 {
662         struct intel8x0 *chip = ac97->private_data;
663 
664         if (snd_intel8x0_ali_codec_semaphore(chip))
665                 return;
666         iputword(chip, ICHREG(ALI_CPR), val);
667         if (ac97->num)
668                 reg |= ALI_CPR_ADDR_SECONDARY;
669         iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
670         snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
671 }
672 
673 
674 /*
675  * DMA I/O
676  */
677 static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev) 
678 {
679         int idx;
680         u32 *bdbar = ichdev->bdbar;
681         unsigned long port = ichdev->reg_offset;
682 
683         iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
684         if (ichdev->size == ichdev->fragsize) {
685                 ichdev->ack_reload = ichdev->ack = 2;
686                 ichdev->fragsize1 = ichdev->fragsize >> 1;
687                 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
688                         bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
689                         bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
690                                                      ichdev->fragsize1 >> ichdev->pos_shift);
691                         bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
692                         bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
693                                                      ichdev->fragsize1 >> ichdev->pos_shift);
694                 }
695                 ichdev->frags = 2;
696         } else {
697                 ichdev->ack_reload = ichdev->ack = 1;
698                 ichdev->fragsize1 = ichdev->fragsize;
699                 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
700                         bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf +
701                                                      (((idx >> 1) * ichdev->fragsize) %
702                                                       ichdev->size));
703                         bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
704                                                      ichdev->fragsize >> ichdev->pos_shift);
705 #if 0
706                         dev_dbg(chip->card->dev, "bdbar[%i] = 0x%x [0x%x]\n",
707                                idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
708 #endif
709                 }
710                 ichdev->frags = ichdev->size / ichdev->fragsize;
711         }
712         iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
713         ichdev->civ = 0;
714         iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
715         ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
716         ichdev->position = 0;
717 #if 0
718         dev_dbg(chip->card->dev,
719                 "lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
720                ichdev->lvi_frag, ichdev->frags, ichdev->fragsize,
721                ichdev->fragsize1);
722 #endif
723         /* clear interrupts */
724         iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
725 }
726 
727 #ifdef __i386__
728 /*
729  * Intel 82443MX running a 100MHz processor system bus has a hardware bug,
730  * which aborts PCI busmaster for audio transfer.  A workaround is to set
731  * the pages as non-cached.  For details, see the errata in
732  *      http://download.intel.com/design/chipsets/specupdt/24505108.pdf
733  */
734 static void fill_nocache(void *buf, int size, int nocache)
735 {
736         size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
737         if (nocache)
738                 set_pages_uc(virt_to_page(buf), size);
739         else
740                 set_pages_wb(virt_to_page(buf), size);
741 }
742 #else
743 #define fill_nocache(buf, size, nocache) do { ; } while (0)
744 #endif
745 
746 /*
747  *  Interrupt handler
748  */
749 
750 static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev)
751 {
752         unsigned long port = ichdev->reg_offset;
753         unsigned long flags;
754         int status, civ, i, step;
755         int ack = 0;
756 
757         spin_lock_irqsave(&chip->reg_lock, flags);
758         status = igetbyte(chip, port + ichdev->roff_sr);
759         civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
760         if (!(status & ICH_BCIS)) {
761                 step = 0;
762         } else if (civ == ichdev->civ) {
763                 // snd_printd("civ same %d\n", civ);
764                 step = 1;
765                 ichdev->civ++;
766                 ichdev->civ &= ICH_REG_LVI_MASK;
767         } else {
768                 step = civ - ichdev->civ;
769                 if (step < 0)
770                         step += ICH_REG_LVI_MASK + 1;
771                 // if (step != 1)
772                 //      snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
773                 ichdev->civ = civ;
774         }
775 
776         ichdev->position += step * ichdev->fragsize1;
777         if (! chip->in_measurement)
778                 ichdev->position %= ichdev->size;
779         ichdev->lvi += step;
780         ichdev->lvi &= ICH_REG_LVI_MASK;
781         iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
782         for (i = 0; i < step; i++) {
783                 ichdev->lvi_frag++;
784                 ichdev->lvi_frag %= ichdev->frags;
785                 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
786 #if 0
787         dev_dbg(chip->card->dev,
788                 "new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n",
789                ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
790                ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
791                inl(port + 4), inb(port + ICH_REG_OFF_CR));
792 #endif
793                 if (--ichdev->ack == 0) {
794                         ichdev->ack = ichdev->ack_reload;
795                         ack = 1;
796                 }
797         }
798         spin_unlock_irqrestore(&chip->reg_lock, flags);
799         if (ack && ichdev->substream) {
800                 snd_pcm_period_elapsed(ichdev->substream);
801         }
802         iputbyte(chip, port + ichdev->roff_sr,
803                  status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
804 }
805 
806 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id)
807 {
808         struct intel8x0 *chip = dev_id;
809         struct ichdev *ichdev;
810         unsigned int status;
811         unsigned int i;
812 
813         status = igetdword(chip, chip->int_sta_reg);
814         if (status == 0xffffffff)       /* we are not yet resumed */
815                 return IRQ_NONE;
816 
817         if ((status & chip->int_sta_mask) == 0) {
818                 if (status) {
819                         /* ack */
820                         iputdword(chip, chip->int_sta_reg, status);
821                         if (! chip->buggy_irq)
822                                 status = 0;
823                 }
824                 return IRQ_RETVAL(status);
825         }
826 
827         for (i = 0; i < chip->bdbars_count; i++) {
828                 ichdev = &chip->ichd[i];
829                 if (status & ichdev->int_sta_mask)
830                         snd_intel8x0_update(chip, ichdev);
831         }
832 
833         /* ack them */
834         iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
835         
836         return IRQ_HANDLED;
837 }
838 
839 /*
840  *  PCM part
841  */
842 
843 static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
844 {
845         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
846         struct ichdev *ichdev = get_ichdev(substream);
847         unsigned char val = 0;
848         unsigned long port = ichdev->reg_offset;
849 
850         switch (cmd) {
851         case SNDRV_PCM_TRIGGER_RESUME:
852                 ichdev->suspended = 0;
853                 /* fallthru */
854         case SNDRV_PCM_TRIGGER_START:
855         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
856                 val = ICH_IOCE | ICH_STARTBM;
857                 ichdev->last_pos = ichdev->position;
858                 break;
859         case SNDRV_PCM_TRIGGER_SUSPEND:
860                 ichdev->suspended = 1;
861                 /* fallthru */
862         case SNDRV_PCM_TRIGGER_STOP:
863                 val = 0;
864                 break;
865         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
866                 val = ICH_IOCE;
867                 break;
868         default:
869                 return -EINVAL;
870         }
871         iputbyte(chip, port + ICH_REG_OFF_CR, val);
872         if (cmd == SNDRV_PCM_TRIGGER_STOP) {
873                 /* wait until DMA stopped */
874                 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
875                 /* reset whole DMA things */
876                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
877         }
878         return 0;
879 }
880 
881 static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd)
882 {
883         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
884         struct ichdev *ichdev = get_ichdev(substream);
885         unsigned long port = ichdev->reg_offset;
886         static int fiforeg[] = {
887                 ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3)
888         };
889         unsigned int val, fifo;
890 
891         val = igetdword(chip, ICHREG(ALI_DMACR));
892         switch (cmd) {
893         case SNDRV_PCM_TRIGGER_RESUME:
894                 ichdev->suspended = 0;
895                 /* fallthru */
896         case SNDRV_PCM_TRIGGER_START:
897         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
898                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
899                         /* clear FIFO for synchronization of channels */
900                         fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
901                         fifo &= ~(0xff << (ichdev->ali_slot % 4));  
902                         fifo |= 0x83 << (ichdev->ali_slot % 4); 
903                         iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
904                 }
905                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
906                 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
907                 /* start DMA */
908                 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot));
909                 break;
910         case SNDRV_PCM_TRIGGER_SUSPEND:
911                 ichdev->suspended = 1;
912                 /* fallthru */
913         case SNDRV_PCM_TRIGGER_STOP:
914         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
915                 /* pause */
916                 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16)));
917                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
918                 while (igetbyte(chip, port + ICH_REG_OFF_CR))
919                         ;
920                 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
921                         break;
922                 /* reset whole DMA things */
923                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
924                 /* clear interrupts */
925                 iputbyte(chip, port + ICH_REG_OFF_SR,
926                          igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
927                 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
928                           igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
929                 break;
930         default:
931                 return -EINVAL;
932         }
933         return 0;
934 }
935 
936 static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream,
937                                   struct snd_pcm_hw_params *hw_params)
938 {
939         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
940         struct ichdev *ichdev = get_ichdev(substream);
941         struct snd_pcm_runtime *runtime = substream->runtime;
942         int dbl = params_rate(hw_params) > 48000;
943         int err;
944 
945         if (chip->fix_nocache && ichdev->page_attr_changed) {
946                 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */
947                 ichdev->page_attr_changed = 0;
948         }
949         err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
950         if (err < 0)
951                 return err;
952         if (chip->fix_nocache) {
953                 if (runtime->dma_area && ! ichdev->page_attr_changed) {
954                         fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
955                         ichdev->page_attr_changed = 1;
956                 }
957         }
958         if (ichdev->pcm_open_flag) {
959                 snd_ac97_pcm_close(ichdev->pcm);
960                 ichdev->pcm_open_flag = 0;
961         }
962         err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
963                                 params_channels(hw_params),
964                                 ichdev->pcm->r[dbl].slots);
965         if (err >= 0) {
966                 ichdev->pcm_open_flag = 1;
967                 /* Force SPDIF setting */
968                 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
969                         snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF,
970                                           params_rate(hw_params));
971         }
972         return err;
973 }
974 
975 static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream)
976 {
977         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
978         struct ichdev *ichdev = get_ichdev(substream);
979 
980         if (ichdev->pcm_open_flag) {
981                 snd_ac97_pcm_close(ichdev->pcm);
982                 ichdev->pcm_open_flag = 0;
983         }
984         if (chip->fix_nocache && ichdev->page_attr_changed) {
985                 fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0);
986                 ichdev->page_attr_changed = 0;
987         }
988         return snd_pcm_lib_free_pages(substream);
989 }
990 
991 static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip,
992                                        struct snd_pcm_runtime *runtime)
993 {
994         unsigned int cnt;
995         int dbl = runtime->rate > 48000;
996 
997         spin_lock_irq(&chip->reg_lock);
998         switch (chip->device_type) {
999         case DEVICE_ALI:
1000                 cnt = igetdword(chip, ICHREG(ALI_SCR));
1001                 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
1002                 if (runtime->channels == 4 || dbl)
1003                         cnt |= ICH_ALI_SC_PCM_4;
1004                 else if (runtime->channels == 6)
1005                         cnt |= ICH_ALI_SC_PCM_6;
1006                 iputdword(chip, ICHREG(ALI_SCR), cnt);
1007                 break;
1008         case DEVICE_SIS:
1009                 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1010                 cnt &= ~ICH_SIS_PCM_246_MASK;
1011                 if (runtime->channels == 4 || dbl)
1012                         cnt |= ICH_SIS_PCM_4;
1013                 else if (runtime->channels == 6)
1014                         cnt |= ICH_SIS_PCM_6;
1015                 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1016                 break;
1017         default:
1018                 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1019                 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
1020                 if (runtime->channels == 4 || dbl)
1021                         cnt |= ICH_PCM_4;
1022                 else if (runtime->channels == 6)
1023                         cnt |= ICH_PCM_6;
1024                 else if (runtime->channels == 8)
1025                         cnt |= ICH_PCM_8;
1026                 if (chip->device_type == DEVICE_NFORCE) {
1027                         /* reset to 2ch once to keep the 6 channel data in alignment,
1028                          * to start from Front Left always
1029                          */
1030                         if (cnt & ICH_PCM_246_MASK) {
1031                                 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
1032                                 spin_unlock_irq(&chip->reg_lock);
1033                                 msleep(50); /* grrr... */
1034                                 spin_lock_irq(&chip->reg_lock);
1035                         }
1036                 } else if (chip->device_type == DEVICE_INTEL_ICH4) {
1037                         if (runtime->sample_bits > 16)
1038                                 cnt |= ICH_PCM_20BIT;
1039                 }
1040                 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1041                 break;
1042         }
1043         spin_unlock_irq(&chip->reg_lock);
1044 }
1045 
1046 static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream)
1047 {
1048         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1049         struct snd_pcm_runtime *runtime = substream->runtime;
1050         struct ichdev *ichdev = get_ichdev(substream);
1051 
1052         ichdev->physbuf = runtime->dma_addr;
1053         ichdev->size = snd_pcm_lib_buffer_bytes(substream);
1054         ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
1055         if (ichdev->ichd == ICHD_PCMOUT) {
1056                 snd_intel8x0_setup_pcm_out(chip, runtime);
1057                 if (chip->device_type == DEVICE_INTEL_ICH4)
1058                         ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
1059         }
1060         snd_intel8x0_setup_periods(chip, ichdev);
1061         return 0;
1062 }
1063 
1064 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream)
1065 {
1066         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1067         struct ichdev *ichdev = get_ichdev(substream);
1068         size_t ptr1, ptr;
1069         int civ, timeout = 10;
1070         unsigned int position;
1071 
1072         spin_lock(&chip->reg_lock);
1073         do {
1074                 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1075                 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1076                 position = ichdev->position;
1077                 if (ptr1 == 0) {
1078                         udelay(10);
1079                         continue;
1080                 }
1081                 if (civ != igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV))
1082                         continue;
1083 
1084                 /* IO read operation is very expensive inside virtual machine
1085                  * as it is emulated. The probability that subsequent PICB read
1086                  * will return different result is high enough to loop till
1087                  * timeout here.
1088                  * Same CIV is strict enough condition to be sure that PICB
1089                  * is valid inside VM on emulated card. */
1090                 if (chip->inside_vm)
1091                         break;
1092                 if (ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1093                         break;
1094         } while (timeout--);
1095         ptr = ichdev->last_pos;
1096         if (ptr1 != 0) {
1097                 ptr1 <<= ichdev->pos_shift;
1098                 ptr = ichdev->fragsize1 - ptr1;
1099                 ptr += position;
1100                 if (ptr < ichdev->last_pos) {
1101                         unsigned int pos_base, last_base;
1102                         pos_base = position / ichdev->fragsize1;
1103                         last_base = ichdev->last_pos / ichdev->fragsize1;
1104                         /* another sanity check; ptr1 can go back to full
1105                          * before the base position is updated
1106                          */
1107                         if (pos_base == last_base)
1108                                 ptr = ichdev->last_pos;
1109                 }
1110         }
1111         ichdev->last_pos = ptr;
1112         spin_unlock(&chip->reg_lock);
1113         if (ptr >= ichdev->size)
1114                 return 0;
1115         return bytes_to_frames(substream->runtime, ptr);
1116 }
1117 
1118 static const struct snd_pcm_hardware snd_intel8x0_stream =
1119 {
1120         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1121                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1122                                  SNDRV_PCM_INFO_MMAP_VALID |
1123                                  SNDRV_PCM_INFO_PAUSE |
1124                                  SNDRV_PCM_INFO_RESUME),
1125         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1126         .rates =                SNDRV_PCM_RATE_48000,
1127         .rate_min =             48000,
1128         .rate_max =             48000,
1129         .channels_min =         2,
1130         .channels_max =         2,
1131         .buffer_bytes_max =     128 * 1024,
1132         .period_bytes_min =     32,
1133         .period_bytes_max =     128 * 1024,
1134         .periods_min =          1,
1135         .periods_max =          1024,
1136         .fifo_size =            0,
1137 };
1138 
1139 static const unsigned int channels4[] = {
1140         2, 4,
1141 };
1142 
1143 static const struct snd_pcm_hw_constraint_list hw_constraints_channels4 = {
1144         .count = ARRAY_SIZE(channels4),
1145         .list = channels4,
1146         .mask = 0,
1147 };
1148 
1149 static const unsigned int channels6[] = {
1150         2, 4, 6,
1151 };
1152 
1153 static const struct snd_pcm_hw_constraint_list hw_constraints_channels6 = {
1154         .count = ARRAY_SIZE(channels6),
1155         .list = channels6,
1156         .mask = 0,
1157 };
1158 
1159 static const unsigned int channels8[] = {
1160         2, 4, 6, 8,
1161 };
1162 
1163 static const struct snd_pcm_hw_constraint_list hw_constraints_channels8 = {
1164         .count = ARRAY_SIZE(channels8),
1165         .list = channels8,
1166         .mask = 0,
1167 };
1168 
1169 static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
1170 {
1171         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1172         struct snd_pcm_runtime *runtime = substream->runtime;
1173         int err;
1174 
1175         ichdev->substream = substream;
1176         runtime->hw = snd_intel8x0_stream;
1177         runtime->hw.rates = ichdev->pcm->rates;
1178         snd_pcm_limit_hw_rates(runtime);
1179         if (chip->device_type == DEVICE_SIS) {
1180                 runtime->hw.buffer_bytes_max = 64*1024;
1181                 runtime->hw.period_bytes_max = 64*1024;
1182         }
1183         if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1184                 return err;
1185         runtime->private_data = ichdev;
1186         return 0;
1187 }
1188 
1189 static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream)
1190 {
1191         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1192         struct snd_pcm_runtime *runtime = substream->runtime;
1193         int err;
1194 
1195         err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1196         if (err < 0)
1197                 return err;
1198 
1199         if (chip->multi8) {
1200                 runtime->hw.channels_max = 8;
1201                 snd_pcm_hw_constraint_list(runtime, 0,
1202                                                 SNDRV_PCM_HW_PARAM_CHANNELS,
1203                                                 &hw_constraints_channels8);
1204         } else if (chip->multi6) {
1205                 runtime->hw.channels_max = 6;
1206                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1207                                            &hw_constraints_channels6);
1208         } else if (chip->multi4) {
1209                 runtime->hw.channels_max = 4;
1210                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1211                                            &hw_constraints_channels4);
1212         }
1213         if (chip->dra) {
1214                 snd_ac97_pcm_double_rate_rules(runtime);
1215         }
1216         if (chip->smp20bit) {
1217                 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1218                 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
1219         }
1220         return 0;
1221 }
1222 
1223 static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream)
1224 {
1225         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1226 
1227         chip->ichd[ICHD_PCMOUT].substream = NULL;
1228         return 0;
1229 }
1230 
1231 static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream)
1232 {
1233         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1234 
1235         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1236 }
1237 
1238 static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream)
1239 {
1240         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1241 
1242         chip->ichd[ICHD_PCMIN].substream = NULL;
1243         return 0;
1244 }
1245 
1246 static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream)
1247 {
1248         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1249 
1250         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1251 }
1252 
1253 static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream)
1254 {
1255         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1256 
1257         chip->ichd[ICHD_MIC].substream = NULL;
1258         return 0;
1259 }
1260 
1261 static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream)
1262 {
1263         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1264 
1265         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1266 }
1267 
1268 static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream)
1269 {
1270         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1271 
1272         chip->ichd[ICHD_MIC2].substream = NULL;
1273         return 0;
1274 }
1275 
1276 static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream)
1277 {
1278         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1279 
1280         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1281 }
1282 
1283 static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream)
1284 {
1285         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1286 
1287         chip->ichd[ICHD_PCM2IN].substream = NULL;
1288         return 0;
1289 }
1290 
1291 static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream)
1292 {
1293         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1294         int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1295 
1296         return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1297 }
1298 
1299 static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream)
1300 {
1301         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1302         int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1303 
1304         chip->ichd[idx].substream = NULL;
1305         return 0;
1306 }
1307 
1308 static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream)
1309 {
1310         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1311         unsigned int val;
1312 
1313         spin_lock_irq(&chip->reg_lock);
1314         val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1315         val |= ICH_ALI_IF_AC97SP;
1316         iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1317         /* also needs to set ALI_SC_CODEC_SPDF correctly */
1318         spin_unlock_irq(&chip->reg_lock);
1319 
1320         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1321 }
1322 
1323 static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream)
1324 {
1325         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1326         unsigned int val;
1327 
1328         chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1329         spin_lock_irq(&chip->reg_lock);
1330         val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1331         val &= ~ICH_ALI_IF_AC97SP;
1332         iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1333         spin_unlock_irq(&chip->reg_lock);
1334 
1335         return 0;
1336 }
1337 
1338 #if 0 // NYI
1339 static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream)
1340 {
1341         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1342 
1343         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1344 }
1345 
1346 static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream)
1347 {
1348         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1349 
1350         chip->ichd[ALID_SPDIFIN].substream = NULL;
1351         return 0;
1352 }
1353 
1354 static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream)
1355 {
1356         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1357 
1358         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1359 }
1360 
1361 static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream)
1362 {
1363         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1364 
1365         chip->ichd[ALID_SPDIFOUT].substream = NULL;
1366         return 0;
1367 }
1368 #endif
1369 
1370 static const struct snd_pcm_ops snd_intel8x0_playback_ops = {
1371         .open =         snd_intel8x0_playback_open,
1372         .close =        snd_intel8x0_playback_close,
1373         .ioctl =        snd_pcm_lib_ioctl,
1374         .hw_params =    snd_intel8x0_hw_params,
1375         .hw_free =      snd_intel8x0_hw_free,
1376         .prepare =      snd_intel8x0_pcm_prepare,
1377         .trigger =      snd_intel8x0_pcm_trigger,
1378         .pointer =      snd_intel8x0_pcm_pointer,
1379 };
1380 
1381 static const struct snd_pcm_ops snd_intel8x0_capture_ops = {
1382         .open =         snd_intel8x0_capture_open,
1383         .close =        snd_intel8x0_capture_close,
1384         .ioctl =        snd_pcm_lib_ioctl,
1385         .hw_params =    snd_intel8x0_hw_params,
1386         .hw_free =      snd_intel8x0_hw_free,
1387         .prepare =      snd_intel8x0_pcm_prepare,
1388         .trigger =      snd_intel8x0_pcm_trigger,
1389         .pointer =      snd_intel8x0_pcm_pointer,
1390 };
1391 
1392 static const struct snd_pcm_ops snd_intel8x0_capture_mic_ops = {
1393         .open =         snd_intel8x0_mic_open,
1394         .close =        snd_intel8x0_mic_close,
1395         .ioctl =        snd_pcm_lib_ioctl,
1396         .hw_params =    snd_intel8x0_hw_params,
1397         .hw_free =      snd_intel8x0_hw_free,
1398         .prepare =      snd_intel8x0_pcm_prepare,
1399         .trigger =      snd_intel8x0_pcm_trigger,
1400         .pointer =      snd_intel8x0_pcm_pointer,
1401 };
1402 
1403 static const struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = {
1404         .open =         snd_intel8x0_mic2_open,
1405         .close =        snd_intel8x0_mic2_close,
1406         .ioctl =        snd_pcm_lib_ioctl,
1407         .hw_params =    snd_intel8x0_hw_params,
1408         .hw_free =      snd_intel8x0_hw_free,
1409         .prepare =      snd_intel8x0_pcm_prepare,
1410         .trigger =      snd_intel8x0_pcm_trigger,
1411         .pointer =      snd_intel8x0_pcm_pointer,
1412 };
1413 
1414 static const struct snd_pcm_ops snd_intel8x0_capture2_ops = {
1415         .open =         snd_intel8x0_capture2_open,
1416         .close =        snd_intel8x0_capture2_close,
1417         .ioctl =        snd_pcm_lib_ioctl,
1418         .hw_params =    snd_intel8x0_hw_params,
1419         .hw_free =      snd_intel8x0_hw_free,
1420         .prepare =      snd_intel8x0_pcm_prepare,
1421         .trigger =      snd_intel8x0_pcm_trigger,
1422         .pointer =      snd_intel8x0_pcm_pointer,
1423 };
1424 
1425 static const struct snd_pcm_ops snd_intel8x0_spdif_ops = {
1426         .open =         snd_intel8x0_spdif_open,
1427         .close =        snd_intel8x0_spdif_close,
1428         .ioctl =        snd_pcm_lib_ioctl,
1429         .hw_params =    snd_intel8x0_hw_params,
1430         .hw_free =      snd_intel8x0_hw_free,
1431         .prepare =      snd_intel8x0_pcm_prepare,
1432         .trigger =      snd_intel8x0_pcm_trigger,
1433         .pointer =      snd_intel8x0_pcm_pointer,
1434 };
1435 
1436 static const struct snd_pcm_ops snd_intel8x0_ali_playback_ops = {
1437         .open =         snd_intel8x0_playback_open,
1438         .close =        snd_intel8x0_playback_close,
1439         .ioctl =        snd_pcm_lib_ioctl,
1440         .hw_params =    snd_intel8x0_hw_params,
1441         .hw_free =      snd_intel8x0_hw_free,
1442         .prepare =      snd_intel8x0_pcm_prepare,
1443         .trigger =      snd_intel8x0_ali_trigger,
1444         .pointer =      snd_intel8x0_pcm_pointer,
1445 };
1446 
1447 static const struct snd_pcm_ops snd_intel8x0_ali_capture_ops = {
1448         .open =         snd_intel8x0_capture_open,
1449         .close =        snd_intel8x0_capture_close,
1450         .ioctl =        snd_pcm_lib_ioctl,
1451         .hw_params =    snd_intel8x0_hw_params,
1452         .hw_free =      snd_intel8x0_hw_free,
1453         .prepare =      snd_intel8x0_pcm_prepare,
1454         .trigger =      snd_intel8x0_ali_trigger,
1455         .pointer =      snd_intel8x0_pcm_pointer,
1456 };
1457 
1458 static const struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = {
1459         .open =         snd_intel8x0_mic_open,
1460         .close =        snd_intel8x0_mic_close,
1461         .ioctl =        snd_pcm_lib_ioctl,
1462         .hw_params =    snd_intel8x0_hw_params,
1463         .hw_free =      snd_intel8x0_hw_free,
1464         .prepare =      snd_intel8x0_pcm_prepare,
1465         .trigger =      snd_intel8x0_ali_trigger,
1466         .pointer =      snd_intel8x0_pcm_pointer,
1467 };
1468 
1469 static const struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = {
1470         .open =         snd_intel8x0_ali_ac97spdifout_open,
1471         .close =        snd_intel8x0_ali_ac97spdifout_close,
1472         .ioctl =        snd_pcm_lib_ioctl,
1473         .hw_params =    snd_intel8x0_hw_params,
1474         .hw_free =      snd_intel8x0_hw_free,
1475         .prepare =      snd_intel8x0_pcm_prepare,
1476         .trigger =      snd_intel8x0_ali_trigger,
1477         .pointer =      snd_intel8x0_pcm_pointer,
1478 };
1479 
1480 #if 0 // NYI
1481 static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = {
1482         .open =         snd_intel8x0_ali_spdifin_open,
1483         .close =        snd_intel8x0_ali_spdifin_close,
1484         .ioctl =        snd_pcm_lib_ioctl,
1485         .hw_params =    snd_intel8x0_hw_params,
1486         .hw_free =      snd_intel8x0_hw_free,
1487         .prepare =      snd_intel8x0_pcm_prepare,
1488         .trigger =      snd_intel8x0_pcm_trigger,
1489         .pointer =      snd_intel8x0_pcm_pointer,
1490 };
1491 
1492 static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = {
1493         .open =         snd_intel8x0_ali_spdifout_open,
1494         .close =        snd_intel8x0_ali_spdifout_close,
1495         .ioctl =        snd_pcm_lib_ioctl,
1496         .hw_params =    snd_intel8x0_hw_params,
1497         .hw_free =      snd_intel8x0_hw_free,
1498         .prepare =      snd_intel8x0_pcm_prepare,
1499         .trigger =      snd_intel8x0_pcm_trigger,
1500         .pointer =      snd_intel8x0_pcm_pointer,
1501 };
1502 #endif // NYI
1503 
1504 struct ich_pcm_table {
1505         char *suffix;
1506         const struct snd_pcm_ops *playback_ops;
1507         const struct snd_pcm_ops *capture_ops;
1508         size_t prealloc_size;
1509         size_t prealloc_max_size;
1510         int ac97_idx;
1511 };
1512 
1513 static int snd_intel8x0_pcm1(struct intel8x0 *chip, int device,
1514                              struct ich_pcm_table *rec)
1515 {
1516         struct snd_pcm *pcm;
1517         int err;
1518         char name[32];
1519 
1520         if (rec->suffix)
1521                 sprintf(name, "Intel ICH - %s", rec->suffix);
1522         else
1523                 strcpy(name, "Intel ICH");
1524         err = snd_pcm_new(chip->card, name, device,
1525                           rec->playback_ops ? 1 : 0,
1526                           rec->capture_ops ? 1 : 0, &pcm);
1527         if (err < 0)
1528                 return err;
1529 
1530         if (rec->playback_ops)
1531                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1532         if (rec->capture_ops)
1533                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1534 
1535         pcm->private_data = chip;
1536         pcm->info_flags = 0;
1537         if (rec->suffix)
1538                 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1539         else
1540                 strcpy(pcm->name, chip->card->shortname);
1541         chip->pcm[device] = pcm;
1542 
1543         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1544                                               snd_dma_pci_data(chip->pci),
1545                                               rec->prealloc_size, rec->prealloc_max_size);
1546 
1547         if (rec->playback_ops &&
1548             rec->playback_ops->open == snd_intel8x0_playback_open) {
1549                 struct snd_pcm_chmap *chmap;
1550                 int chs = 2;
1551                 if (chip->multi8)
1552                         chs = 8;
1553                 else if (chip->multi6)
1554                         chs = 6;
1555                 else if (chip->multi4)
1556                         chs = 4;
1557                 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1558                                              snd_pcm_alt_chmaps, chs, 0,
1559                                              &chmap);
1560                 if (err < 0)
1561                         return err;
1562                 chmap->channel_mask = SND_PCM_CHMAP_MASK_2468;
1563                 chip->ac97[0]->chmaps[SNDRV_PCM_STREAM_PLAYBACK] = chmap;
1564         }
1565 
1566         return 0;
1567 }
1568 
1569 static struct ich_pcm_table intel_pcms[] = {
1570         {
1571                 .playback_ops = &snd_intel8x0_playback_ops,
1572                 .capture_ops = &snd_intel8x0_capture_ops,
1573                 .prealloc_size = 64 * 1024,
1574                 .prealloc_max_size = 128 * 1024,
1575         },
1576         {
1577                 .suffix = "MIC ADC",
1578                 .capture_ops = &snd_intel8x0_capture_mic_ops,
1579                 .prealloc_size = 0,
1580                 .prealloc_max_size = 128 * 1024,
1581                 .ac97_idx = ICHD_MIC,
1582         },
1583         {
1584                 .suffix = "MIC2 ADC",
1585                 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1586                 .prealloc_size = 0,
1587                 .prealloc_max_size = 128 * 1024,
1588                 .ac97_idx = ICHD_MIC2,
1589         },
1590         {
1591                 .suffix = "ADC2",
1592                 .capture_ops = &snd_intel8x0_capture2_ops,
1593                 .prealloc_size = 0,
1594                 .prealloc_max_size = 128 * 1024,
1595                 .ac97_idx = ICHD_PCM2IN,
1596         },
1597         {
1598                 .suffix = "IEC958",
1599                 .playback_ops = &snd_intel8x0_spdif_ops,
1600                 .prealloc_size = 64 * 1024,
1601                 .prealloc_max_size = 128 * 1024,
1602                 .ac97_idx = ICHD_SPBAR,
1603         },
1604 };
1605 
1606 static struct ich_pcm_table nforce_pcms[] = {
1607         {
1608                 .playback_ops = &snd_intel8x0_playback_ops,
1609                 .capture_ops = &snd_intel8x0_capture_ops,
1610                 .prealloc_size = 64 * 1024,
1611                 .prealloc_max_size = 128 * 1024,
1612         },
1613         {
1614                 .suffix = "MIC ADC",
1615                 .capture_ops = &snd_intel8x0_capture_mic_ops,
1616                 .prealloc_size = 0,
1617                 .prealloc_max_size = 128 * 1024,
1618                 .ac97_idx = NVD_MIC,
1619         },
1620         {
1621                 .suffix = "IEC958",
1622                 .playback_ops = &snd_intel8x0_spdif_ops,
1623                 .prealloc_size = 64 * 1024,
1624                 .prealloc_max_size = 128 * 1024,
1625                 .ac97_idx = NVD_SPBAR,
1626         },
1627 };
1628 
1629 static struct ich_pcm_table ali_pcms[] = {
1630         {
1631                 .playback_ops = &snd_intel8x0_ali_playback_ops,
1632                 .capture_ops = &snd_intel8x0_ali_capture_ops,
1633                 .prealloc_size = 64 * 1024,
1634                 .prealloc_max_size = 128 * 1024,
1635         },
1636         {
1637                 .suffix = "MIC ADC",
1638                 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1639                 .prealloc_size = 0,
1640                 .prealloc_max_size = 128 * 1024,
1641                 .ac97_idx = ALID_MIC,
1642         },
1643         {
1644                 .suffix = "IEC958",
1645                 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1646                 /* .capture_ops = &snd_intel8x0_ali_spdifin_ops, */
1647                 .prealloc_size = 64 * 1024,
1648                 .prealloc_max_size = 128 * 1024,
1649                 .ac97_idx = ALID_AC97SPDIFOUT,
1650         },
1651 #if 0 // NYI
1652         {
1653                 .suffix = "HW IEC958",
1654                 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1655                 .prealloc_size = 64 * 1024,
1656                 .prealloc_max_size = 128 * 1024,
1657         },
1658 #endif
1659 };
1660 
1661 static int snd_intel8x0_pcm(struct intel8x0 *chip)
1662 {
1663         int i, tblsize, device, err;
1664         struct ich_pcm_table *tbl, *rec;
1665 
1666         switch (chip->device_type) {
1667         case DEVICE_INTEL_ICH4:
1668                 tbl = intel_pcms;
1669                 tblsize = ARRAY_SIZE(intel_pcms);
1670                 if (spdif_aclink)
1671                         tblsize--;
1672                 break;
1673         case DEVICE_NFORCE:
1674                 tbl = nforce_pcms;
1675                 tblsize = ARRAY_SIZE(nforce_pcms);
1676                 if (spdif_aclink)
1677                         tblsize--;
1678                 break;
1679         case DEVICE_ALI:
1680                 tbl = ali_pcms;
1681                 tblsize = ARRAY_SIZE(ali_pcms);
1682                 break;
1683         default:
1684                 tbl = intel_pcms;
1685                 tblsize = 2;
1686                 break;
1687         }
1688 
1689         device = 0;
1690         for (i = 0; i < tblsize; i++) {
1691                 rec = tbl + i;
1692                 if (i > 0 && rec->ac97_idx) {
1693                         /* activate PCM only when associated AC'97 codec */
1694                         if (! chip->ichd[rec->ac97_idx].pcm)
1695                                 continue;
1696                 }
1697                 err = snd_intel8x0_pcm1(chip, device, rec);
1698                 if (err < 0)
1699                         return err;
1700                 device++;
1701         }
1702 
1703         chip->pcm_devs = device;
1704         return 0;
1705 }
1706         
1707 
1708 /*
1709  *  Mixer part
1710  */
1711 
1712 static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1713 {
1714         struct intel8x0 *chip = bus->private_data;
1715         chip->ac97_bus = NULL;
1716 }
1717 
1718 static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97)
1719 {
1720         struct intel8x0 *chip = ac97->private_data;
1721         chip->ac97[ac97->num] = NULL;
1722 }
1723 
1724 static const struct ac97_pcm ac97_pcm_defs[] = {
1725         /* front PCM */
1726         {
1727                 .exclusive = 1,
1728                 .r = {  {
1729                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1730                                          (1 << AC97_SLOT_PCM_RIGHT) |
1731                                          (1 << AC97_SLOT_PCM_CENTER) |
1732                                          (1 << AC97_SLOT_PCM_SLEFT) |
1733                                          (1 << AC97_SLOT_PCM_SRIGHT) |
1734                                          (1 << AC97_SLOT_LFE)
1735                         },
1736                         {
1737                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1738                                          (1 << AC97_SLOT_PCM_RIGHT) |
1739                                          (1 << AC97_SLOT_PCM_LEFT_0) |
1740                                          (1 << AC97_SLOT_PCM_RIGHT_0)
1741                         }
1742                 }
1743         },
1744         /* PCM IN #1 */
1745         {
1746                 .stream = 1,
1747                 .exclusive = 1,
1748                 .r = {  {
1749                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1750                                          (1 << AC97_SLOT_PCM_RIGHT)
1751                         }
1752                 }
1753         },
1754         /* MIC IN #1 */
1755         {
1756                 .stream = 1,
1757                 .exclusive = 1,
1758                 .r = {  {
1759                                 .slots = (1 << AC97_SLOT_MIC)
1760                         }
1761                 }
1762         },
1763         /* S/PDIF PCM */
1764         {
1765                 .exclusive = 1,
1766                 .spdif = 1,
1767                 .r = {  {
1768                                 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1769                                          (1 << AC97_SLOT_SPDIF_RIGHT2)
1770                         }
1771                 }
1772         },
1773         /* PCM IN #2 */
1774         {
1775                 .stream = 1,
1776                 .exclusive = 1,
1777                 .r = {  {
1778                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1779                                          (1 << AC97_SLOT_PCM_RIGHT)
1780                         }
1781                 }
1782         },
1783         /* MIC IN #2 */
1784         {
1785                 .stream = 1,
1786                 .exclusive = 1,
1787                 .r = {  {
1788                                 .slots = (1 << AC97_SLOT_MIC)
1789                         }
1790                 }
1791         },
1792 };
1793 
1794 static const struct ac97_quirk ac97_quirks[] = {
1795         {
1796                 .subvendor = 0x0e11,
1797                 .subdevice = 0x000e,
1798                 .name = "Compaq Deskpro EN",    /* AD1885 */
1799                 .type = AC97_TUNE_HP_ONLY
1800         },
1801         {
1802                 .subvendor = 0x0e11,
1803                 .subdevice = 0x008a,
1804                 .name = "Compaq Evo W4000",     /* AD1885 */
1805                 .type = AC97_TUNE_HP_ONLY
1806         },
1807         {
1808                 .subvendor = 0x0e11,
1809                 .subdevice = 0x00b8,
1810                 .name = "Compaq Evo D510C",
1811                 .type = AC97_TUNE_HP_ONLY
1812         },
1813         {
1814                 .subvendor = 0x0e11,
1815                 .subdevice = 0x0860,
1816                 .name = "HP/Compaq nx7010",
1817                 .type = AC97_TUNE_MUTE_LED
1818         },
1819         {
1820                 .subvendor = 0x1014,
1821                 .subdevice = 0x0534,
1822                 .name = "ThinkPad X31",
1823                 .type = AC97_TUNE_INV_EAPD
1824         },
1825         {
1826                 .subvendor = 0x1014,
1827                 .subdevice = 0x1f00,
1828                 .name = "MS-9128",
1829                 .type = AC97_TUNE_ALC_JACK
1830         },
1831         {
1832                 .subvendor = 0x1014,
1833                 .subdevice = 0x0267,
1834                 .name = "IBM NetVista A30p",    /* AD1981B */
1835                 .type = AC97_TUNE_HP_ONLY
1836         },
1837         {
1838                 .subvendor = 0x1025,
1839                 .subdevice = 0x0082,
1840                 .name = "Acer Travelmate 2310",
1841                 .type = AC97_TUNE_HP_ONLY
1842         },
1843         {
1844                 .subvendor = 0x1025,
1845                 .subdevice = 0x0083,
1846                 .name = "Acer Aspire 3003LCi",
1847                 .type = AC97_TUNE_HP_ONLY
1848         },
1849         {
1850                 .subvendor = 0x1028,
1851                 .subdevice = 0x00d8,
1852                 .name = "Dell Precision 530",   /* AD1885 */
1853                 .type = AC97_TUNE_HP_ONLY
1854         },
1855         {
1856                 .subvendor = 0x1028,
1857                 .subdevice = 0x010d,
1858                 .name = "Dell", /* which model?  AD1885 */
1859                 .type = AC97_TUNE_HP_ONLY
1860         },
1861         {
1862                 .subvendor = 0x1028,
1863                 .subdevice = 0x0126,
1864                 .name = "Dell Optiplex GX260",  /* AD1981A */
1865                 .type = AC97_TUNE_HP_ONLY
1866         },
1867         {
1868                 .subvendor = 0x1028,
1869                 .subdevice = 0x012c,
1870                 .name = "Dell Precision 650",   /* AD1981A */
1871                 .type = AC97_TUNE_HP_ONLY
1872         },
1873         {
1874                 .subvendor = 0x1028,
1875                 .subdevice = 0x012d,
1876                 .name = "Dell Precision 450",   /* AD1981B*/
1877                 .type = AC97_TUNE_HP_ONLY
1878         },
1879         {
1880                 .subvendor = 0x1028,
1881                 .subdevice = 0x0147,
1882                 .name = "Dell", /* which model?  AD1981B*/
1883                 .type = AC97_TUNE_HP_ONLY
1884         },
1885         {
1886                 .subvendor = 0x1028,
1887                 .subdevice = 0x0151,
1888                 .name = "Dell Optiplex GX270",  /* AD1981B */
1889                 .type = AC97_TUNE_HP_ONLY
1890         },
1891         {
1892                 .subvendor = 0x1028,
1893                 .subdevice = 0x014e,
1894                 .name = "Dell D800", /* STAC9750/51 */
1895                 .type = AC97_TUNE_HP_ONLY
1896         },
1897         {
1898                 .subvendor = 0x1028,
1899                 .subdevice = 0x0163,
1900                 .name = "Dell Unknown", /* STAC9750/51 */
1901                 .type = AC97_TUNE_HP_ONLY
1902         },
1903         {
1904                 .subvendor = 0x1028,
1905                 .subdevice = 0x016a,
1906                 .name = "Dell Inspiron 8600",   /* STAC9750/51 */
1907                 .type = AC97_TUNE_HP_ONLY
1908         },
1909         {
1910                 .subvendor = 0x1028,
1911                 .subdevice = 0x0182,
1912                 .name = "Dell Latitude D610",   /* STAC9750/51 */
1913                 .type = AC97_TUNE_HP_ONLY
1914         },
1915         {
1916                 .subvendor = 0x1028,
1917                 .subdevice = 0x0186,
1918                 .name = "Dell Latitude D810", /* cf. Malone #41015 */
1919                 .type = AC97_TUNE_HP_MUTE_LED
1920         },
1921         {
1922                 .subvendor = 0x1028,
1923                 .subdevice = 0x0188,
1924                 .name = "Dell Inspiron 6000",
1925                 .type = AC97_TUNE_HP_MUTE_LED /* cf. Malone #41015 */
1926         },
1927         {
1928                 .subvendor = 0x1028,
1929                 .subdevice = 0x0189,
1930                 .name = "Dell Inspiron 9300",
1931                 .type = AC97_TUNE_HP_MUTE_LED
1932         },
1933         {
1934                 .subvendor = 0x1028,
1935                 .subdevice = 0x0191,
1936                 .name = "Dell Inspiron 8600",
1937                 .type = AC97_TUNE_HP_ONLY
1938         },
1939         {
1940                 .subvendor = 0x103c,
1941                 .subdevice = 0x006d,
1942                 .name = "HP zv5000",
1943                 .type = AC97_TUNE_MUTE_LED      /*AD1981B*/
1944         },
1945         {       /* FIXME: which codec? */
1946                 .subvendor = 0x103c,
1947                 .subdevice = 0x00c3,
1948                 .name = "HP xw6000",
1949                 .type = AC97_TUNE_HP_ONLY
1950         },
1951         {
1952                 .subvendor = 0x103c,
1953                 .subdevice = 0x088c,
1954                 .name = "HP nc8000",
1955                 .type = AC97_TUNE_HP_MUTE_LED
1956         },
1957         {
1958                 .subvendor = 0x103c,
1959                 .subdevice = 0x0890,
1960                 .name = "HP nc6000",
1961                 .type = AC97_TUNE_MUTE_LED
1962         },
1963         {
1964                 .subvendor = 0x103c,
1965                 .subdevice = 0x129d,
1966                 .name = "HP xw8000",
1967                 .type = AC97_TUNE_HP_ONLY
1968         },
1969         {
1970                 .subvendor = 0x103c,
1971                 .subdevice = 0x0938,
1972                 .name = "HP nc4200",
1973                 .type = AC97_TUNE_HP_MUTE_LED
1974         },
1975         {
1976                 .subvendor = 0x103c,
1977                 .subdevice = 0x099c,
1978                 .name = "HP nx6110/nc6120",
1979                 .type = AC97_TUNE_HP_MUTE_LED
1980         },
1981         {
1982                 .subvendor = 0x103c,
1983                 .subdevice = 0x0944,
1984                 .name = "HP nc6220",
1985                 .type = AC97_TUNE_HP_MUTE_LED
1986         },
1987         {
1988                 .subvendor = 0x103c,
1989                 .subdevice = 0x0934,
1990                 .name = "HP nc8220",
1991                 .type = AC97_TUNE_HP_MUTE_LED
1992         },
1993         {
1994                 .subvendor = 0x103c,
1995                 .subdevice = 0x12f1,
1996                 .name = "HP xw8200",    /* AD1981B*/
1997                 .type = AC97_TUNE_HP_ONLY
1998         },
1999         {
2000                 .subvendor = 0x103c,
2001                 .subdevice = 0x12f2,
2002                 .name = "HP xw6200",
2003                 .type = AC97_TUNE_HP_ONLY
2004         },
2005         {
2006                 .subvendor = 0x103c,
2007                 .subdevice = 0x3008,
2008                 .name = "HP xw4200",    /* AD1981B*/
2009                 .type = AC97_TUNE_HP_ONLY
2010         },
2011         {
2012                 .subvendor = 0x104d,
2013                 .subdevice = 0x8144,
2014                 .name = "Sony",
2015                 .type = AC97_TUNE_INV_EAPD
2016         },
2017         {
2018                 .subvendor = 0x104d,
2019                 .subdevice = 0x8197,
2020                 .name = "Sony S1XP",
2021                 .type = AC97_TUNE_INV_EAPD
2022         },
2023         {
2024                 .subvendor = 0x104d,
2025                 .subdevice = 0x81c0,
2026                 .name = "Sony VAIO VGN-T350P", /*AD1981B*/
2027                 .type = AC97_TUNE_INV_EAPD
2028         },
2029         {
2030                 .subvendor = 0x104d,
2031                 .subdevice = 0x81c5,
2032                 .name = "Sony VAIO VGN-B1VP", /*AD1981B*/
2033                 .type = AC97_TUNE_INV_EAPD
2034         },
2035         {
2036                 .subvendor = 0x1043,
2037                 .subdevice = 0x80f3,
2038                 .name = "ASUS ICH5/AD1985",
2039                 .type = AC97_TUNE_AD_SHARING
2040         },
2041         {
2042                 .subvendor = 0x10cf,
2043                 .subdevice = 0x11c3,
2044                 .name = "Fujitsu-Siemens E4010",
2045                 .type = AC97_TUNE_HP_ONLY
2046         },
2047         {
2048                 .subvendor = 0x10cf,
2049                 .subdevice = 0x1225,
2050                 .name = "Fujitsu-Siemens T3010",
2051                 .type = AC97_TUNE_HP_ONLY
2052         },
2053         {
2054                 .subvendor = 0x10cf,
2055                 .subdevice = 0x1253,
2056                 .name = "Fujitsu S6210",        /* STAC9750/51 */
2057                 .type = AC97_TUNE_HP_ONLY
2058         },
2059         {
2060                 .subvendor = 0x10cf,
2061                 .subdevice = 0x127d,
2062                 .name = "Fujitsu Lifebook P7010",
2063                 .type = AC97_TUNE_HP_ONLY
2064         },
2065         {
2066                 .subvendor = 0x10cf,
2067                 .subdevice = 0x127e,
2068                 .name = "Fujitsu Lifebook C1211D",
2069                 .type = AC97_TUNE_HP_ONLY
2070         },
2071         {
2072                 .subvendor = 0x10cf,
2073                 .subdevice = 0x12ec,
2074                 .name = "Fujitsu-Siemens 4010",
2075                 .type = AC97_TUNE_HP_ONLY
2076         },
2077         {
2078                 .subvendor = 0x10cf,
2079                 .subdevice = 0x12f2,
2080                 .name = "Fujitsu-Siemens Celsius H320",
2081                 .type = AC97_TUNE_SWAP_HP
2082         },
2083         {
2084                 .subvendor = 0x10f1,
2085                 .subdevice = 0x2665,
2086                 .name = "Fujitsu-Siemens Celsius",      /* AD1981? */
2087                 .type = AC97_TUNE_HP_ONLY
2088         },
2089         {
2090                 .subvendor = 0x10f1,
2091                 .subdevice = 0x2885,
2092                 .name = "AMD64 Mobo",   /* ALC650 */
2093                 .type = AC97_TUNE_HP_ONLY
2094         },
2095         {
2096                 .subvendor = 0x10f1,
2097                 .subdevice = 0x2895,
2098                 .name = "Tyan Thunder K8WE",
2099                 .type = AC97_TUNE_HP_ONLY
2100         },
2101         {
2102                 .subvendor = 0x10f7,
2103                 .subdevice = 0x834c,
2104                 .name = "Panasonic CF-R4",
2105                 .type = AC97_TUNE_HP_ONLY,
2106         },
2107         {
2108                 .subvendor = 0x110a,
2109                 .subdevice = 0x0056,
2110                 .name = "Fujitsu-Siemens Scenic",       /* AD1981? */
2111                 .type = AC97_TUNE_HP_ONLY
2112         },
2113         {
2114                 .subvendor = 0x11d4,
2115                 .subdevice = 0x5375,
2116                 .name = "ADI AD1985 (discrete)",
2117                 .type = AC97_TUNE_HP_ONLY
2118         },
2119         {
2120                 .subvendor = 0x1462,
2121                 .subdevice = 0x5470,
2122                 .name = "MSI P4 ATX 645 Ultra",
2123                 .type = AC97_TUNE_HP_ONLY
2124         },
2125         {
2126                 .subvendor = 0x161f,
2127                 .subdevice = 0x202f,
2128                 .name = "Gateway M520",
2129                 .type = AC97_TUNE_INV_EAPD
2130         },
2131         {
2132                 .subvendor = 0x161f,
2133                 .subdevice = 0x203a,
2134                 .name = "Gateway 4525GZ",               /* AD1981B */
2135                 .type = AC97_TUNE_INV_EAPD
2136         },
2137         {
2138                 .subvendor = 0x1734,
2139                 .subdevice = 0x0088,
2140                 .name = "Fujitsu-Siemens D1522",        /* AD1981 */
2141                 .type = AC97_TUNE_HP_ONLY
2142         },
2143         {
2144                 .subvendor = 0x8086,
2145                 .subdevice = 0x2000,
2146                 .mask = 0xfff0,
2147                 .name = "Intel ICH5/AD1985",
2148                 .type = AC97_TUNE_AD_SHARING
2149         },
2150         {
2151                 .subvendor = 0x8086,
2152                 .subdevice = 0x4000,
2153                 .mask = 0xfff0,
2154                 .name = "Intel ICH5/AD1985",
2155                 .type = AC97_TUNE_AD_SHARING
2156         },
2157         {
2158                 .subvendor = 0x8086,
2159                 .subdevice = 0x4856,
2160                 .name = "Intel D845WN (82801BA)",
2161                 .type = AC97_TUNE_SWAP_HP
2162         },
2163         {
2164                 .subvendor = 0x8086,
2165                 .subdevice = 0x4d44,
2166                 .name = "Intel D850EMV2",       /* AD1885 */
2167                 .type = AC97_TUNE_HP_ONLY
2168         },
2169         {
2170                 .subvendor = 0x8086,
2171                 .subdevice = 0x4d56,
2172                 .name = "Intel ICH/AD1885",
2173                 .type = AC97_TUNE_HP_ONLY
2174         },
2175         {
2176                 .subvendor = 0x8086,
2177                 .subdevice = 0x6000,
2178                 .mask = 0xfff0,
2179                 .name = "Intel ICH5/AD1985",
2180                 .type = AC97_TUNE_AD_SHARING
2181         },
2182         {
2183                 .subvendor = 0x8086,
2184                 .subdevice = 0xe000,
2185                 .mask = 0xfff0,
2186                 .name = "Intel ICH5/AD1985",
2187                 .type = AC97_TUNE_AD_SHARING
2188         },
2189 #if 0 /* FIXME: this seems wrong on most boards */
2190         {
2191                 .subvendor = 0x8086,
2192                 .subdevice = 0xa000,
2193                 .mask = 0xfff0,
2194                 .name = "Intel ICH5/AD1985",
2195                 .type = AC97_TUNE_HP_ONLY
2196         },
2197 #endif
2198         { } /* terminator */
2199 };
2200 
2201 static int snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock,
2202                               const char *quirk_override)
2203 {
2204         struct snd_ac97_bus *pbus;
2205         struct snd_ac97_template ac97;
2206         int err;
2207         unsigned int i, codecs;
2208         unsigned int glob_sta = 0;
2209         struct snd_ac97_bus_ops *ops;
2210         static struct snd_ac97_bus_ops standard_bus_ops = {
2211                 .write = snd_intel8x0_codec_write,
2212                 .read = snd_intel8x0_codec_read,
2213         };
2214         static struct snd_ac97_bus_ops ali_bus_ops = {
2215                 .write = snd_intel8x0_ali_codec_write,
2216                 .read = snd_intel8x0_ali_codec_read,
2217         };
2218 
2219         chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
2220         if (!spdif_aclink) {
2221                 switch (chip->device_type) {
2222                 case DEVICE_NFORCE:
2223                         chip->spdif_idx = NVD_SPBAR;
2224                         break;
2225                 case DEVICE_ALI:
2226                         chip->spdif_idx = ALID_AC97SPDIFOUT;
2227                         break;
2228                 case DEVICE_INTEL_ICH4:
2229                         chip->spdif_idx = ICHD_SPBAR;
2230                         break;
2231                 }
2232         }
2233 
2234         chip->in_ac97_init = 1;
2235         
2236         memset(&ac97, 0, sizeof(ac97));
2237         ac97.private_data = chip;
2238         ac97.private_free = snd_intel8x0_mixer_free_ac97;
2239         ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE;
2240         if (chip->xbox)
2241                 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
2242         if (chip->device_type != DEVICE_ALI) {
2243                 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
2244                 ops = &standard_bus_ops;
2245                 chip->in_sdin_init = 1;
2246                 codecs = 0;
2247                 for (i = 0; i < chip->max_codecs; i++) {
2248                         if (! (glob_sta & chip->codec_bit[i]))
2249                                 continue;
2250                         if (chip->device_type == DEVICE_INTEL_ICH4) {
2251                                 snd_intel8x0_codec_read_test(chip, codecs);
2252                                 chip->ac97_sdin[codecs] =
2253                                         igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
2254                                 if (snd_BUG_ON(chip->ac97_sdin[codecs] >= 3))
2255                                         chip->ac97_sdin[codecs] = 0;
2256                         } else
2257                                 chip->ac97_sdin[codecs] = i;
2258                         codecs++;
2259                 }
2260                 chip->in_sdin_init = 0;
2261                 if (! codecs)
2262                         codecs = 1;
2263         } else {
2264                 ops = &ali_bus_ops;
2265                 codecs = 1;
2266                 /* detect the secondary codec */
2267                 for (i = 0; i < 100; i++) {
2268                         unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
2269                         if (reg & 0x40) {
2270                                 codecs = 2;
2271                                 break;
2272                         }
2273                         iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2274                         udelay(1);
2275                 }
2276         }
2277         if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
2278                 goto __err;
2279         pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
2280         if (ac97_clock >= 8000 && ac97_clock <= 48000)
2281                 pbus->clock = ac97_clock;
2282         /* FIXME: my test board doesn't work well with VRA... */
2283         if (chip->device_type == DEVICE_ALI)
2284                 pbus->no_vra = 1;
2285         else
2286                 pbus->dra = 1;
2287         chip->ac97_bus = pbus;
2288         chip->ncodecs = codecs;
2289 
2290         ac97.pci = chip->pci;
2291         for (i = 0; i < codecs; i++) {
2292                 ac97.num = i;
2293                 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
2294                         if (err != -EACCES)
2295                                 dev_err(chip->card->dev,
2296                                         "Unable to initialize codec #%d\n", i);
2297                         if (i == 0)
2298                                 goto __err;
2299                 }
2300         }
2301         /* tune up the primary codec */
2302         snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
2303         /* enable separate SDINs for ICH4 */
2304         if (chip->device_type == DEVICE_INTEL_ICH4)
2305                 pbus->isdin = 1;
2306         /* find the available PCM streams */
2307         i = ARRAY_SIZE(ac97_pcm_defs);
2308         if (chip->device_type != DEVICE_INTEL_ICH4)
2309                 i -= 2;         /* do not allocate PCM2IN and MIC2 */
2310         if (chip->spdif_idx < 0)
2311                 i--;            /* do not allocate S/PDIF */
2312         err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2313         if (err < 0)
2314                 goto __err;
2315         chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2316         chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2317         chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2318         if (chip->spdif_idx >= 0)
2319                 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2320         if (chip->device_type == DEVICE_INTEL_ICH4) {
2321                 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2322                 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2323         }
2324         /* enable separate SDINs for ICH4 */
2325         if (chip->device_type == DEVICE_INTEL_ICH4) {
2326                 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2327                 u8 tmp = igetbyte(chip, ICHREG(SDM));
2328                 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2329                 if (pcm) {
2330                         tmp |= ICH_SE;  /* steer enable for multiple SDINs */
2331                         tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2332                         for (i = 1; i < 4; i++) {
2333                                 if (pcm->r[0].codec[i]) {
2334                                         tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2335                                         break;
2336                                 }
2337                         }
2338                 } else {
2339                         tmp &= ~ICH_SE; /* steer disable */
2340                 }
2341                 iputbyte(chip, ICHREG(SDM), tmp);
2342         }
2343         if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2344                 chip->multi4 = 1;
2345                 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE)) {
2346                         chip->multi6 = 1;
2347                         if (chip->ac97[0]->flags & AC97_HAS_8CH)
2348                                 chip->multi8 = 1;
2349                 }
2350         }
2351         if (pbus->pcms[0].r[1].rslots[0]) {
2352                 chip->dra = 1;
2353         }
2354         if (chip->device_type == DEVICE_INTEL_ICH4) {
2355                 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2356                         chip->smp20bit = 1;
2357         }
2358         if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2359                 /* 48kHz only */
2360                 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2361         }
2362         if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2363                 /* use slot 10/11 for SPDIF */
2364                 u32 val;
2365                 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2366                 val |= ICH_PCM_SPDIF_1011;
2367                 iputdword(chip, ICHREG(GLOB_CNT), val);
2368                 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2369         }
2370         chip->in_ac97_init = 0;
2371         return 0;
2372 
2373  __err:
2374         /* clear the cold-reset bit for the next chance */
2375         if (chip->device_type != DEVICE_ALI)
2376                 iputdword(chip, ICHREG(GLOB_CNT),
2377                           igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2378         return err;
2379 }
2380 
2381 
2382 /*
2383  *
2384  */
2385 
2386 static void do_ali_reset(struct intel8x0 *chip)
2387 {
2388         iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2389         iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2390         iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2391         iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2392         iputdword(chip, ICHREG(ALI_INTERFACECR),
2393                   ICH_ALI_IF_PI|ICH_ALI_IF_PO);
2394         iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2395         iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2396 }
2397 
2398 #ifdef CONFIG_SND_AC97_POWER_SAVE
2399 static struct snd_pci_quirk ich_chip_reset_mode[] = {
2400         SND_PCI_QUIRK(0x1014, 0x051f, "Thinkpad R32", 1),
2401         { } /* end */
2402 };
2403 
2404 static int snd_intel8x0_ich_chip_cold_reset(struct intel8x0 *chip)
2405 {
2406         unsigned int cnt;
2407         /* ACLink on, 2 channels */
2408 
2409         if (snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
2410                 return -EIO;
2411 
2412         cnt = igetdword(chip, ICHREG(GLOB_CNT));
2413         cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2414 
2415         /* do cold reset - the full ac97 powerdown may leave the controller
2416          * in a warm state but actually it cannot communicate with the codec.
2417          */
2418         iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD);
2419         cnt = igetdword(chip, ICHREG(GLOB_CNT));
2420         udelay(10);
2421         iputdword(chip, ICHREG(GLOB_CNT), cnt | ICH_AC97COLD);
2422         msleep(1);
2423         return 0;
2424 }
2425 #define snd_intel8x0_ich_chip_can_cold_reset(chip) \
2426         (!snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
2427 #else
2428 #define snd_intel8x0_ich_chip_cold_reset(chip)  0
2429 #define snd_intel8x0_ich_chip_can_cold_reset(chip) (0)
2430 #endif
2431 
2432 static int snd_intel8x0_ich_chip_reset(struct intel8x0 *chip)
2433 {
2434         unsigned long end_time;
2435         unsigned int cnt;
2436         /* ACLink on, 2 channels */
2437         cnt = igetdword(chip, ICHREG(GLOB_CNT));
2438         cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2439         /* finish cold or do warm reset */
2440         cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2441         iputdword(chip, ICHREG(GLOB_CNT), cnt);
2442         end_time = (jiffies + (HZ / 4)) + 1;
2443         do {
2444                 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
2445                         return 0;
2446                 schedule_timeout_uninterruptible(1);
2447         } while (time_after_eq(end_time, jiffies));
2448         dev_err(chip->card->dev, "AC'97 warm reset still in progress? [0x%x]\n",
2449                    igetdword(chip, ICHREG(GLOB_CNT)));
2450         return -EIO;
2451 }
2452 
2453 static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing)
2454 {
2455         unsigned long end_time;
2456         unsigned int status, nstatus;
2457         unsigned int cnt;
2458         int err;
2459 
2460         /* put logic to right state */
2461         /* first clear status bits */
2462         status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2463         if (chip->device_type == DEVICE_NFORCE)
2464                 status |= ICH_NVSPINT;
2465         cnt = igetdword(chip, ICHREG(GLOB_STA));
2466         iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2467 
2468         if (snd_intel8x0_ich_chip_can_cold_reset(chip))
2469                 err = snd_intel8x0_ich_chip_cold_reset(chip);
2470         else
2471                 err = snd_intel8x0_ich_chip_reset(chip);
2472         if (err < 0)
2473                 return err;
2474 
2475         if (probing) {
2476                 /* wait for any codec ready status.
2477                  * Once it becomes ready it should remain ready
2478                  * as long as we do not disable the ac97 link.
2479                  */
2480                 end_time = jiffies + HZ;
2481                 do {
2482                         status = igetdword(chip, ICHREG(GLOB_STA)) &
2483                                 chip->codec_isr_bits;
2484                         if (status)
2485                                 break;
2486                         schedule_timeout_uninterruptible(1);
2487                 } while (time_after_eq(end_time, jiffies));
2488                 if (! status) {
2489                         /* no codec is found */
2490                         dev_err(chip->card->dev,
2491                                 "codec_ready: codec is not ready [0x%x]\n",
2492                                    igetdword(chip, ICHREG(GLOB_STA)));
2493                         return -EIO;
2494                 }
2495 
2496                 /* wait for other codecs ready status. */
2497                 end_time = jiffies + HZ / 4;
2498                 while (status != chip->codec_isr_bits &&
2499                        time_after_eq(end_time, jiffies)) {
2500                         schedule_timeout_uninterruptible(1);
2501                         status |= igetdword(chip, ICHREG(GLOB_STA)) &
2502                                 chip->codec_isr_bits;
2503                 }
2504 
2505         } else {
2506                 /* resume phase */
2507                 int i;
2508                 status = 0;
2509                 for (i = 0; i < chip->ncodecs; i++)
2510                         if (chip->ac97[i])
2511                                 status |= chip->codec_bit[chip->ac97_sdin[i]];
2512                 /* wait until all the probed codecs are ready */
2513                 end_time = jiffies + HZ;
2514                 do {
2515                         nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
2516                                 chip->codec_isr_bits;
2517                         if (status == nstatus)
2518                                 break;
2519                         schedule_timeout_uninterruptible(1);
2520                 } while (time_after_eq(end_time, jiffies));
2521         }
2522 
2523         if (chip->device_type == DEVICE_SIS) {
2524                 /* unmute the output on SIS7012 */
2525                 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2526         }
2527         if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2528                 /* enable SPDIF interrupt */
2529                 unsigned int val;
2530                 pci_read_config_dword(chip->pci, 0x4c, &val);
2531                 val |= 0x1000000;
2532                 pci_write_config_dword(chip->pci, 0x4c, val);
2533         }
2534         return 0;
2535 }
2536 
2537 static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing)
2538 {
2539         u32 reg;
2540         int i = 0;
2541 
2542         reg = igetdword(chip, ICHREG(ALI_SCR));
2543         if ((reg & 2) == 0)     /* Cold required */
2544                 reg |= 2;
2545         else
2546                 reg |= 1;       /* Warm */
2547         reg &= ~0x80000000;     /* ACLink on */
2548         iputdword(chip, ICHREG(ALI_SCR), reg);
2549 
2550         for (i = 0; i < HZ / 2; i++) {
2551                 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2552                         goto __ok;
2553                 schedule_timeout_uninterruptible(1);
2554         }
2555         dev_err(chip->card->dev, "AC'97 reset failed.\n");
2556         if (probing)
2557                 return -EIO;
2558 
2559  __ok:
2560         for (i = 0; i < HZ / 2; i++) {
2561                 reg = igetdword(chip, ICHREG(ALI_RTSR));
2562                 if (reg & 0x80) /* primary codec */
2563                         break;
2564                 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2565                 schedule_timeout_uninterruptible(1);
2566         }
2567 
2568         do_ali_reset(chip);
2569         return 0;
2570 }
2571 
2572 static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing)
2573 {
2574         unsigned int i, timeout;
2575         int err;
2576         
2577         if (chip->device_type != DEVICE_ALI) {
2578                 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2579                         return err;
2580                 iagetword(chip, 0);     /* clear semaphore flag */
2581         } else {
2582                 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2583                         return err;
2584         }
2585 
2586         /* disable interrupts */
2587         for (i = 0; i < chip->bdbars_count; i++)
2588                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2589         /* reset channels */
2590         for (i = 0; i < chip->bdbars_count; i++)
2591                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2592         for (i = 0; i < chip->bdbars_count; i++) {
2593                 timeout = 100000;
2594                 while (--timeout != 0) {
2595                         if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0)
2596                                 break;
2597                 }
2598                 if (timeout == 0)
2599                         dev_err(chip->card->dev, "reset of registers failed?\n");
2600         }
2601         /* initialize Buffer Descriptor Lists */
2602         for (i = 0; i < chip->bdbars_count; i++)
2603                 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset,
2604                           chip->ichd[i].bdbar_addr);
2605         return 0;
2606 }
2607 
2608 static int snd_intel8x0_free(struct intel8x0 *chip)
2609 {
2610         unsigned int i;
2611 
2612         if (chip->irq < 0)
2613                 goto __hw_end;
2614         /* disable interrupts */
2615         for (i = 0; i < chip->bdbars_count; i++)
2616                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2617         /* reset channels */
2618         for (i = 0; i < chip->bdbars_count; i++)
2619                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2620         if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2621                 /* stop the spdif interrupt */
2622                 unsigned int val;
2623                 pci_read_config_dword(chip->pci, 0x4c, &val);
2624                 val &= ~0x1000000;
2625                 pci_write_config_dword(chip->pci, 0x4c, val);
2626         }
2627         /* --- */
2628 
2629       __hw_end:
2630         if (chip->irq >= 0)
2631                 free_irq(chip->irq, chip);
2632         if (chip->bdbars.area) {
2633                 if (chip->fix_nocache)
2634                         fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0);
2635                 snd_dma_free_pages(&chip->bdbars);
2636         }
2637         if (chip->addr)
2638                 pci_iounmap(chip->pci, chip->addr);
2639         if (chip->bmaddr)
2640                 pci_iounmap(chip->pci, chip->bmaddr);
2641         pci_release_regions(chip->pci);
2642         pci_disable_device(chip->pci);
2643         kfree(chip);
2644         return 0;
2645 }
2646 
2647 #ifdef CONFIG_PM_SLEEP
2648 /*
2649  * power management
2650  */
2651 static int intel8x0_suspend(struct device *dev)
2652 {
2653         struct snd_card *card = dev_get_drvdata(dev);
2654         struct intel8x0 *chip = card->private_data;
2655         int i;
2656 
2657         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2658         for (i = 0; i < chip->pcm_devs; i++)
2659                 snd_pcm_suspend_all(chip->pcm[i]);
2660         /* clear nocache */
2661         if (chip->fix_nocache) {
2662                 for (i = 0; i < chip->bdbars_count; i++) {
2663                         struct ichdev *ichdev = &chip->ichd[i];
2664                         if (ichdev->substream && ichdev->page_attr_changed) {
2665                                 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
2666                                 if (runtime->dma_area)
2667                                         fill_nocache(runtime->dma_area, runtime->dma_bytes, 0);
2668                         }
2669                 }
2670         }
2671         for (i = 0; i < chip->ncodecs; i++)
2672                 snd_ac97_suspend(chip->ac97[i]);
2673         if (chip->device_type == DEVICE_INTEL_ICH4)
2674                 chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
2675 
2676         if (chip->irq >= 0) {
2677                 free_irq(chip->irq, chip);
2678                 chip->irq = -1;
2679         }
2680         return 0;
2681 }
2682 
2683 static int intel8x0_resume(struct device *dev)
2684 {
2685         struct pci_dev *pci = to_pci_dev(dev);
2686         struct snd_card *card = dev_get_drvdata(dev);
2687         struct intel8x0 *chip = card->private_data;
2688         int i;
2689 
2690         snd_intel8x0_chip_init(chip, 0);
2691         if (request_irq(pci->irq, snd_intel8x0_interrupt,
2692                         IRQF_SHARED, KBUILD_MODNAME, chip)) {
2693                 dev_err(dev, "unable to grab IRQ %d, disabling device\n",
2694                         pci->irq);
2695                 snd_card_disconnect(card);
2696                 return -EIO;
2697         }
2698         chip->irq = pci->irq;
2699         synchronize_irq(chip->irq);
2700 
2701         /* re-initialize mixer stuff */
2702         if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2703                 /* enable separate SDINs for ICH4 */
2704                 iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
2705                 /* use slot 10/11 for SPDIF */
2706                 iputdword(chip, ICHREG(GLOB_CNT),
2707                           (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
2708                           ICH_PCM_SPDIF_1011);
2709         }
2710 
2711         /* refill nocache */
2712         if (chip->fix_nocache)
2713                 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2714 
2715         for (i = 0; i < chip->ncodecs; i++)
2716                 snd_ac97_resume(chip->ac97[i]);
2717 
2718         /* refill nocache */
2719         if (chip->fix_nocache) {
2720                 for (i = 0; i < chip->bdbars_count; i++) {
2721                         struct ichdev *ichdev = &chip->ichd[i];
2722                         if (ichdev->substream && ichdev->page_attr_changed) {
2723                                 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
2724                                 if (runtime->dma_area)
2725                                         fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
2726                         }
2727                 }
2728         }
2729 
2730         /* resume status */
2731         for (i = 0; i < chip->bdbars_count; i++) {
2732                 struct ichdev *ichdev = &chip->ichd[i];
2733                 unsigned long port = ichdev->reg_offset;
2734                 if (! ichdev->substream || ! ichdev->suspended)
2735                         continue;
2736                 if (ichdev->ichd == ICHD_PCMOUT)
2737                         snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
2738                 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
2739                 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
2740                 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
2741                 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
2742         }
2743 
2744         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2745         return 0;
2746 }
2747 
2748 static SIMPLE_DEV_PM_OPS(intel8x0_pm, intel8x0_suspend, intel8x0_resume);
2749 #define INTEL8X0_PM_OPS &intel8x0_pm
2750 #else
2751 #define INTEL8X0_PM_OPS NULL
2752 #endif /* CONFIG_PM_SLEEP */
2753 
2754 #define INTEL8X0_TESTBUF_SIZE   32768   /* enough large for one shot */
2755 
2756 static void intel8x0_measure_ac97_clock(struct intel8x0 *chip)
2757 {
2758         struct snd_pcm_substream *subs;
2759         struct ichdev *ichdev;
2760         unsigned long port;
2761         unsigned long pos, pos1, t;
2762         int civ, timeout = 1000, attempt = 1;
2763         ktime_t start_time, stop_time;
2764 
2765         if (chip->ac97_bus->clock != 48000)
2766                 return; /* specified in module option */
2767 
2768       __again:
2769         subs = chip->pcm[0]->streams[0].substream;
2770         if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2771                 dev_warn(chip->card->dev,
2772                          "no playback buffer allocated - aborting measure ac97 clock\n");
2773                 return;
2774         }
2775         ichdev = &chip->ichd[ICHD_PCMOUT];
2776         ichdev->physbuf = subs->dma_buffer.addr;
2777         ichdev->size = ichdev->fragsize = INTEL8X0_TESTBUF_SIZE;
2778         ichdev->substream = NULL; /* don't process interrupts */
2779 
2780         /* set rate */
2781         if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2782                 dev_err(chip->card->dev, "cannot set ac97 rate: clock = %d\n",
2783                         chip->ac97_bus->clock);
2784                 return;
2785         }
2786         snd_intel8x0_setup_periods(chip, ichdev);
2787         port = ichdev->reg_offset;
2788         spin_lock_irq(&chip->reg_lock);
2789         chip->in_measurement = 1;
2790         /* trigger */
2791         if (chip->device_type != DEVICE_ALI)
2792                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2793         else {
2794                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2795                 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2796         }
2797         start_time = ktime_get();
2798         spin_unlock_irq(&chip->reg_lock);
2799         msleep(50);
2800         spin_lock_irq(&chip->reg_lock);
2801         /* check the position */
2802         do {
2803                 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
2804                 pos1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
2805                 if (pos1 == 0) {
2806                         udelay(10);
2807                         continue;
2808                 }
2809                 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
2810                     pos1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
2811                         break;
2812         } while (timeout--);
2813         if (pos1 == 0) {        /* oops, this value is not reliable */
2814                 pos = 0;
2815         } else {
2816                 pos = ichdev->fragsize1;
2817                 pos -= pos1 << ichdev->pos_shift;
2818                 pos += ichdev->position;
2819         }
2820         chip->in_measurement = 0;
2821         stop_time = ktime_get();
2822         /* stop */
2823         if (chip->device_type == DEVICE_ALI) {
2824                 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16));
2825                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2826                 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2827                         ;
2828         } else {
2829                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2830                 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2831                         ;
2832         }
2833         iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2834         spin_unlock_irq(&chip->reg_lock);
2835 
2836         if (pos == 0) {
2837                 dev_err(chip->card->dev,
2838                         "measure - unreliable DMA position..\n");
2839               __retry:
2840                 if (attempt < 3) {
2841                         msleep(300);
2842                         attempt++;
2843                         goto __again;
2844                 }
2845                 goto __end;
2846         }
2847 
2848         pos /= 4;
2849         t = ktime_us_delta(stop_time, start_time);
2850         dev_info(chip->card->dev,
2851                  "%s: measured %lu usecs (%lu samples)\n", __func__, t, pos);
2852         if (t == 0) {
2853                 dev_err(chip->card->dev, "?? calculation error..\n");
2854                 goto __retry;
2855         }
2856         pos *= 1000;
2857         pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2858         if (pos < 40000 || pos >= 60000) {
2859                 /* abnormal value. hw problem? */
2860                 dev_info(chip->card->dev, "measured clock %ld rejected\n", pos);
2861                 goto __retry;
2862         } else if (pos > 40500 && pos < 41500)
2863                 /* first exception - 41000Hz reference clock */
2864                 chip->ac97_bus->clock = 41000;
2865         else if (pos > 43600 && pos < 44600)
2866                 /* second exception - 44100HZ reference clock */
2867                 chip->ac97_bus->clock = 44100;
2868         else if (pos < 47500 || pos > 48500)
2869                 /* not 48000Hz, tuning the clock.. */
2870                 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2871       __end:
2872         dev_info(chip->card->dev, "clocking to %d\n", chip->ac97_bus->clock);
2873         snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0);
2874 }
2875 
2876 static struct snd_pci_quirk intel8x0_clock_list[] = {
2877         SND_PCI_QUIRK(0x0e11, 0x008a, "AD1885", 41000),
2878         SND_PCI_QUIRK(0x1014, 0x0581, "AD1981B", 48000),
2879         SND_PCI_QUIRK(0x1028, 0x00be, "AD1885", 44100),
2880         SND_PCI_QUIRK(0x1028, 0x0177, "AD1980", 48000),
2881         SND_PCI_QUIRK(0x1028, 0x01ad, "AD1981B", 48000),
2882         SND_PCI_QUIRK(0x1043, 0x80f3, "AD1985", 48000),
2883         { }     /* terminator */
2884 };
2885 
2886 static int intel8x0_in_clock_list(struct intel8x0 *chip)
2887 {
2888         struct pci_dev *pci = chip->pci;
2889         const struct snd_pci_quirk *wl;
2890 
2891         wl = snd_pci_quirk_lookup(pci, intel8x0_clock_list);
2892         if (!wl)
2893                 return 0;
2894         dev_info(chip->card->dev, "white list rate for %04x:%04x is %i\n",
2895                pci->subsystem_vendor, pci->subsystem_device, wl->value);
2896         chip->ac97_bus->clock = wl->value;
2897         return 1;
2898 }
2899 
2900 static void snd_intel8x0_proc_read(struct snd_info_entry * entry,
2901                                    struct snd_info_buffer *buffer)
2902 {
2903         struct intel8x0 *chip = entry->private_data;
2904         unsigned int tmp;
2905 
2906         snd_iprintf(buffer, "Intel8x0\n\n");
2907         if (chip->device_type == DEVICE_ALI)
2908                 return;
2909         tmp = igetdword(chip, ICHREG(GLOB_STA));
2910         snd_iprintf(buffer, "Global control        : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2911         snd_iprintf(buffer, "Global status         : 0x%08x\n", tmp);
2912         if (chip->device_type == DEVICE_INTEL_ICH4)
2913                 snd_iprintf(buffer, "SDM                   : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2914         snd_iprintf(buffer, "AC'97 codecs ready    :");
2915         if (tmp & chip->codec_isr_bits) {
2916                 int i;
2917                 static const char *codecs[3] = {
2918                         "primary", "secondary", "tertiary"
2919                 };
2920                 for (i = 0; i < chip->max_codecs; i++)
2921                         if (tmp & chip->codec_bit[i])
2922                                 snd_iprintf(buffer, " %s", codecs[i]);
2923         } else
2924                 snd_iprintf(buffer, " none");
2925         snd_iprintf(buffer, "\n");
2926         if (chip->device_type == DEVICE_INTEL_ICH4 ||
2927             chip->device_type == DEVICE_SIS)
2928                 snd_iprintf(buffer, "AC'97 codecs SDIN     : %i %i %i\n",
2929                         chip->ac97_sdin[0],
2930                         chip->ac97_sdin[1],
2931                         chip->ac97_sdin[2]);
2932 }
2933 
2934 static void snd_intel8x0_proc_init(struct intel8x0 *chip)
2935 {
2936         struct snd_info_entry *entry;
2937 
2938         if (! snd_card_proc_new(chip->card, "intel8x0", &entry))
2939                 snd_info_set_text_ops(entry, chip, snd_intel8x0_proc_read);
2940 }
2941 
2942 static int snd_intel8x0_dev_free(struct snd_device *device)
2943 {
2944         struct intel8x0 *chip = device->device_data;
2945         return snd_intel8x0_free(chip);
2946 }
2947 
2948 struct ich_reg_info {
2949         unsigned int int_sta_mask;
2950         unsigned int offset;
2951 };
2952 
2953 static unsigned int ich_codec_bits[3] = {
2954         ICH_PCR, ICH_SCR, ICH_TCR
2955 };
2956 static unsigned int sis_codec_bits[3] = {
2957         ICH_PCR, ICH_SCR, ICH_SIS_TCR
2958 };
2959 
2960 static int snd_intel8x0_inside_vm(struct pci_dev *pci)
2961 {
2962         int result  = inside_vm;
2963         char *msg   = NULL;
2964 
2965         /* check module parameter first (override detection) */
2966         if (result >= 0) {
2967                 msg = result ? "enable (forced) VM" : "disable (forced) VM";
2968                 goto fini;
2969         }
2970 
2971         /* check for known (emulated) devices */
2972         result = 0;
2973         if (pci->subsystem_vendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
2974             pci->subsystem_device == PCI_SUBDEVICE_ID_QEMU) {
2975                 /* KVM emulated sound, PCI SSID: 1af4:1100 */
2976                 msg = "enable KVM";
2977                 result = 1;
2978         } else if (pci->subsystem_vendor == 0x1ab8) {
2979                 /* Parallels VM emulated sound, PCI SSID: 1ab8:xxxx */
2980                 msg = "enable Parallels VM";
2981                 result = 1;
2982         }
2983 
2984 fini:
2985         if (msg != NULL)
2986                 dev_info(&pci->dev, "%s optimization\n", msg);
2987 
2988         return result;
2989 }
2990 
2991 static int snd_intel8x0_create(struct snd_card *card,
2992                                struct pci_dev *pci,
2993                                unsigned long device_type,
2994                                struct intel8x0 **r_intel8x0)
2995 {
2996         struct intel8x0 *chip;
2997         int err;
2998         unsigned int i;
2999         unsigned int int_sta_masks;
3000         struct ichdev *ichdev;
3001         static struct snd_device_ops ops = {
3002                 .dev_free =     snd_intel8x0_dev_free,
3003         };
3004 
3005         static unsigned int bdbars[] = {
3006                 3, /* DEVICE_INTEL */
3007                 6, /* DEVICE_INTEL_ICH4 */
3008                 3, /* DEVICE_SIS */
3009                 6, /* DEVICE_ALI */
3010                 4, /* DEVICE_NFORCE */
3011         };
3012         static struct ich_reg_info intel_regs[6] = {
3013                 { ICH_PIINT, 0 },
3014                 { ICH_POINT, 0x10 },
3015                 { ICH_MCINT, 0x20 },
3016                 { ICH_M2INT, 0x40 },
3017                 { ICH_P2INT, 0x50 },
3018                 { ICH_SPINT, 0x60 },
3019         };
3020         static struct ich_reg_info nforce_regs[4] = {
3021                 { ICH_PIINT, 0 },
3022                 { ICH_POINT, 0x10 },
3023                 { ICH_MCINT, 0x20 },
3024                 { ICH_NVSPINT, 0x70 },
3025         };
3026         static struct ich_reg_info ali_regs[6] = {
3027                 { ALI_INT_PCMIN, 0x40 },
3028                 { ALI_INT_PCMOUT, 0x50 },
3029                 { ALI_INT_MICIN, 0x60 },
3030                 { ALI_INT_CODECSPDIFOUT, 0x70 },
3031                 { ALI_INT_SPDIFIN, 0xa0 },
3032                 { ALI_INT_SPDIFOUT, 0xb0 },
3033         };
3034         struct ich_reg_info *tbl;
3035 
3036         *r_intel8x0 = NULL;
3037 
3038         if ((err = pci_enable_device(pci)) < 0)
3039                 return err;
3040 
3041         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
3042         if (chip == NULL) {
3043                 pci_disable_device(pci);
3044                 return -ENOMEM;
3045         }
3046         spin_lock_init(&chip->reg_lock);
3047         chip->device_type = device_type;
3048         chip->card = card;
3049         chip->pci = pci;
3050         chip->irq = -1;
3051 
3052         /* module parameters */
3053         chip->buggy_irq = buggy_irq;
3054         chip->buggy_semaphore = buggy_semaphore;
3055         if (xbox)
3056                 chip->xbox = 1;
3057 
3058         chip->inside_vm = snd_intel8x0_inside_vm(pci);
3059 
3060         if (pci->vendor == PCI_VENDOR_ID_INTEL &&
3061             pci->device == PCI_DEVICE_ID_INTEL_440MX)
3062                 chip->fix_nocache = 1; /* enable workaround */
3063 
3064         if ((err = pci_request_regions(pci, card->shortname)) < 0) {
3065                 kfree(chip);
3066                 pci_disable_device(pci);
3067                 return err;
3068         }
3069 
3070         if (device_type == DEVICE_ALI) {
3071                 /* ALI5455 has no ac97 region */
3072                 chip->bmaddr = pci_iomap(pci, 0, 0);
3073                 goto port_inited;
3074         }
3075 
3076         if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */
3077                 chip->addr = pci_iomap(pci, 2, 0);
3078         else
3079                 chip->addr = pci_iomap(pci, 0, 0);
3080         if (!chip->addr) {
3081                 dev_err(card->dev, "AC'97 space ioremap problem\n");
3082                 snd_intel8x0_free(chip);
3083                 return -EIO;
3084         }
3085         if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */
3086                 chip->bmaddr = pci_iomap(pci, 3, 0);
3087         else
3088                 chip->bmaddr = pci_iomap(pci, 1, 0);
3089 
3090  port_inited:
3091         if (!chip->bmaddr) {
3092                 dev_err(card->dev, "Controller space ioremap problem\n");
3093                 snd_intel8x0_free(chip);
3094                 return -EIO;
3095         }
3096         chip->bdbars_count = bdbars[device_type];
3097 
3098         /* initialize offsets */
3099         switch (device_type) {
3100         case DEVICE_NFORCE:
3101                 tbl = nforce_regs;
3102                 break;
3103         case DEVICE_ALI:
3104                 tbl = ali_regs;
3105                 break;
3106         default:
3107                 tbl = intel_regs;
3108                 break;
3109         }
3110         for (i = 0; i < chip->bdbars_count; i++) {
3111                 ichdev = &chip->ichd[i];
3112                 ichdev->ichd = i;
3113                 ichdev->reg_offset = tbl[i].offset;
3114                 ichdev->int_sta_mask = tbl[i].int_sta_mask;
3115                 if (device_type == DEVICE_SIS) {
3116                         /* SiS 7012 swaps the registers */
3117                         ichdev->roff_sr = ICH_REG_OFF_PICB;
3118                         ichdev->roff_picb = ICH_REG_OFF_SR;
3119                 } else {
3120                         ichdev->roff_sr = ICH_REG_OFF_SR;
3121                         ichdev->roff_picb = ICH_REG_OFF_PICB;
3122                 }
3123                 if (device_type == DEVICE_ALI)
3124                         ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
3125                 /* SIS7012 handles the pcm data in bytes, others are in samples */
3126                 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
3127         }
3128 
3129         /* allocate buffer descriptor lists */
3130         /* the start of each lists must be aligned to 8 bytes */
3131         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
3132                                 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
3133                                 &chip->bdbars) < 0) {
3134                 snd_intel8x0_free(chip);
3135                 dev_err(card->dev, "cannot allocate buffer descriptors\n");
3136                 return -ENOMEM;
3137         }
3138         /* tables must be aligned to 8 bytes here, but the kernel pages
3139            are much bigger, so we don't care (on i386) */
3140         /* workaround for 440MX */
3141         if (chip->fix_nocache)
3142                 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
3143         int_sta_masks = 0;
3144         for (i = 0; i < chip->bdbars_count; i++) {
3145                 ichdev = &chip->ichd[i];
3146                 ichdev->bdbar = ((u32 *)chip->bdbars.area) +
3147                         (i * ICH_MAX_FRAGS * 2);
3148                 ichdev->bdbar_addr = chip->bdbars.addr +
3149                         (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
3150                 int_sta_masks |= ichdev->int_sta_mask;
3151         }
3152         chip->int_sta_reg = device_type == DEVICE_ALI ?
3153                 ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
3154         chip->int_sta_mask = int_sta_masks;
3155 
3156         pci_set_master(pci);
3157 
3158         switch(chip->device_type) {
3159         case DEVICE_INTEL_ICH4:
3160                 /* ICH4 can have three codecs */
3161                 chip->max_codecs = 3;
3162                 chip->codec_bit = ich_codec_bits;
3163                 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI;
3164                 break;
3165         case DEVICE_SIS:
3166                 /* recent SIS7012 can have three codecs */
3167                 chip->max_codecs = 3;
3168                 chip->codec_bit = sis_codec_bits;
3169                 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI;
3170                 break;
3171         default:
3172                 /* others up to two codecs */
3173                 chip->max_codecs = 2;
3174                 chip->codec_bit = ich_codec_bits;
3175                 chip->codec_ready_bits = ICH_PRI | ICH_SRI;
3176                 break;
3177         }
3178         for (i = 0; i < chip->max_codecs; i++)
3179                 chip->codec_isr_bits |= chip->codec_bit[i];
3180 
3181         if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
3182                 snd_intel8x0_free(chip);
3183                 return err;
3184         }
3185 
3186         /* request irq after initializaing int_sta_mask, etc */
3187         if (request_irq(pci->irq, snd_intel8x0_interrupt,
3188                         IRQF_SHARED, KBUILD_MODNAME, chip)) {
3189                 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
3190                 snd_intel8x0_free(chip);
3191                 return -EBUSY;
3192         }
3193         chip->irq = pci->irq;
3194 
3195         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
3196                 snd_intel8x0_free(chip);
3197                 return err;
3198         }
3199 
3200         *r_intel8x0 = chip;
3201         return 0;
3202 }
3203 
3204 static struct shortname_table {
3205         unsigned int id;
3206         const char *s;
3207 } shortnames[] = {
3208         { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" },
3209         { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" },
3210         { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" },
3211         { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
3212         { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" },
3213         { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" },
3214         { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" },
3215         { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
3216         { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
3217         { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
3218         { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
3219         { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
3220         { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" },
3221         { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
3222         { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
3223         { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
3224         { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
3225         { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
3226         { 0x003a, "NVidia MCP04" },
3227         { 0x746d, "AMD AMD8111" },
3228         { 0x7445, "AMD AMD768" },
3229         { 0x5455, "ALi M5455" },
3230         { 0, NULL },
3231 };
3232 
3233 static struct snd_pci_quirk spdif_aclink_defaults[] = {
3234         SND_PCI_QUIRK(0x147b, 0x1c1a, "ASUS KN8", 1),
3235         { } /* end */
3236 };
3237 
3238 /* look up white/black list for SPDIF over ac-link */
3239 static int check_default_spdif_aclink(struct pci_dev *pci)
3240 {
3241         const struct snd_pci_quirk *w;
3242 
3243         w = snd_pci_quirk_lookup(pci, spdif_aclink_defaults);
3244         if (w) {
3245                 if (w->value)
3246                         dev_dbg(&pci->dev,
3247                                 "Using SPDIF over AC-Link for %s\n",
3248                                     snd_pci_quirk_name(w));
3249                 else
3250                         dev_dbg(&pci->dev,
3251                                 "Using integrated SPDIF DMA for %s\n",
3252                                     snd_pci_quirk_name(w));
3253                 return w->value;
3254         }
3255         return 0;
3256 }
3257 
3258 static int snd_intel8x0_probe(struct pci_dev *pci,
3259                               const struct pci_device_id *pci_id)
3260 {
3261         struct snd_card *card;
3262         struct intel8x0 *chip;
3263         int err;
3264         struct shortname_table *name;
3265 
3266         err = snd_card_new(&pci->dev, index, id, THIS_MODULE, 0, &card);
3267         if (err < 0)
3268                 return err;
3269 
3270         if (spdif_aclink < 0)
3271                 spdif_aclink = check_default_spdif_aclink(pci);
3272 
3273         strcpy(card->driver, "ICH");
3274         if (!spdif_aclink) {
3275                 switch (pci_id->driver_data) {
3276                 case DEVICE_NFORCE:
3277                         strcpy(card->driver, "NFORCE");
3278                         break;
3279                 case DEVICE_INTEL_ICH4:
3280                         strcpy(card->driver, "ICH4");
3281                 }
3282         }
3283 
3284         strcpy(card->shortname, "Intel ICH");
3285         for (name = shortnames; name->id; name++) {
3286                 if (pci->device == name->id) {
3287                         strcpy(card->shortname, name->s);
3288                         break;
3289                 }
3290         }
3291 
3292         if (buggy_irq < 0) {
3293                 /* some Nforce[2] and ICH boards have problems with IRQ handling.
3294                  * Needs to return IRQ_HANDLED for unknown irqs.
3295                  */
3296                 if (pci_id->driver_data == DEVICE_NFORCE)
3297                         buggy_irq = 1;
3298                 else
3299                         buggy_irq = 0;
3300         }
3301 
3302         if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data,
3303                                        &chip)) < 0) {
3304                 snd_card_free(card);
3305                 return err;
3306         }
3307         card->private_data = chip;
3308 
3309         if ((err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk)) < 0) {
3310                 snd_card_free(card);
3311                 return err;
3312         }
3313         if ((err = snd_intel8x0_pcm(chip)) < 0) {
3314                 snd_card_free(card);
3315                 return err;
3316         }
3317         
3318         snd_intel8x0_proc_init(chip);
3319 
3320         snprintf(card->longname, sizeof(card->longname),
3321                  "%s with %s at irq %i", card->shortname,
3322                  snd_ac97_get_short_name(chip->ac97[0]), chip->irq);
3323 
3324         if (ac97_clock == 0 || ac97_clock == 1) {
3325                 if (ac97_clock == 0) {
3326                         if (intel8x0_in_clock_list(chip) == 0)
3327                                 intel8x0_measure_ac97_clock(chip);
3328                 } else {
3329                         intel8x0_measure_ac97_clock(chip);
3330                 }
3331         }
3332 
3333         if ((err = snd_card_register(card)) < 0) {
3334                 snd_card_free(card);
3335                 return err;
3336         }
3337         pci_set_drvdata(pci, card);
3338         return 0;
3339 }
3340 
3341 static void snd_intel8x0_remove(struct pci_dev *pci)
3342 {
3343         snd_card_free(pci_get_drvdata(pci));
3344 }
3345 
3346 static struct pci_driver intel8x0_driver = {
3347         .name = KBUILD_MODNAME,
3348         .id_table = snd_intel8x0_ids,
3349         .probe = snd_intel8x0_probe,
3350         .remove = snd_intel8x0_remove,
3351         .driver = {
3352                 .pm = INTEL8X0_PM_OPS,
3353         },
3354 };
3355 
3356 module_pci_driver(intel8x0_driver);
3357 

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