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TOMOYO Linux Cross Reference
Linux/sound/pci/pcxhr/pcxhr.c

Version: ~ [ linux-5.10-rc6 ] ~ [ linux-5.9.12 ] ~ [ linux-5.8.18 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.81 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.161 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.210 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.247 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.247 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.19.8 ] ~ [ linux-3.18.140 ] ~ [ linux-3.17.8 ] ~ [ linux-3.16.85 ] ~ [ linux-3.15.10 ] ~ [ linux-3.14.79 ] ~ [ linux-3.13.11 ] ~ [ linux-3.12.74 ] ~ [ linux-3.11.10 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.5 ] ~ [ policy-sample ] ~
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  1 /*
  2  * Driver for Digigram pcxhr compatible soundcards
  3  *
  4  * main file with alsa callbacks
  5  *
  6  * Copyright (c) 2004 by Digigram <alsa@digigram.com>
  7  *
  8  *   This program is free software; you can redistribute it and/or modify
  9  *   it under the terms of the GNU General Public License as published by
 10  *   the Free Software Foundation; either version 2 of the License, or
 11  *   (at your option) any later version.
 12  *
 13  *   This program is distributed in the hope that it will be useful,
 14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 16  *   GNU General Public License for more details.
 17  *
 18  *   You should have received a copy of the GNU General Public License
 19  *   along with this program; if not, write to the Free Software
 20  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 21  */
 22 
 23 
 24 #include <linux/init.h>
 25 #include <linux/interrupt.h>
 26 #include <linux/slab.h>
 27 #include <linux/pci.h>
 28 #include <linux/dma-mapping.h>
 29 #include <linux/delay.h>
 30 #include <linux/moduleparam.h>
 31 #include <linux/mutex.h>
 32 
 33 #include <sound/core.h>
 34 #include <sound/initval.h>
 35 #include <sound/info.h>
 36 #include <sound/control.h>
 37 #include <sound/pcm.h>
 38 #include <sound/pcm_params.h>
 39 #include "pcxhr.h"
 40 #include "pcxhr_mixer.h"
 41 #include "pcxhr_hwdep.h"
 42 #include "pcxhr_core.h"
 43 #include "pcxhr_mix22.h"
 44 
 45 #define DRIVER_NAME "pcxhr"
 46 
 47 MODULE_AUTHOR("Markus Bollinger <bollinger@digigram.com>, "
 48               "Marc Titinger <titinger@digigram.com>");
 49 MODULE_DESCRIPTION("Digigram " DRIVER_NAME " " PCXHR_DRIVER_VERSION_STRING);
 50 MODULE_LICENSE("GPL");
 51 MODULE_SUPPORTED_DEVICE("{{Digigram," DRIVER_NAME "}}");
 52 
 53 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
 54 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
 55 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
 56 static int mono[SNDRV_CARDS];                           /* capture  mono only */
 57 
 58 module_param_array(index, int, NULL, 0444);
 59 MODULE_PARM_DESC(index, "Index value for Digigram " DRIVER_NAME " soundcard");
 60 module_param_array(id, charp, NULL, 0444);
 61 MODULE_PARM_DESC(id, "ID string for Digigram " DRIVER_NAME " soundcard");
 62 module_param_array(enable, bool, NULL, 0444);
 63 MODULE_PARM_DESC(enable, "Enable Digigram " DRIVER_NAME " soundcard");
 64 module_param_array(mono, bool, NULL, 0444);
 65 MODULE_PARM_DESC(mono, "Mono capture mode (default is stereo)");
 66 
 67 enum {
 68         PCI_ID_VX882HR,
 69         PCI_ID_PCX882HR,
 70         PCI_ID_VX881HR,
 71         PCI_ID_PCX881HR,
 72         PCI_ID_VX882E,
 73         PCI_ID_PCX882E,
 74         PCI_ID_VX881E,
 75         PCI_ID_PCX881E,
 76         PCI_ID_VX1222HR,
 77         PCI_ID_PCX1222HR,
 78         PCI_ID_VX1221HR,
 79         PCI_ID_PCX1221HR,
 80         PCI_ID_VX1222E,
 81         PCI_ID_PCX1222E,
 82         PCI_ID_VX1221E,
 83         PCI_ID_PCX1221E,
 84         PCI_ID_VX222HR,
 85         PCI_ID_VX222E,
 86         PCI_ID_PCX22HR,
 87         PCI_ID_PCX22E,
 88         PCI_ID_VX222HRMIC,
 89         PCI_ID_VX222E_MIC,
 90         PCI_ID_PCX924HR,
 91         PCI_ID_PCX924E,
 92         PCI_ID_PCX924HRMIC,
 93         PCI_ID_PCX924E_MIC,
 94         PCI_ID_LAST
 95 };
 96 
 97 static struct pci_device_id pcxhr_ids[] = {
 98         { 0x10b5, 0x9656, 0x1369, 0xb001, 0, 0, PCI_ID_VX882HR, },
 99         { 0x10b5, 0x9656, 0x1369, 0xb101, 0, 0, PCI_ID_PCX882HR, },
100         { 0x10b5, 0x9656, 0x1369, 0xb201, 0, 0, PCI_ID_VX881HR, },
101         { 0x10b5, 0x9656, 0x1369, 0xb301, 0, 0, PCI_ID_PCX881HR, },
102         { 0x10b5, 0x9056, 0x1369, 0xb021, 0, 0, PCI_ID_VX882E, },
103         { 0x10b5, 0x9056, 0x1369, 0xb121, 0, 0, PCI_ID_PCX882E, },
104         { 0x10b5, 0x9056, 0x1369, 0xb221, 0, 0, PCI_ID_VX881E, },
105         { 0x10b5, 0x9056, 0x1369, 0xb321, 0, 0, PCI_ID_PCX881E, },
106         { 0x10b5, 0x9656, 0x1369, 0xb401, 0, 0, PCI_ID_VX1222HR, },
107         { 0x10b5, 0x9656, 0x1369, 0xb501, 0, 0, PCI_ID_PCX1222HR, },
108         { 0x10b5, 0x9656, 0x1369, 0xb601, 0, 0, PCI_ID_VX1221HR, },
109         { 0x10b5, 0x9656, 0x1369, 0xb701, 0, 0, PCI_ID_PCX1221HR, },
110         { 0x10b5, 0x9056, 0x1369, 0xb421, 0, 0, PCI_ID_VX1222E, },
111         { 0x10b5, 0x9056, 0x1369, 0xb521, 0, 0, PCI_ID_PCX1222E, },
112         { 0x10b5, 0x9056, 0x1369, 0xb621, 0, 0, PCI_ID_VX1221E, },
113         { 0x10b5, 0x9056, 0x1369, 0xb721, 0, 0, PCI_ID_PCX1221E, },
114         { 0x10b5, 0x9056, 0x1369, 0xba01, 0, 0, PCI_ID_VX222HR, },
115         { 0x10b5, 0x9056, 0x1369, 0xba21, 0, 0, PCI_ID_VX222E, },
116         { 0x10b5, 0x9056, 0x1369, 0xbd01, 0, 0, PCI_ID_PCX22HR, },
117         { 0x10b5, 0x9056, 0x1369, 0xbd21, 0, 0, PCI_ID_PCX22E, },
118         { 0x10b5, 0x9056, 0x1369, 0xbc01, 0, 0, PCI_ID_VX222HRMIC, },
119         { 0x10b5, 0x9056, 0x1369, 0xbc21, 0, 0, PCI_ID_VX222E_MIC, },
120         { 0x10b5, 0x9056, 0x1369, 0xbb01, 0, 0, PCI_ID_PCX924HR, },
121         { 0x10b5, 0x9056, 0x1369, 0xbb21, 0, 0, PCI_ID_PCX924E, },
122         { 0x10b5, 0x9056, 0x1369, 0xbf01, 0, 0, PCI_ID_PCX924HRMIC, },
123         { 0x10b5, 0x9056, 0x1369, 0xbf21, 0, 0, PCI_ID_PCX924E_MIC, },
124         { 0, }
125 };
126 
127 MODULE_DEVICE_TABLE(pci, pcxhr_ids);
128 
129 struct board_parameters {
130         char* board_name;
131         short playback_chips;
132         short capture_chips;
133         short fw_file_set;
134         short firmware_num;
135 };
136 static struct board_parameters pcxhr_board_params[] = {
137 [PCI_ID_VX882HR] =      { "VX882HR",      4, 4, 0, 41 },
138 [PCI_ID_PCX882HR] =     { "PCX882HR",     4, 4, 0, 41 },
139 [PCI_ID_VX881HR] =      { "VX881HR",      4, 4, 0, 41 },
140 [PCI_ID_PCX881HR] =     { "PCX881HR",     4, 4, 0, 41 },
141 [PCI_ID_VX882E] =       { "VX882e",       4, 4, 1, 41 },
142 [PCI_ID_PCX882E] =      { "PCX882e",      4, 4, 1, 41 },
143 [PCI_ID_VX881E] =       { "VX881e",       4, 4, 1, 41 },
144 [PCI_ID_PCX881E] =      { "PCX881e",      4, 4, 1, 41 },
145 [PCI_ID_VX1222HR] =     { "VX1222HR",     6, 1, 2, 42 },
146 [PCI_ID_PCX1222HR] =    { "PCX1222HR",    6, 1, 2, 42 },
147 [PCI_ID_VX1221HR] =     { "VX1221HR",     6, 1, 2, 42 },
148 [PCI_ID_PCX1221HR] =    { "PCX1221HR",    6, 1, 2, 42 },
149 [PCI_ID_VX1222E] =      { "VX1222e",      6, 1, 3, 42 },
150 [PCI_ID_PCX1222E] =     { "PCX1222e",     6, 1, 3, 42 },
151 [PCI_ID_VX1221E] =      { "VX1221e",      6, 1, 3, 42 },
152 [PCI_ID_PCX1221E] =     { "PCX1221e",     6, 1, 3, 42 },
153 [PCI_ID_VX222HR] =      { "VX222HR",      1, 1, 4, 44 },
154 [PCI_ID_VX222E] =       { "VX222e",       1, 1, 4, 44 },
155 [PCI_ID_PCX22HR] =      { "PCX22HR",      1, 0, 4, 44 },
156 [PCI_ID_PCX22E] =       { "PCX22e",       1, 0, 4, 44 },
157 [PCI_ID_VX222HRMIC] =   { "VX222HR-Mic",  1, 1, 5, 44 },
158 [PCI_ID_VX222E_MIC] =   { "VX222e-Mic",   1, 1, 5, 44 },
159 [PCI_ID_PCX924HR] =     { "PCX924HR",     1, 1, 5, 44 },
160 [PCI_ID_PCX924E] =      { "PCX924e",      1, 1, 5, 44 },
161 [PCI_ID_PCX924HRMIC] =  { "PCX924HR-Mic", 1, 1, 5, 44 },
162 [PCI_ID_PCX924E_MIC] =  { "PCX924e-Mic",  1, 1, 5, 44 },
163 };
164 
165 /* boards without hw AES1 and SRC onboard are all using fw_file_set==4 */
166 /* VX222HR, VX222e, PCX22HR and PCX22e */
167 #define PCXHR_BOARD_HAS_AES1(x) (x->fw_file_set != 4)
168 /* some boards do not support 192kHz on digital AES input plugs */
169 #define PCXHR_BOARD_AESIN_NO_192K(x) ((x->capture_chips == 0) || \
170                                       (x->fw_file_set == 0)   || \
171                                       (x->fw_file_set == 2))
172 
173 static int pcxhr_pll_freq_register(unsigned int freq, unsigned int* pllreg,
174                                    unsigned int* realfreq)
175 {
176         unsigned int reg;
177 
178         if (freq < 6900 || freq > 110000)
179                 return -EINVAL;
180         reg = (28224000 * 2) / freq;
181         reg = (reg - 1) / 2;
182         if (reg < 0x200)
183                 *pllreg = reg + 0x800;
184         else if (reg < 0x400)
185                 *pllreg = reg & 0x1ff;
186         else if (reg < 0x800) {
187                 *pllreg = ((reg >> 1) & 0x1ff) + 0x200;
188                 reg &= ~1;
189         } else {
190                 *pllreg = ((reg >> 2) & 0x1ff) + 0x400;
191                 reg &= ~3;
192         }
193         if (realfreq)
194                 *realfreq = (28224000 / (reg + 1));
195         return 0;
196 }
197 
198 
199 #define PCXHR_FREQ_REG_MASK             0x1f
200 #define PCXHR_FREQ_QUARTZ_48000         0x00
201 #define PCXHR_FREQ_QUARTZ_24000         0x01
202 #define PCXHR_FREQ_QUARTZ_12000         0x09
203 #define PCXHR_FREQ_QUARTZ_32000         0x08
204 #define PCXHR_FREQ_QUARTZ_16000         0x04
205 #define PCXHR_FREQ_QUARTZ_8000          0x0c
206 #define PCXHR_FREQ_QUARTZ_44100         0x02
207 #define PCXHR_FREQ_QUARTZ_22050         0x0a
208 #define PCXHR_FREQ_QUARTZ_11025         0x06
209 #define PCXHR_FREQ_PLL                  0x05
210 #define PCXHR_FREQ_QUARTZ_192000        0x10
211 #define PCXHR_FREQ_QUARTZ_96000         0x18
212 #define PCXHR_FREQ_QUARTZ_176400        0x14
213 #define PCXHR_FREQ_QUARTZ_88200         0x1c
214 #define PCXHR_FREQ_QUARTZ_128000        0x12
215 #define PCXHR_FREQ_QUARTZ_64000         0x1a
216 
217 #define PCXHR_FREQ_WORD_CLOCK           0x0f
218 #define PCXHR_FREQ_SYNC_AES             0x0e
219 #define PCXHR_FREQ_AES_1                0x07
220 #define PCXHR_FREQ_AES_2                0x0b
221 #define PCXHR_FREQ_AES_3                0x03
222 #define PCXHR_FREQ_AES_4                0x0d
223 
224 static int pcxhr_get_clock_reg(struct pcxhr_mgr *mgr, unsigned int rate,
225                                unsigned int *reg, unsigned int *freq)
226 {
227         unsigned int val, realfreq, pllreg;
228         struct pcxhr_rmh rmh;
229         int err;
230 
231         realfreq = rate;
232         switch (mgr->use_clock_type) {
233         case PCXHR_CLOCK_TYPE_INTERNAL :        /* clock by quartz or pll */
234                 switch (rate) {
235                 case 48000 :    val = PCXHR_FREQ_QUARTZ_48000;  break;
236                 case 24000 :    val = PCXHR_FREQ_QUARTZ_24000;  break;
237                 case 12000 :    val = PCXHR_FREQ_QUARTZ_12000;  break;
238                 case 32000 :    val = PCXHR_FREQ_QUARTZ_32000;  break;
239                 case 16000 :    val = PCXHR_FREQ_QUARTZ_16000;  break;
240                 case 8000 :     val = PCXHR_FREQ_QUARTZ_8000;   break;
241                 case 44100 :    val = PCXHR_FREQ_QUARTZ_44100;  break;
242                 case 22050 :    val = PCXHR_FREQ_QUARTZ_22050;  break;
243                 case 11025 :    val = PCXHR_FREQ_QUARTZ_11025;  break;
244                 case 192000 :   val = PCXHR_FREQ_QUARTZ_192000; break;
245                 case 96000 :    val = PCXHR_FREQ_QUARTZ_96000;  break;
246                 case 176400 :   val = PCXHR_FREQ_QUARTZ_176400; break;
247                 case 88200 :    val = PCXHR_FREQ_QUARTZ_88200;  break;
248                 case 128000 :   val = PCXHR_FREQ_QUARTZ_128000; break;
249                 case 64000 :    val = PCXHR_FREQ_QUARTZ_64000;  break;
250                 default :
251                         val = PCXHR_FREQ_PLL;
252                         /* get the value for the pll register */
253                         err = pcxhr_pll_freq_register(rate, &pllreg, &realfreq);
254                         if (err)
255                                 return err;
256                         pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE);
257                         rmh.cmd[0] |= IO_NUM_REG_GENCLK;
258                         rmh.cmd[1]  = pllreg & MASK_DSP_WORD;
259                         rmh.cmd[2]  = pllreg >> 24;
260                         rmh.cmd_len = 3;
261                         err = pcxhr_send_msg(mgr, &rmh);
262                         if (err < 0) {
263                                 snd_printk(KERN_ERR
264                                            "error CMD_ACCESS_IO_WRITE "
265                                            "for PLL register : %x!\n", err);
266                                 return err;
267                         }
268                 }
269                 break;
270         case PCXHR_CLOCK_TYPE_WORD_CLOCK:
271                 val = PCXHR_FREQ_WORD_CLOCK;
272                 break;
273         case PCXHR_CLOCK_TYPE_AES_SYNC:
274                 val = PCXHR_FREQ_SYNC_AES;
275                 break;
276         case PCXHR_CLOCK_TYPE_AES_1:
277                 val = PCXHR_FREQ_AES_1;
278                 break;
279         case PCXHR_CLOCK_TYPE_AES_2:
280                 val = PCXHR_FREQ_AES_2;
281                 break;
282         case PCXHR_CLOCK_TYPE_AES_3:
283                 val = PCXHR_FREQ_AES_3;
284                 break;
285         case PCXHR_CLOCK_TYPE_AES_4:
286                 val = PCXHR_FREQ_AES_4;
287                 break;
288         default:
289                 return -EINVAL;
290         }
291         *reg = val;
292         *freq = realfreq;
293         return 0;
294 }
295 
296 
297 static int pcxhr_sub_set_clock(struct pcxhr_mgr *mgr,
298                                unsigned int rate,
299                                int *changed)
300 {
301         unsigned int val, realfreq, speed;
302         struct pcxhr_rmh rmh;
303         int err;
304 
305         err = pcxhr_get_clock_reg(mgr, rate, &val, &realfreq);
306         if (err)
307                 return err;
308 
309         /* codec speed modes */
310         if (rate < 55000)
311                 speed = 0;      /* single speed */
312         else if (rate < 100000)
313                 speed = 1;      /* dual speed */
314         else
315                 speed = 2;      /* quad speed */
316         if (mgr->codec_speed != speed) {
317                 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); /* mute outputs */
318                 rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT;
319                 if (DSP_EXT_CMD_SET(mgr)) {
320                         rmh.cmd[1]  = 1;
321                         rmh.cmd_len = 2;
322                 }
323                 err = pcxhr_send_msg(mgr, &rmh);
324                 if (err)
325                         return err;
326 
327                 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); /* set speed ratio */
328                 rmh.cmd[0] |= IO_NUM_SPEED_RATIO;
329                 rmh.cmd[1] = speed;
330                 rmh.cmd_len = 2;
331                 err = pcxhr_send_msg(mgr, &rmh);
332                 if (err)
333                         return err;
334         }
335         /* set the new frequency */
336         snd_printdd("clock register : set %x\n", val);
337         err = pcxhr_write_io_num_reg_cont(mgr, PCXHR_FREQ_REG_MASK,
338                                           val, changed);
339         if (err)
340                 return err;
341 
342         mgr->sample_rate_real = realfreq;
343         mgr->cur_clock_type = mgr->use_clock_type;
344 
345         /* unmute after codec speed modes */
346         if (mgr->codec_speed != speed) {
347                 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ); /* unmute outputs */
348                 rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT;
349                 if (DSP_EXT_CMD_SET(mgr)) {
350                         rmh.cmd[1]  = 1;
351                         rmh.cmd_len = 2;
352                 }
353                 err = pcxhr_send_msg(mgr, &rmh);
354                 if (err)
355                         return err;
356                 mgr->codec_speed = speed;       /* save new codec speed */
357         }
358 
359         snd_printdd("pcxhr_sub_set_clock to %dHz (realfreq=%d)\n",
360                     rate, realfreq);
361         return 0;
362 }
363 
364 #define PCXHR_MODIFY_CLOCK_S_BIT        0x04
365 
366 #define PCXHR_IRQ_TIMER_FREQ            92000
367 #define PCXHR_IRQ_TIMER_PERIOD          48
368 
369 int pcxhr_set_clock(struct pcxhr_mgr *mgr, unsigned int rate)
370 {
371         struct pcxhr_rmh rmh;
372         int err, changed;
373 
374         if (rate == 0)
375                 return 0; /* nothing to do */
376 
377         if (mgr->is_hr_stereo)
378                 err = hr222_sub_set_clock(mgr, rate, &changed);
379         else
380                 err = pcxhr_sub_set_clock(mgr, rate, &changed);
381 
382         if (err)
383                 return err;
384 
385         if (changed) {
386                 pcxhr_init_rmh(&rmh, CMD_MODIFY_CLOCK);
387                 rmh.cmd[0] |= PCXHR_MODIFY_CLOCK_S_BIT; /* resync fifos  */
388                 if (rate < PCXHR_IRQ_TIMER_FREQ)
389                         rmh.cmd[1] = PCXHR_IRQ_TIMER_PERIOD;
390                 else
391                         rmh.cmd[1] = PCXHR_IRQ_TIMER_PERIOD * 2;
392                 rmh.cmd[2] = rate;
393                 rmh.cmd_len = 3;
394                 err = pcxhr_send_msg(mgr, &rmh);
395                 if (err)
396                         return err;
397         }
398         return 0;
399 }
400 
401 
402 static int pcxhr_sub_get_external_clock(struct pcxhr_mgr *mgr,
403                                         enum pcxhr_clock_type clock_type,
404                                         int *sample_rate)
405 {
406         struct pcxhr_rmh rmh;
407         unsigned char reg;
408         int err, rate;
409 
410         switch (clock_type) {
411         case PCXHR_CLOCK_TYPE_WORD_CLOCK:
412                 reg = REG_STATUS_WORD_CLOCK;
413                 break;
414         case PCXHR_CLOCK_TYPE_AES_SYNC:
415                 reg = REG_STATUS_AES_SYNC;
416                 break;
417         case PCXHR_CLOCK_TYPE_AES_1:
418                 reg = REG_STATUS_AES_1;
419                 break;
420         case PCXHR_CLOCK_TYPE_AES_2:
421                 reg = REG_STATUS_AES_2;
422                 break;
423         case PCXHR_CLOCK_TYPE_AES_3:
424                 reg = REG_STATUS_AES_3;
425                 break;
426         case PCXHR_CLOCK_TYPE_AES_4:
427                 reg = REG_STATUS_AES_4;
428                 break;
429         default:
430                 return -EINVAL;
431         }
432         pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ);
433         rmh.cmd_len = 2;
434         rmh.cmd[0] |= IO_NUM_REG_STATUS;
435         if (mgr->last_reg_stat != reg) {
436                 rmh.cmd[1]  = reg;
437                 err = pcxhr_send_msg(mgr, &rmh);
438                 if (err)
439                         return err;
440                 udelay(100);    /* wait minimum 2 sample_frames at 32kHz ! */
441                 mgr->last_reg_stat = reg;
442         }
443         rmh.cmd[1]  = REG_STATUS_CURRENT;
444         err = pcxhr_send_msg(mgr, &rmh);
445         if (err)
446                 return err;
447         switch (rmh.stat[1] & 0x0f) {
448         case REG_STATUS_SYNC_32000 :    rate = 32000; break;
449         case REG_STATUS_SYNC_44100 :    rate = 44100; break;
450         case REG_STATUS_SYNC_48000 :    rate = 48000; break;
451         case REG_STATUS_SYNC_64000 :    rate = 64000; break;
452         case REG_STATUS_SYNC_88200 :    rate = 88200; break;
453         case REG_STATUS_SYNC_96000 :    rate = 96000; break;
454         case REG_STATUS_SYNC_128000 :   rate = 128000; break;
455         case REG_STATUS_SYNC_176400 :   rate = 176400; break;
456         case REG_STATUS_SYNC_192000 :   rate = 192000; break;
457         default: rate = 0;
458         }
459         snd_printdd("External clock is at %d Hz\n", rate);
460         *sample_rate = rate;
461         return 0;
462 }
463 
464 
465 int pcxhr_get_external_clock(struct pcxhr_mgr *mgr,
466                              enum pcxhr_clock_type clock_type,
467                              int *sample_rate)
468 {
469         if (mgr->is_hr_stereo)
470                 return hr222_get_external_clock(mgr, clock_type,
471                                                 sample_rate);
472         else
473                 return pcxhr_sub_get_external_clock(mgr, clock_type,
474                                                     sample_rate);
475 }
476 
477 /*
478  *  start or stop playback/capture substream
479  */
480 static int pcxhr_set_stream_state(struct pcxhr_stream *stream)
481 {
482         int err;
483         struct snd_pcxhr *chip;
484         struct pcxhr_rmh rmh;
485         int stream_mask, start;
486 
487         if (stream->status == PCXHR_STREAM_STATUS_SCHEDULE_RUN)
488                 start = 1;
489         else {
490                 if (stream->status != PCXHR_STREAM_STATUS_SCHEDULE_STOP) {
491                         snd_printk(KERN_ERR "ERROR pcxhr_set_stream_state "
492                                    "CANNOT be stopped\n");
493                         return -EINVAL;
494                 }
495                 start = 0;
496         }
497         if (!stream->substream)
498                 return -EINVAL;
499 
500         stream->timer_abs_periods = 0;
501         stream->timer_period_frag = 0;  /* reset theoretical stream pos */
502         stream->timer_buf_periods = 0;
503         stream->timer_is_synced = 0;
504 
505         stream_mask =
506           stream->pipe->is_capture ? 1 : 1<<stream->substream->number;
507 
508         pcxhr_init_rmh(&rmh, start ? CMD_START_STREAM : CMD_STOP_STREAM);
509         pcxhr_set_pipe_cmd_params(&rmh, stream->pipe->is_capture,
510                                   stream->pipe->first_audio, 0, stream_mask);
511 
512         chip = snd_pcm_substream_chip(stream->substream);
513 
514         err = pcxhr_send_msg(chip->mgr, &rmh);
515         if (err)
516                 snd_printk(KERN_ERR "ERROR pcxhr_set_stream_state err=%x;\n",
517                            err);
518         stream->status =
519           start ? PCXHR_STREAM_STATUS_STARTED : PCXHR_STREAM_STATUS_STOPPED;
520         return err;
521 }
522 
523 #define HEADER_FMT_BASE_LIN             0xfed00000
524 #define HEADER_FMT_BASE_FLOAT           0xfad00000
525 #define HEADER_FMT_INTEL                0x00008000
526 #define HEADER_FMT_24BITS               0x00004000
527 #define HEADER_FMT_16BITS               0x00002000
528 #define HEADER_FMT_UPTO11               0x00000200
529 #define HEADER_FMT_UPTO32               0x00000100
530 #define HEADER_FMT_MONO                 0x00000080
531 
532 static int pcxhr_set_format(struct pcxhr_stream *stream)
533 {
534         int err, is_capture, sample_rate, stream_num;
535         struct snd_pcxhr *chip;
536         struct pcxhr_rmh rmh;
537         unsigned int header;
538 
539         switch (stream->format) {
540         case SNDRV_PCM_FORMAT_U8:
541                 header = HEADER_FMT_BASE_LIN;
542                 break;
543         case SNDRV_PCM_FORMAT_S16_LE:
544                 header = HEADER_FMT_BASE_LIN |
545                          HEADER_FMT_16BITS | HEADER_FMT_INTEL;
546                 break;
547         case SNDRV_PCM_FORMAT_S16_BE:
548                 header = HEADER_FMT_BASE_LIN | HEADER_FMT_16BITS;
549                 break;
550         case SNDRV_PCM_FORMAT_S24_3LE:
551                 header = HEADER_FMT_BASE_LIN |
552                          HEADER_FMT_24BITS | HEADER_FMT_INTEL;
553                 break;
554         case SNDRV_PCM_FORMAT_S24_3BE:
555                 header = HEADER_FMT_BASE_LIN | HEADER_FMT_24BITS;
556                 break;
557         case SNDRV_PCM_FORMAT_FLOAT_LE:
558                 header = HEADER_FMT_BASE_FLOAT | HEADER_FMT_INTEL;
559                 break;
560         default:
561                 snd_printk(KERN_ERR
562                            "error pcxhr_set_format() : unknown format\n");
563                 return -EINVAL;
564         }
565         chip = snd_pcm_substream_chip(stream->substream);
566 
567         sample_rate = chip->mgr->sample_rate;
568         if (sample_rate <= 32000 && sample_rate !=0) {
569                 if (sample_rate <= 11025)
570                         header |= HEADER_FMT_UPTO11;
571                 else
572                         header |= HEADER_FMT_UPTO32;
573         }
574         if (stream->channels == 1)
575                 header |= HEADER_FMT_MONO;
576 
577         is_capture = stream->pipe->is_capture;
578         stream_num = is_capture ? 0 : stream->substream->number;
579 
580         pcxhr_init_rmh(&rmh, is_capture ?
581                        CMD_FORMAT_STREAM_IN : CMD_FORMAT_STREAM_OUT);
582         pcxhr_set_pipe_cmd_params(&rmh, is_capture, stream->pipe->first_audio,
583                                   stream_num, 0);
584         if (is_capture) {
585                 /* bug with old dsp versions: */
586                 /* bit 12 also sets the format of the playback stream */
587                 if (DSP_EXT_CMD_SET(chip->mgr))
588                         rmh.cmd[0] |= 1<<10;
589                 else
590                         rmh.cmd[0] |= 1<<12;
591         }
592         rmh.cmd[1] = 0;
593         rmh.cmd_len = 2;
594         if (DSP_EXT_CMD_SET(chip->mgr)) {
595                 /* add channels and set bit 19 if channels>2 */
596                 rmh.cmd[1] = stream->channels;
597                 if (!is_capture) {
598                         /* playback : add channel mask to command */
599                         rmh.cmd[2] = (stream->channels == 1) ? 0x01 : 0x03;
600                         rmh.cmd_len = 3;
601                 }
602         }
603         rmh.cmd[rmh.cmd_len++] = header >> 8;
604         rmh.cmd[rmh.cmd_len++] = (header & 0xff) << 16;
605         err = pcxhr_send_msg(chip->mgr, &rmh);
606         if (err)
607                 snd_printk(KERN_ERR "ERROR pcxhr_set_format err=%x;\n", err);
608         return err;
609 }
610 
611 static int pcxhr_update_r_buffer(struct pcxhr_stream *stream)
612 {
613         int err, is_capture, stream_num;
614         struct pcxhr_rmh rmh;
615         struct snd_pcm_substream *subs = stream->substream;
616         struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
617 
618         is_capture = (subs->stream == SNDRV_PCM_STREAM_CAPTURE);
619         stream_num = is_capture ? 0 : subs->number;
620 
621         snd_printdd("pcxhr_update_r_buffer(pcm%c%d) : "
622                     "addr(%p) bytes(%zx) subs(%d)\n",
623                     is_capture ? 'c' : 'p',
624                     chip->chip_idx, (void *)(long)subs->runtime->dma_addr,
625                     subs->runtime->dma_bytes, subs->number);
626 
627         pcxhr_init_rmh(&rmh, CMD_UPDATE_R_BUFFERS);
628         pcxhr_set_pipe_cmd_params(&rmh, is_capture, stream->pipe->first_audio,
629                                   stream_num, 0);
630 
631         /* max buffer size is 2 MByte */
632         snd_BUG_ON(subs->runtime->dma_bytes >= 0x200000);
633         /* size in bits */
634         rmh.cmd[1] = subs->runtime->dma_bytes * 8;
635         /* most significant byte */
636         rmh.cmd[2] = subs->runtime->dma_addr >> 24;
637         /* this is a circular buffer */
638         rmh.cmd[2] |= 1<<19;
639         /* least 3 significant bytes */
640         rmh.cmd[3] = subs->runtime->dma_addr & MASK_DSP_WORD;
641         rmh.cmd_len = 4;
642         err = pcxhr_send_msg(chip->mgr, &rmh);
643         if (err)
644                 snd_printk(KERN_ERR
645                            "ERROR CMD_UPDATE_R_BUFFERS err=%x;\n", err);
646         return err;
647 }
648 
649 
650 #if 0
651 static int pcxhr_pipe_sample_count(struct pcxhr_stream *stream,
652                                    snd_pcm_uframes_t *sample_count)
653 {
654         struct pcxhr_rmh rmh;
655         int err;
656         pcxhr_t *chip = snd_pcm_substream_chip(stream->substream);
657         pcxhr_init_rmh(&rmh, CMD_PIPE_SAMPLE_COUNT);
658         pcxhr_set_pipe_cmd_params(&rmh, stream->pipe->is_capture, 0, 0,
659                                   1<<stream->pipe->first_audio);
660         err = pcxhr_send_msg(chip->mgr, &rmh);
661         if (err == 0) {
662                 *sample_count = ((snd_pcm_uframes_t)rmh.stat[0]) << 24;
663                 *sample_count += (snd_pcm_uframes_t)rmh.stat[1];
664         }
665         snd_printdd("PIPE_SAMPLE_COUNT = %lx\n", *sample_count);
666         return err;
667 }
668 #endif
669 
670 static inline int pcxhr_stream_scheduled_get_pipe(struct pcxhr_stream *stream,
671                                                   struct pcxhr_pipe **pipe)
672 {
673         if (stream->status == PCXHR_STREAM_STATUS_SCHEDULE_RUN) {
674                 *pipe = stream->pipe;
675                 return 1;
676         }
677         return 0;
678 }
679 
680 static void pcxhr_trigger_tasklet(unsigned long arg)
681 {
682         unsigned long flags;
683         int i, j, err;
684         struct pcxhr_pipe *pipe;
685         struct snd_pcxhr *chip;
686         struct pcxhr_mgr *mgr = (struct pcxhr_mgr*)(arg);
687         int capture_mask = 0;
688         int playback_mask = 0;
689 
690 #ifdef CONFIG_SND_DEBUG_VERBOSE
691         struct timeval my_tv1, my_tv2;
692         do_gettimeofday(&my_tv1);
693 #endif
694         mutex_lock(&mgr->setup_mutex);
695 
696         /* check the pipes concerned and build pipe_array */
697         for (i = 0; i < mgr->num_cards; i++) {
698                 chip = mgr->chip[i];
699                 for (j = 0; j < chip->nb_streams_capt; j++) {
700                         if (pcxhr_stream_scheduled_get_pipe(&chip->capture_stream[j], &pipe))
701                                 capture_mask |= (1 << pipe->first_audio);
702                 }
703                 for (j = 0; j < chip->nb_streams_play; j++) {
704                         if (pcxhr_stream_scheduled_get_pipe(&chip->playback_stream[j], &pipe)) {
705                                 playback_mask |= (1 << pipe->first_audio);
706                                 break;  /* add only once, as all playback
707                                          * streams of one chip use the same pipe
708                                          */
709                         }
710                 }
711         }
712         if (capture_mask == 0 && playback_mask == 0) {
713                 mutex_unlock(&mgr->setup_mutex);
714                 snd_printk(KERN_ERR "pcxhr_trigger_tasklet : no pipes\n");
715                 return;
716         }
717 
718         snd_printdd("pcxhr_trigger_tasklet : "
719                     "playback_mask=%x capture_mask=%x\n",
720                     playback_mask, capture_mask);
721 
722         /* synchronous stop of all the pipes concerned */
723         err = pcxhr_set_pipe_state(mgr,  playback_mask, capture_mask, 0);
724         if (err) {
725                 mutex_unlock(&mgr->setup_mutex);
726                 snd_printk(KERN_ERR "pcxhr_trigger_tasklet : "
727                            "error stop pipes (P%x C%x)\n",
728                            playback_mask, capture_mask);
729                 return;
730         }
731 
732         /* the dsp lost format and buffer info with the stop pipe */
733         for (i = 0; i < mgr->num_cards; i++) {
734                 struct pcxhr_stream *stream;
735                 chip = mgr->chip[i];
736                 for (j = 0; j < chip->nb_streams_capt; j++) {
737                         stream = &chip->capture_stream[j];
738                         if (pcxhr_stream_scheduled_get_pipe(stream, &pipe)) {
739                                 err = pcxhr_set_format(stream);
740                                 err = pcxhr_update_r_buffer(stream);
741                         }
742                 }
743                 for (j = 0; j < chip->nb_streams_play; j++) {
744                         stream = &chip->playback_stream[j];
745                         if (pcxhr_stream_scheduled_get_pipe(stream, &pipe)) {
746                                 err = pcxhr_set_format(stream);
747                                 err = pcxhr_update_r_buffer(stream);
748                         }
749                 }
750         }
751         /* start all the streams */
752         for (i = 0; i < mgr->num_cards; i++) {
753                 struct pcxhr_stream *stream;
754                 chip = mgr->chip[i];
755                 for (j = 0; j < chip->nb_streams_capt; j++) {
756                         stream = &chip->capture_stream[j];
757                         if (pcxhr_stream_scheduled_get_pipe(stream, &pipe))
758                                 err = pcxhr_set_stream_state(stream);
759                 }
760                 for (j = 0; j < chip->nb_streams_play; j++) {
761                         stream = &chip->playback_stream[j];
762                         if (pcxhr_stream_scheduled_get_pipe(stream, &pipe))
763                                 err = pcxhr_set_stream_state(stream);
764                 }
765         }
766 
767         /* synchronous start of all the pipes concerned */
768         err = pcxhr_set_pipe_state(mgr, playback_mask, capture_mask, 1);
769         if (err) {
770                 mutex_unlock(&mgr->setup_mutex);
771                 snd_printk(KERN_ERR "pcxhr_trigger_tasklet : "
772                            "error start pipes (P%x C%x)\n",
773                            playback_mask, capture_mask);
774                 return;
775         }
776 
777         /* put the streams into the running state now
778          * (increment pointer by interrupt)
779          */
780         spin_lock_irqsave(&mgr->lock, flags);
781         for ( i =0; i < mgr->num_cards; i++) {
782                 struct pcxhr_stream *stream;
783                 chip = mgr->chip[i];
784                 for(j = 0; j < chip->nb_streams_capt; j++) {
785                         stream = &chip->capture_stream[j];
786                         if(stream->status == PCXHR_STREAM_STATUS_STARTED)
787                                 stream->status = PCXHR_STREAM_STATUS_RUNNING;
788                 }
789                 for (j = 0; j < chip->nb_streams_play; j++) {
790                         stream = &chip->playback_stream[j];
791                         if (stream->status == PCXHR_STREAM_STATUS_STARTED) {
792                                 /* playback will already have advanced ! */
793                                 stream->timer_period_frag += mgr->granularity;
794                                 stream->status = PCXHR_STREAM_STATUS_RUNNING;
795                         }
796                 }
797         }
798         spin_unlock_irqrestore(&mgr->lock, flags);
799 
800         mutex_unlock(&mgr->setup_mutex);
801 
802 #ifdef CONFIG_SND_DEBUG_VERBOSE
803         do_gettimeofday(&my_tv2);
804         snd_printdd("***TRIGGER TASKLET*** TIME = %ld (err = %x)\n",
805                     (long)(my_tv2.tv_usec - my_tv1.tv_usec), err);
806 #endif
807 }
808 
809 
810 /*
811  *  trigger callback
812  */
813 static int pcxhr_trigger(struct snd_pcm_substream *subs, int cmd)
814 {
815         struct pcxhr_stream *stream;
816         struct snd_pcm_substream *s;
817 
818         switch (cmd) {
819         case SNDRV_PCM_TRIGGER_START:
820                 snd_printdd("SNDRV_PCM_TRIGGER_START\n");
821                 if (snd_pcm_stream_linked(subs)) {
822                         struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
823                         snd_pcm_group_for_each_entry(s, subs) {
824                                 if (snd_pcm_substream_chip(s) != chip)
825                                         continue;
826                                 stream = s->runtime->private_data;
827                                 stream->status =
828                                         PCXHR_STREAM_STATUS_SCHEDULE_RUN;
829                                 snd_pcm_trigger_done(s, subs);
830                         }
831                         tasklet_schedule(&chip->mgr->trigger_taskq);
832                 } else {
833                         stream = subs->runtime->private_data;
834                         snd_printdd("Only one Substream %c %d\n",
835                                     stream->pipe->is_capture ? 'C' : 'P',
836                                     stream->pipe->first_audio);
837                         if (pcxhr_set_format(stream))
838                                 return -EINVAL;
839                         if (pcxhr_update_r_buffer(stream))
840                                 return -EINVAL;
841 
842                         stream->status = PCXHR_STREAM_STATUS_SCHEDULE_RUN;
843                         if (pcxhr_set_stream_state(stream))
844                                 return -EINVAL;
845                         stream->status = PCXHR_STREAM_STATUS_RUNNING;
846                 }
847                 break;
848         case SNDRV_PCM_TRIGGER_STOP:
849                 snd_printdd("SNDRV_PCM_TRIGGER_STOP\n");
850                 snd_pcm_group_for_each_entry(s, subs) {
851                         stream = s->runtime->private_data;
852                         stream->status = PCXHR_STREAM_STATUS_SCHEDULE_STOP;
853                         if (pcxhr_set_stream_state(stream))
854                                 return -EINVAL;
855                         snd_pcm_trigger_done(s, subs);
856                 }
857                 break;
858         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
859         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
860                 /* TODO */
861         default:
862                 return -EINVAL;
863         }
864         return 0;
865 }
866 
867 
868 static int pcxhr_hardware_timer(struct pcxhr_mgr *mgr, int start)
869 {
870         struct pcxhr_rmh rmh;
871         int err;
872 
873         pcxhr_init_rmh(&rmh, CMD_SET_TIMER_INTERRUPT);
874         if (start) {
875                 /* last dsp time invalid */
876                 mgr->dsp_time_last = PCXHR_DSP_TIME_INVALID;
877                 rmh.cmd[0] |= mgr->granularity;
878         }
879         err = pcxhr_send_msg(mgr, &rmh);
880         if (err < 0)
881                 snd_printk(KERN_ERR "error pcxhr_hardware_timer err(%x)\n",
882                            err);
883         return err;
884 }
885 
886 /*
887  *  prepare callback for all pcms
888  */
889 static int pcxhr_prepare(struct snd_pcm_substream *subs)
890 {
891         struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
892         struct pcxhr_mgr *mgr = chip->mgr;
893         int err = 0;
894 
895         snd_printdd("pcxhr_prepare : period_size(%lx) periods(%x) buffer_size(%lx)\n",
896                     subs->runtime->period_size, subs->runtime->periods,
897                     subs->runtime->buffer_size);
898 
899         mutex_lock(&mgr->setup_mutex);
900 
901         do {
902                 /* only the first stream can choose the sample rate */
903                 /* set the clock only once (first stream) */
904                 if (mgr->sample_rate != subs->runtime->rate) {
905                         err = pcxhr_set_clock(mgr, subs->runtime->rate);
906                         if (err)
907                                 break;
908                         if (mgr->sample_rate == 0)
909                                 /* start the DSP-timer */
910                                 err = pcxhr_hardware_timer(mgr, 1);
911                         mgr->sample_rate = subs->runtime->rate;
912                 }
913         } while(0);     /* do only once (so we can use break instead of goto) */
914 
915         mutex_unlock(&mgr->setup_mutex);
916 
917         return err;
918 }
919 
920 
921 /*
922  *  HW_PARAMS callback for all pcms
923  */
924 static int pcxhr_hw_params(struct snd_pcm_substream *subs,
925                            struct snd_pcm_hw_params *hw)
926 {
927         struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
928         struct pcxhr_mgr *mgr = chip->mgr;
929         struct pcxhr_stream *stream = subs->runtime->private_data;
930         snd_pcm_format_t format;
931         int err;
932         int channels;
933 
934         /* set up channels */
935         channels = params_channels(hw);
936 
937         /*  set up format for the stream */
938         format = params_format(hw);
939 
940         mutex_lock(&mgr->setup_mutex);
941 
942         stream->channels = channels;
943         stream->format = format;
944 
945         /* allocate buffer */
946         err = snd_pcm_lib_malloc_pages(subs, params_buffer_bytes(hw));
947 
948         mutex_unlock(&mgr->setup_mutex);
949 
950         return err;
951 }
952 
953 static int pcxhr_hw_free(struct snd_pcm_substream *subs)
954 {
955         snd_pcm_lib_free_pages(subs);
956         return 0;
957 }
958 
959 
960 /*
961  *  CONFIGURATION SPACE for all pcms, mono pcm must update channels_max
962  */
963 static struct snd_pcm_hardware pcxhr_caps =
964 {
965         .info             = (SNDRV_PCM_INFO_MMAP |
966                              SNDRV_PCM_INFO_INTERLEAVED |
967                              SNDRV_PCM_INFO_MMAP_VALID |
968                              SNDRV_PCM_INFO_SYNC_START),
969         .formats          = (SNDRV_PCM_FMTBIT_U8 |
970                              SNDRV_PCM_FMTBIT_S16_LE |
971                              SNDRV_PCM_FMTBIT_S16_BE |
972                              SNDRV_PCM_FMTBIT_S24_3LE |
973                              SNDRV_PCM_FMTBIT_S24_3BE |
974                              SNDRV_PCM_FMTBIT_FLOAT_LE),
975         .rates            = (SNDRV_PCM_RATE_CONTINUOUS |
976                              SNDRV_PCM_RATE_8000_192000),
977         .rate_min         = 8000,
978         .rate_max         = 192000,
979         .channels_min     = 1,
980         .channels_max     = 2,
981         .buffer_bytes_max = (32*1024),
982         /* 1 byte == 1 frame U8 mono (PCXHR_GRANULARITY is frames!) */
983         .period_bytes_min = (2*PCXHR_GRANULARITY),
984         .period_bytes_max = (16*1024),
985         .periods_min      = 2,
986         .periods_max      = (32*1024/PCXHR_GRANULARITY),
987 };
988 
989 
990 static int pcxhr_open(struct snd_pcm_substream *subs)
991 {
992         struct snd_pcxhr       *chip = snd_pcm_substream_chip(subs);
993         struct pcxhr_mgr       *mgr = chip->mgr;
994         struct snd_pcm_runtime *runtime = subs->runtime;
995         struct pcxhr_stream    *stream;
996         int err;
997 
998         mutex_lock(&mgr->setup_mutex);
999 
1000         /* copy the struct snd_pcm_hardware struct */
1001         runtime->hw = pcxhr_caps;
1002 
1003         if( subs->stream == SNDRV_PCM_STREAM_PLAYBACK ) {
1004                 snd_printdd("pcxhr_open playback chip%d subs%d\n",
1005                             chip->chip_idx, subs->number);
1006                 stream = &chip->playback_stream[subs->number];
1007         } else {
1008                 snd_printdd("pcxhr_open capture chip%d subs%d\n",
1009                             chip->chip_idx, subs->number);
1010                 if (mgr->mono_capture)
1011                         runtime->hw.channels_max = 1;
1012                 else
1013                         runtime->hw.channels_min = 2;
1014                 stream = &chip->capture_stream[subs->number];
1015         }
1016         if (stream->status != PCXHR_STREAM_STATUS_FREE){
1017                 /* streams in use */
1018                 snd_printk(KERN_ERR "pcxhr_open chip%d subs%d in use\n",
1019                            chip->chip_idx, subs->number);
1020                 mutex_unlock(&mgr->setup_mutex);
1021                 return -EBUSY;
1022         }
1023 
1024         /* float format support is in some cases buggy on stereo cards */
1025         if (mgr->is_hr_stereo)
1026                 runtime->hw.formats &= ~SNDRV_PCM_FMTBIT_FLOAT_LE;
1027 
1028         /* buffer-size should better be multiple of period-size */
1029         err = snd_pcm_hw_constraint_integer(runtime,
1030                                             SNDRV_PCM_HW_PARAM_PERIODS);
1031         if (err < 0) {
1032                 mutex_unlock(&mgr->setup_mutex);
1033                 return err;
1034         }
1035 
1036         /* if a sample rate is already used or fixed by external clock,
1037          * the stream cannot change
1038          */
1039         if (mgr->sample_rate)
1040                 runtime->hw.rate_min = runtime->hw.rate_max = mgr->sample_rate;
1041         else {
1042                 if (mgr->use_clock_type != PCXHR_CLOCK_TYPE_INTERNAL) {
1043                         int external_rate;
1044                         if (pcxhr_get_external_clock(mgr, mgr->use_clock_type,
1045                                                      &external_rate) ||
1046                             external_rate == 0) {
1047                                 /* cannot detect the external clock rate */
1048                                 mutex_unlock(&mgr->setup_mutex);
1049                                 return -EBUSY;
1050                         }
1051                         runtime->hw.rate_min = external_rate;
1052                         runtime->hw.rate_max = external_rate;
1053                 }
1054         }
1055 
1056         stream->status      = PCXHR_STREAM_STATUS_OPEN;
1057         stream->substream   = subs;
1058         stream->channels    = 0; /* not configured yet */
1059 
1060         runtime->private_data = stream;
1061 
1062         /* better get a divisor of granularity values (96 or 192) */
1063         snd_pcm_hw_constraint_step(runtime, 0,
1064                                    SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 32);
1065         snd_pcm_hw_constraint_step(runtime, 0,
1066                                    SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 32);
1067         snd_pcm_set_sync(subs);
1068 
1069         mgr->ref_count_rate++;
1070 
1071         mutex_unlock(&mgr->setup_mutex);
1072         return 0;
1073 }
1074 
1075 
1076 static int pcxhr_close(struct snd_pcm_substream *subs)
1077 {
1078         struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
1079         struct pcxhr_mgr *mgr = chip->mgr;
1080         struct pcxhr_stream *stream = subs->runtime->private_data;
1081 
1082         mutex_lock(&mgr->setup_mutex);
1083 
1084         snd_printdd("pcxhr_close chip%d subs%d\n",
1085                     chip->chip_idx, subs->number);
1086 
1087         /* sample rate released */
1088         if (--mgr->ref_count_rate == 0) {
1089                 mgr->sample_rate = 0;   /* the sample rate is no more locked */
1090                 pcxhr_hardware_timer(mgr, 0);   /* stop the DSP-timer */
1091         }
1092 
1093         stream->status    = PCXHR_STREAM_STATUS_FREE;
1094         stream->substream = NULL;
1095 
1096         mutex_unlock(&mgr->setup_mutex);
1097 
1098         return 0;
1099 }
1100 
1101 
1102 static snd_pcm_uframes_t pcxhr_stream_pointer(struct snd_pcm_substream *subs)
1103 {
1104         unsigned long flags;
1105         u_int32_t timer_period_frag;
1106         int timer_buf_periods;
1107         struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
1108         struct snd_pcm_runtime *runtime = subs->runtime;
1109         struct pcxhr_stream *stream  = runtime->private_data;
1110 
1111         spin_lock_irqsave(&chip->mgr->lock, flags);
1112 
1113         /* get the period fragment and the nb of periods in the buffer */
1114         timer_period_frag = stream->timer_period_frag;
1115         timer_buf_periods = stream->timer_buf_periods;
1116 
1117         spin_unlock_irqrestore(&chip->mgr->lock, flags);
1118 
1119         return (snd_pcm_uframes_t)((timer_buf_periods * runtime->period_size) +
1120                                    timer_period_frag);
1121 }
1122 
1123 
1124 static struct snd_pcm_ops pcxhr_ops = {
1125         .open      = pcxhr_open,
1126         .close     = pcxhr_close,
1127         .ioctl     = snd_pcm_lib_ioctl,
1128         .prepare   = pcxhr_prepare,
1129         .hw_params = pcxhr_hw_params,
1130         .hw_free   = pcxhr_hw_free,
1131         .trigger   = pcxhr_trigger,
1132         .pointer   = pcxhr_stream_pointer,
1133 };
1134 
1135 /*
1136  */
1137 int pcxhr_create_pcm(struct snd_pcxhr *chip)
1138 {
1139         int err;
1140         struct snd_pcm *pcm;
1141         char name[32];
1142 
1143         sprintf(name, "pcxhr %d", chip->chip_idx);
1144         if ((err = snd_pcm_new(chip->card, name, 0,
1145                                chip->nb_streams_play,
1146                                chip->nb_streams_capt, &pcm)) < 0) {
1147                 snd_printk(KERN_ERR "cannot create pcm %s\n", name);
1148                 return err;
1149         }
1150         pcm->private_data = chip;
1151 
1152         if (chip->nb_streams_play)
1153                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &pcxhr_ops);
1154         if (chip->nb_streams_capt)
1155                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &pcxhr_ops);
1156 
1157         pcm->info_flags = 0;
1158         strcpy(pcm->name, name);
1159 
1160         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1161                                               snd_dma_pci_data(chip->mgr->pci),
1162                                               32*1024, 32*1024);
1163         chip->pcm = pcm;
1164         return 0;
1165 }
1166 
1167 static int pcxhr_chip_free(struct snd_pcxhr *chip)
1168 {
1169         kfree(chip);
1170         return 0;
1171 }
1172 
1173 static int pcxhr_chip_dev_free(struct snd_device *device)
1174 {
1175         struct snd_pcxhr *chip = device->device_data;
1176         return pcxhr_chip_free(chip);
1177 }
1178 
1179 
1180 /*
1181  */
1182 static int __devinit pcxhr_create(struct pcxhr_mgr *mgr,
1183                                   struct snd_card *card, int idx)
1184 {
1185         int err;
1186         struct snd_pcxhr *chip;
1187         static struct snd_device_ops ops = {
1188                 .dev_free = pcxhr_chip_dev_free,
1189         };
1190 
1191         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1192         if (! chip) {
1193                 snd_printk(KERN_ERR "cannot allocate chip\n");
1194                 return -ENOMEM;
1195         }
1196 
1197         chip->card = card;
1198         chip->chip_idx = idx;
1199         chip->mgr = mgr;
1200 
1201         if (idx < mgr->playback_chips)
1202                 /* stereo or mono streams */
1203                 chip->nb_streams_play = PCXHR_PLAYBACK_STREAMS;
1204 
1205         if (idx < mgr->capture_chips) {
1206                 if (mgr->mono_capture)
1207                         chip->nb_streams_capt = 2;      /* 2 mono streams */
1208                 else
1209                         chip->nb_streams_capt = 1;      /* or 1 stereo stream */
1210         }
1211 
1212         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1213                 pcxhr_chip_free(chip);
1214                 return err;
1215         }
1216 
1217         mgr->chip[idx] = chip;
1218         snd_card_set_dev(card, &mgr->pci->dev);
1219 
1220         return 0;
1221 }
1222 
1223 /* proc interface */
1224 static void pcxhr_proc_info(struct snd_info_entry *entry,
1225                             struct snd_info_buffer *buffer)
1226 {
1227         struct snd_pcxhr *chip = entry->private_data;
1228         struct pcxhr_mgr *mgr = chip->mgr;
1229 
1230         snd_iprintf(buffer, "\n%s\n", mgr->longname);
1231 
1232         /* stats available when embedded DSP is running */
1233         if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) {
1234                 struct pcxhr_rmh rmh;
1235                 short ver_maj = (mgr->dsp_version >> 16) & 0xff;
1236                 short ver_min = (mgr->dsp_version >> 8) & 0xff;
1237                 short ver_build = mgr->dsp_version & 0xff;
1238                 snd_iprintf(buffer, "module version %s\n",
1239                             PCXHR_DRIVER_VERSION_STRING);
1240                 snd_iprintf(buffer, "dsp version %d.%d.%d\n",
1241                             ver_maj, ver_min, ver_build);
1242                 if (mgr->board_has_analog)
1243                         snd_iprintf(buffer, "analog io available\n");
1244                 else
1245                         snd_iprintf(buffer, "digital only board\n");
1246 
1247                 /* calc cpu load of the dsp */
1248                 pcxhr_init_rmh(&rmh, CMD_GET_DSP_RESOURCES);
1249                 if( ! pcxhr_send_msg(mgr, &rmh) ) {
1250                         int cur = rmh.stat[0];
1251                         int ref = rmh.stat[1];
1252                         if (ref > 0) {
1253                                 if (mgr->sample_rate_real != 0 &&
1254                                     mgr->sample_rate_real != 48000) {
1255                                         ref = (ref * 48000) /
1256                                           mgr->sample_rate_real;
1257                                         if (mgr->sample_rate_real >=
1258                                             PCXHR_IRQ_TIMER_FREQ)
1259                                                 ref *= 2;
1260                                 }
1261                                 cur = 100 - (100 * cur) / ref;
1262                                 snd_iprintf(buffer, "cpu load    %d%%\n", cur);
1263                                 snd_iprintf(buffer, "buffer pool %d/%d\n",
1264                                             rmh.stat[2], rmh.stat[3]);
1265                         }
1266                 }
1267                 snd_iprintf(buffer, "dma granularity : %d\n",
1268                             mgr->granularity);
1269                 snd_iprintf(buffer, "dsp time errors : %d\n",
1270                             mgr->dsp_time_err);
1271                 snd_iprintf(buffer, "dsp async pipe xrun errors : %d\n",
1272                             mgr->async_err_pipe_xrun);
1273                 snd_iprintf(buffer, "dsp async stream xrun errors : %d\n",
1274                             mgr->async_err_stream_xrun);
1275                 snd_iprintf(buffer, "dsp async last other error : %x\n",
1276                             mgr->async_err_other_last);
1277                 /* debug zone dsp */
1278                 rmh.cmd[0] = 0x4200 + PCXHR_SIZE_MAX_STATUS;
1279                 rmh.cmd_len = 1;
1280                 rmh.stat_len = PCXHR_SIZE_MAX_STATUS;
1281                 rmh.dsp_stat = 0;
1282                 rmh.cmd_idx = CMD_LAST_INDEX;
1283                 if( ! pcxhr_send_msg(mgr, &rmh) ) {
1284                         int i;
1285                         if (rmh.stat_len > 8)
1286                                 rmh.stat_len = 8;
1287                         for (i = 0; i < rmh.stat_len; i++)
1288                                 snd_iprintf(buffer, "debug[%02d] = %06x\n",
1289                                             i,  rmh.stat[i]);
1290                 }
1291         } else
1292                 snd_iprintf(buffer, "no firmware loaded\n");
1293         snd_iprintf(buffer, "\n");
1294 }
1295 static void pcxhr_proc_sync(struct snd_info_entry *entry,
1296                             struct snd_info_buffer *buffer)
1297 {
1298         struct snd_pcxhr *chip = entry->private_data;
1299         struct pcxhr_mgr *mgr = chip->mgr;
1300         static const char *textsHR22[3] = {
1301                 "Internal", "AES Sync", "AES 1"
1302         };
1303         static const char *textsPCXHR[7] = {
1304                 "Internal", "Word", "AES Sync",
1305                 "AES 1", "AES 2", "AES 3", "AES 4"
1306         };
1307         const char **texts;
1308         int max_clock;
1309         if (mgr->is_hr_stereo) {
1310                 texts = textsHR22;
1311                 max_clock = HR22_CLOCK_TYPE_MAX;
1312         } else {
1313                 texts = textsPCXHR;
1314                 max_clock = PCXHR_CLOCK_TYPE_MAX;
1315         }
1316 
1317         snd_iprintf(buffer, "\n%s\n", mgr->longname);
1318         snd_iprintf(buffer, "Current Sample Clock\t: %s\n",
1319                     texts[mgr->cur_clock_type]);
1320         snd_iprintf(buffer, "Current Sample Rate\t= %d\n",
1321                     mgr->sample_rate_real);
1322         /* commands available when embedded DSP is running */
1323         if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) {
1324                 int i, err, sample_rate;
1325                 for (i = 1; i <= max_clock; i++) {
1326                         err = pcxhr_get_external_clock(mgr, i, &sample_rate);
1327                         if (err)
1328                                 break;
1329                         snd_iprintf(buffer, "%s Clock\t\t= %d\n",
1330                                     texts[i], sample_rate);
1331                 }
1332         } else
1333                 snd_iprintf(buffer, "no firmware loaded\n");
1334         snd_iprintf(buffer, "\n");
1335 }
1336 
1337 static void pcxhr_proc_gpio_read(struct snd_info_entry *entry,
1338                                  struct snd_info_buffer *buffer)
1339 {
1340         struct snd_pcxhr *chip = entry->private_data;
1341         struct pcxhr_mgr *mgr = chip->mgr;
1342         /* commands available when embedded DSP is running */
1343         if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) {
1344                 /* gpio ports on stereo boards only available */
1345                 int value = 0;
1346                 hr222_read_gpio(mgr, 1, &value);        /* GPI */
1347                 snd_iprintf(buffer, "GPI: 0x%x\n", value);
1348                 hr222_read_gpio(mgr, 0, &value);        /* GP0 */
1349                 snd_iprintf(buffer, "GPO: 0x%x\n", value);
1350         } else
1351                 snd_iprintf(buffer, "no firmware loaded\n");
1352         snd_iprintf(buffer, "\n");
1353 }
1354 static void pcxhr_proc_gpo_write(struct snd_info_entry *entry,
1355                                  struct snd_info_buffer *buffer)
1356 {
1357         struct snd_pcxhr *chip = entry->private_data;
1358         struct pcxhr_mgr *mgr = chip->mgr;
1359         char line[64];
1360         int value;
1361         /* commands available when embedded DSP is running */
1362         if (!(mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)))
1363                 return;
1364         while (!snd_info_get_line(buffer, line, sizeof(line))) {
1365                 if (sscanf(line, "GPO: 0x%x", &value) != 1)
1366                         continue;
1367                 hr222_write_gpo(mgr, value);    /* GP0 */
1368         }
1369 }
1370 
1371 static void __devinit pcxhr_proc_init(struct snd_pcxhr *chip)
1372 {
1373         struct snd_info_entry *entry;
1374 
1375         if (! snd_card_proc_new(chip->card, "info", &entry))
1376                 snd_info_set_text_ops(entry, chip, pcxhr_proc_info);
1377         if (! snd_card_proc_new(chip->card, "sync", &entry))
1378                 snd_info_set_text_ops(entry, chip, pcxhr_proc_sync);
1379         /* gpio available on stereo sound cards only */
1380         if (chip->mgr->is_hr_stereo &&
1381             !snd_card_proc_new(chip->card, "gpio", &entry)) {
1382                 snd_info_set_text_ops(entry, chip, pcxhr_proc_gpio_read);
1383                 entry->c.text.write = pcxhr_proc_gpo_write;
1384                 entry->mode |= S_IWUSR;
1385         }
1386 }
1387 /* end of proc interface */
1388 
1389 /*
1390  * release all the cards assigned to a manager instance
1391  */
1392 static int pcxhr_free(struct pcxhr_mgr *mgr)
1393 {
1394         unsigned int i;
1395 
1396         for (i = 0; i < mgr->num_cards; i++) {
1397                 if (mgr->chip[i])
1398                         snd_card_free(mgr->chip[i]->card);
1399         }
1400 
1401         /* reset board if some firmware was loaded */
1402         if(mgr->dsp_loaded) {
1403                 pcxhr_reset_board(mgr);
1404                 snd_printdd("reset pcxhr !\n");
1405         }
1406 
1407         /* release irq  */
1408         if (mgr->irq >= 0)
1409                 free_irq(mgr->irq, mgr);
1410 
1411         pci_release_regions(mgr->pci);
1412 
1413         /* free hostport purgebuffer */
1414         if (mgr->hostport.area) {
1415                 snd_dma_free_pages(&mgr->hostport);
1416                 mgr->hostport.area = NULL;
1417         }
1418 
1419         kfree(mgr->prmh);
1420 
1421         pci_disable_device(mgr->pci);
1422         kfree(mgr);
1423         return 0;
1424 }
1425 
1426 /*
1427  *    probe function - creates the card manager
1428  */
1429 static int __devinit pcxhr_probe(struct pci_dev *pci,
1430                                  const struct pci_device_id *pci_id)
1431 {
1432         static int dev;
1433         struct pcxhr_mgr *mgr;
1434         unsigned int i;
1435         int err;
1436         size_t size;
1437         char *card_name;
1438 
1439         if (dev >= SNDRV_CARDS)
1440                 return -ENODEV;
1441         if (! enable[dev]) {
1442                 dev++;
1443                 return -ENOENT;
1444         }
1445 
1446         /* enable PCI device */
1447         if ((err = pci_enable_device(pci)) < 0)
1448                 return err;
1449         pci_set_master(pci);
1450 
1451         /* check if we can restrict PCI DMA transfers to 32 bits */
1452         if (pci_set_dma_mask(pci, DMA_BIT_MASK(32)) < 0) {
1453                 snd_printk(KERN_ERR "architecture does not support "
1454                            "32bit PCI busmaster DMA\n");
1455                 pci_disable_device(pci);
1456                 return -ENXIO;
1457         }
1458 
1459         /* alloc card manager */
1460         mgr = kzalloc(sizeof(*mgr), GFP_KERNEL);
1461         if (! mgr) {
1462                 pci_disable_device(pci);
1463                 return -ENOMEM;
1464         }
1465 
1466         if (snd_BUG_ON(pci_id->driver_data >= PCI_ID_LAST)) {
1467                 kfree(mgr);
1468                 pci_disable_device(pci);
1469                 return -ENODEV;
1470         }
1471         card_name =
1472                 pcxhr_board_params[pci_id->driver_data].board_name;
1473         mgr->playback_chips =
1474                 pcxhr_board_params[pci_id->driver_data].playback_chips;
1475         mgr->capture_chips  =
1476                 pcxhr_board_params[pci_id->driver_data].capture_chips;
1477         mgr->fw_file_set =
1478                 pcxhr_board_params[pci_id->driver_data].fw_file_set;
1479         mgr->firmware_num  =
1480                 pcxhr_board_params[pci_id->driver_data].firmware_num;
1481         mgr->mono_capture = mono[dev];
1482         mgr->is_hr_stereo = (mgr->playback_chips == 1);
1483         mgr->board_has_aes1 = PCXHR_BOARD_HAS_AES1(mgr);
1484         mgr->board_aes_in_192k = !PCXHR_BOARD_AESIN_NO_192K(mgr);
1485 
1486         if (mgr->is_hr_stereo)
1487                 mgr->granularity = PCXHR_GRANULARITY_HR22;
1488         else
1489                 mgr->granularity = PCXHR_GRANULARITY;
1490 
1491         /* resource assignment */
1492         if ((err = pci_request_regions(pci, card_name)) < 0) {
1493                 kfree(mgr);
1494                 pci_disable_device(pci);
1495                 return err;
1496         }
1497         for (i = 0; i < 3; i++)
1498                 mgr->port[i] = pci_resource_start(pci, i);
1499 
1500         mgr->pci = pci;
1501         mgr->irq = -1;
1502 
1503         if (request_irq(pci->irq, pcxhr_interrupt, IRQF_SHARED,
1504                         card_name, mgr)) {
1505                 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1506                 pcxhr_free(mgr);
1507                 return -EBUSY;
1508         }
1509         mgr->irq = pci->irq;
1510 
1511         sprintf(mgr->shortname, "Digigram %s", card_name);
1512         sprintf(mgr->longname, "%s at 0x%lx & 0x%lx, 0x%lx irq %i",
1513                 mgr->shortname,
1514                 mgr->port[0], mgr->port[1], mgr->port[2], mgr->irq);
1515 
1516         /* ISR spinlock  */
1517         spin_lock_init(&mgr->lock);
1518         spin_lock_init(&mgr->msg_lock);
1519 
1520         /* init setup mutex*/
1521         mutex_init(&mgr->setup_mutex);
1522 
1523         /* init taslket */
1524         tasklet_init(&mgr->msg_taskq, pcxhr_msg_tasklet,
1525                      (unsigned long) mgr);
1526         tasklet_init(&mgr->trigger_taskq, pcxhr_trigger_tasklet,
1527                      (unsigned long) mgr);
1528 
1529         mgr->prmh = kmalloc(sizeof(*mgr->prmh) + 
1530                             sizeof(u32) * (PCXHR_SIZE_MAX_LONG_STATUS -
1531                                            PCXHR_SIZE_MAX_STATUS),
1532                             GFP_KERNEL);
1533         if (! mgr->prmh) {
1534                 pcxhr_free(mgr);
1535                 return -ENOMEM;
1536         }
1537 
1538         for (i=0; i < PCXHR_MAX_CARDS; i++) {
1539                 struct snd_card *card;
1540                 char tmpid[16];
1541                 int idx;
1542 
1543                 if (i >= max(mgr->playback_chips, mgr->capture_chips))
1544                         break;
1545                 mgr->num_cards++;
1546 
1547                 if (index[dev] < 0)
1548                         idx = index[dev];
1549                 else
1550                         idx = index[dev] + i;
1551 
1552                 snprintf(tmpid, sizeof(tmpid), "%s-%d",
1553                          id[dev] ? id[dev] : card_name, i);
1554                 err = snd_card_create(idx, tmpid, THIS_MODULE, 0, &card);
1555 
1556                 if (err < 0) {
1557                         snd_printk(KERN_ERR "cannot allocate the card %d\n", i);
1558                         pcxhr_free(mgr);
1559                         return err;
1560                 }
1561 
1562                 strcpy(card->driver, DRIVER_NAME);
1563                 sprintf(card->shortname, "%s [PCM #%d]", mgr->shortname, i);
1564                 sprintf(card->longname, "%s [PCM #%d]", mgr->longname, i);
1565 
1566                 if ((err = pcxhr_create(mgr, card, i)) < 0) {
1567                         snd_card_free(card);
1568                         pcxhr_free(mgr);
1569                         return err;
1570                 }
1571 
1572                 if (i == 0)
1573                         /* init proc interface only for chip0 */
1574                         pcxhr_proc_init(mgr->chip[i]);
1575 
1576                 if ((err = snd_card_register(card)) < 0) {
1577                         pcxhr_free(mgr);
1578                         return err;
1579                 }
1580         }
1581 
1582         /* create hostport purgebuffer */
1583         size = PAGE_ALIGN(sizeof(struct pcxhr_hostport));
1584         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
1585                                 size, &mgr->hostport) < 0) {
1586                 pcxhr_free(mgr);
1587                 return -ENOMEM;
1588         }
1589         /* init purgebuffer */
1590         memset(mgr->hostport.area, 0, size);
1591 
1592         /* create a DSP loader */
1593         err = pcxhr_setup_firmware(mgr);
1594         if (err < 0) {
1595                 pcxhr_free(mgr);
1596                 return err;
1597         }
1598 
1599         pci_set_drvdata(pci, mgr);
1600         dev++;
1601         return 0;
1602 }
1603 
1604 static void __devexit pcxhr_remove(struct pci_dev *pci)
1605 {
1606         pcxhr_free(pci_get_drvdata(pci));
1607         pci_set_drvdata(pci, NULL);
1608 }
1609 
1610 static struct pci_driver driver = {
1611         .name = "Digigram pcxhr",
1612         .id_table = pcxhr_ids,
1613         .probe = pcxhr_probe,
1614         .remove = __devexit_p(pcxhr_remove),
1615 };
1616 
1617 static int __init pcxhr_module_init(void)
1618 {
1619         return pci_register_driver(&driver);
1620 }
1621 
1622 static void __exit pcxhr_module_exit(void)
1623 {
1624         pci_unregister_driver(&driver);
1625 }
1626 
1627 module_init(pcxhr_module_init)
1628 module_exit(pcxhr_module_exit)
1629 

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