~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

TOMOYO Linux Cross Reference
Linux/sound/pci/rme96.c

Version: ~ [ linux-5.5-rc7 ] ~ [ linux-5.4.13 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.97 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.166 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.210 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.210 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.19.8 ] ~ [ linux-3.18.140 ] ~ [ linux-3.17.8 ] ~ [ linux-3.16.81 ] ~ [ linux-3.15.10 ] ~ [ linux-3.14.79 ] ~ [ linux-3.13.11 ] ~ [ linux-3.12.74 ] ~ [ linux-3.11.10 ] ~ [ linux-3.10.108 ] ~ [ linux-3.9.11 ] ~ [ linux-3.8.13 ] ~ [ linux-3.7.10 ] ~ [ linux-3.6.11 ] ~ [ linux-3.5.7 ] ~ [ linux-3.4.113 ] ~ [ linux-3.3.8 ] ~ [ linux-3.2.102 ] ~ [ linux-3.1.10 ] ~ [ linux-3.0.101 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.5 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  *   ALSA driver for RME Digi96, Digi96/8 and Digi96/8 PRO/PAD/PST audio
  3  *   interfaces 
  4  *
  5  *      Copyright (c) 2000, 2001 Anders Torger <torger@ludd.luth.se>
  6  *    
  7  *      Thanks to Henk Hesselink <henk@anda.nl> for the analog volume control
  8  *      code.
  9  *
 10  *   This program is free software; you can redistribute it and/or modify
 11  *   it under the terms of the GNU General Public License as published by
 12  *   the Free Software Foundation; either version 2 of the License, or
 13  *   (at your option) any later version.
 14  *
 15  *   This program is distributed in the hope that it will be useful,
 16  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 17  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 18  *   GNU General Public License for more details.
 19  *
 20  *   You should have received a copy of the GNU General Public License
 21  *   along with this program; if not, write to the Free Software
 22  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 23  *
 24  */      
 25 
 26 #include <linux/delay.h>
 27 #include <linux/init.h>
 28 #include <linux/interrupt.h>
 29 #include <linux/pci.h>
 30 #include <linux/module.h>
 31 #include <linux/vmalloc.h>
 32 
 33 #include <sound/core.h>
 34 #include <sound/info.h>
 35 #include <sound/control.h>
 36 #include <sound/pcm.h>
 37 #include <sound/pcm_params.h>
 38 #include <sound/asoundef.h>
 39 #include <sound/initval.h>
 40 
 41 #include <asm/io.h>
 42 
 43 /* note, two last pcis should be equal, it is not a bug */
 44 
 45 MODULE_AUTHOR("Anders Torger <torger@ludd.luth.se>");
 46 MODULE_DESCRIPTION("RME Digi96, Digi96/8, Digi96/8 PRO, Digi96/8 PST, "
 47                    "Digi96/8 PAD");
 48 MODULE_LICENSE("GPL");
 49 MODULE_SUPPORTED_DEVICE("{{RME,Digi96},"
 50                 "{RME,Digi96/8},"
 51                 "{RME,Digi96/8 PRO},"
 52                 "{RME,Digi96/8 PST},"
 53                 "{RME,Digi96/8 PAD}}");
 54 
 55 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
 56 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
 57 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;     /* Enable this card */
 58 
 59 module_param_array(index, int, NULL, 0444);
 60 MODULE_PARM_DESC(index, "Index value for RME Digi96 soundcard.");
 61 module_param_array(id, charp, NULL, 0444);
 62 MODULE_PARM_DESC(id, "ID string for RME Digi96 soundcard.");
 63 module_param_array(enable, bool, NULL, 0444);
 64 MODULE_PARM_DESC(enable, "Enable RME Digi96 soundcard.");
 65 
 66 /*
 67  * Defines for RME Digi96 series, from internal RME reference documents
 68  * dated 12.01.00
 69  */
 70 
 71 #define RME96_SPDIF_NCHANNELS 2
 72 
 73 /* Playback and capture buffer size */
 74 #define RME96_BUFFER_SIZE 0x10000
 75 
 76 /* IO area size */
 77 #define RME96_IO_SIZE 0x60000
 78 
 79 /* IO area offsets */
 80 #define RME96_IO_PLAY_BUFFER      0x0
 81 #define RME96_IO_REC_BUFFER       0x10000
 82 #define RME96_IO_CONTROL_REGISTER 0x20000
 83 #define RME96_IO_ADDITIONAL_REG   0x20004
 84 #define RME96_IO_CONFIRM_PLAY_IRQ 0x20008
 85 #define RME96_IO_CONFIRM_REC_IRQ  0x2000C
 86 #define RME96_IO_SET_PLAY_POS     0x40000
 87 #define RME96_IO_RESET_PLAY_POS   0x4FFFC
 88 #define RME96_IO_SET_REC_POS      0x50000
 89 #define RME96_IO_RESET_REC_POS    0x5FFFC
 90 #define RME96_IO_GET_PLAY_POS     0x20000
 91 #define RME96_IO_GET_REC_POS      0x30000
 92 
 93 /* Write control register bits */
 94 #define RME96_WCR_START     (1 << 0)
 95 #define RME96_WCR_START_2   (1 << 1)
 96 #define RME96_WCR_GAIN_0    (1 << 2)
 97 #define RME96_WCR_GAIN_1    (1 << 3)
 98 #define RME96_WCR_MODE24    (1 << 4)
 99 #define RME96_WCR_MODE24_2  (1 << 5)
100 #define RME96_WCR_BM        (1 << 6)
101 #define RME96_WCR_BM_2      (1 << 7)
102 #define RME96_WCR_ADAT      (1 << 8)
103 #define RME96_WCR_FREQ_0    (1 << 9)
104 #define RME96_WCR_FREQ_1    (1 << 10)
105 #define RME96_WCR_DS        (1 << 11)
106 #define RME96_WCR_PRO       (1 << 12)
107 #define RME96_WCR_EMP       (1 << 13)
108 #define RME96_WCR_SEL       (1 << 14)
109 #define RME96_WCR_MASTER    (1 << 15)
110 #define RME96_WCR_PD        (1 << 16)
111 #define RME96_WCR_INP_0     (1 << 17)
112 #define RME96_WCR_INP_1     (1 << 18)
113 #define RME96_WCR_THRU_0    (1 << 19)
114 #define RME96_WCR_THRU_1    (1 << 20)
115 #define RME96_WCR_THRU_2    (1 << 21)
116 #define RME96_WCR_THRU_3    (1 << 22)
117 #define RME96_WCR_THRU_4    (1 << 23)
118 #define RME96_WCR_THRU_5    (1 << 24)
119 #define RME96_WCR_THRU_6    (1 << 25)
120 #define RME96_WCR_THRU_7    (1 << 26)
121 #define RME96_WCR_DOLBY     (1 << 27)
122 #define RME96_WCR_MONITOR_0 (1 << 28)
123 #define RME96_WCR_MONITOR_1 (1 << 29)
124 #define RME96_WCR_ISEL      (1 << 30)
125 #define RME96_WCR_IDIS      (1 << 31)
126 
127 #define RME96_WCR_BITPOS_GAIN_0 2
128 #define RME96_WCR_BITPOS_GAIN_1 3
129 #define RME96_WCR_BITPOS_FREQ_0 9
130 #define RME96_WCR_BITPOS_FREQ_1 10
131 #define RME96_WCR_BITPOS_INP_0 17
132 #define RME96_WCR_BITPOS_INP_1 18
133 #define RME96_WCR_BITPOS_MONITOR_0 28
134 #define RME96_WCR_BITPOS_MONITOR_1 29
135 
136 /* Read control register bits */
137 #define RME96_RCR_AUDIO_ADDR_MASK 0xFFFF
138 #define RME96_RCR_IRQ_2     (1 << 16)
139 #define RME96_RCR_T_OUT     (1 << 17)
140 #define RME96_RCR_DEV_ID_0  (1 << 21)
141 #define RME96_RCR_DEV_ID_1  (1 << 22)
142 #define RME96_RCR_LOCK      (1 << 23)
143 #define RME96_RCR_VERF      (1 << 26)
144 #define RME96_RCR_F0        (1 << 27)
145 #define RME96_RCR_F1        (1 << 28)
146 #define RME96_RCR_F2        (1 << 29)
147 #define RME96_RCR_AUTOSYNC  (1 << 30)
148 #define RME96_RCR_IRQ       (1 << 31)
149 
150 #define RME96_RCR_BITPOS_F0 27
151 #define RME96_RCR_BITPOS_F1 28
152 #define RME96_RCR_BITPOS_F2 29
153 
154 /* Additional register bits */
155 #define RME96_AR_WSEL       (1 << 0)
156 #define RME96_AR_ANALOG     (1 << 1)
157 #define RME96_AR_FREQPAD_0  (1 << 2)
158 #define RME96_AR_FREQPAD_1  (1 << 3)
159 #define RME96_AR_FREQPAD_2  (1 << 4)
160 #define RME96_AR_PD2        (1 << 5)
161 #define RME96_AR_DAC_EN     (1 << 6)
162 #define RME96_AR_CLATCH     (1 << 7)
163 #define RME96_AR_CCLK       (1 << 8)
164 #define RME96_AR_CDATA      (1 << 9)
165 
166 #define RME96_AR_BITPOS_F0 2
167 #define RME96_AR_BITPOS_F1 3
168 #define RME96_AR_BITPOS_F2 4
169 
170 /* Monitor tracks */
171 #define RME96_MONITOR_TRACKS_1_2 0
172 #define RME96_MONITOR_TRACKS_3_4 1
173 #define RME96_MONITOR_TRACKS_5_6 2
174 #define RME96_MONITOR_TRACKS_7_8 3
175 
176 /* Attenuation */
177 #define RME96_ATTENUATION_0 0
178 #define RME96_ATTENUATION_6 1
179 #define RME96_ATTENUATION_12 2
180 #define RME96_ATTENUATION_18 3
181 
182 /* Input types */
183 #define RME96_INPUT_OPTICAL 0
184 #define RME96_INPUT_COAXIAL 1
185 #define RME96_INPUT_INTERNAL 2
186 #define RME96_INPUT_XLR 3
187 #define RME96_INPUT_ANALOG 4
188 
189 /* Clock modes */
190 #define RME96_CLOCKMODE_SLAVE 0
191 #define RME96_CLOCKMODE_MASTER 1
192 #define RME96_CLOCKMODE_WORDCLOCK 2
193 
194 /* Block sizes in bytes */
195 #define RME96_SMALL_BLOCK_SIZE 2048
196 #define RME96_LARGE_BLOCK_SIZE 8192
197 
198 /* Volume control */
199 #define RME96_AD1852_VOL_BITS 14
200 #define RME96_AD1855_VOL_BITS 10
201 
202 /* Defines for snd_rme96_trigger */
203 #define RME96_TB_START_PLAYBACK 1
204 #define RME96_TB_START_CAPTURE 2
205 #define RME96_TB_STOP_PLAYBACK 4
206 #define RME96_TB_STOP_CAPTURE 8
207 #define RME96_TB_RESET_PLAYPOS 16
208 #define RME96_TB_RESET_CAPTUREPOS 32
209 #define RME96_TB_CLEAR_PLAYBACK_IRQ 64
210 #define RME96_TB_CLEAR_CAPTURE_IRQ 128
211 #define RME96_RESUME_PLAYBACK   (RME96_TB_START_PLAYBACK)
212 #define RME96_RESUME_CAPTURE    (RME96_TB_START_CAPTURE)
213 #define RME96_RESUME_BOTH       (RME96_RESUME_PLAYBACK \
214                                 | RME96_RESUME_CAPTURE)
215 #define RME96_START_PLAYBACK    (RME96_TB_START_PLAYBACK \
216                                 | RME96_TB_RESET_PLAYPOS)
217 #define RME96_START_CAPTURE     (RME96_TB_START_CAPTURE \
218                                 | RME96_TB_RESET_CAPTUREPOS)
219 #define RME96_START_BOTH        (RME96_START_PLAYBACK \
220                                 | RME96_START_CAPTURE)
221 #define RME96_STOP_PLAYBACK     (RME96_TB_STOP_PLAYBACK \
222                                 | RME96_TB_CLEAR_PLAYBACK_IRQ)
223 #define RME96_STOP_CAPTURE      (RME96_TB_STOP_CAPTURE \
224                                 | RME96_TB_CLEAR_CAPTURE_IRQ)
225 #define RME96_STOP_BOTH         (RME96_STOP_PLAYBACK \
226                                 | RME96_STOP_CAPTURE)
227 
228 struct rme96 {
229         spinlock_t    lock;
230         int irq;
231         unsigned long port;
232         void __iomem *iobase;
233         
234         u32 wcreg;    /* cached write control register value */
235         u32 wcreg_spdif;                /* S/PDIF setup */
236         u32 wcreg_spdif_stream;         /* S/PDIF setup (temporary) */
237         u32 rcreg;    /* cached read control register value */
238         u32 areg;     /* cached additional register value */
239         u16 vol[2]; /* cached volume of analog output */
240 
241         u8 rev; /* card revision number */
242 
243 #ifdef CONFIG_PM
244         u32 playback_pointer;
245         u32 capture_pointer;
246         void *playback_suspend_buffer;
247         void *capture_suspend_buffer;
248 #endif
249 
250         struct snd_pcm_substream *playback_substream;
251         struct snd_pcm_substream *capture_substream;
252 
253         int playback_frlog; /* log2 of framesize */
254         int capture_frlog;
255         
256         size_t playback_periodsize; /* in bytes, zero if not used */
257         size_t capture_periodsize; /* in bytes, zero if not used */
258 
259         struct snd_card *card;
260         struct snd_pcm *spdif_pcm;
261         struct snd_pcm *adat_pcm; 
262         struct pci_dev     *pci;
263         struct snd_kcontrol   *spdif_ctl;
264 };
265 
266 static DEFINE_PCI_DEVICE_TABLE(snd_rme96_ids) = {
267         { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96), 0, },
268         { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8), 0, },
269         { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PRO), 0, },
270         { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST), 0, },
271         { 0, }
272 };
273 
274 MODULE_DEVICE_TABLE(pci, snd_rme96_ids);
275 
276 #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START)
277 #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2)
278 #define RME96_HAS_ANALOG_IN(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
279 #define RME96_HAS_ANALOG_OUT(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO || \
280                                      (rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
281 #define RME96_DAC_IS_1852(rme96) (RME96_HAS_ANALOG_OUT(rme96) && (rme96)->rev >= 4)
282 #define RME96_DAC_IS_1855(rme96) (((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && (rme96)->rev < 4) || \
283                                   ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO && (rme96)->rev == 2))
284 #define RME96_185X_MAX_OUT(rme96) ((1 << (RME96_DAC_IS_1852(rme96) ? RME96_AD1852_VOL_BITS : RME96_AD1855_VOL_BITS)) - 1)
285 
286 static int
287 snd_rme96_playback_prepare(struct snd_pcm_substream *substream);
288 
289 static int
290 snd_rme96_capture_prepare(struct snd_pcm_substream *substream);
291 
292 static int
293 snd_rme96_playback_trigger(struct snd_pcm_substream *substream, 
294                            int cmd);
295 
296 static int
297 snd_rme96_capture_trigger(struct snd_pcm_substream *substream, 
298                           int cmd);
299 
300 static snd_pcm_uframes_t
301 snd_rme96_playback_pointer(struct snd_pcm_substream *substream);
302 
303 static snd_pcm_uframes_t
304 snd_rme96_capture_pointer(struct snd_pcm_substream *substream);
305 
306 static void snd_rme96_proc_init(struct rme96 *rme96);
307 
308 static int
309 snd_rme96_create_switches(struct snd_card *card,
310                           struct rme96 *rme96);
311 
312 static int
313 snd_rme96_getinputtype(struct rme96 *rme96);
314 
315 static inline unsigned int
316 snd_rme96_playback_ptr(struct rme96 *rme96)
317 {
318         return (readl(rme96->iobase + RME96_IO_GET_PLAY_POS)
319                 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->playback_frlog;
320 }
321 
322 static inline unsigned int
323 snd_rme96_capture_ptr(struct rme96 *rme96)
324 {
325         return (readl(rme96->iobase + RME96_IO_GET_REC_POS)
326                 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->capture_frlog;
327 }
328 
329 static int
330 snd_rme96_playback_silence(struct snd_pcm_substream *substream,
331                            int channel, /* not used (interleaved data) */
332                            snd_pcm_uframes_t pos,
333                            snd_pcm_uframes_t count)
334 {
335         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
336         count <<= rme96->playback_frlog;
337         pos <<= rme96->playback_frlog;
338         memset_io(rme96->iobase + RME96_IO_PLAY_BUFFER + pos,
339                   0, count);
340         return 0;
341 }
342 
343 static int
344 snd_rme96_playback_copy(struct snd_pcm_substream *substream,
345                         int channel, /* not used (interleaved data) */
346                         snd_pcm_uframes_t pos,
347                         void __user *src,
348                         snd_pcm_uframes_t count)
349 {
350         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
351         count <<= rme96->playback_frlog;
352         pos <<= rme96->playback_frlog;
353         copy_from_user_toio(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, src,
354                             count);
355         return 0;
356 }
357 
358 static int
359 snd_rme96_capture_copy(struct snd_pcm_substream *substream,
360                        int channel, /* not used (interleaved data) */
361                        snd_pcm_uframes_t pos,
362                        void __user *dst,
363                        snd_pcm_uframes_t count)
364 {
365         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
366         count <<= rme96->capture_frlog;
367         pos <<= rme96->capture_frlog;
368         copy_to_user_fromio(dst, rme96->iobase + RME96_IO_REC_BUFFER + pos,
369                             count);
370         return 0;
371 }
372 
373 /*
374  * Digital output capabilities (S/PDIF)
375  */
376 static struct snd_pcm_hardware snd_rme96_playback_spdif_info =
377 {
378         .info =              (SNDRV_PCM_INFO_MMAP_IOMEM |
379                               SNDRV_PCM_INFO_MMAP_VALID |
380                               SNDRV_PCM_INFO_SYNC_START |
381                               SNDRV_PCM_INFO_RESUME |
382                               SNDRV_PCM_INFO_INTERLEAVED |
383                               SNDRV_PCM_INFO_PAUSE),
384         .formats =           (SNDRV_PCM_FMTBIT_S16_LE |
385                               SNDRV_PCM_FMTBIT_S32_LE),
386         .rates =             (SNDRV_PCM_RATE_32000 |
387                               SNDRV_PCM_RATE_44100 | 
388                               SNDRV_PCM_RATE_48000 | 
389                               SNDRV_PCM_RATE_64000 |
390                               SNDRV_PCM_RATE_88200 | 
391                               SNDRV_PCM_RATE_96000),
392         .rate_min =          32000,
393         .rate_max =          96000,
394         .channels_min =      2,
395         .channels_max =      2,
396         .buffer_bytes_max =  RME96_BUFFER_SIZE,
397         .period_bytes_min =  RME96_SMALL_BLOCK_SIZE,
398         .period_bytes_max =  RME96_LARGE_BLOCK_SIZE,
399         .periods_min =       RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
400         .periods_max =       RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
401         .fifo_size =         0,
402 };
403 
404 /*
405  * Digital input capabilities (S/PDIF)
406  */
407 static struct snd_pcm_hardware snd_rme96_capture_spdif_info =
408 {
409         .info =              (SNDRV_PCM_INFO_MMAP_IOMEM |
410                               SNDRV_PCM_INFO_MMAP_VALID |
411                               SNDRV_PCM_INFO_SYNC_START |
412                               SNDRV_PCM_INFO_RESUME |
413                               SNDRV_PCM_INFO_INTERLEAVED |
414                               SNDRV_PCM_INFO_PAUSE),
415         .formats =           (SNDRV_PCM_FMTBIT_S16_LE |
416                               SNDRV_PCM_FMTBIT_S32_LE),
417         .rates =             (SNDRV_PCM_RATE_32000 |
418                               SNDRV_PCM_RATE_44100 | 
419                               SNDRV_PCM_RATE_48000 | 
420                               SNDRV_PCM_RATE_64000 |
421                               SNDRV_PCM_RATE_88200 | 
422                               SNDRV_PCM_RATE_96000),
423         .rate_min =          32000,
424         .rate_max =          96000,
425         .channels_min =      2,
426         .channels_max =      2,
427         .buffer_bytes_max =  RME96_BUFFER_SIZE,
428         .period_bytes_min =  RME96_SMALL_BLOCK_SIZE,
429         .period_bytes_max =  RME96_LARGE_BLOCK_SIZE,
430         .periods_min =       RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
431         .periods_max =       RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
432         .fifo_size =         0,
433 };
434 
435 /*
436  * Digital output capabilities (ADAT)
437  */
438 static struct snd_pcm_hardware snd_rme96_playback_adat_info =
439 {
440         .info =              (SNDRV_PCM_INFO_MMAP_IOMEM |
441                               SNDRV_PCM_INFO_MMAP_VALID |
442                               SNDRV_PCM_INFO_SYNC_START |
443                               SNDRV_PCM_INFO_RESUME |
444                               SNDRV_PCM_INFO_INTERLEAVED |
445                               SNDRV_PCM_INFO_PAUSE),
446         .formats =           (SNDRV_PCM_FMTBIT_S16_LE |
447                               SNDRV_PCM_FMTBIT_S32_LE),
448         .rates =             (SNDRV_PCM_RATE_44100 | 
449                               SNDRV_PCM_RATE_48000),
450         .rate_min =          44100,
451         .rate_max =          48000,
452         .channels_min =      8,
453         .channels_max =      8,
454         .buffer_bytes_max =  RME96_BUFFER_SIZE,
455         .period_bytes_min =  RME96_SMALL_BLOCK_SIZE,
456         .period_bytes_max =  RME96_LARGE_BLOCK_SIZE,
457         .periods_min =       RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
458         .periods_max =       RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
459         .fifo_size =         0,
460 };
461 
462 /*
463  * Digital input capabilities (ADAT)
464  */
465 static struct snd_pcm_hardware snd_rme96_capture_adat_info =
466 {
467         .info =              (SNDRV_PCM_INFO_MMAP_IOMEM |
468                               SNDRV_PCM_INFO_MMAP_VALID |
469                               SNDRV_PCM_INFO_SYNC_START |
470                               SNDRV_PCM_INFO_RESUME |
471                               SNDRV_PCM_INFO_INTERLEAVED |
472                               SNDRV_PCM_INFO_PAUSE),
473         .formats =           (SNDRV_PCM_FMTBIT_S16_LE |
474                               SNDRV_PCM_FMTBIT_S32_LE),
475         .rates =             (SNDRV_PCM_RATE_44100 | 
476                               SNDRV_PCM_RATE_48000),
477         .rate_min =          44100,
478         .rate_max =          48000,
479         .channels_min =      8,
480         .channels_max =      8,
481         .buffer_bytes_max =  RME96_BUFFER_SIZE,
482         .period_bytes_min =  RME96_SMALL_BLOCK_SIZE,
483         .period_bytes_max =  RME96_LARGE_BLOCK_SIZE,
484         .periods_min =       RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
485         .periods_max =       RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
486         .fifo_size =         0,
487 };
488 
489 /*
490  * The CDATA, CCLK and CLATCH bits can be used to write to the SPI interface
491  * of the AD1852 or AD1852 D/A converter on the board.  CDATA must be set up
492  * on the falling edge of CCLK and be stable on the rising edge.  The rising
493  * edge of CLATCH after the last data bit clocks in the whole data word.
494  * A fast processor could probably drive the SPI interface faster than the
495  * DAC can handle (3MHz for the 1855, unknown for the 1852).  The udelay(1)
496  * limits the data rate to 500KHz and only causes a delay of 33 microsecs.
497  *
498  * NOTE: increased delay from 1 to 10, since there where problems setting
499  * the volume.
500  */
501 static void
502 snd_rme96_write_SPI(struct rme96 *rme96, u16 val)
503 {
504         int i;
505 
506         for (i = 0; i < 16; i++) {
507                 if (val & 0x8000) {
508                         rme96->areg |= RME96_AR_CDATA;
509                 } else {
510                         rme96->areg &= ~RME96_AR_CDATA;
511                 }
512                 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CLATCH);
513                 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
514                 udelay(10);
515                 rme96->areg |= RME96_AR_CCLK;
516                 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
517                 udelay(10);
518                 val <<= 1;
519         }
520         rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CDATA);
521         rme96->areg |= RME96_AR_CLATCH;
522         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
523         udelay(10);
524         rme96->areg &= ~RME96_AR_CLATCH;
525         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
526 }
527 
528 static void
529 snd_rme96_apply_dac_volume(struct rme96 *rme96)
530 {
531         if (RME96_DAC_IS_1852(rme96)) {
532                 snd_rme96_write_SPI(rme96, (rme96->vol[0] << 2) | 0x0);
533                 snd_rme96_write_SPI(rme96, (rme96->vol[1] << 2) | 0x2);
534         } else if (RME96_DAC_IS_1855(rme96)) {
535                 snd_rme96_write_SPI(rme96, (rme96->vol[0] & 0x3FF) | 0x000);
536                 snd_rme96_write_SPI(rme96, (rme96->vol[1] & 0x3FF) | 0x400);
537         }
538 }
539 
540 static void
541 snd_rme96_reset_dac(struct rme96 *rme96)
542 {
543         writel(rme96->wcreg | RME96_WCR_PD,
544                rme96->iobase + RME96_IO_CONTROL_REGISTER);
545         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
546 }
547 
548 static int
549 snd_rme96_getmontracks(struct rme96 *rme96)
550 {
551         return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) +
552                 (((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1);
553 }
554 
555 static int
556 snd_rme96_setmontracks(struct rme96 *rme96,
557                        int montracks)
558 {
559         if (montracks & 1) {
560                 rme96->wcreg |= RME96_WCR_MONITOR_0;
561         } else {
562                 rme96->wcreg &= ~RME96_WCR_MONITOR_0;
563         }
564         if (montracks & 2) {
565                 rme96->wcreg |= RME96_WCR_MONITOR_1;
566         } else {
567                 rme96->wcreg &= ~RME96_WCR_MONITOR_1;
568         }
569         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
570         return 0;
571 }
572 
573 static int
574 snd_rme96_getattenuation(struct rme96 *rme96)
575 {
576         return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) +
577                 (((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1);
578 }
579 
580 static int
581 snd_rme96_setattenuation(struct rme96 *rme96,
582                          int attenuation)
583 {
584         switch (attenuation) {
585         case 0:
586                 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) &
587                         ~RME96_WCR_GAIN_1;
588                 break;
589         case 1:
590                 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) &
591                         ~RME96_WCR_GAIN_1;
592                 break;
593         case 2:
594                 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) |
595                         RME96_WCR_GAIN_1;
596                 break;
597         case 3:
598                 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) |
599                         RME96_WCR_GAIN_1;
600                 break;
601         default:
602                 return -EINVAL;
603         }
604         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
605         return 0;
606 }
607 
608 static int
609 snd_rme96_capture_getrate(struct rme96 *rme96,
610                           int *is_adat)
611 {       
612         int n, rate;
613 
614         *is_adat = 0;
615         if (rme96->areg & RME96_AR_ANALOG) {
616                 /* Analog input, overrides S/PDIF setting */
617                 n = ((rme96->areg >> RME96_AR_BITPOS_F0) & 1) +
618                         (((rme96->areg >> RME96_AR_BITPOS_F1) & 1) << 1);
619                 switch (n) {
620                 case 1:
621                         rate = 32000;
622                         break;
623                 case 2:
624                         rate = 44100;
625                         break;
626                 case 3:
627                         rate = 48000;
628                         break;
629                 default:
630                         return -1;
631                 }
632                 return (rme96->areg & RME96_AR_BITPOS_F2) ? rate << 1 : rate;
633         }
634 
635         rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
636         if (rme96->rcreg & RME96_RCR_LOCK) {
637                 /* ADAT rate */
638                 *is_adat = 1;
639                 if (rme96->rcreg & RME96_RCR_T_OUT) {
640                         return 48000;
641                 }
642                 return 44100;
643         }
644 
645         if (rme96->rcreg & RME96_RCR_VERF) {
646                 return -1;
647         }
648         
649         /* S/PDIF rate */
650         n = ((rme96->rcreg >> RME96_RCR_BITPOS_F0) & 1) +
651                 (((rme96->rcreg >> RME96_RCR_BITPOS_F1) & 1) << 1) +
652                 (((rme96->rcreg >> RME96_RCR_BITPOS_F2) & 1) << 2);
653         
654         switch (n) {
655         case 0:         
656                 if (rme96->rcreg & RME96_RCR_T_OUT) {
657                         return 64000;
658                 }
659                 return -1;
660         case 3: return 96000;
661         case 4: return 88200;
662         case 5: return 48000;
663         case 6: return 44100;
664         case 7: return 32000;
665         default:
666                 break;
667         }
668         return -1;
669 }
670 
671 static int
672 snd_rme96_playback_getrate(struct rme96 *rme96)
673 {
674         int rate, dummy;
675 
676         if (!(rme96->wcreg & RME96_WCR_MASTER) &&
677             snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
678             (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
679         {
680                 /* slave clock */
681                 return rate;
682         }
683         rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) +
684                 (((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1);
685         switch (rate) {
686         case 1:
687                 rate = 32000;
688                 break;
689         case 2:
690                 rate = 44100;
691                 break;
692         case 3:
693                 rate = 48000;
694                 break;
695         default:
696                 return -1;
697         }
698         return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate;
699 }
700 
701 static int
702 snd_rme96_playback_setrate(struct rme96 *rme96,
703                            int rate)
704 {
705         int ds;
706 
707         ds = rme96->wcreg & RME96_WCR_DS;
708         switch (rate) {
709         case 32000:
710                 rme96->wcreg &= ~RME96_WCR_DS;
711                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
712                         ~RME96_WCR_FREQ_1;
713                 break;
714         case 44100:
715                 rme96->wcreg &= ~RME96_WCR_DS;
716                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
717                         ~RME96_WCR_FREQ_0;
718                 break;
719         case 48000:
720                 rme96->wcreg &= ~RME96_WCR_DS;
721                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
722                         RME96_WCR_FREQ_1;
723                 break;
724         case 64000:
725                 rme96->wcreg |= RME96_WCR_DS;
726                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
727                         ~RME96_WCR_FREQ_1;
728                 break;
729         case 88200:
730                 rme96->wcreg |= RME96_WCR_DS;
731                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
732                         ~RME96_WCR_FREQ_0;
733                 break;
734         case 96000:
735                 rme96->wcreg |= RME96_WCR_DS;
736                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
737                         RME96_WCR_FREQ_1;
738                 break;
739         default:
740                 return -EINVAL;
741         }
742         if ((!ds && rme96->wcreg & RME96_WCR_DS) ||
743             (ds && !(rme96->wcreg & RME96_WCR_DS)))
744         {
745                 /* change to/from double-speed: reset the DAC (if available) */
746                 snd_rme96_reset_dac(rme96);
747                 return 1; /* need to restore volume */
748         } else {
749                 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
750                 return 0;
751         }
752 }
753 
754 static int
755 snd_rme96_capture_analog_setrate(struct rme96 *rme96,
756                                  int rate)
757 {
758         switch (rate) {
759         case 32000:
760                 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
761                                ~RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
762                 break;
763         case 44100:
764                 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
765                                RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
766                 break;
767         case 48000:
768                 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
769                                RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
770                 break;
771         case 64000:
772                 if (rme96->rev < 4) {
773                         return -EINVAL;
774                 }
775                 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
776                                ~RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
777                 break;
778         case 88200:
779                 if (rme96->rev < 4) {
780                         return -EINVAL;
781                 }
782                 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
783                                RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
784                 break;
785         case 96000:
786                 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
787                                RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
788                 break;
789         default:
790                 return -EINVAL;
791         }
792         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
793         return 0;
794 }
795 
796 static int
797 snd_rme96_setclockmode(struct rme96 *rme96,
798                        int mode)
799 {
800         switch (mode) {
801         case RME96_CLOCKMODE_SLAVE:
802                 /* AutoSync */ 
803                 rme96->wcreg &= ~RME96_WCR_MASTER;
804                 rme96->areg &= ~RME96_AR_WSEL;
805                 break;
806         case RME96_CLOCKMODE_MASTER:
807                 /* Internal */
808                 rme96->wcreg |= RME96_WCR_MASTER;
809                 rme96->areg &= ~RME96_AR_WSEL;
810                 break;
811         case RME96_CLOCKMODE_WORDCLOCK:
812                 /* Word clock is a master mode */
813                 rme96->wcreg |= RME96_WCR_MASTER; 
814                 rme96->areg |= RME96_AR_WSEL;
815                 break;
816         default:
817                 return -EINVAL;
818         }
819         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
820         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
821         return 0;
822 }
823 
824 static int
825 snd_rme96_getclockmode(struct rme96 *rme96)
826 {
827         if (rme96->areg & RME96_AR_WSEL) {
828                 return RME96_CLOCKMODE_WORDCLOCK;
829         }
830         return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER :
831                 RME96_CLOCKMODE_SLAVE;
832 }
833 
834 static int
835 snd_rme96_setinputtype(struct rme96 *rme96,
836                        int type)
837 {
838         int n;
839 
840         switch (type) {
841         case RME96_INPUT_OPTICAL:
842                 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) &
843                         ~RME96_WCR_INP_1;
844                 break;
845         case RME96_INPUT_COAXIAL:
846                 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) &
847                         ~RME96_WCR_INP_1;
848                 break;
849         case RME96_INPUT_INTERNAL:
850                 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) |
851                         RME96_WCR_INP_1;
852                 break;
853         case RME96_INPUT_XLR:
854                 if ((rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST &&
855                      rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PRO) ||
856                     (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST &&
857                      rme96->rev > 4))
858                 {
859                         /* Only Digi96/8 PRO and Digi96/8 PAD supports XLR */
860                         return -EINVAL;
861                 }
862                 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) |
863                         RME96_WCR_INP_1;
864                 break;
865         case RME96_INPUT_ANALOG:
866                 if (!RME96_HAS_ANALOG_IN(rme96)) {
867                         return -EINVAL;
868                 }
869                 rme96->areg |= RME96_AR_ANALOG;
870                 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
871                 if (rme96->rev < 4) {
872                         /*
873                          * Revision less than 004 does not support 64 and
874                          * 88.2 kHz
875                          */
876                         if (snd_rme96_capture_getrate(rme96, &n) == 88200) {
877                                 snd_rme96_capture_analog_setrate(rme96, 44100);
878                         }
879                         if (snd_rme96_capture_getrate(rme96, &n) == 64000) {
880                                 snd_rme96_capture_analog_setrate(rme96, 32000);
881                         }
882                 }
883                 return 0;
884         default:
885                 return -EINVAL;
886         }
887         if (type != RME96_INPUT_ANALOG && RME96_HAS_ANALOG_IN(rme96)) {
888                 rme96->areg &= ~RME96_AR_ANALOG;
889                 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
890         }
891         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
892         return 0;
893 }
894 
895 static int
896 snd_rme96_getinputtype(struct rme96 *rme96)
897 {
898         if (rme96->areg & RME96_AR_ANALOG) {
899                 return RME96_INPUT_ANALOG;
900         }
901         return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) +
902                 (((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1);
903 }
904 
905 static void
906 snd_rme96_setframelog(struct rme96 *rme96,
907                       int n_channels,
908                       int is_playback)
909 {
910         int frlog;
911         
912         if (n_channels == 2) {
913                 frlog = 1;
914         } else {
915                 /* assume 8 channels */
916                 frlog = 3;
917         }
918         if (is_playback) {
919                 frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1;
920                 rme96->playback_frlog = frlog;
921         } else {
922                 frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1;
923                 rme96->capture_frlog = frlog;
924         }
925 }
926 
927 static int
928 snd_rme96_playback_setformat(struct rme96 *rme96,
929                              int format)
930 {
931         switch (format) {
932         case SNDRV_PCM_FORMAT_S16_LE:
933                 rme96->wcreg &= ~RME96_WCR_MODE24;
934                 break;
935         case SNDRV_PCM_FORMAT_S32_LE:
936                 rme96->wcreg |= RME96_WCR_MODE24;
937                 break;
938         default:
939                 return -EINVAL;
940         }
941         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
942         return 0;
943 }
944 
945 static int
946 snd_rme96_capture_setformat(struct rme96 *rme96,
947                             int format)
948 {
949         switch (format) {
950         case SNDRV_PCM_FORMAT_S16_LE:
951                 rme96->wcreg &= ~RME96_WCR_MODE24_2;
952                 break;
953         case SNDRV_PCM_FORMAT_S32_LE:
954                 rme96->wcreg |= RME96_WCR_MODE24_2;
955                 break;
956         default:
957                 return -EINVAL;
958         }
959         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
960         return 0;
961 }
962 
963 static void
964 snd_rme96_set_period_properties(struct rme96 *rme96,
965                                 size_t period_bytes)
966 {
967         switch (period_bytes) {
968         case RME96_LARGE_BLOCK_SIZE:
969                 rme96->wcreg &= ~RME96_WCR_ISEL;
970                 break;
971         case RME96_SMALL_BLOCK_SIZE:
972                 rme96->wcreg |= RME96_WCR_ISEL;
973                 break;
974         default:
975                 snd_BUG();
976                 break;
977         }
978         rme96->wcreg &= ~RME96_WCR_IDIS;
979         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
980 }
981 
982 static int
983 snd_rme96_playback_hw_params(struct snd_pcm_substream *substream,
984                              struct snd_pcm_hw_params *params)
985 {
986         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
987         struct snd_pcm_runtime *runtime = substream->runtime;
988         int err, rate, dummy;
989         bool apply_dac_volume = false;
990 
991         runtime->dma_area = (void __force *)(rme96->iobase +
992                                              RME96_IO_PLAY_BUFFER);
993         runtime->dma_addr = rme96->port + RME96_IO_PLAY_BUFFER;
994         runtime->dma_bytes = RME96_BUFFER_SIZE;
995 
996         spin_lock_irq(&rme96->lock);
997         if (!(rme96->wcreg & RME96_WCR_MASTER) &&
998             snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
999             (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1000         {
1001                 /* slave clock */
1002                 if ((int)params_rate(params) != rate) {
1003                         err = -EIO;
1004                         goto error;
1005                 }
1006         } else {
1007                 err = snd_rme96_playback_setrate(rme96, params_rate(params));
1008                 if (err < 0)
1009                         goto error;
1010                 apply_dac_volume = err > 0; /* need to restore volume later? */
1011         }
1012 
1013         err = snd_rme96_playback_setformat(rme96, params_format(params));
1014         if (err < 0)
1015                 goto error;
1016         snd_rme96_setframelog(rme96, params_channels(params), 1);
1017         if (rme96->capture_periodsize != 0) {
1018                 if (params_period_size(params) << rme96->playback_frlog !=
1019                     rme96->capture_periodsize)
1020                 {
1021                         err = -EBUSY;
1022                         goto error;
1023                 }
1024         }
1025         rme96->playback_periodsize =
1026                 params_period_size(params) << rme96->playback_frlog;
1027         snd_rme96_set_period_properties(rme96, rme96->playback_periodsize);
1028         /* S/PDIF setup */
1029         if ((rme96->wcreg & RME96_WCR_ADAT) == 0) {
1030                 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
1031                 writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1032         }
1033 
1034         err = 0;
1035  error:
1036         spin_unlock_irq(&rme96->lock);
1037         if (apply_dac_volume) {
1038                 usleep_range(3000, 10000);
1039                 snd_rme96_apply_dac_volume(rme96);
1040         }
1041 
1042         return err;
1043 }
1044 
1045 static int
1046 snd_rme96_capture_hw_params(struct snd_pcm_substream *substream,
1047                             struct snd_pcm_hw_params *params)
1048 {
1049         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1050         struct snd_pcm_runtime *runtime = substream->runtime;
1051         int err, isadat, rate;
1052         
1053         runtime->dma_area = (void __force *)(rme96->iobase +
1054                                              RME96_IO_REC_BUFFER);
1055         runtime->dma_addr = rme96->port + RME96_IO_REC_BUFFER;
1056         runtime->dma_bytes = RME96_BUFFER_SIZE;
1057 
1058         spin_lock_irq(&rme96->lock);
1059         if ((err = snd_rme96_capture_setformat(rme96, params_format(params))) < 0) {
1060                 spin_unlock_irq(&rme96->lock);
1061                 return err;
1062         }
1063         if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1064                 if ((err = snd_rme96_capture_analog_setrate(rme96,
1065                                                             params_rate(params))) < 0)
1066                 {
1067                         spin_unlock_irq(&rme96->lock);
1068                         return err;
1069                 }
1070         } else if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
1071                 if ((int)params_rate(params) != rate) {
1072                         spin_unlock_irq(&rme96->lock);
1073                         return -EIO;                    
1074                 }
1075                 if ((isadat && runtime->hw.channels_min == 2) ||
1076                     (!isadat && runtime->hw.channels_min == 8))
1077                 {
1078                         spin_unlock_irq(&rme96->lock);
1079                         return -EIO;
1080                 }
1081         }
1082         snd_rme96_setframelog(rme96, params_channels(params), 0);
1083         if (rme96->playback_periodsize != 0) {
1084                 if (params_period_size(params) << rme96->capture_frlog !=
1085                     rme96->playback_periodsize)
1086                 {
1087                         spin_unlock_irq(&rme96->lock);
1088                         return -EBUSY;
1089                 }
1090         }
1091         rme96->capture_periodsize =
1092                 params_period_size(params) << rme96->capture_frlog;
1093         snd_rme96_set_period_properties(rme96, rme96->capture_periodsize);
1094         spin_unlock_irq(&rme96->lock);
1095 
1096         return 0;
1097 }
1098 
1099 static void
1100 snd_rme96_trigger(struct rme96 *rme96,
1101                   int op)
1102 {
1103         if (op & RME96_TB_RESET_PLAYPOS)
1104                 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1105         if (op & RME96_TB_RESET_CAPTUREPOS)
1106                 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1107         if (op & RME96_TB_CLEAR_PLAYBACK_IRQ) {
1108                 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1109                 if (rme96->rcreg & RME96_RCR_IRQ)
1110                         writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1111         }
1112         if (op & RME96_TB_CLEAR_CAPTURE_IRQ) {
1113                 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1114                 if (rme96->rcreg & RME96_RCR_IRQ_2)
1115                         writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1116         }
1117         if (op & RME96_TB_START_PLAYBACK)
1118                 rme96->wcreg |= RME96_WCR_START;
1119         if (op & RME96_TB_STOP_PLAYBACK)
1120                 rme96->wcreg &= ~RME96_WCR_START;
1121         if (op & RME96_TB_START_CAPTURE)
1122                 rme96->wcreg |= RME96_WCR_START_2;
1123         if (op & RME96_TB_STOP_CAPTURE)
1124                 rme96->wcreg &= ~RME96_WCR_START_2;
1125         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1126 }
1127 
1128 
1129 
1130 static irqreturn_t
1131 snd_rme96_interrupt(int irq,
1132                     void *dev_id)
1133 {
1134         struct rme96 *rme96 = (struct rme96 *)dev_id;
1135 
1136         rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1137         /* fastpath out, to ease interrupt sharing */
1138         if (!((rme96->rcreg & RME96_RCR_IRQ) ||
1139               (rme96->rcreg & RME96_RCR_IRQ_2)))
1140         {
1141                 return IRQ_NONE;
1142         }
1143         
1144         if (rme96->rcreg & RME96_RCR_IRQ) {
1145                 /* playback */
1146                 snd_pcm_period_elapsed(rme96->playback_substream);
1147                 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1148         }
1149         if (rme96->rcreg & RME96_RCR_IRQ_2) {
1150                 /* capture */
1151                 snd_pcm_period_elapsed(rme96->capture_substream);               
1152                 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1153         }
1154         return IRQ_HANDLED;
1155 }
1156 
1157 static unsigned int period_bytes[] = { RME96_SMALL_BLOCK_SIZE, RME96_LARGE_BLOCK_SIZE };
1158 
1159 static struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = {
1160         .count = ARRAY_SIZE(period_bytes),
1161         .list = period_bytes,
1162         .mask = 0
1163 };
1164 
1165 static void
1166 rme96_set_buffer_size_constraint(struct rme96 *rme96,
1167                                  struct snd_pcm_runtime *runtime)
1168 {
1169         unsigned int size;
1170 
1171         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1172                                      RME96_BUFFER_SIZE, RME96_BUFFER_SIZE);
1173         if ((size = rme96->playback_periodsize) != 0 ||
1174             (size = rme96->capture_periodsize) != 0)
1175                 snd_pcm_hw_constraint_minmax(runtime,
1176                                              SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1177                                              size, size);
1178         else
1179                 snd_pcm_hw_constraint_list(runtime, 0,
1180                                            SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1181                                            &hw_constraints_period_bytes);
1182 }
1183 
1184 static int
1185 snd_rme96_playback_spdif_open(struct snd_pcm_substream *substream)
1186 {
1187         int rate, dummy;
1188         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1189         struct snd_pcm_runtime *runtime = substream->runtime;
1190 
1191         snd_pcm_set_sync(substream);
1192         spin_lock_irq(&rme96->lock);    
1193         if (rme96->playback_substream != NULL) {
1194                 spin_unlock_irq(&rme96->lock);
1195                 return -EBUSY;
1196         }
1197         rme96->wcreg &= ~RME96_WCR_ADAT;
1198         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1199         rme96->playback_substream = substream;
1200         spin_unlock_irq(&rme96->lock);
1201 
1202         runtime->hw = snd_rme96_playback_spdif_info;
1203         if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1204             snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1205             (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1206         {
1207                 /* slave clock */
1208                 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1209                 runtime->hw.rate_min = rate;
1210                 runtime->hw.rate_max = rate;
1211         }        
1212         rme96_set_buffer_size_constraint(rme96, runtime);
1213 
1214         rme96->wcreg_spdif_stream = rme96->wcreg_spdif;
1215         rme96->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1216         snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1217                        SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1218         return 0;
1219 }
1220 
1221 static int
1222 snd_rme96_capture_spdif_open(struct snd_pcm_substream *substream)
1223 {
1224         int isadat, rate;
1225         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1226         struct snd_pcm_runtime *runtime = substream->runtime;
1227 
1228         snd_pcm_set_sync(substream);
1229         runtime->hw = snd_rme96_capture_spdif_info;
1230         if (snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1231             (rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0)
1232         {
1233                 if (isadat) {
1234                         return -EIO;
1235                 }
1236                 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1237                 runtime->hw.rate_min = rate;
1238                 runtime->hw.rate_max = rate;
1239         }
1240         
1241         spin_lock_irq(&rme96->lock);
1242         if (rme96->capture_substream != NULL) {
1243                 spin_unlock_irq(&rme96->lock);
1244                 return -EBUSY;
1245         }
1246         rme96->capture_substream = substream;
1247         spin_unlock_irq(&rme96->lock);
1248         
1249         rme96_set_buffer_size_constraint(rme96, runtime);
1250         return 0;
1251 }
1252 
1253 static int
1254 snd_rme96_playback_adat_open(struct snd_pcm_substream *substream)
1255 {
1256         int rate, dummy;
1257         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1258         struct snd_pcm_runtime *runtime = substream->runtime;        
1259         
1260         snd_pcm_set_sync(substream);
1261         spin_lock_irq(&rme96->lock);    
1262         if (rme96->playback_substream != NULL) {
1263                 spin_unlock_irq(&rme96->lock);
1264                 return -EBUSY;
1265         }
1266         rme96->wcreg |= RME96_WCR_ADAT;
1267         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1268         rme96->playback_substream = substream;
1269         spin_unlock_irq(&rme96->lock);
1270         
1271         runtime->hw = snd_rme96_playback_adat_info;
1272         if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1273             snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1274             (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1275         {
1276                 /* slave clock */
1277                 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1278                 runtime->hw.rate_min = rate;
1279                 runtime->hw.rate_max = rate;
1280         }        
1281         rme96_set_buffer_size_constraint(rme96, runtime);
1282         return 0;
1283 }
1284 
1285 static int
1286 snd_rme96_capture_adat_open(struct snd_pcm_substream *substream)
1287 {
1288         int isadat, rate;
1289         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1290         struct snd_pcm_runtime *runtime = substream->runtime;
1291 
1292         snd_pcm_set_sync(substream);
1293         runtime->hw = snd_rme96_capture_adat_info;
1294         if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1295                 /* makes no sense to use analog input. Note that analog
1296                    expension cards AEB4/8-I are RME96_INPUT_INTERNAL */
1297                 return -EIO;
1298         }
1299         if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
1300                 if (!isadat) {
1301                         return -EIO;
1302                 }
1303                 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1304                 runtime->hw.rate_min = rate;
1305                 runtime->hw.rate_max = rate;
1306         }
1307         
1308         spin_lock_irq(&rme96->lock);    
1309         if (rme96->capture_substream != NULL) {
1310                 spin_unlock_irq(&rme96->lock);
1311                 return -EBUSY;
1312         }
1313         rme96->capture_substream = substream;
1314         spin_unlock_irq(&rme96->lock);
1315 
1316         rme96_set_buffer_size_constraint(rme96, runtime);
1317         return 0;
1318 }
1319 
1320 static int
1321 snd_rme96_playback_close(struct snd_pcm_substream *substream)
1322 {
1323         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1324         int spdif = 0;
1325 
1326         spin_lock_irq(&rme96->lock);    
1327         if (RME96_ISPLAYING(rme96)) {
1328                 snd_rme96_trigger(rme96, RME96_STOP_PLAYBACK);
1329         }
1330         rme96->playback_substream = NULL;
1331         rme96->playback_periodsize = 0;
1332         spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0;
1333         spin_unlock_irq(&rme96->lock);
1334         if (spdif) {
1335                 rme96->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1336                 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1337                                SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1338         }
1339         return 0;
1340 }
1341 
1342 static int
1343 snd_rme96_capture_close(struct snd_pcm_substream *substream)
1344 {
1345         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1346         
1347         spin_lock_irq(&rme96->lock);    
1348         if (RME96_ISRECORDING(rme96)) {
1349                 snd_rme96_trigger(rme96, RME96_STOP_CAPTURE);
1350         }
1351         rme96->capture_substream = NULL;
1352         rme96->capture_periodsize = 0;
1353         spin_unlock_irq(&rme96->lock);
1354         return 0;
1355 }
1356 
1357 static int
1358 snd_rme96_playback_prepare(struct snd_pcm_substream *substream)
1359 {
1360         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1361         
1362         spin_lock_irq(&rme96->lock);    
1363         if (RME96_ISPLAYING(rme96)) {
1364                 snd_rme96_trigger(rme96, RME96_STOP_PLAYBACK);
1365         }
1366         writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1367         spin_unlock_irq(&rme96->lock);
1368         return 0;
1369 }
1370 
1371 static int
1372 snd_rme96_capture_prepare(struct snd_pcm_substream *substream)
1373 {
1374         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1375         
1376         spin_lock_irq(&rme96->lock);    
1377         if (RME96_ISRECORDING(rme96)) {
1378                 snd_rme96_trigger(rme96, RME96_STOP_CAPTURE);
1379         }
1380         writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1381         spin_unlock_irq(&rme96->lock);
1382         return 0;
1383 }
1384 
1385 static int
1386 snd_rme96_playback_trigger(struct snd_pcm_substream *substream, 
1387                            int cmd)
1388 {
1389         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1390         struct snd_pcm_substream *s;
1391         bool sync;
1392 
1393         snd_pcm_group_for_each_entry(s, substream) {
1394                 if (snd_pcm_substream_chip(s) == rme96)
1395                         snd_pcm_trigger_done(s, substream);
1396         }
1397 
1398         sync = (rme96->playback_substream && rme96->capture_substream) &&
1399                (rme96->playback_substream->group ==
1400                 rme96->capture_substream->group);
1401 
1402         switch (cmd) {
1403         case SNDRV_PCM_TRIGGER_START:
1404                 if (!RME96_ISPLAYING(rme96)) {
1405                         if (substream != rme96->playback_substream)
1406                                 return -EBUSY;
1407                         snd_rme96_trigger(rme96, sync ? RME96_START_BOTH
1408                                                  : RME96_START_PLAYBACK);
1409                 }
1410                 break;
1411 
1412         case SNDRV_PCM_TRIGGER_SUSPEND:
1413         case SNDRV_PCM_TRIGGER_STOP:
1414                 if (RME96_ISPLAYING(rme96)) {
1415                         if (substream != rme96->playback_substream)
1416                                 return -EBUSY;
1417                         snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH
1418                                                  :  RME96_STOP_PLAYBACK);
1419                 }
1420                 break;
1421 
1422         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1423                 if (RME96_ISPLAYING(rme96))
1424                         snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH
1425                                                  : RME96_STOP_PLAYBACK);
1426                 break;
1427 
1428         case SNDRV_PCM_TRIGGER_RESUME:
1429         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1430                 if (!RME96_ISPLAYING(rme96))
1431                         snd_rme96_trigger(rme96, sync ? RME96_RESUME_BOTH
1432                                                  : RME96_RESUME_PLAYBACK);
1433                 break;
1434 
1435         default:
1436                 return -EINVAL;
1437         }
1438 
1439         return 0;
1440 }
1441 
1442 static int
1443 snd_rme96_capture_trigger(struct snd_pcm_substream *substream, 
1444                           int cmd)
1445 {
1446         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1447         struct snd_pcm_substream *s;
1448         bool sync;
1449 
1450         snd_pcm_group_for_each_entry(s, substream) {
1451                 if (snd_pcm_substream_chip(s) == rme96)
1452                         snd_pcm_trigger_done(s, substream);
1453         }
1454 
1455         sync = (rme96->playback_substream && rme96->capture_substream) &&
1456                (rme96->playback_substream->group ==
1457                 rme96->capture_substream->group);
1458 
1459         switch (cmd) {
1460         case SNDRV_PCM_TRIGGER_START:
1461                 if (!RME96_ISRECORDING(rme96)) {
1462                         if (substream != rme96->capture_substream)
1463                                 return -EBUSY;
1464                         snd_rme96_trigger(rme96, sync ? RME96_START_BOTH
1465                                                  : RME96_START_CAPTURE);
1466                 }
1467                 break;
1468 
1469         case SNDRV_PCM_TRIGGER_SUSPEND:
1470         case SNDRV_PCM_TRIGGER_STOP:
1471                 if (RME96_ISRECORDING(rme96)) {
1472                         if (substream != rme96->capture_substream)
1473                                 return -EBUSY;
1474                         snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH
1475                                                  : RME96_STOP_CAPTURE);
1476                 }
1477                 break;
1478 
1479         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1480                 if (RME96_ISRECORDING(rme96))
1481                         snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH
1482                                                  : RME96_STOP_CAPTURE);
1483                 break;
1484 
1485         case SNDRV_PCM_TRIGGER_RESUME:
1486         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1487                 if (!RME96_ISRECORDING(rme96))
1488                         snd_rme96_trigger(rme96, sync ? RME96_RESUME_BOTH
1489                                                  : RME96_RESUME_CAPTURE);
1490                 break;
1491 
1492         default:
1493                 return -EINVAL;
1494         }
1495 
1496         return 0;
1497 }
1498 
1499 static snd_pcm_uframes_t
1500 snd_rme96_playback_pointer(struct snd_pcm_substream *substream)
1501 {
1502         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1503         return snd_rme96_playback_ptr(rme96);
1504 }
1505 
1506 static snd_pcm_uframes_t
1507 snd_rme96_capture_pointer(struct snd_pcm_substream *substream)
1508 {
1509         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1510         return snd_rme96_capture_ptr(rme96);
1511 }
1512 
1513 static struct snd_pcm_ops snd_rme96_playback_spdif_ops = {
1514         .open =         snd_rme96_playback_spdif_open,
1515         .close =        snd_rme96_playback_close,
1516         .ioctl =        snd_pcm_lib_ioctl,
1517         .hw_params =    snd_rme96_playback_hw_params,
1518         .prepare =      snd_rme96_playback_prepare,
1519         .trigger =      snd_rme96_playback_trigger,
1520         .pointer =      snd_rme96_playback_pointer,
1521         .copy =         snd_rme96_playback_copy,
1522         .silence =      snd_rme96_playback_silence,
1523         .mmap =         snd_pcm_lib_mmap_iomem,
1524 };
1525 
1526 static struct snd_pcm_ops snd_rme96_capture_spdif_ops = {
1527         .open =         snd_rme96_capture_spdif_open,
1528         .close =        snd_rme96_capture_close,
1529         .ioctl =        snd_pcm_lib_ioctl,
1530         .hw_params =    snd_rme96_capture_hw_params,
1531         .prepare =      snd_rme96_capture_prepare,
1532         .trigger =      snd_rme96_capture_trigger,
1533         .pointer =      snd_rme96_capture_pointer,
1534         .copy =         snd_rme96_capture_copy,
1535         .mmap =         snd_pcm_lib_mmap_iomem,
1536 };
1537 
1538 static struct snd_pcm_ops snd_rme96_playback_adat_ops = {
1539         .open =         snd_rme96_playback_adat_open,
1540         .close =        snd_rme96_playback_close,
1541         .ioctl =        snd_pcm_lib_ioctl,
1542         .hw_params =    snd_rme96_playback_hw_params,
1543         .prepare =      snd_rme96_playback_prepare,
1544         .trigger =      snd_rme96_playback_trigger,
1545         .pointer =      snd_rme96_playback_pointer,
1546         .copy =         snd_rme96_playback_copy,
1547         .silence =      snd_rme96_playback_silence,
1548         .mmap =         snd_pcm_lib_mmap_iomem,
1549 };
1550 
1551 static struct snd_pcm_ops snd_rme96_capture_adat_ops = {
1552         .open =         snd_rme96_capture_adat_open,
1553         .close =        snd_rme96_capture_close,
1554         .ioctl =        snd_pcm_lib_ioctl,
1555         .hw_params =    snd_rme96_capture_hw_params,
1556         .prepare =      snd_rme96_capture_prepare,
1557         .trigger =      snd_rme96_capture_trigger,
1558         .pointer =      snd_rme96_capture_pointer,
1559         .copy =         snd_rme96_capture_copy,
1560         .mmap =         snd_pcm_lib_mmap_iomem,
1561 };
1562 
1563 static void
1564 snd_rme96_free(void *private_data)
1565 {
1566         struct rme96 *rme96 = (struct rme96 *)private_data;
1567 
1568         if (rme96 == NULL) {
1569                 return;
1570         }
1571         if (rme96->irq >= 0) {
1572                 snd_rme96_trigger(rme96, RME96_STOP_BOTH);
1573                 rme96->areg &= ~RME96_AR_DAC_EN;
1574                 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1575                 free_irq(rme96->irq, (void *)rme96);
1576                 rme96->irq = -1;
1577         }
1578         if (rme96->iobase) {
1579                 iounmap(rme96->iobase);
1580                 rme96->iobase = NULL;
1581         }
1582         if (rme96->port) {
1583                 pci_release_regions(rme96->pci);
1584                 rme96->port = 0;
1585         }
1586 #ifdef CONFIG_PM
1587         vfree(rme96->playback_suspend_buffer);
1588         vfree(rme96->capture_suspend_buffer);
1589 #endif
1590         pci_disable_device(rme96->pci);
1591 }
1592 
1593 static void
1594 snd_rme96_free_spdif_pcm(struct snd_pcm *pcm)
1595 {
1596         struct rme96 *rme96 = pcm->private_data;
1597         rme96->spdif_pcm = NULL;
1598 }
1599 
1600 static void
1601 snd_rme96_free_adat_pcm(struct snd_pcm *pcm)
1602 {
1603         struct rme96 *rme96 = pcm->private_data;
1604         rme96->adat_pcm = NULL;
1605 }
1606 
1607 static int
1608 snd_rme96_create(struct rme96 *rme96)
1609 {
1610         struct pci_dev *pci = rme96->pci;
1611         int err;
1612 
1613         rme96->irq = -1;
1614         spin_lock_init(&rme96->lock);
1615 
1616         if ((err = pci_enable_device(pci)) < 0)
1617                 return err;
1618 
1619         if ((err = pci_request_regions(pci, "RME96")) < 0)
1620                 return err;
1621         rme96->port = pci_resource_start(rme96->pci, 0);
1622 
1623         rme96->iobase = ioremap_nocache(rme96->port, RME96_IO_SIZE);
1624         if (!rme96->iobase) {
1625                 snd_printk(KERN_ERR "unable to remap memory region 0x%lx-0x%lx\n", rme96->port, rme96->port + RME96_IO_SIZE - 1);
1626                 return -ENOMEM;
1627         }
1628 
1629         if (request_irq(pci->irq, snd_rme96_interrupt, IRQF_SHARED,
1630                         KBUILD_MODNAME, rme96)) {
1631                 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1632                 return -EBUSY;
1633         }
1634         rme96->irq = pci->irq;
1635 
1636         /* read the card's revision number */
1637         pci_read_config_byte(pci, 8, &rme96->rev);      
1638         
1639         /* set up ALSA pcm device for S/PDIF */
1640         if ((err = snd_pcm_new(rme96->card, "Digi96 IEC958", 0,
1641                                1, 1, &rme96->spdif_pcm)) < 0)
1642         {
1643                 return err;
1644         }
1645         rme96->spdif_pcm->private_data = rme96;
1646         rme96->spdif_pcm->private_free = snd_rme96_free_spdif_pcm;
1647         strcpy(rme96->spdif_pcm->name, "Digi96 IEC958");
1648         snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_spdif_ops);
1649         snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_spdif_ops);
1650 
1651         rme96->spdif_pcm->info_flags = 0;
1652 
1653         /* set up ALSA pcm device for ADAT */
1654         if (pci->device == PCI_DEVICE_ID_RME_DIGI96) {
1655                 /* ADAT is not available on the base model */
1656                 rme96->adat_pcm = NULL;
1657         } else {
1658                 if ((err = snd_pcm_new(rme96->card, "Digi96 ADAT", 1,
1659                                        1, 1, &rme96->adat_pcm)) < 0)
1660                 {
1661                         return err;
1662                 }               
1663                 rme96->adat_pcm->private_data = rme96;
1664                 rme96->adat_pcm->private_free = snd_rme96_free_adat_pcm;
1665                 strcpy(rme96->adat_pcm->name, "Digi96 ADAT");
1666                 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_adat_ops);
1667                 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_adat_ops);
1668                 
1669                 rme96->adat_pcm->info_flags = 0;
1670         }
1671 
1672         rme96->playback_periodsize = 0;
1673         rme96->capture_periodsize = 0;
1674         
1675         /* make sure playback/capture is stopped, if by some reason active */
1676         snd_rme96_trigger(rme96, RME96_STOP_BOTH);
1677         
1678         /* set default values in registers */
1679         rme96->wcreg =
1680                 RME96_WCR_FREQ_1 | /* set 44.1 kHz playback */
1681                 RME96_WCR_SEL |    /* normal playback */
1682                 RME96_WCR_MASTER | /* set to master clock mode */
1683                 RME96_WCR_INP_0;   /* set coaxial input */
1684 
1685         rme96->areg = RME96_AR_FREQPAD_1; /* set 44.1 kHz analog capture */
1686 
1687         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1688         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1689         
1690         /* reset the ADC */
1691         writel(rme96->areg | RME96_AR_PD2,
1692                rme96->iobase + RME96_IO_ADDITIONAL_REG);
1693         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);   
1694 
1695         /* reset and enable the DAC (order is important). */
1696         snd_rme96_reset_dac(rme96);
1697         rme96->areg |= RME96_AR_DAC_EN;
1698         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1699 
1700         /* reset playback and record buffer pointers */
1701         writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1702         writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1703 
1704         /* reset volume */
1705         rme96->vol[0] = rme96->vol[1] = 0;
1706         if (RME96_HAS_ANALOG_OUT(rme96)) {
1707                 snd_rme96_apply_dac_volume(rme96);
1708         }
1709         
1710         /* init switch interface */
1711         if ((err = snd_rme96_create_switches(rme96->card, rme96)) < 0) {
1712                 return err;
1713         }
1714 
1715         /* init proc interface */
1716         snd_rme96_proc_init(rme96);
1717         
1718         return 0;
1719 }
1720 
1721 /*
1722  * proc interface
1723  */
1724 
1725 static void 
1726 snd_rme96_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
1727 {
1728         int n;
1729         struct rme96 *rme96 = entry->private_data;
1730         
1731         rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1732 
1733         snd_iprintf(buffer, rme96->card->longname);
1734         snd_iprintf(buffer, " (index #%d)\n", rme96->card->number + 1);
1735 
1736         snd_iprintf(buffer, "\nGeneral settings\n");
1737         if (rme96->wcreg & RME96_WCR_IDIS) {
1738                 snd_iprintf(buffer, "  period size: N/A (interrupts "
1739                             "disabled)\n");
1740         } else if (rme96->wcreg & RME96_WCR_ISEL) {
1741                 snd_iprintf(buffer, "  period size: 2048 bytes\n");
1742         } else {
1743                 snd_iprintf(buffer, "  period size: 8192 bytes\n");
1744         }       
1745         snd_iprintf(buffer, "\nInput settings\n");
1746         switch (snd_rme96_getinputtype(rme96)) {
1747         case RME96_INPUT_OPTICAL:
1748                 snd_iprintf(buffer, "  input: optical");
1749                 break;
1750         case RME96_INPUT_COAXIAL:
1751                 snd_iprintf(buffer, "  input: coaxial");
1752                 break;
1753         case RME96_INPUT_INTERNAL:
1754                 snd_iprintf(buffer, "  input: internal");
1755                 break;
1756         case RME96_INPUT_XLR:
1757                 snd_iprintf(buffer, "  input: XLR");
1758                 break;
1759         case RME96_INPUT_ANALOG:
1760                 snd_iprintf(buffer, "  input: analog");
1761                 break;
1762         }
1763         if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1764                 snd_iprintf(buffer, "\n  sample rate: no valid signal\n");
1765         } else {
1766                 if (n) {
1767                         snd_iprintf(buffer, " (8 channels)\n");
1768                 } else {
1769                         snd_iprintf(buffer, " (2 channels)\n");
1770                 }
1771                 snd_iprintf(buffer, "  sample rate: %d Hz\n",
1772                             snd_rme96_capture_getrate(rme96, &n));
1773         }
1774         if (rme96->wcreg & RME96_WCR_MODE24_2) {
1775                 snd_iprintf(buffer, "  sample format: 24 bit\n");
1776         } else {
1777                 snd_iprintf(buffer, "  sample format: 16 bit\n");
1778         }
1779         
1780         snd_iprintf(buffer, "\nOutput settings\n");
1781         if (rme96->wcreg & RME96_WCR_SEL) {
1782                 snd_iprintf(buffer, "  output signal: normal playback\n");
1783         } else {
1784                 snd_iprintf(buffer, "  output signal: same as input\n");
1785         }
1786         snd_iprintf(buffer, "  sample rate: %d Hz\n",
1787                     snd_rme96_playback_getrate(rme96));
1788         if (rme96->wcreg & RME96_WCR_MODE24) {
1789                 snd_iprintf(buffer, "  sample format: 24 bit\n");
1790         } else {
1791                 snd_iprintf(buffer, "  sample format: 16 bit\n");
1792         }
1793         if (rme96->areg & RME96_AR_WSEL) {
1794                 snd_iprintf(buffer, "  sample clock source: word clock\n");
1795         } else if (rme96->wcreg & RME96_WCR_MASTER) {
1796                 snd_iprintf(buffer, "  sample clock source: internal\n");
1797         } else if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1798                 snd_iprintf(buffer, "  sample clock source: autosync (internal anyway due to analog input setting)\n");
1799         } else if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1800                 snd_iprintf(buffer, "  sample clock source: autosync (internal anyway due to no valid signal)\n");
1801         } else {
1802                 snd_iprintf(buffer, "  sample clock source: autosync\n");
1803         }
1804         if (rme96->wcreg & RME96_WCR_PRO) {
1805                 snd_iprintf(buffer, "  format: AES/EBU (professional)\n");
1806         } else {
1807                 snd_iprintf(buffer, "  format: IEC958 (consumer)\n");
1808         }
1809         if (rme96->wcreg & RME96_WCR_EMP) {
1810                 snd_iprintf(buffer, "  emphasis: on\n");
1811         } else {
1812                 snd_iprintf(buffer, "  emphasis: off\n");
1813         }
1814         if (rme96->wcreg & RME96_WCR_DOLBY) {
1815                 snd_iprintf(buffer, "  non-audio (dolby): on\n");
1816         } else {
1817                 snd_iprintf(buffer, "  non-audio (dolby): off\n");
1818         }
1819         if (RME96_HAS_ANALOG_IN(rme96)) {
1820                 snd_iprintf(buffer, "\nAnalog output settings\n");
1821                 switch (snd_rme96_getmontracks(rme96)) {
1822                 case RME96_MONITOR_TRACKS_1_2:
1823                         snd_iprintf(buffer, "  monitored ADAT tracks: 1+2\n");
1824                         break;
1825                 case RME96_MONITOR_TRACKS_3_4:
1826                         snd_iprintf(buffer, "  monitored ADAT tracks: 3+4\n");
1827                         break;
1828                 case RME96_MONITOR_TRACKS_5_6:
1829                         snd_iprintf(buffer, "  monitored ADAT tracks: 5+6\n");
1830                         break;
1831                 case RME96_MONITOR_TRACKS_7_8:
1832                         snd_iprintf(buffer, "  monitored ADAT tracks: 7+8\n");
1833                         break;
1834                 }
1835                 switch (snd_rme96_getattenuation(rme96)) {
1836                 case RME96_ATTENUATION_0:
1837                         snd_iprintf(buffer, "  attenuation: 0 dB\n");
1838                         break;
1839                 case RME96_ATTENUATION_6:
1840                         snd_iprintf(buffer, "  attenuation: -6 dB\n");
1841                         break;
1842                 case RME96_ATTENUATION_12:
1843                         snd_iprintf(buffer, "  attenuation: -12 dB\n");
1844                         break;
1845                 case RME96_ATTENUATION_18:
1846                         snd_iprintf(buffer, "  attenuation: -18 dB\n");
1847                         break;
1848                 }
1849                 snd_iprintf(buffer, "  volume left: %u\n", rme96->vol[0]);
1850                 snd_iprintf(buffer, "  volume right: %u\n", rme96->vol[1]);
1851         }
1852 }
1853 
1854 static void snd_rme96_proc_init(struct rme96 *rme96)
1855 {
1856         struct snd_info_entry *entry;
1857 
1858         if (! snd_card_proc_new(rme96->card, "rme96", &entry))
1859                 snd_info_set_text_ops(entry, rme96, snd_rme96_proc_read);
1860 }
1861 
1862 /*
1863  * control interface
1864  */
1865 
1866 #define snd_rme96_info_loopback_control         snd_ctl_boolean_mono_info
1867 
1868 static int
1869 snd_rme96_get_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1870 {
1871         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1872         
1873         spin_lock_irq(&rme96->lock);
1874         ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1;
1875         spin_unlock_irq(&rme96->lock);
1876         return 0;
1877 }
1878 static int
1879 snd_rme96_put_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1880 {
1881         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1882         unsigned int val;
1883         int change;
1884         
1885         val = ucontrol->value.integer.value[0] ? 0 : RME96_WCR_SEL;
1886         spin_lock_irq(&rme96->lock);
1887         val = (rme96->wcreg & ~RME96_WCR_SEL) | val;
1888         change = val != rme96->wcreg;
1889         rme96->wcreg = val;
1890         writel(val, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1891         spin_unlock_irq(&rme96->lock);
1892         return change;
1893 }
1894 
1895 static int
1896 snd_rme96_info_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1897 {
1898         static char *_texts[5] = { "Optical", "Coaxial", "Internal", "XLR", "Analog" };
1899         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1900         char *texts[5] = { _texts[0], _texts[1], _texts[2], _texts[3], _texts[4] };
1901         
1902         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1903         uinfo->count = 1;
1904         switch (rme96->pci->device) {
1905         case PCI_DEVICE_ID_RME_DIGI96:
1906         case PCI_DEVICE_ID_RME_DIGI96_8:
1907                 uinfo->value.enumerated.items = 3;
1908                 break;
1909         case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1910                 uinfo->value.enumerated.items = 4;
1911                 break;
1912         case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1913                 if (rme96->rev > 4) {
1914                         /* PST */
1915                         uinfo->value.enumerated.items = 4;
1916                         texts[3] = _texts[4]; /* Analog instead of XLR */
1917                 } else {
1918                         /* PAD */
1919                         uinfo->value.enumerated.items = 5;
1920                 }
1921                 break;
1922         default:
1923                 snd_BUG();
1924                 break;
1925         }
1926         if (uinfo->value.enumerated.item > uinfo->value.enumerated.items - 1) {
1927                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1928         }
1929         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1930         return 0;
1931 }
1932 static int
1933 snd_rme96_get_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1934 {
1935         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1936         unsigned int items = 3;
1937         
1938         spin_lock_irq(&rme96->lock);
1939         ucontrol->value.enumerated.item[0] = snd_rme96_getinputtype(rme96);
1940         
1941         switch (rme96->pci->device) {
1942         case PCI_DEVICE_ID_RME_DIGI96:
1943         case PCI_DEVICE_ID_RME_DIGI96_8:
1944                 items = 3;
1945                 break;
1946         case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1947                 items = 4;
1948                 break;
1949         case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1950                 if (rme96->rev > 4) {
1951                         /* for handling PST case, (INPUT_ANALOG is moved to INPUT_XLR */
1952                         if (ucontrol->value.enumerated.item[0] == RME96_INPUT_ANALOG) {
1953                                 ucontrol->value.enumerated.item[0] = RME96_INPUT_XLR;
1954                         }
1955                         items = 4;
1956                 } else {
1957                         items = 5;
1958                 }
1959                 break;
1960         default:
1961                 snd_BUG();
1962                 break;
1963         }
1964         if (ucontrol->value.enumerated.item[0] >= items) {
1965                 ucontrol->value.enumerated.item[0] = items - 1;
1966         }
1967         
1968         spin_unlock_irq(&rme96->lock);
1969         return 0;
1970 }
1971 static int
1972 snd_rme96_put_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1973 {
1974         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1975         unsigned int val;
1976         int change, items = 3;
1977         
1978         switch (rme96->pci->device) {
1979         case PCI_DEVICE_ID_RME_DIGI96:
1980         case PCI_DEVICE_ID_RME_DIGI96_8:
1981                 items = 3;
1982                 break;
1983         case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1984                 items = 4;
1985                 break;
1986         case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1987                 if (rme96->rev > 4) {
1988                         items = 4;
1989                 } else {
1990                         items = 5;
1991                 }
1992                 break;
1993         default:
1994                 snd_BUG();
1995                 break;
1996         }
1997         val = ucontrol->value.enumerated.item[0] % items;
1998         
1999         /* special case for PST */
2000         if (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && rme96->rev > 4) {
2001                 if (val == RME96_INPUT_XLR) {
2002                         val = RME96_INPUT_ANALOG;
2003                 }
2004         }
2005         
2006         spin_lock_irq(&rme96->lock);
2007         change = (int)val != snd_rme96_getinputtype(rme96);
2008         snd_rme96_setinputtype(rme96, val);
2009         spin_unlock_irq(&rme96->lock);
2010         return change;
2011 }
2012 
2013 static int
2014 snd_rme96_info_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2015 {
2016         static char *texts[3] = { "AutoSync", "Internal", "Word" };
2017         
2018         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2019         uinfo->count = 1;
2020         uinfo->value.enumerated.items = 3;
2021         if (uinfo->value.enumerated.item > 2) {
2022                 uinfo->value.enumerated.item = 2;
2023         }
2024         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2025         return 0;
2026 }
2027 static int
2028 snd_rme96_get_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2029 {
2030         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2031         
2032         spin_lock_irq(&rme96->lock);
2033         ucontrol->value.enumerated.item[0] = snd_rme96_getclockmode(rme96);
2034         spin_unlock_irq(&rme96->lock);
2035         return 0;
2036 }
2037 static int
2038 snd_rme96_put_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2039 {
2040         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2041         unsigned int val;
2042         int change;
2043         
2044         val = ucontrol->value.enumerated.item[0] % 3;
2045         spin_lock_irq(&rme96->lock);
2046         change = (int)val != snd_rme96_getclockmode(rme96);
2047         snd_rme96_setclockmode(rme96, val);
2048         spin_unlock_irq(&rme96->lock);
2049         return change;
2050 }
2051 
2052 static int
2053 snd_rme96_info_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2054 {
2055         static char *texts[4] = { "0 dB", "-6 dB", "-12 dB", "-18 dB" };
2056         
2057         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2058         uinfo->count = 1;
2059         uinfo->value.enumerated.items = 4;
2060         if (uinfo->value.enumerated.item > 3) {
2061                 uinfo->value.enumerated.item = 3;
2062         }
2063         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2064         return 0;
2065 }
2066 static int
2067 snd_rme96_get_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2068 {
2069         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2070         
2071         spin_lock_irq(&rme96->lock);
2072         ucontrol->value.enumerated.item[0] = snd_rme96_getattenuation(rme96);
2073         spin_unlock_irq(&rme96->lock);
2074         return 0;
2075 }
2076 static int
2077 snd_rme96_put_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2078 {
2079         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2080         unsigned int val;
2081         int change;
2082         
2083         val = ucontrol->value.enumerated.item[0] % 4;
2084         spin_lock_irq(&rme96->lock);
2085 
2086         change = (int)val != snd_rme96_getattenuation(rme96);
2087         snd_rme96_setattenuation(rme96, val);
2088         spin_unlock_irq(&rme96->lock);
2089         return change;
2090 }
2091 
2092 static int
2093 snd_rme96_info_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2094 {
2095         static char *texts[4] = { "1+2", "3+4", "5+6", "7+8" };
2096         
2097         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2098         uinfo->count = 1;
2099         uinfo->value.enumerated.items = 4;
2100         if (uinfo->value.enumerated.item > 3) {
2101                 uinfo->value.enumerated.item = 3;
2102         }
2103         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2104         return 0;
2105 }
2106 static int
2107 snd_rme96_get_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2108 {
2109         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2110         
2111         spin_lock_irq(&rme96->lock);
2112         ucontrol->value.enumerated.item[0] = snd_rme96_getmontracks(rme96);
2113         spin_unlock_irq(&rme96->lock);
2114         return 0;
2115 }
2116 static int
2117 snd_rme96_put_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2118 {
2119         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2120         unsigned int val;
2121         int change;
2122         
2123         val = ucontrol->value.enumerated.item[0] % 4;
2124         spin_lock_irq(&rme96->lock);
2125         change = (int)val != snd_rme96_getmontracks(rme96);
2126         snd_rme96_setmontracks(rme96, val);
2127         spin_unlock_irq(&rme96->lock);
2128         return change;
2129 }
2130 
2131 static u32 snd_rme96_convert_from_aes(struct snd_aes_iec958 *aes)
2132 {
2133         u32 val = 0;
2134         val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME96_WCR_PRO : 0;
2135         val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME96_WCR_DOLBY : 0;
2136         if (val & RME96_WCR_PRO)
2137                 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2138         else
2139                 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2140         return val;
2141 }
2142 
2143 static void snd_rme96_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
2144 {
2145         aes->status[0] = ((val & RME96_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0) |
2146                          ((val & RME96_WCR_DOLBY) ? IEC958_AES0_NONAUDIO : 0);
2147         if (val & RME96_WCR_PRO)
2148                 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
2149         else
2150                 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
2151 }
2152 
2153 static int snd_rme96_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2154 {
2155         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2156         uinfo->count = 1;
2157         return 0;
2158 }
2159 
2160 static int snd_rme96_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2161 {
2162         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2163         
2164         snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif);
2165         return 0;
2166 }
2167 
2168 static int snd_rme96_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2169 {
2170         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2171         int change;
2172         u32 val;
2173         
2174         val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2175         spin_lock_irq(&rme96->lock);
2176         change = val != rme96->wcreg_spdif;
2177         rme96->wcreg_spdif = val;
2178         spin_unlock_irq(&rme96->lock);
2179         return change;
2180 }
2181 
2182 static int snd_rme96_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2183 {
2184         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2185         uinfo->count = 1;
2186         return 0;
2187 }
2188 
2189 static int snd_rme96_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2190 {
2191         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2192         
2193         snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif_stream);
2194         return 0;
2195 }
2196 
2197 static int snd_rme96_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2198 {
2199         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2200         int change;
2201         u32 val;
2202         
2203         val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2204         spin_lock_irq(&rme96->lock);
2205         change = val != rme96->wcreg_spdif_stream;
2206         rme96->wcreg_spdif_stream = val;
2207         rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
2208         rme96->wcreg |= val;
2209         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
2210         spin_unlock_irq(&rme96->lock);
2211         return change;
2212 }
2213 
2214 static int snd_rme96_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2215 {
2216         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2217         uinfo->count = 1;
2218         return 0;
2219 }
2220 
2221 static int snd_rme96_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2222 {
2223         ucontrol->value.iec958.status[0] = kcontrol->private_value;
2224         return 0;
2225 }
2226 
2227 static int
2228 snd_rme96_dac_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2229 {
2230         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2231         
2232         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2233         uinfo->count = 2;
2234         uinfo->value.integer.min = 0;
2235         uinfo->value.integer.max = RME96_185X_MAX_OUT(rme96);
2236         return 0;
2237 }
2238 
2239 static int
2240 snd_rme96_dac_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u)
2241 {
2242         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2243 
2244         spin_lock_irq(&rme96->lock);
2245         u->value.integer.value[0] = rme96->vol[0];
2246         u->value.integer.value[1] = rme96->vol[1];
2247         spin_unlock_irq(&rme96->lock);
2248 
2249         return 0;
2250 }
2251 
2252 static int
2253 snd_rme96_dac_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u)
2254 {
2255         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2256         int change = 0;
2257         unsigned int vol, maxvol;
2258 
2259 
2260         if (!RME96_HAS_ANALOG_OUT(rme96))
2261                 return -EINVAL;
2262         maxvol = RME96_185X_MAX_OUT(rme96);
2263         spin_lock_irq(&rme96->lock);
2264         vol = u->value.integer.value[0];
2265         if (vol != rme96->vol[0] && vol <= maxvol) {
2266                 rme96->vol[0] = vol;
2267                 change = 1;
2268         }
2269         vol = u->value.integer.value[1];
2270         if (vol != rme96->vol[1] && vol <= maxvol) {
2271                 rme96->vol[1] = vol;
2272                 change = 1;
2273         }
2274         if (change)
2275                 snd_rme96_apply_dac_volume(rme96);
2276         spin_unlock_irq(&rme96->lock);
2277 
2278         return change;
2279 }
2280 
2281 static struct snd_kcontrol_new snd_rme96_controls[] = {
2282 {
2283         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2284         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2285         .info =         snd_rme96_control_spdif_info,
2286         .get =          snd_rme96_control_spdif_get,
2287         .put =          snd_rme96_control_spdif_put
2288 },
2289 {
2290         .access =       SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2291         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2292         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2293         .info =         snd_rme96_control_spdif_stream_info,
2294         .get =          snd_rme96_control_spdif_stream_get,
2295         .put =          snd_rme96_control_spdif_stream_put
2296 },
2297 {
2298         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
2299         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2300         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2301         .info =         snd_rme96_control_spdif_mask_info,
2302         .get =          snd_rme96_control_spdif_mask_get,
2303         .private_value = IEC958_AES0_NONAUDIO |
2304                         IEC958_AES0_PROFESSIONAL |
2305                         IEC958_AES0_CON_EMPHASIS
2306 },
2307 {
2308         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
2309         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2310         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2311         .info =         snd_rme96_control_spdif_mask_info,
2312         .get =          snd_rme96_control_spdif_mask_get,
2313         .private_value = IEC958_AES0_NONAUDIO |
2314                         IEC958_AES0_PROFESSIONAL |
2315                         IEC958_AES0_PRO_EMPHASIS
2316 },
2317 {
2318         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2319         .name =         "Input Connector",
2320         .info =         snd_rme96_info_inputtype_control, 
2321         .get =          snd_rme96_get_inputtype_control,
2322         .put =          snd_rme96_put_inputtype_control 
2323 },
2324 {
2325         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2326         .name =         "Loopback Input",
2327         .info =         snd_rme96_info_loopback_control,
2328         .get =          snd_rme96_get_loopback_control,
2329         .put =          snd_rme96_put_loopback_control
2330 },
2331 {
2332         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2333         .name =         "Sample Clock Source",
2334         .info =         snd_rme96_info_clockmode_control, 
2335         .get =          snd_rme96_get_clockmode_control,
2336         .put =          snd_rme96_put_clockmode_control
2337 },
2338 {
2339         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2340         .name =         "Monitor Tracks",
2341         .info =         snd_rme96_info_montracks_control, 
2342         .get =          snd_rme96_get_montracks_control,
2343         .put =          snd_rme96_put_montracks_control
2344 },
2345 {
2346         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2347         .name =         "Attenuation",
2348         .info =         snd_rme96_info_attenuation_control, 
2349         .get =          snd_rme96_get_attenuation_control,
2350         .put =          snd_rme96_put_attenuation_control
2351 },
2352 {
2353         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2354         .name =         "DAC Playback Volume",
2355         .info =         snd_rme96_dac_volume_info,
2356         .get =          snd_rme96_dac_volume_get,
2357         .put =          snd_rme96_dac_volume_put
2358 }
2359 };
2360 
2361 static int
2362 snd_rme96_create_switches(struct snd_card *card,
2363                           struct rme96 *rme96)
2364 {
2365         int idx, err;
2366         struct snd_kcontrol *kctl;
2367 
2368         for (idx = 0; idx < 7; idx++) {
2369                 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
2370                         return err;
2371                 if (idx == 1)   /* IEC958 (S/PDIF) Stream */
2372                         rme96->spdif_ctl = kctl;
2373         }
2374 
2375         if (RME96_HAS_ANALOG_OUT(rme96)) {
2376                 for (idx = 7; idx < 10; idx++)
2377                         if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
2378                                 return err;
2379         }
2380         
2381         return 0;
2382 }
2383 
2384 /*
2385  * Card initialisation
2386  */
2387 
2388 #ifdef CONFIG_PM
2389 
2390 static int
2391 snd_rme96_suspend(struct pci_dev *pci,
2392                   pm_message_t state)
2393 {
2394         struct snd_card *card = pci_get_drvdata(pci);
2395         struct rme96 *rme96 = card->private_data;
2396 
2397         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2398         snd_pcm_suspend(rme96->playback_substream);
2399         snd_pcm_suspend(rme96->capture_substream);
2400 
2401         /* save capture & playback pointers */
2402         rme96->playback_pointer = readl(rme96->iobase + RME96_IO_GET_PLAY_POS)
2403                                   & RME96_RCR_AUDIO_ADDR_MASK;
2404         rme96->capture_pointer = readl(rme96->iobase + RME96_IO_GET_REC_POS)
2405                                  & RME96_RCR_AUDIO_ADDR_MASK;
2406 
2407         /* save playback and capture buffers */
2408         memcpy_fromio(rme96->playback_suspend_buffer,
2409                       rme96->iobase + RME96_IO_PLAY_BUFFER, RME96_BUFFER_SIZE);
2410         memcpy_fromio(rme96->capture_suspend_buffer,
2411                       rme96->iobase + RME96_IO_REC_BUFFER, RME96_BUFFER_SIZE);
2412 
2413         /* disable the DAC  */
2414         rme96->areg &= ~RME96_AR_DAC_EN;
2415         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
2416 
2417         pci_disable_device(pci);
2418         pci_save_state(pci);
2419 
2420         return 0;
2421 }
2422 
2423 static int
2424 snd_rme96_resume(struct pci_dev *pci)
2425 {
2426         struct snd_card *card = pci_get_drvdata(pci);
2427         struct rme96 *rme96 = card->private_data;
2428 
2429         pci_restore_state(pci);
2430         if (pci_enable_device(pci) < 0) {
2431                 printk(KERN_ERR "rme96: pci_enable_device failed, disabling device\n");
2432                 snd_card_disconnect(card);
2433                 return -EIO;
2434         }
2435 
2436         /* reset playback and record buffer pointers */
2437         writel(0, rme96->iobase + RME96_IO_SET_PLAY_POS
2438                   + rme96->playback_pointer);
2439         writel(0, rme96->iobase + RME96_IO_SET_REC_POS
2440                   + rme96->capture_pointer);
2441 
2442         /* restore playback and capture buffers */
2443         memcpy_toio(rme96->iobase + RME96_IO_PLAY_BUFFER,
2444                     rme96->playback_suspend_buffer, RME96_BUFFER_SIZE);
2445         memcpy_toio(rme96->iobase + RME96_IO_REC_BUFFER,
2446                     rme96->capture_suspend_buffer, RME96_BUFFER_SIZE);
2447 
2448         /* reset the ADC */
2449         writel(rme96->areg | RME96_AR_PD2,
2450                rme96->iobase + RME96_IO_ADDITIONAL_REG);
2451         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
2452 
2453         /* reset and enable DAC, restore analog volume */
2454         snd_rme96_reset_dac(rme96);
2455         rme96->areg |= RME96_AR_DAC_EN;
2456         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
2457         if (RME96_HAS_ANALOG_OUT(rme96)) {
2458                 usleep_range(3000, 10000);
2459                 snd_rme96_apply_dac_volume(rme96);
2460         }
2461 
2462         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2463 
2464         return 0;
2465 }
2466 
2467 #endif
2468 
2469 static void snd_rme96_card_free(struct snd_card *card)
2470 {
2471         snd_rme96_free(card->private_data);
2472 }
2473 
2474 static int
2475 snd_rme96_probe(struct pci_dev *pci,
2476                 const struct pci_device_id *pci_id)
2477 {
2478         static int dev;
2479         struct rme96 *rme96;
2480         struct snd_card *card;
2481         int err;
2482         u8 val;
2483 
2484         if (dev >= SNDRV_CARDS) {
2485                 return -ENODEV;
2486         }
2487         if (!enable[dev]) {
2488                 dev++;
2489                 return -ENOENT;
2490         }
2491         err = snd_card_create(index[dev], id[dev], THIS_MODULE,
2492                               sizeof(struct rme96), &card);
2493         if (err < 0)
2494                 return err;
2495         card->private_free = snd_rme96_card_free;
2496         rme96 = card->private_data;
2497         rme96->card = card;
2498         rme96->pci = pci;
2499         snd_card_set_dev(card, &pci->dev);
2500         if ((err = snd_rme96_create(rme96)) < 0) {
2501                 snd_card_free(card);
2502                 return err;
2503         }
2504         
2505 #ifdef CONFIG_PM
2506         rme96->playback_suspend_buffer = vmalloc(RME96_BUFFER_SIZE);
2507         if (!rme96->playback_suspend_buffer) {
2508                 snd_printk(KERN_ERR
2509                            "Failed to allocate playback suspend buffer!\n");
2510                 snd_card_free(card);
2511                 return -ENOMEM;
2512         }
2513         rme96->capture_suspend_buffer = vmalloc(RME96_BUFFER_SIZE);
2514         if (!rme96->capture_suspend_buffer) {
2515                 snd_printk(KERN_ERR
2516                            "Failed to allocate capture suspend buffer!\n");
2517                 snd_card_free(card);
2518                 return -ENOMEM;
2519         }
2520 #endif
2521 
2522         strcpy(card->driver, "Digi96");
2523         switch (rme96->pci->device) {
2524         case PCI_DEVICE_ID_RME_DIGI96:
2525                 strcpy(card->shortname, "RME Digi96");
2526                 break;
2527         case PCI_DEVICE_ID_RME_DIGI96_8:
2528                 strcpy(card->shortname, "RME Digi96/8");
2529                 break;
2530         case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
2531                 strcpy(card->shortname, "RME Digi96/8 PRO");
2532                 break;
2533         case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
2534                 pci_read_config_byte(rme96->pci, 8, &val);
2535                 if (val < 5) {
2536                         strcpy(card->shortname, "RME Digi96/8 PAD");
2537                 } else {
2538                         strcpy(card->shortname, "RME Digi96/8 PST");
2539                 }
2540                 break;
2541         }
2542         sprintf(card->longname, "%s at 0x%lx, irq %d", card->shortname,
2543                 rme96->port, rme96->irq);
2544         
2545         if ((err = snd_card_register(card)) < 0) {
2546                 snd_card_free(card);
2547                 return err;     
2548         }
2549         pci_set_drvdata(pci, card);
2550         dev++;
2551         return 0;
2552 }
2553 
2554 static void snd_rme96_remove(struct pci_dev *pci)
2555 {
2556         snd_card_free(pci_get_drvdata(pci));
2557 }
2558 
2559 static struct pci_driver rme96_driver = {
2560         .name = KBUILD_MODNAME,
2561         .id_table = snd_rme96_ids,
2562         .probe = snd_rme96_probe,
2563         .remove = snd_rme96_remove,
2564 #ifdef CONFIG_PM
2565         .suspend = snd_rme96_suspend,
2566         .resume = snd_rme96_resume,
2567 #endif
2568 };
2569 
2570 module_pci_driver(rme96_driver);
2571 

~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

kernel.org | git.kernel.org | LWN.net | Project Home | Wiki (Japanese) | Wiki (English) | SVN repository | Mail admin

Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.

osdn.jp