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TOMOYO Linux Cross Reference
Linux/sound/pci/rme9652/hdspm.c

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  1 /*
  2  *   ALSA driver for RME Hammerfall DSP MADI audio interface(s)
  3  *
  4  *      Copyright (c) 2003 Winfried Ritsch (IEM)
  5  *      code based on hdsp.c   Paul Davis
  6  *                             Marcus Andersson
  7  *                             Thomas Charbonnel
  8  *      Modified 2006-06-01 for AES32 support by Remy Bruno
  9  *                                               <remy.bruno@trinnov.com>
 10  *
 11  *      Modified 2009-04-13 for proper metering by Florian Faber
 12  *                                               <faber@faberman.de>
 13  *
 14  *      Modified 2009-04-14 for native float support by Florian Faber
 15  *                                               <faber@faberman.de>
 16  *
 17  *      Modified 2009-04-26 fixed bug in rms metering by Florian Faber
 18  *                                               <faber@faberman.de>
 19  *
 20  *      Modified 2009-04-30 added hw serial number support by Florian Faber
 21  *
 22  *      Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth
 23  *
 24  *      Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth
 25  *
 26  *   This program is free software; you can redistribute it and/or modify
 27  *   it under the terms of the GNU General Public License as published by
 28  *   the Free Software Foundation; either version 2 of the License, or
 29  *   (at your option) any later version.
 30  *
 31  *   This program is distributed in the hope that it will be useful,
 32  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 33  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 34  *   GNU General Public License for more details.
 35  *
 36  *   You should have received a copy of the GNU General Public License
 37  *   along with this program; if not, write to the Free Software
 38  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 39  *
 40  */
 41 #include <linux/init.h>
 42 #include <linux/delay.h>
 43 #include <linux/interrupt.h>
 44 #include <linux/module.h>
 45 #include <linux/slab.h>
 46 #include <linux/pci.h>
 47 #include <linux/math64.h>
 48 #include <asm/io.h>
 49 
 50 #include <sound/core.h>
 51 #include <sound/control.h>
 52 #include <sound/pcm.h>
 53 #include <sound/pcm_params.h>
 54 #include <sound/info.h>
 55 #include <sound/asoundef.h>
 56 #include <sound/rawmidi.h>
 57 #include <sound/hwdep.h>
 58 #include <sound/initval.h>
 59 
 60 #include <sound/hdspm.h>
 61 
 62 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;        /* Index 0-MAX */
 63 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;         /* ID for this card */
 64 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
 65 
 66 module_param_array(index, int, NULL, 0444);
 67 MODULE_PARM_DESC(index, "Index value for RME HDSPM interface.");
 68 
 69 module_param_array(id, charp, NULL, 0444);
 70 MODULE_PARM_DESC(id, "ID string for RME HDSPM interface.");
 71 
 72 module_param_array(enable, bool, NULL, 0444);
 73 MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards.");
 74 
 75 
 76 MODULE_AUTHOR
 77 (
 78         "Winfried Ritsch <ritsch_AT_iem.at>, "
 79         "Paul Davis <paul@linuxaudiosystems.com>, "
 80         "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, "
 81         "Remy Bruno <remy.bruno@trinnov.com>, "
 82         "Florian Faber <faberman@linuxproaudio.org>, "
 83         "Adrian Knoth <adi@drcomp.erfurt.thur.de>"
 84 );
 85 MODULE_DESCRIPTION("RME HDSPM");
 86 MODULE_LICENSE("GPL");
 87 MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}");
 88 
 89 /* --- Write registers. ---
 90   These are defined as byte-offsets from the iobase value.  */
 91 
 92 #define HDSPM_WR_SETTINGS             0
 93 #define HDSPM_outputBufferAddress    32
 94 #define HDSPM_inputBufferAddress     36
 95 #define HDSPM_controlRegister        64
 96 #define HDSPM_interruptConfirmation  96
 97 #define HDSPM_control2Reg            256  /* not in specs ???????? */
 98 #define HDSPM_freqReg                256  /* for AES32 */
 99 #define HDSPM_midiDataOut0           352  /* just believe in old code */
100 #define HDSPM_midiDataOut1           356
101 #define HDSPM_eeprom_wr              384  /* for AES32 */
102 
103 /* DMA enable for 64 channels, only Bit 0 is relevant */
104 #define HDSPM_outputEnableBase       512  /* 512-767  input  DMA */
105 #define HDSPM_inputEnableBase        768  /* 768-1023 output DMA */
106 
107 /* 16 page addresses for each of the 64 channels DMA buffer in and out
108    (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */
109 #define HDSPM_pageAddressBufferOut       8192
110 #define HDSPM_pageAddressBufferIn        (HDSPM_pageAddressBufferOut+64*16*4)
111 
112 #define HDSPM_MADI_mixerBase    32768   /* 32768-65535 for 2x64x64 Fader */
113 
114 #define HDSPM_MATRIX_MIXER_SIZE  8192   /* = 2*64*64 * 4 Byte => 32kB */
115 
116 /* --- Read registers. ---
117    These are defined as byte-offsets from the iobase value */
118 #define HDSPM_statusRegister    0
119 /*#define HDSPM_statusRegister2  96 */
120 /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at
121  * offset 192, for AES32 *and* MADI
122  * => need to check that offset 192 is working on MADI */
123 #define HDSPM_statusRegister2  192
124 #define HDSPM_timecodeRegister 128
125 
126 /* AIO, RayDAT */
127 #define HDSPM_RD_STATUS_0 0
128 #define HDSPM_RD_STATUS_1 64
129 #define HDSPM_RD_STATUS_2 128
130 #define HDSPM_RD_STATUS_3 192
131 
132 #define HDSPM_RD_TCO           256
133 #define HDSPM_RD_PLL_FREQ      512
134 #define HDSPM_WR_TCO           128
135 
136 #define HDSPM_TCO1_TCO_lock                     0x00000001
137 #define HDSPM_TCO1_WCK_Input_Range_LSB          0x00000002
138 #define HDSPM_TCO1_WCK_Input_Range_MSB          0x00000004
139 #define HDSPM_TCO1_LTC_Input_valid              0x00000008
140 #define HDSPM_TCO1_WCK_Input_valid              0x00000010
141 #define HDSPM_TCO1_Video_Input_Format_NTSC      0x00000020
142 #define HDSPM_TCO1_Video_Input_Format_PAL       0x00000040
143 
144 #define HDSPM_TCO1_set_TC                       0x00000100
145 #define HDSPM_TCO1_set_drop_frame_flag          0x00000200
146 #define HDSPM_TCO1_LTC_Format_LSB               0x00000400
147 #define HDSPM_TCO1_LTC_Format_MSB               0x00000800
148 
149 #define HDSPM_TCO2_TC_run                       0x00010000
150 #define HDSPM_TCO2_WCK_IO_ratio_LSB             0x00020000
151 #define HDSPM_TCO2_WCK_IO_ratio_MSB             0x00040000
152 #define HDSPM_TCO2_set_num_drop_frames_LSB      0x00080000
153 #define HDSPM_TCO2_set_num_drop_frames_MSB      0x00100000
154 #define HDSPM_TCO2_set_jam_sync                 0x00200000
155 #define HDSPM_TCO2_set_flywheel                 0x00400000
156 
157 #define HDSPM_TCO2_set_01_4                     0x01000000
158 #define HDSPM_TCO2_set_pull_down                0x02000000
159 #define HDSPM_TCO2_set_pull_up                  0x04000000
160 #define HDSPM_TCO2_set_freq                     0x08000000
161 #define HDSPM_TCO2_set_term_75R                 0x10000000
162 #define HDSPM_TCO2_set_input_LSB                0x20000000
163 #define HDSPM_TCO2_set_input_MSB                0x40000000
164 #define HDSPM_TCO2_set_freq_from_app            0x80000000
165 
166 
167 #define HDSPM_midiDataOut0    352
168 #define HDSPM_midiDataOut1    356
169 #define HDSPM_midiDataOut2    368
170 
171 #define HDSPM_midiDataIn0     360
172 #define HDSPM_midiDataIn1     364
173 #define HDSPM_midiDataIn2     372
174 #define HDSPM_midiDataIn3     376
175 
176 /* status is data bytes in MIDI-FIFO (0-128) */
177 #define HDSPM_midiStatusOut0  384
178 #define HDSPM_midiStatusOut1  388
179 #define HDSPM_midiStatusOut2  400
180 
181 #define HDSPM_midiStatusIn0   392
182 #define HDSPM_midiStatusIn1   396
183 #define HDSPM_midiStatusIn2   404
184 #define HDSPM_midiStatusIn3   408
185 
186 
187 /* the meters are regular i/o-mapped registers, but offset
188    considerably from the rest. the peak registers are reset
189    when read; the least-significant 4 bits are full-scale counters;
190    the actual peak value is in the most-significant 24 bits.
191 */
192 
193 #define HDSPM_MADI_INPUT_PEAK           4096
194 #define HDSPM_MADI_PLAYBACK_PEAK        4352
195 #define HDSPM_MADI_OUTPUT_PEAK          4608
196 
197 #define HDSPM_MADI_INPUT_RMS_L          6144
198 #define HDSPM_MADI_PLAYBACK_RMS_L       6400
199 #define HDSPM_MADI_OUTPUT_RMS_L         6656
200 
201 #define HDSPM_MADI_INPUT_RMS_H          7168
202 #define HDSPM_MADI_PLAYBACK_RMS_H       7424
203 #define HDSPM_MADI_OUTPUT_RMS_H         7680
204 
205 /* --- Control Register bits --------- */
206 #define HDSPM_Start                (1<<0) /* start engine */
207 
208 #define HDSPM_Latency0             (1<<1) /* buffer size = 2^n */
209 #define HDSPM_Latency1             (1<<2) /* where n is defined */
210 #define HDSPM_Latency2             (1<<3) /* by Latency{2,1,0} */
211 
212 #define HDSPM_ClockModeMaster      (1<<4) /* 1=Master, 0=Autosync */
213 #define HDSPM_c0Master          0x1    /* Master clock bit in settings
214                                           register [RayDAT, AIO] */
215 
216 #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */
217 
218 #define HDSPM_Frequency0  (1<<6)  /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */
219 #define HDSPM_Frequency1  (1<<7)  /* 0=32kHz/64kHz */
220 #define HDSPM_DoubleSpeed (1<<8)  /* 0=normal speed, 1=double speed */
221 #define HDSPM_QuadSpeed   (1<<31) /* quad speed bit */
222 
223 #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */
224 #define HDSPM_TX_64ch     (1<<10) /* Output 64channel MODE=1,
225                                      56channelMODE=0 */ /* MADI ONLY*/
226 #define HDSPM_Emphasis    (1<<10) /* Emphasis */ /* AES32 ONLY */
227 
228 #define HDSPM_AutoInp     (1<<11) /* Auto Input (takeover) == Safe Mode,
229                                      0=off, 1=on  */ /* MADI ONLY */
230 #define HDSPM_Dolby       (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */
231 
232 #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax
233                                     * -- MADI ONLY
234                                     */
235 #define HDSPM_InputSelect1 (1<<15) /* should be 0 */
236 
237 #define HDSPM_SyncRef2     (1<<13)
238 #define HDSPM_SyncRef3     (1<<25)
239 
240 #define HDSPM_SMUX         (1<<18) /* Frame ??? */ /* MADI ONY */
241 #define HDSPM_clr_tms      (1<<19) /* clear track marker, do not use
242                                       AES additional bits in
243                                       lower 5 Audiodatabits ??? */
244 #define HDSPM_taxi_reset   (1<<20) /* ??? */ /* MADI ONLY ? */
245 #define HDSPM_WCK48        (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */
246 
247 #define HDSPM_Midi0InterruptEnable 0x0400000
248 #define HDSPM_Midi1InterruptEnable 0x0800000
249 #define HDSPM_Midi2InterruptEnable 0x0200000
250 #define HDSPM_Midi3InterruptEnable 0x4000000
251 
252 #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */
253 #define HDSPe_FLOAT_FORMAT         0x2000000
254 
255 #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */
256 #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */
257 #define HDSPM_QS_QuadWire   (1<<28) /* AES32 ONLY */
258 
259 #define HDSPM_wclk_sel (1<<30)
260 
261 /* --- bit helper defines */
262 #define HDSPM_LatencyMask    (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2)
263 #define HDSPM_FrequencyMask  (HDSPM_Frequency0|HDSPM_Frequency1|\
264                               HDSPM_DoubleSpeed|HDSPM_QuadSpeed)
265 #define HDSPM_InputMask      (HDSPM_InputSelect0|HDSPM_InputSelect1)
266 #define HDSPM_InputOptical   0
267 #define HDSPM_InputCoaxial   (HDSPM_InputSelect0)
268 #define HDSPM_SyncRefMask    (HDSPM_SyncRef0|HDSPM_SyncRef1|\
269                               HDSPM_SyncRef2|HDSPM_SyncRef3)
270 
271 #define HDSPM_c0_SyncRef0      0x2
272 #define HDSPM_c0_SyncRef1      0x4
273 #define HDSPM_c0_SyncRef2      0x8
274 #define HDSPM_c0_SyncRef3      0x10
275 #define HDSPM_c0_SyncRefMask   (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\
276                                 HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3)
277 
278 #define HDSPM_SYNC_FROM_WORD    0       /* Preferred sync reference */
279 #define HDSPM_SYNC_FROM_MADI    1       /* choices - used by "pref_sync_ref" */
280 #define HDSPM_SYNC_FROM_TCO     2
281 #define HDSPM_SYNC_FROM_SYNC_IN 3
282 
283 #define HDSPM_Frequency32KHz    HDSPM_Frequency0
284 #define HDSPM_Frequency44_1KHz  HDSPM_Frequency1
285 #define HDSPM_Frequency48KHz   (HDSPM_Frequency1|HDSPM_Frequency0)
286 #define HDSPM_Frequency64KHz   (HDSPM_DoubleSpeed|HDSPM_Frequency0)
287 #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1)
288 #define HDSPM_Frequency96KHz   (HDSPM_DoubleSpeed|HDSPM_Frequency1|\
289                                 HDSPM_Frequency0)
290 #define HDSPM_Frequency128KHz   (HDSPM_QuadSpeed|HDSPM_Frequency0)
291 #define HDSPM_Frequency176_4KHz   (HDSPM_QuadSpeed|HDSPM_Frequency1)
292 #define HDSPM_Frequency192KHz   (HDSPM_QuadSpeed|HDSPM_Frequency1|\
293                                  HDSPM_Frequency0)
294 
295 
296 /* Synccheck Status */
297 #define HDSPM_SYNC_CHECK_NO_LOCK 0
298 #define HDSPM_SYNC_CHECK_LOCK    1
299 #define HDSPM_SYNC_CHECK_SYNC    2
300 
301 /* AutoSync References - used by "autosync_ref" control switch */
302 #define HDSPM_AUTOSYNC_FROM_WORD      0
303 #define HDSPM_AUTOSYNC_FROM_MADI      1
304 #define HDSPM_AUTOSYNC_FROM_TCO       2
305 #define HDSPM_AUTOSYNC_FROM_SYNC_IN   3
306 #define HDSPM_AUTOSYNC_FROM_NONE      4
307 
308 /* Possible sources of MADI input */
309 #define HDSPM_OPTICAL 0         /* optical   */
310 #define HDSPM_COAXIAL 1         /* BNC */
311 
312 #define hdspm_encode_latency(x)       (((x)<<1) & HDSPM_LatencyMask)
313 #define hdspm_decode_latency(x)       ((((x) & HDSPM_LatencyMask)>>1))
314 
315 #define hdspm_encode_in(x) (((x)&0x3)<<14)
316 #define hdspm_decode_in(x) (((x)>>14)&0x3)
317 
318 /* --- control2 register bits --- */
319 #define HDSPM_TMS             (1<<0)
320 #define HDSPM_TCK             (1<<1)
321 #define HDSPM_TDI             (1<<2)
322 #define HDSPM_JTAG            (1<<3)
323 #define HDSPM_PWDN            (1<<4)
324 #define HDSPM_PROGRAM         (1<<5)
325 #define HDSPM_CONFIG_MODE_0   (1<<6)
326 #define HDSPM_CONFIG_MODE_1   (1<<7)
327 /*#define HDSPM_VERSION_BIT     (1<<8) not defined any more*/
328 #define HDSPM_BIGENDIAN_MODE  (1<<9)
329 #define HDSPM_RD_MULTIPLE     (1<<10)
330 
331 /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and
332      that do not conflict with specific bits for AES32 seem to be valid also
333      for the AES32
334  */
335 #define HDSPM_audioIRQPending    (1<<0) /* IRQ is high and pending */
336 #define HDSPM_RX_64ch            (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */
337 #define HDSPM_AB_int             (1<<2) /* InputChannel Opt=0, Coax=1
338                                          * (like inp0)
339                                          */
340 
341 #define HDSPM_madiLock           (1<<3) /* MADI Locked =1, no=0 */
342 #define HDSPM_madiSync          (1<<18) /* MADI is in sync */
343 
344 #define HDSPM_tcoLock    0x00000020 /* Optional TCO locked status FOR HDSPe MADI! */
345 #define HDSPM_tcoSync    0x10000000 /* Optional TCO sync status */
346 
347 #define HDSPM_syncInLock 0x00010000 /* Sync In lock status FOR HDSPe MADI! */
348 #define HDSPM_syncInSync 0x00020000 /* Sync In sync status FOR HDSPe MADI! */
349 
350 #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
351                         /* since 64byte accurate, last 6 bits are not used */
352 
353 
354 
355 #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */
356 
357 #define HDSPM_madiFreq0         (1<<22) /* system freq 0=error */
358 #define HDSPM_madiFreq1         (1<<23) /* 1=32, 2=44.1 3=48 */
359 #define HDSPM_madiFreq2         (1<<24) /* 4=64, 5=88.2 6=96 */
360 #define HDSPM_madiFreq3         (1<<25) /* 7=128, 8=176.4 9=192 */
361 
362 #define HDSPM_BufferID          (1<<26) /* (Double)Buffer ID toggles with
363                                          * Interrupt
364                                          */
365 #define HDSPM_tco_detect         0x08000000
366 #define HDSPM_tco_lock           0x20000000
367 
368 #define HDSPM_s2_tco_detect      0x00000040
369 #define HDSPM_s2_AEBO_D          0x00000080
370 #define HDSPM_s2_AEBI_D          0x00000100
371 
372 
373 #define HDSPM_midi0IRQPending    0x40000000
374 #define HDSPM_midi1IRQPending    0x80000000
375 #define HDSPM_midi2IRQPending    0x20000000
376 #define HDSPM_midi2IRQPendingAES 0x00000020
377 #define HDSPM_midi3IRQPending    0x00200000
378 
379 /* --- status bit helpers */
380 #define HDSPM_madiFreqMask  (HDSPM_madiFreq0|HDSPM_madiFreq1|\
381                              HDSPM_madiFreq2|HDSPM_madiFreq3)
382 #define HDSPM_madiFreq32    (HDSPM_madiFreq0)
383 #define HDSPM_madiFreq44_1  (HDSPM_madiFreq1)
384 #define HDSPM_madiFreq48    (HDSPM_madiFreq0|HDSPM_madiFreq1)
385 #define HDSPM_madiFreq64    (HDSPM_madiFreq2)
386 #define HDSPM_madiFreq88_2  (HDSPM_madiFreq0|HDSPM_madiFreq2)
387 #define HDSPM_madiFreq96    (HDSPM_madiFreq1|HDSPM_madiFreq2)
388 #define HDSPM_madiFreq128   (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2)
389 #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3)
390 #define HDSPM_madiFreq192   (HDSPM_madiFreq3|HDSPM_madiFreq0)
391 
392 /* Status2 Register bits */ /* MADI ONLY */
393 
394 #define HDSPM_version0 (1<<0)   /* not really defined but I guess */
395 #define HDSPM_version1 (1<<1)   /* in former cards it was ??? */
396 #define HDSPM_version2 (1<<2)
397 
398 #define HDSPM_wcLock (1<<3)     /* Wordclock is detected and locked */
399 #define HDSPM_wcSync (1<<4)     /* Wordclock is in sync with systemclock */
400 
401 #define HDSPM_wc_freq0 (1<<5)   /* input freq detected via autosync  */
402 #define HDSPM_wc_freq1 (1<<6)   /* 001=32, 010==44.1, 011=48, */
403 #define HDSPM_wc_freq2 (1<<7)   /* 100=64, 101=88.2, 110=96, 111=128 */
404 #define HDSPM_wc_freq3 0x800    /* 1000=176.4, 1001=192 */
405 
406 #define HDSPM_SyncRef0 0x10000  /* Sync Reference */
407 #define HDSPM_SyncRef1 0x20000
408 
409 #define HDSPM_SelSyncRef0 (1<<8)        /* AutoSync Source */
410 #define HDSPM_SelSyncRef1 (1<<9)        /* 000=word, 001=MADI, */
411 #define HDSPM_SelSyncRef2 (1<<10)       /* 111=no valid signal */
412 
413 #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync)
414 
415 #define HDSPM_wcFreqMask  (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2|\
416                             HDSPM_wc_freq3)
417 #define HDSPM_wcFreq32    (HDSPM_wc_freq0)
418 #define HDSPM_wcFreq44_1  (HDSPM_wc_freq1)
419 #define HDSPM_wcFreq48    (HDSPM_wc_freq0|HDSPM_wc_freq1)
420 #define HDSPM_wcFreq64    (HDSPM_wc_freq2)
421 #define HDSPM_wcFreq88_2  (HDSPM_wc_freq0|HDSPM_wc_freq2)
422 #define HDSPM_wcFreq96    (HDSPM_wc_freq1|HDSPM_wc_freq2)
423 #define HDSPM_wcFreq128   (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2)
424 #define HDSPM_wcFreq176_4 (HDSPM_wc_freq3)
425 #define HDSPM_wcFreq192   (HDSPM_wc_freq0|HDSPM_wc_freq3)
426 
427 #define HDSPM_status1_F_0 0x0400000
428 #define HDSPM_status1_F_1 0x0800000
429 #define HDSPM_status1_F_2 0x1000000
430 #define HDSPM_status1_F_3 0x2000000
431 #define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3)
432 
433 
434 #define HDSPM_SelSyncRefMask       (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
435                                     HDSPM_SelSyncRef2)
436 #define HDSPM_SelSyncRef_WORD      0
437 #define HDSPM_SelSyncRef_MADI      (HDSPM_SelSyncRef0)
438 #define HDSPM_SelSyncRef_TCO       (HDSPM_SelSyncRef1)
439 #define HDSPM_SelSyncRef_SyncIn    (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1)
440 #define HDSPM_SelSyncRef_NVALID    (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
441                                     HDSPM_SelSyncRef2)
442 
443 /*
444    For AES32, bits for status, status2 and timecode are different
445 */
446 /* status */
447 #define HDSPM_AES32_wcLock      0x0200000
448 #define HDSPM_AES32_wcSync      0x0100000
449 #define HDSPM_AES32_wcFreq_bit  22
450 /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function
451   HDSPM_bit2freq */
452 #define HDSPM_AES32_syncref_bit  16
453 /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */
454 
455 #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0
456 #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1
457 #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2
458 #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3
459 #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4
460 #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5
461 #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6
462 #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7
463 #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8
464 #define HDSPM_AES32_AUTOSYNC_FROM_NONE 9
465 
466 /*  status2 */
467 /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */
468 #define HDSPM_LockAES   0x80
469 #define HDSPM_LockAES1  0x80
470 #define HDSPM_LockAES2  0x40
471 #define HDSPM_LockAES3  0x20
472 #define HDSPM_LockAES4  0x10
473 #define HDSPM_LockAES5  0x8
474 #define HDSPM_LockAES6  0x4
475 #define HDSPM_LockAES7  0x2
476 #define HDSPM_LockAES8  0x1
477 /*
478    Timecode
479    After windows driver sources, bits 4*i to 4*i+3 give the input frequency on
480    AES i+1
481  bits 3210
482       0001  32kHz
483       0010  44.1kHz
484       0011  48kHz
485       0100  64kHz
486       0101  88.2kHz
487       0110  96kHz
488       0111  128kHz
489       1000  176.4kHz
490       1001  192kHz
491   NB: Timecode register doesn't seem to work on AES32 card revision 230
492 */
493 
494 /* Mixer Values */
495 #define UNITY_GAIN          32768       /* = 65536/2 */
496 #define MINUS_INFINITY_GAIN 0
497 
498 /* Number of channels for different Speed Modes */
499 #define MADI_SS_CHANNELS       64
500 #define MADI_DS_CHANNELS       32
501 #define MADI_QS_CHANNELS       16
502 
503 #define RAYDAT_SS_CHANNELS     36
504 #define RAYDAT_DS_CHANNELS     20
505 #define RAYDAT_QS_CHANNELS     12
506 
507 #define AIO_IN_SS_CHANNELS        14
508 #define AIO_IN_DS_CHANNELS        10
509 #define AIO_IN_QS_CHANNELS        8
510 #define AIO_OUT_SS_CHANNELS        16
511 #define AIO_OUT_DS_CHANNELS        12
512 #define AIO_OUT_QS_CHANNELS        10
513 
514 #define AES32_CHANNELS          16
515 
516 /* the size of a substream (1 mono data stream) */
517 #define HDSPM_CHANNEL_BUFFER_SAMPLES  (16*1024)
518 #define HDSPM_CHANNEL_BUFFER_BYTES    (4*HDSPM_CHANNEL_BUFFER_SAMPLES)
519 
520 /* the size of the area we need to allocate for DMA transfers. the
521    size is the same regardless of the number of channels, and
522    also the latency to use.
523    for one direction !!!
524 */
525 #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES)
526 #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024)
527 
528 #define HDSPM_RAYDAT_REV        211
529 #define HDSPM_AIO_REV           212
530 #define HDSPM_MADIFACE_REV      213
531 
532 /* speed factor modes */
533 #define HDSPM_SPEED_SINGLE 0
534 #define HDSPM_SPEED_DOUBLE 1
535 #define HDSPM_SPEED_QUAD   2
536 
537 /* names for speed modes */
538 static char *hdspm_speed_names[] = { "single", "double", "quad" };
539 
540 static char *texts_autosync_aes_tco[] = { "Word Clock",
541                                           "AES1", "AES2", "AES3", "AES4",
542                                           "AES5", "AES6", "AES7", "AES8",
543                                           "TCO" };
544 static char *texts_autosync_aes[] = { "Word Clock",
545                                       "AES1", "AES2", "AES3", "AES4",
546                                       "AES5", "AES6", "AES7", "AES8" };
547 static char *texts_autosync_madi_tco[] = { "Word Clock",
548                                            "MADI", "TCO", "Sync In" };
549 static char *texts_autosync_madi[] = { "Word Clock",
550                                        "MADI", "Sync In" };
551 
552 static char *texts_autosync_raydat_tco[] = {
553         "Word Clock",
554         "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
555         "AES", "SPDIF", "TCO", "Sync In"
556 };
557 static char *texts_autosync_raydat[] = {
558         "Word Clock",
559         "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
560         "AES", "SPDIF", "Sync In"
561 };
562 static char *texts_autosync_aio_tco[] = {
563         "Word Clock",
564         "ADAT", "AES", "SPDIF", "TCO", "Sync In"
565 };
566 static char *texts_autosync_aio[] = { "Word Clock",
567                                       "ADAT", "AES", "SPDIF", "Sync In" };
568 
569 static char *texts_freq[] = {
570         "No Lock",
571         "32 kHz",
572         "44.1 kHz",
573         "48 kHz",
574         "64 kHz",
575         "88.2 kHz",
576         "96 kHz",
577         "128 kHz",
578         "176.4 kHz",
579         "192 kHz"
580 };
581 
582 static char *texts_ports_madi[] = {
583         "MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6",
584         "MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12",
585         "MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18",
586         "MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24",
587         "MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30",
588         "MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36",
589         "MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42",
590         "MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48",
591         "MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54",
592         "MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60",
593         "MADI.61", "MADI.62", "MADI.63", "MADI.64",
594 };
595 
596 
597 static char *texts_ports_raydat_ss[] = {
598         "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6",
599         "ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
600         "ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2",
601         "ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8",
602         "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6",
603         "ADAT4.7", "ADAT4.8",
604         "AES.L", "AES.R",
605         "SPDIF.L", "SPDIF.R"
606 };
607 
608 static char *texts_ports_raydat_ds[] = {
609         "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4",
610         "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
611         "ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4",
612         "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4",
613         "AES.L", "AES.R",
614         "SPDIF.L", "SPDIF.R"
615 };
616 
617 static char *texts_ports_raydat_qs[] = {
618         "ADAT1.1", "ADAT1.2",
619         "ADAT2.1", "ADAT2.2",
620         "ADAT3.1", "ADAT3.2",
621         "ADAT4.1", "ADAT4.2",
622         "AES.L", "AES.R",
623         "SPDIF.L", "SPDIF.R"
624 };
625 
626 
627 static char *texts_ports_aio_in_ss[] = {
628         "Analogue.L", "Analogue.R",
629         "AES.L", "AES.R",
630         "SPDIF.L", "SPDIF.R",
631         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
632         "ADAT.7", "ADAT.8"
633 };
634 
635 static char *texts_ports_aio_out_ss[] = {
636         "Analogue.L", "Analogue.R",
637         "AES.L", "AES.R",
638         "SPDIF.L", "SPDIF.R",
639         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
640         "ADAT.7", "ADAT.8",
641         "Phone.L", "Phone.R"
642 };
643 
644 static char *texts_ports_aio_in_ds[] = {
645         "Analogue.L", "Analogue.R",
646         "AES.L", "AES.R",
647         "SPDIF.L", "SPDIF.R",
648         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4"
649 };
650 
651 static char *texts_ports_aio_out_ds[] = {
652         "Analogue.L", "Analogue.R",
653         "AES.L", "AES.R",
654         "SPDIF.L", "SPDIF.R",
655         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
656         "Phone.L", "Phone.R"
657 };
658 
659 static char *texts_ports_aio_in_qs[] = {
660         "Analogue.L", "Analogue.R",
661         "AES.L", "AES.R",
662         "SPDIF.L", "SPDIF.R",
663         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4"
664 };
665 
666 static char *texts_ports_aio_out_qs[] = {
667         "Analogue.L", "Analogue.R",
668         "AES.L", "AES.R",
669         "SPDIF.L", "SPDIF.R",
670         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
671         "Phone.L", "Phone.R"
672 };
673 
674 static char *texts_ports_aes32[] = {
675         "AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7",
676         "AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14",
677         "AES.15", "AES.16"
678 };
679 
680 /* These tables map the ALSA channels 1..N to the channels that we
681    need to use in order to find the relevant channel buffer. RME
682    refers to this kind of mapping as between "the ADAT channel and
683    the DMA channel." We index it using the logical audio channel,
684    and the value is the DMA channel (i.e. channel buffer number)
685    where the data for that channel can be read/written from/to.
686 */
687 
688 static char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = {
689         0, 1, 2, 3, 4, 5, 6, 7,
690         8, 9, 10, 11, 12, 13, 14, 15,
691         16, 17, 18, 19, 20, 21, 22, 23,
692         24, 25, 26, 27, 28, 29, 30, 31,
693         32, 33, 34, 35, 36, 37, 38, 39,
694         40, 41, 42, 43, 44, 45, 46, 47,
695         48, 49, 50, 51, 52, 53, 54, 55,
696         56, 57, 58, 59, 60, 61, 62, 63
697 };
698 
699 static char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = {
700         4, 5, 6, 7, 8, 9, 10, 11,       /* ADAT 1 */
701         12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */
702         20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */
703         28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */
704         0, 1,                   /* AES */
705         2, 3,                   /* SPDIF */
706         -1, -1, -1, -1,
707         -1, -1, -1, -1, -1, -1, -1, -1,
708         -1, -1, -1, -1, -1, -1, -1, -1,
709         -1, -1, -1, -1, -1, -1, -1, -1,
710 };
711 
712 static char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = {
713         4, 5, 6, 7,             /* ADAT 1 */
714         8, 9, 10, 11,           /* ADAT 2 */
715         12, 13, 14, 15,         /* ADAT 3 */
716         16, 17, 18, 19,         /* ADAT 4 */
717         0, 1,                   /* AES */
718         2, 3,                   /* SPDIF */
719         -1, -1, -1, -1,
720         -1, -1, -1, -1, -1, -1, -1, -1,
721         -1, -1, -1, -1, -1, -1, -1, -1,
722         -1, -1, -1, -1, -1, -1, -1, -1,
723         -1, -1, -1, -1, -1, -1, -1, -1,
724         -1, -1, -1, -1, -1, -1, -1, -1,
725 };
726 
727 static char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = {
728         4, 5,                   /* ADAT 1 */
729         6, 7,                   /* ADAT 2 */
730         8, 9,                   /* ADAT 3 */
731         10, 11,                 /* ADAT 4 */
732         0, 1,                   /* AES */
733         2, 3,                   /* SPDIF */
734         -1, -1, -1, -1,
735         -1, -1, -1, -1, -1, -1, -1, -1,
736         -1, -1, -1, -1, -1, -1, -1, -1,
737         -1, -1, -1, -1, -1, -1, -1, -1,
738         -1, -1, -1, -1, -1, -1, -1, -1,
739         -1, -1, -1, -1, -1, -1, -1, -1,
740         -1, -1, -1, -1, -1, -1, -1, -1,
741 };
742 
743 static char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = {
744         0, 1,                   /* line in */
745         8, 9,                   /* aes in, */
746         10, 11,                 /* spdif in */
747         12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */
748         -1, -1,
749         -1, -1, -1, -1, -1, -1, -1, -1,
750         -1, -1, -1, -1, -1, -1, -1, -1,
751         -1, -1, -1, -1, -1, -1, -1, -1,
752         -1, -1, -1, -1, -1, -1, -1, -1,
753         -1, -1, -1, -1, -1, -1, -1, -1,
754         -1, -1, -1, -1, -1, -1, -1, -1,
755 };
756 
757 static char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = {
758         0, 1,                   /* line out */
759         8, 9,                   /* aes out */
760         10, 11,                 /* spdif out */
761         12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */
762         6, 7,                   /* phone out */
763         -1, -1, -1, -1, -1, -1, -1, -1,
764         -1, -1, -1, -1, -1, -1, -1, -1,
765         -1, -1, -1, -1, -1, -1, -1, -1,
766         -1, -1, -1, -1, -1, -1, -1, -1,
767         -1, -1, -1, -1, -1, -1, -1, -1,
768         -1, -1, -1, -1, -1, -1, -1, -1,
769 };
770 
771 static char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = {
772         0, 1,                   /* line in */
773         8, 9,                   /* aes in */
774         10, 11,                 /* spdif in */
775         12, 14, 16, 18,         /* adat in */
776         -1, -1, -1, -1, -1, -1,
777         -1, -1, -1, -1, -1, -1, -1, -1,
778         -1, -1, -1, -1, -1, -1, -1, -1,
779         -1, -1, -1, -1, -1, -1, -1, -1,
780         -1, -1, -1, -1, -1, -1, -1, -1,
781         -1, -1, -1, -1, -1, -1, -1, -1,
782         -1, -1, -1, -1, -1, -1, -1, -1
783 };
784 
785 static char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = {
786         0, 1,                   /* line out */
787         8, 9,                   /* aes out */
788         10, 11,                 /* spdif out */
789         12, 14, 16, 18,         /* adat out */
790         6, 7,                   /* phone out */
791         -1, -1, -1, -1,
792         -1, -1, -1, -1, -1, -1, -1, -1,
793         -1, -1, -1, -1, -1, -1, -1, -1,
794         -1, -1, -1, -1, -1, -1, -1, -1,
795         -1, -1, -1, -1, -1, -1, -1, -1,
796         -1, -1, -1, -1, -1, -1, -1, -1,
797         -1, -1, -1, -1, -1, -1, -1, -1
798 };
799 
800 static char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = {
801         0, 1,                   /* line in */
802         8, 9,                   /* aes in */
803         10, 11,                 /* spdif in */
804         12, 16,                 /* adat in */
805         -1, -1, -1, -1, -1, -1, -1, -1,
806         -1, -1, -1, -1, -1, -1, -1, -1,
807         -1, -1, -1, -1, -1, -1, -1, -1,
808         -1, -1, -1, -1, -1, -1, -1, -1,
809         -1, -1, -1, -1, -1, -1, -1, -1,
810         -1, -1, -1, -1, -1, -1, -1, -1,
811         -1, -1, -1, -1, -1, -1, -1, -1
812 };
813 
814 static char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = {
815         0, 1,                   /* line out */
816         8, 9,                   /* aes out */
817         10, 11,                 /* spdif out */
818         12, 16,                 /* adat out */
819         6, 7,                   /* phone out */
820         -1, -1, -1, -1, -1, -1,
821         -1, -1, -1, -1, -1, -1, -1, -1,
822         -1, -1, -1, -1, -1, -1, -1, -1,
823         -1, -1, -1, -1, -1, -1, -1, -1,
824         -1, -1, -1, -1, -1, -1, -1, -1,
825         -1, -1, -1, -1, -1, -1, -1, -1,
826         -1, -1, -1, -1, -1, -1, -1, -1
827 };
828 
829 static char channel_map_aes32[HDSPM_MAX_CHANNELS] = {
830         0, 1, 2, 3, 4, 5, 6, 7,
831         8, 9, 10, 11, 12, 13, 14, 15,
832         -1, -1, -1, -1, -1, -1, -1, -1,
833         -1, -1, -1, -1, -1, -1, -1, -1,
834         -1, -1, -1, -1, -1, -1, -1, -1,
835         -1, -1, -1, -1, -1, -1, -1, -1,
836         -1, -1, -1, -1, -1, -1, -1, -1,
837         -1, -1, -1, -1, -1, -1, -1, -1
838 };
839 
840 struct hdspm_midi {
841         struct hdspm *hdspm;
842         int id;
843         struct snd_rawmidi *rmidi;
844         struct snd_rawmidi_substream *input;
845         struct snd_rawmidi_substream *output;
846         char istimer;           /* timer in use */
847         struct timer_list timer;
848         spinlock_t lock;
849         int pending;
850         int dataIn;
851         int statusIn;
852         int dataOut;
853         int statusOut;
854         int ie;
855         int irq;
856 };
857 
858 struct hdspm_tco {
859         int input;
860         int framerate;
861         int wordclock;
862         int samplerate;
863         int pull;
864         int term; /* 0 = off, 1 = on */
865 };
866 
867 struct hdspm {
868         spinlock_t lock;
869         /* only one playback and/or capture stream */
870         struct snd_pcm_substream *capture_substream;
871         struct snd_pcm_substream *playback_substream;
872 
873         char *card_name;             /* for procinfo */
874         unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/
875 
876         uint8_t io_type;
877 
878         int monitor_outs;       /* set up monitoring outs init flag */
879 
880         u32 control_register;   /* cached value */
881         u32 control2_register;  /* cached value */
882         u32 settings_register;
883 
884         struct hdspm_midi midi[4];
885         struct tasklet_struct midi_tasklet;
886 
887         size_t period_bytes;
888         unsigned char ss_in_channels;
889         unsigned char ds_in_channels;
890         unsigned char qs_in_channels;
891         unsigned char ss_out_channels;
892         unsigned char ds_out_channels;
893         unsigned char qs_out_channels;
894 
895         unsigned char max_channels_in;
896         unsigned char max_channels_out;
897 
898         signed char *channel_map_in;
899         signed char *channel_map_out;
900 
901         signed char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs;
902         signed char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs;
903 
904         char **port_names_in;
905         char **port_names_out;
906 
907         char **port_names_in_ss, **port_names_in_ds, **port_names_in_qs;
908         char **port_names_out_ss, **port_names_out_ds, **port_names_out_qs;
909 
910         unsigned char *playback_buffer; /* suitably aligned address */
911         unsigned char *capture_buffer;  /* suitably aligned address */
912 
913         pid_t capture_pid;      /* process id which uses capture */
914         pid_t playback_pid;     /* process id which uses capture */
915         int running;            /* running status */
916 
917         int last_external_sample_rate;  /* samplerate mystic ... */
918         int last_internal_sample_rate;
919         int system_sample_rate;
920 
921         int dev;                /* Hardware vars... */
922         int irq;
923         unsigned long port;
924         void __iomem *iobase;
925 
926         int irq_count;          /* for debug */
927         int midiPorts;
928 
929         struct snd_card *card;  /* one card */
930         struct snd_pcm *pcm;            /* has one pcm */
931         struct snd_hwdep *hwdep;        /* and a hwdep for additional ioctl */
932         struct pci_dev *pci;    /* and an pci info */
933 
934         /* Mixer vars */
935         /* fast alsa mixer */
936         struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS];
937         /* but input to much, so not used */
938         struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS];
939         /* full mixer accessible over mixer ioctl or hwdep-device */
940         struct hdspm_mixer *mixer;
941 
942         struct hdspm_tco *tco;  /* NULL if no TCO detected */
943 
944         char **texts_autosync;
945         int texts_autosync_items;
946 
947         cycles_t last_interrupt;
948 
949         unsigned int serial;
950 
951         struct hdspm_peak_rms peak_rms;
952 };
953 
954 
955 static DEFINE_PCI_DEVICE_TABLE(snd_hdspm_ids) = {
956         {
957          .vendor = PCI_VENDOR_ID_XILINX,
958          .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI,
959          .subvendor = PCI_ANY_ID,
960          .subdevice = PCI_ANY_ID,
961          .class = 0,
962          .class_mask = 0,
963          .driver_data = 0},
964         {0,}
965 };
966 
967 MODULE_DEVICE_TABLE(pci, snd_hdspm_ids);
968 
969 /* prototypes */
970 static int snd_hdspm_create_alsa_devices(struct snd_card *card,
971                                          struct hdspm *hdspm);
972 static int snd_hdspm_create_pcm(struct snd_card *card,
973                                 struct hdspm *hdspm);
974 
975 static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm);
976 static inline int hdspm_get_pll_freq(struct hdspm *hdspm);
977 static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm);
978 static int hdspm_autosync_ref(struct hdspm *hdspm);
979 static int snd_hdspm_set_defaults(struct hdspm *hdspm);
980 static int hdspm_system_clock_mode(struct hdspm *hdspm);
981 static void hdspm_set_sgbuf(struct hdspm *hdspm,
982                             struct snd_pcm_substream *substream,
983                              unsigned int reg, int channels);
984 
985 static inline int HDSPM_bit2freq(int n)
986 {
987         static const int bit2freq_tab[] = {
988                 0, 32000, 44100, 48000, 64000, 88200,
989                 96000, 128000, 176400, 192000 };
990         if (n < 1 || n > 9)
991                 return 0;
992         return bit2freq_tab[n];
993 }
994 
995 /* Write/read to/from HDSPM with Adresses in Bytes
996    not words but only 32Bit writes are allowed */
997 
998 static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg,
999                                unsigned int val)
1000 {
1001         writel(val, hdspm->iobase + reg);
1002 }
1003 
1004 static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg)
1005 {
1006         return readl(hdspm->iobase + reg);
1007 }
1008 
1009 /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader
1010    mixer is write only on hardware so we have to cache him for read
1011    each fader is a u32, but uses only the first 16 bit */
1012 
1013 static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan,
1014                                      unsigned int in)
1015 {
1016         if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1017                 return 0;
1018 
1019         return hdspm->mixer->ch[chan].in[in];
1020 }
1021 
1022 static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan,
1023                                      unsigned int pb)
1024 {
1025         if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1026                 return 0;
1027         return hdspm->mixer->ch[chan].pb[pb];
1028 }
1029 
1030 static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan,
1031                                       unsigned int in, unsigned short data)
1032 {
1033         if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1034                 return -1;
1035 
1036         hdspm_write(hdspm,
1037                     HDSPM_MADI_mixerBase +
1038                     ((in + 128 * chan) * sizeof(u32)),
1039                     (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF));
1040         return 0;
1041 }
1042 
1043 static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan,
1044                                       unsigned int pb, unsigned short data)
1045 {
1046         if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1047                 return -1;
1048 
1049         hdspm_write(hdspm,
1050                     HDSPM_MADI_mixerBase +
1051                     ((64 + pb + 128 * chan) * sizeof(u32)),
1052                     (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF));
1053         return 0;
1054 }
1055 
1056 
1057 /* enable DMA for specific channels, now available for DSP-MADI */
1058 static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v)
1059 {
1060         hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v);
1061 }
1062 
1063 static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v)
1064 {
1065         hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v);
1066 }
1067 
1068 /* check if same process is writing and reading */
1069 static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm)
1070 {
1071         unsigned long flags;
1072         int ret = 1;
1073 
1074         spin_lock_irqsave(&hdspm->lock, flags);
1075         if ((hdspm->playback_pid != hdspm->capture_pid) &&
1076             (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) {
1077                 ret = 0;
1078         }
1079         spin_unlock_irqrestore(&hdspm->lock, flags);
1080         return ret;
1081 }
1082 
1083 /* round arbitary sample rates to commonly known rates */
1084 static int hdspm_round_frequency(int rate)
1085 {
1086         if (rate < 38050)
1087                 return 32000;
1088         if (rate < 46008)
1089                 return 44100;
1090         else
1091                 return 48000;
1092 }
1093 
1094 /* QS and DS rates normally can not be detected
1095  * automatically by the card. Only exception is MADI
1096  * in 96k frame mode.
1097  *
1098  * So if we read SS values (32 .. 48k), check for
1099  * user-provided DS/QS bits in the control register
1100  * and multiply the base frequency accordingly.
1101  */
1102 static int hdspm_rate_multiplier(struct hdspm *hdspm, int rate)
1103 {
1104         if (rate <= 48000) {
1105                 if (hdspm->control_register & HDSPM_QuadSpeed)
1106                         return rate * 4;
1107                 else if (hdspm->control_register &
1108                                 HDSPM_DoubleSpeed)
1109                         return rate * 2;
1110         };
1111         return rate;
1112 }
1113 
1114 static int hdspm_tco_sync_check(struct hdspm *hdspm);
1115 static int hdspm_sync_in_sync_check(struct hdspm *hdspm);
1116 
1117 /* check for external sample rate */
1118 static int hdspm_external_sample_rate(struct hdspm *hdspm)
1119 {
1120         unsigned int status, status2, timecode;
1121         int syncref, rate = 0, rate_bits;
1122 
1123         switch (hdspm->io_type) {
1124         case AES32:
1125                 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1126                 status = hdspm_read(hdspm, HDSPM_statusRegister);
1127                 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
1128 
1129                 syncref = hdspm_autosync_ref(hdspm);
1130 
1131                 if (syncref == HDSPM_AES32_AUTOSYNC_FROM_WORD &&
1132                                 status & HDSPM_AES32_wcLock)
1133                         return HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF);
1134 
1135                 if (syncref >= HDSPM_AES32_AUTOSYNC_FROM_AES1 &&
1136                                 syncref <= HDSPM_AES32_AUTOSYNC_FROM_AES8 &&
1137                                 status2 & (HDSPM_LockAES >>
1138                                 (syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1)))
1139                         return HDSPM_bit2freq((timecode >> (4*(syncref-HDSPM_AES32_AUTOSYNC_FROM_AES1))) & 0xF);
1140                 return 0;
1141                 break;
1142 
1143         case MADIface:
1144                 status = hdspm_read(hdspm, HDSPM_statusRegister);
1145 
1146                 if (!(status & HDSPM_madiLock)) {
1147                         rate = 0;  /* no lock */
1148                 } else {
1149                         switch (status & (HDSPM_status1_freqMask)) {
1150                         case HDSPM_status1_F_0*1:
1151                                 rate = 32000; break;
1152                         case HDSPM_status1_F_0*2:
1153                                 rate = 44100; break;
1154                         case HDSPM_status1_F_0*3:
1155                                 rate = 48000; break;
1156                         case HDSPM_status1_F_0*4:
1157                                 rate = 64000; break;
1158                         case HDSPM_status1_F_0*5:
1159                                 rate = 88200; break;
1160                         case HDSPM_status1_F_0*6:
1161                                 rate = 96000; break;
1162                         case HDSPM_status1_F_0*7:
1163                                 rate = 128000; break;
1164                         case HDSPM_status1_F_0*8:
1165                                 rate = 176400; break;
1166                         case HDSPM_status1_F_0*9:
1167                                 rate = 192000; break;
1168                         default:
1169                                 rate = 0; break;
1170                         }
1171                 }
1172 
1173                 break;
1174 
1175         case MADI:
1176         case AIO:
1177         case RayDAT:
1178                 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1179                 status = hdspm_read(hdspm, HDSPM_statusRegister);
1180                 rate = 0;
1181 
1182                 /* if wordclock has synced freq and wordclock is valid */
1183                 if ((status2 & HDSPM_wcLock) != 0 &&
1184                                 (status2 & HDSPM_SelSyncRef0) == 0) {
1185 
1186                         rate_bits = status2 & HDSPM_wcFreqMask;
1187 
1188 
1189                         switch (rate_bits) {
1190                         case HDSPM_wcFreq32:
1191                                 rate = 32000;
1192                                 break;
1193                         case HDSPM_wcFreq44_1:
1194                                 rate = 44100;
1195                                 break;
1196                         case HDSPM_wcFreq48:
1197                                 rate = 48000;
1198                                 break;
1199                         case HDSPM_wcFreq64:
1200                                 rate = 64000;
1201                                 break;
1202                         case HDSPM_wcFreq88_2:
1203                                 rate = 88200;
1204                                 break;
1205                         case HDSPM_wcFreq96:
1206                                 rate = 96000;
1207                                 break;
1208                         case HDSPM_wcFreq128:
1209                                 rate = 128000;
1210                                 break;
1211                         case HDSPM_wcFreq176_4:
1212                                 rate = 176400;
1213                                 break;
1214                         case HDSPM_wcFreq192:
1215                                 rate = 192000;
1216                                 break;
1217                         default:
1218                                 rate = 0;
1219                                 break;
1220                         }
1221                 }
1222 
1223                 /* if rate detected and Syncref is Word than have it,
1224                  * word has priority to MADI
1225                  */
1226                 if (rate != 0 &&
1227                 (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD)
1228                         return hdspm_rate_multiplier(hdspm, rate);
1229 
1230                 /* maybe a madi input (which is taken if sel sync is madi) */
1231                 if (status & HDSPM_madiLock) {
1232                         rate_bits = status & HDSPM_madiFreqMask;
1233 
1234                         switch (rate_bits) {
1235                         case HDSPM_madiFreq32:
1236                                 rate = 32000;
1237                                 break;
1238                         case HDSPM_madiFreq44_1:
1239                                 rate = 44100;
1240                                 break;
1241                         case HDSPM_madiFreq48:
1242                                 rate = 48000;
1243                                 break;
1244                         case HDSPM_madiFreq64:
1245                                 rate = 64000;
1246                                 break;
1247                         case HDSPM_madiFreq88_2:
1248                                 rate = 88200;
1249                                 break;
1250                         case HDSPM_madiFreq96:
1251                                 rate = 96000;
1252                                 break;
1253                         case HDSPM_madiFreq128:
1254                                 rate = 128000;
1255                                 break;
1256                         case HDSPM_madiFreq176_4:
1257                                 rate = 176400;
1258                                 break;
1259                         case HDSPM_madiFreq192:
1260                                 rate = 192000;
1261                                 break;
1262                         default:
1263                                 rate = 0;
1264                                 break;
1265                         }
1266 
1267                 } /* endif HDSPM_madiLock */
1268 
1269                 /* check sample rate from TCO or SYNC_IN */
1270                 {
1271                         bool is_valid_input = 0;
1272                         bool has_sync = 0;
1273 
1274                         syncref = hdspm_autosync_ref(hdspm);
1275                         if (HDSPM_AUTOSYNC_FROM_TCO == syncref) {
1276                                 is_valid_input = 1;
1277                                 has_sync = (HDSPM_SYNC_CHECK_SYNC ==
1278                                         hdspm_tco_sync_check(hdspm));
1279                         } else if (HDSPM_AUTOSYNC_FROM_SYNC_IN == syncref) {
1280                                 is_valid_input = 1;
1281                                 has_sync = (HDSPM_SYNC_CHECK_SYNC ==
1282                                         hdspm_sync_in_sync_check(hdspm));
1283                         }
1284 
1285                         if (is_valid_input && has_sync) {
1286                                 rate = hdspm_round_frequency(
1287                                         hdspm_get_pll_freq(hdspm));
1288                         }
1289                 }
1290 
1291                 rate = hdspm_rate_multiplier(hdspm, rate);
1292 
1293                 break;
1294         }
1295 
1296         return rate;
1297 }
1298 
1299 /* return latency in samples per period */
1300 static int hdspm_get_latency(struct hdspm *hdspm)
1301 {
1302         int n;
1303 
1304         n = hdspm_decode_latency(hdspm->control_register);
1305 
1306         /* Special case for new RME cards with 32 samples period size.
1307          * The three latency bits in the control register
1308          * (HDSP_LatencyMask) encode latency values of 64 samples as
1309          * 0, 128 samples as 1 ... 4096 samples as 6. For old cards, 7
1310          * denotes 8192 samples, but on new cards like RayDAT or AIO,
1311          * it corresponds to 32 samples.
1312          */
1313         if ((7 == n) && (RayDAT == hdspm->io_type || AIO == hdspm->io_type))
1314                 n = -1;
1315 
1316         return 1 << (n + 6);
1317 }
1318 
1319 /* Latency function */
1320 static inline void hdspm_compute_period_size(struct hdspm *hdspm)
1321 {
1322         hdspm->period_bytes = 4 * hdspm_get_latency(hdspm);
1323 }
1324 
1325 
1326 static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm)
1327 {
1328         int position;
1329 
1330         position = hdspm_read(hdspm, HDSPM_statusRegister);
1331 
1332         switch (hdspm->io_type) {
1333         case RayDAT:
1334         case AIO:
1335                 position &= HDSPM_BufferPositionMask;
1336                 position /= 4; /* Bytes per sample */
1337                 break;
1338         default:
1339                 position = (position & HDSPM_BufferID) ?
1340                         (hdspm->period_bytes / 4) : 0;
1341         }
1342 
1343         return position;
1344 }
1345 
1346 
1347 static inline void hdspm_start_audio(struct hdspm * s)
1348 {
1349         s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start);
1350         hdspm_write(s, HDSPM_controlRegister, s->control_register);
1351 }
1352 
1353 static inline void hdspm_stop_audio(struct hdspm * s)
1354 {
1355         s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable);
1356         hdspm_write(s, HDSPM_controlRegister, s->control_register);
1357 }
1358 
1359 /* should I silence all or only opened ones ? doit all for first even is 4MB*/
1360 static void hdspm_silence_playback(struct hdspm *hdspm)
1361 {
1362         int i;
1363         int n = hdspm->period_bytes;
1364         void *buf = hdspm->playback_buffer;
1365 
1366         if (buf == NULL)
1367                 return;
1368 
1369         for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
1370                 memset(buf, 0, n);
1371                 buf += HDSPM_CHANNEL_BUFFER_BYTES;
1372         }
1373 }
1374 
1375 static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames)
1376 {
1377         int n;
1378 
1379         spin_lock_irq(&s->lock);
1380 
1381         if (32 == frames) {
1382                 /* Special case for new RME cards like RayDAT/AIO which
1383                  * support period sizes of 32 samples. Since latency is
1384                  * encoded in the three bits of HDSP_LatencyMask, we can only
1385                  * have values from 0 .. 7. While 0 still means 64 samples and
1386                  * 6 represents 4096 samples on all cards, 7 represents 8192
1387                  * on older cards and 32 samples on new cards.
1388                  *
1389                  * In other words, period size in samples is calculated by
1390                  * 2^(n+6) with n ranging from 0 .. 7.
1391                  */
1392                 n = 7;
1393         } else {
1394                 frames >>= 7;
1395                 n = 0;
1396                 while (frames) {
1397                         n++;
1398                         frames >>= 1;
1399                 }
1400         }
1401 
1402         s->control_register &= ~HDSPM_LatencyMask;
1403         s->control_register |= hdspm_encode_latency(n);
1404 
1405         hdspm_write(s, HDSPM_controlRegister, s->control_register);
1406 
1407         hdspm_compute_period_size(s);
1408 
1409         spin_unlock_irq(&s->lock);
1410 
1411         return 0;
1412 }
1413 
1414 static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period)
1415 {
1416         u64 freq_const;
1417 
1418         if (period == 0)
1419                 return 0;
1420 
1421         switch (hdspm->io_type) {
1422         case MADI:
1423         case AES32:
1424                 freq_const = 110069313433624ULL;
1425                 break;
1426         case RayDAT:
1427         case AIO:
1428                 freq_const = 104857600000000ULL;
1429                 break;
1430         case MADIface:
1431                 freq_const = 131072000000000ULL;
1432                 break;
1433         default:
1434                 snd_BUG();
1435                 return 0;
1436         }
1437 
1438         return div_u64(freq_const, period);
1439 }
1440 
1441 
1442 static void hdspm_set_dds_value(struct hdspm *hdspm, int rate)
1443 {
1444         u64 n;
1445 
1446         if (rate >= 112000)
1447                 rate /= 4;
1448         else if (rate >= 56000)
1449                 rate /= 2;
1450 
1451         switch (hdspm->io_type) {
1452         case MADIface:
1453                 n = 131072000000000ULL;  /* 125 MHz */
1454                 break;
1455         case MADI:
1456         case AES32:
1457                 n = 110069313433624ULL;  /* 105 MHz */
1458                 break;
1459         case RayDAT:
1460         case AIO:
1461                 n = 104857600000000ULL;  /* 100 MHz */
1462                 break;
1463         default:
1464                 snd_BUG();
1465                 return;
1466         }
1467 
1468         n = div_u64(n, rate);
1469         /* n should be less than 2^32 for being written to FREQ register */
1470         snd_BUG_ON(n >> 32);
1471         hdspm_write(hdspm, HDSPM_freqReg, (u32)n);
1472 }
1473 
1474 /* dummy set rate lets see what happens */
1475 static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally)
1476 {
1477         int current_rate;
1478         int rate_bits;
1479         int not_set = 0;
1480         int current_speed, target_speed;
1481 
1482         /* ASSUMPTION: hdspm->lock is either set, or there is no need for
1483            it (e.g. during module initialization).
1484          */
1485 
1486         if (!(hdspm->control_register & HDSPM_ClockModeMaster)) {
1487 
1488                 /* SLAVE --- */
1489                 if (called_internally) {
1490 
1491                         /* request from ctl or card initialization
1492                            just make a warning an remember setting
1493                            for future master mode switching */
1494 
1495                         snd_printk(KERN_WARNING "HDSPM: "
1496                                    "Warning: device is not running "
1497                                    "as a clock master.\n");
1498                         not_set = 1;
1499                 } else {
1500 
1501                         /* hw_param request while in AutoSync mode */
1502                         int external_freq =
1503                             hdspm_external_sample_rate(hdspm);
1504 
1505                         if (hdspm_autosync_ref(hdspm) ==
1506                             HDSPM_AUTOSYNC_FROM_NONE) {
1507 
1508                                 snd_printk(KERN_WARNING "HDSPM: "
1509                                            "Detected no Externel Sync \n");
1510                                 not_set = 1;
1511 
1512                         } else if (rate != external_freq) {
1513 
1514                                 snd_printk(KERN_WARNING "HDSPM: "
1515                                            "Warning: No AutoSync source for "
1516                                            "requested rate\n");
1517                                 not_set = 1;
1518                         }
1519                 }
1520         }
1521 
1522         current_rate = hdspm->system_sample_rate;
1523 
1524         /* Changing between Singe, Double and Quad speed is not
1525            allowed if any substreams are open. This is because such a change
1526            causes a shift in the location of the DMA buffers and a reduction
1527            in the number of available buffers.
1528 
1529            Note that a similar but essentially insoluble problem exists for
1530            externally-driven rate changes. All we can do is to flag rate
1531            changes in the read/write routines.
1532          */
1533 
1534         if (current_rate <= 48000)
1535                 current_speed = HDSPM_SPEED_SINGLE;
1536         else if (current_rate <= 96000)
1537                 current_speed = HDSPM_SPEED_DOUBLE;
1538         else
1539                 current_speed = HDSPM_SPEED_QUAD;
1540 
1541         if (rate <= 48000)
1542                 target_speed = HDSPM_SPEED_SINGLE;
1543         else if (rate <= 96000)
1544                 target_speed = HDSPM_SPEED_DOUBLE;
1545         else
1546                 target_speed = HDSPM_SPEED_QUAD;
1547 
1548         switch (rate) {
1549         case 32000:
1550                 rate_bits = HDSPM_Frequency32KHz;
1551                 break;
1552         case 44100:
1553                 rate_bits = HDSPM_Frequency44_1KHz;
1554                 break;
1555         case 48000:
1556                 rate_bits = HDSPM_Frequency48KHz;
1557                 break;
1558         case 64000:
1559                 rate_bits = HDSPM_Frequency64KHz;
1560                 break;
1561         case 88200:
1562                 rate_bits = HDSPM_Frequency88_2KHz;
1563                 break;
1564         case 96000:
1565                 rate_bits = HDSPM_Frequency96KHz;
1566                 break;
1567         case 128000:
1568                 rate_bits = HDSPM_Frequency128KHz;
1569                 break;
1570         case 176400:
1571                 rate_bits = HDSPM_Frequency176_4KHz;
1572                 break;
1573         case 192000:
1574                 rate_bits = HDSPM_Frequency192KHz;
1575                 break;
1576         default:
1577                 return -EINVAL;
1578         }
1579 
1580         if (current_speed != target_speed
1581             && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) {
1582                 snd_printk
1583                     (KERN_ERR "HDSPM: "
1584                      "cannot change from %s speed to %s speed mode "
1585                      "(capture PID = %d, playback PID = %d)\n",
1586                      hdspm_speed_names[current_speed],
1587                      hdspm_speed_names[target_speed],
1588                      hdspm->capture_pid, hdspm->playback_pid);
1589                 return -EBUSY;
1590         }
1591 
1592         hdspm->control_register &= ~HDSPM_FrequencyMask;
1593         hdspm->control_register |= rate_bits;
1594         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1595 
1596         /* For AES32, need to set DDS value in FREQ register
1597            For MADI, also apparently */
1598         hdspm_set_dds_value(hdspm, rate);
1599 
1600         if (AES32 == hdspm->io_type && rate != current_rate)
1601                 hdspm_write(hdspm, HDSPM_eeprom_wr, 0);
1602 
1603         hdspm->system_sample_rate = rate;
1604 
1605         if (rate <= 48000) {
1606                 hdspm->channel_map_in = hdspm->channel_map_in_ss;
1607                 hdspm->channel_map_out = hdspm->channel_map_out_ss;
1608                 hdspm->max_channels_in = hdspm->ss_in_channels;
1609                 hdspm->max_channels_out = hdspm->ss_out_channels;
1610                 hdspm->port_names_in = hdspm->port_names_in_ss;
1611                 hdspm->port_names_out = hdspm->port_names_out_ss;
1612         } else if (rate <= 96000) {
1613                 hdspm->channel_map_in = hdspm->channel_map_in_ds;
1614                 hdspm->channel_map_out = hdspm->channel_map_out_ds;
1615                 hdspm->max_channels_in = hdspm->ds_in_channels;
1616                 hdspm->max_channels_out = hdspm->ds_out_channels;
1617                 hdspm->port_names_in = hdspm->port_names_in_ds;
1618                 hdspm->port_names_out = hdspm->port_names_out_ds;
1619         } else {
1620                 hdspm->channel_map_in = hdspm->channel_map_in_qs;
1621                 hdspm->channel_map_out = hdspm->channel_map_out_qs;
1622                 hdspm->max_channels_in = hdspm->qs_in_channels;
1623                 hdspm->max_channels_out = hdspm->qs_out_channels;
1624                 hdspm->port_names_in = hdspm->port_names_in_qs;
1625                 hdspm->port_names_out = hdspm->port_names_out_qs;
1626         }
1627 
1628         if (not_set != 0)
1629                 return -1;
1630 
1631         return 0;
1632 }
1633 
1634 /* mainly for init to 0 on load */
1635 static void all_in_all_mixer(struct hdspm * hdspm, int sgain)
1636 {
1637         int i, j;
1638         unsigned int gain;
1639 
1640         if (sgain > UNITY_GAIN)
1641                 gain = UNITY_GAIN;
1642         else if (sgain < 0)
1643                 gain = 0;
1644         else
1645                 gain = sgain;
1646 
1647         for (i = 0; i < HDSPM_MIXER_CHANNELS; i++)
1648                 for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) {
1649                         hdspm_write_in_gain(hdspm, i, j, gain);
1650                         hdspm_write_pb_gain(hdspm, i, j, gain);
1651                 }
1652 }
1653 
1654 /*----------------------------------------------------------------------------
1655    MIDI
1656   ----------------------------------------------------------------------------*/
1657 
1658 static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm,
1659                                                       int id)
1660 {
1661         /* the hardware already does the relevant bit-mask with 0xff */
1662         return hdspm_read(hdspm, hdspm->midi[id].dataIn);
1663 }
1664 
1665 static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id,
1666                                               int val)
1667 {
1668         /* the hardware already does the relevant bit-mask with 0xff */
1669         return hdspm_write(hdspm, hdspm->midi[id].dataOut, val);
1670 }
1671 
1672 static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id)
1673 {
1674         return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF;
1675 }
1676 
1677 static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id)
1678 {
1679         int fifo_bytes_used;
1680 
1681         fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF;
1682 
1683         if (fifo_bytes_used < 128)
1684                 return  128 - fifo_bytes_used;
1685         else
1686                 return 0;
1687 }
1688 
1689 static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id)
1690 {
1691         while (snd_hdspm_midi_input_available (hdspm, id))
1692                 snd_hdspm_midi_read_byte (hdspm, id);
1693 }
1694 
1695 static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi)
1696 {
1697         unsigned long flags;
1698         int n_pending;
1699         int to_write;
1700         int i;
1701         unsigned char buf[128];
1702 
1703         /* Output is not interrupt driven */
1704 
1705         spin_lock_irqsave (&hmidi->lock, flags);
1706         if (hmidi->output &&
1707             !snd_rawmidi_transmit_empty (hmidi->output)) {
1708                 n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm,
1709                                                             hmidi->id);
1710                 if (n_pending > 0) {
1711                         if (n_pending > (int)sizeof (buf))
1712                                 n_pending = sizeof (buf);
1713 
1714                         to_write = snd_rawmidi_transmit (hmidi->output, buf,
1715                                                          n_pending);
1716                         if (to_write > 0) {
1717                                 for (i = 0; i < to_write; ++i)
1718                                         snd_hdspm_midi_write_byte (hmidi->hdspm,
1719                                                                    hmidi->id,
1720                                                                    buf[i]);
1721                         }
1722                 }
1723         }
1724         spin_unlock_irqrestore (&hmidi->lock, flags);
1725         return 0;
1726 }
1727 
1728 static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi)
1729 {
1730         unsigned char buf[128]; /* this buffer is designed to match the MIDI
1731                                  * input FIFO size
1732                                  */
1733         unsigned long flags;
1734         int n_pending;
1735         int i;
1736 
1737         spin_lock_irqsave (&hmidi->lock, flags);
1738         n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id);
1739         if (n_pending > 0) {
1740                 if (hmidi->input) {
1741                         if (n_pending > (int)sizeof (buf))
1742                                 n_pending = sizeof (buf);
1743                         for (i = 0; i < n_pending; ++i)
1744                                 buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm,
1745                                                                    hmidi->id);
1746                         if (n_pending)
1747                                 snd_rawmidi_receive (hmidi->input, buf,
1748                                                      n_pending);
1749                 } else {
1750                         /* flush the MIDI input FIFO */
1751                         while (n_pending--)
1752                                 snd_hdspm_midi_read_byte (hmidi->hdspm,
1753                                                           hmidi->id);
1754                 }
1755         }
1756         hmidi->pending = 0;
1757         spin_unlock_irqrestore(&hmidi->lock, flags);
1758 
1759         spin_lock_irqsave(&hmidi->hdspm->lock, flags);
1760         hmidi->hdspm->control_register |= hmidi->ie;
1761         hdspm_write(hmidi->hdspm, HDSPM_controlRegister,
1762                     hmidi->hdspm->control_register);
1763         spin_unlock_irqrestore(&hmidi->hdspm->lock, flags);
1764 
1765         return snd_hdspm_midi_output_write (hmidi);
1766 }
1767 
1768 static void
1769 snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1770 {
1771         struct hdspm *hdspm;
1772         struct hdspm_midi *hmidi;
1773         unsigned long flags;
1774 
1775         hmidi = substream->rmidi->private_data;
1776         hdspm = hmidi->hdspm;
1777 
1778         spin_lock_irqsave (&hdspm->lock, flags);
1779         if (up) {
1780                 if (!(hdspm->control_register & hmidi->ie)) {
1781                         snd_hdspm_flush_midi_input (hdspm, hmidi->id);
1782                         hdspm->control_register |= hmidi->ie;
1783                 }
1784         } else {
1785                 hdspm->control_register &= ~hmidi->ie;
1786         }
1787 
1788         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1789         spin_unlock_irqrestore (&hdspm->lock, flags);
1790 }
1791 
1792 static void snd_hdspm_midi_output_timer(unsigned long data)
1793 {
1794         struct hdspm_midi *hmidi = (struct hdspm_midi *) data;
1795         unsigned long flags;
1796 
1797         snd_hdspm_midi_output_write(hmidi);
1798         spin_lock_irqsave (&hmidi->lock, flags);
1799 
1800         /* this does not bump hmidi->istimer, because the
1801            kernel automatically removed the timer when it
1802            expired, and we are now adding it back, thus
1803            leaving istimer wherever it was set before.
1804         */
1805 
1806         if (hmidi->istimer) {
1807                 hmidi->timer.expires = 1 + jiffies;
1808                 add_timer(&hmidi->timer);
1809         }
1810 
1811         spin_unlock_irqrestore (&hmidi->lock, flags);
1812 }
1813 
1814 static void
1815 snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1816 {
1817         struct hdspm_midi *hmidi;
1818         unsigned long flags;
1819 
1820         hmidi = substream->rmidi->private_data;
1821         spin_lock_irqsave (&hmidi->lock, flags);
1822         if (up) {
1823                 if (!hmidi->istimer) {
1824                         init_timer(&hmidi->timer);
1825                         hmidi->timer.function = snd_hdspm_midi_output_timer;
1826                         hmidi->timer.data = (unsigned long) hmidi;
1827                         hmidi->timer.expires = 1 + jiffies;
1828                         add_timer(&hmidi->timer);
1829                         hmidi->istimer++;
1830                 }
1831         } else {
1832                 if (hmidi->istimer && --hmidi->istimer <= 0)
1833                         del_timer (&hmidi->timer);
1834         }
1835         spin_unlock_irqrestore (&hmidi->lock, flags);
1836         if (up)
1837                 snd_hdspm_midi_output_write(hmidi);
1838 }
1839 
1840 static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream)
1841 {
1842         struct hdspm_midi *hmidi;
1843 
1844         hmidi = substream->rmidi->private_data;
1845         spin_lock_irq (&hmidi->lock);
1846         snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id);
1847         hmidi->input = substream;
1848         spin_unlock_irq (&hmidi->lock);
1849 
1850         return 0;
1851 }
1852 
1853 static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream)
1854 {
1855         struct hdspm_midi *hmidi;
1856 
1857         hmidi = substream->rmidi->private_data;
1858         spin_lock_irq (&hmidi->lock);
1859         hmidi->output = substream;
1860         spin_unlock_irq (&hmidi->lock);
1861 
1862         return 0;
1863 }
1864 
1865 static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream)
1866 {
1867         struct hdspm_midi *hmidi;
1868 
1869         snd_hdspm_midi_input_trigger (substream, 0);
1870 
1871         hmidi = substream->rmidi->private_data;
1872         spin_lock_irq (&hmidi->lock);
1873         hmidi->input = NULL;
1874         spin_unlock_irq (&hmidi->lock);
1875 
1876         return 0;
1877 }
1878 
1879 static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream)
1880 {
1881         struct hdspm_midi *hmidi;
1882 
1883         snd_hdspm_midi_output_trigger (substream, 0);
1884 
1885         hmidi = substream->rmidi->private_data;
1886         spin_lock_irq (&hmidi->lock);
1887         hmidi->output = NULL;
1888         spin_unlock_irq (&hmidi->lock);
1889 
1890         return 0;
1891 }
1892 
1893 static struct snd_rawmidi_ops snd_hdspm_midi_output =
1894 {
1895         .open =         snd_hdspm_midi_output_open,
1896         .close =        snd_hdspm_midi_output_close,
1897         .trigger =      snd_hdspm_midi_output_trigger,
1898 };
1899 
1900 static struct snd_rawmidi_ops snd_hdspm_midi_input =
1901 {
1902         .open =         snd_hdspm_midi_input_open,
1903         .close =        snd_hdspm_midi_input_close,
1904         .trigger =      snd_hdspm_midi_input_trigger,
1905 };
1906 
1907 static int snd_hdspm_create_midi(struct snd_card *card,
1908                                  struct hdspm *hdspm, int id)
1909 {
1910         int err;
1911         char buf[32];
1912 
1913         hdspm->midi[id].id = id;
1914         hdspm->midi[id].hdspm = hdspm;
1915         spin_lock_init (&hdspm->midi[id].lock);
1916 
1917         if (0 == id) {
1918                 if (MADIface == hdspm->io_type) {
1919                         /* MIDI-over-MADI on HDSPe MADIface */
1920                         hdspm->midi[0].dataIn = HDSPM_midiDataIn2;
1921                         hdspm->midi[0].statusIn = HDSPM_midiStatusIn2;
1922                         hdspm->midi[0].dataOut = HDSPM_midiDataOut2;
1923                         hdspm->midi[0].statusOut = HDSPM_midiStatusOut2;
1924                         hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable;
1925                         hdspm->midi[0].irq = HDSPM_midi2IRQPending;
1926                 } else {
1927                         hdspm->midi[0].dataIn = HDSPM_midiDataIn0;
1928                         hdspm->midi[0].statusIn = HDSPM_midiStatusIn0;
1929                         hdspm->midi[0].dataOut = HDSPM_midiDataOut0;
1930                         hdspm->midi[0].statusOut = HDSPM_midiStatusOut0;
1931                         hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable;
1932                         hdspm->midi[0].irq = HDSPM_midi0IRQPending;
1933                 }
1934         } else if (1 == id) {
1935                 hdspm->midi[1].dataIn = HDSPM_midiDataIn1;
1936                 hdspm->midi[1].statusIn = HDSPM_midiStatusIn1;
1937                 hdspm->midi[1].dataOut = HDSPM_midiDataOut1;
1938                 hdspm->midi[1].statusOut = HDSPM_midiStatusOut1;
1939                 hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable;
1940                 hdspm->midi[1].irq = HDSPM_midi1IRQPending;
1941         } else if ((2 == id) && (MADI == hdspm->io_type)) {
1942                 /* MIDI-over-MADI on HDSPe MADI */
1943                 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
1944                 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
1945                 hdspm->midi[2].dataOut = HDSPM_midiDataOut2;
1946                 hdspm->midi[2].statusOut = HDSPM_midiStatusOut2;
1947                 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
1948                 hdspm->midi[2].irq = HDSPM_midi2IRQPending;
1949         } else if (2 == id) {
1950                 /* TCO MTC, read only */
1951                 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
1952                 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
1953                 hdspm->midi[2].dataOut = -1;
1954                 hdspm->midi[2].statusOut = -1;
1955                 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
1956                 hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES;
1957         } else if (3 == id) {
1958                 /* TCO MTC on HDSPe MADI */
1959                 hdspm->midi[3].dataIn = HDSPM_midiDataIn3;
1960                 hdspm->midi[3].statusIn = HDSPM_midiStatusIn3;
1961                 hdspm->midi[3].dataOut = -1;
1962                 hdspm->midi[3].statusOut = -1;
1963                 hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable;
1964                 hdspm->midi[3].irq = HDSPM_midi3IRQPending;
1965         }
1966 
1967         if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) ||
1968                                         (MADIface == hdspm->io_type)))) {
1969                 if ((id == 0) && (MADIface == hdspm->io_type)) {
1970                         sprintf(buf, "%s MIDIoverMADI", card->shortname);
1971                 } else if ((id == 2) && (MADI == hdspm->io_type)) {
1972                         sprintf(buf, "%s MIDIoverMADI", card->shortname);
1973                 } else {
1974                         sprintf(buf, "%s MIDI %d", card->shortname, id+1);
1975                 }
1976                 err = snd_rawmidi_new(card, buf, id, 1, 1,
1977                                 &hdspm->midi[id].rmidi);
1978                 if (err < 0)
1979                         return err;
1980 
1981                 sprintf(hdspm->midi[id].rmidi->name, "%s MIDI %d",
1982                                 card->id, id+1);
1983                 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
1984 
1985                 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
1986                                 SNDRV_RAWMIDI_STREAM_OUTPUT,
1987                                 &snd_hdspm_midi_output);
1988                 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
1989                                 SNDRV_RAWMIDI_STREAM_INPUT,
1990                                 &snd_hdspm_midi_input);
1991 
1992                 hdspm->midi[id].rmidi->info_flags |=
1993                         SNDRV_RAWMIDI_INFO_OUTPUT |
1994                         SNDRV_RAWMIDI_INFO_INPUT |
1995                         SNDRV_RAWMIDI_INFO_DUPLEX;
1996         } else {
1997                 /* TCO MTC, read only */
1998                 sprintf(buf, "%s MTC %d", card->shortname, id+1);
1999                 err = snd_rawmidi_new(card, buf, id, 1, 1,
2000                                 &hdspm->midi[id].rmidi);
2001                 if (err < 0)
2002                         return err;
2003 
2004                 sprintf(hdspm->midi[id].rmidi->name,
2005                                 "%s MTC %d", card->id, id+1);
2006                 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
2007 
2008                 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2009                                 SNDRV_RAWMIDI_STREAM_INPUT,
2010                                 &snd_hdspm_midi_input);
2011 
2012                 hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT;
2013         }
2014 
2015         return 0;
2016 }
2017 
2018 
2019 static void hdspm_midi_tasklet(unsigned long arg)
2020 {
2021         struct hdspm *hdspm = (struct hdspm *)arg;
2022         int i = 0;
2023 
2024         while (i < hdspm->midiPorts) {
2025                 if (hdspm->midi[i].pending)
2026                         snd_hdspm_midi_input_read(&hdspm->midi[i]);
2027 
2028                 i++;
2029         }
2030 }
2031 
2032 
2033 /*-----------------------------------------------------------------------------
2034   Status Interface
2035   ----------------------------------------------------------------------------*/
2036 
2037 /* get the system sample rate which is set */
2038 
2039 
2040 static inline int hdspm_get_pll_freq(struct hdspm *hdspm)
2041 {
2042         unsigned int period, rate;
2043 
2044         period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
2045         rate = hdspm_calc_dds_value(hdspm, period);
2046 
2047         return rate;
2048 }
2049 
2050 /**
2051  * Calculate the real sample rate from the
2052  * current DDS value.
2053  **/
2054 static int hdspm_get_system_sample_rate(struct hdspm *hdspm)
2055 {
2056         unsigned int rate;
2057 
2058         rate = hdspm_get_pll_freq(hdspm);
2059 
2060         if (rate > 207000) {
2061                 /* Unreasonable high sample rate as seen on PCI MADI cards. */
2062                 if (0 == hdspm_system_clock_mode(hdspm)) {
2063                         /* master mode, return internal sample rate */
2064                         rate = hdspm->system_sample_rate;
2065                 } else {
2066                         /* slave mode, return external sample rate */
2067                         rate = hdspm_external_sample_rate(hdspm);
2068                 }
2069         }
2070 
2071         return rate;
2072 }
2073 
2074 
2075 #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \
2076 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2077         .name = xname, \
2078         .index = xindex, \
2079         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2080                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2081         .info = snd_hdspm_info_system_sample_rate, \
2082         .put = snd_hdspm_put_system_sample_rate, \
2083         .get = snd_hdspm_get_system_sample_rate \
2084 }
2085 
2086 static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol,
2087                                              struct snd_ctl_elem_info *uinfo)
2088 {
2089         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2090         uinfo->count = 1;
2091         uinfo->value.integer.min = 27000;
2092         uinfo->value.integer.max = 207000;
2093         uinfo->value.integer.step = 1;
2094         return 0;
2095 }
2096 
2097 
2098 static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol,
2099                                             struct snd_ctl_elem_value *
2100                                             ucontrol)
2101 {
2102         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2103 
2104         ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm);
2105         return 0;
2106 }
2107 
2108 static int snd_hdspm_put_system_sample_rate(struct snd_kcontrol *kcontrol,
2109                                             struct snd_ctl_elem_value *
2110                                             ucontrol)
2111 {
2112         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2113 
2114         hdspm_set_dds_value(hdspm, ucontrol->value.enumerated.item[0]);
2115         return 0;
2116 }
2117 
2118 
2119 /**
2120  * Returns the WordClock sample rate class for the given card.
2121  **/
2122 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm)
2123 {
2124         int status;
2125 
2126         switch (hdspm->io_type) {
2127         case RayDAT:
2128         case AIO:
2129                 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2130                 return (status >> 16) & 0xF;
2131                 break;
2132         default:
2133                 break;
2134         }
2135 
2136 
2137         return 0;
2138 }
2139 
2140 
2141 /**
2142  * Returns the TCO sample rate class for the given card.
2143  **/
2144 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm)
2145 {
2146         int status;
2147 
2148         if (hdspm->tco) {
2149                 switch (hdspm->io_type) {
2150                 case RayDAT:
2151                 case AIO:
2152                         status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2153                         return (status >> 20) & 0xF;
2154                         break;
2155                 default:
2156                         break;
2157                 }
2158         }
2159 
2160         return 0;
2161 }
2162 
2163 
2164 /**
2165  * Returns the SYNC_IN sample rate class for the given card.
2166  **/
2167 static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm)
2168 {
2169         int status;
2170 
2171         if (hdspm->tco) {
2172                 switch (hdspm->io_type) {
2173                 case RayDAT:
2174                 case AIO:
2175                         status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2176                         return (status >> 12) & 0xF;
2177                         break;
2178                 default:
2179                         break;
2180                 }
2181         }
2182 
2183         return 0;
2184 }
2185 
2186 
2187 /**
2188  * Returns the sample rate class for input source <idx> for
2189  * 'new style' cards like the AIO and RayDAT.
2190  **/
2191 static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx)
2192 {
2193         int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2194 
2195         return (status >> (idx*4)) & 0xF;
2196 }
2197 
2198 #define ENUMERATED_CTL_INFO(info, texts) \
2199 { \
2200         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; \
2201         uinfo->count = 1; \
2202         uinfo->value.enumerated.items = ARRAY_SIZE(texts); \
2203         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) \
2204                 uinfo->value.enumerated.item =  uinfo->value.enumerated.items - 1; \
2205         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); \
2206 }
2207 
2208 
2209 
2210 #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
2211 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2212         .name = xname, \
2213         .private_value = xindex, \
2214         .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2215         .info = snd_hdspm_info_autosync_sample_rate, \
2216         .get = snd_hdspm_get_autosync_sample_rate \
2217 }
2218 
2219 
2220 static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2221                                                struct snd_ctl_elem_info *uinfo)
2222 {
2223         ENUMERATED_CTL_INFO(uinfo, texts_freq);
2224         return 0;
2225 }
2226 
2227 
2228 static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2229                                               struct snd_ctl_elem_value *
2230                                               ucontrol)
2231 {
2232         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2233 
2234         switch (hdspm->io_type) {
2235         case RayDAT:
2236                 switch (kcontrol->private_value) {
2237                 case 0:
2238                         ucontrol->value.enumerated.item[0] =
2239                                 hdspm_get_wc_sample_rate(hdspm);
2240                         break;
2241                 case 7:
2242                         ucontrol->value.enumerated.item[0] =
2243                                 hdspm_get_tco_sample_rate(hdspm);
2244                         break;
2245                 case 8:
2246                         ucontrol->value.enumerated.item[0] =
2247                                 hdspm_get_sync_in_sample_rate(hdspm);
2248                         break;
2249                 default:
2250                         ucontrol->value.enumerated.item[0] =
2251                                 hdspm_get_s1_sample_rate(hdspm,
2252                                                 kcontrol->private_value-1);
2253                 }
2254                 break;
2255 
2256         case AIO:
2257                 switch (kcontrol->private_value) {
2258                 case 0: /* WC */
2259                         ucontrol->value.enumerated.item[0] =
2260                                 hdspm_get_wc_sample_rate(hdspm);
2261                         break;
2262                 case 4: /* TCO */
2263                         ucontrol->value.enumerated.item[0] =
2264                                 hdspm_get_tco_sample_rate(hdspm);
2265                         break;
2266                 case 5: /* SYNC_IN */
2267                         ucontrol->value.enumerated.item[0] =
2268                                 hdspm_get_sync_in_sample_rate(hdspm);
2269                         break;
2270                 default:
2271                         ucontrol->value.enumerated.item[0] =
2272                                 hdspm_get_s1_sample_rate(hdspm,
2273                                                 ucontrol->id.index-1);
2274                 }
2275                 break;
2276 
2277         case AES32:
2278 
2279                 switch (kcontrol->private_value) {
2280                 case 0: /* WC */
2281                         ucontrol->value.enumerated.item[0] =
2282                                 hdspm_get_wc_sample_rate(hdspm);
2283                         break;
2284                 case 9: /* TCO */
2285                         ucontrol->value.enumerated.item[0] =
2286                                 hdspm_get_tco_sample_rate(hdspm);
2287                         break;
2288                 case 10: /* SYNC_IN */
2289                         ucontrol->value.enumerated.item[0] =
2290                                 hdspm_get_sync_in_sample_rate(hdspm);
2291                         break;
2292                 default: /* AES1 to AES8 */
2293                         ucontrol->value.enumerated.item[0] =
2294                                 hdspm_get_s1_sample_rate(hdspm,
2295                                                 kcontrol->private_value-1);
2296                         break;
2297                 }
2298                 break;
2299 
2300         case MADI:
2301         case MADIface:
2302                 {
2303                         int rate = hdspm_external_sample_rate(hdspm);
2304                         int i, selected_rate = 0;
2305                         for (i = 1; i < 10; i++)
2306                                 if (HDSPM_bit2freq(i) == rate) {
2307                                         selected_rate = i;
2308                                         break;
2309                                 }
2310                         ucontrol->value.enumerated.item[0] = selected_rate;
2311                 }
2312                 break;
2313 
2314         default:
2315                 break;
2316         }
2317 
2318         return 0;
2319 }
2320 
2321 
2322 #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \
2323 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2324         .name = xname, \
2325         .index = xindex, \
2326         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2327                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2328         .info = snd_hdspm_info_system_clock_mode, \
2329         .get = snd_hdspm_get_system_clock_mode, \
2330         .put = snd_hdspm_put_system_clock_mode, \
2331 }
2332 
2333 
2334 /**
2335  * Returns the system clock mode for the given card.
2336  * @returns 0 - master, 1 - slave
2337  **/
2338 static int hdspm_system_clock_mode(struct hdspm *hdspm)
2339 {
2340         switch (hdspm->io_type) {
2341         case AIO:
2342         case RayDAT:
2343                 if (hdspm->settings_register & HDSPM_c0Master)
2344                         return 0;
2345                 break;
2346 
2347         default:
2348                 if (hdspm->control_register & HDSPM_ClockModeMaster)
2349                         return 0;
2350         }
2351 
2352         return 1;
2353 }
2354 
2355 
2356 /**
2357  * Sets the system clock mode.
2358  * @param mode 0 - master, 1 - slave
2359  **/
2360 static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode)
2361 {
2362         switch (hdspm->io_type) {
2363         case AIO:
2364         case RayDAT:
2365                 if (0 == mode)
2366                         hdspm->settings_register |= HDSPM_c0Master;
2367                 else
2368                         hdspm->settings_register &= ~HDSPM_c0Master;
2369 
2370                 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2371                 break;
2372 
2373         default:
2374                 if (0 == mode)
2375                         hdspm->control_register |= HDSPM_ClockModeMaster;
2376                 else
2377                         hdspm->control_register &= ~HDSPM_ClockModeMaster;
2378 
2379                 hdspm_write(hdspm, HDSPM_controlRegister,
2380                                 hdspm->control_register);
2381         }
2382 }
2383 
2384 
2385 static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol,
2386                                             struct snd_ctl_elem_info *uinfo)
2387 {
2388         static char *texts[] = { "Master", "AutoSync" };
2389         ENUMERATED_CTL_INFO(uinfo, texts);
2390         return 0;
2391 }
2392 
2393 static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol,
2394                                            struct snd_ctl_elem_value *ucontrol)
2395 {
2396         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2397 
2398         ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm);
2399         return 0;
2400 }
2401 
2402 static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol,
2403                                            struct snd_ctl_elem_value *ucontrol)
2404 {
2405         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2406         int val;
2407 
2408         if (!snd_hdspm_use_is_exclusive(hdspm))
2409                 return -EBUSY;
2410 
2411         val = ucontrol->value.enumerated.item[0];
2412         if (val < 0)
2413                 val = 0;
2414         else if (val > 1)
2415                 val = 1;
2416 
2417         hdspm_set_system_clock_mode(hdspm, val);
2418 
2419         return 0;
2420 }
2421 
2422 
2423 #define HDSPM_INTERNAL_CLOCK(xname, xindex) \
2424 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2425         .name = xname, \
2426         .index = xindex, \
2427         .info = snd_hdspm_info_clock_source, \
2428         .get = snd_hdspm_get_clock_source, \
2429         .put = snd_hdspm_put_clock_source \
2430 }
2431 
2432 
2433 static int hdspm_clock_source(struct hdspm * hdspm)
2434 {
2435         switch (hdspm->system_sample_rate) {
2436         case 32000: return 0;
2437         case 44100: return 1;
2438         case 48000: return 2;
2439         case 64000: return 3;
2440         case 88200: return 4;
2441         case 96000: return 5;
2442         case 128000: return 6;
2443         case 176400: return 7;
2444         case 192000: return 8;
2445         }
2446 
2447         return -1;
2448 }
2449 
2450 static int hdspm_set_clock_source(struct hdspm * hdspm, int mode)
2451 {
2452         int rate;
2453         switch (mode) {
2454         case 0:
2455                 rate = 32000; break;
2456         case 1:
2457                 rate = 44100; break;
2458         case 2:
2459                 rate = 48000; break;
2460         case 3:
2461                 rate = 64000; break;
2462         case 4:
2463                 rate = 88200; break;
2464         case 5:
2465                 rate = 96000; break;
2466         case 6:
2467                 rate = 128000; break;
2468         case 7:
2469                 rate = 176400; break;
2470         case 8:
2471                 rate = 192000; break;
2472         default:
2473                 rate = 48000;
2474         }
2475         hdspm_set_rate(hdspm, rate, 1);
2476         return 0;
2477 }
2478 
2479 static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol,
2480                                        struct snd_ctl_elem_info *uinfo)
2481 {
2482         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2483         uinfo->count = 1;
2484         uinfo->value.enumerated.items = 9;
2485 
2486         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2487                 uinfo->value.enumerated.item =
2488                     uinfo->value.enumerated.items - 1;
2489 
2490         strcpy(uinfo->value.enumerated.name,
2491                texts_freq[uinfo->value.enumerated.item+1]);
2492 
2493         return 0;
2494 }
2495 
2496 static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol,
2497                                       struct snd_ctl_elem_value *ucontrol)
2498 {
2499         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2500 
2501         ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm);
2502         return 0;
2503 }
2504 
2505 static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol,
2506                                       struct snd_ctl_elem_value *ucontrol)
2507 {
2508         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2509         int change;
2510         int val;
2511 
2512         if (!snd_hdspm_use_is_exclusive(hdspm))
2513                 return -EBUSY;
2514         val = ucontrol->value.enumerated.item[0];
2515         if (val < 0)
2516                 val = 0;
2517         if (val > 9)
2518                 val = 9;
2519         spin_lock_irq(&hdspm->lock);
2520         if (val != hdspm_clock_source(hdspm))
2521                 change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0;
2522         else
2523                 change = 0;
2524         spin_unlock_irq(&hdspm->lock);
2525         return change;
2526 }
2527 
2528 
2529 #define HDSPM_PREF_SYNC_REF(xname, xindex) \
2530 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2531         .name = xname, \
2532         .index = xindex, \
2533         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2534                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2535         .info = snd_hdspm_info_pref_sync_ref, \
2536         .get = snd_hdspm_get_pref_sync_ref, \
2537         .put = snd_hdspm_put_pref_sync_ref \
2538 }
2539 
2540 
2541 /**
2542  * Returns the current preferred sync reference setting.
2543  * The semantics of the return value are depending on the
2544  * card, please see the comments for clarification.
2545  **/
2546 static int hdspm_pref_sync_ref(struct hdspm * hdspm)
2547 {
2548         switch (hdspm->io_type) {
2549         case AES32:
2550                 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2551                 case 0: return 0;  /* WC */
2552                 case HDSPM_SyncRef0: return 1; /* AES 1 */
2553                 case HDSPM_SyncRef1: return 2; /* AES 2 */
2554                 case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */
2555                 case HDSPM_SyncRef2: return 4; /* AES 4 */
2556                 case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */
2557                 case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */
2558                 case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0:
2559                                                     return 7; /* AES 7 */
2560                 case HDSPM_SyncRef3: return 8; /* AES 8 */
2561                 case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */
2562                 }
2563                 break;
2564 
2565         case MADI:
2566         case MADIface:
2567                 if (hdspm->tco) {
2568                         switch (hdspm->control_register & HDSPM_SyncRefMask) {
2569                         case 0: return 0;  /* WC */
2570                         case HDSPM_SyncRef0: return 1;  /* MADI */
2571                         case HDSPM_SyncRef1: return 2;  /* TCO */
2572                         case HDSPM_SyncRef1+HDSPM_SyncRef0:
2573                                              return 3;  /* SYNC_IN */
2574                         }
2575                 } else {
2576                         switch (hdspm->control_register & HDSPM_SyncRefMask) {
2577                         case 0: return 0;  /* WC */
2578                         case HDSPM_SyncRef0: return 1;  /* MADI */
2579                         case HDSPM_SyncRef1+HDSPM_SyncRef0:
2580                                              return 2;  /* SYNC_IN */
2581                         }
2582                 }
2583                 break;
2584 
2585         case RayDAT:
2586                 if (hdspm->tco) {
2587                         switch ((hdspm->settings_register &
2588                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2589                         case 0: return 0;  /* WC */
2590                         case 3: return 1;  /* ADAT 1 */
2591                         case 4: return 2;  /* ADAT 2 */
2592                         case 5: return 3;  /* ADAT 3 */
2593                         case 6: return 4;  /* ADAT 4 */
2594                         case 1: return 5;  /* AES */
2595                         case 2: return 6;  /* SPDIF */
2596                         case 9: return 7;  /* TCO */
2597                         case 10: return 8; /* SYNC_IN */
2598                         }
2599                 } else {
2600                         switch ((hdspm->settings_register &
2601                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2602                         case 0: return 0;  /* WC */
2603                         case 3: return 1;  /* ADAT 1 */
2604                         case 4: return 2;  /* ADAT 2 */
2605                         case 5: return 3;  /* ADAT 3 */
2606                         case 6: return 4;  /* ADAT 4 */
2607                         case 1: return 5;  /* AES */
2608                         case 2: return 6;  /* SPDIF */
2609                         case 10: return 7; /* SYNC_IN */
2610                         }
2611                 }
2612 
2613                 break;
2614 
2615         case AIO:
2616                 if (hdspm->tco) {
2617                         switch ((hdspm->settings_register &
2618                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2619                         case 0: return 0;  /* WC */
2620                         case 3: return 1;  /* ADAT */
2621                         case 1: return 2;  /* AES */
2622                         case 2: return 3;  /* SPDIF */
2623                         case 9: return 4;  /* TCO */
2624                         case 10: return 5; /* SYNC_IN */
2625                         }
2626                 } else {
2627                         switch ((hdspm->settings_register &
2628                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2629                         case 0: return 0;  /* WC */
2630                         case 3: return 1;  /* ADAT */
2631                         case 1: return 2;  /* AES */
2632                         case 2: return 3;  /* SPDIF */
2633                         case 10: return 4; /* SYNC_IN */
2634                         }
2635                 }
2636 
2637                 break;
2638         }
2639 
2640         return -1;
2641 }
2642 
2643 
2644 /**
2645  * Set the preferred sync reference to <pref>. The semantics
2646  * of <pref> are depending on the card type, see the comments
2647  * for clarification.
2648  **/
2649 static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref)
2650 {
2651         int p = 0;
2652 
2653         switch (hdspm->io_type) {
2654         case AES32:
2655                 hdspm->control_register &= ~HDSPM_SyncRefMask;
2656                 switch (pref) {
2657                 case 0: /* WC  */
2658                         break;
2659                 case 1: /* AES 1 */
2660                         hdspm->control_register |= HDSPM_SyncRef0;
2661                         break;
2662                 case 2: /* AES 2 */
2663                         hdspm->control_register |= HDSPM_SyncRef1;
2664                         break;
2665                 case 3: /* AES 3 */
2666                         hdspm->control_register |=
2667                                 HDSPM_SyncRef1+HDSPM_SyncRef0;
2668                         break;
2669                 case 4: /* AES 4 */
2670                         hdspm->control_register |= HDSPM_SyncRef2;
2671                         break;
2672                 case 5: /* AES 5 */
2673                         hdspm->control_register |=
2674                                 HDSPM_SyncRef2+HDSPM_SyncRef0;
2675                         break;
2676                 case 6: /* AES 6 */
2677                         hdspm->control_register |=
2678                                 HDSPM_SyncRef2+HDSPM_SyncRef1;
2679                         break;
2680                 case 7: /* AES 7 */
2681                         hdspm->control_register |=
2682                                 HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0;
2683                         break;
2684                 case 8: /* AES 8 */
2685                         hdspm->control_register |= HDSPM_SyncRef3;
2686                         break;
2687                 case 9: /* TCO */
2688                         hdspm->control_register |=
2689                                 HDSPM_SyncRef3+HDSPM_SyncRef0;
2690                         break;
2691                 default:
2692                         return -1;
2693                 }
2694 
2695                 break;
2696 
2697         case MADI:
2698         case MADIface:
2699                 hdspm->control_register &= ~HDSPM_SyncRefMask;
2700                 if (hdspm->tco) {
2701                         switch (pref) {
2702                         case 0: /* WC */
2703                                 break;
2704                         case 1: /* MADI */
2705                                 hdspm->control_register |= HDSPM_SyncRef0;
2706                                 break;
2707                         case 2: /* TCO */
2708                                 hdspm->control_register |= HDSPM_SyncRef1;
2709                                 break;
2710                         case 3: /* SYNC_IN */
2711                                 hdspm->control_register |=
2712                                         HDSPM_SyncRef0+HDSPM_SyncRef1;
2713                                 break;
2714                         default:
2715                                 return -1;
2716                         }
2717                 } else {
2718                         switch (pref) {
2719                         case 0: /* WC */
2720                                 break;
2721                         case 1: /* MADI */
2722                                 hdspm->control_register |= HDSPM_SyncRef0;
2723                                 break;
2724                         case 2: /* SYNC_IN */
2725                                 hdspm->control_register |=
2726                                         HDSPM_SyncRef0+HDSPM_SyncRef1;
2727                                 break;
2728                         default:
2729                                 return -1;
2730                         }
2731                 }
2732 
2733                 break;
2734 
2735         case RayDAT:
2736                 if (hdspm->tco) {
2737                         switch (pref) {
2738                         case 0: p = 0; break;  /* WC */
2739                         case 1: p = 3; break;  /* ADAT 1 */
2740                         case 2: p = 4; break;  /* ADAT 2 */
2741                         case 3: p = 5; break;  /* ADAT 3 */
2742                         case 4: p = 6; break;  /* ADAT 4 */
2743                         case 5: p = 1; break;  /* AES */
2744                         case 6: p = 2; break;  /* SPDIF */
2745                         case 7: p = 9; break;  /* TCO */
2746                         case 8: p = 10; break; /* SYNC_IN */
2747                         default: return -1;
2748                         }
2749                 } else {
2750                         switch (pref) {
2751                         case 0: p = 0; break;  /* WC */
2752                         case 1: p = 3; break;  /* ADAT 1 */
2753                         case 2: p = 4; break;  /* ADAT 2 */
2754                         case 3: p = 5; break;  /* ADAT 3 */
2755                         case 4: p = 6; break;  /* ADAT 4 */
2756                         case 5: p = 1; break;  /* AES */
2757                         case 6: p = 2; break;  /* SPDIF */
2758                         case 7: p = 10; break; /* SYNC_IN */
2759                         default: return -1;
2760                         }
2761                 }
2762                 break;
2763 
2764         case AIO:
2765                 if (hdspm->tco) {
2766                         switch (pref) {
2767                         case 0: p = 0; break;  /* WC */
2768                         case 1: p = 3; break;  /* ADAT */
2769                         case 2: p = 1; break;  /* AES */
2770                         case 3: p = 2; break;  /* SPDIF */
2771                         case 4: p = 9; break;  /* TCO */
2772                         case 5: p = 10; break; /* SYNC_IN */
2773                         default: return -1;
2774                         }
2775                 } else {
2776                         switch (pref) {
2777                         case 0: p = 0; break;  /* WC */
2778                         case 1: p = 3; break;  /* ADAT */
2779                         case 2: p = 1; break;  /* AES */
2780                         case 3: p = 2; break;  /* SPDIF */
2781                         case 4: p = 10; break; /* SYNC_IN */
2782                         default: return -1;
2783                         }
2784                 }
2785                 break;
2786         }
2787 
2788         switch (hdspm->io_type) {
2789         case RayDAT:
2790         case AIO:
2791                 hdspm->settings_register &= ~HDSPM_c0_SyncRefMask;
2792                 hdspm->settings_register |= HDSPM_c0_SyncRef0 * p;
2793                 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2794                 break;
2795 
2796         case MADI:
2797         case MADIface:
2798         case AES32:
2799                 hdspm_write(hdspm, HDSPM_controlRegister,
2800                                 hdspm->control_register);
2801         }
2802 
2803         return 0;
2804 }
2805 
2806 
2807 static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol,
2808                                         struct snd_ctl_elem_info *uinfo)
2809 {
2810         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2811 
2812         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2813         uinfo->count = 1;
2814         uinfo->value.enumerated.items = hdspm->texts_autosync_items;
2815 
2816         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2817                 uinfo->value.enumerated.item =
2818                         uinfo->value.enumerated.items - 1;
2819 
2820         strcpy(uinfo->value.enumerated.name,
2821                         hdspm->texts_autosync[uinfo->value.enumerated.item]);
2822 
2823         return 0;
2824 }
2825 
2826 static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol,
2827                                        struct snd_ctl_elem_value *ucontrol)
2828 {
2829         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2830         int psf = hdspm_pref_sync_ref(hdspm);
2831 
2832         if (psf >= 0) {
2833                 ucontrol->value.enumerated.item[0] = psf;
2834                 return 0;
2835         }
2836 
2837         return -1;
2838 }
2839 
2840 static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol,
2841                                        struct snd_ctl_elem_value *ucontrol)
2842 {
2843         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2844         int val, change = 0;
2845 
2846         if (!snd_hdspm_use_is_exclusive(hdspm))
2847                 return -EBUSY;
2848 
2849         val = ucontrol->value.enumerated.item[0];
2850 
2851         if (val < 0)
2852                 val = 0;
2853         else if (val >= hdspm->texts_autosync_items)
2854                 val = hdspm->texts_autosync_items-1;
2855 
2856         spin_lock_irq(&hdspm->lock);
2857         if (val != hdspm_pref_sync_ref(hdspm))
2858                 change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0;
2859 
2860         spin_unlock_irq(&hdspm->lock);
2861         return change;
2862 }
2863 
2864 
2865 #define HDSPM_AUTOSYNC_REF(xname, xindex) \
2866 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2867         .name = xname, \
2868         .index = xindex, \
2869         .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2870         .info = snd_hdspm_info_autosync_ref, \
2871         .get = snd_hdspm_get_autosync_ref, \
2872 }
2873 
2874 static int hdspm_autosync_ref(struct hdspm *hdspm)
2875 {
2876         if (AES32 == hdspm->io_type) {
2877                 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister);
2878                 unsigned int syncref =
2879                         (status >> HDSPM_AES32_syncref_bit) & 0xF;
2880                 if (syncref == 0)
2881                         return HDSPM_AES32_AUTOSYNC_FROM_WORD;
2882                 if (syncref <= 8)
2883                         return syncref;
2884                 return HDSPM_AES32_AUTOSYNC_FROM_NONE;
2885         } else if (MADI == hdspm->io_type) {
2886                 /* This looks at the autosync selected sync reference */
2887                 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
2888 
2889                 switch (status2 & HDSPM_SelSyncRefMask) {
2890                 case HDSPM_SelSyncRef_WORD:
2891                         return HDSPM_AUTOSYNC_FROM_WORD;
2892                 case HDSPM_SelSyncRef_MADI:
2893                         return HDSPM_AUTOSYNC_FROM_MADI;
2894                 case HDSPM_SelSyncRef_TCO:
2895                         return HDSPM_AUTOSYNC_FROM_TCO;
2896                 case HDSPM_SelSyncRef_SyncIn:
2897                         return HDSPM_AUTOSYNC_FROM_SYNC_IN;
2898                 case HDSPM_SelSyncRef_NVALID:
2899                         return HDSPM_AUTOSYNC_FROM_NONE;
2900                 default:
2901                         return 0;
2902                 }
2903 
2904         }
2905         return 0;
2906 }
2907 
2908 
2909 static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol,
2910                                        struct snd_ctl_elem_info *uinfo)
2911 {
2912         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2913 
2914         if (AES32 == hdspm->io_type) {
2915                 static char *texts[] = { "WordClock", "AES1", "AES2", "AES3",
2916                         "AES4", "AES5", "AES6", "AES7", "AES8", "None"};
2917 
2918                 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2919                 uinfo->count = 1;
2920                 uinfo->value.enumerated.items = 10;
2921                 if (uinfo->value.enumerated.item >=
2922                     uinfo->value.enumerated.items)
2923                         uinfo->value.enumerated.item =
2924                                 uinfo->value.enumerated.items - 1;
2925                 strcpy(uinfo->value.enumerated.name,
2926                                 texts[uinfo->value.enumerated.item]);
2927         } else if (MADI == hdspm->io_type) {
2928                 static char *texts[] = {"Word Clock", "MADI", "TCO",
2929                         "Sync In", "None" };
2930 
2931                 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2932                 uinfo->count = 1;
2933                 uinfo->value.enumerated.items = 5;
2934                 if (uinfo->value.enumerated.item >=
2935                                 uinfo->value.enumerated.items)
2936                         uinfo->value.enumerated.item =
2937                                 uinfo->value.enumerated.items - 1;
2938                 strcpy(uinfo->value.enumerated.name,
2939                                 texts[uinfo->value.enumerated.item]);
2940         }
2941         return 0;
2942 }
2943 
2944 static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol,
2945                                       struct snd_ctl_elem_value *ucontrol)
2946 {
2947         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2948 
2949         ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm);
2950         return 0;
2951 }
2952 
2953 
2954 
2955 #define HDSPM_TCO_VIDEO_INPUT_FORMAT(xname, xindex) \
2956 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2957         .name = xname, \
2958         .access = SNDRV_CTL_ELEM_ACCESS_READ |\
2959                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2960         .info = snd_hdspm_info_tco_video_input_format, \
2961         .get = snd_hdspm_get_tco_video_input_format, \
2962 }
2963 
2964 static int snd_hdspm_info_tco_video_input_format(struct snd_kcontrol *kcontrol,
2965                                        struct snd_ctl_elem_info *uinfo)
2966 {
2967         static char *texts[] = {"No video", "NTSC", "PAL"};
2968         ENUMERATED_CTL_INFO(uinfo, texts);
2969         return 0;
2970 }
2971 
2972 static int snd_hdspm_get_tco_video_input_format(struct snd_kcontrol *kcontrol,
2973                                       struct snd_ctl_elem_value *ucontrol)
2974 {
2975         u32 status;
2976         int ret = 0;
2977 
2978         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2979         status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
2980         switch (status & (HDSPM_TCO1_Video_Input_Format_NTSC |
2981                         HDSPM_TCO1_Video_Input_Format_PAL)) {
2982         case HDSPM_TCO1_Video_Input_Format_NTSC:
2983                 /* ntsc */
2984                 ret = 1;
2985                 break;
2986         case HDSPM_TCO1_Video_Input_Format_PAL:
2987                 /* pal */
2988                 ret = 2;
2989                 break;
2990         default:
2991                 /* no video */
2992                 ret = 0;
2993                 break;
2994         }
2995         ucontrol->value.enumerated.item[0] = ret;
2996         return 0;
2997 }
2998 
2999 
3000 
3001 #define HDSPM_TCO_LTC_FRAMES(xname, xindex) \
3002 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3003         .name = xname, \
3004         .access = SNDRV_CTL_ELEM_ACCESS_READ |\
3005                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3006         .info = snd_hdspm_info_tco_ltc_frames, \
3007         .get = snd_hdspm_get_tco_ltc_frames, \
3008 }
3009 
3010 static int snd_hdspm_info_tco_ltc_frames(struct snd_kcontrol *kcontrol,
3011                                        struct snd_ctl_elem_info *uinfo)
3012 {
3013         static char *texts[] = {"No lock", "24 fps", "25 fps", "29.97 fps",
3014                                 "30 fps"};
3015         ENUMERATED_CTL_INFO(uinfo, texts);
3016         return 0;
3017 }
3018 
3019 static int hdspm_tco_ltc_frames(struct hdspm *hdspm)
3020 {
3021         u32 status;
3022         int ret = 0;
3023 
3024         status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3025         if (status & HDSPM_TCO1_LTC_Input_valid) {
3026                 switch (status & (HDSPM_TCO1_LTC_Format_LSB |
3027                                         HDSPM_TCO1_LTC_Format_MSB)) {
3028                 case 0:
3029                         /* 24 fps */
3030                         ret = 1;
3031                         break;
3032                 case HDSPM_TCO1_LTC_Format_LSB:
3033                         /* 25 fps */
3034                         ret = 2;
3035                         break;
3036                 case HDSPM_TCO1_LTC_Format_MSB:
3037                         /* 25 fps */
3038                         ret = 3;
3039                         break;
3040                 default:
3041                         /* 30 fps */
3042                         ret = 4;
3043                         break;
3044                 }
3045         }
3046 
3047         return ret;
3048 }
3049 
3050 static int snd_hdspm_get_tco_ltc_frames(struct snd_kcontrol *kcontrol,
3051                                       struct snd_ctl_elem_value *ucontrol)
3052 {
3053         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3054 
3055         ucontrol->value.enumerated.item[0] = hdspm_tco_ltc_frames(hdspm);
3056         return 0;
3057 }
3058 
3059 #define HDSPM_TOGGLE_SETTING(xname, xindex) \
3060 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3061         .name = xname, \
3062         .private_value = xindex, \
3063         .info = snd_hdspm_info_toggle_setting, \
3064         .get = snd_hdspm_get_toggle_setting, \
3065         .put = snd_hdspm_put_toggle_setting \
3066 }
3067 
3068 static int hdspm_toggle_setting(struct hdspm *hdspm, u32 regmask)
3069 {
3070         return (hdspm->control_register & regmask) ? 1 : 0;
3071 }
3072 
3073 static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out)
3074 {
3075         if (out)
3076                 hdspm->control_register |= regmask;
3077         else
3078                 hdspm->control_register &= ~regmask;
3079         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3080 
3081         return 0;
3082 }
3083 
3084 #define snd_hdspm_info_toggle_setting           snd_ctl_boolean_mono_info
3085 
3086 static int snd_hdspm_get_toggle_setting(struct snd_kcontrol *kcontrol,
3087                                struct snd_ctl_elem_value *ucontrol)
3088 {
3089         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3090         u32 regmask = kcontrol->private_value;
3091 
3092         spin_lock_irq(&hdspm->lock);
3093         ucontrol->value.integer.value[0] = hdspm_toggle_setting(hdspm, regmask);
3094         spin_unlock_irq(&hdspm->lock);
3095         return 0;
3096 }
3097 
3098 static int snd_hdspm_put_toggle_setting(struct snd_kcontrol *kcontrol,
3099                                struct snd_ctl_elem_value *ucontrol)
3100 {
3101         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3102         u32 regmask = kcontrol->private_value;
3103         int change;
3104         unsigned int val;
3105 
3106         if (!snd_hdspm_use_is_exclusive(hdspm))
3107                 return -EBUSY;
3108         val = ucontrol->value.integer.value[0] & 1;
3109         spin_lock_irq(&hdspm->lock);
3110         change = (int) val != hdspm_toggle_setting(hdspm, regmask);
3111         hdspm_set_toggle_setting(hdspm, regmask, val);
3112         spin_unlock_irq(&hdspm->lock);
3113         return change;
3114 }
3115 
3116 #define HDSPM_INPUT_SELECT(xname, xindex) \
3117 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3118         .name = xname, \
3119         .index = xindex, \
3120         .info = snd_hdspm_info_input_select, \
3121         .get = snd_hdspm_get_input_select, \
3122         .put = snd_hdspm_put_input_select \
3123 }
3124 
3125 static int hdspm_input_select(struct hdspm * hdspm)
3126 {
3127         return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0;
3128 }
3129 
3130 static int hdspm_set_input_select(struct hdspm * hdspm, int out)
3131 {
3132         if (out)
3133                 hdspm->control_register |= HDSPM_InputSelect0;
3134         else
3135                 hdspm->control_register &= ~HDSPM_InputSelect0;
3136         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3137 
3138         return 0;
3139 }
3140 
3141 static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol,
3142                                        struct snd_ctl_elem_info *uinfo)
3143 {
3144         static char *texts[] = { "optical", "coaxial" };
3145         ENUMERATED_CTL_INFO(uinfo, texts);
3146         return 0;
3147 }
3148 
3149 static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol,
3150                                       struct snd_ctl_elem_value *ucontrol)
3151 {
3152         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3153 
3154         spin_lock_irq(&hdspm->lock);
3155         ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm);
3156         spin_unlock_irq(&hdspm->lock);
3157         return 0;
3158 }
3159 
3160 static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol,
3161                                       struct snd_ctl_elem_value *ucontrol)
3162 {
3163         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3164         int change;
3165         unsigned int val;
3166 
3167         if (!snd_hdspm_use_is_exclusive(hdspm))
3168                 return -EBUSY;
3169         val = ucontrol->value.integer.value[0] & 1;
3170         spin_lock_irq(&hdspm->lock);
3171         change = (int) val != hdspm_input_select(hdspm);
3172         hdspm_set_input_select(hdspm, val);
3173         spin_unlock_irq(&hdspm->lock);
3174         return change;
3175 }
3176 
3177 
3178 #define HDSPM_DS_WIRE(xname, xindex) \
3179 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3180         .name = xname, \
3181         .index = xindex, \
3182         .info = snd_hdspm_info_ds_wire, \
3183         .get = snd_hdspm_get_ds_wire, \
3184         .put = snd_hdspm_put_ds_wire \
3185 }
3186 
3187 static int hdspm_ds_wire(struct hdspm * hdspm)
3188 {
3189         return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0;
3190 }
3191 
3192 static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds)
3193 {
3194         if (ds)
3195                 hdspm->control_register |= HDSPM_DS_DoubleWire;
3196         else
3197                 hdspm->control_register &= ~HDSPM_DS_DoubleWire;
3198         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3199 
3200         return 0;
3201 }
3202 
3203 static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol,
3204                                   struct snd_ctl_elem_info *uinfo)
3205 {
3206         static char *texts[] = { "Single", "Double" };
3207         ENUMERATED_CTL_INFO(uinfo, texts);
3208         return 0;
3209 }
3210 
3211 static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol,
3212                                  struct snd_ctl_elem_value *ucontrol)
3213 {
3214         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3215 
3216         spin_lock_irq(&hdspm->lock);
3217         ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm);
3218         spin_unlock_irq(&hdspm->lock);
3219         return 0;
3220 }
3221 
3222 static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol,
3223                                  struct snd_ctl_elem_value *ucontrol)
3224 {
3225         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3226         int change;
3227         unsigned int val;
3228 
3229         if (!snd_hdspm_use_is_exclusive(hdspm))
3230                 return -EBUSY;
3231         val = ucontrol->value.integer.value[0] & 1;
3232         spin_lock_irq(&hdspm->lock);
3233         change = (int) val != hdspm_ds_wire(hdspm);
3234         hdspm_set_ds_wire(hdspm, val);
3235         spin_unlock_irq(&hdspm->lock);
3236         return change;
3237 }
3238 
3239 
3240 #define HDSPM_QS_WIRE(xname, xindex) \
3241 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3242         .name = xname, \
3243         .index = xindex, \
3244         .info = snd_hdspm_info_qs_wire, \
3245         .get = snd_hdspm_get_qs_wire, \
3246         .put = snd_hdspm_put_qs_wire \
3247 }
3248 
3249 static int hdspm_qs_wire(struct hdspm * hdspm)
3250 {
3251         if (hdspm->control_register & HDSPM_QS_DoubleWire)
3252                 return 1;
3253         if (hdspm->control_register & HDSPM_QS_QuadWire)
3254                 return 2;
3255         return 0;
3256 }
3257 
3258 static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode)
3259 {
3260         hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire);
3261         switch (mode) {
3262         case 0:
3263                 break;
3264         case 1:
3265                 hdspm->control_register |= HDSPM_QS_DoubleWire;
3266                 break;
3267         case 2:
3268                 hdspm->control_register |= HDSPM_QS_QuadWire;
3269                 break;
3270         }
3271         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3272 
3273         return 0;
3274 }
3275 
3276 static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol,
3277                                        struct snd_ctl_elem_info *uinfo)
3278 {
3279         static char *texts[] = { "Single", "Double", "Quad" };
3280         ENUMERATED_CTL_INFO(uinfo, texts);
3281         return 0;
3282 }
3283 
3284 static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol,
3285                                       struct snd_ctl_elem_value *ucontrol)
3286 {
3287         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3288 
3289         spin_lock_irq(&hdspm->lock);
3290         ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm);
3291         spin_unlock_irq(&hdspm->lock);
3292         return 0;
3293 }
3294 
3295 static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol,
3296                                       struct snd_ctl_elem_value *ucontrol)
3297 {
3298         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3299         int change;
3300         int val;
3301 
3302         if (!snd_hdspm_use_is_exclusive(hdspm))
3303                 return -EBUSY;
3304         val = ucontrol->value.integer.value[0];
3305         if (val < 0)
3306                 val = 0;
3307         if (val > 2)
3308                 val = 2;
3309         spin_lock_irq(&hdspm->lock);
3310         change = val != hdspm_qs_wire(hdspm);
3311         hdspm_set_qs_wire(hdspm, val);
3312         spin_unlock_irq(&hdspm->lock);
3313         return change;
3314 }
3315 
3316 #define HDSPM_MADI_SPEEDMODE(xname, xindex) \
3317 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3318         .name = xname, \
3319         .index = xindex, \
3320         .info = snd_hdspm_info_madi_speedmode, \
3321         .get = snd_hdspm_get_madi_speedmode, \
3322         .put = snd_hdspm_put_madi_speedmode \
3323 }
3324 
3325 static int hdspm_madi_speedmode(struct hdspm *hdspm)
3326 {
3327         if (hdspm->control_register & HDSPM_QuadSpeed)
3328                 return 2;
3329         if (hdspm->control_register & HDSPM_DoubleSpeed)
3330                 return 1;
3331         return 0;
3332 }
3333 
3334 static int hdspm_set_madi_speedmode(struct hdspm *hdspm, int mode)
3335 {
3336         hdspm->control_register &= ~(HDSPM_DoubleSpeed | HDSPM_QuadSpeed);
3337         switch (mode) {
3338         case 0:
3339                 break;
3340         case 1:
3341                 hdspm->control_register |= HDSPM_DoubleSpeed;
3342                 break;
3343         case 2:
3344                 hdspm->control_register |= HDSPM_QuadSpeed;
3345                 break;
3346         }
3347         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3348 
3349         return 0;
3350 }
3351 
3352 static int snd_hdspm_info_madi_speedmode(struct snd_kcontrol *kcontrol,
3353                                        struct snd_ctl_elem_info *uinfo)
3354 {
3355         static char *texts[] = { "Single", "Double", "Quad" };
3356         ENUMERATED_CTL_INFO(uinfo, texts);
3357         return 0;
3358 }
3359 
3360 static int snd_hdspm_get_madi_speedmode(struct snd_kcontrol *kcontrol,
3361                                       struct snd_ctl_elem_value *ucontrol)
3362 {
3363         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3364 
3365         spin_lock_irq(&hdspm->lock);
3366         ucontrol->value.enumerated.item[0] = hdspm_madi_speedmode(hdspm);
3367         spin_unlock_irq(&hdspm->lock);
3368         return 0;
3369 }
3370 
3371 static int snd_hdspm_put_madi_speedmode(struct snd_kcontrol *kcontrol,
3372                                       struct snd_ctl_elem_value *ucontrol)
3373 {
3374         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3375         int change;
3376         int val;
3377 
3378         if (!snd_hdspm_use_is_exclusive(hdspm))
3379                 return -EBUSY;
3380         val = ucontrol->value.integer.value[0];
3381         if (val < 0)
3382                 val = 0;
3383         if (val > 2)
3384                 val = 2;
3385         spin_lock_irq(&hdspm->lock);
3386         change = val != hdspm_madi_speedmode(hdspm);
3387         hdspm_set_madi_speedmode(hdspm, val);
3388         spin_unlock_irq(&hdspm->lock);
3389         return change;
3390 }
3391 
3392 #define HDSPM_MIXER(xname, xindex) \
3393 {       .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3394         .name = xname, \
3395         .index = xindex, \
3396         .device = 0, \
3397         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3398                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3399         .info = snd_hdspm_info_mixer, \
3400         .get = snd_hdspm_get_mixer, \
3401         .put = snd_hdspm_put_mixer \
3402 }
3403 
3404 static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol,
3405                                 struct snd_ctl_elem_info *uinfo)
3406 {
3407         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3408         uinfo->count = 3;
3409         uinfo->value.integer.min = 0;
3410         uinfo->value.integer.max = 65535;
3411         uinfo->value.integer.step = 1;
3412         return 0;
3413 }
3414 
3415 static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol,
3416                                struct snd_ctl_elem_value *ucontrol)
3417 {
3418         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3419         int source;
3420         int destination;
3421 
3422         source = ucontrol->value.integer.value[0];
3423         if (source < 0)
3424                 source = 0;
3425         else if (source >= 2 * HDSPM_MAX_CHANNELS)
3426                 source = 2 * HDSPM_MAX_CHANNELS - 1;
3427 
3428         destination = ucontrol->value.integer.value[1];
3429         if (destination < 0)
3430                 destination = 0;
3431         else if (destination >= HDSPM_MAX_CHANNELS)
3432                 destination = HDSPM_MAX_CHANNELS - 1;
3433 
3434         spin_lock_irq(&hdspm->lock);
3435         if (source >= HDSPM_MAX_CHANNELS)
3436                 ucontrol->value.integer.value[2] =
3437                     hdspm_read_pb_gain(hdspm, destination,
3438                                        source - HDSPM_MAX_CHANNELS);
3439         else
3440                 ucontrol->value.integer.value[2] =
3441                     hdspm_read_in_gain(hdspm, destination, source);
3442 
3443         spin_unlock_irq(&hdspm->lock);
3444 
3445         return 0;
3446 }
3447 
3448 static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol,
3449                                struct snd_ctl_elem_value *ucontrol)
3450 {
3451         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3452         int change;
3453         int source;
3454         int destination;
3455         int gain;
3456 
3457         if (!snd_hdspm_use_is_exclusive(hdspm))
3458                 return -EBUSY;
3459 
3460         source = ucontrol->value.integer.value[0];
3461         destination = ucontrol->value.integer.value[1];
3462 
3463         if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS)
3464                 return -1;
3465         if (destination < 0 || destination >= HDSPM_MAX_CHANNELS)
3466                 return -1;
3467 
3468         gain = ucontrol->value.integer.value[2];
3469 
3470         spin_lock_irq(&hdspm->lock);
3471 
3472         if (source >= HDSPM_MAX_CHANNELS)
3473                 change = gain != hdspm_read_pb_gain(hdspm, destination,
3474                                                     source -
3475                                                     HDSPM_MAX_CHANNELS);
3476         else
3477                 change = gain != hdspm_read_in_gain(hdspm, destination,
3478                                                     source);
3479 
3480         if (change) {
3481                 if (source >= HDSPM_MAX_CHANNELS)
3482                         hdspm_write_pb_gain(hdspm, destination,
3483                                             source - HDSPM_MAX_CHANNELS,
3484                                             gain);
3485                 else
3486                         hdspm_write_in_gain(hdspm, destination, source,
3487                                             gain);
3488         }
3489         spin_unlock_irq(&hdspm->lock);
3490 
3491         return change;
3492 }
3493 
3494 /* The simple mixer control(s) provide gain control for the
3495    basic 1:1 mappings of playback streams to output
3496    streams.
3497 */
3498 
3499 #define HDSPM_PLAYBACK_MIXER \
3500 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3501         .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \
3502                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3503         .info = snd_hdspm_info_playback_mixer, \
3504         .get = snd_hdspm_get_playback_mixer, \
3505         .put = snd_hdspm_put_playback_mixer \
3506 }
3507 
3508 static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol,
3509                                          struct snd_ctl_elem_info *uinfo)
3510 {
3511         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3512         uinfo->count = 1;
3513         uinfo->value.integer.min = 0;
3514         uinfo->value.integer.max = 64;
3515         uinfo->value.integer.step = 1;
3516         return 0;
3517 }
3518 
3519 static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol,
3520                                         struct snd_ctl_elem_value *ucontrol)
3521 {
3522         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3523         int channel;
3524 
3525         channel = ucontrol->id.index - 1;
3526 
3527         if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3528                 return -EINVAL;
3529 
3530         spin_lock_irq(&hdspm->lock);
3531         ucontrol->value.integer.value[0] =
3532           (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN;
3533         spin_unlock_irq(&hdspm->lock);
3534 
3535         return 0;
3536 }
3537 
3538 static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol,
3539                                         struct snd_ctl_elem_value *ucontrol)
3540 {
3541         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3542         int change;
3543         int channel;
3544         int gain;
3545 
3546         if (!snd_hdspm_use_is_exclusive(hdspm))
3547                 return -EBUSY;
3548 
3549         channel = ucontrol->id.index - 1;
3550 
3551         if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3552                 return -EINVAL;
3553 
3554         gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64;
3555 
3556         spin_lock_irq(&hdspm->lock);
3557         change =
3558             gain != hdspm_read_pb_gain(hdspm, channel,
3559                                        channel);
3560         if (change)
3561                 hdspm_write_pb_gain(hdspm, channel, channel,
3562                                     gain);
3563         spin_unlock_irq(&hdspm->lock);
3564         return change;
3565 }
3566 
3567 #define HDSPM_SYNC_CHECK(xname, xindex) \
3568 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3569         .name = xname, \
3570         .private_value = xindex, \
3571         .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3572         .info = snd_hdspm_info_sync_check, \
3573         .get = snd_hdspm_get_sync_check \
3574 }
3575 
3576 #define HDSPM_TCO_LOCK_CHECK(xname, xindex) \
3577 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3578         .name = xname, \
3579         .private_value = xindex, \
3580         .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3581         .info = snd_hdspm_tco_info_lock_check, \
3582         .get = snd_hdspm_get_sync_check \
3583 }
3584 
3585 
3586 
3587 static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol,
3588                                      struct snd_ctl_elem_info *uinfo)
3589 {
3590         static char *texts[] = { "No Lock", "Lock", "Sync", "N/A" };
3591         ENUMERATED_CTL_INFO(uinfo, texts);
3592         return 0;
3593 }
3594 
3595 static int snd_hdspm_tco_info_lock_check(struct snd_kcontrol *kcontrol,
3596                                      struct snd_ctl_elem_info *uinfo)
3597 {
3598         static char *texts[] = { "No Lock", "Lock" };
3599         ENUMERATED_CTL_INFO(uinfo, texts);
3600         return 0;
3601 }
3602 
3603 static int hdspm_wc_sync_check(struct hdspm *hdspm)
3604 {
3605         int status, status2;
3606 
3607         switch (hdspm->io_type) {
3608         case AES32:
3609                 status = hdspm_read(hdspm, HDSPM_statusRegister);
3610                 if (status & HDSPM_AES32_wcLock) {
3611                         if (status & HDSPM_AES32_wcSync)
3612                                 return 2;
3613                         else
3614                                 return 1;
3615                 }
3616                 return 0;
3617                 break;
3618 
3619         case MADI:
3620                 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3621                 if (status2 & HDSPM_wcLock) {
3622                         if (status2 & HDSPM_wcSync)
3623                                 return 2;
3624                         else
3625                                 return 1;
3626                 }
3627                 return 0;
3628                 break;
3629 
3630         case RayDAT:
3631         case AIO:
3632                 status = hdspm_read(hdspm, HDSPM_statusRegister);
3633 
3634                 if (status & 0x2000000)
3635                         return 2;
3636                 else if (status & 0x1000000)
3637                         return 1;
3638                 return 0;
3639 
3640                 break;
3641 
3642         case MADIface:
3643                 break;
3644         }
3645 
3646 
3647         return 3;
3648 }
3649 
3650 
3651 static int hdspm_madi_sync_check(struct hdspm *hdspm)
3652 {
3653         int status = hdspm_read(hdspm, HDSPM_statusRegister);
3654         if (status & HDSPM_madiLock) {
3655                 if (status & HDSPM_madiSync)
3656                         return 2;
3657                 else
3658                         return 1;
3659         }
3660         return 0;
3661 }
3662 
3663 
3664 static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx)
3665 {
3666         int status, lock, sync;
3667 
3668         status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3669 
3670         lock = (status & (0x1<<idx)) ? 1 : 0;
3671         sync = (status & (0x100<<idx)) ? 1 : 0;
3672 
3673         if (lock && sync)
3674                 return 2;
3675         else if (lock)
3676                 return 1;
3677         return 0;
3678 }
3679 
3680 
3681 static int hdspm_sync_in_sync_check(struct hdspm *hdspm)
3682 {
3683         int status, lock = 0, sync = 0;
3684 
3685         switch (hdspm->io_type) {
3686         case RayDAT:
3687         case AIO:
3688                 status = hdspm_read(hdspm, HDSPM_RD_STATUS_3);
3689                 lock = (status & 0x400) ? 1 : 0;
3690                 sync = (status & 0x800) ? 1 : 0;
3691                 break;
3692 
3693         case MADI:
3694                 status = hdspm_read(hdspm, HDSPM_statusRegister);
3695                 lock = (status & HDSPM_syncInLock) ? 1 : 0;
3696                 sync = (status & HDSPM_syncInSync) ? 1 : 0;
3697                 break;
3698 
3699         case AES32:
3700                 status = hdspm_read(hdspm, HDSPM_statusRegister2);
3701                 lock = (status & 0x100000) ? 1 : 0;
3702                 sync = (status & 0x200000) ? 1 : 0;
3703                 break;
3704 
3705         case MADIface:
3706                 break;
3707         }
3708 
3709         if (lock && sync)
3710                 return 2;
3711         else if (lock)
3712                 return 1;
3713 
3714         return 0;
3715 }
3716 
3717 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx)
3718 {
3719         int status2, lock, sync;
3720         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3721 
3722         lock = (status2 & (0x0080 >> idx)) ? 1 : 0;
3723         sync = (status2 & (0x8000 >> idx)) ? 1 : 0;
3724 
3725         if (sync)
3726                 return 2;
3727         else if (lock)
3728                 return 1;
3729         return 0;
3730 }
3731 
3732 static int hdspm_tco_input_check(struct hdspm *hdspm, u32 mask)
3733 {
3734         u32 status;
3735         status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3736 
3737         return (status & mask) ? 1 : 0;
3738 }
3739 
3740 
3741 static int hdspm_tco_sync_check(struct hdspm *hdspm)
3742 {
3743         int status;
3744 
3745         if (hdspm->tco) {
3746                 switch (hdspm->io_type) {
3747                 case MADI:
3748                 case AES32:
3749                         status = hdspm_read(hdspm, HDSPM_statusRegister);
3750                         if (status & HDSPM_tcoLock) {
3751                                 if (status & HDSPM_tcoSync)
3752                                         return 2;
3753                                 else
3754                                         return 1;
3755                         }
3756                         return 0;
3757 
3758                         break;
3759 
3760                 case RayDAT:
3761                 case AIO:
3762                         status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3763 
3764                         if (status & 0x8000000)
3765                                 return 2; /* Sync */
3766                         if (status & 0x4000000)
3767                                 return 1; /* Lock */
3768                         return 0; /* No signal */
3769                         break;
3770 
3771                 default:
3772                         break;
3773                 }
3774         }
3775 
3776         return 3; /* N/A */
3777 }
3778 
3779 
3780 static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol,
3781                                     struct snd_ctl_elem_value *ucontrol)
3782 {
3783         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3784         int val = -1;
3785 
3786         switch (hdspm->io_type) {
3787         case RayDAT:
3788                 switch (kcontrol->private_value) {
3789                 case 0: /* WC */
3790                         val = hdspm_wc_sync_check(hdspm); break;
3791                 case 7: /* TCO */
3792                         val = hdspm_tco_sync_check(hdspm); break;
3793                 case 8: /* SYNC IN */
3794                         val = hdspm_sync_in_sync_check(hdspm); break;
3795                 default:
3796                         val = hdspm_s1_sync_check(hdspm,
3797                                         kcontrol->private_value-1);
3798                 }
3799                 break;
3800 
3801         case AIO:
3802                 switch (kcontrol->private_value) {
3803                 case 0: /* WC */
3804                         val = hdspm_wc_sync_check(hdspm); break;
3805                 case 4: /* TCO */
3806                         val = hdspm_tco_sync_check(hdspm); break;
3807                 case 5: /* SYNC IN */
3808                         val = hdspm_sync_in_sync_check(hdspm); break;
3809                 default:
3810                         val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1);
3811                 }
3812                 break;
3813 
3814         case MADI:
3815                 switch (kcontrol->private_value) {
3816                 case 0: /* WC */
3817                         val = hdspm_wc_sync_check(hdspm); break;
3818                 case 1: /* MADI */
3819                         val = hdspm_madi_sync_check(hdspm); break;
3820                 case 2: /* TCO */
3821                         val = hdspm_tco_sync_check(hdspm); break;
3822                 case 3: /* SYNC_IN */
3823                         val = hdspm_sync_in_sync_check(hdspm); break;
3824                 }
3825                 break;
3826 
3827         case MADIface:
3828                 val = hdspm_madi_sync_check(hdspm); /* MADI */
3829                 break;
3830 
3831         case AES32:
3832                 switch (kcontrol->private_value) {
3833                 case 0: /* WC */
3834                         val = hdspm_wc_sync_check(hdspm); break;
3835                 case 9: /* TCO */
3836                         val = hdspm_tco_sync_check(hdspm); break;
3837                 case 10 /* SYNC IN */:
3838                         val = hdspm_sync_in_sync_check(hdspm); break;
3839                 default: /* AES1 to AES8 */
3840                          val = hdspm_aes_sync_check(hdspm,
3841                                          kcontrol->private_value-1);
3842                 }
3843                 break;
3844 
3845         }
3846 
3847         if (hdspm->tco) {
3848                 switch (kcontrol->private_value) {
3849                 case 11:
3850                         /* Check TCO for lock state of its current input */
3851                         val = hdspm_tco_input_check(hdspm, HDSPM_TCO1_TCO_lock);
3852                         break;
3853                 case 12:
3854                         /* Check TCO for valid time code on LTC input. */
3855                         val = hdspm_tco_input_check(hdspm,
3856                                 HDSPM_TCO1_LTC_Input_valid);
3857                         break;
3858                 default:
3859                         break;
3860                 }
3861         }
3862 
3863         if (-1 == val)
3864                 val = 3;
3865 
3866         ucontrol->value.enumerated.item[0] = val;
3867         return 0;
3868 }
3869 
3870 
3871 
3872 /**
3873  * TCO controls
3874  **/
3875 static void hdspm_tco_write(struct hdspm *hdspm)
3876 {
3877         unsigned int tc[4] = { 0, 0, 0, 0};
3878 
3879         switch (hdspm->tco->input) {
3880         case 0:
3881                 tc[2] |= HDSPM_TCO2_set_input_MSB;
3882                 break;
3883         case 1:
3884                 tc[2] |= HDSPM_TCO2_set_input_LSB;
3885                 break;
3886         default:
3887                 break;
3888         }
3889 
3890         switch (hdspm->tco->framerate) {
3891         case 1:
3892                 tc[1] |= HDSPM_TCO1_LTC_Format_LSB;
3893                 break;
3894         case 2:
3895                 tc[1] |= HDSPM_TCO1_LTC_Format_MSB;
3896                 break;
3897         case 3:
3898                 tc[1] |= HDSPM_TCO1_LTC_Format_MSB +
3899                         HDSPM_TCO1_set_drop_frame_flag;
3900                 break;
3901         case 4:
3902                 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
3903                         HDSPM_TCO1_LTC_Format_MSB;
3904                 break;
3905         case 5:
3906                 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
3907                         HDSPM_TCO1_LTC_Format_MSB +
3908                         HDSPM_TCO1_set_drop_frame_flag;
3909                 break;
3910         default:
3911                 break;
3912         }
3913 
3914         switch (hdspm->tco->wordclock) {
3915         case 1:
3916                 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB;
3917                 break;
3918         case 2:
3919                 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB;
3920                 break;
3921         default:
3922                 break;
3923         }
3924 
3925         switch (hdspm->tco->samplerate) {
3926         case 1:
3927                 tc[2] |= HDSPM_TCO2_set_freq;
3928                 break;
3929         case 2:
3930                 tc[2] |= HDSPM_TCO2_set_freq_from_app;
3931                 break;
3932         default:
3933                 break;
3934         }
3935 
3936         switch (hdspm->tco->pull) {
3937         case 1:
3938                 tc[2] |= HDSPM_TCO2_set_pull_up;
3939                 break;
3940         case 2:
3941                 tc[2] |= HDSPM_TCO2_set_pull_down;
3942                 break;
3943         case 3:
3944                 tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4;
3945                 break;
3946         case 4:
3947                 tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4;
3948                 break;
3949         default:
3950                 break;
3951         }
3952 
3953         if (1 == hdspm->tco->term) {
3954                 tc[2] |= HDSPM_TCO2_set_term_75R;
3955         }
3956 
3957         hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]);
3958         hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]);
3959         hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]);
3960         hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]);
3961 }
3962 
3963 
3964 #define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \
3965 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3966         .name = xname, \
3967         .index = xindex, \
3968         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
3969                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3970         .info = snd_hdspm_info_tco_sample_rate, \
3971         .get = snd_hdspm_get_tco_sample_rate, \
3972         .put = snd_hdspm_put_tco_sample_rate \
3973 }
3974 
3975 static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol,
3976                                           struct snd_ctl_elem_info *uinfo)
3977 {
3978         static char *texts[] = { "44.1 kHz", "48 kHz" };
3979         ENUMERATED_CTL_INFO(uinfo, texts);
3980         return 0;
3981 }
3982 
3983 static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol,
3984                                       struct snd_ctl_elem_value *ucontrol)
3985 {
3986         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3987 
3988         ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate;
3989 
3990         return 0;
3991 }
3992 
3993 static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol,
3994                                          struct snd_ctl_elem_value *ucontrol)
3995 {
3996         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3997 
3998         if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) {
3999                 hdspm->tco->samplerate = ucontrol->value.enumerated.item[0];
4000 
4001                 hdspm_tco_write(hdspm);
4002 
4003                 return 1;
4004         }
4005 
4006         return 0;
4007 }
4008 
4009 
4010 #define HDSPM_TCO_PULL(xname, xindex) \
4011 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4012         .name = xname, \
4013         .index = xindex, \
4014         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4015                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4016         .info = snd_hdspm_info_tco_pull, \
4017         .get = snd_hdspm_get_tco_pull, \
4018         .put = snd_hdspm_put_tco_pull \
4019 }
4020 
4021 static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol,
4022                                    struct snd_ctl_elem_info *uinfo)
4023 {
4024         static char *texts[] = { "", "+ 0.1 %", "- 0.1 %", "+ 4 %", "- 4 %" };
4025         ENUMERATED_CTL_INFO(uinfo, texts);
4026         return 0;
4027 }
4028 
4029 static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol,
4030                                   struct snd_ctl_elem_value *ucontrol)
4031 {
4032         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4033 
4034         ucontrol->value.enumerated.item[0] = hdspm->tco->pull;
4035 
4036         return 0;
4037 }
4038 
4039 static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol,
4040                                   struct snd_ctl_elem_value *ucontrol)
4041 {
4042         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4043 
4044         if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) {
4045                 hdspm->tco->pull = ucontrol->value.enumerated.item[0];
4046 
4047                 hdspm_tco_write(hdspm);
4048 
4049                 return 1;
4050         }
4051 
4052         return 0;
4053 }
4054 
4055 #define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \
4056 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4057         .name = xname, \
4058         .index = xindex, \
4059         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4060                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4061         .info = snd_hdspm_info_tco_wck_conversion, \
4062         .get = snd_hdspm_get_tco_wck_conversion, \
4063         .put = snd_hdspm_put_tco_wck_conversion \
4064 }
4065 
4066 static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4067                                              struct snd_ctl_elem_info *uinfo)
4068 {
4069         static char *texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" };
4070         ENUMERATED_CTL_INFO(uinfo, texts);
4071         return 0;
4072 }
4073 
4074 static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4075                                             struct snd_ctl_elem_value *ucontrol)
4076 {
4077         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4078 
4079         ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock;
4080 
4081         return 0;
4082 }
4083 
4084 static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4085                                             struct snd_ctl_elem_value *ucontrol)
4086 {
4087         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4088 
4089         if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) {
4090                 hdspm->tco->wordclock = ucontrol->value.enumerated.item[0];
4091 
4092                 hdspm_tco_write(hdspm);
4093 
4094                 return 1;
4095         }
4096 
4097         return 0;
4098 }
4099 
4100 
4101 #define HDSPM_TCO_FRAME_RATE(xname, xindex) \
4102 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4103         .name = xname, \
4104         .index = xindex, \
4105         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4106                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4107         .info = snd_hdspm_info_tco_frame_rate, \
4108         .get = snd_hdspm_get_tco_frame_rate, \
4109         .put = snd_hdspm_put_tco_frame_rate \
4110 }
4111 
4112 static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol,
4113                                           struct snd_ctl_elem_info *uinfo)
4114 {
4115         static char *texts[] = { "24 fps", "25 fps", "29.97fps",
4116                 "29.97 dfps", "30 fps", "30 dfps" };
4117         ENUMERATED_CTL_INFO(uinfo, texts);
4118         return 0;
4119 }
4120 
4121 static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol,
4122                                         struct snd_ctl_elem_value *ucontrol)
4123 {
4124         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4125 
4126         ucontrol->value.enumerated.item[0] = hdspm->tco->framerate;
4127 
4128         return 0;
4129 }
4130 
4131 static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol,
4132                                         struct snd_ctl_elem_value *ucontrol)
4133 {
4134         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4135 
4136         if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) {
4137                 hdspm->tco->framerate = ucontrol->value.enumerated.item[0];
4138 
4139                 hdspm_tco_write(hdspm);
4140 
4141                 return 1;
4142         }
4143 
4144         return 0;
4145 }
4146 
4147 
4148 #define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \
4149 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4150         .name = xname, \
4151         .index = xindex, \
4152         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4153                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4154         .info = snd_hdspm_info_tco_sync_source, \
4155         .get = snd_hdspm_get_tco_sync_source, \
4156         .put = snd_hdspm_put_tco_sync_source \
4157 }
4158 
4159 static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol,
4160                                           struct snd_ctl_elem_info *uinfo)
4161 {
4162         static char *texts[] = { "LTC", "Video", "WCK" };
4163         ENUMERATED_CTL_INFO(uinfo, texts);
4164         return 0;
4165 }
4166 
4167 static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol,
4168                                          struct snd_ctl_elem_value *ucontrol)
4169 {
4170         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4171 
4172         ucontrol->value.enumerated.item[0] = hdspm->tco->input;
4173 
4174         return 0;
4175 }
4176 
4177 static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol,
4178                                          struct snd_ctl_elem_value *ucontrol)
4179 {
4180         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4181 
4182         if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) {
4183                 hdspm->tco->input = ucontrol->value.enumerated.item[0];
4184 
4185                 hdspm_tco_write(hdspm);
4186 
4187                 return 1;
4188         }
4189 
4190         return 0;
4191 }
4192 
4193 
4194 #define HDSPM_TCO_WORD_TERM(xname, xindex) \
4195 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4196         .name = xname, \
4197         .index = xindex, \
4198         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4199                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4200         .info = snd_hdspm_info_tco_word_term, \
4201         .get = snd_hdspm_get_tco_word_term, \
4202         .put = snd_hdspm_put_tco_word_term \
4203 }
4204 
4205 static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol,
4206                                         struct snd_ctl_elem_info *uinfo)
4207 {
4208         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
4209         uinfo->count = 1;
4210         uinfo->value.integer.min = 0;
4211         uinfo->value.integer.max = 1;
4212 
4213         return 0;
4214 }
4215 
4216 
4217 static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol,
4218                                        struct snd_ctl_elem_value *ucontrol)
4219 {
4220         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4221 
4222         ucontrol->value.enumerated.item[0] = hdspm->tco->term;
4223 
4224         return 0;
4225 }
4226 
4227 
4228 static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol,
4229                                        struct snd_ctl_elem_value *ucontrol)
4230 {
4231         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4232 
4233         if (hdspm->tco->term != ucontrol->value.enumerated.item[0]) {
4234                 hdspm->tco->term = ucontrol->value.enumerated.item[0];
4235 
4236                 hdspm_tco_write(hdspm);
4237 
4238                 return 1;
4239         }
4240 
4241         return 0;
4242 }
4243 
4244 
4245 
4246 
4247 static struct snd_kcontrol_new snd_hdspm_controls_madi[] = {
4248         HDSPM_MIXER("Mixer", 0),
4249         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4250         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4251         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4252         HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4253         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4254         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4255         HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4256         HDSPM_SYNC_CHECK("MADI SyncCheck", 1),
4257         HDSPM_SYNC_CHECK("TCO SyncCheck", 2),
4258         HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3),
4259         HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut),
4260         HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch),
4261         HDSPM_TOGGLE_SETTING("Disable 96K frames", HDSPM_SMUX),
4262         HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
4263         HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp),
4264         HDSPM_INPUT_SELECT("Input Select", 0),
4265         HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4266 };
4267 
4268 
4269 static struct snd_kcontrol_new snd_hdspm_controls_madiface[] = {
4270         HDSPM_MIXER("Mixer", 0),
4271         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4272         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4273         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4274         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4275         HDSPM_SYNC_CHECK("MADI SyncCheck", 0),
4276         HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch),
4277         HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
4278         HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp),
4279         HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4280 };
4281 
4282 static struct snd_kcontrol_new snd_hdspm_controls_aio[] = {
4283         HDSPM_MIXER("Mixer", 0),
4284         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4285         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4286         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4287         HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4288         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4289         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4290         HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4291         HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4292         HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4293         HDSPM_SYNC_CHECK("ADAT SyncCheck", 3),
4294         HDSPM_SYNC_CHECK("TCO SyncCheck", 4),
4295         HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5),
4296         HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4297         HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4298         HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4299         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3),
4300         HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4),
4301         HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5)
4302 
4303                 /*
4304                    HDSPM_INPUT_SELECT("Input Select", 0),
4305                    HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0),
4306                    HDSPM_PROFESSIONAL("SPDIF Out Professional", 0);
4307                    HDSPM_SPDIF_IN("SPDIF In", 0);
4308                    HDSPM_BREAKOUT_CABLE("Breakout Cable", 0);
4309                    HDSPM_INPUT_LEVEL("Input Level", 0);
4310                    HDSPM_OUTPUT_LEVEL("Output Level", 0);
4311                    HDSPM_PHONES("Phones", 0);
4312                    */
4313 };
4314 
4315 static struct snd_kcontrol_new snd_hdspm_controls_raydat[] = {
4316         HDSPM_MIXER("Mixer", 0),
4317         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4318         HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0),
4319         HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0),
4320         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4321         HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4322         HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4323         HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4324         HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3),
4325         HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4),
4326         HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5),
4327         HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6),
4328         HDSPM_SYNC_CHECK("TCO SyncCheck", 7),
4329         HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8),
4330         HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4331         HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4332         HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4333         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3),
4334         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4),
4335         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5),
4336         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6),
4337         HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7),
4338         HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8)
4339 };
4340 
4341 static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = {
4342         HDSPM_MIXER("Mixer", 0),
4343         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4344         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4345         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4346         HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4347         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4348         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4349         HDSPM_SYNC_CHECK("WC Sync Check", 0),
4350         HDSPM_SYNC_CHECK("AES1 Sync Check", 1),
4351         HDSPM_SYNC_CHECK("AES2 Sync Check", 2),
4352         HDSPM_SYNC_CHECK("AES3 Sync Check", 3),
4353         HDSPM_SYNC_CHECK("AES4 Sync Check", 4),
4354         HDSPM_SYNC_CHECK("AES5 Sync Check", 5),
4355         HDSPM_SYNC_CHECK("AES6 Sync Check", 6),
4356         HDSPM_SYNC_CHECK("AES7 Sync Check", 7),
4357         HDSPM_SYNC_CHECK("AES8 Sync Check", 8),
4358         HDSPM_SYNC_CHECK("TCO Sync Check", 9),
4359         HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10),
4360         HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4361         HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1),
4362         HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2),
4363         HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3),
4364         HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4),
4365         HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5),
4366         HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6),
4367         HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7),
4368         HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8),
4369         HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9),
4370         HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10),
4371         HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut),
4372         HDSPM_TOGGLE_SETTING("Emphasis", HDSPM_Emphasis),
4373         HDSPM_TOGGLE_SETTING("Non Audio", HDSPM_Dolby),
4374         HDSPM_TOGGLE_SETTING("Professional", HDSPM_Professional),
4375         HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
4376         HDSPM_DS_WIRE("Double Speed Wire Mode", 0),
4377         HDSPM_QS_WIRE("Quad Speed Wire Mode", 0),
4378 };
4379 
4380 
4381 
4382 /* Control elements for the optional TCO module */
4383 static struct snd_kcontrol_new snd_hdspm_controls_tco[] = {
4384         HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0),
4385         HDSPM_TCO_PULL("TCO Pull", 0),
4386         HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0),
4387         HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0),
4388         HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0),
4389         HDSPM_TCO_WORD_TERM("TCO Word Term", 0),
4390         HDSPM_TCO_LOCK_CHECK("TCO Input Check", 11),
4391         HDSPM_TCO_LOCK_CHECK("TCO LTC Valid", 12),
4392         HDSPM_TCO_LTC_FRAMES("TCO Detected Frame Rate", 0),
4393         HDSPM_TCO_VIDEO_INPUT_FORMAT("Video Input Format", 0)
4394 };
4395 
4396 
4397 static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER;
4398 
4399 
4400 static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm)
4401 {
4402         int i;
4403 
4404         for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) {
4405                 if (hdspm->system_sample_rate > 48000) {
4406                         hdspm->playback_mixer_ctls[i]->vd[0].access =
4407                                 SNDRV_CTL_ELEM_ACCESS_INACTIVE |
4408                                 SNDRV_CTL_ELEM_ACCESS_READ |
4409                                 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4410                 } else {
4411                         hdspm->playback_mixer_ctls[i]->vd[0].access =
4412                                 SNDRV_CTL_ELEM_ACCESS_READWRITE |
4413                                 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4414                 }
4415                 snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE |
4416                                 SNDRV_CTL_EVENT_MASK_INFO,
4417                                 &hdspm->playback_mixer_ctls[i]->id);
4418         }
4419 
4420         return 0;
4421 }
4422 
4423 
4424 static int snd_hdspm_create_controls(struct snd_card *card,
4425                                         struct hdspm *hdspm)
4426 {
4427         unsigned int idx, limit;
4428         int err;
4429         struct snd_kcontrol *kctl;
4430         struct snd_kcontrol_new *list = NULL;
4431 
4432         switch (hdspm->io_type) {
4433         case MADI:
4434                 list = snd_hdspm_controls_madi;
4435                 limit = ARRAY_SIZE(snd_hdspm_controls_madi);
4436                 break;
4437         case MADIface:
4438                 list = snd_hdspm_controls_madiface;
4439                 limit = ARRAY_SIZE(snd_hdspm_controls_madiface);
4440                 break;
4441         case AIO:
4442                 list = snd_hdspm_controls_aio;
4443                 limit = ARRAY_SIZE(snd_hdspm_controls_aio);
4444                 break;
4445         case RayDAT:
4446                 list = snd_hdspm_controls_raydat;
4447                 limit = ARRAY_SIZE(snd_hdspm_controls_raydat);
4448                 break;
4449         case AES32:
4450                 list = snd_hdspm_controls_aes32;
4451                 limit = ARRAY_SIZE(snd_hdspm_controls_aes32);
4452                 break;
4453         }
4454 
4455         if (NULL != list) {
4456                 for (idx = 0; idx < limit; idx++) {
4457                         err = snd_ctl_add(card,
4458                                         snd_ctl_new1(&list[idx], hdspm));
4459                         if (err < 0)
4460                                 return err;
4461                 }
4462         }
4463 
4464 
4465         /* create simple 1:1 playback mixer controls */
4466         snd_hdspm_playback_mixer.name = "Chn";
4467         if (hdspm->system_sample_rate >= 128000) {
4468                 limit = hdspm->qs_out_channels;
4469         } else if (hdspm->system_sample_rate >= 64000) {
4470                 limit = hdspm->ds_out_channels;
4471         } else {
4472                 limit = hdspm->ss_out_channels;
4473         }
4474         for (idx = 0; idx < limit; ++idx) {
4475                 snd_hdspm_playback_mixer.index = idx + 1;
4476                 kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm);
4477                 err = snd_ctl_add(card, kctl);
4478                 if (err < 0)
4479                         return err;
4480                 hdspm->playback_mixer_ctls[idx] = kctl;
4481         }
4482 
4483 
4484         if (hdspm->tco) {
4485                 /* add tco control elements */
4486                 list = snd_hdspm_controls_tco;
4487                 limit = ARRAY_SIZE(snd_hdspm_controls_tco);
4488                 for (idx = 0; idx < limit; idx++) {
4489                         err = snd_ctl_add(card,
4490                                         snd_ctl_new1(&list[idx], hdspm));
4491                         if (err < 0)
4492                                 return err;
4493                 }
4494         }
4495 
4496         return 0;
4497 }
4498 
4499 /*------------------------------------------------------------
4500    /proc interface
4501  ------------------------------------------------------------*/
4502 
4503 static void
4504 snd_hdspm_proc_read_madi(struct snd_info_entry * entry,
4505                          struct snd_info_buffer *buffer)
4506 {
4507         struct hdspm *hdspm = entry->private_data;
4508         unsigned int status, status2, control, freq;
4509 
4510         char *pref_sync_ref;
4511         char *autosync_ref;
4512         char *system_clock_mode;
4513         char *insel;
4514         int x, x2;
4515 
4516         /* TCO stuff */
4517         int a, ltc, frames, seconds, minutes, hours;
4518         unsigned int period;
4519         u64 freq_const = 0;
4520         u32 rate;
4521 
4522         status = hdspm_read(hdspm, HDSPM_statusRegister);
4523         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4524         control = hdspm->control_register;
4525         freq = hdspm_read(hdspm, HDSPM_timecodeRegister);
4526 
4527         snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n",
4528                         hdspm->card_name, hdspm->card->number + 1,
4529                         hdspm->firmware_rev,
4530                         (status2 & HDSPM_version0) |
4531                         (status2 & HDSPM_version1) | (status2 &
4532                                 HDSPM_version2));
4533 
4534         snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n",
4535                         (hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF,
4536                         hdspm->serial);
4537 
4538         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4539                         hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4540 
4541         snd_iprintf(buffer, "--- System ---\n");
4542 
4543         snd_iprintf(buffer,
4544                 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4545                 status & HDSPM_audioIRQPending,
4546                 (status & HDSPM_midi0IRQPending) ? 1 : 0,
4547                 (status & HDSPM_midi1IRQPending) ? 1 : 0,
4548                 hdspm->irq_count);
4549         snd_iprintf(buffer,
4550                 "HW pointer: id = %d, rawptr = %d (%d->%d) "
4551                 "estimated= %ld (bytes)\n",
4552                 ((status & HDSPM_BufferID) ? 1 : 0),
4553                 (status & HDSPM_BufferPositionMask),
4554                 (status & HDSPM_BufferPositionMask) %
4555                 (2 * (int)hdspm->period_bytes),
4556                 ((status & HDSPM_BufferPositionMask) - 64) %
4557                 (2 * (int)hdspm->period_bytes),
4558                 (long) hdspm_hw_pointer(hdspm) * 4);
4559 
4560         snd_iprintf(buffer,
4561                 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
4562                 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
4563                 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
4564                 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
4565                 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
4566         snd_iprintf(buffer,
4567                 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
4568                 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
4569                 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
4570         snd_iprintf(buffer,
4571                 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
4572                 "status2=0x%x\n",
4573                 hdspm->control_register, hdspm->control2_register,
4574                 status, status2);
4575         if (status & HDSPM_tco_detect) {
4576                 snd_iprintf(buffer, "TCO module detected.\n");
4577                 a = hdspm_read(hdspm, HDSPM_RD_TCO+4);
4578                 if (a & HDSPM_TCO1_LTC_Input_valid) {
4579                         snd_iprintf(buffer, "  LTC valid, ");
4580                         switch (a & (HDSPM_TCO1_LTC_Format_LSB |
4581                                                 HDSPM_TCO1_LTC_Format_MSB)) {
4582                         case 0:
4583                                 snd_iprintf(buffer, "24 fps, ");
4584                                 break;
4585                         case HDSPM_TCO1_LTC_Format_LSB:
4586                                 snd_iprintf(buffer, "25 fps, ");
4587                                 break;
4588                         case HDSPM_TCO1_LTC_Format_MSB:
4589                                 snd_iprintf(buffer, "29.97 fps, ");
4590                                 break;
4591                         default:
4592                                 snd_iprintf(buffer, "30 fps, ");
4593                                 break;
4594                         }
4595                         if (a & HDSPM_TCO1_set_drop_frame_flag) {
4596                                 snd_iprintf(buffer, "drop frame\n");
4597                         } else {
4598                                 snd_iprintf(buffer, "full frame\n");
4599                         }
4600                 } else {
4601                         snd_iprintf(buffer, "  no LTC\n");
4602                 }
4603                 if (a & HDSPM_TCO1_Video_Input_Format_NTSC) {
4604                         snd_iprintf(buffer, "  Video: NTSC\n");
4605                 } else if (a & HDSPM_TCO1_Video_Input_Format_PAL) {
4606                         snd_iprintf(buffer, "  Video: PAL\n");
4607                 } else {
4608                         snd_iprintf(buffer, "  No video\n");
4609                 }
4610                 if (a & HDSPM_TCO1_TCO_lock) {
4611                         snd_iprintf(buffer, "  Sync: lock\n");
4612                 } else {
4613                         snd_iprintf(buffer, "  Sync: no lock\n");
4614                 }
4615 
4616                 switch (hdspm->io_type) {
4617                 case MADI:
4618                 case AES32:
4619                         freq_const = 110069313433624ULL;
4620                         break;
4621                 case RayDAT:
4622                 case AIO:
4623                         freq_const = 104857600000000ULL;
4624                         break;
4625                 case MADIface:
4626                         break; /* no TCO possible */
4627                 }
4628 
4629                 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
4630                 snd_iprintf(buffer, "    period: %u\n", period);
4631 
4632 
4633                 /* rate = freq_const/period; */
4634                 rate = div_u64(freq_const, period);
4635 
4636                 if (control & HDSPM_QuadSpeed) {
4637                         rate *= 4;
4638                 } else if (control & HDSPM_DoubleSpeed) {
4639                         rate *= 2;
4640                 }
4641 
4642                 snd_iprintf(buffer, "  Frequency: %u Hz\n",
4643                                 (unsigned int) rate);
4644 
4645                 ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
4646                 frames = ltc & 0xF;
4647                 ltc >>= 4;
4648                 frames += (ltc & 0x3) * 10;
4649                 ltc >>= 4;
4650                 seconds = ltc & 0xF;
4651                 ltc >>= 4;
4652                 seconds += (ltc & 0x7) * 10;
4653                 ltc >>= 4;
4654                 minutes = ltc & 0xF;
4655                 ltc >>= 4;
4656                 minutes += (ltc & 0x7) * 10;
4657                 ltc >>= 4;
4658                 hours = ltc & 0xF;
4659                 ltc >>= 4;
4660                 hours += (ltc & 0x3) * 10;
4661                 snd_iprintf(buffer,
4662                         "  LTC In: %02d:%02d:%02d:%02d\n",
4663                         hours, minutes, seconds, frames);
4664 
4665         } else {
4666                 snd_iprintf(buffer, "No TCO module detected.\n");
4667         }
4668 
4669         snd_iprintf(buffer, "--- Settings ---\n");
4670 
4671         x = hdspm_get_latency(hdspm);
4672 
4673         snd_iprintf(buffer,
4674                 "Size (Latency): %d samples (2 periods of %lu bytes)\n",
4675                 x, (unsigned long) hdspm->period_bytes);
4676 
4677         snd_iprintf(buffer, "Line out: %s\n",
4678                 (hdspm->control_register & HDSPM_LineOut) ? "on " : "off");
4679 
4680         switch (hdspm->control_register & HDSPM_InputMask) {
4681         case HDSPM_InputOptical:
4682                 insel = "Optical";
4683                 break;
4684         case HDSPM_InputCoaxial:
4685                 insel = "Coaxial";
4686                 break;
4687         default:
4688                 insel = "Unknown";
4689         }
4690 
4691         snd_iprintf(buffer,
4692                 "ClearTrackMarker = %s, Transmit in %s Channel Mode, "
4693                 "Auto Input %s\n",
4694                 (hdspm->control_register & HDSPM_clr_tms) ? "on" : "off",
4695                 (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56",
4696                 (hdspm->control_register & HDSPM_AutoInp) ? "on" : "off");
4697 
4698 
4699         if (!(hdspm->control_register & HDSPM_ClockModeMaster))
4700                 system_clock_mode = "AutoSync";
4701         else
4702                 system_clock_mode = "Master";
4703         snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode);
4704 
4705         switch (hdspm_pref_sync_ref(hdspm)) {
4706         case HDSPM_SYNC_FROM_WORD:
4707                 pref_sync_ref = "Word Clock";
4708                 break;
4709         case HDSPM_SYNC_FROM_MADI:
4710                 pref_sync_ref = "MADI Sync";
4711                 break;
4712         case HDSPM_SYNC_FROM_TCO:
4713                 pref_sync_ref = "TCO";
4714                 break;
4715         case HDSPM_SYNC_FROM_SYNC_IN:
4716                 pref_sync_ref = "Sync In";
4717                 break;
4718         default:
4719                 pref_sync_ref = "XXXX Clock";
4720                 break;
4721         }
4722         snd_iprintf(buffer, "Preferred Sync Reference: %s\n",
4723                         pref_sync_ref);
4724 
4725         snd_iprintf(buffer, "System Clock Frequency: %d\n",
4726                         hdspm->system_sample_rate);
4727 
4728 
4729         snd_iprintf(buffer, "--- Status:\n");
4730 
4731         x = status & HDSPM_madiSync;
4732         x2 = status2 & HDSPM_wcSync;
4733 
4734         snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n",
4735                         (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") :
4736                         "NoLock",
4737                         (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") :
4738                         "NoLock");
4739 
4740         switch (hdspm_autosync_ref(hdspm)) {
4741         case HDSPM_AUTOSYNC_FROM_SYNC_IN:
4742                 autosync_ref = "Sync In";
4743                 break;
4744         case HDSPM_AUTOSYNC_FROM_TCO:
4745                 autosync_ref = "TCO";
4746                 break;
4747         case HDSPM_AUTOSYNC_FROM_WORD:
4748                 autosync_ref = "Word Clock";
4749                 break;
4750         case HDSPM_AUTOSYNC_FROM_MADI:
4751                 autosync_ref = "MADI Sync";
4752                 break;
4753         case HDSPM_AUTOSYNC_FROM_NONE:
4754                 autosync_ref = "Input not valid";
4755                 break;
4756         default:
4757                 autosync_ref = "---";
4758                 break;
4759         }
4760         snd_iprintf(buffer,
4761                 "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n",
4762                 autosync_ref, hdspm_external_sample_rate(hdspm),
4763                 (status & HDSPM_madiFreqMask) >> 22,
4764                 (status2 & HDSPM_wcFreqMask) >> 5);
4765 
4766         snd_iprintf(buffer, "Input: %s, Mode=%s\n",
4767                 (status & HDSPM_AB_int) ? "Coax" : "Optical",
4768                 (status & HDSPM_RX_64ch) ? "64 channels" :
4769                 "56 channels");
4770 
4771         snd_iprintf(buffer, "\n");
4772 }
4773 
4774 static void
4775 snd_hdspm_proc_read_aes32(struct snd_info_entry * entry,
4776                           struct snd_info_buffer *buffer)
4777 {
4778         struct hdspm *hdspm = entry->private_data;
4779         unsigned int status;
4780         unsigned int status2;
4781         unsigned int timecode;
4782         unsigned int wcLock, wcSync;
4783         int pref_syncref;
4784         char *autosync_ref;
4785         int x;
4786 
4787         status = hdspm_read(hdspm, HDSPM_statusRegister);
4788         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4789         timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
4790 
4791         snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n",
4792                     hdspm->card_name, hdspm->card->number + 1,
4793                     hdspm->firmware_rev);
4794 
4795         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4796                     hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4797 
4798         snd_iprintf(buffer, "--- System ---\n");
4799 
4800         snd_iprintf(buffer,
4801                     "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4802                     status & HDSPM_audioIRQPending,
4803                     (status & HDSPM_midi0IRQPending) ? 1 : 0,
4804                     (status & HDSPM_midi1IRQPending) ? 1 : 0,
4805                     hdspm->irq_count);
4806         snd_iprintf(buffer,
4807                     "HW pointer: id = %d, rawptr = %d (%d->%d) "
4808                     "estimated= %ld (bytes)\n",
4809                     ((status & HDSPM_BufferID) ? 1 : 0),
4810                     (status & HDSPM_BufferPositionMask),
4811                     (status & HDSPM_BufferPositionMask) %
4812                     (2 * (int)hdspm->period_bytes),
4813                     ((status & HDSPM_BufferPositionMask) - 64) %
4814                     (2 * (int)hdspm->period_bytes),
4815                     (long) hdspm_hw_pointer(hdspm) * 4);
4816 
4817         snd_iprintf(buffer,
4818                     "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
4819                     hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
4820                     hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
4821                     hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
4822                     hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
4823         snd_iprintf(buffer,
4824                     "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
4825                     hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
4826                     hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
4827         snd_iprintf(buffer,
4828                     "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
4829                     "status2=0x%x\n",
4830                     hdspm->control_register, hdspm->control2_register,
4831                     status, status2);
4832 
4833         snd_iprintf(buffer, "--- Settings ---\n");
4834 
4835         x = hdspm_get_latency(hdspm);
4836 
4837         snd_iprintf(buffer,
4838                     "Size (Latency): %d samples (2 periods of %lu bytes)\n",
4839                     x, (unsigned long) hdspm->period_bytes);
4840 
4841         snd_iprintf(buffer, "Line out: %s\n",
4842                     (hdspm->
4843                      control_register & HDSPM_LineOut) ? "on " : "off");
4844 
4845         snd_iprintf(buffer,
4846                     "ClearTrackMarker %s, Emphasis %s, Dolby %s\n",
4847                     (hdspm->
4848                      control_register & HDSPM_clr_tms) ? "on" : "off",
4849                     (hdspm->
4850                      control_register & HDSPM_Emphasis) ? "on" : "off",
4851                     (hdspm->
4852                      control_register & HDSPM_Dolby) ? "on" : "off");
4853 
4854 
4855         pref_syncref = hdspm_pref_sync_ref(hdspm);
4856         if (pref_syncref == 0)
4857                 snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n");
4858         else
4859                 snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n",
4860                                 pref_syncref);
4861 
4862         snd_iprintf(buffer, "System Clock Frequency: %d\n",
4863                     hdspm->system_sample_rate);
4864 
4865         snd_iprintf(buffer, "Double speed: %s\n",
4866                         hdspm->control_register & HDSPM_DS_DoubleWire?
4867                         "Double wire" : "Single wire");
4868         snd_iprintf(buffer, "Quad speed: %s\n",
4869                         hdspm->control_register & HDSPM_QS_DoubleWire?
4870                         "Double wire" :
4871                         hdspm->control_register & HDSPM_QS_QuadWire?
4872                         "Quad wire" : "Single wire");
4873 
4874         snd_iprintf(buffer, "--- Status:\n");
4875 
4876         wcLock = status & HDSPM_AES32_wcLock;
4877         wcSync = wcLock && (status & HDSPM_AES32_wcSync);
4878 
4879         snd_iprintf(buffer, "Word: %s  Frequency: %d\n",
4880                     (wcLock) ? (wcSync ? "Sync   " : "Lock   ") : "No Lock",
4881                     HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF));
4882 
4883         for (x = 0; x < 8; x++) {
4884                 snd_iprintf(buffer, "AES%d: %s  Frequency: %d\n",
4885                             x+1,
4886                             (status2 & (HDSPM_LockAES >> x)) ?
4887                             "Sync   " : "No Lock",
4888                             HDSPM_bit2freq((timecode >> (4*x)) & 0xF));
4889         }
4890 
4891         switch (hdspm_autosync_ref(hdspm)) {
4892         case HDSPM_AES32_AUTOSYNC_FROM_NONE:
4893                 autosync_ref = "None"; break;
4894         case HDSPM_AES32_AUTOSYNC_FROM_WORD:
4895                 autosync_ref = "Word Clock"; break;
4896         case HDSPM_AES32_AUTOSYNC_FROM_AES1:
4897                 autosync_ref = "AES1"; break;
4898         case HDSPM_AES32_AUTOSYNC_FROM_AES2:
4899                 autosync_ref = "AES2"; break;
4900         case HDSPM_AES32_AUTOSYNC_FROM_AES3:
4901                 autosync_ref = "AES3"; break;
4902         case HDSPM_AES32_AUTOSYNC_FROM_AES4:
4903                 autosync_ref = "AES4"; break;
4904         case HDSPM_AES32_AUTOSYNC_FROM_AES5:
4905                 autosync_ref = "AES5"; break;
4906         case HDSPM_AES32_AUTOSYNC_FROM_AES6:
4907                 autosync_ref = "AES6"; break;
4908         case HDSPM_AES32_AUTOSYNC_FROM_AES7:
4909                 autosync_ref = "AES7"; break;
4910         case HDSPM_AES32_AUTOSYNC_FROM_AES8:
4911                 autosync_ref = "AES8"; break;
4912         default:
4913                 autosync_ref = "---"; break;
4914         }
4915         snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref);
4916 
4917         snd_iprintf(buffer, "\n");
4918 }
4919 
4920 static void
4921 snd_hdspm_proc_read_raydat(struct snd_info_entry *entry,
4922                          struct snd_info_buffer *buffer)
4923 {
4924         struct hdspm *hdspm = entry->private_data;
4925         unsigned int status1, status2, status3, control, i;
4926         unsigned int lock, sync;
4927 
4928         status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */
4929         status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */
4930         status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */
4931 
4932         control = hdspm->control_register;
4933 
4934         snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1);
4935         snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2);
4936         snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3);
4937 
4938 
4939         snd_iprintf(buffer, "\n*** CLOCK MODE\n\n");
4940 
4941         snd_iprintf(buffer, "Clock mode      : %s\n",
4942                 (hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave");
4943         snd_iprintf(buffer, "System frequency: %d Hz\n",
4944                 hdspm_get_system_sample_rate(hdspm));
4945 
4946         snd_iprintf(buffer, "\n*** INPUT STATUS\n\n");
4947 
4948         lock = 0x1;
4949         sync = 0x100;
4950 
4951         for (i = 0; i < 8; i++) {
4952                 snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n",
4953                                 i,
4954                                 (status1 & lock) ? 1 : 0,
4955                                 (status1 & sync) ? 1 : 0,
4956                                 texts_freq[(status2 >> (i * 4)) & 0xF]);
4957 
4958                 lock = lock<<1;
4959                 sync = sync<<1;
4960         }
4961 
4962         snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n",
4963                         (status1 & 0x1000000) ? 1 : 0,
4964                         (status1 & 0x2000000) ? 1 : 0,
4965                         texts_freq[(status1 >> 16) & 0xF]);
4966 
4967         snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n",
4968                         (status1 & 0x4000000) ? 1 : 0,
4969                         (status1 & 0x8000000) ? 1 : 0,
4970                         texts_freq[(status1 >> 20) & 0xF]);
4971 
4972         snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n",
4973                         (status3 & 0x400) ? 1 : 0,
4974                         (status3 & 0x800) ? 1 : 0,
4975                         texts_freq[(status2 >> 12) & 0xF]);
4976 
4977 }
4978 
4979 #ifdef CONFIG_SND_DEBUG
4980 static void
4981 snd_hdspm_proc_read_debug(struct snd_info_entry *entry,
4982                           struct snd_info_buffer *buffer)
4983 {
4984         struct hdspm *hdspm = entry->private_data;
4985 
4986         int j,i;
4987 
4988         for (i = 0; i < 256 /* 1024*64 */; i += j) {
4989                 snd_iprintf(buffer, "0x%08X: ", i);
4990                 for (j = 0; j < 16; j += 4)
4991                         snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j));
4992                 snd_iprintf(buffer, "\n");
4993         }
4994 }
4995 #endif
4996 
4997 
4998 static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry,
4999                           struct snd_info_buffer *buffer)
5000 {
5001         struct hdspm *hdspm = entry->private_data;
5002         int i;
5003 
5004         snd_iprintf(buffer, "# generated by hdspm\n");
5005 
5006         for (i = 0; i < hdspm->max_channels_in; i++) {
5007                 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]);
5008         }
5009 }
5010 
5011 static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry,
5012                           struct snd_info_buffer *buffer)
5013 {
5014         struct hdspm *hdspm = entry->private_data;
5015         int i;
5016 
5017         snd_iprintf(buffer, "# generated by hdspm\n");
5018 
5019         for (i = 0; i < hdspm->max_channels_out; i++) {
5020                 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]);
5021         }
5022 }
5023 
5024 
5025 static void snd_hdspm_proc_init(struct hdspm *hdspm)
5026 {
5027         struct snd_info_entry *entry;
5028 
5029         if (!snd_card_proc_new(hdspm->card, "hdspm", &entry)) {
5030                 switch (hdspm->io_type) {
5031                 case AES32:
5032                         snd_info_set_text_ops(entry, hdspm,
5033                                         snd_hdspm_proc_read_aes32);
5034                         break;
5035                 case MADI:
5036                         snd_info_set_text_ops(entry, hdspm,
5037                                         snd_hdspm_proc_read_madi);
5038                         break;
5039                 case MADIface:
5040                         /* snd_info_set_text_ops(entry, hdspm,
5041                          snd_hdspm_proc_read_madiface); */
5042                         break;
5043                 case RayDAT:
5044                         snd_info_set_text_ops(entry, hdspm,
5045                                         snd_hdspm_proc_read_raydat);
5046                         break;
5047                 case AIO:
5048                         break;
5049                 }
5050         }
5051 
5052         if (!snd_card_proc_new(hdspm->card, "ports.in", &entry)) {
5053                 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_in);
5054         }
5055 
5056         if (!snd_card_proc_new(hdspm->card, "ports.out", &entry)) {
5057                 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_out);
5058         }
5059 
5060 #ifdef CONFIG_SND_DEBUG
5061         /* debug file to read all hdspm registers */
5062         if (!snd_card_proc_new(hdspm->card, "debug", &entry))
5063                 snd_info_set_text_ops(entry, hdspm,
5064                                 snd_hdspm_proc_read_debug);
5065 #endif
5066 }
5067 
5068 /*------------------------------------------------------------
5069    hdspm intitialize
5070  ------------------------------------------------------------*/
5071 
5072 static int snd_hdspm_set_defaults(struct hdspm * hdspm)
5073 {
5074         /* ASSUMPTION: hdspm->lock is either held, or there is no need to
5075            hold it (e.g. during module initialization).
5076            */
5077 
5078         /* set defaults:       */
5079 
5080         hdspm->settings_register = 0;
5081 
5082         switch (hdspm->io_type) {
5083         case MADI:
5084         case MADIface:
5085                 hdspm->control_register =
5086                         0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5087                 break;
5088 
5089         case RayDAT:
5090         case AIO:
5091                 hdspm->settings_register = 0x1 + 0x1000;
5092                 /* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0,
5093                  * line_out */
5094                 hdspm->control_register =
5095                         0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5096                 break;
5097 
5098         case AES32:
5099                 hdspm->control_register =
5100                         HDSPM_ClockModeMaster | /* Master Cloack Mode on */
5101                         hdspm_encode_latency(7) | /* latency max=8192samples */
5102                         HDSPM_SyncRef0 |        /* AES1 is syncclock */
5103                         HDSPM_LineOut | /* Analog output in */
5104                         HDSPM_Professional;  /* Professional mode */
5105                 break;
5106         }
5107 
5108         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5109 
5110         if (AES32 == hdspm->io_type) {
5111                 /* No control2 register for AES32 */
5112 #ifdef SNDRV_BIG_ENDIAN
5113                 hdspm->control2_register = HDSPM_BIGENDIAN_MODE;
5114 #else
5115                 hdspm->control2_register = 0;
5116 #endif
5117 
5118                 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register);
5119         }
5120         hdspm_compute_period_size(hdspm);
5121 
5122         /* silence everything */
5123 
5124         all_in_all_mixer(hdspm, 0 * UNITY_GAIN);
5125 
5126         if (hdspm->io_type == AIO || hdspm->io_type == RayDAT) {
5127                 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
5128         }
5129 
5130         /* set a default rate so that the channel map is set up. */
5131         hdspm_set_rate(hdspm, 48000, 1);
5132 
5133         return 0;
5134 }
5135 
5136 
5137 /*------------------------------------------------------------
5138    interrupt
5139  ------------------------------------------------------------*/
5140 
5141 static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id)
5142 {
5143         struct hdspm *hdspm = (struct hdspm *) dev_id;
5144         unsigned int status;
5145         int i, audio, midi, schedule = 0;
5146         /* cycles_t now; */
5147 
5148         status = hdspm_read(hdspm, HDSPM_statusRegister);
5149 
5150         audio = status & HDSPM_audioIRQPending;
5151         midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending |
5152                         HDSPM_midi2IRQPending | HDSPM_midi3IRQPending);
5153 
5154         /* now = get_cycles(); */
5155         /**
5156          *   LAT_2..LAT_0 period  counter (win)  counter (mac)
5157          *          6       4096   ~256053425     ~514672358
5158          *          5       2048   ~128024983     ~257373821
5159          *          4       1024    ~64023706     ~128718089
5160          *          3        512    ~32005945      ~64385999
5161          *          2        256    ~16003039      ~32260176
5162          *          1        128     ~7998738      ~16194507
5163          *          0         64     ~3998231       ~8191558
5164          **/
5165         /*
5166            snd_printk(KERN_INFO "snd_hdspm_interrupt %llu @ %llx\n",
5167            now-hdspm->last_interrupt, status & 0xFFC0);
5168            hdspm->last_interrupt = now;
5169         */
5170 
5171         if (!audio && !midi)
5172                 return IRQ_NONE;
5173 
5174         hdspm_write(hdspm, HDSPM_interruptConfirmation, 0);
5175         hdspm->irq_count++;
5176 
5177 
5178         if (audio) {
5179                 if (hdspm->capture_substream)
5180                         snd_pcm_period_elapsed(hdspm->capture_substream);
5181 
5182                 if (hdspm->playback_substream)
5183                         snd_pcm_period_elapsed(hdspm->playback_substream);
5184         }
5185 
5186         if (midi) {
5187                 i = 0;
5188                 while (i < hdspm->midiPorts) {
5189                         if ((hdspm_read(hdspm,
5190                                 hdspm->midi[i].statusIn) & 0xff) &&
5191                                         (status & hdspm->midi[i].irq)) {
5192                                 /* we disable interrupts for this input until
5193                                  * processing is done
5194                                  */
5195                                 hdspm->control_register &= ~hdspm->midi[i].ie;
5196                                 hdspm_write(hdspm, HDSPM_controlRegister,
5197                                                 hdspm->control_register);
5198                                 hdspm->midi[i].pending = 1;
5199                                 schedule = 1;
5200                         }
5201 
5202                         i++;
5203                 }
5204 
5205                 if (schedule)
5206                         tasklet_hi_schedule(&hdspm->midi_tasklet);
5207         }
5208 
5209         return IRQ_HANDLED;
5210 }
5211 
5212 /*------------------------------------------------------------
5213    pcm interface
5214   ------------------------------------------------------------*/
5215 
5216 
5217 static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream
5218                                               *substream)
5219 {
5220         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5221         return hdspm_hw_pointer(hdspm);
5222 }
5223 
5224 
5225 static int snd_hdspm_reset(struct snd_pcm_substream *substream)
5226 {
5227         struct snd_pcm_runtime *runtime = substream->runtime;
5228         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5229         struct snd_pcm_substream *other;
5230 
5231         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5232                 other = hdspm->capture_substream;
5233         else
5234                 other = hdspm->playback_substream;
5235 
5236         if (hdspm->running)
5237                 runtime->status->hw_ptr = hdspm_hw_pointer(hdspm);
5238         else
5239                 runtime->status->hw_ptr = 0;
5240         if (other) {
5241                 struct snd_pcm_substream *s;
5242                 struct snd_pcm_runtime *oruntime = other->runtime;
5243                 snd_pcm_group_for_each_entry(s, substream) {
5244                         if (s == other) {
5245                                 oruntime->status->hw_ptr =
5246                                         runtime->status->hw_ptr;
5247                                 break;
5248                         }
5249                 }
5250         }
5251         return 0;
5252 }
5253 
5254 static int snd_hdspm_hw_params(struct snd_pcm_substream *substream,
5255                                struct snd_pcm_hw_params *params)
5256 {
5257         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5258         int err;
5259         int i;
5260         pid_t this_pid;
5261         pid_t other_pid;
5262 
5263         spin_lock_irq(&hdspm->lock);
5264 
5265         if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5266                 this_pid = hdspm->playback_pid;
5267                 other_pid = hdspm->capture_pid;
5268         } else {
5269                 this_pid = hdspm->capture_pid;
5270                 other_pid = hdspm->playback_pid;
5271         }
5272 
5273         if (other_pid > 0 && this_pid != other_pid) {
5274 
5275                 /* The other stream is open, and not by the same
5276                    task as this one. Make sure that the parameters
5277                    that matter are the same.
5278                    */
5279 
5280                 if (params_rate(params) != hdspm->system_sample_rate) {
5281                         spin_unlock_irq(&hdspm->lock);
5282                         _snd_pcm_hw_param_setempty(params,
5283                                         SNDRV_PCM_HW_PARAM_RATE);
5284                         return -EBUSY;
5285                 }
5286 
5287                 if (params_period_size(params) != hdspm->period_bytes / 4) {
5288                         spin_unlock_irq(&hdspm->lock);
5289                         _snd_pcm_hw_param_setempty(params,
5290                                         SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5291                         return -EBUSY;
5292                 }
5293 
5294         }
5295         /* We're fine. */
5296         spin_unlock_irq(&hdspm->lock);
5297 
5298         /* how to make sure that the rate matches an externally-set one ?   */
5299 
5300         spin_lock_irq(&hdspm->lock);
5301         err = hdspm_set_rate(hdspm, params_rate(params), 0);
5302         if (err < 0) {
5303                 snd_printk(KERN_INFO "err on hdspm_set_rate: %d\n", err);
5304                 spin_unlock_irq(&hdspm->lock);
5305                 _snd_pcm_hw_param_setempty(params,
5306                                 SNDRV_PCM_HW_PARAM_RATE);
5307                 return err;
5308         }
5309         spin_unlock_irq(&hdspm->lock);
5310 
5311         err = hdspm_set_interrupt_interval(hdspm,
5312                         params_period_size(params));
5313         if (err < 0) {
5314                 snd_printk(KERN_INFO "err on hdspm_set_interrupt_interval: %d\n", err);
5315                 _snd_pcm_hw_param_setempty(params,
5316                                 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5317                 return err;
5318         }
5319 
5320         /* Memory allocation, takashi's method, dont know if we should
5321          * spinlock
5322          */
5323         /* malloc all buffer even if not enabled to get sure */
5324         /* Update for MADI rev 204: we need to allocate for all channels,
5325          * otherwise it doesn't work at 96kHz */
5326 
5327         err =
5328                 snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES);
5329         if (err < 0) {
5330                 snd_printk(KERN_INFO "err on snd_pcm_lib_malloc_pages: %d\n", err);
5331                 return err;
5332         }
5333 
5334         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5335 
5336                 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferOut,
5337                                 params_channels(params));
5338 
5339                 for (i = 0; i < params_channels(params); ++i)
5340                         snd_hdspm_enable_out(hdspm, i, 1);
5341 
5342                 hdspm->playback_buffer =
5343                         (unsigned char *) substream->runtime->dma_area;
5344                 snd_printdd("Allocated sample buffer for playback at %p\n",
5345                                 hdspm->playback_buffer);
5346         } else {
5347                 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferIn,
5348                                 params_channels(params));
5349 
5350                 for (i = 0; i < params_channels(params); ++i)
5351                         snd_hdspm_enable_in(hdspm, i, 1);
5352 
5353                 hdspm->capture_buffer =
5354                         (unsigned char *) substream->runtime->dma_area;
5355                 snd_printdd("Allocated sample buffer for capture at %p\n",
5356                                 hdspm->capture_buffer);
5357         }
5358 
5359         /*
5360            snd_printdd("Allocated sample buffer for %s at 0x%08X\n",
5361            substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5362            "playback" : "capture",
5363            snd_pcm_sgbuf_get_addr(substream, 0));
5364            */
5365         /*
5366            snd_printdd("set_hwparams: %s %d Hz, %d channels, bs = %d\n",
5367            substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5368            "playback" : "capture",
5369            params_rate(params), params_channels(params),
5370            params_buffer_size(params));
5371            */
5372 
5373 
5374         /* Switch to native float format if requested */
5375         if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) {
5376                 if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT))
5377                         snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE float format.\n");
5378 
5379                 hdspm->control_register |= HDSPe_FLOAT_FORMAT;
5380         } else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) {
5381                 if (hdspm->control_register & HDSPe_FLOAT_FORMAT)
5382                         snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE integer format.\n");
5383 
5384                 hdspm->control_register &= ~HDSPe_FLOAT_FORMAT;
5385         }
5386         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5387 
5388         return 0;
5389 }
5390 
5391 static int snd_hdspm_hw_free(struct snd_pcm_substream *substream)
5392 {
5393         int i;
5394         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5395 
5396         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5397 
5398                 /* params_channels(params) should be enough,
5399                    but to get sure in case of error */
5400                 for (i = 0; i < hdspm->max_channels_out; ++i)
5401                         snd_hdspm_enable_out(hdspm, i, 0);
5402 
5403                 hdspm->playback_buffer = NULL;
5404         } else {
5405                 for (i = 0; i < hdspm->max_channels_in; ++i)
5406                         snd_hdspm_enable_in(hdspm, i, 0);
5407 
5408                 hdspm->capture_buffer = NULL;
5409 
5410         }
5411 
5412         snd_pcm_lib_free_pages(substream);
5413 
5414         return 0;
5415 }
5416 
5417 
5418 static int snd_hdspm_channel_info(struct snd_pcm_substream *substream,
5419                 struct snd_pcm_channel_info *info)
5420 {
5421         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5422 
5423         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5424                 if (snd_BUG_ON(info->channel >= hdspm->max_channels_out)) {
5425                         snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel out of range (%d)\n", info->channel);
5426                         return -EINVAL;
5427                 }
5428 
5429                 if (hdspm->channel_map_out[info->channel] < 0) {
5430                         snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel %d mapped out\n", info->channel);
5431                         return -EINVAL;
5432                 }
5433 
5434                 info->offset = hdspm->channel_map_out[info->channel] *
5435                         HDSPM_CHANNEL_BUFFER_BYTES;
5436         } else {
5437                 if (snd_BUG_ON(info->channel >= hdspm->max_channels_in)) {
5438                         snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel out of range (%d)\n", info->channel);
5439                         return -EINVAL;
5440                 }
5441 
5442                 if (hdspm->channel_map_in[info->channel] < 0) {
5443                         snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel %d mapped out\n", info->channel);
5444                         return -EINVAL;
5445                 }
5446 
5447                 info->offset = hdspm->channel_map_in[info->channel] *
5448                         HDSPM_CHANNEL_BUFFER_BYTES;
5449         }
5450 
5451         info->first = 0;
5452         info->step = 32;
5453         return 0;
5454 }
5455 
5456 
5457 static int snd_hdspm_ioctl(struct snd_pcm_substream *substream,
5458                 unsigned int cmd, void *arg)
5459 {
5460         switch (cmd) {
5461         case SNDRV_PCM_IOCTL1_RESET:
5462                 return snd_hdspm_reset(substream);
5463 
5464         case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
5465                 {
5466                         struct snd_pcm_channel_info *info = arg;
5467                         return snd_hdspm_channel_info(substream, info);
5468                 }
5469         default:
5470                 break;
5471         }
5472 
5473         return snd_pcm_lib_ioctl(substream, cmd, arg);
5474 }
5475 
5476 static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd)
5477 {
5478         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5479         struct snd_pcm_substream *other;
5480         int running;
5481 
5482         spin_lock(&hdspm->lock);
5483         running = hdspm->running;
5484         switch (cmd) {
5485         case SNDRV_PCM_TRIGGER_START:
5486                 running |= 1 << substream->stream;
5487                 break;
5488         case SNDRV_PCM_TRIGGER_STOP:
5489                 running &= ~(1 << substream->stream);
5490                 break;
5491         default:
5492                 snd_BUG();
5493                 spin_unlock(&hdspm->lock);
5494                 return -EINVAL;
5495         }
5496         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5497                 other = hdspm->capture_substream;
5498         else
5499                 other = hdspm->playback_substream;
5500 
5501         if (other) {
5502                 struct snd_pcm_substream *s;
5503                 snd_pcm_group_for_each_entry(s, substream) {
5504                         if (s == other) {
5505                                 snd_pcm_trigger_done(s, substream);
5506                                 if (cmd == SNDRV_PCM_TRIGGER_START)
5507                                         running |= 1 << s->stream;
5508                                 else
5509                                         running &= ~(1 << s->stream);
5510                                 goto _ok;
5511                         }
5512                 }
5513                 if (cmd == SNDRV_PCM_TRIGGER_START) {
5514                         if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK))
5515                                         && substream->stream ==
5516                                         SNDRV_PCM_STREAM_CAPTURE)
5517                                 hdspm_silence_playback(hdspm);
5518                 } else {
5519                         if (running &&
5520                                 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5521                                 hdspm_silence_playback(hdspm);
5522                 }
5523         } else {
5524                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
5525                         hdspm_silence_playback(hdspm);
5526         }
5527 _ok:
5528         snd_pcm_trigger_done(substream, substream);
5529         if (!hdspm->running && running)
5530                 hdspm_start_audio(hdspm);
5531         else if (hdspm->running && !running)
5532                 hdspm_stop_audio(hdspm);
5533         hdspm->running = running;
5534         spin_unlock(&hdspm->lock);
5535 
5536         return 0;
5537 }
5538 
5539 static int snd_hdspm_prepare(struct snd_pcm_substream *substream)
5540 {
5541         return 0;
5542 }
5543 
5544 static struct snd_pcm_hardware snd_hdspm_playback_subinfo = {
5545         .info = (SNDRV_PCM_INFO_MMAP |
5546                  SNDRV_PCM_INFO_MMAP_VALID |
5547                  SNDRV_PCM_INFO_NONINTERLEAVED |
5548                  SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE),
5549         .formats = SNDRV_PCM_FMTBIT_S32_LE,
5550         .rates = (SNDRV_PCM_RATE_32000 |
5551                   SNDRV_PCM_RATE_44100 |
5552                   SNDRV_PCM_RATE_48000 |
5553                   SNDRV_PCM_RATE_64000 |
5554                   SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5555                   SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ),
5556         .rate_min = 32000,
5557         .rate_max = 192000,
5558         .channels_min = 1,
5559         .channels_max = HDSPM_MAX_CHANNELS,
5560         .buffer_bytes_max =
5561             HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5562         .period_bytes_min = (32 * 4),
5563         .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
5564         .periods_min = 2,
5565         .periods_max = 512,
5566         .fifo_size = 0
5567 };
5568 
5569 static struct snd_pcm_hardware snd_hdspm_capture_subinfo = {
5570         .info = (SNDRV_PCM_INFO_MMAP |
5571                  SNDRV_PCM_INFO_MMAP_VALID |
5572                  SNDRV_PCM_INFO_NONINTERLEAVED |
5573                  SNDRV_PCM_INFO_SYNC_START),
5574         .formats = SNDRV_PCM_FMTBIT_S32_LE,
5575         .rates = (SNDRV_PCM_RATE_32000 |
5576                   SNDRV_PCM_RATE_44100 |
5577                   SNDRV_PCM_RATE_48000 |
5578                   SNDRV_PCM_RATE_64000 |
5579                   SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5580                   SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000),
5581         .rate_min = 32000,
5582         .rate_max = 192000,
5583         .channels_min = 1,
5584         .channels_max = HDSPM_MAX_CHANNELS,
5585         .buffer_bytes_max =
5586             HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5587         .period_bytes_min = (32 * 4),
5588         .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
5589         .periods_min = 2,
5590         .periods_max = 512,
5591         .fifo_size = 0
5592 };
5593 
5594 static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
5595                                            struct snd_pcm_hw_rule *rule)
5596 {
5597         struct hdspm *hdspm = rule->private;
5598         struct snd_interval *c =
5599             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5600         struct snd_interval *r =
5601             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5602 
5603         if (r->min > 96000 && r->max <= 192000) {
5604                 struct snd_interval t = {
5605                         .min = hdspm->qs_in_channels,
5606                         .max = hdspm->qs_in_channels,
5607                         .integer = 1,
5608                 };
5609                 return snd_interval_refine(c, &t);
5610         } else if (r->min > 48000 && r->max <= 96000) {
5611                 struct snd_interval t = {
5612                         .min = hdspm->ds_in_channels,
5613                         .max = hdspm->ds_in_channels,
5614                         .integer = 1,
5615                 };
5616                 return snd_interval_refine(c, &t);
5617         } else if (r->max < 64000) {
5618                 struct snd_interval t = {
5619                         .min = hdspm->ss_in_channels,
5620                         .max = hdspm->ss_in_channels,
5621                         .integer = 1,
5622                 };
5623                 return snd_interval_refine(c, &t);
5624         }
5625 
5626         return 0;
5627 }
5628 
5629 static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
5630                                            struct snd_pcm_hw_rule * rule)
5631 {
5632         struct hdspm *hdspm = rule->private;
5633         struct snd_interval *c =
5634             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5635         struct snd_interval *r =
5636             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5637 
5638         if (r->min > 96000 && r->max <= 192000) {
5639                 struct snd_interval t = {
5640                         .min = hdspm->qs_out_channels,
5641                         .max = hdspm->qs_out_channels,
5642                         .integer = 1,
5643                 };
5644                 return snd_interval_refine(c, &t);
5645         } else if (r->min > 48000 && r->max <= 96000) {
5646                 struct snd_interval t = {
5647                         .min = hdspm->ds_out_channels,
5648                         .max = hdspm->ds_out_channels,
5649                         .integer = 1,
5650                 };
5651                 return snd_interval_refine(c, &t);
5652         } else if (r->max < 64000) {
5653                 struct snd_interval t = {
5654                         .min = hdspm->ss_out_channels,
5655                         .max = hdspm->ss_out_channels,
5656                         .integer = 1,
5657                 };
5658                 return snd_interval_refine(c, &t);
5659         } else {
5660         }
5661         return 0;
5662 }
5663 
5664 static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
5665                                            struct snd_pcm_hw_rule * rule)
5666 {
5667         struct hdspm *hdspm = rule->private;
5668         struct snd_interval *c =
5669             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5670         struct snd_interval *r =
5671             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5672 
5673         if (c->min >= hdspm->ss_in_channels) {
5674                 struct snd_interval t = {
5675                         .min = 32000,
5676                         .max = 48000,
5677                         .integer = 1,
5678                 };
5679                 return snd_interval_refine(r, &t);
5680         } else if (c->max <= hdspm->qs_in_channels) {
5681                 struct snd_interval t = {
5682                         .min = 128000,
5683                         .max = 192000,
5684                         .integer = 1,
5685                 };
5686                 return snd_interval_refine(r, &t);
5687         } else if (c->max <= hdspm->ds_in_channels) {
5688                 struct snd_interval t = {
5689                         .min = 64000,
5690                         .max = 96000,
5691                         .integer = 1,
5692                 };
5693                 return snd_interval_refine(r, &t);
5694         }
5695 
5696         return 0;
5697 }
5698 static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
5699                                            struct snd_pcm_hw_rule *rule)
5700 {
5701         struct hdspm *hdspm = rule->private;
5702         struct snd_interval *c =
5703             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5704         struct snd_interval *r =
5705             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5706 
5707         if (c->min >= hdspm->ss_out_channels) {
5708                 struct snd_interval t = {
5709                         .min = 32000,
5710                         .max = 48000,
5711                         .integer = 1,
5712                 };
5713                 return snd_interval_refine(r, &t);
5714         } else if (c->max <= hdspm->qs_out_channels) {
5715                 struct snd_interval t = {
5716                         .min = 128000,
5717                         .max = 192000,
5718                         .integer = 1,
5719                 };
5720                 return snd_interval_refine(r, &t);
5721         } else if (c->max <= hdspm->ds_out_channels) {
5722                 struct snd_interval t = {
5723                         .min = 64000,
5724                         .max = 96000,
5725                         .integer = 1,
5726                 };
5727                 return snd_interval_refine(r, &t);
5728         }
5729 
5730         return 0;
5731 }
5732 
5733 static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params *params,
5734                                       struct snd_pcm_hw_rule *rule)
5735 {
5736         unsigned int list[3];
5737         struct hdspm *hdspm = rule->private;
5738         struct snd_interval *c = hw_param_interval(params,
5739                         SNDRV_PCM_HW_PARAM_CHANNELS);
5740 
5741         list[0] = hdspm->qs_in_channels;
5742         list[1] = hdspm->ds_in_channels;
5743         list[2] = hdspm->ss_in_channels;
5744         return snd_interval_list(c, 3, list, 0);
5745 }
5746 
5747 static int snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params *params,
5748                                       struct snd_pcm_hw_rule *rule)
5749 {
5750         unsigned int list[3];
5751         struct hdspm *hdspm = rule->private;
5752         struct snd_interval *c = hw_param_interval(params,
5753                         SNDRV_PCM_HW_PARAM_CHANNELS);
5754 
5755         list[0] = hdspm->qs_out_channels;
5756         list[1] = hdspm->ds_out_channels;
5757         list[2] = hdspm->ss_out_channels;
5758         return snd_interval_list(c, 3, list, 0);
5759 }
5760 
5761 
5762 static unsigned int hdspm_aes32_sample_rates[] = {
5763         32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000
5764 };
5765 
5766 static struct snd_pcm_hw_constraint_list
5767 hdspm_hw_constraints_aes32_sample_rates = {
5768         .count = ARRAY_SIZE(hdspm_aes32_sample_rates),
5769         .list = hdspm_aes32_sample_rates,
5770         .mask = 0
5771 };
5772 
5773 static int snd_hdspm_playback_open(struct snd_pcm_substream *substream)
5774 {
5775         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5776         struct