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TOMOYO Linux Cross Reference
Linux/sound/pci/rme9652/hdspm.c

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  1 /*
  2  *   ALSA driver for RME Hammerfall DSP MADI audio interface(s)
  3  *
  4  *      Copyright (c) 2003 Winfried Ritsch (IEM)
  5  *      code based on hdsp.c   Paul Davis
  6  *                             Marcus Andersson
  7  *                             Thomas Charbonnel
  8  *      Modified 2006-06-01 for AES32 support by Remy Bruno
  9  *                                               <remy.bruno@trinnov.com>
 10  *
 11  *      Modified 2009-04-13 for proper metering by Florian Faber
 12  *                                               <faber@faberman.de>
 13  *
 14  *      Modified 2009-04-14 for native float support by Florian Faber
 15  *                                               <faber@faberman.de>
 16  *
 17  *      Modified 2009-04-26 fixed bug in rms metering by Florian Faber
 18  *                                               <faber@faberman.de>
 19  *
 20  *      Modified 2009-04-30 added hw serial number support by Florian Faber
 21  *
 22  *      Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth
 23  *
 24  *      Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth
 25  *
 26  *   This program is free software; you can redistribute it and/or modify
 27  *   it under the terms of the GNU General Public License as published by
 28  *   the Free Software Foundation; either version 2 of the License, or
 29  *   (at your option) any later version.
 30  *
 31  *   This program is distributed in the hope that it will be useful,
 32  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 33  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 34  *   GNU General Public License for more details.
 35  *
 36  *   You should have received a copy of the GNU General Public License
 37  *   along with this program; if not, write to the Free Software
 38  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 39  *
 40  */
 41 
 42 /* *************    Register Documentation   *******************************************************
 43  *
 44  * Work in progress! Documentation is based on the code in this file.
 45  *
 46  * --------- HDSPM_controlRegister ---------
 47  * :7654.3210:7654.3210:7654.3210:7654.3210: bit number per byte
 48  * :||||.||||:||||.||||:||||.||||:||||.||||:
 49  * :3322.2222:2222.1111:1111.1100:0000.0000: bit number
 50  * :1098.7654:3210.9876:5432.1098:7654.3210: 0..31
 51  * :||||.||||:||||.||||:||||.||||:||||.||||:
 52  * :8421.8421:8421.8421:8421.8421:8421.8421: hex digit
 53  * :    .    :    .    :    .    :  x .    :  HDSPM_AudioInterruptEnable \_ setting both bits
 54  * :    .    :    .    :    .    :    .   x:  HDSPM_Start                /  enables audio IO
 55  * :    .    :    .    :    .    :   x.    :  HDSPM_ClockModeMaster - 1: Master, 0: Slave
 56  * :    .    :    .    :    .    :    .210 :  HDSPM_LatencyMask - 3 Bit value for latency
 57  * :    .    :    .    :    .    :    .    :      0:64, 1:128, 2:256, 3:512,
 58  * :    .    :    .    :    .    :    .    :      4:1024, 5:2048, 6:4096, 7:8192
 59  * :x   .    :    .    :    .   x:xx  .    :  HDSPM_FrequencyMask
 60  * :    .    :    .    :    .    :10  .    :  HDSPM_Frequency1|HDSPM_Frequency0: 1=32K,2=44.1K,3=48K,0=??
 61  * :    .    :    .    :    .   x:    .    :  <MADI> HDSPM_DoubleSpeed
 62  * :x   .    :    .    :    .    :    .    :  <MADI> HDSPM_QuadSpeed
 63  * :    .  3 :    .  10:  2 .    :    .    :  HDSPM_SyncRefMask :
 64  * :    .    :    .   x:    .    :    .    :  HDSPM_SyncRef0
 65  * :    .    :    .  x :    .    :    .    :  HDSPM_SyncRef1
 66  * :    .    :    .    :  x .    :    .    :  <AES32> HDSPM_SyncRef2
 67  * :    .  x :    .    :    .    :    .    :  <AES32> HDSPM_SyncRef3
 68  * :    .    :    .  10:    .    :    .    :  <MADI> sync ref: 0:WC, 1:Madi, 2:TCO, 3:SyncIn
 69  * :    .  3 :    .  10:  2 .    :    .    :  <AES32>  0:WC, 1:AES1 ... 8:AES8, 9: TCO, 10:SyncIn?
 70  * :    .  x :    .    :    .    :    .    :  <MADIe> HDSPe_FLOAT_FORMAT
 71  * :    .    :    .    : x  .    :    .    :  <MADI> HDSPM_InputSelect0 : 0=optical,1=coax
 72  * :    .    :    .    :x   .    :    .    :  <MADI> HDSPM_InputSelect1
 73  * :    .    :    .x   :    .    :    .    :  <MADI> HDSPM_clr_tms
 74  * :    .    :    .    :    . x  :    .    :  <MADI> HDSPM_TX_64ch
 75  * :    .    :    .    :    . x  :    .    :  <AES32> HDSPM_Emphasis
 76  * :    .    :    .    :    .x   :    .    :  <MADI> HDSPM_AutoInp
 77  * :    .    :    . x  :    .    :    .    :  <MADI> HDSPM_SMUX
 78  * :    .    :    .x   :    .    :    .    :  <MADI> HDSPM_clr_tms
 79  * :    .    :   x.    :    .    :    .    :  <MADI> HDSPM_taxi_reset
 80  * :    .   x:    .    :    .    :    .    :  <MADI> HDSPM_LineOut
 81  * :    .   x:    .    :    .    :    .    :  <AES32> ??????????????????
 82  * :    .    :   x.    :    .    :    .    :  <AES32> HDSPM_WCK48
 83  * :    .    :    .    :    .x   :    .    :  <AES32> HDSPM_Dolby
 84  * :    .    : x  .    :    .    :    .    :  HDSPM_Midi0InterruptEnable
 85  * :    .    :x   .    :    .    :    .    :  HDSPM_Midi1InterruptEnable
 86  * :    .    :  x .    :    .    :    .    :  HDSPM_Midi2InterruptEnable
 87  * :    . x  :    .    :    .    :    .    :  <MADI> HDSPM_Midi3InterruptEnable
 88  * :    . x  :    .    :    .    :    .    :  <AES32> HDSPM_DS_DoubleWire
 89  * :    .x   :    .    :    .    :    .    :  <AES32> HDSPM_QS_DoubleWire
 90  * :   x.    :    .    :    .    :    .    :  <AES32> HDSPM_QS_QuadWire
 91  * :    .    :    .    :    .  x :    .    :  <AES32> HDSPM_Professional
 92  * : x  .    :    .    :    .    :    .    :  HDSPM_wclk_sel
 93  * :    .    :    .    :    .    :    .    :
 94  * :7654.3210:7654.3210:7654.3210:7654.3210: bit number per byte
 95  * :||||.||||:||||.||||:||||.||||:||||.||||:
 96  * :3322.2222:2222.1111:1111.1100:0000.0000: bit number
 97  * :1098.7654:3210.9876:5432.1098:7654.3210: 0..31
 98  * :||||.||||:||||.||||:||||.||||:||||.||||:
 99  * :8421.8421:8421.8421:8421.8421:8421.8421:hex digit
100  *
101  *
102  *
103  * AIO / RayDAT only
104  *
105  * ------------ HDSPM_WR_SETTINGS ----------
106  * :3322.2222:2222.1111:1111.1100:0000.0000: bit number per byte
107  * :1098.7654:3210.9876:5432.1098:7654.3210:
108  * :||||.||||:||||.||||:||||.||||:||||.||||: bit number
109  * :7654.3210:7654.3210:7654.3210:7654.3210: 0..31
110  * :||||.||||:||||.||||:||||.||||:||||.||||:
111  * :8421.8421:8421.8421:8421.8421:8421.8421: hex digit
112  * :    .    :    .    :    .    :    .   x: HDSPM_c0Master 1: Master, 0: Slave
113  * :    .    :    .    :    .    :    .  x : HDSPM_c0_SyncRef0
114  * :    .    :    .    :    .    :    . x  : HDSPM_c0_SyncRef1
115  * :    .    :    .    :    .    :    .x   : HDSPM_c0_SyncRef2
116  * :    .    :    .    :    .    :   x.    : HDSPM_c0_SyncRef3
117  * :    .    :    .    :    .    :   3.210 : HDSPM_c0_SyncRefMask:
118  * :    .    :    .    :    .    :    .    :  RayDat: 0:WC, 1:AES, 2:SPDIF, 3..6: ADAT1..4,
119  * :    .    :    .    :    .    :    .    :          9:TCO, 10:SyncIn
120  * :    .    :    .    :    .    :    .    :  AIO: 0:WC, 1:AES, 2: SPDIF, 3: ATAT,
121  * :    .    :    .    :    .    :    .    :          9:TCO, 10:SyncIn
122  * :    .    :    .    :    .    :    .    :
123  * :    .    :    .    :    .    :    .    :
124  * :3322.2222:2222.1111:1111.1100:0000.0000: bit number per byte
125  * :1098.7654:3210.9876:5432.1098:7654.3210:
126  * :||||.||||:||||.||||:||||.||||:||||.||||: bit number
127  * :7654.3210:7654.3210:7654.3210:7654.3210: 0..31
128  * :||||.||||:||||.||||:||||.||||:||||.||||:
129  * :8421.8421:8421.8421:8421.8421:8421.8421: hex digit
130  *
131  */
132 #include <linux/init.h>
133 #include <linux/delay.h>
134 #include <linux/interrupt.h>
135 #include <linux/module.h>
136 #include <linux/slab.h>
137 #include <linux/pci.h>
138 #include <linux/math64.h>
139 #include <asm/io.h>
140 
141 #include <sound/core.h>
142 #include <sound/control.h>
143 #include <sound/pcm.h>
144 #include <sound/pcm_params.h>
145 #include <sound/info.h>
146 #include <sound/asoundef.h>
147 #include <sound/rawmidi.h>
148 #include <sound/hwdep.h>
149 #include <sound/initval.h>
150 
151 #include <sound/hdspm.h>
152 
153 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;        /* Index 0-MAX */
154 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;         /* ID for this card */
155 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
156 
157 module_param_array(index, int, NULL, 0444);
158 MODULE_PARM_DESC(index, "Index value for RME HDSPM interface.");
159 
160 module_param_array(id, charp, NULL, 0444);
161 MODULE_PARM_DESC(id, "ID string for RME HDSPM interface.");
162 
163 module_param_array(enable, bool, NULL, 0444);
164 MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards.");
165 
166 
167 MODULE_AUTHOR
168 (
169         "Winfried Ritsch <ritsch_AT_iem.at>, "
170         "Paul Davis <paul@linuxaudiosystems.com>, "
171         "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, "
172         "Remy Bruno <remy.bruno@trinnov.com>, "
173         "Florian Faber <faberman@linuxproaudio.org>, "
174         "Adrian Knoth <adi@drcomp.erfurt.thur.de>"
175 );
176 MODULE_DESCRIPTION("RME HDSPM");
177 MODULE_LICENSE("GPL");
178 MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}");
179 
180 /* --- Write registers. ---
181   These are defined as byte-offsets from the iobase value.  */
182 
183 #define HDSPM_WR_SETTINGS             0
184 #define HDSPM_outputBufferAddress    32
185 #define HDSPM_inputBufferAddress     36
186 #define HDSPM_controlRegister        64
187 #define HDSPM_interruptConfirmation  96
188 #define HDSPM_control2Reg            256  /* not in specs ???????? */
189 #define HDSPM_freqReg                256  /* for setting arbitrary clock values (DDS feature) */
190 #define HDSPM_midiDataOut0           352  /* just believe in old code */
191 #define HDSPM_midiDataOut1           356
192 #define HDSPM_eeprom_wr              384  /* for AES32 */
193 
194 /* DMA enable for 64 channels, only Bit 0 is relevant */
195 #define HDSPM_outputEnableBase       512  /* 512-767  input  DMA */
196 #define HDSPM_inputEnableBase        768  /* 768-1023 output DMA */
197 
198 /* 16 page addresses for each of the 64 channels DMA buffer in and out
199    (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */
200 #define HDSPM_pageAddressBufferOut       8192
201 #define HDSPM_pageAddressBufferIn        (HDSPM_pageAddressBufferOut+64*16*4)
202 
203 #define HDSPM_MADI_mixerBase    32768   /* 32768-65535 for 2x64x64 Fader */
204 
205 #define HDSPM_MATRIX_MIXER_SIZE  8192   /* = 2*64*64 * 4 Byte => 32kB */
206 
207 /* --- Read registers. ---
208    These are defined as byte-offsets from the iobase value */
209 #define HDSPM_statusRegister    0
210 /*#define HDSPM_statusRegister2  96 */
211 /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at
212  * offset 192, for AES32 *and* MADI
213  * => need to check that offset 192 is working on MADI */
214 #define HDSPM_statusRegister2  192
215 #define HDSPM_timecodeRegister 128
216 
217 /* AIO, RayDAT */
218 #define HDSPM_RD_STATUS_0 0
219 #define HDSPM_RD_STATUS_1 64
220 #define HDSPM_RD_STATUS_2 128
221 #define HDSPM_RD_STATUS_3 192
222 
223 #define HDSPM_RD_TCO           256
224 #define HDSPM_RD_PLL_FREQ      512
225 #define HDSPM_WR_TCO           128
226 
227 #define HDSPM_TCO1_TCO_lock                     0x00000001
228 #define HDSPM_TCO1_WCK_Input_Range_LSB          0x00000002
229 #define HDSPM_TCO1_WCK_Input_Range_MSB          0x00000004
230 #define HDSPM_TCO1_LTC_Input_valid              0x00000008
231 #define HDSPM_TCO1_WCK_Input_valid              0x00000010
232 #define HDSPM_TCO1_Video_Input_Format_NTSC      0x00000020
233 #define HDSPM_TCO1_Video_Input_Format_PAL       0x00000040
234 
235 #define HDSPM_TCO1_set_TC                       0x00000100
236 #define HDSPM_TCO1_set_drop_frame_flag          0x00000200
237 #define HDSPM_TCO1_LTC_Format_LSB               0x00000400
238 #define HDSPM_TCO1_LTC_Format_MSB               0x00000800
239 
240 #define HDSPM_TCO2_TC_run                       0x00010000
241 #define HDSPM_TCO2_WCK_IO_ratio_LSB             0x00020000
242 #define HDSPM_TCO2_WCK_IO_ratio_MSB             0x00040000
243 #define HDSPM_TCO2_set_num_drop_frames_LSB      0x00080000
244 #define HDSPM_TCO2_set_num_drop_frames_MSB      0x00100000
245 #define HDSPM_TCO2_set_jam_sync                 0x00200000
246 #define HDSPM_TCO2_set_flywheel                 0x00400000
247 
248 #define HDSPM_TCO2_set_01_4                     0x01000000
249 #define HDSPM_TCO2_set_pull_down                0x02000000
250 #define HDSPM_TCO2_set_pull_up                  0x04000000
251 #define HDSPM_TCO2_set_freq                     0x08000000
252 #define HDSPM_TCO2_set_term_75R                 0x10000000
253 #define HDSPM_TCO2_set_input_LSB                0x20000000
254 #define HDSPM_TCO2_set_input_MSB                0x40000000
255 #define HDSPM_TCO2_set_freq_from_app            0x80000000
256 
257 
258 #define HDSPM_midiDataOut0    352
259 #define HDSPM_midiDataOut1    356
260 #define HDSPM_midiDataOut2    368
261 
262 #define HDSPM_midiDataIn0     360
263 #define HDSPM_midiDataIn1     364
264 #define HDSPM_midiDataIn2     372
265 #define HDSPM_midiDataIn3     376
266 
267 /* status is data bytes in MIDI-FIFO (0-128) */
268 #define HDSPM_midiStatusOut0  384
269 #define HDSPM_midiStatusOut1  388
270 #define HDSPM_midiStatusOut2  400
271 
272 #define HDSPM_midiStatusIn0   392
273 #define HDSPM_midiStatusIn1   396
274 #define HDSPM_midiStatusIn2   404
275 #define HDSPM_midiStatusIn3   408
276 
277 
278 /* the meters are regular i/o-mapped registers, but offset
279    considerably from the rest. the peak registers are reset
280    when read; the least-significant 4 bits are full-scale counters;
281    the actual peak value is in the most-significant 24 bits.
282 */
283 
284 #define HDSPM_MADI_INPUT_PEAK           4096
285 #define HDSPM_MADI_PLAYBACK_PEAK        4352
286 #define HDSPM_MADI_OUTPUT_PEAK          4608
287 
288 #define HDSPM_MADI_INPUT_RMS_L          6144
289 #define HDSPM_MADI_PLAYBACK_RMS_L       6400
290 #define HDSPM_MADI_OUTPUT_RMS_L         6656
291 
292 #define HDSPM_MADI_INPUT_RMS_H          7168
293 #define HDSPM_MADI_PLAYBACK_RMS_H       7424
294 #define HDSPM_MADI_OUTPUT_RMS_H         7680
295 
296 /* --- Control Register bits --------- */
297 #define HDSPM_Start                (1<<0) /* start engine */
298 
299 #define HDSPM_Latency0             (1<<1) /* buffer size = 2^n */
300 #define HDSPM_Latency1             (1<<2) /* where n is defined */
301 #define HDSPM_Latency2             (1<<3) /* by Latency{2,1,0} */
302 
303 #define HDSPM_ClockModeMaster      (1<<4) /* 1=Master, 0=Autosync */
304 #define HDSPM_c0Master          0x1    /* Master clock bit in settings
305                                           register [RayDAT, AIO] */
306 
307 #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */
308 
309 #define HDSPM_Frequency0  (1<<6)  /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */
310 #define HDSPM_Frequency1  (1<<7)  /* 0=32kHz/64kHz */
311 #define HDSPM_DoubleSpeed (1<<8)  /* 0=normal speed, 1=double speed */
312 #define HDSPM_QuadSpeed   (1<<31) /* quad speed bit */
313 
314 #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */
315 #define HDSPM_TX_64ch     (1<<10) /* Output 64channel MODE=1,
316                                      56channelMODE=0 */ /* MADI ONLY*/
317 #define HDSPM_Emphasis    (1<<10) /* Emphasis */ /* AES32 ONLY */
318 
319 #define HDSPM_AutoInp     (1<<11) /* Auto Input (takeover) == Safe Mode,
320                                      0=off, 1=on  */ /* MADI ONLY */
321 #define HDSPM_Dolby       (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */
322 
323 #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax
324                                     * -- MADI ONLY
325                                     */
326 #define HDSPM_InputSelect1 (1<<15) /* should be 0 */
327 
328 #define HDSPM_SyncRef2     (1<<13)
329 #define HDSPM_SyncRef3     (1<<25)
330 
331 #define HDSPM_SMUX         (1<<18) /* Frame ??? */ /* MADI ONY */
332 #define HDSPM_clr_tms      (1<<19) /* clear track marker, do not use
333                                       AES additional bits in
334                                       lower 5 Audiodatabits ??? */
335 #define HDSPM_taxi_reset   (1<<20) /* ??? */ /* MADI ONLY ? */
336 #define HDSPM_WCK48        (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */
337 
338 #define HDSPM_Midi0InterruptEnable 0x0400000
339 #define HDSPM_Midi1InterruptEnable 0x0800000
340 #define HDSPM_Midi2InterruptEnable 0x0200000
341 #define HDSPM_Midi3InterruptEnable 0x4000000
342 
343 #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */
344 #define HDSPe_FLOAT_FORMAT         0x2000000
345 
346 #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */
347 #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */
348 #define HDSPM_QS_QuadWire   (1<<28) /* AES32 ONLY */
349 
350 #define HDSPM_wclk_sel (1<<30)
351 
352 /* additional control register bits for AIO*/
353 #define HDSPM_c0_Wck48                          0x20 /* also RayDAT */
354 #define HDSPM_c0_Input0                         0x1000
355 #define HDSPM_c0_Input1                         0x2000
356 #define HDSPM_c0_Spdif_Opt                      0x4000
357 #define HDSPM_c0_Pro                            0x8000
358 #define HDSPM_c0_clr_tms                        0x10000
359 #define HDSPM_c0_AEB1                           0x20000
360 #define HDSPM_c0_AEB2                           0x40000
361 #define HDSPM_c0_LineOut                        0x80000
362 #define HDSPM_c0_AD_GAIN0                       0x100000
363 #define HDSPM_c0_AD_GAIN1                       0x200000
364 #define HDSPM_c0_DA_GAIN0                       0x400000
365 #define HDSPM_c0_DA_GAIN1                       0x800000
366 #define HDSPM_c0_PH_GAIN0                       0x1000000
367 #define HDSPM_c0_PH_GAIN1                       0x2000000
368 #define HDSPM_c0_Sym6db                         0x4000000
369 
370 
371 /* --- bit helper defines */
372 #define HDSPM_LatencyMask    (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2)
373 #define HDSPM_FrequencyMask  (HDSPM_Frequency0|HDSPM_Frequency1|\
374                               HDSPM_DoubleSpeed|HDSPM_QuadSpeed)
375 #define HDSPM_InputMask      (HDSPM_InputSelect0|HDSPM_InputSelect1)
376 #define HDSPM_InputOptical   0
377 #define HDSPM_InputCoaxial   (HDSPM_InputSelect0)
378 #define HDSPM_SyncRefMask    (HDSPM_SyncRef0|HDSPM_SyncRef1|\
379                               HDSPM_SyncRef2|HDSPM_SyncRef3)
380 
381 #define HDSPM_c0_SyncRef0      0x2
382 #define HDSPM_c0_SyncRef1      0x4
383 #define HDSPM_c0_SyncRef2      0x8
384 #define HDSPM_c0_SyncRef3      0x10
385 #define HDSPM_c0_SyncRefMask   (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\
386                                 HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3)
387 
388 #define HDSPM_SYNC_FROM_WORD    0       /* Preferred sync reference */
389 #define HDSPM_SYNC_FROM_MADI    1       /* choices - used by "pref_sync_ref" */
390 #define HDSPM_SYNC_FROM_TCO     2
391 #define HDSPM_SYNC_FROM_SYNC_IN 3
392 
393 #define HDSPM_Frequency32KHz    HDSPM_Frequency0
394 #define HDSPM_Frequency44_1KHz  HDSPM_Frequency1
395 #define HDSPM_Frequency48KHz   (HDSPM_Frequency1|HDSPM_Frequency0)
396 #define HDSPM_Frequency64KHz   (HDSPM_DoubleSpeed|HDSPM_Frequency0)
397 #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1)
398 #define HDSPM_Frequency96KHz   (HDSPM_DoubleSpeed|HDSPM_Frequency1|\
399                                 HDSPM_Frequency0)
400 #define HDSPM_Frequency128KHz   (HDSPM_QuadSpeed|HDSPM_Frequency0)
401 #define HDSPM_Frequency176_4KHz   (HDSPM_QuadSpeed|HDSPM_Frequency1)
402 #define HDSPM_Frequency192KHz   (HDSPM_QuadSpeed|HDSPM_Frequency1|\
403                                  HDSPM_Frequency0)
404 
405 
406 /* Synccheck Status */
407 #define HDSPM_SYNC_CHECK_NO_LOCK 0
408 #define HDSPM_SYNC_CHECK_LOCK    1
409 #define HDSPM_SYNC_CHECK_SYNC    2
410 
411 /* AutoSync References - used by "autosync_ref" control switch */
412 #define HDSPM_AUTOSYNC_FROM_WORD      0
413 #define HDSPM_AUTOSYNC_FROM_MADI      1
414 #define HDSPM_AUTOSYNC_FROM_TCO       2
415 #define HDSPM_AUTOSYNC_FROM_SYNC_IN   3
416 #define HDSPM_AUTOSYNC_FROM_NONE      4
417 
418 /* Possible sources of MADI input */
419 #define HDSPM_OPTICAL 0         /* optical   */
420 #define HDSPM_COAXIAL 1         /* BNC */
421 
422 #define hdspm_encode_latency(x)       (((x)<<1) & HDSPM_LatencyMask)
423 #define hdspm_decode_latency(x)       ((((x) & HDSPM_LatencyMask)>>1))
424 
425 #define hdspm_encode_in(x) (((x)&0x3)<<14)
426 #define hdspm_decode_in(x) (((x)>>14)&0x3)
427 
428 /* --- control2 register bits --- */
429 #define HDSPM_TMS             (1<<0)
430 #define HDSPM_TCK             (1<<1)
431 #define HDSPM_TDI             (1<<2)
432 #define HDSPM_JTAG            (1<<3)
433 #define HDSPM_PWDN            (1<<4)
434 #define HDSPM_PROGRAM         (1<<5)
435 #define HDSPM_CONFIG_MODE_0   (1<<6)
436 #define HDSPM_CONFIG_MODE_1   (1<<7)
437 /*#define HDSPM_VERSION_BIT     (1<<8) not defined any more*/
438 #define HDSPM_BIGENDIAN_MODE  (1<<9)
439 #define HDSPM_RD_MULTIPLE     (1<<10)
440 
441 /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and
442      that do not conflict with specific bits for AES32 seem to be valid also
443      for the AES32
444  */
445 #define HDSPM_audioIRQPending    (1<<0) /* IRQ is high and pending */
446 #define HDSPM_RX_64ch            (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */
447 #define HDSPM_AB_int             (1<<2) /* InputChannel Opt=0, Coax=1
448                                          * (like inp0)
449                                          */
450 
451 #define HDSPM_madiLock           (1<<3) /* MADI Locked =1, no=0 */
452 #define HDSPM_madiSync          (1<<18) /* MADI is in sync */
453 
454 #define HDSPM_tcoLockMadi    0x00000020 /* Optional TCO locked status for HDSPe MADI*/
455 #define HDSPM_tcoSync    0x10000000 /* Optional TCO sync status for HDSPe MADI and AES32!*/
456 
457 #define HDSPM_syncInLock 0x00010000 /* Sync In lock status for HDSPe MADI! */
458 #define HDSPM_syncInSync 0x00020000 /* Sync In sync status for HDSPe MADI! */
459 
460 #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
461                         /* since 64byte accurate, last 6 bits are not used */
462 
463 
464 
465 #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */
466 
467 #define HDSPM_madiFreq0         (1<<22) /* system freq 0=error */
468 #define HDSPM_madiFreq1         (1<<23) /* 1=32, 2=44.1 3=48 */
469 #define HDSPM_madiFreq2         (1<<24) /* 4=64, 5=88.2 6=96 */
470 #define HDSPM_madiFreq3         (1<<25) /* 7=128, 8=176.4 9=192 */
471 
472 #define HDSPM_BufferID          (1<<26) /* (Double)Buffer ID toggles with
473                                          * Interrupt
474                                          */
475 #define HDSPM_tco_detect         0x08000000
476 #define HDSPM_tcoLockAes         0x20000000 /* Optional TCO locked status for HDSPe AES */
477 
478 #define HDSPM_s2_tco_detect      0x00000040
479 #define HDSPM_s2_AEBO_D          0x00000080
480 #define HDSPM_s2_AEBI_D          0x00000100
481 
482 
483 #define HDSPM_midi0IRQPending    0x40000000
484 #define HDSPM_midi1IRQPending    0x80000000
485 #define HDSPM_midi2IRQPending    0x20000000
486 #define HDSPM_midi2IRQPendingAES 0x00000020
487 #define HDSPM_midi3IRQPending    0x00200000
488 
489 /* --- status bit helpers */
490 #define HDSPM_madiFreqMask  (HDSPM_madiFreq0|HDSPM_madiFreq1|\
491                              HDSPM_madiFreq2|HDSPM_madiFreq3)
492 #define HDSPM_madiFreq32    (HDSPM_madiFreq0)
493 #define HDSPM_madiFreq44_1  (HDSPM_madiFreq1)
494 #define HDSPM_madiFreq48    (HDSPM_madiFreq0|HDSPM_madiFreq1)
495 #define HDSPM_madiFreq64    (HDSPM_madiFreq2)
496 #define HDSPM_madiFreq88_2  (HDSPM_madiFreq0|HDSPM_madiFreq2)
497 #define HDSPM_madiFreq96    (HDSPM_madiFreq1|HDSPM_madiFreq2)
498 #define HDSPM_madiFreq128   (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2)
499 #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3)
500 #define HDSPM_madiFreq192   (HDSPM_madiFreq3|HDSPM_madiFreq0)
501 
502 /* Status2 Register bits */ /* MADI ONLY */
503 
504 #define HDSPM_version0 (1<<0)   /* not really defined but I guess */
505 #define HDSPM_version1 (1<<1)   /* in former cards it was ??? */
506 #define HDSPM_version2 (1<<2)
507 
508 #define HDSPM_wcLock (1<<3)     /* Wordclock is detected and locked */
509 #define HDSPM_wcSync (1<<4)     /* Wordclock is in sync with systemclock */
510 
511 #define HDSPM_wc_freq0 (1<<5)   /* input freq detected via autosync  */
512 #define HDSPM_wc_freq1 (1<<6)   /* 001=32, 010==44.1, 011=48, */
513 #define HDSPM_wc_freq2 (1<<7)   /* 100=64, 101=88.2, 110=96, 111=128 */
514 #define HDSPM_wc_freq3 0x800    /* 1000=176.4, 1001=192 */
515 
516 #define HDSPM_SyncRef0 0x10000  /* Sync Reference */
517 #define HDSPM_SyncRef1 0x20000
518 
519 #define HDSPM_SelSyncRef0 (1<<8)        /* AutoSync Source */
520 #define HDSPM_SelSyncRef1 (1<<9)        /* 000=word, 001=MADI, */
521 #define HDSPM_SelSyncRef2 (1<<10)       /* 111=no valid signal */
522 
523 #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync)
524 
525 #define HDSPM_wcFreqMask  (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2|\
526                             HDSPM_wc_freq3)
527 #define HDSPM_wcFreq32    (HDSPM_wc_freq0)
528 #define HDSPM_wcFreq44_1  (HDSPM_wc_freq1)
529 #define HDSPM_wcFreq48    (HDSPM_wc_freq0|HDSPM_wc_freq1)
530 #define HDSPM_wcFreq64    (HDSPM_wc_freq2)
531 #define HDSPM_wcFreq88_2  (HDSPM_wc_freq0|HDSPM_wc_freq2)
532 #define HDSPM_wcFreq96    (HDSPM_wc_freq1|HDSPM_wc_freq2)
533 #define HDSPM_wcFreq128   (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2)
534 #define HDSPM_wcFreq176_4 (HDSPM_wc_freq3)
535 #define HDSPM_wcFreq192   (HDSPM_wc_freq0|HDSPM_wc_freq3)
536 
537 #define HDSPM_status1_F_0 0x0400000
538 #define HDSPM_status1_F_1 0x0800000
539 #define HDSPM_status1_F_2 0x1000000
540 #define HDSPM_status1_F_3 0x2000000
541 #define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3)
542 
543 
544 #define HDSPM_SelSyncRefMask       (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
545                                     HDSPM_SelSyncRef2)
546 #define HDSPM_SelSyncRef_WORD      0
547 #define HDSPM_SelSyncRef_MADI      (HDSPM_SelSyncRef0)
548 #define HDSPM_SelSyncRef_TCO       (HDSPM_SelSyncRef1)
549 #define HDSPM_SelSyncRef_SyncIn    (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1)
550 #define HDSPM_SelSyncRef_NVALID    (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
551                                     HDSPM_SelSyncRef2)
552 
553 /*
554    For AES32, bits for status, status2 and timecode are different
555 */
556 /* status */
557 #define HDSPM_AES32_wcLock      0x0200000
558 #define HDSPM_AES32_wcSync      0x0100000
559 #define HDSPM_AES32_wcFreq_bit  22
560 /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function
561   HDSPM_bit2freq */
562 #define HDSPM_AES32_syncref_bit  16
563 /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */
564 
565 #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0
566 #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1
567 #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2
568 #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3
569 #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4
570 #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5
571 #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6
572 #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7
573 #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8
574 #define HDSPM_AES32_AUTOSYNC_FROM_TCO 9
575 #define HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN 10
576 #define HDSPM_AES32_AUTOSYNC_FROM_NONE 11
577 
578 /*  status2 */
579 /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */
580 #define HDSPM_LockAES   0x80
581 #define HDSPM_LockAES1  0x80
582 #define HDSPM_LockAES2  0x40
583 #define HDSPM_LockAES3  0x20
584 #define HDSPM_LockAES4  0x10
585 #define HDSPM_LockAES5  0x8
586 #define HDSPM_LockAES6  0x4
587 #define HDSPM_LockAES7  0x2
588 #define HDSPM_LockAES8  0x1
589 /*
590    Timecode
591    After windows driver sources, bits 4*i to 4*i+3 give the input frequency on
592    AES i+1
593  bits 3210
594       0001  32kHz
595       0010  44.1kHz
596       0011  48kHz
597       0100  64kHz
598       0101  88.2kHz
599       0110  96kHz
600       0111  128kHz
601       1000  176.4kHz
602       1001  192kHz
603   NB: Timecode register doesn't seem to work on AES32 card revision 230
604 */
605 
606 /* Mixer Values */
607 #define UNITY_GAIN          32768       /* = 65536/2 */
608 #define MINUS_INFINITY_GAIN 0
609 
610 /* Number of channels for different Speed Modes */
611 #define MADI_SS_CHANNELS       64
612 #define MADI_DS_CHANNELS       32
613 #define MADI_QS_CHANNELS       16
614 
615 #define RAYDAT_SS_CHANNELS     36
616 #define RAYDAT_DS_CHANNELS     20
617 #define RAYDAT_QS_CHANNELS     12
618 
619 #define AIO_IN_SS_CHANNELS        14
620 #define AIO_IN_DS_CHANNELS        10
621 #define AIO_IN_QS_CHANNELS        8
622 #define AIO_OUT_SS_CHANNELS        16
623 #define AIO_OUT_DS_CHANNELS        12
624 #define AIO_OUT_QS_CHANNELS        10
625 
626 #define AES32_CHANNELS          16
627 
628 /* the size of a substream (1 mono data stream) */
629 #define HDSPM_CHANNEL_BUFFER_SAMPLES  (16*1024)
630 #define HDSPM_CHANNEL_BUFFER_BYTES    (4*HDSPM_CHANNEL_BUFFER_SAMPLES)
631 
632 /* the size of the area we need to allocate for DMA transfers. the
633    size is the same regardless of the number of channels, and
634    also the latency to use.
635    for one direction !!!
636 */
637 #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES)
638 #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024)
639 
640 #define HDSPM_RAYDAT_REV        211
641 #define HDSPM_AIO_REV           212
642 #define HDSPM_MADIFACE_REV      213
643 
644 /* speed factor modes */
645 #define HDSPM_SPEED_SINGLE 0
646 #define HDSPM_SPEED_DOUBLE 1
647 #define HDSPM_SPEED_QUAD   2
648 
649 /* names for speed modes */
650 static char *hdspm_speed_names[] = { "single", "double", "quad" };
651 
652 static const char *const texts_autosync_aes_tco[] = { "Word Clock",
653                                           "AES1", "AES2", "AES3", "AES4",
654                                           "AES5", "AES6", "AES7", "AES8",
655                                           "TCO", "Sync In"
656 };
657 static const char *const texts_autosync_aes[] = { "Word Clock",
658                                       "AES1", "AES2", "AES3", "AES4",
659                                       "AES5", "AES6", "AES7", "AES8",
660                                       "Sync In"
661 };
662 static const char *const texts_autosync_madi_tco[] = { "Word Clock",
663                                            "MADI", "TCO", "Sync In" };
664 static const char *const texts_autosync_madi[] = { "Word Clock",
665                                        "MADI", "Sync In" };
666 
667 static const char *const texts_autosync_raydat_tco[] = {
668         "Word Clock",
669         "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
670         "AES", "SPDIF", "TCO", "Sync In"
671 };
672 static const char *const texts_autosync_raydat[] = {
673         "Word Clock",
674         "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
675         "AES", "SPDIF", "Sync In"
676 };
677 static const char *const texts_autosync_aio_tco[] = {
678         "Word Clock",
679         "ADAT", "AES", "SPDIF", "TCO", "Sync In"
680 };
681 static const char *const texts_autosync_aio[] = { "Word Clock",
682                                       "ADAT", "AES", "SPDIF", "Sync In" };
683 
684 static const char *const texts_freq[] = {
685         "No Lock",
686         "32 kHz",
687         "44.1 kHz",
688         "48 kHz",
689         "64 kHz",
690         "88.2 kHz",
691         "96 kHz",
692         "128 kHz",
693         "176.4 kHz",
694         "192 kHz"
695 };
696 
697 static char *texts_ports_madi[] = {
698         "MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6",
699         "MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12",
700         "MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18",
701         "MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24",
702         "MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30",
703         "MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36",
704         "MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42",
705         "MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48",
706         "MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54",
707         "MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60",
708         "MADI.61", "MADI.62", "MADI.63", "MADI.64",
709 };
710 
711 
712 static char *texts_ports_raydat_ss[] = {
713         "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6",
714         "ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
715         "ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2",
716         "ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8",
717         "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6",
718         "ADAT4.7", "ADAT4.8",
719         "AES.L", "AES.R",
720         "SPDIF.L", "SPDIF.R"
721 };
722 
723 static char *texts_ports_raydat_ds[] = {
724         "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4",
725         "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
726         "ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4",
727         "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4",
728         "AES.L", "AES.R",
729         "SPDIF.L", "SPDIF.R"
730 };
731 
732 static char *texts_ports_raydat_qs[] = {
733         "ADAT1.1", "ADAT1.2",
734         "ADAT2.1", "ADAT2.2",
735         "ADAT3.1", "ADAT3.2",
736         "ADAT4.1", "ADAT4.2",
737         "AES.L", "AES.R",
738         "SPDIF.L", "SPDIF.R"
739 };
740 
741 
742 static char *texts_ports_aio_in_ss[] = {
743         "Analogue.L", "Analogue.R",
744         "AES.L", "AES.R",
745         "SPDIF.L", "SPDIF.R",
746         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
747         "ADAT.7", "ADAT.8",
748         "AEB.1", "AEB.2", "AEB.3", "AEB.4"
749 };
750 
751 static char *texts_ports_aio_out_ss[] = {
752         "Analogue.L", "Analogue.R",
753         "AES.L", "AES.R",
754         "SPDIF.L", "SPDIF.R",
755         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
756         "ADAT.7", "ADAT.8",
757         "Phone.L", "Phone.R",
758         "AEB.1", "AEB.2", "AEB.3", "AEB.4"
759 };
760 
761 static char *texts_ports_aio_in_ds[] = {
762         "Analogue.L", "Analogue.R",
763         "AES.L", "AES.R",
764         "SPDIF.L", "SPDIF.R",
765         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
766         "AEB.1", "AEB.2", "AEB.3", "AEB.4"
767 };
768 
769 static char *texts_ports_aio_out_ds[] = {
770         "Analogue.L", "Analogue.R",
771         "AES.L", "AES.R",
772         "SPDIF.L", "SPDIF.R",
773         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
774         "Phone.L", "Phone.R",
775         "AEB.1", "AEB.2", "AEB.3", "AEB.4"
776 };
777 
778 static char *texts_ports_aio_in_qs[] = {
779         "Analogue.L", "Analogue.R",
780         "AES.L", "AES.R",
781         "SPDIF.L", "SPDIF.R",
782         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
783         "AEB.1", "AEB.2", "AEB.3", "AEB.4"
784 };
785 
786 static char *texts_ports_aio_out_qs[] = {
787         "Analogue.L", "Analogue.R",
788         "AES.L", "AES.R",
789         "SPDIF.L", "SPDIF.R",
790         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
791         "Phone.L", "Phone.R",
792         "AEB.1", "AEB.2", "AEB.3", "AEB.4"
793 };
794 
795 static char *texts_ports_aes32[] = {
796         "AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7",
797         "AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14",
798         "AES.15", "AES.16"
799 };
800 
801 /* These tables map the ALSA channels 1..N to the channels that we
802    need to use in order to find the relevant channel buffer. RME
803    refers to this kind of mapping as between "the ADAT channel and
804    the DMA channel." We index it using the logical audio channel,
805    and the value is the DMA channel (i.e. channel buffer number)
806    where the data for that channel can be read/written from/to.
807 */
808 
809 static char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = {
810         0, 1, 2, 3, 4, 5, 6, 7,
811         8, 9, 10, 11, 12, 13, 14, 15,
812         16, 17, 18, 19, 20, 21, 22, 23,
813         24, 25, 26, 27, 28, 29, 30, 31,
814         32, 33, 34, 35, 36, 37, 38, 39,
815         40, 41, 42, 43, 44, 45, 46, 47,
816         48, 49, 50, 51, 52, 53, 54, 55,
817         56, 57, 58, 59, 60, 61, 62, 63
818 };
819 
820 static char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = {
821         4, 5, 6, 7, 8, 9, 10, 11,       /* ADAT 1 */
822         12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */
823         20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */
824         28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */
825         0, 1,                   /* AES */
826         2, 3,                   /* SPDIF */
827         -1, -1, -1, -1,
828         -1, -1, -1, -1, -1, -1, -1, -1,
829         -1, -1, -1, -1, -1, -1, -1, -1,
830         -1, -1, -1, -1, -1, -1, -1, -1,
831 };
832 
833 static char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = {
834         4, 5, 6, 7,             /* ADAT 1 */
835         8, 9, 10, 11,           /* ADAT 2 */
836         12, 13, 14, 15,         /* ADAT 3 */
837         16, 17, 18, 19,         /* ADAT 4 */
838         0, 1,                   /* AES */
839         2, 3,                   /* SPDIF */
840         -1, -1, -1, -1,
841         -1, -1, -1, -1, -1, -1, -1, -1,
842         -1, -1, -1, -1, -1, -1, -1, -1,
843         -1, -1, -1, -1, -1, -1, -1, -1,
844         -1, -1, -1, -1, -1, -1, -1, -1,
845         -1, -1, -1, -1, -1, -1, -1, -1,
846 };
847 
848 static char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = {
849         4, 5,                   /* ADAT 1 */
850         6, 7,                   /* ADAT 2 */
851         8, 9,                   /* ADAT 3 */
852         10, 11,                 /* ADAT 4 */
853         0, 1,                   /* AES */
854         2, 3,                   /* SPDIF */
855         -1, -1, -1, -1,
856         -1, -1, -1, -1, -1, -1, -1, -1,
857         -1, -1, -1, -1, -1, -1, -1, -1,
858         -1, -1, -1, -1, -1, -1, -1, -1,
859         -1, -1, -1, -1, -1, -1, -1, -1,
860         -1, -1, -1, -1, -1, -1, -1, -1,
861         -1, -1, -1, -1, -1, -1, -1, -1,
862 };
863 
864 static char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = {
865         0, 1,                   /* line in */
866         8, 9,                   /* aes in, */
867         10, 11,                 /* spdif in */
868         12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */
869         2, 3, 4, 5,             /* AEB */
870         -1, -1, -1, -1, -1, -1,
871         -1, -1, -1, -1, -1, -1, -1, -1,
872         -1, -1, -1, -1, -1, -1, -1, -1,
873         -1, -1, -1, -1, -1, -1, -1, -1,
874         -1, -1, -1, -1, -1, -1, -1, -1,
875         -1, -1, -1, -1, -1, -1, -1, -1,
876 };
877 
878 static char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = {
879         0, 1,                   /* line out */
880         8, 9,                   /* aes out */
881         10, 11,                 /* spdif out */
882         12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */
883         6, 7,                   /* phone out */
884         2, 3, 4, 5,             /* AEB */
885         -1, -1, -1, -1,
886         -1, -1, -1, -1, -1, -1, -1, -1,
887         -1, -1, -1, -1, -1, -1, -1, -1,
888         -1, -1, -1, -1, -1, -1, -1, -1,
889         -1, -1, -1, -1, -1, -1, -1, -1,
890         -1, -1, -1, -1, -1, -1, -1, -1,
891 };
892 
893 static char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = {
894         0, 1,                   /* line in */
895         8, 9,                   /* aes in */
896         10, 11,                 /* spdif in */
897         12, 14, 16, 18,         /* adat in */
898         2, 3, 4, 5,             /* AEB */
899         -1, -1,
900         -1, -1, -1, -1, -1, -1, -1, -1,
901         -1, -1, -1, -1, -1, -1, -1, -1,
902         -1, -1, -1, -1, -1, -1, -1, -1,
903         -1, -1, -1, -1, -1, -1, -1, -1,
904         -1, -1, -1, -1, -1, -1, -1, -1,
905         -1, -1, -1, -1, -1, -1, -1, -1
906 };
907 
908 static char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = {
909         0, 1,                   /* line out */
910         8, 9,                   /* aes out */
911         10, 11,                 /* spdif out */
912         12, 14, 16, 18,         /* adat out */
913         6, 7,                   /* phone out */
914         2, 3, 4, 5,             /* AEB */
915         -1, -1, -1, -1, -1, -1, -1, -1,
916         -1, -1, -1, -1, -1, -1, -1, -1,
917         -1, -1, -1, -1, -1, -1, -1, -1,
918         -1, -1, -1, -1, -1, -1, -1, -1,
919         -1, -1, -1, -1, -1, -1, -1, -1,
920         -1, -1, -1, -1, -1, -1, -1, -1
921 };
922 
923 static char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = {
924         0, 1,                   /* line in */
925         8, 9,                   /* aes in */
926         10, 11,                 /* spdif in */
927         12, 16,                 /* adat in */
928         2, 3, 4, 5,             /* AEB */
929         -1, -1, -1, -1,
930         -1, -1, -1, -1, -1, -1, -1, -1,
931         -1, -1, -1, -1, -1, -1, -1, -1,
932         -1, -1, -1, -1, -1, -1, -1, -1,
933         -1, -1, -1, -1, -1, -1, -1, -1,
934         -1, -1, -1, -1, -1, -1, -1, -1,
935         -1, -1, -1, -1, -1, -1, -1, -1
936 };
937 
938 static char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = {
939         0, 1,                   /* line out */
940         8, 9,                   /* aes out */
941         10, 11,                 /* spdif out */
942         12, 16,                 /* adat out */
943         6, 7,                   /* phone out */
944         2, 3, 4, 5,             /* AEB */
945         -1, -1,
946         -1, -1, -1, -1, -1, -1, -1, -1,
947         -1, -1, -1, -1, -1, -1, -1, -1,
948         -1, -1, -1, -1, -1, -1, -1, -1,
949         -1, -1, -1, -1, -1, -1, -1, -1,
950         -1, -1, -1, -1, -1, -1, -1, -1,
951         -1, -1, -1, -1, -1, -1, -1, -1
952 };
953 
954 static char channel_map_aes32[HDSPM_MAX_CHANNELS] = {
955         0, 1, 2, 3, 4, 5, 6, 7,
956         8, 9, 10, 11, 12, 13, 14, 15,
957         -1, -1, -1, -1, -1, -1, -1, -1,
958         -1, -1, -1, -1, -1, -1, -1, -1,
959         -1, -1, -1, -1, -1, -1, -1, -1,
960         -1, -1, -1, -1, -1, -1, -1, -1,
961         -1, -1, -1, -1, -1, -1, -1, -1,
962         -1, -1, -1, -1, -1, -1, -1, -1
963 };
964 
965 struct hdspm_midi {
966         struct hdspm *hdspm;
967         int id;
968         struct snd_rawmidi *rmidi;
969         struct snd_rawmidi_substream *input;
970         struct snd_rawmidi_substream *output;
971         char istimer;           /* timer in use */
972         struct timer_list timer;
973         spinlock_t lock;
974         int pending;
975         int dataIn;
976         int statusIn;
977         int dataOut;
978         int statusOut;
979         int ie;
980         int irq;
981 };
982 
983 struct hdspm_tco {
984         int input; /* 0: LTC, 1:Video, 2: WC*/
985         int framerate; /* 0=24, 1=25, 2=29.97, 3=29.97d, 4=30, 5=30d */
986         int wordclock; /* 0=1:1, 1=44.1->48, 2=48->44.1 */
987         int samplerate; /* 0=44.1, 1=48, 2= freq from app */
988         int pull; /*   0=0, 1=+0.1%, 2=-0.1%, 3=+4%, 4=-4%*/
989         int term; /* 0 = off, 1 = on */
990 };
991 
992 struct hdspm {
993         spinlock_t lock;
994         /* only one playback and/or capture stream */
995         struct snd_pcm_substream *capture_substream;
996         struct snd_pcm_substream *playback_substream;
997 
998         char *card_name;             /* for procinfo */
999         unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/
1000 
1001         uint8_t io_type;
1002 
1003         int monitor_outs;       /* set up monitoring outs init flag */
1004 
1005         u32 control_register;   /* cached value */
1006         u32 control2_register;  /* cached value */
1007         u32 settings_register;  /* cached value for AIO / RayDat (sync reference, master/slave) */
1008 
1009         struct hdspm_midi midi[4];
1010         struct tasklet_struct midi_tasklet;
1011 
1012         size_t period_bytes;
1013         unsigned char ss_in_channels;
1014         unsigned char ds_in_channels;
1015         unsigned char qs_in_channels;
1016         unsigned char ss_out_channels;
1017         unsigned char ds_out_channels;
1018         unsigned char qs_out_channels;
1019 
1020         unsigned char max_channels_in;
1021         unsigned char max_channels_out;
1022 
1023         signed char *channel_map_in;
1024         signed char *channel_map_out;
1025 
1026         signed char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs;
1027         signed char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs;
1028 
1029         char **port_names_in;
1030         char **port_names_out;
1031 
1032         char **port_names_in_ss, **port_names_in_ds, **port_names_in_qs;
1033         char **port_names_out_ss, **port_names_out_ds, **port_names_out_qs;
1034 
1035         unsigned char *playback_buffer; /* suitably aligned address */
1036         unsigned char *capture_buffer;  /* suitably aligned address */
1037 
1038         pid_t capture_pid;      /* process id which uses capture */
1039         pid_t playback_pid;     /* process id which uses capture */
1040         int running;            /* running status */
1041 
1042         int last_external_sample_rate;  /* samplerate mystic ... */
1043         int last_internal_sample_rate;
1044         int system_sample_rate;
1045 
1046         int dev;                /* Hardware vars... */
1047         int irq;
1048         unsigned long port;
1049         void __iomem *iobase;
1050 
1051         int irq_count;          /* for debug */
1052         int midiPorts;
1053 
1054         struct snd_card *card;  /* one card */
1055         struct snd_pcm *pcm;            /* has one pcm */
1056         struct snd_hwdep *hwdep;        /* and a hwdep for additional ioctl */
1057         struct pci_dev *pci;    /* and an pci info */
1058 
1059         /* Mixer vars */
1060         /* fast alsa mixer */
1061         struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS];
1062         /* but input to much, so not used */
1063         struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS];
1064         /* full mixer accessible over mixer ioctl or hwdep-device */
1065         struct hdspm_mixer *mixer;
1066 
1067         struct hdspm_tco *tco;  /* NULL if no TCO detected */
1068 
1069         const char *const *texts_autosync;
1070         int texts_autosync_items;
1071 
1072         cycles_t last_interrupt;
1073 
1074         unsigned int serial;
1075 
1076         struct hdspm_peak_rms peak_rms;
1077 };
1078 
1079 
1080 static DEFINE_PCI_DEVICE_TABLE(snd_hdspm_ids) = {
1081         {
1082          .vendor = PCI_VENDOR_ID_XILINX,
1083          .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI,
1084          .subvendor = PCI_ANY_ID,
1085          .subdevice = PCI_ANY_ID,
1086          .class = 0,
1087          .class_mask = 0,
1088          .driver_data = 0},
1089         {0,}
1090 };
1091 
1092 MODULE_DEVICE_TABLE(pci, snd_hdspm_ids);
1093 
1094 /* prototypes */
1095 static int snd_hdspm_create_alsa_devices(struct snd_card *card,
1096                                          struct hdspm *hdspm);
1097 static int snd_hdspm_create_pcm(struct snd_card *card,
1098                                 struct hdspm *hdspm);
1099 
1100 static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm);
1101 static inline int hdspm_get_pll_freq(struct hdspm *hdspm);
1102 static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm);
1103 static int hdspm_autosync_ref(struct hdspm *hdspm);
1104 static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out);
1105 static int snd_hdspm_set_defaults(struct hdspm *hdspm);
1106 static int hdspm_system_clock_mode(struct hdspm *hdspm);
1107 static void hdspm_set_sgbuf(struct hdspm *hdspm,
1108                             struct snd_pcm_substream *substream,
1109                              unsigned int reg, int channels);
1110 
1111 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx);
1112 static int hdspm_wc_sync_check(struct hdspm *hdspm);
1113 static int hdspm_tco_sync_check(struct hdspm *hdspm);
1114 static int hdspm_sync_in_sync_check(struct hdspm *hdspm);
1115 
1116 static int hdspm_get_aes_sample_rate(struct hdspm *hdspm, int index);
1117 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm);
1118 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm);
1119 
1120 
1121 
1122 static inline int HDSPM_bit2freq(int n)
1123 {
1124         static const int bit2freq_tab[] = {
1125                 0, 32000, 44100, 48000, 64000, 88200,
1126                 96000, 128000, 176400, 192000 };
1127         if (n < 1 || n > 9)
1128                 return 0;
1129         return bit2freq_tab[n];
1130 }
1131 
1132 static bool hdspm_is_raydat_or_aio(struct hdspm *hdspm)
1133 {
1134         return ((AIO == hdspm->io_type) || (RayDAT == hdspm->io_type));
1135 }
1136 
1137 
1138 /* Write/read to/from HDSPM with Adresses in Bytes
1139    not words but only 32Bit writes are allowed */
1140 
1141 static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg,
1142                                unsigned int val)
1143 {
1144         writel(val, hdspm->iobase + reg);
1145 }
1146 
1147 static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg)
1148 {
1149         return readl(hdspm->iobase + reg);
1150 }
1151 
1152 /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader
1153    mixer is write only on hardware so we have to cache him for read
1154    each fader is a u32, but uses only the first 16 bit */
1155 
1156 static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan,
1157                                      unsigned int in)
1158 {
1159         if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1160                 return 0;
1161 
1162         return hdspm->mixer->ch[chan].in[in];
1163 }
1164 
1165 static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan,
1166                                      unsigned int pb)
1167 {
1168         if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1169                 return 0;
1170         return hdspm->mixer->ch[chan].pb[pb];
1171 }
1172 
1173 static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan,
1174                                       unsigned int in, unsigned short data)
1175 {
1176         if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1177                 return -1;
1178 
1179         hdspm_write(hdspm,
1180                     HDSPM_MADI_mixerBase +
1181                     ((in + 128 * chan) * sizeof(u32)),
1182                     (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF));
1183         return 0;
1184 }
1185 
1186 static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan,
1187                                       unsigned int pb, unsigned short data)
1188 {
1189         if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1190                 return -1;
1191 
1192         hdspm_write(hdspm,
1193                     HDSPM_MADI_mixerBase +
1194                     ((64 + pb + 128 * chan) * sizeof(u32)),
1195                     (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF));
1196         return 0;
1197 }
1198 
1199 
1200 /* enable DMA for specific channels, now available for DSP-MADI */
1201 static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v)
1202 {
1203         hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v);
1204 }
1205 
1206 static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v)
1207 {
1208         hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v);
1209 }
1210 
1211 /* check if same process is writing and reading */
1212 static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm)
1213 {
1214         unsigned long flags;
1215         int ret = 1;
1216 
1217         spin_lock_irqsave(&hdspm->lock, flags);
1218         if ((hdspm->playback_pid != hdspm->capture_pid) &&
1219             (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) {
1220                 ret = 0;
1221         }
1222         spin_unlock_irqrestore(&hdspm->lock, flags);
1223         return ret;
1224 }
1225 
1226 /* round arbitary sample rates to commonly known rates */
1227 static int hdspm_round_frequency(int rate)
1228 {
1229         if (rate < 38050)
1230                 return 32000;
1231         if (rate < 46008)
1232                 return 44100;
1233         else
1234                 return 48000;
1235 }
1236 
1237 /* QS and DS rates normally can not be detected
1238  * automatically by the card. Only exception is MADI
1239  * in 96k frame mode.
1240  *
1241  * So if we read SS values (32 .. 48k), check for
1242  * user-provided DS/QS bits in the control register
1243  * and multiply the base frequency accordingly.
1244  */
1245 static int hdspm_rate_multiplier(struct hdspm *hdspm, int rate)
1246 {
1247         if (rate <= 48000) {
1248                 if (hdspm->control_register & HDSPM_QuadSpeed)
1249                         return rate * 4;
1250                 else if (hdspm->control_register &
1251                                 HDSPM_DoubleSpeed)
1252                         return rate * 2;
1253         }
1254         return rate;
1255 }
1256 
1257 /* check for external sample rate, returns the sample rate in Hz*/
1258 static int hdspm_external_sample_rate(struct hdspm *hdspm)
1259 {
1260         unsigned int status, status2, timecode;
1261         int syncref, rate = 0, rate_bits;
1262 
1263         switch (hdspm->io_type) {
1264         case AES32:
1265                 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1266                 status = hdspm_read(hdspm, HDSPM_statusRegister);
1267                 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
1268 
1269                 syncref = hdspm_autosync_ref(hdspm);
1270                 switch (syncref) {
1271                 case HDSPM_AES32_AUTOSYNC_FROM_WORD:
1272                 /* Check WC sync and get sample rate */
1273                         if (hdspm_wc_sync_check(hdspm))
1274                                 return HDSPM_bit2freq(hdspm_get_wc_sample_rate(hdspm));
1275                         break;
1276 
1277                 case HDSPM_AES32_AUTOSYNC_FROM_AES1:
1278                 case HDSPM_AES32_AUTOSYNC_FROM_AES2:
1279                 case HDSPM_AES32_AUTOSYNC_FROM_AES3:
1280                 case HDSPM_AES32_AUTOSYNC_FROM_AES4:
1281                 case HDSPM_AES32_AUTOSYNC_FROM_AES5:
1282                 case HDSPM_AES32_AUTOSYNC_FROM_AES6:
1283                 case HDSPM_AES32_AUTOSYNC_FROM_AES7:
1284                 case HDSPM_AES32_AUTOSYNC_FROM_AES8:
1285                 /* Check AES sync and get sample rate */
1286                         if (hdspm_aes_sync_check(hdspm, syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1))
1287                                 return HDSPM_bit2freq(hdspm_get_aes_sample_rate(hdspm,
1288                                                         syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1));
1289                         break;
1290 
1291 
1292                 case HDSPM_AES32_AUTOSYNC_FROM_TCO:
1293                 /* Check TCO sync and get sample rate */
1294                         if (hdspm_tco_sync_check(hdspm))
1295                                 return HDSPM_bit2freq(hdspm_get_tco_sample_rate(hdspm));
1296                         break;
1297                 default:
1298                         return 0;
1299                 } /* end switch(syncref) */
1300                 break;
1301 
1302         case MADIface:
1303                 status = hdspm_read(hdspm, HDSPM_statusRegister);
1304 
1305                 if (!(status & HDSPM_madiLock)) {
1306                         rate = 0;  /* no lock */
1307                 } else {
1308                         switch (status & (HDSPM_status1_freqMask)) {
1309                         case HDSPM_status1_F_0*1:
1310                                 rate = 32000; break;
1311                         case HDSPM_status1_F_0*2:
1312                                 rate = 44100; break;
1313                         case HDSPM_status1_F_0*3:
1314                                 rate = 48000; break;
1315                         case HDSPM_status1_F_0*4:
1316                                 rate = 64000; break;
1317                         case HDSPM_status1_F_0*5:
1318                                 rate = 88200; break;
1319                         case HDSPM_status1_F_0*6:
1320                                 rate = 96000; break;
1321                         case HDSPM_status1_F_0*7:
1322                                 rate = 128000; break;
1323                         case HDSPM_status1_F_0*8:
1324                                 rate = 176400; break;
1325                         case HDSPM_status1_F_0*9:
1326                                 rate = 192000; break;
1327                         default:
1328                                 rate = 0; break;
1329                         }
1330                 }
1331 
1332                 break;
1333 
1334         case MADI:
1335         case AIO:
1336         case RayDAT:
1337                 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1338                 status = hdspm_read(hdspm, HDSPM_statusRegister);
1339                 rate = 0;
1340 
1341                 /* if wordclock has synced freq and wordclock is valid */
1342                 if ((status2 & HDSPM_wcLock) != 0 &&
1343                                 (status2 & HDSPM_SelSyncRef0) == 0) {
1344 
1345                         rate_bits = status2 & HDSPM_wcFreqMask;
1346 
1347 
1348                         switch (rate_bits) {
1349                         case HDSPM_wcFreq32:
1350                                 rate = 32000;
1351                                 break;
1352                         case HDSPM_wcFreq44_1:
1353                                 rate = 44100;
1354                                 break;
1355                         case HDSPM_wcFreq48:
1356                                 rate = 48000;
1357                                 break;
1358                         case HDSPM_wcFreq64:
1359                                 rate = 64000;
1360                                 break;
1361                         case HDSPM_wcFreq88_2:
1362                                 rate = 88200;
1363                                 break;
1364                         case HDSPM_wcFreq96:
1365                                 rate = 96000;
1366                                 break;
1367                         case HDSPM_wcFreq128:
1368                                 rate = 128000;
1369                                 break;
1370                         case HDSPM_wcFreq176_4:
1371                                 rate = 176400;
1372                                 break;
1373                         case HDSPM_wcFreq192:
1374                                 rate = 192000;
1375                                 break;
1376                         default:
1377                                 rate = 0;
1378                                 break;
1379                         }
1380                 }
1381 
1382                 /* if rate detected and Syncref is Word than have it,
1383                  * word has priority to MADI
1384                  */
1385                 if (rate != 0 &&
1386                 (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD)
1387                         return hdspm_rate_multiplier(hdspm, rate);
1388 
1389                 /* maybe a madi input (which is taken if sel sync is madi) */
1390                 if (status & HDSPM_madiLock) {
1391                         rate_bits = status & HDSPM_madiFreqMask;
1392 
1393                         switch (rate_bits) {
1394                         case HDSPM_madiFreq32:
1395                                 rate = 32000;
1396                                 break;
1397                         case HDSPM_madiFreq44_1:
1398                                 rate = 44100;
1399                                 break;
1400                         case HDSPM_madiFreq48:
1401                                 rate = 48000;
1402                                 break;
1403                         case HDSPM_madiFreq64:
1404                                 rate = 64000;
1405                                 break;
1406                         case HDSPM_madiFreq88_2:
1407                                 rate = 88200;
1408                                 break;
1409                         case HDSPM_madiFreq96:
1410                                 rate = 96000;
1411                                 break;
1412                         case HDSPM_madiFreq128:
1413                                 rate = 128000;
1414                                 break;
1415                         case HDSPM_madiFreq176_4:
1416                                 rate = 176400;
1417                                 break;
1418                         case HDSPM_madiFreq192:
1419                                 rate = 192000;
1420                                 break;
1421                         default:
1422                                 rate = 0;
1423                                 break;
1424                         }
1425 
1426                 } /* endif HDSPM_madiLock */
1427 
1428                 /* check sample rate from TCO or SYNC_IN */
1429                 {
1430                         bool is_valid_input = 0;
1431                         bool has_sync = 0;
1432 
1433                         syncref = hdspm_autosync_ref(hdspm);
1434                         if (HDSPM_AUTOSYNC_FROM_TCO == syncref) {
1435                                 is_valid_input = 1;
1436                                 has_sync = (HDSPM_SYNC_CHECK_SYNC ==
1437                                         hdspm_tco_sync_check(hdspm));
1438                         } else if (HDSPM_AUTOSYNC_FROM_SYNC_IN == syncref) {
1439                                 is_valid_input = 1;
1440                                 has_sync = (HDSPM_SYNC_CHECK_SYNC ==
1441                                         hdspm_sync_in_sync_check(hdspm));
1442                         }
1443 
1444                         if (is_valid_input && has_sync) {
1445                                 rate = hdspm_round_frequency(
1446                                         hdspm_get_pll_freq(hdspm));
1447                         }
1448                 }
1449 
1450                 rate = hdspm_rate_multiplier(hdspm, rate);
1451 
1452                 break;
1453         }
1454 
1455         return rate;
1456 }
1457 
1458 /* return latency in samples per period */
1459 static int hdspm_get_latency(struct hdspm *hdspm)
1460 {
1461         int n;
1462 
1463         n = hdspm_decode_latency(hdspm->control_register);
1464 
1465         /* Special case for new RME cards with 32 samples period size.
1466          * The three latency bits in the control register
1467          * (HDSP_LatencyMask) encode latency values of 64 samples as
1468          * 0, 128 samples as 1 ... 4096 samples as 6. For old cards, 7
1469          * denotes 8192 samples, but on new cards like RayDAT or AIO,
1470          * it corresponds to 32 samples.
1471          */
1472         if ((7 == n) && (RayDAT == hdspm->io_type || AIO == hdspm->io_type))
1473                 n = -1;
1474 
1475         return 1 << (n + 6);
1476 }
1477 
1478 /* Latency function */
1479 static inline void hdspm_compute_period_size(struct hdspm *hdspm)
1480 {
1481         hdspm->period_bytes = 4 * hdspm_get_latency(hdspm);
1482 }
1483 
1484 
1485 static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm)
1486 {
1487         int position;
1488 
1489         position = hdspm_read(hdspm, HDSPM_statusRegister);
1490 
1491         switch (hdspm->io_type) {
1492         case RayDAT:
1493         case AIO:
1494                 position &= HDSPM_BufferPositionMask;
1495                 position /= 4; /* Bytes per sample */
1496                 break;
1497         default:
1498                 position = (position & HDSPM_BufferID) ?
1499                         (hdspm->period_bytes / 4) : 0;
1500         }
1501 
1502         return position;
1503 }
1504 
1505 
1506 static inline void hdspm_start_audio(struct hdspm * s)
1507 {
1508         s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start);
1509         hdspm_write(s, HDSPM_controlRegister, s->control_register);
1510 }
1511 
1512 static inline void hdspm_stop_audio(struct hdspm * s)
1513 {
1514         s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable);
1515         hdspm_write(s, HDSPM_controlRegister, s->control_register);
1516 }
1517 
1518 /* should I silence all or only opened ones ? doit all for first even is 4MB*/
1519 static void hdspm_silence_playback(struct hdspm *hdspm)
1520 {
1521         int i;
1522         int n = hdspm->period_bytes;
1523         void *buf = hdspm->playback_buffer;
1524 
1525         if (buf == NULL)
1526                 return;
1527 
1528         for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
1529                 memset(buf, 0, n);
1530                 buf += HDSPM_CHANNEL_BUFFER_BYTES;
1531         }
1532 }
1533 
1534 static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames)
1535 {
1536         int n;
1537 
1538         spin_lock_irq(&s->lock);
1539 
1540         if (32 == frames) {
1541                 /* Special case for new RME cards like RayDAT/AIO which
1542                  * support period sizes of 32 samples. Since latency is
1543                  * encoded in the three bits of HDSP_LatencyMask, we can only
1544                  * have values from 0 .. 7. While 0 still means 64 samples and
1545                  * 6 represents 4096 samples on all cards, 7 represents 8192
1546                  * on older cards and 32 samples on new cards.
1547                  *
1548                  * In other words, period size in samples is calculated by
1549                  * 2^(n+6) with n ranging from 0 .. 7.
1550                  */
1551                 n = 7;
1552         } else {
1553                 frames >>= 7;
1554                 n = 0;
1555                 while (frames) {
1556                         n++;
1557                         frames >>= 1;
1558                 }
1559         }
1560 
1561         s->control_register &= ~HDSPM_LatencyMask;
1562         s->control_register |= hdspm_encode_latency(n);
1563 
1564         hdspm_write(s, HDSPM_controlRegister, s->control_register);
1565 
1566         hdspm_compute_period_size(s);
1567 
1568         spin_unlock_irq(&s->lock);
1569 
1570         return 0;
1571 }
1572 
1573 static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period)
1574 {
1575         u64 freq_const;
1576 
1577         if (period == 0)
1578                 return 0;
1579 
1580         switch (hdspm->io_type) {
1581         case MADI:
1582         case AES32:
1583                 freq_const = 110069313433624ULL;
1584                 break;
1585         case RayDAT:
1586         case AIO:
1587                 freq_const = 104857600000000ULL;
1588                 break;
1589         case MADIface:
1590                 freq_const = 131072000000000ULL;
1591                 break;
1592         default:
1593                 snd_BUG();
1594                 return 0;
1595         }
1596 
1597         return div_u64(freq_const, period);
1598 }
1599 
1600 
1601 static void hdspm_set_dds_value(struct hdspm *hdspm, int rate)
1602 {
1603         u64 n;
1604 
1605         if (snd_BUG_ON(rate <= 0))
1606                 return;
1607 
1608         if (rate >= 112000)
1609                 rate /= 4;
1610         else if (rate >= 56000)
1611                 rate /= 2;
1612 
1613         switch (hdspm->io_type) {
1614         case MADIface:
1615                 n = 131072000000000ULL;  /* 125 MHz */
1616                 break;
1617         case MADI:
1618         case AES32:
1619                 n = 110069313433624ULL;  /* 105 MHz */
1620                 break;
1621         case RayDAT:
1622         case AIO:
1623                 n = 104857600000000ULL;  /* 100 MHz */
1624                 break;
1625         default:
1626                 snd_BUG();
1627                 return;
1628         }
1629 
1630         n = div_u64(n, rate);
1631         /* n should be less than 2^32 for being written to FREQ register */
1632         snd_BUG_ON(n >> 32);
1633         hdspm_write(hdspm, HDSPM_freqReg, (u32)n);
1634 }
1635 
1636 /* dummy set rate lets see what happens */
1637 static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally)
1638 {
1639         int current_rate;
1640         int rate_bits;
1641         int not_set = 0;
1642         int current_speed, target_speed;
1643 
1644         /* ASSUMPTION: hdspm->lock is either set, or there is no need for
1645            it (e.g. during module initialization).
1646          */
1647 
1648         if (!(hdspm->control_register & HDSPM_ClockModeMaster)) {
1649 
1650                 /* SLAVE --- */
1651                 if (called_internally) {
1652 
1653                         /* request from ctl or card initialization
1654                            just make a warning an remember setting
1655                            for future master mode switching */
1656 
1657                         snd_printk(KERN_WARNING "HDSPM: "
1658                                    "Warning: device is not running "
1659                                    "as a clock master.\n");
1660                         not_set = 1;
1661                 } else {
1662 
1663                         /* hw_param request while in AutoSync mode */
1664                         int external_freq =
1665                             hdspm_external_sample_rate(hdspm);
1666 
1667                         if (hdspm_autosync_ref(hdspm) ==
1668                             HDSPM_AUTOSYNC_FROM_NONE) {
1669 
1670                                 snd_printk(KERN_WARNING "HDSPM: "
1671                                            "Detected no Externel Sync \n");
1672                                 not_set = 1;
1673 
1674                         } else if (rate != external_freq) {
1675 
1676                                 snd_printk(KERN_WARNING "HDSPM: "
1677                                            "Warning: No AutoSync source for "
1678                                            "requested rate\n");
1679                                 not_set = 1;
1680                         }
1681                 }
1682         }
1683 
1684         current_rate = hdspm->system_sample_rate;
1685 
1686         /* Changing between Singe, Double and Quad speed is not
1687            allowed if any substreams are open. This is because such a change
1688            causes a shift in the location of the DMA buffers and a reduction
1689            in the number of available buffers.
1690 
1691            Note that a similar but essentially insoluble problem exists for
1692            externally-driven rate changes. All we can do is to flag rate
1693            changes in the read/write routines.
1694          */
1695 
1696         if (current_rate <= 48000)
1697                 current_speed = HDSPM_SPEED_SINGLE;
1698         else if (current_rate <= 96000)
1699                 current_speed = HDSPM_SPEED_DOUBLE;
1700         else
1701                 current_speed = HDSPM_SPEED_QUAD;
1702 
1703         if (rate <= 48000)
1704                 target_speed = HDSPM_SPEED_SINGLE;
1705         else if (rate <= 96000)
1706                 target_speed = HDSPM_SPEED_DOUBLE;
1707         else
1708                 target_speed = HDSPM_SPEED_QUAD;
1709 
1710         switch (rate) {
1711         case 32000:
1712                 rate_bits = HDSPM_Frequency32KHz;
1713                 break;
1714         case 44100:
1715                 rate_bits = HDSPM_Frequency44_1KHz;
1716                 break;
1717         case 48000:
1718                 rate_bits = HDSPM_Frequency48KHz;
1719                 break;
1720         case 64000:
1721                 rate_bits = HDSPM_Frequency64KHz;
1722                 break;
1723         case 88200:
1724                 rate_bits = HDSPM_Frequency88_2KHz;
1725                 break;
1726         case 96000:
1727                 rate_bits = HDSPM_Frequency96KHz;
1728                 break;
1729         case 128000:
1730                 rate_bits = HDSPM_Frequency128KHz;
1731                 break;
1732         case 176400:
1733                 rate_bits = HDSPM_Frequency176_4KHz;
1734                 break;
1735         case 192000:
1736                 rate_bits = HDSPM_Frequency192KHz;
1737                 break;
1738         default:
1739                 return -EINVAL;
1740         }
1741 
1742         if (current_speed != target_speed
1743             && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) {
1744                 snd_printk
1745                     (KERN_ERR "HDSPM: "
1746                      "cannot change from %s speed to %s speed mode "
1747                      "(capture PID = %d, playback PID = %d)\n",
1748                      hdspm_speed_names[current_speed],
1749                      hdspm_speed_names[target_speed],
1750                      hdspm->capture_pid, hdspm->playback_pid);
1751                 return -EBUSY;
1752         }
1753 
1754         hdspm->control_register &= ~HDSPM_FrequencyMask;
1755         hdspm->control_register |= rate_bits;
1756         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1757 
1758         /* For AES32, need to set DDS value in FREQ register
1759            For MADI, also apparently */
1760         hdspm_set_dds_value(hdspm, rate);
1761 
1762         if (AES32 == hdspm->io_type && rate != current_rate)
1763                 hdspm_write(hdspm, HDSPM_eeprom_wr, 0);
1764 
1765         hdspm->system_sample_rate = rate;
1766 
1767         if (rate <= 48000) {
1768                 hdspm->channel_map_in = hdspm->channel_map_in_ss;
1769                 hdspm->channel_map_out = hdspm->channel_map_out_ss;
1770                 hdspm->max_channels_in = hdspm->ss_in_channels;
1771                 hdspm->max_channels_out = hdspm->ss_out_channels;
1772                 hdspm->port_names_in = hdspm->port_names_in_ss;
1773                 hdspm->port_names_out = hdspm->port_names_out_ss;
1774         } else if (rate <= 96000) {
1775                 hdspm->channel_map_in = hdspm->channel_map_in_ds;
1776                 hdspm->channel_map_out = hdspm->channel_map_out_ds;
1777                 hdspm->max_channels_in = hdspm->ds_in_channels;
1778                 hdspm->max_channels_out = hdspm->ds_out_channels;
1779                 hdspm->port_names_in = hdspm->port_names_in_ds;
1780                 hdspm->port_names_out = hdspm->port_names_out_ds;
1781         } else {
1782                 hdspm->channel_map_in = hdspm->channel_map_in_qs;
1783                 hdspm->channel_map_out = hdspm->channel_map_out_qs;
1784                 hdspm->max_channels_in = hdspm->qs_in_channels;
1785                 hdspm->max_channels_out = hdspm->qs_out_channels;
1786                 hdspm->port_names_in = hdspm->port_names_in_qs;
1787                 hdspm->port_names_out = hdspm->port_names_out_qs;
1788         }
1789 
1790         if (not_set != 0)
1791                 return -1;
1792 
1793         return 0;
1794 }
1795 
1796 /* mainly for init to 0 on load */
1797 static void all_in_all_mixer(struct hdspm * hdspm, int sgain)
1798 {
1799         int i, j;
1800         unsigned int gain;
1801 
1802         if (sgain > UNITY_GAIN)
1803                 gain = UNITY_GAIN;
1804         else if (sgain < 0)
1805                 gain = 0;
1806         else
1807                 gain = sgain;
1808 
1809         for (i = 0; i < HDSPM_MIXER_CHANNELS; i++)
1810                 for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) {
1811                         hdspm_write_in_gain(hdspm, i, j, gain);
1812                         hdspm_write_pb_gain(hdspm, i, j, gain);
1813                 }
1814 }
1815 
1816 /*----------------------------------------------------------------------------
1817    MIDI
1818   ----------------------------------------------------------------------------*/
1819 
1820 static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm,
1821                                                       int id)
1822 {
1823         /* the hardware already does the relevant bit-mask with 0xff */
1824         return hdspm_read(hdspm, hdspm->midi[id].dataIn);
1825 }
1826 
1827 static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id,
1828                                               int val)
1829 {
1830         /* the hardware already does the relevant bit-mask with 0xff */
1831         return hdspm_write(hdspm, hdspm->midi[id].dataOut, val);
1832 }
1833 
1834 static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id)
1835 {
1836         return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF;
1837 }
1838 
1839 static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id)
1840 {
1841         int fifo_bytes_used;
1842 
1843         fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF;
1844 
1845         if (fifo_bytes_used < 128)
1846                 return  128 - fifo_bytes_used;
1847         else
1848                 return 0;
1849 }
1850 
1851 static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id)
1852 {
1853         while (snd_hdspm_midi_input_available (hdspm, id))
1854                 snd_hdspm_midi_read_byte (hdspm, id);
1855 }
1856 
1857 static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi)
1858 {
1859         unsigned long flags;
1860         int n_pending;
1861         int to_write;
1862         int i;
1863         unsigned char buf[128];
1864 
1865         /* Output is not interrupt driven */
1866 
1867         spin_lock_irqsave (&hmidi->lock, flags);
1868         if (hmidi->output &&
1869             !snd_rawmidi_transmit_empty (hmidi->output)) {
1870                 n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm,
1871                                                             hmidi->id);
1872                 if (n_pending > 0) {
1873                         if (n_pending > (int)sizeof (buf))
1874                                 n_pending = sizeof (buf);
1875 
1876                         to_write = snd_rawmidi_transmit (hmidi->output, buf,
1877                                                          n_pending);
1878                         if (to_write > 0) {
1879                                 for (i = 0; i < to_write; ++i)
1880                                         snd_hdspm_midi_write_byte (hmidi->hdspm,
1881                                                                    hmidi->id,
1882                                                                    buf[i]);
1883                         }
1884                 }
1885         }
1886         spin_unlock_irqrestore (&hmidi->lock, flags);
1887         return 0;
1888 }
1889 
1890 static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi)
1891 {
1892         unsigned char buf[128]; /* this buffer is designed to match the MIDI
1893                                  * input FIFO size
1894                                  */
1895         unsigned long flags;
1896         int n_pending;
1897         int i;
1898 
1899         spin_lock_irqsave (&hmidi->lock, flags);
1900         n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id);
1901         if (n_pending > 0) {
1902                 if (hmidi->input) {
1903                         if (n_pending > (int)sizeof (buf))
1904                                 n_pending = sizeof (buf);
1905                         for (i = 0; i < n_pending; ++i)
1906                                 buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm,
1907                                                                    hmidi->id);
1908                         if (n_pending)
1909                                 snd_rawmidi_receive (hmidi->input, buf,
1910                                                      n_pending);
1911                 } else {
1912                         /* flush the MIDI input FIFO */
1913                         while (n_pending--)
1914                                 snd_hdspm_midi_read_byte (hmidi->hdspm,
1915                                                           hmidi->id);
1916                 }
1917         }
1918         hmidi->pending = 0;
1919         spin_unlock_irqrestore(&hmidi->lock, flags);
1920 
1921         spin_lock_irqsave(&hmidi->hdspm->lock, flags);
1922         hmidi->hdspm->control_register |= hmidi->ie;
1923         hdspm_write(hmidi->hdspm, HDSPM_controlRegister,
1924                     hmidi->hdspm->control_register);
1925         spin_unlock_irqrestore(&hmidi->hdspm->lock, flags);
1926 
1927         return snd_hdspm_midi_output_write (hmidi);
1928 }
1929 
1930 static void
1931 snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1932 {
1933         struct hdspm *hdspm;
1934         struct hdspm_midi *hmidi;
1935         unsigned long flags;
1936 
1937         hmidi = substream->rmidi->private_data;
1938         hdspm = hmidi->hdspm;
1939 
1940         spin_lock_irqsave (&hdspm->lock, flags);
1941         if (up) {
1942                 if (!(hdspm->control_register & hmidi->ie)) {
1943                         snd_hdspm_flush_midi_input (hdspm, hmidi->id);
1944                         hdspm->control_register |= hmidi->ie;
1945                 }
1946         } else {
1947                 hdspm->control_register &= ~hmidi->ie;
1948         }
1949 
1950         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1951         spin_unlock_irqrestore (&hdspm->lock, flags);
1952 }
1953 
1954 static void snd_hdspm_midi_output_timer(unsigned long data)
1955 {
1956         struct hdspm_midi *hmidi = (struct hdspm_midi *) data;
1957         unsigned long flags;
1958 
1959         snd_hdspm_midi_output_write(hmidi);
1960         spin_lock_irqsave (&hmidi->lock, flags);
1961 
1962         /* this does not bump hmidi->istimer, because the
1963            kernel automatically removed the timer when it
1964            expired, and we are now adding it back, thus
1965            leaving istimer wherever it was set before.
1966         */
1967 
1968         if (hmidi->istimer) {
1969                 hmidi->timer.expires = 1 + jiffies;
1970                 add_timer(&hmidi->timer);
1971         }
1972 
1973         spin_unlock_irqrestore (&hmidi->lock, flags);
1974 }
1975 
1976 static void
1977 snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1978 {
1979         struct hdspm_midi *hmidi;
1980         unsigned long flags;
1981 
1982         hmidi = substream->rmidi->private_data;
1983         spin_lock_irqsave (&hmidi->lock, flags);
1984         if (up) {
1985                 if (!hmidi->istimer) {
1986                         init_timer(&hmidi->timer);
1987                         hmidi->timer.function = snd_hdspm_midi_output_timer;
1988                         hmidi->timer.data = (unsigned long) hmidi;
1989                         hmidi->timer.expires = 1 + jiffies;
1990                         add_timer(&hmidi->timer);
1991                         hmidi->istimer++;
1992                 }
1993         } else {
1994                 if (hmidi->istimer && --hmidi->istimer <= 0)
1995                         del_timer (&hmidi->timer);
1996         }
1997         spin_unlock_irqrestore (&hmidi->lock, flags);
1998         if (up)
1999                 snd_hdspm_midi_output_write(hmidi);
2000 }
2001 
2002 static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream)
2003 {
2004         struct hdspm_midi *hmidi;
2005 
2006         hmidi = substream->rmidi->private_data;
2007         spin_lock_irq (&hmidi->lock);
2008         snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id);
2009         hmidi->input = substream;
2010         spin_unlock_irq (&hmidi->lock);
2011 
2012         return 0;
2013 }
2014 
2015 static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream)
2016 {
2017         struct hdspm_midi *hmidi;
2018 
2019         hmidi = substream->rmidi->private_data;
2020         spin_lock_irq (&hmidi->lock);
2021         hmidi->output = substream;
2022         spin_unlock_irq (&hmidi->lock);
2023 
2024         return 0;
2025 }
2026 
2027 static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream)
2028 {
2029         struct hdspm_midi *hmidi;
2030 
2031         snd_hdspm_midi_input_trigger (substream, 0);
2032 
2033         hmidi = substream->rmidi->private_data;
2034         spin_lock_irq (&hmidi->lock);
2035         hmidi->input = NULL;
2036         spin_unlock_irq (&hmidi->lock);
2037 
2038         return 0;
2039 }
2040 
2041 static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream)
2042 {
2043         struct hdspm_midi *hmidi;
2044 
2045         snd_hdspm_midi_output_trigger (substream, 0);
2046 
2047         hmidi = substream->rmidi->private_data;
2048         spin_lock_irq (&hmidi->lock);
2049         hmidi->output = NULL;
2050         spin_unlock_irq (&hmidi->lock);
2051 
2052         return 0;
2053 }
2054 
2055 static struct snd_rawmidi_ops snd_hdspm_midi_output =
2056 {
2057         .open =         snd_hdspm_midi_output_open,
2058         .close =        snd_hdspm_midi_output_close,
2059         .trigger =      snd_hdspm_midi_output_trigger,
2060 };
2061 
2062 static struct snd_rawmidi_ops snd_hdspm_midi_input =
2063 {
2064         .open =         snd_hdspm_midi_input_open,
2065         .close =        snd_hdspm_midi_input_close,
2066         .trigger =      snd_hdspm_midi_input_trigger,
2067 };
2068 
2069 static int snd_hdspm_create_midi(struct snd_card *card,
2070                                  struct hdspm *hdspm, int id)
2071 {
2072         int err;
2073         char buf[32];
2074 
2075         hdspm->midi[id].id = id;
2076         hdspm->midi[id].hdspm = hdspm;
2077         spin_lock_init (&hdspm->midi[id].lock);
2078 
2079         if (0 == id) {
2080                 if (MADIface == hdspm->io_type) {
2081                         /* MIDI-over-MADI on HDSPe MADIface */
2082                         hdspm->midi[0].dataIn = HDSPM_midiDataIn2;
2083                         hdspm->midi[0].statusIn = HDSPM_midiStatusIn2;
2084                         hdspm->midi[0].dataOut = HDSPM_midiDataOut2;
2085                         hdspm->midi[0].statusOut = HDSPM_midiStatusOut2;
2086                         hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable;
2087                         hdspm->midi[0].irq = HDSPM_midi2IRQPending;
2088                 } else {
2089                         hdspm->midi[0].dataIn = HDSPM_midiDataIn0;
2090                         hdspm->midi[0].statusIn = HDSPM_midiStatusIn0;
2091                         hdspm->midi[0].dataOut = HDSPM_midiDataOut0;
2092                         hdspm->midi[0].statusOut = HDSPM_midiStatusOut0;
2093                         hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable;
2094                         hdspm->midi[0].irq = HDSPM_midi0IRQPending;
2095                 }
2096         } else if (1 == id) {
2097                 hdspm->midi[1].dataIn = HDSPM_midiDataIn1;
2098                 hdspm->midi[1].statusIn = HDSPM_midiStatusIn1;
2099                 hdspm->midi[1].dataOut = HDSPM_midiDataOut1;
2100                 hdspm->midi[1].statusOut = HDSPM_midiStatusOut1;
2101                 hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable;
2102                 hdspm->midi[1].irq = HDSPM_midi1IRQPending;
2103         } else if ((2 == id) && (MADI == hdspm->io_type)) {
2104                 /* MIDI-over-MADI on HDSPe MADI */
2105                 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
2106                 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
2107                 hdspm->midi[2].dataOut = HDSPM_midiDataOut2;
2108                 hdspm->midi[2].statusOut = HDSPM_midiStatusOut2;
2109                 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
2110                 hdspm->midi[2].irq = HDSPM_midi2IRQPending;
2111         } else if (2 == id) {
2112                 /* TCO MTC, read only */
2113                 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
2114                 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
2115                 hdspm->midi[2].dataOut = -1;
2116                 hdspm->midi[2].statusOut = -1;
2117                 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
2118                 hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES;
2119         } else if (3 == id) {
2120                 /* TCO MTC on HDSPe MADI */
2121                 hdspm->midi[3].dataIn = HDSPM_midiDataIn3;
2122                 hdspm->midi[3].statusIn = HDSPM_midiStatusIn3;
2123                 hdspm->midi[3].dataOut = -1;
2124                 hdspm->midi[3].statusOut = -1;
2125                 hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable;
2126                 hdspm->midi[3].irq = HDSPM_midi3IRQPending;
2127         }
2128 
2129         if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) ||
2130                                         (MADIface == hdspm->io_type)))) {
2131                 if ((id == 0) && (MADIface == hdspm->io_type)) {
2132                         sprintf(buf, "%s MIDIoverMADI", card->shortname);
2133                 } else if ((id == 2) && (MADI == hdspm->io_type)) {
2134                         sprintf(buf, "%s MIDIoverMADI", card->shortname);
2135                 } else {
2136                         sprintf(buf, "%s MIDI %d", card->shortname, id+1);
2137                 }
2138                 err = snd_rawmidi_new(card, buf, id, 1, 1,
2139                                 &hdspm->midi[id].rmidi);
2140                 if (err < 0)
2141                         return err;
2142 
2143                 sprintf(hdspm->midi[id].rmidi->name, "%s MIDI %d",
2144                                 card->id, id+1);
2145                 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
2146 
2147                 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2148                                 SNDRV_RAWMIDI_STREAM_OUTPUT,
2149                                 &snd_hdspm_midi_output);
2150                 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2151                                 SNDRV_RAWMIDI_STREAM_INPUT,
2152                                 &snd_hdspm_midi_input);
2153 
2154                 hdspm->midi[id].rmidi->info_flags |=
2155                         SNDRV_RAWMIDI_INFO_OUTPUT |
2156                         SNDRV_RAWMIDI_INFO_INPUT |
2157                         SNDRV_RAWMIDI_INFO_DUPLEX;
2158         } else {
2159                 /* TCO MTC, read only */
2160                 sprintf(buf, "%s MTC %d", card->shortname, id+1);
2161                 err = snd_rawmidi_new(card, buf, id, 1, 1,
2162                                 &hdspm->midi[id].rmidi);
2163                 if (err < 0)
2164                         return err;
2165 
2166                 sprintf(hdspm->midi[id].rmidi->name,
2167                                 "%s MTC %d", card->id, id+1);
2168                 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
2169 
2170                 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2171                                 SNDRV_RAWMIDI_STREAM_INPUT,
2172                                 &snd_hdspm_midi_input);
2173 
2174                 hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT;
2175         }
2176 
2177         return 0;
2178 }
2179 
2180 
2181 static void hdspm_midi_tasklet(unsigned long arg)
2182 {
2183         struct hdspm *hdspm = (struct hdspm *)arg;
2184         int i = 0;
2185 
2186         while (i < hdspm->midiPorts) {
2187                 if (hdspm->midi[i].pending)
2188                         snd_hdspm_midi_input_read(&hdspm->midi[i]);
2189 
2190                 i++;
2191         }
2192 }
2193 
2194 
2195 /*-----------------------------------------------------------------------------
2196   Status Interface
2197   ----------------------------------------------------------------------------*/
2198 
2199 /* get the system sample rate which is set */
2200 
2201 
2202 static inline int hdspm_get_pll_freq(struct hdspm *hdspm)
2203 {
2204         unsigned int period, rate;
2205 
2206         period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
2207         rate = hdspm_calc_dds_value(hdspm, period);
2208 
2209         return rate;
2210 }
2211 
2212 /**
2213  * Calculate the real sample rate from the
2214  * current DDS value.
2215  **/
2216 static int hdspm_get_system_sample_rate(struct hdspm *hdspm)
2217 {
2218         unsigned int rate;
2219 
2220         rate = hdspm_get_pll_freq(hdspm);
2221 
2222         if (rate > 207000) {
2223                 /* Unreasonable high sample rate as seen on PCI MADI cards. */
2224                 if (0 == hdspm_system_clock_mode(hdspm)) {
2225                         /* master mode, return internal sample rate */
2226                         rate = hdspm->system_sample_rate;
2227                 } else {
2228                         /* slave mode, return external sample rate */
2229                         rate = hdspm_external_sample_rate(hdspm);
2230                         if (!rate)
2231                                 rate = hdspm->system_sample_rate;
2232                 }
2233         }
2234 
2235         return rate;
2236 }
2237 
2238 
2239 #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \
2240 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2241         .name = xname, \
2242         .index = xindex, \
2243         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2244                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2245         .info = snd_hdspm_info_system_sample_rate, \
2246         .put = snd_hdspm_put_system_sample_rate, \
2247         .get = snd_hdspm_get_system_sample_rate \
2248 }
2249 
2250 static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol,
2251                                              struct snd_ctl_elem_info *uinfo)
2252 {
2253         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2254         uinfo->count = 1;
2255         uinfo->value.integer.min = 27000;
2256         uinfo->value.integer.max = 207000;
2257         uinfo->value.integer.step = 1;
2258         return 0;
2259 }
2260 
2261 
2262 static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol,
2263                                             struct snd_ctl_elem_value *
2264                                             ucontrol)
2265 {
2266         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2267 
2268         ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm);
2269         return 0;
2270 }
2271 
2272 static int snd_hdspm_put_system_sample_rate(struct snd_kcontrol *kcontrol,
2273                                             struct snd_ctl_elem_value *
2274                                             ucontrol)
2275 {
2276         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2277         int rate = ucontrol->value.integer.value[0];
2278 
2279         if (rate < 27000 || rate > 207000)
2280                 return -EINVAL;
2281         hdspm_set_dds_value(hdspm, ucontrol->value.integer.value[0]);
2282         return 0;
2283 }
2284 
2285 
2286 /**
2287  * Returns the WordClock sample rate class for the given card.
2288  **/
2289 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm)
2290 {
2291         int status;
2292 
2293         switch (hdspm->io_type) {
2294         case RayDAT:
2295         case AIO:
2296                 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2297                 return (status >> 16) & 0xF;
2298                 break;
2299         case AES32:
2300                 status = hdspm_read(hdspm, HDSPM_statusRegister);
2301                 return (status >> HDSPM_AES32_wcFreq_bit) & 0xF;
2302         default:
2303                 break;
2304         }
2305 
2306 
2307         return 0;
2308 }
2309 
2310 
2311 /**
2312  * Returns the TCO sample rate class for the given card.
2313  **/
2314 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm)
2315 {
2316         int status;
2317 
2318         if (hdspm->tco) {
2319                 switch (hdspm->io_type) {
2320                 case RayDAT:
2321                 case AIO:
2322                         status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2323                         return (status >> 20) & 0xF;
2324                         break;
2325                 case AES32:
2326                         status = hdspm_read(hdspm, HDSPM_statusRegister);
2327                         return (status >> 1) & 0xF;
2328                 default:
2329                         break;
2330                 }
2331         }
2332 
2333         return 0;
2334 }
2335 
2336 
2337 /**
2338  * Returns the SYNC_IN sample rate class for the given card.
2339  **/
2340 static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm)
2341 {
2342         int status;
2343 
2344         if (hdspm->tco) {
2345                 switch (hdspm->io_type) {
2346                 case RayDAT:
2347                 case AIO:
2348                         status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2349                         return (status >> 12) & 0xF;
2350                         break;
2351                 default:
2352                         break;
2353                 }
2354         }
2355 
2356         return 0;
2357 }
2358 
2359 /**
2360  * Returns the AES sample rate class for the given card.
2361  **/
2362 static int hdspm_get_aes_sample_rate(struct hdspm *hdspm, int index)
2363 {
2364         int timecode;
2365 
2366         switch (hdspm->io_type) {
2367         case AES32:
2368                 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
2369                 return (timecode >> (4*index)) & 0xF;
2370                 break;
2371         default:
2372                 break;
2373         }
2374         return 0;
2375 }
2376 
2377 /**
2378  * Returns the sample rate class for input source <idx> for
2379  * 'new style' cards like the AIO and RayDAT.
2380  **/
2381 static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx)
2382 {
2383         int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2384 
2385         return (status >> (idx*4)) & 0xF;
2386 }
2387 
2388 #define ENUMERATED_CTL_INFO(info, texts) \
2389         snd_ctl_enum_info(info, 1, ARRAY_SIZE(texts), texts)
2390 
2391 
2392 /* Helper function to query the external sample rate and return the
2393  * corresponding enum to be returned to userspace.
2394  */
2395 static int hdspm_external_rate_to_enum(struct hdspm *hdspm)
2396 {
2397         int rate = hdspm_external_sample_rate(hdspm);
2398         int i, selected_rate = 0;
2399         for (i = 1; i < 10; i++)
2400                 if (HDSPM_bit2freq(i) == rate) {
2401                         selected_rate = i;
2402                         break;
2403                 }
2404         return selected_rate;
2405 }
2406 
2407 
2408 #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
2409 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2410         .name = xname, \
2411         .private_value = xindex, \
2412         .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2413         .info = snd_hdspm_info_autosync_sample_rate, \
2414         .get = snd_hdspm_get_autosync_sample_rate \
2415 }
2416 
2417 
2418 static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2419                                                struct snd_ctl_elem_info *uinfo)
2420 {
2421         ENUMERATED_CTL_INFO(uinfo, texts_freq);
2422         return 0;
2423 }
2424 
2425 
2426 static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2427                                               struct snd_ctl_elem_value *
2428                                               ucontrol)
2429 {
2430         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2431 
2432         switch (hdspm->io_type) {
2433         case RayDAT:
2434                 switch (kcontrol->private_value) {
2435                 case 0:
2436                         ucontrol->value.enumerated.item[0] =
2437                                 hdspm_get_wc_sample_rate(hdspm);
2438                         break;
2439                 case 7:
2440                         ucontrol->value.enumerated.item[0] =
2441                                 hdspm_get_tco_sample_rate(hdspm);
2442                         break;
2443                 case 8:
2444                         ucontrol->value.enumerated.item[0] =
2445                                 hdspm_get_sync_in_sample_rate(hdspm);
2446                         break;
2447                 default:
2448                         ucontrol->value.enumerated.item[0] =
2449                                 hdspm_get_s1_sample_rate(hdspm,
2450                                                 kcontrol->private_value-1);
2451                 }
2452                 break;
2453 
2454         case AIO:
2455                 switch (kcontrol->private_value) {
2456                 case 0: /* WC */
2457                         ucontrol->value.enumerated.item[0] =
2458                                 hdspm_get_wc_sample_rate(hdspm);
2459                         break;
2460                 case 4: /* TCO */
2461                         ucontrol->value.enumerated.item[0] =
2462                                 hdspm_get_tco_sample_rate(hdspm);
2463                         break;
2464                 case 5: /* SYNC_IN */
2465                         ucontrol->value.enumerated.item[0] =
2466                                 hdspm_get_sync_in_sample_rate(hdspm);
2467                         break;
2468                 default:
2469                         ucontrol->value.enumerated.item[0] =
2470                                 hdspm_get_s1_sample_rate(hdspm,
2471                                                 kcontrol->private_value-1);
2472                 }
2473                 break;
2474 
2475         case AES32:
2476 
2477                 switch (kcontrol->private_value) {
2478                 case 0: /* WC */
2479                         ucontrol->value.enumerated.item[0] =
2480                                 hdspm_get_wc_sample_rate(hdspm);
2481                         break;
2482                 case 9: /* TCO */
2483                         ucontrol->value.enumerated.item[0] =
2484                                 hdspm_get_tco_sample_rate(hdspm);
2485                         break;
2486                 case 10: /* SYNC_IN */
2487                         ucontrol->value.enumerated.item[0] =
2488                                 hdspm_get_sync_in_sample_rate(hdspm);
2489                         break;
2490                 case 11: /* External Rate */
2491                         ucontrol->value.enumerated.item[0] =
2492                                 hdspm_external_rate_to_enum(hdspm);
2493                         break;
2494                 default: /* AES1 to AES8 */
2495                         ucontrol->value.enumerated.item[0] =
2496                                 hdspm_get_aes_sample_rate(hdspm,
2497                                                 kcontrol->private_value -
2498                                                 HDSPM_AES32_AUTOSYNC_FROM_AES1);
2499                         break;
2500                 }
2501                 break;
2502 
2503         case MADI:
2504         case MADIface:
2505                 ucontrol->value.enumerated.item[0] =
2506                         hdspm_external_rate_to_enum(hdspm);
2507                 break;
2508         default:
2509                 break;
2510         }
2511 
2512         return 0;
2513 }
2514 
2515 
2516 #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \
2517 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2518         .name = xname, \
2519         .index = xindex, \
2520         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2521                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2522         .info = snd_hdspm_info_system_clock_mode, \
2523         .get = snd_hdspm_get_system_clock_mode, \
2524         .put = snd_hdspm_put_system_clock_mode, \
2525 }
2526 
2527 
2528 /**
2529  * Returns the system clock mode for the given card.
2530  * @returns 0 - master, 1 - slave
2531  **/
2532 static int hdspm_system_clock_mode(struct hdspm *hdspm)
2533 {
2534         switch (hdspm->io_type) {
2535         case AIO:
2536         case RayDAT:
2537                 if (hdspm->settings_register & HDSPM_c0Master)
2538                         return 0;
2539                 break;
2540 
2541         default:
2542                 if (hdspm->control_register & HDSPM_ClockModeMaster)
2543                         return 0;
2544         }
2545 
2546         return 1;
2547 }
2548 
2549 
2550 /**
2551  * Sets the system clock mode.
2552  * @param mode 0 - master, 1 - slave
2553  **/
2554 static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode)
2555 {
2556         hdspm_set_toggle_setting(hdspm,
2557                         (hdspm_is_raydat_or_aio(hdspm)) ?
2558                         HDSPM_c0Master : HDSPM_ClockModeMaster,
2559                         (0 == mode));
2560 }
2561 
2562 
2563 static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol,
2564                                             struct snd_ctl_elem_info *uinfo)
2565 {
2566         static const char *const texts[] = { "Master", "AutoSync" };
2567         ENUMERATED_CTL_INFO(uinfo, texts);
2568         return 0;
2569 }
2570 
2571 static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol,
2572                                            struct snd_ctl_elem_value *ucontrol)
2573 {
2574         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2575 
2576         ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm);
2577         return 0;
2578 }
2579 
2580 static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol,
2581                                            struct snd_ctl_elem_value *ucontrol)
2582 {
2583         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2584         int val;
2585 
2586         if (!snd_hdspm_use_is_exclusive(hdspm))
2587                 return -EBUSY;
2588 
2589         val = ucontrol->value.enumerated.item[0];
2590         if (val < 0)
2591                 val = 0;
2592         else if (val > 1)
2593                 val = 1;
2594 
2595         hdspm_set_system_clock_mode(hdspm, val);
2596 
2597         return 0;
2598 }
2599 
2600 
2601 #define HDSPM_INTERNAL_CLOCK(xname, xindex) \
2602 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2603         .name = xname, \
2604         .index = xindex, \
2605         .info = snd_hdspm_info_clock_source, \
2606         .get = snd_hdspm_get_clock_source, \
2607         .put = snd_hdspm_put_clock_source \
2608 }
2609 
2610 
2611 static int hdspm_clock_source(struct hdspm * hdspm)
2612 {
2613         switch (hdspm->system_sample_rate) {
2614         case 32000: return 0;
2615         case 44100: return 1;
2616         case 48000: return 2;
2617         case 64000: return 3;
2618         case 88200: return 4;
2619         case 96000: return 5;
2620         case 128000: return 6;
2621         case 176400: return 7;
2622         case 192000: return 8;
2623         }
2624 
2625         return -1;
2626 }
2627 
2628 static int hdspm_set_clock_source(struct hdspm * hdspm, int mode)
2629 {
2630         int rate;
2631         switch (mode) {
2632         case 0:
2633                 rate = 32000; break;
2634         case 1:
2635                 rate = 44100; break;
2636         case 2:
2637                 rate = 48000; break;
2638         case 3:
2639                 rate = 64000; break;
2640         case 4:
2641                 rate = 88200; break;
2642         case 5:
2643                 rate = 96000; break;
2644         case 6:
2645                 rate = 128000; break;
2646         case 7:
2647                 rate = 176400; break;
2648         case 8:
2649                 rate = 192000; break;
2650         default:
2651                 rate = 48000;
2652         }
2653         hdspm_set_rate(hdspm, rate, 1);
2654         return 0;
2655 }
2656 
2657 static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol,
2658                                        struct snd_ctl_elem_info *uinfo)
2659 {
2660         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2661         uinfo->count = 1;
2662         uinfo->value.enumerated.items = 9;
2663 
2664         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2665                 uinfo->value.enumerated.item =
2666                     uinfo->value.enumerated.items - 1;
2667 
2668         strcpy(uinfo->value.enumerated.name,
2669                texts_freq[uinfo->value.enumerated.item+1]);
2670 
2671         return 0;
2672 }
2673 
2674 static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol,
2675                                       struct snd_ctl_elem_value *ucontrol)
2676 {
2677         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2678 
2679         ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm);
2680         return 0;
2681 }
2682 
2683 static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol,
2684                                       struct snd_ctl_elem_value *ucontrol)
2685 {
2686         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2687         int change;
2688         int val;
2689 
2690         if (!snd_hdspm_use_is_exclusive(hdspm))
2691                 return -EBUSY;
2692         val = ucontrol->value.enumerated.item[0];
2693         if (val < 0)
2694                 val = 0;
2695         if (val > 9)
2696                 val = 9;
2697         spin_lock_irq(&hdspm->lock);
2698         if (val != hdspm_clock_source(hdspm))
2699                 change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0;
2700         else
2701                 change = 0;
2702         spin_unlock_irq(&hdspm->lock);
2703         return change;
2704 }
2705 
2706 
2707 #define HDSPM_PREF_SYNC_REF(xname, xindex) \
2708 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2709         .name = xname, \
2710         .index = xindex, \
2711         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2712                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2713         .info = snd_hdspm_info_pref_sync_ref, \
2714         .get = snd_hdspm_get_pref_sync_ref, \
2715         .put = snd_hdspm_put_pref_sync_ref \
2716 }
2717 
2718 
2719 /**
2720  * Returns the current preferred sync reference setting.
2721  * The semantics of the return value are depending on the
2722  * card, please see the comments for clarification.
2723  **/
2724 static int hdspm_pref_sync_ref(struct hdspm * hdspm)
2725 {
2726         switch (hdspm->io_type) {
2727         case AES32:
2728                 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2729                 case 0: return 0;  /* WC */
2730                 case HDSPM_SyncRef0: return 1; /* AES 1 */
2731                 case HDSPM_SyncRef1: return 2; /* AES 2 */
2732                 case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */
2733                 case HDSPM_SyncRef2: return 4; /* AES 4 */
2734                 case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */
2735                 case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */
2736                 case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0:
2737                                                     return 7; /* AES 7 */
2738                 case HDSPM_SyncRef3: return 8; /* AES 8 */
2739                 case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */
2740                 }
2741                 break;
2742 
2743         case MADI:
2744         case MADIface:
2745                 if (hdspm->tco) {
2746                         switch (hdspm->control_register & HDSPM_SyncRefMask) {
2747                         case 0: return 0;  /* WC */
2748                         case HDSPM_SyncRef0: return 1;  /* MADI */
2749                         case HDSPM_SyncRef1: return 2;  /* TCO */
2750                         case HDSPM_SyncRef1+HDSPM_SyncRef0:
2751                                              return 3;  /* SYNC_IN */
2752                         }
2753                 } else {
2754                         switch (hdspm->control_register & HDSPM_SyncRefMask) {
2755                         case 0: return 0;  /* WC */
2756                         case HDSPM_SyncRef0: return 1;  /* MADI */
2757                         case HDSPM_SyncRef1+HDSPM_SyncRef0:
2758                                              return 2;  /* SYNC_IN */
2759                         }
2760                 }
2761                 break;
2762 
2763         case RayDAT:
2764                 if (hdspm->tco) {
2765                         switch ((hdspm->settings_register &
2766                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2767                         case 0: return 0;  /* WC */
2768                         case 3: return 1;  /* ADAT 1 */
2769                         case 4: return 2;  /* ADAT 2 */
2770                         case 5: return 3;  /* ADAT 3 */
2771                         case 6: return 4;  /* ADAT 4 */
2772                         case 1: return 5;  /* AES */
2773                         case 2: return 6;  /* SPDIF */
2774                         case 9: return 7;  /* TCO */
2775                         case 10: return 8; /* SYNC_IN */
2776                         }
2777                 } else {
2778                         switch ((hdspm->settings_register &
2779                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2780                         case 0: return 0;  /* WC */
2781                         case 3: return 1;  /* ADAT 1 */
2782                         case 4: return 2;  /* ADAT 2 */
2783                         case 5: return 3;  /* ADAT 3 */
2784                         case 6: return 4;  /* ADAT 4 */
2785                         case 1: return 5;  /* AES */
2786                         case 2: return 6;  /* SPDIF */
2787                         case 10: return 7; /* SYNC_IN */
2788                         }
2789                 }
2790 
2791                 break;
2792 
2793         case AIO:
2794                 if (hdspm->tco) {
2795                         switch ((hdspm->settings_register &
2796                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2797                         case 0: return 0;  /* WC */
2798                         case 3: return 1;  /* ADAT */
2799                         case 1: return 2;  /* AES */
2800                         case 2: return 3;  /* SPDIF */
2801                         case 9: return 4;  /* TCO */
2802                         case 10: return 5; /* SYNC_IN */
2803                         }
2804                 } else {
2805                         switch ((hdspm->settings_register &
2806                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2807                         case 0: return 0;  /* WC */
2808                         case 3: return 1;  /* ADAT */
2809                         case 1: return 2;  /* AES */
2810                         case 2: return 3;  /* SPDIF */
2811                         case 10: return 4; /* SYNC_IN */
2812                         }
2813                 }
2814 
2815                 break;
2816         }
2817 
2818         return -1;
2819 }
2820 
2821 
2822 /**
2823  * Set the preferred sync reference to <pref>. The semantics
2824  * of <pref> are depending on the card type, see the comments
2825  * for clarification.
2826  **/
2827 static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref)
2828 {
2829         int p = 0;
2830 
2831         switch (hdspm->io_type) {
2832         case AES32:
2833                 hdspm->control_register &= ~HDSPM_SyncRefMask;
2834                 switch (pref) {
2835                 case 0: /* WC  */
2836                         break;
2837                 case 1: /* AES 1 */
2838                         hdspm->control_register |= HDSPM_SyncRef0;
2839                         break;
2840                 case 2: /* AES 2 */
2841                         hdspm->control_register |= HDSPM_SyncRef1;
2842                         break;
2843                 case 3: /* AES 3 */
2844                         hdspm->control_register |=
2845                                 HDSPM_SyncRef1+HDSPM_SyncRef0;
2846                         break;
2847                 case 4: /* AES 4 */
2848                         hdspm->control_register |= HDSPM_SyncRef2;
2849                         break;
2850                 case 5: /* AES 5 */
2851                         hdspm->control_register |=
2852                                 HDSPM_SyncRef2+HDSPM_SyncRef0;
2853                         break;
2854                 case 6: /* AES 6 */
2855                         hdspm->control_register |=
2856                                 HDSPM_SyncRef2+HDSPM_SyncRef1;
2857                         break;
2858                 case 7: /* AES 7 */
2859                         hdspm->control_register |=
2860                                 HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0;
2861                         break;
2862                 case 8: /* AES 8 */
2863                         hdspm->control_register |= HDSPM_SyncRef3;
2864                         break;
2865                 case 9: /* TCO */
2866                         hdspm->control_register |=
2867                                 HDSPM_SyncRef3+HDSPM_SyncRef0;
2868                         break;
2869                 default:
2870                         return -1;
2871                 }
2872 
2873                 break;
2874 
2875         case MADI:
2876         case MADIface:
2877                 hdspm->control_register &= ~HDSPM_SyncRefMask;
2878                 if (hdspm->tco) {
2879                         switch (pref) {
2880                         case 0: /* WC */
2881                                 break;
2882                         case 1: /* MADI */
2883                                 hdspm->control_register |= HDSPM_SyncRef0;
2884                                 break;
2885                         case 2: /* TCO */
2886                                 hdspm->control_register |= HDSPM_SyncRef1;
2887                                 break;
2888                         case 3: /* SYNC_IN */
2889                                 hdspm->control_register |=
2890                                         HDSPM_SyncRef0+HDSPM_SyncRef1;
2891                                 break;
2892                         default:
2893                                 return -1;
2894                         }
2895                 } else {
2896                         switch (pref) {
2897                         case 0: /* WC */
2898                                 break;
2899                         case 1: /* MADI */
2900                                 hdspm->control_register |= HDSPM_SyncRef0;
2901                                 break;
2902                         case 2: /* SYNC_IN */
2903                                 hdspm->control_register |=
2904                                         HDSPM_SyncRef0+HDSPM_SyncRef1;
2905                                 break;
2906                         default:
2907                                 return -1;
2908                         }
2909                 }
2910 
2911                 break;
2912 
2913         case RayDAT:
2914                 if (hdspm->tco) {
2915                         switch (pref) {
2916                         case 0: p = 0; break;  /* WC */
2917                         case 1: p = 3; break;  /* ADAT 1 */
2918                         case 2: p = 4; break;  /* ADAT 2 */
2919                         case 3: p = 5; break;  /* ADAT 3 */
2920                         case 4: p = 6; break;  /* ADAT 4 */
2921                         case 5: p = 1; break;  /* AES */
2922                         case 6: p = 2; break;  /* SPDIF */
2923                         case 7: p = 9; break;  /* TCO */
2924                         case 8: p = 10; break; /* SYNC_IN */
2925                         default: return -1;
2926                         }
2927                 } else {
2928                         switch (pref) {
2929                         case 0: p = 0; break;  /* WC */
2930                         case 1: p = 3; break;  /* ADAT 1 */
2931                         case 2: p = 4; break;  /* ADAT 2 */
2932                         case 3: p = 5; break;  /* ADAT 3 */
2933                         case 4: p = 6; break;  /* ADAT 4 */
2934                         case 5: p = 1; break;  /* AES */
2935                         case 6: p = 2; break;  /* SPDIF */
2936                         case 7: p = 10; break; /* SYNC_IN */
2937                         default: return -1;
2938                         }
2939                 }
2940                 break;
2941 
2942         case AIO:
2943                 if (hdspm->tco) {
2944                         switch (pref) {
2945                         case 0: p = 0; break;  /* WC */
2946                         case 1: p = 3; break;  /* ADAT */
2947                         case 2: p = 1; break;  /* AES */
2948                         case 3: p = 2; break;  /* SPDIF */
2949                         case 4: p = 9; break;  /* TCO */
2950                         case 5: p = 10; break; /* SYNC_IN */
2951                         default: return -1;
2952                         }
2953                 } else {
2954                         switch (pref) {
2955                         case 0: p = 0; break;  /* WC */
2956                         case 1: p = 3; break;  /* ADAT */
2957                         case 2: p = 1; break;  /* AES */
2958                         case 3: p = 2; break;  /* SPDIF */
2959                         case 4: p = 10; break; /* SYNC_IN */
2960                         default: return -1;
2961                         }
2962                 }
2963                 break;
2964         }
2965 
2966         switch (hdspm->io_type) {
2967         case RayDAT:
2968         case AIO:
2969                 hdspm->settings_register &= ~HDSPM_c0_SyncRefMask;
2970                 hdspm->settings_register |= HDSPM_c0_SyncRef0 * p;
2971                 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2972                 break;
2973 
2974         case MADI:
2975         case MADIface:
2976         case AES32:
2977                 hdspm_write(hdspm, HDSPM_controlRegister,
2978                                 hdspm->control_register);
2979         }
2980 
2981         return 0;
2982 }
2983 
2984 
2985 static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol,
2986                                         struct snd_ctl_elem_info *uinfo)
2987 {
2988         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2989 
2990         snd_ctl_enum_info(uinfo, 1, hdspm->texts_autosync_items, hdspm->texts_autosync);
2991 
2992         return 0;
2993 }
2994 
2995 static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol,
2996                                        struct snd_ctl_elem_value *ucontrol)
2997 {
2998         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2999         int psf = hdspm_pref_sync_ref(hdspm);
3000 
3001         if (psf >= 0) {
3002                 ucontrol->value.enumerated.item[0] = psf;
3003                 return 0;
3004         }
3005 
3006         return -1;
3007 }
3008 
3009 static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol,
3010                                        struct snd_ctl_elem_value *ucontrol)
3011 {
3012         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3013         int val, change = 0;
3014 
3015         if (!snd_hdspm_use_is_exclusive(hdspm))
3016                 return -EBUSY;
3017 
3018         val = ucontrol->value.enumerated.item[0];
3019 
3020         if (val < 0)
3021                 val = 0;
3022         else if (val >= hdspm->texts_autosync_items)
3023                 val = hdspm->texts_autosync_items-1;
3024 
3025         spin_lock_irq(&hdspm->lock);
3026         if (val != hdspm_pref_sync_ref(hdspm))
3027                 change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0;
3028 
3029         spin_unlock_irq(&hdspm->lock);
3030         return change;
3031 }
3032 
3033 
3034 #define HDSPM_AUTOSYNC_REF(xname, xindex) \
3035 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3036         .name = xname, \
3037         .index = xindex, \
3038         .access = SNDRV_CTL_ELEM_ACCESS_READ, \
3039         .info = snd_hdspm_info_autosync_ref, \
3040         .get = snd_hdspm_get_autosync_ref, \
3041 }
3042 
3043 static int hdspm_autosync_ref(struct hdspm *hdspm)
3044 {
3045         /* This looks at the autosync selected sync reference */
3046         if (AES32 == hdspm->io_type) {
3047 
3048                 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister);
3049                 unsigned int syncref = (status >> HDSPM_AES32_syncref_bit) & 0xF;
3050                 if ((syncref >= HDSPM_AES32_AUTOSYNC_FROM_WORD) &&
3051                                 (syncref <= HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN)) {
3052                         return syncref;
3053                 }
3054                 return HDSPM_AES32_AUTOSYNC_FROM_NONE;
3055 
3056         } else if (MADI == hdspm->io_type) {
3057 
3058                 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3059                 switch (status2 & HDSPM_SelSyncRefMask) {
3060                 case HDSPM_SelSyncRef_WORD:
3061                         return HDSPM_AUTOSYNC_FROM_WORD;
3062                 case HDSPM_SelSyncRef_MADI:
3063                         return HDSPM_AUTOSYNC_FROM_MADI;
3064                 case HDSPM_SelSyncRef_TCO:
3065                         return HDSPM_AUTOSYNC_FROM_TCO;
3066                 case HDSPM_SelSyncRef_SyncIn:
3067                         return HDSPM_AUTOSYNC_FROM_SYNC_IN;
3068                 case HDSPM_SelSyncRef_NVALID:
3069                         return HDSPM_AUTOSYNC_FROM_NONE;
3070                 default:
3071                         return HDSPM_AUTOSYNC_FROM_NONE;
3072                 }
3073 
3074         }
3075         return 0;
3076 }
3077 
3078 
3079 static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol,
3080                                        struct snd_ctl_elem_info *uinfo)
3081 {
3082         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3083 
3084         if (AES32 == hdspm->io_type) {
3085                 static const char *const texts[] = { "WordClock", "AES1", "AES2", "AES3",
3086                         "AES4", "AES5", "AES6", "AES7", "AES8", "TCO", "Sync In", "None"};
3087 
3088                 ENUMERATED_CTL_INFO(uinfo, texts);
3089         } else if (MADI == hdspm->io_type) {
3090                 static const char *const texts[] = {"Word Clock", "MADI", "TCO",
3091                         "Sync In", "None" };
3092 
3093                 ENUMERATED_CTL_INFO(uinfo, texts);
3094         }
3095         return 0;
3096 }
3097 
3098 static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol,
3099                                       struct snd_ctl_elem_value *ucontrol)
3100 {
3101         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3102 
3103         ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm);
3104         return 0;
3105 }
3106 
3107 
3108 
3109 #define HDSPM_TCO_VIDEO_INPUT_FORMAT(xname, xindex) \
3110 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3111         .name = xname, \
3112         .access = SNDRV_CTL_ELEM_ACCESS_READ |\
3113                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3114         .info = snd_hdspm_info_tco_video_input_format, \
3115         .get = snd_hdspm_get_tco_video_input_format, \
3116 }
3117 
3118 static int snd_hdspm_info_tco_video_input_format(struct snd_kcontrol *kcontrol,
3119                                        struct snd_ctl_elem_info *uinfo)
3120 {
3121         static const char *const texts[] = {"No video", "NTSC", "PAL"};
3122         ENUMERATED_CTL_INFO(uinfo, texts);
3123         return 0;
3124 }
3125 
3126 static int snd_hdspm_get_tco_video_input_format(struct snd_kcontrol *kcontrol,
3127                                       struct snd_ctl_elem_value *ucontrol)
3128 {
3129         u32 status;
3130         int ret = 0;
3131 
3132         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3133         status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3134         switch (status & (HDSPM_TCO1_Video_Input_Format_NTSC |
3135                         HDSPM_TCO1_Video_Input_Format_PAL)) {
3136         case HDSPM_TCO1_Video_Input_Format_NTSC:
3137                 /* ntsc */
3138                 ret = 1;
3139                 break;
3140         case HDSPM_TCO1_Video_Input_Format_PAL:
3141                 /* pal */
3142                 ret = 2;
3143                 break;
3144         default:
3145                 /* no video */
3146                 ret = 0;
3147                 break;
3148         }
3149         ucontrol->value.enumerated.item[0] = ret;
3150         return 0;
3151 }
3152 
3153 
3154 
3155 #define HDSPM_TCO_LTC_FRAMES(xname, xindex) \
3156 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3157         .name = xname, \
3158         .access = SNDRV_CTL_ELEM_ACCESS_READ |\
3159                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3160         .info = snd_hdspm_info_tco_ltc_frames, \
3161         .get = snd_hdspm_get_tco_ltc_frames, \
3162 }
3163 
3164 static int snd_hdspm_info_tco_ltc_frames(struct snd_kcontrol *kcontrol,
3165                                        struct snd_ctl_elem_info *uinfo)
3166 {
3167         static const char *const texts[] = {"No lock", "24 fps", "25 fps", "29.97 fps",
3168                                 "30 fps"};
3169         ENUMERATED_CTL_INFO(uinfo, texts);
3170         return 0;
3171 }
3172 
3173 static int hdspm_tco_ltc_frames(struct hdspm *hdspm)
3174 {
3175         u32 status;
3176         int ret = 0;
3177 
3178         status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3179         if (status & HDSPM_TCO1_LTC_Input_valid) {
3180                 switch (status & (HDSPM_TCO1_LTC_Format_LSB |
3181                                         HDSPM_TCO1_LTC_Format_MSB)) {
3182                 case 0:
3183                         /* 24 fps */
3184                         ret = fps_24;
3185                         break;
3186                 case HDSPM_TCO1_LTC_Format_LSB:
3187                         /* 25 fps */
3188                         ret = fps_25;
3189                         break;
3190                 case HDSPM_TCO1_LTC_Format_MSB:
3191                         /* 29.97 fps */
3192                         ret = fps_2997;
3193                         break;
3194                 default:
3195                         /* 30 fps */
3196                         ret = fps_30;
3197                         break;
3198                 }
3199         }
3200 
3201         return ret;
3202 }
3203 
3204 static int snd_hdspm_get_tco_ltc_frames(struct snd_kcontrol *kcontrol,
3205                                       struct snd_ctl_elem_value *ucontrol)
3206 {
3207         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3208 
3209         ucontrol->value.enumerated.item[0] = hdspm_tco_ltc_frames(hdspm);
3210         return 0;
3211 }
3212 
3213 #define HDSPM_TOGGLE_SETTING(xname, xindex) \
3214 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3215         .name = xname, \
3216         .private_value = xindex, \
3217         .info = snd_hdspm_info_toggle_setting, \
3218         .get = snd_hdspm_get_toggle_setting, \
3219         .put = snd_hdspm_put_toggle_setting \
3220 }
3221 
3222 static int hdspm_toggle_setting(struct hdspm *hdspm, u32 regmask)
3223 {
3224         u32 reg;
3225 
3226         if (hdspm_is_raydat_or_aio(hdspm))
3227                 reg = hdspm->settings_register;
3228         else
3229                 reg = hdspm->control_register;
3230 
3231         return (reg & regmask) ? 1 : 0;
3232 }
3233 
3234 static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out)
3235 {
3236         u32 *reg;
3237         u32 target_reg;
3238 
3239         if (hdspm_is_raydat_or_aio(hdspm)) {
3240                 reg = &(hdspm->settings_register);
3241                 target_reg = HDSPM_WR_SETTINGS;
3242         } else {
3243                 reg = &(hdspm->control_register);
3244                 target_reg = HDSPM_controlRegister;
3245         }
3246 
3247         if (out)
3248                 *reg |= regmask;
3249         else
3250                 *reg &= ~regmask;
3251 
3252         hdspm_write(hdspm, target_reg, *reg);
3253 
3254         return 0;
3255 }
3256 
3257 #define snd_hdspm_info_toggle_setting           snd_ctl_boolean_mono_info
3258 
3259 static int snd_hdspm_get_toggle_setting(struct snd_kcontrol *kcontrol,
3260                                struct snd_ctl_elem_value *ucontrol)
3261 {
3262         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3263         u32 regmask = kcontrol->private_value;
3264 
3265         spin_lock_irq(&hdspm->lock);
3266         ucontrol->value.integer.value[0] = hdspm_toggle_setting(hdspm, regmask);
3267         spin_unlock_irq(&hdspm->lock);
3268         return 0;
3269 }
3270 
3271 static int snd_hdspm_put_toggle_setting(struct snd_kcontrol *kcontrol,
3272                                struct snd_ctl_elem_value *ucontrol)
3273 {
3274         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3275         u32 regmask = kcontrol->private_value;
3276         int change;
3277         unsigned int val;
3278 
3279         if (!snd_hdspm_use_is_exclusive(hdspm))
3280                 return -EBUSY;
3281         val = ucontrol->value.integer.value[0] & 1;
3282         spin_lock_irq(&hdspm->lock);
3283         change = (int) val != hdspm_toggle_setting(hdspm, regmask);
3284         hdspm_set_toggle_setting(hdspm, regmask, val);
3285         spin_unlock_irq(&hdspm->lock);
3286         return change;
3287 }
3288 
3289 #define HDSPM_INPUT_SELECT(xname, xindex) \
3290 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3291         .name = xname, \
3292         .index = xindex, \
3293         .info = snd_hdspm_info_input_select, \
3294         .get = snd_hdspm_get_input_select, \
3295         .put = snd_hdspm_put_input_select \
3296 }
3297 
3298 static int hdspm_input_select(struct hdspm * hdspm)
3299 {
3300         return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0;
3301 }
3302 
3303 static int hdspm_set_input_select(struct hdspm * hdspm, int out)
3304 {
3305         if (out)
3306                 hdspm->control_register |= HDSPM_InputSelect0;
3307         else
3308                 hdspm->control_register &= ~HDSPM_InputSelect0;
3309         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3310 
3311         return 0;
3312 }
3313 
3314 static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol,
3315                                        struct snd_ctl_elem_info *uinfo)
3316 {
3317         static const char *const texts[] = { "optical", "coaxial" };
3318         ENUMERATED_CTL_INFO(uinfo, texts);
3319         return 0;
3320 }
3321 
3322 static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol,
3323                                       struct snd_ctl_elem_value *ucontrol)
3324 {
3325         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3326 
3327         spin_lock_irq(&hdspm->lock);
3328         ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm);
3329         spin_unlock_irq(&hdspm->lock);
3330         return 0;
3331 }
3332 
3333 static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol,
3334                                       struct snd_ctl_elem_value *ucontrol)
3335 {
3336         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3337         int change;
3338         unsigned int val;
3339 
3340         if (!snd_hdspm_use_is_exclusive(hdspm))
3341                 return -EBUSY;
3342         val = ucontrol->value.integer.value[0] & 1;
3343         spin_lock_irq(&hdspm->lock);
3344         change = (int) val != hdspm_input_select(hdspm);
3345         hdspm_set_input_select(hdspm, val);
3346         spin_unlock_irq(&hdspm->lock);
3347         return change;
3348 }
3349 
3350 
3351 #define HDSPM_DS_WIRE(xname, xindex) \
3352 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3353         .name = xname, \
3354         .index = xindex, \
3355         .info = snd_hdspm_info_ds_wire, \
3356         .get = snd_hdspm_get_ds_wire, \
3357         .put = snd_hdspm_put_ds_wire \
3358 }
3359 
3360 static int hdspm_ds_wire(struct hdspm * hdspm)
3361 {
3362         return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0;
3363 }
3364 
3365 static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds)
3366 {
3367         if (ds)
3368                 hdspm->control_register |= HDSPM_DS_DoubleWire;
3369         else
3370                 hdspm->control_register &= ~HDSPM_DS_DoubleWire;
3371         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3372 
3373         return 0;
3374 }
3375 
3376 static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol,
3377                                   struct snd_ctl_elem_info *uinfo)
3378 {
3379         static const char *const texts[] = { "Single", "Double" };
3380         ENUMERATED_CTL_INFO(uinfo, texts);
3381         return 0;
3382 }
3383 
3384 static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol,
3385                                  struct snd_ctl_elem_value *ucontrol)
3386 {
3387         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3388 
3389         spin_lock_irq(&hdspm->lock);
3390         ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm);
3391         spin_unlock_irq(&hdspm->lock);
3392         return 0;
3393 }
3394 
3395 static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol,
3396                                  struct snd_ctl_elem_value *ucontrol)
3397 {
3398         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3399         int change;
3400         unsigned int val;
3401 
3402         if (!snd_hdspm_use_is_exclusive(hdspm))
3403                 return -EBUSY;
3404         val = ucontrol->value.integer.value[0] & 1;
3405         spin_lock_irq(&hdspm->lock);
3406         change = (int) val != hdspm_ds_wire(hdspm);
3407         hdspm_set_ds_wire(hdspm, val);
3408         spin_unlock_irq(&hdspm->lock);
3409         return change;
3410 }
3411 
3412 
3413 #define HDSPM_QS_WIRE(xname, xindex) \
3414 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3415         .name = xname, \
3416         .index = xindex, \
3417         .info = snd_hdspm_info_qs_wire, \
3418         .get = snd_hdspm_get_qs_wire, \
3419         .put = snd_hdspm_put_qs_wire \
3420 }
3421 
3422 static int hdspm_qs_wire(struct hdspm * hdspm)
3423 {
3424         if (hdspm->control_register & HDSPM_QS_DoubleWire)
3425                 return 1;
3426         if (hdspm->control_register & HDSPM_QS_QuadWire)
3427                 return 2;
3428         return 0;
3429 }
3430 
3431 static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode)
3432 {
3433         hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire);
3434         switch (mode) {
3435         case 0:
3436                 break;
3437         case 1:
3438                 hdspm->control_register |= HDSPM_QS_DoubleWire;
3439                 break;
3440         case 2:
3441                 hdspm->control_register |= HDSPM_QS_QuadWire;
3442                 break;
3443         }
3444         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3445 
3446         return 0;
3447 }
3448 
3449 static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol,
3450                                        struct snd_ctl_elem_info *uinfo)
3451 {
3452         static const char *const texts[] = { "Single", "Double", "Quad" };
3453         ENUMERATED_CTL_INFO(uinfo, texts);
3454         return 0;
3455 }
3456 
3457 static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol,
3458                                       struct snd_ctl_elem_value *ucontrol)
3459 {
3460         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3461 
3462         spin_lock_irq(&hdspm->lock);
3463         ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm);
3464         spin_unlock_irq(&hdspm->lock);
3465         return 0;
3466 }
3467 
3468 static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol,
3469                                       struct snd_ctl_elem_value *ucontrol)
3470 {
3471         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3472         int change;
3473         int val;
3474 
3475         if (!snd_hdspm_use_is_exclusive(hdspm))
3476                 return -EBUSY;
3477         val = ucontrol->value.integer.value[0];
3478         if (val < 0)
3479                 val = 0;
3480         if (val > 2)
3481                 val = 2;
3482         spin_lock_irq(&hdspm->lock);
3483         change = val != hdspm_qs_wire(hdspm);
3484         hdspm_set_qs_wire(hdspm, val);
3485         spin_unlock_irq(&hdspm->lock);
3486         return change;
3487 }
3488 
3489 #define HDSPM_CONTROL_TRISTATE(xname, xindex) \
3490 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3491         .name = xname, \
3492         .private_value = xindex, \
3493         .info = snd_hdspm_info_tristate, \
3494         .get = snd_hdspm_get_tristate, \
3495         .put = snd_hdspm_put_tristate \
3496 }
3497 
3498 static int hdspm_tristate(struct hdspm *hdspm, u32 regmask)
3499 {
3500         u32 reg = hdspm->settings_register & (regmask * 3);
3501         return reg / regmask;
3502 }
3503 
3504 static int hdspm_set_tristate(struct hdspm *hdspm, int mode, u32 regmask)
3505 {
3506         hdspm->settings_register &= ~(regmask * 3);
3507         hdspm->settings_register |= (regmask * mode);
3508         hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
3509 
3510         return 0;
3511 }
3512 
3513 static int snd_hdspm_info_tristate(struct snd_kcontrol *kcontrol,
3514                                        struct snd_ctl_elem_info *uinfo)
3515 {
3516         u32 regmask = kcontrol->private_value;
3517 
3518         static const char *const texts_spdif[] = { "Optical", "Coaxial", "Internal" };
3519         static const char *const texts_levels[] = { "Hi Gain", "+4 dBu", "-10 dBV" };
3520 
3521         switch (regmask) {
3522         case HDSPM_c0_Input0:
3523                 ENUMERATED_CTL_INFO(uinfo, texts_spdif);
3524                 break;
3525         default:
3526                 ENUMERATED_CTL_INFO(uinfo, texts_levels);
3527                 break;
3528         }
3529         return 0;
3530 }
3531 
3532 static int snd_hdspm_get_tristate(struct snd_kcontrol *kcontrol,
3533                                       struct snd_ctl_elem_value *ucontrol)
3534 {
3535         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3536         u32 regmask = kcontrol->private_value;
3537 
3538         spin_lock_irq(&hdspm->lock);
3539         ucontrol->value.enumerated.item[0] = hdspm_tristate(hdspm, regmask);
3540         spin_unlock_irq(&hdspm->lock);
3541         return 0;
3542 }
3543 
3544 static int snd_hdspm_put_tristate(struct snd_kcontrol *kcontrol,
3545                                       struct snd_ctl_elem_value *ucontrol)
3546 {
3547         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3548         u32 regmask = kcontrol->private_value;
3549         int change;
3550         int val;
3551 
3552         if (!snd_hdspm_use_is_exclusive(hdspm))
3553                 return -EBUSY;
3554         val = ucontrol->value.integer.value[0];
3555         if (val < 0)
3556                 val = 0;
3557         if (val > 2)
3558                 val = 2;
3559 
3560         spin_lock_irq(&hdspm->lock);
3561         change = val != hdspm_tristate(hdspm, regmask);
3562         hdspm_set_tristate(hdspm, val, regmask);
3563         spin_unlock_irq(&hdspm->lock);
3564         return change;
3565 }
3566 
3567 #define HDSPM_MADI_SPEEDMODE(xname, xindex) \
3568 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3569         .name = xname, \
3570         .index = xindex, \
3571         .info = snd_hdspm_info_madi_speedmode, \
3572         .get = snd_hdspm_get_madi_speedmode, \
3573         .put = snd_hdspm_put_madi_speedmode \
3574 }
3575 
3576 static int hdspm_madi_speedmode(struct hdspm *hdspm)
3577 {
3578         if (hdspm->control_register & HDSPM_QuadSpeed)
3579                 return 2;
3580         if (hdspm->control_register & HDSPM_DoubleSpeed)
3581                 return 1;
3582         return 0;
3583 }
3584 
3585 static int hdspm_set_madi_speedmode(struct hdspm *hdspm, int mode)
3586 {
3587         hdspm->control_register &= ~(HDSPM_DoubleSpeed | HDSPM_QuadSpeed);
3588         switch (mode) {
3589         case 0:
3590                 break;
3591         case 1:
3592                 hdspm->control_register |= HDSPM_DoubleSpeed;
3593                 break;
3594         case 2:
3595                 hdspm->control_register |= HDSPM_QuadSpeed;
3596                 break;
3597         }
3598         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3599 
3600         return 0;
3601 }
3602 
3603 static int snd_hdspm_info_madi_speedmode(struct snd_kcontrol *kcontrol,
3604                                        struct snd_ctl_elem_info *uinfo)
3605 {
3606         static const char *const texts[] = { "Single", "Double", "Quad" };
3607         ENUMERATED_CTL_INFO(uinfo, texts);
3608         return 0;
3609 }
3610 
3611 static int snd_hdspm_get_madi_speedmode(struct snd_kcontrol *kcontrol,
3612                                       struct snd_ctl_elem_value *ucontrol)
3613 {
3614         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3615 
3616         spin_lock_irq(&hdspm->lock);
3617         ucontrol->value.enumerated.item[0] = hdspm_madi_speedmode(hdspm);
3618         spin_unlock_irq(&hdspm->lock);
3619         return 0;
3620 }
3621 
3622 static int snd_hdspm_put_madi_speedmode(struct snd_kcontrol *kcontrol,
3623                                       struct snd_ctl_elem_value *ucontrol)
3624 {
3625         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3626         int change;
3627         int val;
3628 
3629         if (!snd_hdspm_use_is_exclusive(hdspm))
3630                 return -EBUSY;
3631         val = ucontrol->value.integer.value[0];
3632         if (val < 0)
3633                 val = 0;
3634         if (val > 2)
3635                 val = 2;
3636         spin_lock_irq(&hdspm->lock);
3637         change = val != hdspm_madi_speedmode(hdspm);
3638         hdspm_set_madi_speedmode(hdspm, val);
3639         spin_unlock_irq(&hdspm->lock);
3640         return change;
3641 }
3642 
3643 #define HDSPM_MIXER(xname, xindex) \
3644 {       .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3645         .name = xname, \
3646         .index = xindex, \
3647         .device = 0, \
3648         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3649                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3650         .info = snd_hdspm_info_mixer, \
3651         .get = snd_hdspm_get_mixer, \
3652         .put = snd_hdspm_put_mixer \
3653 }
3654 
3655 static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol,
3656                                 struct snd_ctl_elem_info *uinfo)
3657 {
3658         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3659         uinfo->count = 3;
3660         uinfo->value.integer.min = 0;
3661         uinfo->value.integer.max = 65535;
3662         uinfo->value.integer.step = 1;
3663         return 0;
3664 }
3665 
3666 static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol,
3667                                struct snd_ctl_elem_value *ucontrol)
3668 {
3669         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3670         int source;
3671         int destination;
3672 
3673         source = ucontrol->value.integer.value[0];
3674         if (source < 0)
3675                 source = 0;
3676         else if (source >= 2 * HDSPM_MAX_CHANNELS)
3677                 source = 2 * HDSPM_MAX_CHANNELS - 1;
3678 
3679         destination = ucontrol->value.integer.value[1];
3680         if (destination < 0)
3681                 destination = 0;
3682         else if (destination >= HDSPM_MAX_CHANNELS)
3683                 destination = HDSPM_MAX_CHANNELS - 1;
3684 
3685         spin_lock_irq(&hdspm->lock);
3686         if (source >= HDSPM_MAX_CHANNELS)
3687                 ucontrol->value.integer.value[2] =
3688                     hdspm_read_pb_gain(hdspm, destination,
3689                                        source - HDSPM_MAX_CHANNELS);
3690         else
3691                 ucontrol->value.integer.value[2] =
3692                     hdspm_read_in_gain(hdspm, destination, source);
3693 
3694         spin_unlock_irq(&hdspm->lock);
3695 
3696         return 0;
3697 }
3698 
3699 static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol,
3700                                struct snd_ctl_elem_value *ucontrol)
3701 {
3702         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3703         int change;
3704         int source;
3705         int destination;
3706         int gain;
3707 
3708         if (!snd_hdspm_use_is_exclusive(hdspm))
3709                 return -EBUSY;
3710 
3711         source = ucontrol->value.integer.value[0];
3712         destination = ucontrol->value.integer.value[1];
3713 
3714         if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS)
3715                 return -1;
3716         if (destination < 0 || destination >= HDSPM_MAX_CHANNELS)
3717                 return -1;
3718 
3719         gain = ucontrol->value.integer.value[2];
3720 
3721         spin_lock_irq(&hdspm->lock);
3722 
3723         if (source >= HDSPM_MAX_CHANNELS)
3724                 change = gain != hdspm_read_pb_gain(hdspm, destination,
3725                                                     source -
3726                                                     HDSPM_MAX_CHANNELS);
3727         else
3728                 change = gain != hdspm_read_in_gain(hdspm, destination,
3729                                                     source);
3730 
3731         if (change) {
3732                 if (source >= HDSPM_MAX_CHANNELS)
3733                         hdspm_write_pb_gain(hdspm, destination,
3734                                             source - HDSPM_MAX_CHANNELS,
3735                                             gain);
3736                 else
3737                         hdspm_write_in_gain(hdspm, destination, source,
3738                                             gain);
3739         }
3740         spin_unlock_irq(&hdspm->lock);
3741 
3742         return change;
3743 }
3744 
3745 /* The simple mixer control(s) provide gain control for the
3746    basic 1:1 mappings of playback streams to output
3747    streams.
3748 */
3749 
3750 #define HDSPM_PLAYBACK_MIXER \
3751 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3752         .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \
3753                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3754         .info = snd_hdspm_info_playback_mixer, \
3755         .get = snd_hdspm_get_playback_mixer, \
3756         .put = snd_hdspm_put_playback_mixer \
3757 }
3758 
3759 static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol,
3760                                          struct snd_ctl_elem_info *uinfo)
3761 {
3762         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3763         uinfo->count = 1;
3764         uinfo->value.integer.min = 0;
3765         uinfo->value.integer.max = 64;
3766         uinfo->value.integer.step = 1;
3767         return 0;
3768 }
3769 
3770 static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol,
3771                                         struct snd_ctl_elem_value *ucontrol)
3772 {
3773         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3774         int channel;
3775 
3776         channel = ucontrol->id.index - 1;
3777 
3778         if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3779                 return -EINVAL;
3780 
3781         spin_lock_irq(&hdspm->lock);
3782         ucontrol->value.integer.value[0] =
3783           (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN;
3784         spin_unlock_irq(&hdspm->lock);
3785 
3786         return 0;
3787 }
3788 
3789 static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol,
3790                                         struct snd_ctl_elem_value *ucontrol)
3791 {
3792         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3793         int change;
3794         int channel;
3795         int gain;
3796 
3797         if (!snd_hdspm_use_is_exclusive(hdspm))
3798                 return -EBUSY;
3799 
3800         channel = ucontrol->id.index - 1;
3801 
3802         if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3803                 return -EINVAL;
3804 
3805         gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64;
3806 
3807         spin_lock_irq(&hdspm->lock);
3808         change =
3809             gain != hdspm_read_pb_gain(hdspm, channel,
3810                                        channel);
3811         if (change)
3812                 hdspm_write_pb_gain(hdspm, channel, channel,
3813                                     gain);
3814         spin_unlock_irq(&hdspm->lock);
3815         return change;
3816 }
3817 
3818 #define HDSPM_SYNC_CHECK(xname, xindex) \
3819 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3820         .name = xname, \
3821         .private_value = xindex, \
3822         .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3823         .info = snd_hdspm_info_sync_check, \
3824         .get = snd_hdspm_get_sync_check \
3825 }
3826 
3827 #define HDSPM_TCO_LOCK_CHECK(xname, xindex) \
3828 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3829         .name = xname, \
3830         .private_value = xindex, \
3831         .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3832         .info = snd_hdspm_tco_info_lock_check, \
3833         .get = snd_hdspm_get_sync_check \
3834 }
3835 
3836 
3837 
3838 static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol,
3839                                      struct snd_ctl_elem_info *uinfo)
3840 {
3841         static const char *const texts[] = { "No Lock", "Lock", "Sync", "N/A" };
3842         ENUMERATED_CTL_INFO(uinfo, texts);
3843         return 0;
3844 }
3845 
3846 static int snd_hdspm_tco_info_lock_check(struct snd_kcontrol *kcontrol,
3847                                      struct snd_ctl_elem_info *uinfo)
3848 {
3849         static const char *const texts[] = { "No Lock", "Lock" };
3850         ENUMERATED_CTL_INFO(uinfo, texts);
3851         return 0;
3852 }
3853 
3854 static int hdspm_wc_sync_check(struct hdspm *hdspm)
3855 {
3856         int status, status2;
3857 
3858         switch (hdspm->io_type) {
3859         case AES32:
3860                 status = hdspm_read(hdspm, HDSPM_statusRegister);
3861                 if (status & HDSPM_AES32_wcLock) {
3862                         if (status & HDSPM_AES32_wcSync)
3863                                 return 2;
3864                         else
3865                                 return 1;
3866                 }
3867                 return 0;
3868                 break;
3869 
3870         case MADI:
3871                 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3872                 if (status2 & HDSPM_wcLock) {
3873                         if (status2 & HDSPM_wcSync)
3874                                 return 2;
3875                         else
3876                                 return 1;
3877                 }
3878                 return 0;
3879                 break;
3880 
3881         case RayDAT:
3882         case AIO:
3883                 status = hdspm_read(hdspm, HDSPM_statusRegister);
3884 
3885                 if (status & 0x2000000)
3886                         return 2;
3887                 else if (status & 0x1000000)
3888                         return 1;
3889                 return 0;
3890 
3891                 break;
3892 
3893         case MADIface:
3894                 break;
3895         }
3896 
3897 
3898         return 3;
3899 }
3900 
3901 
3902 static int hdspm_madi_sync_check(struct hdspm *hdspm)
3903 {
3904         int status = hdspm_read(hdspm, HDSPM_statusRegister);
3905         if (status & HDSPM_madiLock) {
3906                 if (status & HDSPM_madiSync)
3907                         return 2;
3908                 else
3909                         return 1;
3910         }
3911         return 0;
3912 }
3913 
3914 
3915 static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx)
3916 {
3917         int status, lock, sync;
3918 
3919         status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3920 
3921         lock = (status & (0x1<<idx)) ? 1 : 0;
3922         sync = (status & (0x100<<idx)) ? 1 : 0;
3923 
3924         if (lock && sync)
3925                 return 2;
3926         else if (lock)
3927                 return 1;
3928         return 0;
3929 }
3930 
3931 
3932 static int hdspm_sync_in_sync_check(struct hdspm *hdspm)
3933 {
3934         int status, lock = 0, sync = 0;
3935 
3936         switch (hdspm->io_type) {
3937         case RayDAT:
3938         case AIO:
3939                 status = hdspm_read(hdspm, HDSPM_RD_STATUS_3);
3940                 lock = (status & 0x400) ? 1 : 0;
3941                 sync = (status & 0x800) ? 1 : 0;
3942                 break;
3943 
3944         case MADI:
3945                 status = hdspm_read(hdspm, HDSPM_statusRegister);
3946                 lock = (status & HDSPM_syncInLock) ? 1 : 0;
3947                 sync = (status & HDSPM_syncInSync) ? 1 : 0;
3948                 break;
3949 
3950         case AES32:
3951                 status = hdspm_read(hdspm, HDSPM_statusRegister2);
3952                 lock = (status & 0x100000) ? 1 : 0;
3953                 sync = (status & 0x200000) ? 1 : 0;
3954                 break;
3955 
3956         case MADIface:
3957                 break;
3958         }
3959 
3960         if (lock && sync)
3961                 return 2;
3962         else if (lock)
3963                 return 1;
3964 
3965         return 0;
3966 }
3967 
3968 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx)
3969 {
3970         int status2, lock, sync;
3971         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3972 
3973         lock = (status2 & (0x0080 >> idx)) ? 1 : 0;
3974         sync = (status2 & (0x8000 >> idx)) ? 1 : 0;
3975 
3976         if (sync)
3977                 return 2;
3978         else if (lock)
3979                 return 1;
3980         return 0;
3981 }
3982 
3983 static int hdspm_tco_input_check(struct hdspm *hdspm, u32 mask)
3984 {
3985         u32 status;
3986         status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3987 
3988         return (status & mask) ? 1 : 0;
3989 }
3990 
3991 
3992 static int hdspm_tco_sync_check(struct hdspm *hdspm)
3993 {
3994         int status;
3995 
3996         if (hdspm->tco) {
3997                 switch (hdspm->io_type) {
3998                 case MADI:
3999                         status = hdspm_read(hdspm, HDSPM_statusRegister);
4000                         if (status & HDSPM_tcoLockMadi) {
4001                                 if (status & HDSPM_tcoSync)
4002                                         return 2;
4003                                 else
4004                                         return 1;
4005                         }
4006                         return 0;
4007                         break;
4008                 case AES32:
4009                         status = hdspm_read(hdspm, HDSPM_statusRegister);
4010                         if (status & HDSPM_tcoLockAes) {
4011                                 if (status & HDSPM_tcoSync)
4012                                         return 2;
4013                                 else
4014                                         return 1;
4015                         }
4016                         return 0;
4017 
4018                         break;
4019 
4020                 case RayDAT:
4021                 case AIO:
4022                         status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
4023 
4024                         if (status & 0x8000000)
4025                                 return 2; /* Sync */
4026                         if (status & 0x4000000)
4027                                 return 1; /* Lock */
4028                         return 0; /* No signal */
4029                         break;
4030 
4031                 default:
4032                         break;
4033                 }
4034         }
4035 
4036         return 3; /* N/A */
4037 }
4038 
4039 
4040 static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol,
4041                                     struct snd_ctl_elem_value *ucontrol)
4042 {
4043         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4044         int val = -1;
4045 
4046         switch (hdspm->io_type) {
4047         case RayDAT:
4048                 switch (kcontrol->private_value) {
4049                 case 0: /* WC */
4050                         val = hdspm_wc_sync_check(hdspm); break;
4051                 case 7: /* TCO */
4052                         val = hdspm_tco_sync_check(hdspm); break;
4053                 case 8: /* SYNC IN */
4054                         val = hdspm_sync_in_sync_check(hdspm); break;
4055                 default:
4056                         val = hdspm_s1_sync_check(hdspm,
4057                                         kcontrol->private_value-1);
4058                 }
4059                 break;
4060 
4061         case AIO:
4062                 switch (kcontrol->private_value) {
4063                 case 0: /* WC */
4064                         val = hdspm_wc_sync_check(hdspm); break;
4065                 case 4: /* TCO */
4066                         val = hdspm_tco_sync_check(hdspm); break;
4067                 case 5: /* SYNC IN */
4068                         val = hdspm_sync_in_sync_check(hdspm); break;
4069                 default:
4070                         val = hdspm_s1_sync_check(hdspm,
4071                                         kcontrol->private_value-1);
4072                 }
4073                 break;
4074 
4075         case MADI:
4076                 switch (kcontrol->private_value) {
4077                 case 0: /* WC */
4078                         val = hdspm_wc_sync_check(hdspm); break;
4079                 case 1: /* MADI */
4080                         val = hdspm_madi_sync_check(hdspm); break;
4081                 case 2: /* TCO */
4082                         val = hdspm_tco_sync_check(hdspm); break;
4083                 case 3: /* SYNC_IN */
4084                         val = hdspm_sync_in_sync_check(hdspm); break;
4085                 }
4086                 break;
4087 
4088         case MADIface:
4089                 val = hdspm_madi_sync_check(hdspm); /* MADI */
4090                 break;
4091 
4092         case AES32:
4093                 switch (kcontrol->private_value) {
4094                 case 0: /* WC */
4095                         val = hdspm_wc_sync_check(hdspm); break;
4096                 case 9: /* TCO */
4097                         val = hdspm_tco_sync_check(hdspm); break;
4098                 case 10 /* SYNC IN */:
4099                         val = hdspm_sync_in_sync_check(hdspm); break;
4100                 default: /* AES1 to AES8 */
4101                          val = hdspm_aes_sync_check(hdspm,
4102                                          kcontrol->private_value-1);
4103                 }
4104                 break;
4105 
4106         }
4107 
4108         if (hdspm->tco) {
4109                 switch (kcontrol->private_value) {
4110                 case 11:
4111                         /* Check TCO for lock state of its current input */
4112                         val = hdspm_tco_input_check(hdspm, HDSPM_TCO1_TCO_lock);
4113                         break;
4114                 case 12:
4115                         /* Check TCO for valid time code on LTC input. */
4116                         val = hdspm_tco_input_check(hdspm,
4117                                 HDSPM_TCO1_LTC_Input_valid);
4118                         break;
4119                 default:
4120                         break;
4121                 }
4122         }
4123 
4124         if (-1 == val)
4125                 val = 3;
4126 
4127         ucontrol->value.enumerated.item[0] = val;
4128         return 0;
4129 }
4130 
4131 
4132 
4133 /**
4134  * TCO controls
4135  **/
4136 static void hdspm_tco_write(struct hdspm *hdspm)
4137 {
4138         unsigned int tc[4] = { 0, 0, 0, 0};
4139 
4140         switch (hdspm->tco->input) {
4141         case 0:
4142                 tc[2] |= HDSPM_TCO2_set_input_MSB;
4143                 break;
4144         case 1:
4145                 tc[2] |= HDSPM_TCO2_set_input_LSB;
4146                 break;
4147         default:
4148                 break;
4149         }
4150 
4151         switch (hdspm->tco->framerate) {
4152         case 1:
4153                 tc[1] |= HDSPM_TCO1_LTC_Format_LSB;
4154                 break;
4155         case 2:
4156                 tc[1] |= HDSPM_TCO1_LTC_Format_MSB;
4157                 break;
4158         case 3:
4159                 tc[1] |= HDSPM_TCO1_LTC_Format_MSB +
4160                         HDSPM_TCO1_set_drop_frame_flag;
4161                 break;
4162         case 4:
4163                 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
4164                         HDSPM_TCO1_LTC_Format_MSB;
4165                 break;
4166         case 5:
4167                 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
4168                         HDSPM_TCO1_LTC_Format_MSB +
4169                         HDSPM_TCO1_set_drop_frame_flag;
4170                 break;
4171         default:
4172                 break;
4173         }
4174 
4175         switch (hdspm->tco->wordclock) {
4176         case 1:
4177                 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB;
4178                 break;
4179         case 2:
4180                 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB;
4181                 break;
4182         default:
4183                 break;
4184         }
4185 
4186         switch (hdspm->tco->samplerate) {
4187         case 1:
4188                 tc[2] |= HDSPM_TCO2_set_freq;
4189                 break;
4190         case 2:
4191                 tc[2] |= HDSPM_TCO2_set_freq_from_app;
4192                 break;
4193         default:
4194                 break;
4195         }
4196 
4197         switch (hdspm->tco->pull) {
4198         case 1:
4199                 tc[2] |= HDSPM_TCO2_set_pull_up;
4200                 break;
4201         case 2:
4202                 tc[2] |= HDSPM_TCO2_set_pull_down;
4203                 break;
4204         case 3:
4205                 tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4;
4206                 break;
4207         case 4:
4208                 tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4;
4209                 break;
4210         default:
4211                 break;
4212         }
4213 
4214         if (1 == hdspm->tco->term) {
4215                 tc[2] |= HDSPM_TCO2_set_term_75R;
4216         }
4217 
4218         hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]);
4219         hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]);
4220         hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]);
4221         hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]);
4222 }
4223 
4224 
4225 #define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \
4226 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4227         .name = xname, \
4228         .index = xindex, \
4229         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4230                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4231         .info = snd_hdspm_info_tco_sample_rate, \
4232         .get = snd_hdspm_get_tco_sample_rate, \
4233         .put = snd_hdspm_put_tco_sample_rate \
4234 }
4235 
4236 static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol,
4237                                           struct snd_ctl_elem_info *uinfo)
4238 {
4239         /* TODO freq from app could be supported here, see tco->samplerate */
4240         static const char *const texts[] = { "44.1 kHz", "48 kHz" };
4241         ENUMERATED_CTL_INFO(uinfo, texts);
4242         return 0;
4243 }
4244 
4245 static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol,
4246                                       struct snd_ctl_elem_value *ucontrol)
4247 {
4248         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4249 
4250         ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate;
4251 
4252         return 0;
4253 }
4254 
4255 static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol,
4256                                          struct snd_ctl_elem_value *ucontrol)
4257 {
4258         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4259 
4260         if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) {
4261                 hdspm->tco->samplerate = ucontrol->value.enumerated.item[0];
4262 
4263                 hdspm_tco_write(hdspm);
4264 
4265                 return 1;
4266         }
4267 
4268         return 0;
4269 }
4270 
4271 
4272 #define HDSPM_TCO_PULL(xname, xindex) \
4273 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4274         .name = xname, \
4275         .index = xindex, \
4276         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4277                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4278         .info = snd_hdspm_info_tco_pull, \
4279         .get = snd_hdspm_get_tco_pull, \
4280         .put = snd_hdspm_put_tco_pull \
4281 }
4282 
4283 static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol,
4284                                    struct snd_ctl_elem_info *uinfo)
4285 {
4286         static const char *const texts[] = { "", "+ 0.1 %", "- 0.1 %",
4287                 "+ 4 %", "- 4 %" };
4288         ENUMERATED_CTL_INFO(uinfo, texts);
4289         return 0;
4290 }
4291 
4292 static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol,
4293                                   struct snd_ctl_elem_value *ucontrol)
4294 {
4295         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4296 
4297         ucontrol->value.enumerated.item[0] = hdspm->tco->pull;
4298 
4299         return 0;
4300 }
4301 
4302 static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol,
4303                                   struct snd_ctl_elem_value *ucontrol)
4304 {
4305         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4306 
4307         if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) {
4308                 hdspm->tco->pull = ucontrol->value.enumerated.item[0];
4309 
4310                 hdspm_tco_write(hdspm);
4311 
4312                 return 1;
4313         }
4314 
4315         return 0;
4316 }
4317 
4318 #define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \
4319 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4320         .name = xname, \
4321         .index = xindex, \
4322         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4323                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4324         .info = snd_hdspm_info_tco_wck_conversion, \
4325         .get = snd_hdspm_get_tco_wck_conversion, \
4326         .put = snd_hdspm_put_tco_wck_conversion \
4327 }
4328 
4329 static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4330                                              struct snd_ctl_elem_info *uinfo)
4331 {
4332         static const char *const texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" };
4333         ENUMERATED_CTL_INFO(uinfo, texts);
4334         return 0;
4335 }
4336 
4337 static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4338                                             struct snd_ctl_elem_value *ucontrol)
4339 {
4340         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4341 
4342         ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock;
4343 
4344         return 0;
4345 }
4346 
4347 static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4348                                             struct snd_ctl_elem_value *ucontrol)
4349 {
4350         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4351 
4352         if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) {
4353                 hdspm->tco->wordclock = ucontrol->value.enumerated.item[0];
4354 
4355                 hdspm_tco_write(hdspm);
4356 
4357                 return 1;
4358         }
4359 
4360         return 0;
4361 }
4362 
4363 
4364 #define HDSPM_TCO_FRAME_RATE(xname, xindex) \
4365 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4366         .name = xname, \
4367         .index = xindex, \
4368         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4369                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4370         .info = snd_hdspm_info_tco_frame_rate, \
4371         .get = snd_hdspm_get_tco_frame_rate, \
4372         .put = snd_hdspm_put_tco_frame_rate \
4373 }
4374 
4375 static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol,
4376                                           struct snd_ctl_elem_info *uinfo)
4377 {
4378         static const char *const texts[] = { "24 fps", "25 fps", "29.97fps",
4379                 "29.97 dfps", "30 fps", "30 dfps" };
4380         ENUMERATED_CTL_INFO(uinfo, texts);
4381         return 0;
4382 }
4383 
4384 static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol,
4385                                         struct snd_ctl_elem_value *ucontrol)
4386 {
4387         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4388 
4389         ucontrol->value.enumerated.item[0] = hdspm->tco->framerate;
4390 
4391         return 0;
4392 }
4393 
4394 static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol,
4395                                         struct snd_ctl_elem_value *ucontrol)
4396 {
4397         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4398 
4399         if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) {
4400                 hdspm->tco->framerate = ucontrol->value.enumerated.item[0];
4401 
4402                 hdspm_tco_write(hdspm);
4403 
4404                 return 1;
4405         }
4406 
4407         return 0;
4408 }
4409 
4410 
4411 #define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \
4412 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4413         .name = xname, \
4414         .index = xindex, \
4415         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4416                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4417         .info = snd_hdspm_info_tco_sync_source, \
4418         .get = snd_hdspm_get_tco_sync_source, \
4419         .put = snd_hdspm_put_tco_sync_source \
4420 }
4421 
4422 static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol,
4423                                           struct snd_ctl_elem_info *uinfo)
4424 {
4425         static const char *const texts[] = { "LTC", "Video", "WCK" };
4426         ENUMERATED_CTL_INFO(uinfo, texts);
4427         return 0;
4428 }
4429 
4430 static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol,
4431                                          struct snd_ctl_elem_value *ucontrol)
4432 {
4433         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4434 
4435         ucontrol->value.enumerated.item[0] = hdspm->tco->input;
4436 
4437         return 0;
4438 }
4439 
4440 static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol,
4441                                          struct snd_ctl_elem_value *ucontrol)
4442 {
4443         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4444 
4445         if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) {
4446                 hdspm->tco->input = ucontrol->value.enumerated.item[0];
4447 
4448                 hdspm_tco_write(hdspm);
4449 
4450                 return 1;
4451         }
4452 
4453         return 0;
4454 }
4455 
4456 
4457 #define HDSPM_TCO_WORD_TERM(xname, xindex) \
4458 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4459         .name = xname, \
4460         .index = xindex, \
4461         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4462                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4463         .info = snd_hdspm_info_tco_word_term, \
4464         .get = snd_hdspm_get_tco_word_term, \
4465         .put = snd_hdspm_put_tco_word_term \
4466 }
4467 
4468 static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol,
4469                                         struct snd_ctl_elem_info *uinfo)
4470 {
4471         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
4472         uinfo->count = 1;
4473         uinfo->value.integer.min = 0;
4474         uinfo->value.integer.max = 1;
4475 
4476         return 0;
4477 }
4478 
4479 
4480 static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol,
4481                                        struct snd_ctl_elem_value *ucontrol)
4482 {
4483         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4484 
4485         ucontrol->value.integer.value[0] = hdspm->tco->term;
4486 
4487         return 0;
4488 }
4489 
4490 
4491 static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol,
4492                                        struct snd_ctl_elem_value *ucontrol)
4493 {
4494         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4495 
4496         if (hdspm->tco->term != ucontrol->value.integer.value[0]) {
4497                 hdspm->tco->term = ucontrol->value.integer.value[0];
4498 
4499                 hdspm_tco_write(hdspm);
4500 
4501                 return 1;
4502         }
4503 
4504         return 0;
4505 }
4506 
4507 
4508 
4509 
4510 static struct snd_kcontrol_new snd_hdspm_controls_madi[] = {
4511         HDSPM_MIXER("Mixer", 0),
4512         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4513         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4514         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4515         HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4516         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4517         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4518         HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4519         HDSPM_SYNC_CHECK("MADI SyncCheck", 1),
4520         HDSPM_SYNC_CHECK("TCO SyncCheck", 2),
4521         HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3),
4522         HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut),
4523         HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch),
4524         HDSPM_TOGGLE_SETTING("Disable 96K frames", HDSPM_SMUX),
4525         HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
4526         HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp),
4527         HDSPM_INPUT_SELECT("Input Select", 0),
4528         HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4529 };
4530 
4531 
4532 static struct snd_kcontrol_new snd_hdspm_controls_madiface[] = {
4533         HDSPM_MIXER("Mixer", 0),
4534         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4535         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4536         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4537         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4538         HDSPM_SYNC_CHECK("MADI SyncCheck", 0),
4539         HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch),
4540         HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
4541         HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp),
4542         HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4543 };
4544 
4545 static struct snd_kcontrol_new snd_hdspm_controls_aio[] = {
4546         HDSPM_MIXER("Mixer", 0),
4547         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4548         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4549         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4550         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4551         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4552         HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4553         HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4554         HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4555         HDSPM_SYNC_CHECK("ADAT SyncCheck", 3),
4556         HDSPM_SYNC_CHECK("TCO SyncCheck", 4),
4557         HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5),
4558         HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4559         HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4560         HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4561         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3),
4562         HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4),
4563         HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5),
4564         HDSPM_CONTROL_TRISTATE("S/PDIF Input", HDSPM_c0_Input0),
4565         HDSPM_TOGGLE_SETTING("S/PDIF Out Optical", HDSPM_c0_Spdif_Opt),
4566         HDSPM_TOGGLE_SETTING("S/PDIF Out Professional", HDSPM_c0_Pro),
4567         HDSPM_TOGGLE_SETTING("ADAT internal (AEB/TEB)", HDSPM_c0_AEB1),
4568         HDSPM_TOGGLE_SETTING("XLR Breakout Cable", HDSPM_c0_Sym6db),
4569         HDSPM_TOGGLE_SETTING("Single Speed WordClock Out", HDSPM_c0_Wck48),
4570         HDSPM_CONTROL_TRISTATE("Input Level", HDSPM_c0_AD_GAIN0),
4571         HDSPM_CONTROL_TRISTATE("Output Level", HDSPM_c0_DA_GAIN0),
4572         HDSPM_CONTROL_TRISTATE("Phones Level", HDSPM_c0_PH_GAIN0)
4573 
4574                 /*
4575                    HDSPM_INPUT_SELECT("Input Select", 0),
4576                    HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0),
4577                    HDSPM_PROFESSIONAL("SPDIF Out Professional", 0);
4578                    HDSPM_SPDIF_IN("SPDIF In", 0);
4579                    HDSPM_BREAKOUT_CABLE("Breakout Cable", 0);
4580                    HDSPM_INPUT_LEVEL("Input Level", 0);
4581                    HDSPM_OUTPUT_LEVEL("Output Level", 0);
4582                    HDSPM_PHONES("Phones", 0);
4583                    */
4584 };
4585 
4586 static struct snd_kcontrol_new snd_hdspm_controls_raydat[] = {
4587         HDSPM_MIXER("Mixer", 0),
4588         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4589         HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0),
4590         HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0),
4591         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4592         HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4593         HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4594         HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4595         HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3),
4596         HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4),
4597         HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5),
4598         HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6),
4599         HDSPM_SYNC_CHECK("TCO SyncCheck", 7),
4600         HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8),
4601         HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4602         HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4603         HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4604         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3),
4605         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4),
4606         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5),
4607         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6),
4608         HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7),
4609         HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8),
4610         HDSPM_TOGGLE_SETTING("S/PDIF Out Professional", HDSPM_c0_Pro),
4611         HDSPM_TOGGLE_SETTING("Single Speed WordClock Out", HDSPM_c0_Wck48)
4612 };
4613 
4614 static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = {
4615         HDSPM_MIXER("Mixer", 0),
4616         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4617         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4618         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4619         HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4620         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4621         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 11),
4622         HDSPM_SYNC_CHECK("WC Sync Check", 0),
4623         HDSPM_SYNC_CHECK("AES1 Sync Check", 1),
4624         HDSPM_SYNC_CHECK("AES2 Sync Check", 2),
4625         HDSPM_SYNC_CHECK("AES3 Sync Check", 3),
4626         HDSPM_SYNC_CHECK("AES4 Sync Check", 4),
4627         HDSPM_SYNC_CHECK("AES5 Sync Check", 5),
4628         HDSPM_SYNC_CHECK("AES6 Sync Check", 6),
4629         HDSPM_SYNC_CHECK("AES7 Sync Check", 7),
4630         HDSPM_SYNC_CHECK("AES8 Sync Check", 8),
4631         HDSPM_SYNC_CHECK("TCO Sync Check", 9),
4632         HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10),
4633         HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4634         HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1),
4635         HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2),
4636         HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3),
4637         HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4),
4638         HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5),
4639         HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6),
4640         HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7),
4641         HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8),
4642         HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9),
4643         HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10),
4644         HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut),
4645         HDSPM_TOGGLE_SETTING("Emphasis", HDSPM_Emphasis),
4646         HDSPM_TOGGLE_SETTING("Non Audio", HDSPM_Dolby),
4647         HDSPM_TOGGLE_SETTING("Professional", HDSPM_Professional),
4648         HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
4649         HDSPM_DS_WIRE("Double Speed Wire Mode", 0),
4650         HDSPM_QS_WIRE("Quad Speed Wire Mode", 0),
4651 };
4652 
4653 
4654 
4655 /* Control elements for the optional TCO module */
4656 static struct snd_kcontrol_new snd_hdspm_controls_tco[] = {
4657         HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0),
4658         HDSPM_TCO_PULL("TCO Pull", 0),
4659         HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0),
4660         HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0),
4661         HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0),
4662         HDSPM_TCO_WORD_TERM("TCO Word Term", 0),
4663         HDSPM_TCO_LOCK_CHECK("TCO Input Check", 11),
4664         HDSPM_TCO_LOCK_CHECK("TCO LTC Valid", 12),
4665         HDSPM_TCO_LTC_FRAMES("TCO Detected Frame Rate", 0),
4666         HDSPM_TCO_VIDEO_INPUT_FORMAT("Video Input Format", 0)
4667 };
4668 
4669 
4670 static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER;
4671 
4672 
4673 static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm)
4674 {
4675         int i;
4676 
4677         for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) {
4678                 if (hdspm->system_sample_rate > 48000) {
4679                         hdspm->playback_mixer_ctls[i]->vd[0].access =
4680                                 SNDRV_CTL_ELEM_ACCESS_INACTIVE |
4681                                 SNDRV_CTL_ELEM_ACCESS_READ |
4682                                 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4683                 } else {
4684                         hdspm->playback_mixer_ctls[i]->vd[0].access =
4685                                 SNDRV_CTL_ELEM_ACCESS_READWRITE |
4686                                 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4687                 }
4688                 snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE |
4689                                 SNDRV_CTL_EVENT_MASK_INFO,
4690                                 &hdspm->playback_mixer_ctls[i]->id);
4691         }
4692 
4693         return 0;
4694 }
4695 
4696 
4697 static int snd_hdspm_create_controls(struct snd_card *card,
4698                                         struct hdspm *hdspm)
4699 {
4700         unsigned int idx, limit;
4701         int err;
4702         struct snd_kcontrol *kctl;
4703         struct snd_kcontrol_new *list = NULL;
4704 
4705         switch (hdspm->io_type) {
4706         case MADI:
4707                 list = snd_hdspm_controls_madi;
4708                 limit = ARRAY_SIZE(snd_hdspm_controls_madi);
4709                 break;
4710         case MADIface:
4711                 list = snd_hdspm_controls_madiface;
4712                 limit = ARRAY_SIZE(snd_hdspm_controls_madiface);
4713                 break;
4714         case AIO:
4715                 list = snd_hdspm_controls_aio;
4716                 limit = ARRAY_SIZE(snd_hdspm_controls_aio);
4717                 break;
4718         case RayDAT:
4719                 list = snd_hdspm_controls_raydat;
4720                 limit = ARRAY_SIZE(snd_hdspm_controls_raydat);
4721                 break;
4722         case AES32:
4723                 list = snd_hdspm_controls_aes32;
4724                 limit = ARRAY_SIZE(snd_hdspm_controls_aes32);
4725                 break;
4726         }
4727 
4728         if (NULL != list) {
4729                 for (idx = 0; idx < limit; idx++) {
4730                         err = snd_ctl_add(card,
4731                                         snd_ctl_new1(&list[idx], hdspm));
4732                         if (err < 0)
4733                                 return err;
4734                 }
4735         }
4736 
4737 
4738         /* create simple 1:1 playback mixer controls */
4739         snd_hdspm_playback_mixer.name = "Chn";
4740         if (hdspm->system_sample_rate >= 128000) {
4741                 limit = hdspm->qs_out_channels;
4742         } else if (hdspm->system_sample_rate >= 64000) {
4743                 limit = hdspm->ds_out_channels;
4744         } else {
4745                 limit = hdspm->ss_out_channels;
4746         }
4747         for (idx = 0; idx < limit; ++idx) {
4748                 snd_hdspm_playback_mixer.index = idx + 1;
4749                 kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm);
4750                 err = snd_ctl_add(card, kctl);
4751                 if (err < 0)
4752                         return err;
4753                 hdspm->playback_mixer_ctls[idx] = kctl;
4754         }
4755 
4756 
4757         if (hdspm->tco) {
4758                 /* add tco control elements */
4759                 list = snd_hdspm_controls_tco;
4760                 limit = ARRAY_SIZE(snd_hdspm_controls_tco);
4761                 for (idx = 0; idx < limit; idx++) {
4762                         err = snd_ctl_add(card,
4763                                         snd_ctl_new1(&list[idx], hdspm));
4764                         if (err < 0)
4765                                 return err;
4766                 }
4767         }
4768 
4769         return 0;
4770 }
4771 
4772 /*------------------------------------------------------------
4773    /proc interface
4774  ------------------------------------------------------------*/
4775 
4776 static void
4777 snd_hdspm_proc_read_tco(struct snd_info_entry *entry,
4778                                         struct snd_info_buffer *buffer)
4779 {
4780         struct hdspm *hdspm = entry->private_data;
4781         unsigned int status, control;
4782         int a, ltc, frames, seconds, minutes, hours;
4783         unsigned int period;
4784         u64 freq_const = 0;
4785         u32 rate;
4786 
4787         snd_iprintf(buffer, "--- TCO ---\n");
4788 
4789         status = hdspm_read(hdspm, HDSPM_statusRegister);
4790         control = hdspm->control_register;
4791 
4792 
4793         if (status & HDSPM_tco_detect) {
4794                 snd_iprintf(buffer, "TCO module detected.\n");
4795                 a = hdspm_read(hdspm, HDSPM_RD_TCO+4);
4796                 if (a & HDSPM_TCO1_LTC_Input_valid) {
4797                         snd_iprintf(buffer, "  LTC valid, ");
4798                         switch (a & (HDSPM_TCO1_LTC_Format_LSB |
4799                                                 HDSPM_TCO1_LTC_Format_MSB)) {
4800                         case 0:
4801                                 snd_iprintf(buffer, "24 fps, ");
4802                                 break;
4803                         case HDSPM_TCO1_LTC_Format_LSB:
4804                                 snd_iprintf(buffer, "25 fps, ");
4805                                 break;
4806                         case HDSPM_TCO1_LTC_Format_MSB:
4807                                 snd_iprintf(buffer, "29.97 fps, ");
4808                                 break;
4809                         default:
4810                                 snd_iprintf(buffer, "30 fps, ");
4811                                 break;
4812                         }
4813                         if (a & HDSPM_TCO1_set_drop_frame_flag) {
4814                                 snd_iprintf(buffer, "drop frame\n");
4815                         } else {
4816                                 snd_iprintf(buffer, "full frame\n");
4817                         }
4818                 } else {
4819                         snd_iprintf(buffer, "  no LTC\n");
4820                 }
4821                 if (a & HDSPM_TCO1_Video_Input_Format_NTSC) {
4822                         snd_iprintf(buffer, "  Video: NTSC\n");
4823                 } else if (a & HDSPM_TCO1_Video_Input_Format_PAL) {
4824                         snd_iprintf(buffer, "  Video: PAL\n");
4825                 } else {
4826                         snd_iprintf(buffer, "  No video\n");
4827                 }
4828                 if (a & HDSPM_TCO1_TCO_lock) {
4829                         snd_iprintf(buffer, "  Sync: lock\n");
4830                 } else {
4831                         snd_iprintf(buffer, "  Sync: no lock\n");
4832                 }
4833 
4834                 switch (hdspm->io_type) {
4835                 case MADI:
4836                 case AES32:
4837                         freq_const = 110069313433624ULL;
4838                         break;
4839                 case RayDAT:
4840                 case AIO:
4841                         freq_const = 104857600000000ULL;
4842                         break;
4843                 case MADIface:
4844                         break; /* no TCO possible */
4845                 }
4846 
4847                 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
4848                 snd_iprintf(buffer, "    period: %u\n", period);
4849 
4850 
4851                 /* rate = freq_const/period; */
4852                 rate = div_u64(freq_const, period);
4853 
4854                 if (control & HDSPM_QuadSpeed) {
4855                         rate *= 4;
4856                 } else if (control & HDSPM_DoubleSpeed) {
4857                         rate *= 2;
4858                 }
4859 
4860                 snd_iprintf(buffer, "  Frequency: %u Hz\n",
4861                                 (unsigned int) rate);
4862 
4863                 ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
4864                 frames = ltc & 0xF;
4865                 ltc >>= 4;
4866                 frames += (ltc & 0x3) * 10;
4867                 ltc >>= 4;
4868                 seconds = ltc & 0xF;
4869                 ltc >>= 4;
4870                 seconds += (ltc & 0x7) * 10;
4871                 ltc >>= 4;
4872                 minutes = ltc & 0xF;
4873                 ltc >>= 4;
4874                 minutes += (ltc & 0x7) * 10;
4875                 ltc >>= 4;
4876                 hours = ltc & 0xF;
4877                 ltc >>= 4;
4878                 hours += (ltc & 0x3) * 10;
4879                 snd_iprintf(buffer,
4880                         "  LTC In: %02d:%02d:%02d:%02d\n",
4881                         hours, minutes, seconds, frames);
4882 
4883         } else {
4884                 snd_iprintf(buffer, "No TCO module detected.\n");
4885         }
4886 }
4887 
4888 static void
4889 snd_hdspm_proc_read_madi(struct snd_info_entry *entry,
4890                          struct snd_info_buffer *buffer)
4891 {
4892         struct hdspm *hdspm = entry->private_data;
4893         unsigned int status, status2, control, freq;
4894 
4895         char *pref_sync_ref;
4896         char *autosync_ref;
4897         char *system_clock_mode;
4898         char *insel;
4899         int x, x2;
4900 
4901         status = hdspm_read(hdspm, HDSPM_statusRegister);
4902         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4903         control = hdspm->control_register;
4904         freq = hdspm_read(hdspm, HDSPM_timecodeRegister);
4905 
4906         snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n",
4907                         hdspm->card_name, hdspm->card->number + 1,
4908                         hdspm->firmware_rev,
4909                         (status2 & HDSPM_version0) |
4910                         (status2 & HDSPM_version1) | (status2 &
4911                                 HDSPM_version2));
4912 
4913         snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n",
4914                         (hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF,
4915                         hdspm->serial);
4916 
4917         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4918                         hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4919 
4920         snd_iprintf(buffer, "--- System ---\n");
4921 
4922         snd_iprintf(buffer,
4923                 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4924                 status & HDSPM_audioIRQPending,
4925                 (status & HDSPM_midi0IRQPending) ? 1 : 0,
4926                 (status & HDSPM_midi1IRQPending) ? 1 : 0,
4927                 hdspm->irq_count);
4928         snd_iprintf(buffer,
4929                 "HW pointer: id = %d, rawptr = %d (%d->%d) "
4930                 "estimated= %ld (bytes)\n",
4931                 ((status & HDSPM_BufferID) ? 1 : 0),
4932                 (status & HDSPM_BufferPositionMask),
4933                 (status & HDSPM_BufferPositionMask) %
4934                 (2 * (int)hdspm->period_bytes),
4935                 ((status & HDSPM_BufferPositionMask) - 64) %
4936                 (2 * (int)hdspm->period_bytes),
4937                 (long) hdspm_hw_pointer(hdspm) * 4);
4938 
4939         snd_iprintf(buffer,
4940                 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
4941                 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
4942                 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
4943                 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
4944                 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
4945         snd_iprintf(buffer,
4946                 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
4947                 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
4948                 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
4949         snd_iprintf(buffer,
4950                 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
4951                 "status2=0x%x\n",
4952                 hdspm->control_register, hdspm->control2_register,
4953                 status, status2);
4954 
4955 
4956         snd_iprintf(buffer, "--- Settings ---\n");
4957 
4958         x = hdspm_get_latency(hdspm);
4959 
4960         snd_iprintf(buffer,
4961                 "Size (Latency): %d samples (2 periods of %lu bytes)\n",
4962                 x, (unsigned long) hdspm->period_bytes);
4963 
4964         snd_iprintf(buffer, "Line out: %s\n",
4965                 (hdspm->control_register & HDSPM_LineOut) ? "on " : "off");
4966 
4967         switch (hdspm->control_register & HDSPM_InputMask) {
4968         case HDSPM_InputOptical:
4969                 insel = "Optical";
4970                 break;
4971         case HDSPM_InputCoaxial:
4972                 insel = "Coaxial";
4973                 break;
4974         default:
4975                 insel = "Unknown";
4976         }
4977 
4978         snd_iprintf(buffer,
4979                 "ClearTrackMarker = %s, Transmit in %s Channel Mode, "
4980                 "Auto Input %s\n",
4981                 (hdspm->control_register & HDSPM_clr_tms) ? "on" : "off",
4982                 (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56",
4983                 (hdspm->control_register & HDSPM_AutoInp) ? "on" : "off");
4984 
4985 
4986         if (!(hdspm->control_register & HDSPM_ClockModeMaster))
4987                 system_clock_mode = "AutoSync";
4988         else
4989                 system_clock_mode = "Master";
4990         snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode);
4991 
4992         switch (hdspm_pref_sync_ref(hdspm)) {
4993         case HDSPM_SYNC_FROM_WORD:
4994                 pref_sync_ref = "Word Clock";
4995                 break;
4996         case HDSPM_SYNC_FROM_MADI:
4997                 pref_sync_ref = "MADI Sync";
4998                 break;
4999         case HDSPM_SYNC_FROM_TCO:
5000                 pref_sync_ref = "TCO";
5001                 break;
5002         case HDSPM_SYNC_FROM_SYNC_IN:
5003                 pref_sync_ref = "Sync In";
5004                 break;
5005         default:
5006                 pref_sync_ref = "XXXX Clock";
5007                 break;
5008         }
5009         snd_iprintf(buffer, "Preferred Sync Reference: %s\n",
5010                         pref_sync_ref);
5011 
5012         snd_iprintf(buffer, "System Clock Frequency: %d\n",
5013                         hdspm->system_sample_rate);
5014 
5015 
5016         snd_iprintf(buffer, "--- Status:\n");
5017 
5018         x = status & HDSPM_madiSync;
5019         x2 = status2 & HDSPM_wcSync;
5020 
5021         snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n",
5022                         (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") :
5023                         "NoLock",
5024                         (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") :
5025                         "NoLock");
5026 
5027         switch (hdspm_autosync_ref(hdspm)) {
5028         case HDSPM_AUTOSYNC_FROM_SYNC_IN:
5029                 autosync_ref = "Sync In";
5030                 break;
5031         case HDSPM_AUTOSYNC_FROM_TCO:
5032                 autosync_ref = "TCO";
5033                 break;
5034         case HDSPM_AUTOSYNC_FROM_WORD:
5035                 autosync_ref = "Word Clock";
5036                 break;
5037         case HDSPM_AUTOSYNC_FROM_MADI:
5038                 autosync_ref = "MADI Sync";
5039                 break;
5040         case HDSPM_AUTOSYNC_FROM_NONE:
5041                 autosync_ref = "Input not valid";
5042                 break;
5043         default:
5044                 autosync_ref = "---";
5045                 break;
5046         }
5047         snd_iprintf(buffer,
5048                 "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n",
5049                 autosync_ref, hdspm_external_sample_rate(hdspm),
5050                 (status & HDSPM_madiFreqMask) >> 22,
5051                 (status2 & HDSPM_wcFreqMask) >> 5);
5052 
5053         snd_iprintf(buffer, "Input: %s, Mode=%s\n",
5054                 (status & HDSPM_AB_int) ? "Coax" : "Optical",
5055                 (status & HDSPM_RX_64ch) ? "64 channels" :
5056                 "56 channels");
5057 
5058         /* call readout function for TCO specific status */
5059         snd_hdspm_proc_read_tco(entry, buffer);
5060 
5061         snd_iprintf(buffer, "\n");
5062 }
5063 
5064 static void
5065 snd_hdspm_proc_read_aes32(struct snd_info_entry * entry,
5066                           struct snd_info_buffer *buffer)
5067 {
5068         struct hdspm *hdspm = entry->private_data;
5069         unsigned int status;
5070         unsigned int status2;
5071         unsigned int timecode;
5072         unsigned int wcLock, wcSync;
5073         int pref_syncref;
5074         char *autosync_ref;
5075         int x;
5076 
5077         status = hdspm_read(hdspm, HDSPM_statusRegister);
5078         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
5079         timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
5080 
5081         snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n",
5082                     hdspm->card_name, hdspm->card->number + 1,
5083                     hdspm->firmware_rev);
5084 
5085         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
5086                     hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
5087 
5088         snd_iprintf(buffer, "--- System ---\n");
5089 
5090         snd_iprintf(buffer,
5091                     "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
5092                     status & HDSPM_audioIRQPending,
5093                     (status & HDSPM_midi0IRQPending) ? 1 : 0,
5094                     (status & HDSPM_midi1IRQPending) ? 1 : 0,
5095                     hdspm->irq_count);
5096         snd_iprintf(buffer,
5097                     "HW pointer: id = %d, rawptr = %d (%d->%d) "
5098                     "estimated= %ld (bytes)\n",
5099                     ((status & HDSPM_BufferID) ? 1 : 0),
5100                     (status & HDSPM_BufferPositionMask),
5101                     (status & HDSPM_BufferPositionMask) %
5102                     (2 * (int)hdspm->period_bytes),
5103                     ((status & HDSPM_BufferPositionMask) - 64) %
5104                     (2 * (int)hdspm->period_bytes),
5105                     (long) hdspm_hw_pointer(hdspm) * 4);
5106 
5107         snd_iprintf(buffer,
5108                     "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
5109                     hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
5110                     hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
5111                     hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
5112                     hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
5113         snd_iprintf(buffer,
5114                     "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
5115                     hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
5116                     hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
5117         snd_iprintf(buffer,
5118                     "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
5119                     "status2=0x%x\n",
5120                     hdspm->control_register, hdspm->control2_register,
5121                     status, status2);
5122 
5123         snd_iprintf(buffer, "--- Settings ---\n");
5124 
5125         x = hdspm_get_latency(hdspm);
5126 
5127         snd_iprintf(buffer,
5128                     "Size (Latency): %d samples (2 periods of %lu bytes)\n",
5129                     x, (unsigned long) hdspm->period_bytes);
5130 
5131         snd_iprintf(buffer, "Line out: %s\n",
5132                     (hdspm->
5133                      control_register & HDSPM_LineOut) ? "on " : "off");
5134 
5135         snd_iprintf(buffer,
5136                     "ClearTrackMarker %s, Emphasis %s, Dolby %s\n",
5137                     (hdspm->
5138                      control_register & HDSPM_clr_tms) ? "on" : "off",
5139                     (hdspm->
5140                      control_register & HDSPM_Emphasis) ? "on" : "off",
5141                     (hdspm->
5142                      control_register & HDSPM_Dolby) ? "on" : "off");
5143 
5144 
5145         pref_syncref = hdspm_pref_sync_ref(hdspm);
5146         if (pref_syncref == 0)
5147                 snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n");
5148         else
5149                 snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n",
5150                                 pref_syncref);
5151 
5152         snd_iprintf(buffer, "System Clock Frequency: %d\n",
5153                     hdspm->system_sample_rate);
5154 
5155         snd_iprintf(buffer, "Double speed: %s\n",
5156                         hdspm->control_register & HDSPM_DS_DoubleWire?
5157                         "Double wire" : "Single wire");
5158         snd_iprintf(buffer, "Quad speed: %s\n",
5159                         hdspm->control_register & HDSPM_QS_DoubleWire?
5160                         "Double wire" :
5161                         hdspm->control_register & HDSPM_QS_QuadWire?
5162                         "Quad wire" : "Single wire");
5163 
5164         snd_iprintf(buffer, "--- Status:\n");
5165 
5166         wcLock = status & HDSPM_AES32_wcLock;
5167         wcSync = wcLock && (status & HDSPM_AES32_wcSync);
5168 
5169         snd_iprintf(buffer, "Word: %s  Frequency: %d\n",
5170                     (wcLock) ? (wcSync ? "Sync   " : "Lock   ") : "No Lock",
5171                     HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF));
5172 
5173         for (x = 0; x < 8; x++) {
5174                 snd_iprintf(buffer, "AES%d: %s  Frequency: %d\n",
5175                             x+1,
5176                             (status2 & (HDSPM_LockAES >> x)) ?
5177                             "Sync   " : "No Lock",
5178                             HDSPM_bit2freq((timecode >> (4*x)) & 0xF));
5179         }
5180 
5181         switch (hdspm_autosync_ref(hdspm)) {
5182         case HDSPM_AES32_AUTOSYNC_FROM_NONE:
5183                 autosync_ref = "None"; break;
5184         case HDSPM_AES32_AUTOSYNC_FROM_WORD:
5185                 autosync_ref = "Word Clock"; break;
5186         case HDSPM_AES32_AUTOSYNC_FROM_AES1:
5187                 autosync_ref = "AES1"; break;
5188         case HDSPM_AES32_AUTOSYNC_FROM_AES2:
5189                 autosync_ref = "AES2"; break;
5190         case HDSPM_AES32_AUTOSYNC_FROM_AES3:
5191                 autosync_ref = "AES3"; break;
5192         case HDSPM_AES32_AUTOSYNC_FROM_AES4:
5193                 autosync_ref = "AES4"; break;
5194         case HDSPM_AES32_AUTOSYNC_FROM_AES5:
5195                 autosync_ref = "AES5"; break;
5196         case HDSPM_AES32_AUTOSYNC_FROM_AES6:
5197                 autosync_ref = "AES6"; break;
5198         case HDSPM_AES32_AUTOSYNC_FROM_AES7:
5199                 autosync_ref = "AES7"; break;
5200         case HDSPM_AES32_AUTOSYNC_FROM_AES8:
5201                 autosync_ref = "AES8"; break;
5202         case HDSPM_AES32_AUTOSYNC_FROM_TCO:
5203                 autosync_ref = "TCO"; break;
5204         case HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN:
5205                 autosync_ref = "Sync In"; break;
5206         default:
5207                 autosync_ref = "---"; break;
5208         }
5209         snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref);
5210 
5211         /* call readout function for TCO specific status */
5212         snd_hdspm_proc_read_tco(entry, buffer);
5213 
5214         snd_iprintf(buffer, "\n");
5215 }
5216 
5217 static void
5218 snd_hdspm_proc_read_raydat(struct snd_info_entry *entry,
5219                          struct snd_info_buffer *buffer)
5220 {
5221         struct hdspm *hdspm = entry->private_data;
5222         unsigned int status1, status2, status3, control, i;
5223         unsigned int lock, sync;
5224 
5225         status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */
5226         status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */
5227         status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */
5228 
5229         control = hdspm->control_register;
5230 
5231         snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1);
5232         snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2);
5233         snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3);
5234 
5235 
5236         snd_iprintf(buffer, "\n*** CLOCK MODE\n\n");
5237 
5238         snd_iprintf(buffer, "Clock mode      : %s\n",
5239                 (hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave");
5240         snd_iprintf(buffer, "System frequency: %d Hz\n",
5241                 hdspm_get_system_sample_rate(hdspm));
5242 
5243         snd_iprintf(buffer, "\n*** INPUT STATUS\n\n");
5244 
5245         lock = 0x1;
5246         sync = 0x100;
5247 
5248         for (i = 0; i < 8; i++) {
5249                 snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n",
5250                                 i,
5251                                 (status1 & lock) ? 1 : 0,
5252                                 (status1 & sync) ? 1 : 0,
5253                                 texts_freq[(status2 >> (i * 4)) & 0xF]);
5254 
5255                 lock = lock<<1;
5256                 sync = sync<<1;
5257         }
5258 
5259         snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n",
5260                         (status1 & 0x1000000) ? 1 : 0,
5261                         (status1 & 0x2000000) ? 1 : 0,
5262                         texts_freq[(status1 >> 16) & 0xF]);
5263 
5264         snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n",
5265                         (status1 & 0x4000000) ? 1 : 0,
5266                         (status1 & 0x8000000) ? 1 : 0,
5267                         texts_freq[(status1 >> 20) & 0xF]);
5268 
5269         snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n",
5270                         (status3 & 0x400) ? 1 : 0,
5271                         (status3 & 0x800) ? 1 : 0,
5272                         texts_freq[(status2 >> 12) & 0xF]);
5273 
5274 }
5275 
5276 #ifdef CONFIG_SND_DEBUG
5277 static void
5278 snd_hdspm_proc_read_debug(struct snd_info_entry *entry,
5279                           struct snd_info_buffer *buffer)
5280 {
5281         struct hdspm *hdspm = entry->private_data;
5282 
5283         int j,i;
5284 
5285         for (i = 0; i < 256 /* 1024*64 */; i += j) {
5286                 snd_iprintf(buffer, "0x%08X: ", i);
5287                 for (j = 0; j < 16; j += 4)
5288                         snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j));
5289                 snd_iprintf(buffer, "\n");
5290         }
5291 }
5292 #endif
5293 
5294 
5295 static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry,
5296                           struct snd_info_buffer *buffer)
5297 {
5298         struct hdspm *hdspm = entry->private_data;
5299         int i;
5300 
5301         snd_iprintf(buffer, "# generated by hdspm\n");
5302 
5303         for (i = 0; i < hdspm->max_channels_in; i++) {
5304                 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]);
5305         }
5306 }
5307 
5308 static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry,
5309                           struct snd_info_buffer *buffer)
5310 {
5311         struct hdspm *hdspm = entry->private_data;
5312         int i;
5313 
5314         snd_iprintf(buffer, "# generated by hdspm\n");
5315 
5316         for (i = 0; i < hdspm->max_channels_out; i++) {
5317                 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]);
5318         }
5319 }
5320 
5321 
5322 static void snd_hdspm_proc_init(struct hdspm *hdspm)
5323 {
5324         struct snd_info_entry *entry;
5325 
5326         if (!snd_card_proc_new(hdspm->card, "hdspm", &entry)) {
5327                 switch (hdspm->io_type) {
5328                 case AES32:
5329                         snd_info_set_text_ops(entry, hdspm,
5330                                         snd_hdspm_proc_read_aes32);
5331                         break;
5332                 case MADI:
5333                         snd_info_set_text_ops(entry, hdspm,
5334                                         snd_hdspm_proc_read_madi);
5335                         break;
5336                 case MADIface:
5337                         /* snd_info_set_text_ops(entry, hdspm,
5338                          snd_hdspm_proc_read_madiface); */
5339                         break;
5340                 case RayDAT:
5341                         snd_info_set_text_ops(entry, hdspm,
5342                                         snd_hdspm_proc_read_raydat);
5343                         break;
5344                 case AIO:
5345                         break;
5346                 }
5347         }
5348 
5349         if (!snd_card_proc_new(hdspm->card, "ports.in", &entry)) {
5350                 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_in);
5351         }
5352 
5353         if (!snd_card_proc_new(hdspm->card, "ports.out", &entry)) {
5354                 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_out);
5355         }
5356 
5357 #ifdef CONFIG_SND_DEBUG
5358         /* debug file to read all hdspm registers */
5359         if (!snd_card_proc_new(hdspm->card, "debug", &entry))
5360                 snd_info_set_text_ops(entry, hdspm,
5361                                 snd_hdspm_proc_read_debug);
5362 #endif
5363 }
5364 
5365 /*------------------------------------------------------------
5366    hdspm intitialize
5367  ------------------------------------------------------------*/
5368 
5369 static int snd_hdspm_set_defaults(struct hdspm * hdspm)
5370 {
5371         /* ASSUMPTION: hdspm->lock is either held, or there is no need to
5372            hold it (e.g. during module initialization).
5373            */
5374 
5375         /* set defaults:       */
5376 
5377         hdspm->settings_register = 0;
5378 
5379         switch (hdspm->io_type) {
5380         case MADI:
5381         case MADIface:
5382                 hdspm->control_register =
5383                         0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5384                 break;
5385 
5386         case RayDAT:
5387         case AIO:
5388                 hdspm->settings_register = 0x1 + 0x1000;
5389                 /* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0,
5390                  * line_out */
5391                 hdspm->control_register =
5392                         0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5393                 break;
5394 
5395         case AES32:
5396                 hdspm->control_register =
5397                         HDSPM_ClockModeMaster | /* Master Clock Mode on */
5398                         hdspm_encode_latency(7) | /* latency max=8192samples */
5399                         HDSPM_SyncRef0 |        /* AES1 is syncclock */
5400                         HDSPM_LineOut | /* Analog output in */
5401                         HDSPM_Professional;  /* Professional mode */
5402                 break;
5403         }
5404 
5405         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5406 
5407         if (AES32 == hdspm->io_type) {
5408                 /* No control2 register for AES32 */
5409 #ifdef SNDRV_BIG_ENDIAN
5410                 hdspm->control2_register = HDSPM_BIGENDIAN_MODE;
5411 #else
5412                 hdspm->control2_register = 0;
5413 #endif
5414 
5415                 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register);
5416         }
5417         hdspm_compute_period_size(hdspm);
5418 
5419         /* silence everything */
5420 
5421         all_in_all_mixer(hdspm, 0 * UNITY_GAIN);
5422 
5423         if (hdspm_is_raydat_or_aio(hdspm))
5424                 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
5425 
5426         /* set a default rate so that the channel map is set up. */
5427         hdspm_set_rate(hdspm, 48000, 1);
5428 
5429         return 0;
5430 }
5431 
5432 
5433 /*------------------------------------------------------------
5434    interrupt
5435  ------------------------------------------------------------*/
5436 
5437 static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id)
5438 {
5439         struct hdspm *hdspm = (struct hdspm *) dev_id;
5440         unsigned int status;
5441         int i, audio, midi, schedule = 0;
5442         /* cycles_t now; */
5443 
5444         status = hdspm_read(hdspm, HDSPM_statusRegister);
5445 
5446         audio = status & HDSPM_audioIRQPending;
5447         midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending |
5448                         HDSPM_midi2IRQPending | HDSPM_midi3IRQPending);
5449 
5450         /* now = get_cycles(); */
5451         /**
5452          *   LAT_2..LAT_0 period  counter (win)  counter (mac)
5453          *          6       4096   ~256053425     ~514672358
5454          *          5       2048   ~128024983     ~257373821
5455          *          4       1024    ~64023706     ~128718089
5456          *          3        512    ~32005945      ~64385999
5457          *          2        256    ~16003039      ~32260176
5458          *          1        128     ~7998738      ~16194507
5459          *          0         64     ~3998231       ~8191558
5460          **/
5461         /*
5462            snd_printk(KERN_INFO "snd_hdspm_interrupt %llu @ %llx\n",
5463            now-hdspm->last_interrupt, status & 0xFFC0);
5464            hdspm->last_interrupt = now;
5465         */
5466 
5467         if (!audio && !midi)
5468                 return IRQ_NONE;
5469 
5470         hdspm_write(hdspm, HDSPM_interruptConfirmation, 0);
5471         hdspm->irq_count++;
5472 
5473 
5474         if (audio) {
5475                 if (hdspm->capture_substream)
5476                         snd_pcm_period_elapsed(hdspm->capture_substream);
5477 
5478                 if (hdspm->playback_substream)
5479                         snd_pcm_period_elapsed(hdspm->playback_substream);
5480         }
5481 
5482         if (midi) {
5483                 i = 0;
5484                 while (i < hdspm->midiPorts) {
5485                         if ((hdspm_read(hdspm,
5486                                 hdspm->midi[i].statusIn) & 0xff) &&
5487                                         (status & hdspm->midi[i].irq)) {
5488                                 /* we disable interrupts for this input until
5489                                  * processing is done
5490                                  */
5491                                 hdspm->control_register &= ~hdspm->midi[i].ie;
5492                                 hdspm_write(hdspm, HDSPM_controlRegister,
5493                                                 hdspm->control_register);
5494                                 hdspm->midi[i].pending = 1;
5495                                 schedule = 1;
5496                         }
5497 
5498                         i++;
5499                 }
5500 
5501                 if (schedule)
5502                         tasklet_hi_schedule(&hdspm->midi_tasklet);
5503         }
5504 
5505         return IRQ_HANDLED;
5506 }
5507 
5508 /*------------------------------------------------------------
5509    pcm interface
5510   ------------------------------------------------------------*/
5511 
5512 
5513 static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream
5514                                               *substream)
5515 {
5516         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5517         return hdspm_hw_pointer(hdspm);
5518 }
5519 
5520 
5521 static int snd_hdspm_reset(struct snd_pcm_substream *substream)
5522 {
5523         struct snd_pcm_runtime *runtime = substream->runtime;
5524         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5525         struct snd_pcm_substream *other;
5526 
5527         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5528                 other = hdspm->capture_substream;
5529         else
5530                 other = hdspm->playback_substream;
5531 
5532         if (hdspm->running)
5533                 runtime->status->hw_ptr = hdspm_hw_pointer(hdspm);
5534         else
5535                 runtime->status->hw_ptr = 0;
5536         if (other) {
5537                 struct snd_pcm_substream *s;
5538                 struct snd_pcm_runtime *oruntime = other->runtime;
5539                 snd_pcm_group_for_each_entry(s, substream) {
5540                         if (s == other) {
5541                                 oruntime->status->hw_ptr =
5542                                         runtime->status->hw_ptr;
5543                                 break;
5544                         }
5545                 }
5546         }
5547         return 0;
5548 }
5549 
5550 static int snd_hdspm_hw_params(struct snd_pcm_substream *substream,
5551                                struct snd_pcm_hw_params *params)
5552 {
5553         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5554         int err;
5555         int i;
5556         pid_t this_pid;
5557         pid_t other_pid;
5558 
5559         spin_lock_irq(&hdspm->lock);
5560 
5561         if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5562                 this_pid = hdspm->playback_pid;
5563                 other_pid = hdspm->capture_pid;
5564         } else {
5565                 this_pid = hdspm->capture_pid;
5566                 other_pid = hdspm->playback_pid;
5567         }
5568 
5569         if (other_pid > 0 && this_pid != other_pid) {
5570 
5571                 /* The other stream is open, and not by the same
5572                    task as this one. Make sure that the parameters
5573                    that matter are the same.
5574                    */
5575 
5576                 if (params_rate(params) != hdspm->system_sample_rate) {
5577                         spin_unlock_irq(&hdspm->lock);
5578                         _snd_pcm_hw_param_setempty(params,
5579                                         SNDRV_PCM_HW_PARAM_RATE);
5580                         return -EBUSY;
5581                 }
5582 
5583                 if (params_period_size(params) != hdspm->period_bytes / 4) {
5584                         spin_unlock_irq(&hdspm->lock);
5585                         _snd_pcm_hw_param_setempty(params,
5586                                         SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5587                         return -EBUSY;
5588                 }
5589 
5590         }
5591         /* We're fine. */
5592         spin_unlock_irq(&hdspm->lock);
5593 
5594         /* how to make sure that the rate matches an externally-set one ?   */
5595 
5596         spin_lock_irq(&hdspm->lock);
5597         err = hdspm_set_rate(hdspm, params_rate(params), 0);
5598         if (err < 0) {
5599                 snd_printk(KERN_INFO "err on hdspm_set_rate: %d\n", err);
5600                 spin_unlock_irq(&hdspm->lock);
5601                 _snd_pcm_hw_param_setempty(params,
5602                                 SNDRV_PCM_HW_PARAM_RATE);
5603                 return err;
5604         }
5605         spin_unlock_irq(&hdspm->lock);
5606 
5607         err = hdspm_set_interrupt_interval(hdspm,
5608                         params_period_size(params));
5609         if (err < 0) {
5610                 snd_printk(KERN_INFO "err on hdspm_set_interrupt_interval: %d\n", err);
5611                 _snd_pcm_hw_param_setempty(params,
5612                                 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5613                 return err;
5614         }
5615 
5616         /* Memory allocation, takashi's method, dont know if we should
5617          * spinlock
5618          */
5619         /* malloc all buffer even if not enabled to get sure */
5620         /* Update for MADI rev 204: we need to allocate for all channels,
5621          * otherwise it doesn't work at 96kHz */
5622 
5623         err =
5624                 snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES);
5625         if (err < 0) {
5626                 snd_printk(KERN_INFO "err on snd_pcm_lib_malloc_pages: %d\n", err);
5627                 return err;
5628         }
5629 
5630         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5631 
5632                 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferOut,
5633                                 params_channels(params));
5634 
5635                 for (i = 0; i < params_channels(params); ++i)
5636                         snd_hdspm_enable_out(hdspm, i, 1);
5637 
5638                 hdspm->playback_buffer =
5639                         (unsigned char *) substream->runtime->dma_area;
5640                 snd_printdd("Allocated sample buffer for playback at %p\n",
5641                                 hdspm->playback_buffer);
5642         } else {
5643                 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferIn,
5644                                 params_channels(params));
5645 
5646                 for (i = 0; i < params_channels(params); ++i)
5647                         snd_hdspm_enable_in(hdspm, i, 1);
5648 
5649                 hdspm->capture_buffer =
5650                         (unsigned char *) substream->runtime->dma_area;
5651                 snd_printdd("Allocated sample buffer for capture at %p\n",
5652                                 hdspm->capture_buffer);
5653         }
5654 
5655         /*
5656            snd_printdd("Allocated sample buffer for %s at 0x%08X\n",
5657            substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5658            "playback" : "capture",
5659            snd_pcm_sgbuf_get_addr(substream, 0));
5660            */
5661         /*
5662            snd_printdd("set_hwparams: %s %d Hz, %d channels, bs = %d\n",
5663            substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5664            "playback" : "capture",
5665            params_rate(params), params_channels(params),
5666            params_buffer_size(params));
5667            */
5668 
5669 
5670         /*  For AES cards, the float format bit is the same as the
5671          *  preferred sync reference. Since we don't want to break
5672          *  sync settings, we have to skip the remaining part of this
5673          *  function.
5674          */
5675         if (hdspm->io_type == AES32) {
5676                 return 0;
5677         }
5678 
5679 
5680         /* Switch to native float format if requested */
5681         if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) {
5682                 if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT))
5683                         snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE float format.\n");
5684 
5685                 hdspm->control_register |= HDSPe_FLOAT_FORMAT;
5686         } else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) {
5687                 if (hdspm->control_register & HDSPe_FLOAT_FORMAT)
5688                         snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE integer format.\n");
5689 
5690                 hdspm->control_register &= ~HDSPe_FLOAT_FORMAT;
5691         }
5692         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5693 
5694         return 0;
5695 }
5696 
5697 static int snd_hdspm_hw_free(struct snd_pcm_substream *substream)
5698 {
5699         int i;
5700         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5701 
5702         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5703 
5704                 /* params_channels(params) should be enough,
5705                    but to get sure in case of error */
5706                 for (i = 0; i < hdspm->max_channels_out; ++i)
5707                         snd_hdspm_enable_out(hdspm, i, 0);
5708 
5709                 hdspm->playback_buffer = NULL;
5710         } else {
5711                 for (i = 0; i < hdspm->max_channels_in; ++i)
5712                         snd_hdspm_enable_in(hdspm, i, 0);
5713 
5714                 hdspm->capture_buffer = NULL;
5715 
5716         }
5717 
5718         snd_pcm_lib_free_pages(substream);
5719 
5720         return 0;
5721 }
5722 
5723 
5724 static int snd_hdspm_channel_info(struct snd_pcm_substream *substream,
5725                 struct snd_pcm_channel_info *info)
5726 {
5727         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5728 
5729         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5730                 if (snd_BUG_ON(info->channel >= hdspm->max_channels_out)) {
5731                         snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel out of range (%d)\n", info->channel);
5732                         return -EINVAL;
5733                 }
5734 
5735                 if (hdspm->channel_map_out[info->channel] < 0) {
5736                         snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel %d mapped out\n", info->channel);
5737                         return -EINVAL;
5738                 }
5739 
5740                 info->offset = hdspm->channel_map_out[info->channel] *
5741                         HDSPM_CHANNEL_BUFFER_BYTES;
5742         } else {
5743                 if (snd_BUG_ON(info->channel >= hdspm->max_channels_in)) {
5744                         snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel out of range (%d)\n", info->channel);
5745                         return -EINVAL;
5746                 }
5747 
5748                 if (hdspm->channel_map_in[info->channel] < 0) {
5749                         snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel %d mapped out\n", info->channel);
5750                         return -EINVAL;
5751                 }
5752 
5753                 info->offset = hdspm->channel_map_in[info->channel] *
5754                         HDSPM_CHANNEL_BUFFER_BYTES;
5755         }
5756 
5757         info->first = 0;
5758         info->step = 32;
5759         return 0;
5760 }
5761 
5762 
5763 static int snd_hdspm_ioctl(struct snd_pcm_substream *substream,
5764                 unsigned int cmd, void *arg)
5765 {
5766         switch (cmd) {
5767         case SNDRV_PCM_IOCTL1_RESET:
5768                 return snd_hdspm_reset(substream);
5769 
5770         case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
5771                 {
5772                         struct snd_pcm_channel_info *info = arg;
5773                         return snd_hdspm_channel_info(substream, info);
5774                 }
5775         default:
5776                 break;
5777         }
5778 
5779         return snd_pcm_lib_ioctl(substream, cmd, arg);
5780 }
5781 
5782 static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd)
5783 {
5784         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5785         struct snd_pcm_substream *other;
5786         int running;
5787 
5788         spin_lock(&hdspm->lock);
5789         running = hdspm->running;
5790         switch (cmd) {
5791         case SNDRV_PCM_TRIGGER_START:
5792                 running |= 1 << substream->stream;
5793                 break;
5794         case SNDRV_PCM_TRIGGER_STOP:
5795                 running &= ~(1 << substream->stream);
5796                 break;
5797         default:
5798                 snd_BUG();
5799                 spin_unlock(&hdspm->lock);
5800                 return -EINVAL;
5801         }
5802         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5803                 other = hdspm->capture_substream;
5804         else
5805                 other = hdspm->playback_substream;
5806 
5807         if (other) {
5808                 struct snd_pcm_substream *s;
5809                 snd_pcm_group_for_each_entry(s, substream) {
5810                         if (s == other) {
5811                                 snd_pcm_trigger_done(s, substream);
5812                                 if (cmd == SNDRV_PCM_TRIGGER_START)
5813                                         running |= 1 << s->stream;
5814                                 else
5815                                         running &= ~(1 << s->stream);
5816                                 goto _ok;
5817                         }
5818                 }
5819                 if (cmd == SNDRV_PCM_TRIGGER_START) {
5820                         if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK))
5821                                         && substream->stream ==
5822                                         SNDRV_PCM_STREAM_CAPTURE)
5823                                 hdspm_silence_playback(hdspm);
5824                 } else {
5825                         if (running &&
5826                                 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5827                                 hdspm_silence_playback(hdspm);
5828                 }
5829         } else {
5830                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
5831                         hdspm_silence_playback(hdspm);
5832         }
5833 _ok:
5834         snd_pcm_trigger_done(substream, substream);
5835         if (!hdspm->running && running)
5836                 hdspm_start_audio(hdspm);
5837         else if (hdspm->running && !running)
5838                 hdspm_stop_audio(hdspm);
5839         hdspm->running = running;
5840         spin_unlock(&hdspm->lock);
5841 
5842         return 0;
5843 }
5844 
5845 static int snd_hdspm_prepare(struct snd_pcm_substream *substream)
5846 {
5847         return 0;
5848 }
5849 
5850 static struct snd_pcm_hardware snd_hdspm_playback_subinfo = {
5851         .info = (SNDRV_PCM_INFO_MMAP |
5852                  SNDRV_PCM_INFO_MMAP_VALID |
5853                  SNDRV_PCM_INFO_NONINTERLEAVED |
5854                  SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE),
5855         .formats = SNDRV_PCM_FMTBIT_S32_LE,
5856         .rates = (SNDRV_PCM_RATE_32000 |
5857                   SNDRV_PCM_RATE_44100 |
5858                   SNDRV_PCM_RATE_48000 |
5859                   SNDRV_PCM_RATE_64000 |
5860                   SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5861                   SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ),
5862         .rate_min = 32000,
5863         .rate_max = 192000,
5864         .channels_min = 1,
5865         .channels_max = HDSPM_MAX_CHANNELS,
5866         .buffer_bytes_max =
5867             HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5868         .period_bytes_min = (32 * 4),
5869         .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
5870         .periods_min = 2,
5871         .periods_max = 512,
5872         .fifo_size = 0
5873 };
5874 
5875 static struct snd_pcm_hardware snd_hdspm_capture_subinfo = {
5876         .info = (SNDRV_PCM_INFO_MMAP |
5877                  SNDRV_PCM_INFO_MMAP_VALID |
5878                  SNDRV_PCM_INFO_NONINTERLEAVED |
5879                  SNDRV_PCM_INFO_SYNC_START),
5880         .formats = SNDRV_PCM_FMTBIT_S32_LE,
5881         .rates = (SNDRV_PCM_RATE_32000 |
5882                   SNDRV_PCM_RATE_44100 |
5883                   SNDRV_PCM_RATE_48000 |
5884                   SNDRV_PCM_RATE_64000 |
5885                   SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5886                   SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000),
5887         .rate_min = 32000,
5888         .rate_max = 192000,
5889         .channels_min = 1,
5890         .channels_max = HDSPM_MAX_CHANNELS,
5891         .buffer_bytes_max =
5892             HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5893         .period_bytes_min = (32 * 4),
5894         .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
5895         .periods_min = 2,
5896         .periods_max = 512,
5897         .fifo_size = 0
5898 };
5899 
5900 static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
5901                                            struct snd_pcm_hw_rule *rule)
5902 {
5903         struct hdspm *hdspm = rule->private;
5904         struct snd_interval *c =
5905             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5906         struct snd_interval *r =
5907             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5908 
5909         if (r->min > 96000 && r->max <= 192000) {
5910                 struct snd_interval t = {
5911                         .min = hdspm->qs_in_channels,
5912                         .max = hdspm->qs_in_channels,
5913                         .integer = 1,
5914                 };
5915                 return snd_interval_refine(c, &t);
5916         } else if (r->min > 48000 && r->max <= 96000) {
5917                 struct snd_interval t = {
5918                         .min = hdspm->ds_in_channels,
5919                         .max = hdspm->ds_in_channels,
5920                         .integer = 1,