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TOMOYO Linux Cross Reference
Linux/sound/pci/rme9652/hdspm.c

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  1 // SPDX-License-Identifier: GPL-2.0-or-later
  2 /*
  3  *   ALSA driver for RME Hammerfall DSP MADI audio interface(s)
  4  *
  5  *      Copyright (c) 2003 Winfried Ritsch (IEM)
  6  *      code based on hdsp.c   Paul Davis
  7  *                             Marcus Andersson
  8  *                             Thomas Charbonnel
  9  *      Modified 2006-06-01 for AES32 support by Remy Bruno
 10  *                                               <remy.bruno@trinnov.com>
 11  *
 12  *      Modified 2009-04-13 for proper metering by Florian Faber
 13  *                                               <faber@faberman.de>
 14  *
 15  *      Modified 2009-04-14 for native float support by Florian Faber
 16  *                                               <faber@faberman.de>
 17  *
 18  *      Modified 2009-04-26 fixed bug in rms metering by Florian Faber
 19  *                                               <faber@faberman.de>
 20  *
 21  *      Modified 2009-04-30 added hw serial number support by Florian Faber
 22  *
 23  *      Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth
 24  *
 25  *      Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth
 26  *
 27  *      Modified 2019-05-23 fix AIO single speed ADAT capture and playback
 28  *      by Philippe.Bekaert@uhasselt.be
 29  */
 30 
 31 /* *************    Register Documentation   *******************************************************
 32  *
 33  * Work in progress! Documentation is based on the code in this file.
 34  *
 35  * --------- HDSPM_controlRegister ---------
 36  * :7654.3210:7654.3210:7654.3210:7654.3210: bit number per byte
 37  * :||||.||||:||||.||||:||||.||||:||||.||||:
 38  * :3322.2222:2222.1111:1111.1100:0000.0000: bit number
 39  * :1098.7654:3210.9876:5432.1098:7654.3210: 0..31
 40  * :||||.||||:||||.||||:||||.||||:||||.||||:
 41  * :8421.8421:8421.8421:8421.8421:8421.8421: hex digit
 42  * :    .    :    .    :    .    :  x .    :  HDSPM_AudioInterruptEnable \_ setting both bits
 43  * :    .    :    .    :    .    :    .   x:  HDSPM_Start                /  enables audio IO
 44  * :    .    :    .    :    .    :   x.    :  HDSPM_ClockModeMaster - 1: Master, 0: Slave
 45  * :    .    :    .    :    .    :    .210 :  HDSPM_LatencyMask - 3 Bit value for latency
 46  * :    .    :    .    :    .    :    .    :      0:64, 1:128, 2:256, 3:512,
 47  * :    .    :    .    :    .    :    .    :      4:1024, 5:2048, 6:4096, 7:8192
 48  * :x   .    :    .    :    .   x:xx  .    :  HDSPM_FrequencyMask
 49  * :    .    :    .    :    .    :10  .    :  HDSPM_Frequency1|HDSPM_Frequency0: 1=32K,2=44.1K,3=48K,0=??
 50  * :    .    :    .    :    .   x:    .    :  <MADI> HDSPM_DoubleSpeed
 51  * :x   .    :    .    :    .    :    .    :  <MADI> HDSPM_QuadSpeed
 52  * :    .  3 :    .  10:  2 .    :    .    :  HDSPM_SyncRefMask :
 53  * :    .    :    .   x:    .    :    .    :  HDSPM_SyncRef0
 54  * :    .    :    .  x :    .    :    .    :  HDSPM_SyncRef1
 55  * :    .    :    .    :  x .    :    .    :  <AES32> HDSPM_SyncRef2
 56  * :    .  x :    .    :    .    :    .    :  <AES32> HDSPM_SyncRef3
 57  * :    .    :    .  10:    .    :    .    :  <MADI> sync ref: 0:WC, 1:Madi, 2:TCO, 3:SyncIn
 58  * :    .  3 :    .  10:  2 .    :    .    :  <AES32>  0:WC, 1:AES1 ... 8:AES8, 9: TCO, 10:SyncIn?
 59  * :    .  x :    .    :    .    :    .    :  <MADIe> HDSPe_FLOAT_FORMAT
 60  * :    .    :    .    : x  .    :    .    :  <MADI> HDSPM_InputSelect0 : 0=optical,1=coax
 61  * :    .    :    .    :x   .    :    .    :  <MADI> HDSPM_InputSelect1
 62  * :    .    :    .x   :    .    :    .    :  <MADI> HDSPM_clr_tms
 63  * :    .    :    .    :    . x  :    .    :  <MADI> HDSPM_TX_64ch
 64  * :    .    :    .    :    . x  :    .    :  <AES32> HDSPM_Emphasis
 65  * :    .    :    .    :    .x   :    .    :  <MADI> HDSPM_AutoInp
 66  * :    .    :    . x  :    .    :    .    :  <MADI> HDSPM_SMUX
 67  * :    .    :    .x   :    .    :    .    :  <MADI> HDSPM_clr_tms
 68  * :    .    :   x.    :    .    :    .    :  <MADI> HDSPM_taxi_reset
 69  * :    .   x:    .    :    .    :    .    :  <MADI> HDSPM_LineOut
 70  * :    .   x:    .    :    .    :    .    :  <AES32> ??????????????????
 71  * :    .    :   x.    :    .    :    .    :  <AES32> HDSPM_WCK48
 72  * :    .    :    .    :    .x   :    .    :  <AES32> HDSPM_Dolby
 73  * :    .    : x  .    :    .    :    .    :  HDSPM_Midi0InterruptEnable
 74  * :    .    :x   .    :    .    :    .    :  HDSPM_Midi1InterruptEnable
 75  * :    .    :  x .    :    .    :    .    :  HDSPM_Midi2InterruptEnable
 76  * :    . x  :    .    :    .    :    .    :  <MADI> HDSPM_Midi3InterruptEnable
 77  * :    . x  :    .    :    .    :    .    :  <AES32> HDSPM_DS_DoubleWire
 78  * :    .x   :    .    :    .    :    .    :  <AES32> HDSPM_QS_DoubleWire
 79  * :   x.    :    .    :    .    :    .    :  <AES32> HDSPM_QS_QuadWire
 80  * :    .    :    .    :    .  x :    .    :  <AES32> HDSPM_Professional
 81  * : x  .    :    .    :    .    :    .    :  HDSPM_wclk_sel
 82  * :    .    :    .    :    .    :    .    :
 83  * :7654.3210:7654.3210:7654.3210:7654.3210: bit number per byte
 84  * :||||.||||:||||.||||:||||.||||:||||.||||:
 85  * :3322.2222:2222.1111:1111.1100:0000.0000: bit number
 86  * :1098.7654:3210.9876:5432.1098:7654.3210: 0..31
 87  * :||||.||||:||||.||||:||||.||||:||||.||||:
 88  * :8421.8421:8421.8421:8421.8421:8421.8421:hex digit
 89  *
 90  *
 91  *
 92  * AIO / RayDAT only
 93  *
 94  * ------------ HDSPM_WR_SETTINGS ----------
 95  * :3322.2222:2222.1111:1111.1100:0000.0000: bit number per byte
 96  * :1098.7654:3210.9876:5432.1098:7654.3210:
 97  * :||||.||||:||||.||||:||||.||||:||||.||||: bit number
 98  * :7654.3210:7654.3210:7654.3210:7654.3210: 0..31
 99  * :||||.||||:||||.||||:||||.||||:||||.||||:
100  * :8421.8421:8421.8421:8421.8421:8421.8421: hex digit
101  * :    .    :    .    :    .    :    .   x: HDSPM_c0Master 1: Master, 0: Slave
102  * :    .    :    .    :    .    :    .  x : HDSPM_c0_SyncRef0
103  * :    .    :    .    :    .    :    . x  : HDSPM_c0_SyncRef1
104  * :    .    :    .    :    .    :    .x   : HDSPM_c0_SyncRef2
105  * :    .    :    .    :    .    :   x.    : HDSPM_c0_SyncRef3
106  * :    .    :    .    :    .    :   3.210 : HDSPM_c0_SyncRefMask:
107  * :    .    :    .    :    .    :    .    :  RayDat: 0:WC, 1:AES, 2:SPDIF, 3..6: ADAT1..4,
108  * :    .    :    .    :    .    :    .    :          9:TCO, 10:SyncIn
109  * :    .    :    .    :    .    :    .    :  AIO: 0:WC, 1:AES, 2: SPDIF, 3: ATAT,
110  * :    .    :    .    :    .    :    .    :          9:TCO, 10:SyncIn
111  * :    .    :    .    :    .    :    .    :
112  * :    .    :    .    :    .    :    .    :
113  * :3322.2222:2222.1111:1111.1100:0000.0000: bit number per byte
114  * :1098.7654:3210.9876:5432.1098:7654.3210:
115  * :||||.||||:||||.||||:||||.||||:||||.||||: bit number
116  * :7654.3210:7654.3210:7654.3210:7654.3210: 0..31
117  * :||||.||||:||||.||||:||||.||||:||||.||||:
118  * :8421.8421:8421.8421:8421.8421:8421.8421: hex digit
119  *
120  */
121 #include <linux/init.h>
122 #include <linux/delay.h>
123 #include <linux/interrupt.h>
124 #include <linux/module.h>
125 #include <linux/slab.h>
126 #include <linux/pci.h>
127 #include <linux/math64.h>
128 #include <linux/io.h>
129 #include <linux/nospec.h>
130 
131 #include <sound/core.h>
132 #include <sound/control.h>
133 #include <sound/pcm.h>
134 #include <sound/pcm_params.h>
135 #include <sound/info.h>
136 #include <sound/asoundef.h>
137 #include <sound/rawmidi.h>
138 #include <sound/hwdep.h>
139 #include <sound/initval.h>
140 
141 #include <sound/hdspm.h>
142 
143 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;        /* Index 0-MAX */
144 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;         /* ID for this card */
145 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
146 
147 module_param_array(index, int, NULL, 0444);
148 MODULE_PARM_DESC(index, "Index value for RME HDSPM interface.");
149 
150 module_param_array(id, charp, NULL, 0444);
151 MODULE_PARM_DESC(id, "ID string for RME HDSPM interface.");
152 
153 module_param_array(enable, bool, NULL, 0444);
154 MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards.");
155 
156 
157 MODULE_AUTHOR
158 (
159         "Winfried Ritsch <ritsch_AT_iem.at>, "
160         "Paul Davis <paul@linuxaudiosystems.com>, "
161         "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, "
162         "Remy Bruno <remy.bruno@trinnov.com>, "
163         "Florian Faber <faberman@linuxproaudio.org>, "
164         "Adrian Knoth <adi@drcomp.erfurt.thur.de>"
165 );
166 MODULE_DESCRIPTION("RME HDSPM");
167 MODULE_LICENSE("GPL");
168 MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}");
169 
170 /* --- Write registers. ---
171   These are defined as byte-offsets from the iobase value.  */
172 
173 #define HDSPM_WR_SETTINGS             0
174 #define HDSPM_outputBufferAddress    32
175 #define HDSPM_inputBufferAddress     36
176 #define HDSPM_controlRegister        64
177 #define HDSPM_interruptConfirmation  96
178 #define HDSPM_control2Reg            256  /* not in specs ???????? */
179 #define HDSPM_freqReg                256  /* for setting arbitrary clock values (DDS feature) */
180 #define HDSPM_midiDataOut0           352  /* just believe in old code */
181 #define HDSPM_midiDataOut1           356
182 #define HDSPM_eeprom_wr              384  /* for AES32 */
183 
184 /* DMA enable for 64 channels, only Bit 0 is relevant */
185 #define HDSPM_outputEnableBase       512  /* 512-767  input  DMA */
186 #define HDSPM_inputEnableBase        768  /* 768-1023 output DMA */
187 
188 /* 16 page addresses for each of the 64 channels DMA buffer in and out
189    (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */
190 #define HDSPM_pageAddressBufferOut       8192
191 #define HDSPM_pageAddressBufferIn        (HDSPM_pageAddressBufferOut+64*16*4)
192 
193 #define HDSPM_MADI_mixerBase    32768   /* 32768-65535 for 2x64x64 Fader */
194 
195 #define HDSPM_MATRIX_MIXER_SIZE  8192   /* = 2*64*64 * 4 Byte => 32kB */
196 
197 /* --- Read registers. ---
198    These are defined as byte-offsets from the iobase value */
199 #define HDSPM_statusRegister    0
200 /*#define HDSPM_statusRegister2  96 */
201 /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at
202  * offset 192, for AES32 *and* MADI
203  * => need to check that offset 192 is working on MADI */
204 #define HDSPM_statusRegister2  192
205 #define HDSPM_timecodeRegister 128
206 
207 /* AIO, RayDAT */
208 #define HDSPM_RD_STATUS_0 0
209 #define HDSPM_RD_STATUS_1 64
210 #define HDSPM_RD_STATUS_2 128
211 #define HDSPM_RD_STATUS_3 192
212 
213 #define HDSPM_RD_TCO           256
214 #define HDSPM_RD_PLL_FREQ      512
215 #define HDSPM_WR_TCO           128
216 
217 #define HDSPM_TCO1_TCO_lock                     0x00000001
218 #define HDSPM_TCO1_WCK_Input_Range_LSB          0x00000002
219 #define HDSPM_TCO1_WCK_Input_Range_MSB          0x00000004
220 #define HDSPM_TCO1_LTC_Input_valid              0x00000008
221 #define HDSPM_TCO1_WCK_Input_valid              0x00000010
222 #define HDSPM_TCO1_Video_Input_Format_NTSC      0x00000020
223 #define HDSPM_TCO1_Video_Input_Format_PAL       0x00000040
224 
225 #define HDSPM_TCO1_set_TC                       0x00000100
226 #define HDSPM_TCO1_set_drop_frame_flag          0x00000200
227 #define HDSPM_TCO1_LTC_Format_LSB               0x00000400
228 #define HDSPM_TCO1_LTC_Format_MSB               0x00000800
229 
230 #define HDSPM_TCO2_TC_run                       0x00010000
231 #define HDSPM_TCO2_WCK_IO_ratio_LSB             0x00020000
232 #define HDSPM_TCO2_WCK_IO_ratio_MSB             0x00040000
233 #define HDSPM_TCO2_set_num_drop_frames_LSB      0x00080000
234 #define HDSPM_TCO2_set_num_drop_frames_MSB      0x00100000
235 #define HDSPM_TCO2_set_jam_sync                 0x00200000
236 #define HDSPM_TCO2_set_flywheel                 0x00400000
237 
238 #define HDSPM_TCO2_set_01_4                     0x01000000
239 #define HDSPM_TCO2_set_pull_down                0x02000000
240 #define HDSPM_TCO2_set_pull_up                  0x04000000
241 #define HDSPM_TCO2_set_freq                     0x08000000
242 #define HDSPM_TCO2_set_term_75R                 0x10000000
243 #define HDSPM_TCO2_set_input_LSB                0x20000000
244 #define HDSPM_TCO2_set_input_MSB                0x40000000
245 #define HDSPM_TCO2_set_freq_from_app            0x80000000
246 
247 
248 #define HDSPM_midiDataOut0    352
249 #define HDSPM_midiDataOut1    356
250 #define HDSPM_midiDataOut2    368
251 
252 #define HDSPM_midiDataIn0     360
253 #define HDSPM_midiDataIn1     364
254 #define HDSPM_midiDataIn2     372
255 #define HDSPM_midiDataIn3     376
256 
257 /* status is data bytes in MIDI-FIFO (0-128) */
258 #define HDSPM_midiStatusOut0  384
259 #define HDSPM_midiStatusOut1  388
260 #define HDSPM_midiStatusOut2  400
261 
262 #define HDSPM_midiStatusIn0   392
263 #define HDSPM_midiStatusIn1   396
264 #define HDSPM_midiStatusIn2   404
265 #define HDSPM_midiStatusIn3   408
266 
267 
268 /* the meters are regular i/o-mapped registers, but offset
269    considerably from the rest. the peak registers are reset
270    when read; the least-significant 4 bits are full-scale counters;
271    the actual peak value is in the most-significant 24 bits.
272 */
273 
274 #define HDSPM_MADI_INPUT_PEAK           4096
275 #define HDSPM_MADI_PLAYBACK_PEAK        4352
276 #define HDSPM_MADI_OUTPUT_PEAK          4608
277 
278 #define HDSPM_MADI_INPUT_RMS_L          6144
279 #define HDSPM_MADI_PLAYBACK_RMS_L       6400
280 #define HDSPM_MADI_OUTPUT_RMS_L         6656
281 
282 #define HDSPM_MADI_INPUT_RMS_H          7168
283 #define HDSPM_MADI_PLAYBACK_RMS_H       7424
284 #define HDSPM_MADI_OUTPUT_RMS_H         7680
285 
286 /* --- Control Register bits --------- */
287 #define HDSPM_Start                (1<<0) /* start engine */
288 
289 #define HDSPM_Latency0             (1<<1) /* buffer size = 2^n */
290 #define HDSPM_Latency1             (1<<2) /* where n is defined */
291 #define HDSPM_Latency2             (1<<3) /* by Latency{2,1,0} */
292 
293 #define HDSPM_ClockModeMaster      (1<<4) /* 1=Master, 0=Autosync */
294 #define HDSPM_c0Master          0x1    /* Master clock bit in settings
295                                           register [RayDAT, AIO] */
296 
297 #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */
298 
299 #define HDSPM_Frequency0  (1<<6)  /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */
300 #define HDSPM_Frequency1  (1<<7)  /* 0=32kHz/64kHz */
301 #define HDSPM_DoubleSpeed (1<<8)  /* 0=normal speed, 1=double speed */
302 #define HDSPM_QuadSpeed   (1<<31) /* quad speed bit */
303 
304 #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */
305 #define HDSPM_TX_64ch     (1<<10) /* Output 64channel MODE=1,
306                                      56channelMODE=0 */ /* MADI ONLY*/
307 #define HDSPM_Emphasis    (1<<10) /* Emphasis */ /* AES32 ONLY */
308 
309 #define HDSPM_AutoInp     (1<<11) /* Auto Input (takeover) == Safe Mode,
310                                      0=off, 1=on  */ /* MADI ONLY */
311 #define HDSPM_Dolby       (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */
312 
313 #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax
314                                     * -- MADI ONLY
315                                     */
316 #define HDSPM_InputSelect1 (1<<15) /* should be 0 */
317 
318 #define HDSPM_SyncRef2     (1<<13)
319 #define HDSPM_SyncRef3     (1<<25)
320 
321 #define HDSPM_SMUX         (1<<18) /* Frame ??? */ /* MADI ONY */
322 #define HDSPM_clr_tms      (1<<19) /* clear track marker, do not use
323                                       AES additional bits in
324                                       lower 5 Audiodatabits ??? */
325 #define HDSPM_taxi_reset   (1<<20) /* ??? */ /* MADI ONLY ? */
326 #define HDSPM_WCK48        (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */
327 
328 #define HDSPM_Midi0InterruptEnable 0x0400000
329 #define HDSPM_Midi1InterruptEnable 0x0800000
330 #define HDSPM_Midi2InterruptEnable 0x0200000
331 #define HDSPM_Midi3InterruptEnable 0x4000000
332 
333 #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */
334 #define HDSPe_FLOAT_FORMAT         0x2000000
335 
336 #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */
337 #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */
338 #define HDSPM_QS_QuadWire   (1<<28) /* AES32 ONLY */
339 
340 #define HDSPM_wclk_sel (1<<30)
341 
342 /* additional control register bits for AIO*/
343 #define HDSPM_c0_Wck48                          0x20 /* also RayDAT */
344 #define HDSPM_c0_Input0                         0x1000
345 #define HDSPM_c0_Input1                         0x2000
346 #define HDSPM_c0_Spdif_Opt                      0x4000
347 #define HDSPM_c0_Pro                            0x8000
348 #define HDSPM_c0_clr_tms                        0x10000
349 #define HDSPM_c0_AEB1                           0x20000
350 #define HDSPM_c0_AEB2                           0x40000
351 #define HDSPM_c0_LineOut                        0x80000
352 #define HDSPM_c0_AD_GAIN0                       0x100000
353 #define HDSPM_c0_AD_GAIN1                       0x200000
354 #define HDSPM_c0_DA_GAIN0                       0x400000
355 #define HDSPM_c0_DA_GAIN1                       0x800000
356 #define HDSPM_c0_PH_GAIN0                       0x1000000
357 #define HDSPM_c0_PH_GAIN1                       0x2000000
358 #define HDSPM_c0_Sym6db                         0x4000000
359 
360 
361 /* --- bit helper defines */
362 #define HDSPM_LatencyMask    (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2)
363 #define HDSPM_FrequencyMask  (HDSPM_Frequency0|HDSPM_Frequency1|\
364                               HDSPM_DoubleSpeed|HDSPM_QuadSpeed)
365 #define HDSPM_InputMask      (HDSPM_InputSelect0|HDSPM_InputSelect1)
366 #define HDSPM_InputOptical   0
367 #define HDSPM_InputCoaxial   (HDSPM_InputSelect0)
368 #define HDSPM_SyncRefMask    (HDSPM_SyncRef0|HDSPM_SyncRef1|\
369                               HDSPM_SyncRef2|HDSPM_SyncRef3)
370 
371 #define HDSPM_c0_SyncRef0      0x2
372 #define HDSPM_c0_SyncRef1      0x4
373 #define HDSPM_c0_SyncRef2      0x8
374 #define HDSPM_c0_SyncRef3      0x10
375 #define HDSPM_c0_SyncRefMask   (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\
376                                 HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3)
377 
378 #define HDSPM_SYNC_FROM_WORD    0       /* Preferred sync reference */
379 #define HDSPM_SYNC_FROM_MADI    1       /* choices - used by "pref_sync_ref" */
380 #define HDSPM_SYNC_FROM_TCO     2
381 #define HDSPM_SYNC_FROM_SYNC_IN 3
382 
383 #define HDSPM_Frequency32KHz    HDSPM_Frequency0
384 #define HDSPM_Frequency44_1KHz  HDSPM_Frequency1
385 #define HDSPM_Frequency48KHz   (HDSPM_Frequency1|HDSPM_Frequency0)
386 #define HDSPM_Frequency64KHz   (HDSPM_DoubleSpeed|HDSPM_Frequency0)
387 #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1)
388 #define HDSPM_Frequency96KHz   (HDSPM_DoubleSpeed|HDSPM_Frequency1|\
389                                 HDSPM_Frequency0)
390 #define HDSPM_Frequency128KHz   (HDSPM_QuadSpeed|HDSPM_Frequency0)
391 #define HDSPM_Frequency176_4KHz   (HDSPM_QuadSpeed|HDSPM_Frequency1)
392 #define HDSPM_Frequency192KHz   (HDSPM_QuadSpeed|HDSPM_Frequency1|\
393                                  HDSPM_Frequency0)
394 
395 
396 /* Synccheck Status */
397 #define HDSPM_SYNC_CHECK_NO_LOCK 0
398 #define HDSPM_SYNC_CHECK_LOCK    1
399 #define HDSPM_SYNC_CHECK_SYNC    2
400 
401 /* AutoSync References - used by "autosync_ref" control switch */
402 #define HDSPM_AUTOSYNC_FROM_WORD      0
403 #define HDSPM_AUTOSYNC_FROM_MADI      1
404 #define HDSPM_AUTOSYNC_FROM_TCO       2
405 #define HDSPM_AUTOSYNC_FROM_SYNC_IN   3
406 #define HDSPM_AUTOSYNC_FROM_NONE      4
407 
408 /* Possible sources of MADI input */
409 #define HDSPM_OPTICAL 0         /* optical   */
410 #define HDSPM_COAXIAL 1         /* BNC */
411 
412 #define hdspm_encode_latency(x)       (((x)<<1) & HDSPM_LatencyMask)
413 #define hdspm_decode_latency(x)       ((((x) & HDSPM_LatencyMask)>>1))
414 
415 #define hdspm_encode_in(x) (((x)&0x3)<<14)
416 #define hdspm_decode_in(x) (((x)>>14)&0x3)
417 
418 /* --- control2 register bits --- */
419 #define HDSPM_TMS             (1<<0)
420 #define HDSPM_TCK             (1<<1)
421 #define HDSPM_TDI             (1<<2)
422 #define HDSPM_JTAG            (1<<3)
423 #define HDSPM_PWDN            (1<<4)
424 #define HDSPM_PROGRAM         (1<<5)
425 #define HDSPM_CONFIG_MODE_0   (1<<6)
426 #define HDSPM_CONFIG_MODE_1   (1<<7)
427 /*#define HDSPM_VERSION_BIT     (1<<8) not defined any more*/
428 #define HDSPM_BIGENDIAN_MODE  (1<<9)
429 #define HDSPM_RD_MULTIPLE     (1<<10)
430 
431 /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and
432      that do not conflict with specific bits for AES32 seem to be valid also
433      for the AES32
434  */
435 #define HDSPM_audioIRQPending    (1<<0) /* IRQ is high and pending */
436 #define HDSPM_RX_64ch            (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */
437 #define HDSPM_AB_int             (1<<2) /* InputChannel Opt=0, Coax=1
438                                          * (like inp0)
439                                          */
440 
441 #define HDSPM_madiLock           (1<<3) /* MADI Locked =1, no=0 */
442 #define HDSPM_madiSync          (1<<18) /* MADI is in sync */
443 
444 #define HDSPM_tcoLockMadi    0x00000020 /* Optional TCO locked status for HDSPe MADI*/
445 #define HDSPM_tcoSync    0x10000000 /* Optional TCO sync status for HDSPe MADI and AES32!*/
446 
447 #define HDSPM_syncInLock 0x00010000 /* Sync In lock status for HDSPe MADI! */
448 #define HDSPM_syncInSync 0x00020000 /* Sync In sync status for HDSPe MADI! */
449 
450 #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
451                         /* since 64byte accurate, last 6 bits are not used */
452 
453 
454 
455 #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */
456 
457 #define HDSPM_madiFreq0         (1<<22) /* system freq 0=error */
458 #define HDSPM_madiFreq1         (1<<23) /* 1=32, 2=44.1 3=48 */
459 #define HDSPM_madiFreq2         (1<<24) /* 4=64, 5=88.2 6=96 */
460 #define HDSPM_madiFreq3         (1<<25) /* 7=128, 8=176.4 9=192 */
461 
462 #define HDSPM_BufferID          (1<<26) /* (Double)Buffer ID toggles with
463                                          * Interrupt
464                                          */
465 #define HDSPM_tco_detect         0x08000000
466 #define HDSPM_tcoLockAes         0x20000000 /* Optional TCO locked status for HDSPe AES */
467 
468 #define HDSPM_s2_tco_detect      0x00000040
469 #define HDSPM_s2_AEBO_D          0x00000080
470 #define HDSPM_s2_AEBI_D          0x00000100
471 
472 
473 #define HDSPM_midi0IRQPending    0x40000000
474 #define HDSPM_midi1IRQPending    0x80000000
475 #define HDSPM_midi2IRQPending    0x20000000
476 #define HDSPM_midi2IRQPendingAES 0x00000020
477 #define HDSPM_midi3IRQPending    0x00200000
478 
479 /* --- status bit helpers */
480 #define HDSPM_madiFreqMask  (HDSPM_madiFreq0|HDSPM_madiFreq1|\
481                              HDSPM_madiFreq2|HDSPM_madiFreq3)
482 #define HDSPM_madiFreq32    (HDSPM_madiFreq0)
483 #define HDSPM_madiFreq44_1  (HDSPM_madiFreq1)
484 #define HDSPM_madiFreq48    (HDSPM_madiFreq0|HDSPM_madiFreq1)
485 #define HDSPM_madiFreq64    (HDSPM_madiFreq2)
486 #define HDSPM_madiFreq88_2  (HDSPM_madiFreq0|HDSPM_madiFreq2)
487 #define HDSPM_madiFreq96    (HDSPM_madiFreq1|HDSPM_madiFreq2)
488 #define HDSPM_madiFreq128   (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2)
489 #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3)
490 #define HDSPM_madiFreq192   (HDSPM_madiFreq3|HDSPM_madiFreq0)
491 
492 /* Status2 Register bits */ /* MADI ONLY */
493 
494 #define HDSPM_version0 (1<<0)   /* not really defined but I guess */
495 #define HDSPM_version1 (1<<1)   /* in former cards it was ??? */
496 #define HDSPM_version2 (1<<2)
497 
498 #define HDSPM_wcLock (1<<3)     /* Wordclock is detected and locked */
499 #define HDSPM_wcSync (1<<4)     /* Wordclock is in sync with systemclock */
500 
501 #define HDSPM_wc_freq0 (1<<5)   /* input freq detected via autosync  */
502 #define HDSPM_wc_freq1 (1<<6)   /* 001=32, 010==44.1, 011=48, */
503 #define HDSPM_wc_freq2 (1<<7)   /* 100=64, 101=88.2, 110=96, 111=128 */
504 #define HDSPM_wc_freq3 0x800    /* 1000=176.4, 1001=192 */
505 
506 #define HDSPM_SyncRef0 0x10000  /* Sync Reference */
507 #define HDSPM_SyncRef1 0x20000
508 
509 #define HDSPM_SelSyncRef0 (1<<8)        /* AutoSync Source */
510 #define HDSPM_SelSyncRef1 (1<<9)        /* 000=word, 001=MADI, */
511 #define HDSPM_SelSyncRef2 (1<<10)       /* 111=no valid signal */
512 
513 #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync)
514 
515 #define HDSPM_wcFreqMask  (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2|\
516                             HDSPM_wc_freq3)
517 #define HDSPM_wcFreq32    (HDSPM_wc_freq0)
518 #define HDSPM_wcFreq44_1  (HDSPM_wc_freq1)
519 #define HDSPM_wcFreq48    (HDSPM_wc_freq0|HDSPM_wc_freq1)
520 #define HDSPM_wcFreq64    (HDSPM_wc_freq2)
521 #define HDSPM_wcFreq88_2  (HDSPM_wc_freq0|HDSPM_wc_freq2)
522 #define HDSPM_wcFreq96    (HDSPM_wc_freq1|HDSPM_wc_freq2)
523 #define HDSPM_wcFreq128   (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2)
524 #define HDSPM_wcFreq176_4 (HDSPM_wc_freq3)
525 #define HDSPM_wcFreq192   (HDSPM_wc_freq0|HDSPM_wc_freq3)
526 
527 #define HDSPM_status1_F_0 0x0400000
528 #define HDSPM_status1_F_1 0x0800000
529 #define HDSPM_status1_F_2 0x1000000
530 #define HDSPM_status1_F_3 0x2000000
531 #define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3)
532 
533 
534 #define HDSPM_SelSyncRefMask       (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
535                                     HDSPM_SelSyncRef2)
536 #define HDSPM_SelSyncRef_WORD      0
537 #define HDSPM_SelSyncRef_MADI      (HDSPM_SelSyncRef0)
538 #define HDSPM_SelSyncRef_TCO       (HDSPM_SelSyncRef1)
539 #define HDSPM_SelSyncRef_SyncIn    (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1)
540 #define HDSPM_SelSyncRef_NVALID    (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
541                                     HDSPM_SelSyncRef2)
542 
543 /*
544    For AES32, bits for status, status2 and timecode are different
545 */
546 /* status */
547 #define HDSPM_AES32_wcLock      0x0200000
548 #define HDSPM_AES32_wcSync      0x0100000
549 #define HDSPM_AES32_wcFreq_bit  22
550 /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function
551   HDSPM_bit2freq */
552 #define HDSPM_AES32_syncref_bit  16
553 /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */
554 
555 #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0
556 #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1
557 #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2
558 #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3
559 #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4
560 #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5
561 #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6
562 #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7
563 #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8
564 #define HDSPM_AES32_AUTOSYNC_FROM_TCO 9
565 #define HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN 10
566 #define HDSPM_AES32_AUTOSYNC_FROM_NONE 11
567 
568 /*  status2 */
569 /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */
570 #define HDSPM_LockAES   0x80
571 #define HDSPM_LockAES1  0x80
572 #define HDSPM_LockAES2  0x40
573 #define HDSPM_LockAES3  0x20
574 #define HDSPM_LockAES4  0x10
575 #define HDSPM_LockAES5  0x8
576 #define HDSPM_LockAES6  0x4
577 #define HDSPM_LockAES7  0x2
578 #define HDSPM_LockAES8  0x1
579 /*
580    Timecode
581    After windows driver sources, bits 4*i to 4*i+3 give the input frequency on
582    AES i+1
583  bits 3210
584       0001  32kHz
585       0010  44.1kHz
586       0011  48kHz
587       0100  64kHz
588       0101  88.2kHz
589       0110  96kHz
590       0111  128kHz
591       1000  176.4kHz
592       1001  192kHz
593   NB: Timecode register doesn't seem to work on AES32 card revision 230
594 */
595 
596 /* Mixer Values */
597 #define UNITY_GAIN          32768       /* = 65536/2 */
598 #define MINUS_INFINITY_GAIN 0
599 
600 /* Number of channels for different Speed Modes */
601 #define MADI_SS_CHANNELS       64
602 #define MADI_DS_CHANNELS       32
603 #define MADI_QS_CHANNELS       16
604 
605 #define RAYDAT_SS_CHANNELS     36
606 #define RAYDAT_DS_CHANNELS     20
607 #define RAYDAT_QS_CHANNELS     12
608 
609 #define AIO_IN_SS_CHANNELS        14
610 #define AIO_IN_DS_CHANNELS        10
611 #define AIO_IN_QS_CHANNELS        8
612 #define AIO_OUT_SS_CHANNELS        16
613 #define AIO_OUT_DS_CHANNELS        12
614 #define AIO_OUT_QS_CHANNELS        10
615 
616 #define AES32_CHANNELS          16
617 
618 /* the size of a substream (1 mono data stream) */
619 #define HDSPM_CHANNEL_BUFFER_SAMPLES  (16*1024)
620 #define HDSPM_CHANNEL_BUFFER_BYTES    (4*HDSPM_CHANNEL_BUFFER_SAMPLES)
621 
622 /* the size of the area we need to allocate for DMA transfers. the
623    size is the same regardless of the number of channels, and
624    also the latency to use.
625    for one direction !!!
626 */
627 #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES)
628 #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024)
629 
630 #define HDSPM_RAYDAT_REV        211
631 #define HDSPM_AIO_REV           212
632 #define HDSPM_MADIFACE_REV      213
633 
634 /* speed factor modes */
635 #define HDSPM_SPEED_SINGLE 0
636 #define HDSPM_SPEED_DOUBLE 1
637 #define HDSPM_SPEED_QUAD   2
638 
639 /* names for speed modes */
640 static const char * const hdspm_speed_names[] = { "single", "double", "quad" };
641 
642 static const char *const texts_autosync_aes_tco[] = { "Word Clock",
643                                           "AES1", "AES2", "AES3", "AES4",
644                                           "AES5", "AES6", "AES7", "AES8",
645                                           "TCO", "Sync In"
646 };
647 static const char *const texts_autosync_aes[] = { "Word Clock",
648                                       "AES1", "AES2", "AES3", "AES4",
649                                       "AES5", "AES6", "AES7", "AES8",
650                                       "Sync In"
651 };
652 static const char *const texts_autosync_madi_tco[] = { "Word Clock",
653                                            "MADI", "TCO", "Sync In" };
654 static const char *const texts_autosync_madi[] = { "Word Clock",
655                                        "MADI", "Sync In" };
656 
657 static const char *const texts_autosync_raydat_tco[] = {
658         "Word Clock",
659         "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
660         "AES", "SPDIF", "TCO", "Sync In"
661 };
662 static const char *const texts_autosync_raydat[] = {
663         "Word Clock",
664         "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
665         "AES", "SPDIF", "Sync In"
666 };
667 static const char *const texts_autosync_aio_tco[] = {
668         "Word Clock",
669         "ADAT", "AES", "SPDIF", "TCO", "Sync In"
670 };
671 static const char *const texts_autosync_aio[] = { "Word Clock",
672                                       "ADAT", "AES", "SPDIF", "Sync In" };
673 
674 static const char *const texts_freq[] = {
675         "No Lock",
676         "32 kHz",
677         "44.1 kHz",
678         "48 kHz",
679         "64 kHz",
680         "88.2 kHz",
681         "96 kHz",
682         "128 kHz",
683         "176.4 kHz",
684         "192 kHz"
685 };
686 
687 static const char * const texts_ports_madi[] = {
688         "MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6",
689         "MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12",
690         "MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18",
691         "MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24",
692         "MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30",
693         "MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36",
694         "MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42",
695         "MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48",
696         "MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54",
697         "MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60",
698         "MADI.61", "MADI.62", "MADI.63", "MADI.64",
699 };
700 
701 
702 static const char * const texts_ports_raydat_ss[] = {
703         "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6",
704         "ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
705         "ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2",
706         "ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8",
707         "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6",
708         "ADAT4.7", "ADAT4.8",
709         "AES.L", "AES.R",
710         "SPDIF.L", "SPDIF.R"
711 };
712 
713 static const char * const texts_ports_raydat_ds[] = {
714         "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4",
715         "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
716         "ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4",
717         "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4",
718         "AES.L", "AES.R",
719         "SPDIF.L", "SPDIF.R"
720 };
721 
722 static const char * const texts_ports_raydat_qs[] = {
723         "ADAT1.1", "ADAT1.2",
724         "ADAT2.1", "ADAT2.2",
725         "ADAT3.1", "ADAT3.2",
726         "ADAT4.1", "ADAT4.2",
727         "AES.L", "AES.R",
728         "SPDIF.L", "SPDIF.R"
729 };
730 
731 
732 static const char * const texts_ports_aio_in_ss[] = {
733         "Analogue.L", "Analogue.R",
734         "AES.L", "AES.R",
735         "SPDIF.L", "SPDIF.R",
736         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
737         "ADAT.7", "ADAT.8",
738         "AEB.1", "AEB.2", "AEB.3", "AEB.4"
739 };
740 
741 static const char * const texts_ports_aio_out_ss[] = {
742         "Analogue.L", "Analogue.R",
743         "AES.L", "AES.R",
744         "SPDIF.L", "SPDIF.R",
745         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
746         "ADAT.7", "ADAT.8",
747         "Phone.L", "Phone.R",
748         "AEB.1", "AEB.2", "AEB.3", "AEB.4"
749 };
750 
751 static const char * const texts_ports_aio_in_ds[] = {
752         "Analogue.L", "Analogue.R",
753         "AES.L", "AES.R",
754         "SPDIF.L", "SPDIF.R",
755         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
756         "AEB.1", "AEB.2", "AEB.3", "AEB.4"
757 };
758 
759 static const char * const texts_ports_aio_out_ds[] = {
760         "Analogue.L", "Analogue.R",
761         "AES.L", "AES.R",
762         "SPDIF.L", "SPDIF.R",
763         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
764         "Phone.L", "Phone.R",
765         "AEB.1", "AEB.2", "AEB.3", "AEB.4"
766 };
767 
768 static const char * const texts_ports_aio_in_qs[] = {
769         "Analogue.L", "Analogue.R",
770         "AES.L", "AES.R",
771         "SPDIF.L", "SPDIF.R",
772         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
773         "AEB.1", "AEB.2", "AEB.3", "AEB.4"
774 };
775 
776 static const char * const texts_ports_aio_out_qs[] = {
777         "Analogue.L", "Analogue.R",
778         "AES.L", "AES.R",
779         "SPDIF.L", "SPDIF.R",
780         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
781         "Phone.L", "Phone.R",
782         "AEB.1", "AEB.2", "AEB.3", "AEB.4"
783 };
784 
785 static const char * const texts_ports_aes32[] = {
786         "AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7",
787         "AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14",
788         "AES.15", "AES.16"
789 };
790 
791 /* These tables map the ALSA channels 1..N to the channels that we
792    need to use in order to find the relevant channel buffer. RME
793    refers to this kind of mapping as between "the ADAT channel and
794    the DMA channel." We index it using the logical audio channel,
795    and the value is the DMA channel (i.e. channel buffer number)
796    where the data for that channel can be read/written from/to.
797 */
798 
799 static const char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = {
800         0, 1, 2, 3, 4, 5, 6, 7,
801         8, 9, 10, 11, 12, 13, 14, 15,
802         16, 17, 18, 19, 20, 21, 22, 23,
803         24, 25, 26, 27, 28, 29, 30, 31,
804         32, 33, 34, 35, 36, 37, 38, 39,
805         40, 41, 42, 43, 44, 45, 46, 47,
806         48, 49, 50, 51, 52, 53, 54, 55,
807         56, 57, 58, 59, 60, 61, 62, 63
808 };
809 
810 static const char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = {
811         4, 5, 6, 7, 8, 9, 10, 11,       /* ADAT 1 */
812         12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */
813         20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */
814         28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */
815         0, 1,                   /* AES */
816         2, 3,                   /* SPDIF */
817         -1, -1, -1, -1,
818         -1, -1, -1, -1, -1, -1, -1, -1,
819         -1, -1, -1, -1, -1, -1, -1, -1,
820         -1, -1, -1, -1, -1, -1, -1, -1,
821 };
822 
823 static const char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = {
824         4, 5, 6, 7,             /* ADAT 1 */
825         8, 9, 10, 11,           /* ADAT 2 */
826         12, 13, 14, 15,         /* ADAT 3 */
827         16, 17, 18, 19,         /* ADAT 4 */
828         0, 1,                   /* AES */
829         2, 3,                   /* SPDIF */
830         -1, -1, -1, -1,
831         -1, -1, -1, -1, -1, -1, -1, -1,
832         -1, -1, -1, -1, -1, -1, -1, -1,
833         -1, -1, -1, -1, -1, -1, -1, -1,
834         -1, -1, -1, -1, -1, -1, -1, -1,
835         -1, -1, -1, -1, -1, -1, -1, -1,
836 };
837 
838 static const char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = {
839         4, 5,                   /* ADAT 1 */
840         6, 7,                   /* ADAT 2 */
841         8, 9,                   /* ADAT 3 */
842         10, 11,                 /* ADAT 4 */
843         0, 1,                   /* AES */
844         2, 3,                   /* SPDIF */
845         -1, -1, -1, -1,
846         -1, -1, -1, -1, -1, -1, -1, -1,
847         -1, -1, -1, -1, -1, -1, -1, -1,
848         -1, -1, -1, -1, -1, -1, -1, -1,
849         -1, -1, -1, -1, -1, -1, -1, -1,
850         -1, -1, -1, -1, -1, -1, -1, -1,
851         -1, -1, -1, -1, -1, -1, -1, -1,
852 };
853 
854 static const char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = {
855         0, 1,                   /* line in */
856         8, 9,                   /* aes in, */
857         10, 11,                 /* spdif in */
858         12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */
859         2, 3, 4, 5,             /* AEB */
860         -1, -1, -1, -1, -1, -1,
861         -1, -1, -1, -1, -1, -1, -1, -1,
862         -1, -1, -1, -1, -1, -1, -1, -1,
863         -1, -1, -1, -1, -1, -1, -1, -1,
864         -1, -1, -1, -1, -1, -1, -1, -1,
865         -1, -1, -1, -1, -1, -1, -1, -1,
866 };
867 
868 static const char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = {
869         0, 1,                   /* line out */
870         8, 9,                   /* aes out */
871         10, 11,                 /* spdif out */
872         12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */
873         6, 7,                   /* phone out */
874         2, 3, 4, 5,             /* AEB */
875         -1, -1, -1, -1,
876         -1, -1, -1, -1, -1, -1, -1, -1,
877         -1, -1, -1, -1, -1, -1, -1, -1,
878         -1, -1, -1, -1, -1, -1, -1, -1,
879         -1, -1, -1, -1, -1, -1, -1, -1,
880         -1, -1, -1, -1, -1, -1, -1, -1,
881 };
882 
883 static const char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = {
884         0, 1,                   /* line in */
885         8, 9,                   /* aes in */
886         10, 11,                 /* spdif in */
887         12, 14, 16, 18,         /* adat in */
888         2, 3, 4, 5,             /* AEB */
889         -1, -1,
890         -1, -1, -1, -1, -1, -1, -1, -1,
891         -1, -1, -1, -1, -1, -1, -1, -1,
892         -1, -1, -1, -1, -1, -1, -1, -1,
893         -1, -1, -1, -1, -1, -1, -1, -1,
894         -1, -1, -1, -1, -1, -1, -1, -1,
895         -1, -1, -1, -1, -1, -1, -1, -1
896 };
897 
898 static const char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = {
899         0, 1,                   /* line out */
900         8, 9,                   /* aes out */
901         10, 11,                 /* spdif out */
902         12, 14, 16, 18,         /* adat out */
903         6, 7,                   /* phone out */
904         2, 3, 4, 5,             /* AEB */
905         -1, -1, -1, -1, -1, -1, -1, -1,
906         -1, -1, -1, -1, -1, -1, -1, -1,
907         -1, -1, -1, -1, -1, -1, -1, -1,
908         -1, -1, -1, -1, -1, -1, -1, -1,
909         -1, -1, -1, -1, -1, -1, -1, -1,
910         -1, -1, -1, -1, -1, -1, -1, -1
911 };
912 
913 static const char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = {
914         0, 1,                   /* line in */
915         8, 9,                   /* aes in */
916         10, 11,                 /* spdif in */
917         12, 16,                 /* adat in */
918         2, 3, 4, 5,             /* AEB */
919         -1, -1, -1, -1,
920         -1, -1, -1, -1, -1, -1, -1, -1,
921         -1, -1, -1, -1, -1, -1, -1, -1,
922         -1, -1, -1, -1, -1, -1, -1, -1,
923         -1, -1, -1, -1, -1, -1, -1, -1,
924         -1, -1, -1, -1, -1, -1, -1, -1,
925         -1, -1, -1, -1, -1, -1, -1, -1
926 };
927 
928 static const char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = {
929         0, 1,                   /* line out */
930         8, 9,                   /* aes out */
931         10, 11,                 /* spdif out */
932         12, 16,                 /* adat out */
933         6, 7,                   /* phone out */
934         2, 3, 4, 5,             /* AEB */
935         -1, -1,
936         -1, -1, -1, -1, -1, -1, -1, -1,
937         -1, -1, -1, -1, -1, -1, -1, -1,
938         -1, -1, -1, -1, -1, -1, -1, -1,
939         -1, -1, -1, -1, -1, -1, -1, -1,
940         -1, -1, -1, -1, -1, -1, -1, -1,
941         -1, -1, -1, -1, -1, -1, -1, -1
942 };
943 
944 static const char channel_map_aes32[HDSPM_MAX_CHANNELS] = {
945         0, 1, 2, 3, 4, 5, 6, 7,
946         8, 9, 10, 11, 12, 13, 14, 15,
947         -1, -1, -1, -1, -1, -1, -1, -1,
948         -1, -1, -1, -1, -1, -1, -1, -1,
949         -1, -1, -1, -1, -1, -1, -1, -1,
950         -1, -1, -1, -1, -1, -1, -1, -1,
951         -1, -1, -1, -1, -1, -1, -1, -1,
952         -1, -1, -1, -1, -1, -1, -1, -1
953 };
954 
955 struct hdspm_midi {
956         struct hdspm *hdspm;
957         int id;
958         struct snd_rawmidi *rmidi;
959         struct snd_rawmidi_substream *input;
960         struct snd_rawmidi_substream *output;
961         char istimer;           /* timer in use */
962         struct timer_list timer;
963         spinlock_t lock;
964         int pending;
965         int dataIn;
966         int statusIn;
967         int dataOut;
968         int statusOut;
969         int ie;
970         int irq;
971 };
972 
973 struct hdspm_tco {
974         int input; /* 0: LTC, 1:Video, 2: WC*/
975         int framerate; /* 0=24, 1=25, 2=29.97, 3=29.97d, 4=30, 5=30d */
976         int wordclock; /* 0=1:1, 1=44.1->48, 2=48->44.1 */
977         int samplerate; /* 0=44.1, 1=48, 2= freq from app */
978         int pull; /*   0=0, 1=+0.1%, 2=-0.1%, 3=+4%, 4=-4%*/
979         int term; /* 0 = off, 1 = on */
980 };
981 
982 struct hdspm {
983         spinlock_t lock;
984         /* only one playback and/or capture stream */
985         struct snd_pcm_substream *capture_substream;
986         struct snd_pcm_substream *playback_substream;
987 
988         char *card_name;             /* for procinfo */
989         unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/
990 
991         uint8_t io_type;
992 
993         int monitor_outs;       /* set up monitoring outs init flag */
994 
995         u32 control_register;   /* cached value */
996         u32 control2_register;  /* cached value */
997         u32 settings_register;  /* cached value for AIO / RayDat (sync reference, master/slave) */
998 
999         struct hdspm_midi midi[4];
1000         struct work_struct midi_work;
1001 
1002         size_t period_bytes;
1003         unsigned char ss_in_channels;
1004         unsigned char ds_in_channels;
1005         unsigned char qs_in_channels;
1006         unsigned char ss_out_channels;
1007         unsigned char ds_out_channels;
1008         unsigned char qs_out_channels;
1009 
1010         unsigned char max_channels_in;
1011         unsigned char max_channels_out;
1012 
1013         const signed char *channel_map_in;
1014         const signed char *channel_map_out;
1015 
1016         const signed char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs;
1017         const signed char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs;
1018 
1019         const char * const *port_names_in;
1020         const char * const *port_names_out;
1021 
1022         const char * const *port_names_in_ss;
1023         const char * const *port_names_in_ds;
1024         const char * const *port_names_in_qs;
1025         const char * const *port_names_out_ss;
1026         const char * const *port_names_out_ds;
1027         const char * const *port_names_out_qs;
1028 
1029         unsigned char *playback_buffer; /* suitably aligned address */
1030         unsigned char *capture_buffer;  /* suitably aligned address */
1031 
1032         pid_t capture_pid;      /* process id which uses capture */
1033         pid_t playback_pid;     /* process id which uses capture */
1034         int running;            /* running status */
1035 
1036         int last_external_sample_rate;  /* samplerate mystic ... */
1037         int last_internal_sample_rate;
1038         int system_sample_rate;
1039 
1040         int dev;                /* Hardware vars... */
1041         int irq;
1042         unsigned long port;
1043         void __iomem *iobase;
1044 
1045         int irq_count;          /* for debug */
1046         int midiPorts;
1047 
1048         struct snd_card *card;  /* one card */
1049         struct snd_pcm *pcm;            /* has one pcm */
1050         struct snd_hwdep *hwdep;        /* and a hwdep for additional ioctl */
1051         struct pci_dev *pci;    /* and an pci info */
1052 
1053         /* Mixer vars */
1054         /* fast alsa mixer */
1055         struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS];
1056         /* but input to much, so not used */
1057         struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS];
1058         /* full mixer accessible over mixer ioctl or hwdep-device */
1059         struct hdspm_mixer *mixer;
1060 
1061         struct hdspm_tco *tco;  /* NULL if no TCO detected */
1062 
1063         const char *const *texts_autosync;
1064         int texts_autosync_items;
1065 
1066         cycles_t last_interrupt;
1067 
1068         unsigned int serial;
1069 
1070         struct hdspm_peak_rms peak_rms;
1071 };
1072 
1073 
1074 static const struct pci_device_id snd_hdspm_ids[] = {
1075         {
1076          .vendor = PCI_VENDOR_ID_XILINX,
1077          .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI,
1078          .subvendor = PCI_ANY_ID,
1079          .subdevice = PCI_ANY_ID,
1080          .class = 0,
1081          .class_mask = 0,
1082          .driver_data = 0},
1083         {0,}
1084 };
1085 
1086 MODULE_DEVICE_TABLE(pci, snd_hdspm_ids);
1087 
1088 /* prototypes */
1089 static int snd_hdspm_create_alsa_devices(struct snd_card *card,
1090                                          struct hdspm *hdspm);
1091 static int snd_hdspm_create_pcm(struct snd_card *card,
1092                                 struct hdspm *hdspm);
1093 
1094 static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm);
1095 static inline int hdspm_get_pll_freq(struct hdspm *hdspm);
1096 static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm);
1097 static int hdspm_autosync_ref(struct hdspm *hdspm);
1098 static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out);
1099 static int snd_hdspm_set_defaults(struct hdspm *hdspm);
1100 static int hdspm_system_clock_mode(struct hdspm *hdspm);
1101 static void hdspm_set_channel_dma_addr(struct hdspm *hdspm,
1102                                        struct snd_pcm_substream *substream,
1103                                        unsigned int reg, int channels);
1104 
1105 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx);
1106 static int hdspm_wc_sync_check(struct hdspm *hdspm);
1107 static int hdspm_tco_sync_check(struct hdspm *hdspm);
1108 static int hdspm_sync_in_sync_check(struct hdspm *hdspm);
1109 
1110 static int hdspm_get_aes_sample_rate(struct hdspm *hdspm, int index);
1111 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm);
1112 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm);
1113 
1114 
1115 
1116 static inline int HDSPM_bit2freq(int n)
1117 {
1118         static const int bit2freq_tab[] = {
1119                 0, 32000, 44100, 48000, 64000, 88200,
1120                 96000, 128000, 176400, 192000 };
1121         if (n < 1 || n > 9)
1122                 return 0;
1123         return bit2freq_tab[n];
1124 }
1125 
1126 static bool hdspm_is_raydat_or_aio(struct hdspm *hdspm)
1127 {
1128         return ((AIO == hdspm->io_type) || (RayDAT == hdspm->io_type));
1129 }
1130 
1131 
1132 /* Write/read to/from HDSPM with Adresses in Bytes
1133    not words but only 32Bit writes are allowed */
1134 
1135 static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg,
1136                                unsigned int val)
1137 {
1138         writel(val, hdspm->iobase + reg);
1139 }
1140 
1141 static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg)
1142 {
1143         return readl(hdspm->iobase + reg);
1144 }
1145 
1146 /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader
1147    mixer is write only on hardware so we have to cache him for read
1148    each fader is a u32, but uses only the first 16 bit */
1149 
1150 static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan,
1151                                      unsigned int in)
1152 {
1153         if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1154                 return 0;
1155 
1156         return hdspm->mixer->ch[chan].in[in];
1157 }
1158 
1159 static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan,
1160                                      unsigned int pb)
1161 {
1162         if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1163                 return 0;
1164         return hdspm->mixer->ch[chan].pb[pb];
1165 }
1166 
1167 static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan,
1168                                       unsigned int in, unsigned short data)
1169 {
1170         if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1171                 return -1;
1172 
1173         hdspm_write(hdspm,
1174                     HDSPM_MADI_mixerBase +
1175                     ((in + 128 * chan) * sizeof(u32)),
1176                     (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF));
1177         return 0;
1178 }
1179 
1180 static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan,
1181                                       unsigned int pb, unsigned short data)
1182 {
1183         if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1184                 return -1;
1185 
1186         hdspm_write(hdspm,
1187                     HDSPM_MADI_mixerBase +
1188                     ((64 + pb + 128 * chan) * sizeof(u32)),
1189                     (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF));
1190         return 0;
1191 }
1192 
1193 
1194 /* enable DMA for specific channels, now available for DSP-MADI */
1195 static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v)
1196 {
1197         hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v);
1198 }
1199 
1200 static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v)
1201 {
1202         hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v);
1203 }
1204 
1205 /* check if same process is writing and reading */
1206 static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm)
1207 {
1208         unsigned long flags;
1209         int ret = 1;
1210 
1211         spin_lock_irqsave(&hdspm->lock, flags);
1212         if ((hdspm->playback_pid != hdspm->capture_pid) &&
1213             (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) {
1214                 ret = 0;
1215         }
1216         spin_unlock_irqrestore(&hdspm->lock, flags);
1217         return ret;
1218 }
1219 
1220 /* round arbitrary sample rates to commonly known rates */
1221 static int hdspm_round_frequency(int rate)
1222 {
1223         if (rate < 38050)
1224                 return 32000;
1225         if (rate < 46008)
1226                 return 44100;
1227         else
1228                 return 48000;
1229 }
1230 
1231 /* QS and DS rates normally can not be detected
1232  * automatically by the card. Only exception is MADI
1233  * in 96k frame mode.
1234  *
1235  * So if we read SS values (32 .. 48k), check for
1236  * user-provided DS/QS bits in the control register
1237  * and multiply the base frequency accordingly.
1238  */
1239 static int hdspm_rate_multiplier(struct hdspm *hdspm, int rate)
1240 {
1241         if (rate <= 48000) {
1242                 if (hdspm->control_register & HDSPM_QuadSpeed)
1243                         return rate * 4;
1244                 else if (hdspm->control_register &
1245                                 HDSPM_DoubleSpeed)
1246                         return rate * 2;
1247         }
1248         return rate;
1249 }
1250 
1251 /* check for external sample rate, returns the sample rate in Hz*/
1252 static int hdspm_external_sample_rate(struct hdspm *hdspm)
1253 {
1254         unsigned int status, status2;
1255         int syncref, rate = 0, rate_bits;
1256 
1257         switch (hdspm->io_type) {
1258         case AES32:
1259                 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1260                 status = hdspm_read(hdspm, HDSPM_statusRegister);
1261 
1262                 syncref = hdspm_autosync_ref(hdspm);
1263                 switch (syncref) {
1264                 case HDSPM_AES32_AUTOSYNC_FROM_WORD:
1265                 /* Check WC sync and get sample rate */
1266                         if (hdspm_wc_sync_check(hdspm))
1267                                 return HDSPM_bit2freq(hdspm_get_wc_sample_rate(hdspm));
1268                         break;
1269 
1270                 case HDSPM_AES32_AUTOSYNC_FROM_AES1:
1271                 case HDSPM_AES32_AUTOSYNC_FROM_AES2:
1272                 case HDSPM_AES32_AUTOSYNC_FROM_AES3:
1273                 case HDSPM_AES32_AUTOSYNC_FROM_AES4:
1274                 case HDSPM_AES32_AUTOSYNC_FROM_AES5:
1275                 case HDSPM_AES32_AUTOSYNC_FROM_AES6:
1276                 case HDSPM_AES32_AUTOSYNC_FROM_AES7:
1277                 case HDSPM_AES32_AUTOSYNC_FROM_AES8:
1278                 /* Check AES sync and get sample rate */
1279                         if (hdspm_aes_sync_check(hdspm, syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1))
1280                                 return HDSPM_bit2freq(hdspm_get_aes_sample_rate(hdspm,
1281                                                         syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1));
1282                         break;
1283 
1284 
1285                 case HDSPM_AES32_AUTOSYNC_FROM_TCO:
1286                 /* Check TCO sync and get sample rate */
1287                         if (hdspm_tco_sync_check(hdspm))
1288                                 return HDSPM_bit2freq(hdspm_get_tco_sample_rate(hdspm));
1289                         break;
1290                 default:
1291                         return 0;
1292                 } /* end switch(syncref) */
1293                 break;
1294 
1295         case MADIface:
1296                 status = hdspm_read(hdspm, HDSPM_statusRegister);
1297 
1298                 if (!(status & HDSPM_madiLock)) {
1299                         rate = 0;  /* no lock */
1300                 } else {
1301                         switch (status & (HDSPM_status1_freqMask)) {
1302                         case HDSPM_status1_F_0*1:
1303                                 rate = 32000; break;
1304                         case HDSPM_status1_F_0*2:
1305                                 rate = 44100; break;
1306                         case HDSPM_status1_F_0*3:
1307                                 rate = 48000; break;
1308                         case HDSPM_status1_F_0*4:
1309                                 rate = 64000; break;
1310                         case HDSPM_status1_F_0*5:
1311                                 rate = 88200; break;
1312                         case HDSPM_status1_F_0*6:
1313                                 rate = 96000; break;
1314                         case HDSPM_status1_F_0*7:
1315                                 rate = 128000; break;
1316                         case HDSPM_status1_F_0*8:
1317                                 rate = 176400; break;
1318                         case HDSPM_status1_F_0*9:
1319                                 rate = 192000; break;
1320                         default:
1321                                 rate = 0; break;
1322                         }
1323                 }
1324 
1325                 break;
1326 
1327         case MADI:
1328         case AIO:
1329         case RayDAT:
1330                 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1331                 status = hdspm_read(hdspm, HDSPM_statusRegister);
1332                 rate = 0;
1333 
1334                 /* if wordclock has synced freq and wordclock is valid */
1335                 if ((status2 & HDSPM_wcLock) != 0 &&
1336                                 (status2 & HDSPM_SelSyncRef0) == 0) {
1337 
1338                         rate_bits = status2 & HDSPM_wcFreqMask;
1339 
1340 
1341                         switch (rate_bits) {
1342                         case HDSPM_wcFreq32:
1343                                 rate = 32000;
1344                                 break;
1345                         case HDSPM_wcFreq44_1:
1346                                 rate = 44100;
1347                                 break;
1348                         case HDSPM_wcFreq48:
1349                                 rate = 48000;
1350                                 break;
1351                         case HDSPM_wcFreq64:
1352                                 rate = 64000;
1353                                 break;
1354                         case HDSPM_wcFreq88_2:
1355                                 rate = 88200;
1356                                 break;
1357                         case HDSPM_wcFreq96:
1358                                 rate = 96000;
1359                                 break;
1360                         case HDSPM_wcFreq128:
1361                                 rate = 128000;
1362                                 break;
1363                         case HDSPM_wcFreq176_4:
1364                                 rate = 176400;
1365                                 break;
1366                         case HDSPM_wcFreq192:
1367                                 rate = 192000;
1368                                 break;
1369                         default:
1370                                 rate = 0;
1371                                 break;
1372                         }
1373                 }
1374 
1375                 /* if rate detected and Syncref is Word than have it,
1376                  * word has priority to MADI
1377                  */
1378                 if (rate != 0 &&
1379                 (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD)
1380                         return hdspm_rate_multiplier(hdspm, rate);
1381 
1382                 /* maybe a madi input (which is taken if sel sync is madi) */
1383                 if (status & HDSPM_madiLock) {
1384                         rate_bits = status & HDSPM_madiFreqMask;
1385 
1386                         switch (rate_bits) {
1387                         case HDSPM_madiFreq32:
1388                                 rate = 32000;
1389                                 break;
1390                         case HDSPM_madiFreq44_1:
1391                                 rate = 44100;
1392                                 break;
1393                         case HDSPM_madiFreq48:
1394                                 rate = 48000;
1395                                 break;
1396                         case HDSPM_madiFreq64:
1397                                 rate = 64000;
1398                                 break;
1399                         case HDSPM_madiFreq88_2:
1400                                 rate = 88200;
1401                                 break;
1402                         case HDSPM_madiFreq96:
1403                                 rate = 96000;
1404                                 break;
1405                         case HDSPM_madiFreq128:
1406                                 rate = 128000;
1407                                 break;
1408                         case HDSPM_madiFreq176_4:
1409                                 rate = 176400;
1410                                 break;
1411                         case HDSPM_madiFreq192:
1412                                 rate = 192000;
1413                                 break;
1414                         default:
1415                                 rate = 0;
1416                                 break;
1417                         }
1418 
1419                 } /* endif HDSPM_madiLock */
1420 
1421                 /* check sample rate from TCO or SYNC_IN */
1422                 {
1423                         bool is_valid_input = 0;
1424                         bool has_sync = 0;
1425 
1426                         syncref = hdspm_autosync_ref(hdspm);
1427                         if (HDSPM_AUTOSYNC_FROM_TCO == syncref) {
1428                                 is_valid_input = 1;
1429                                 has_sync = (HDSPM_SYNC_CHECK_SYNC ==
1430                                         hdspm_tco_sync_check(hdspm));
1431                         } else if (HDSPM_AUTOSYNC_FROM_SYNC_IN == syncref) {
1432                                 is_valid_input = 1;
1433                                 has_sync = (HDSPM_SYNC_CHECK_SYNC ==
1434                                         hdspm_sync_in_sync_check(hdspm));
1435                         }
1436 
1437                         if (is_valid_input && has_sync) {
1438                                 rate = hdspm_round_frequency(
1439                                         hdspm_get_pll_freq(hdspm));
1440                         }
1441                 }
1442 
1443                 rate = hdspm_rate_multiplier(hdspm, rate);
1444 
1445                 break;
1446         }
1447 
1448         return rate;
1449 }
1450 
1451 /* return latency in samples per period */
1452 static int hdspm_get_latency(struct hdspm *hdspm)
1453 {
1454         int n;
1455 
1456         n = hdspm_decode_latency(hdspm->control_register);
1457 
1458         /* Special case for new RME cards with 32 samples period size.
1459          * The three latency bits in the control register
1460          * (HDSP_LatencyMask) encode latency values of 64 samples as
1461          * 0, 128 samples as 1 ... 4096 samples as 6. For old cards, 7
1462          * denotes 8192 samples, but on new cards like RayDAT or AIO,
1463          * it corresponds to 32 samples.
1464          */
1465         if ((7 == n) && (RayDAT == hdspm->io_type || AIO == hdspm->io_type))
1466                 n = -1;
1467 
1468         return 1 << (n + 6);
1469 }
1470 
1471 /* Latency function */
1472 static inline void hdspm_compute_period_size(struct hdspm *hdspm)
1473 {
1474         hdspm->period_bytes = 4 * hdspm_get_latency(hdspm);
1475 }
1476 
1477 
1478 static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm)
1479 {
1480         int position;
1481 
1482         position = hdspm_read(hdspm, HDSPM_statusRegister);
1483 
1484         switch (hdspm->io_type) {
1485         case RayDAT:
1486         case AIO:
1487                 position &= HDSPM_BufferPositionMask;
1488                 position /= 4; /* Bytes per sample */
1489                 break;
1490         default:
1491                 position = (position & HDSPM_BufferID) ?
1492                         (hdspm->period_bytes / 4) : 0;
1493         }
1494 
1495         return position;
1496 }
1497 
1498 
1499 static inline void hdspm_start_audio(struct hdspm * s)
1500 {
1501         s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start);
1502         hdspm_write(s, HDSPM_controlRegister, s->control_register);
1503 }
1504 
1505 static inline void hdspm_stop_audio(struct hdspm * s)
1506 {
1507         s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable);
1508         hdspm_write(s, HDSPM_controlRegister, s->control_register);
1509 }
1510 
1511 /* should I silence all or only opened ones ? doit all for first even is 4MB*/
1512 static void hdspm_silence_playback(struct hdspm *hdspm)
1513 {
1514         int i;
1515         int n = hdspm->period_bytes;
1516         void *buf = hdspm->playback_buffer;
1517 
1518         if (!buf)
1519                 return;
1520 
1521         for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
1522                 memset(buf, 0, n);
1523                 buf += HDSPM_CHANNEL_BUFFER_BYTES;
1524         }
1525 }
1526 
1527 static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames)
1528 {
1529         int n;
1530 
1531         spin_lock_irq(&s->lock);
1532 
1533         if (32 == frames) {
1534                 /* Special case for new RME cards like RayDAT/AIO which
1535                  * support period sizes of 32 samples. Since latency is
1536                  * encoded in the three bits of HDSP_LatencyMask, we can only
1537                  * have values from 0 .. 7. While 0 still means 64 samples and
1538                  * 6 represents 4096 samples on all cards, 7 represents 8192
1539                  * on older cards and 32 samples on new cards.
1540                  *
1541                  * In other words, period size in samples is calculated by
1542                  * 2^(n+6) with n ranging from 0 .. 7.
1543                  */
1544                 n = 7;
1545         } else {
1546                 frames >>= 7;
1547                 n = 0;
1548                 while (frames) {
1549                         n++;
1550                         frames >>= 1;
1551                 }
1552         }
1553 
1554         s->control_register &= ~HDSPM_LatencyMask;
1555         s->control_register |= hdspm_encode_latency(n);
1556 
1557         hdspm_write(s, HDSPM_controlRegister, s->control_register);
1558 
1559         hdspm_compute_period_size(s);
1560 
1561         spin_unlock_irq(&s->lock);
1562 
1563         return 0;
1564 }
1565 
1566 static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period)
1567 {
1568         u64 freq_const;
1569 
1570         if (period == 0)
1571                 return 0;
1572 
1573         switch (hdspm->io_type) {
1574         case MADI:
1575         case AES32:
1576                 freq_const = 110069313433624ULL;
1577                 break;
1578         case RayDAT:
1579         case AIO:
1580                 freq_const = 104857600000000ULL;
1581                 break;
1582         case MADIface:
1583                 freq_const = 131072000000000ULL;
1584                 break;
1585         default:
1586                 snd_BUG();
1587                 return 0;
1588         }
1589 
1590         return div_u64(freq_const, period);
1591 }
1592 
1593 
1594 static void hdspm_set_dds_value(struct hdspm *hdspm, int rate)
1595 {
1596         u64 n;
1597 
1598         if (snd_BUG_ON(rate <= 0))
1599                 return;
1600 
1601         if (rate >= 112000)
1602                 rate /= 4;
1603         else if (rate >= 56000)
1604                 rate /= 2;
1605 
1606         switch (hdspm->io_type) {
1607         case MADIface:
1608                 n = 131072000000000ULL;  /* 125 MHz */
1609                 break;
1610         case MADI:
1611         case AES32:
1612                 n = 110069313433624ULL;  /* 105 MHz */
1613                 break;
1614         case RayDAT:
1615         case AIO:
1616                 n = 104857600000000ULL;  /* 100 MHz */
1617                 break;
1618         default:
1619                 snd_BUG();
1620                 return;
1621         }
1622 
1623         n = div_u64(n, rate);
1624         /* n should be less than 2^32 for being written to FREQ register */
1625         snd_BUG_ON(n >> 32);
1626         hdspm_write(hdspm, HDSPM_freqReg, (u32)n);
1627 }
1628 
1629 /* dummy set rate lets see what happens */
1630 static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally)
1631 {
1632         int current_rate;
1633         int rate_bits;
1634         int not_set = 0;
1635         int current_speed, target_speed;
1636 
1637         /* ASSUMPTION: hdspm->lock is either set, or there is no need for
1638            it (e.g. during module initialization).
1639          */
1640 
1641         if (!(hdspm->control_register & HDSPM_ClockModeMaster)) {
1642 
1643                 /* SLAVE --- */
1644                 if (called_internally) {
1645 
1646                         /* request from ctl or card initialization
1647                            just make a warning an remember setting
1648                            for future master mode switching */
1649 
1650                         dev_warn(hdspm->card->dev,
1651                                  "Warning: device is not running as a clock master.\n");
1652                         not_set = 1;
1653                 } else {
1654 
1655                         /* hw_param request while in AutoSync mode */
1656                         int external_freq =
1657                             hdspm_external_sample_rate(hdspm);
1658 
1659                         if (hdspm_autosync_ref(hdspm) ==
1660                             HDSPM_AUTOSYNC_FROM_NONE) {
1661 
1662                                 dev_warn(hdspm->card->dev,
1663                                          "Detected no External Sync\n");
1664                                 not_set = 1;
1665 
1666                         } else if (rate != external_freq) {
1667 
1668                                 dev_warn(hdspm->card->dev,
1669                                          "Warning: No AutoSync source for requested rate\n");
1670                                 not_set = 1;
1671                         }
1672                 }
1673         }
1674 
1675         current_rate = hdspm->system_sample_rate;
1676 
1677         /* Changing between Singe, Double and Quad speed is not
1678            allowed if any substreams are open. This is because such a change
1679            causes a shift in the location of the DMA buffers and a reduction
1680            in the number of available buffers.
1681 
1682            Note that a similar but essentially insoluble problem exists for
1683            externally-driven rate changes. All we can do is to flag rate
1684            changes in the read/write routines.
1685          */
1686 
1687         if (current_rate <= 48000)
1688                 current_speed = HDSPM_SPEED_SINGLE;
1689         else if (current_rate <= 96000)
1690                 current_speed = HDSPM_SPEED_DOUBLE;
1691         else
1692                 current_speed = HDSPM_SPEED_QUAD;
1693 
1694         if (rate <= 48000)
1695                 target_speed = HDSPM_SPEED_SINGLE;
1696         else if (rate <= 96000)
1697                 target_speed = HDSPM_SPEED_DOUBLE;
1698         else
1699                 target_speed = HDSPM_SPEED_QUAD;
1700 
1701         switch (rate) {
1702         case 32000:
1703                 rate_bits = HDSPM_Frequency32KHz;
1704                 break;
1705         case 44100:
1706                 rate_bits = HDSPM_Frequency44_1KHz;
1707                 break;
1708         case 48000:
1709                 rate_bits = HDSPM_Frequency48KHz;
1710                 break;
1711         case 64000:
1712                 rate_bits = HDSPM_Frequency64KHz;
1713                 break;
1714         case 88200:
1715                 rate_bits = HDSPM_Frequency88_2KHz;
1716                 break;
1717         case 96000:
1718                 rate_bits = HDSPM_Frequency96KHz;
1719                 break;
1720         case 128000:
1721                 rate_bits = HDSPM_Frequency128KHz;
1722                 break;
1723         case 176400:
1724                 rate_bits = HDSPM_Frequency176_4KHz;
1725                 break;
1726         case 192000:
1727                 rate_bits = HDSPM_Frequency192KHz;
1728                 break;
1729         default:
1730                 return -EINVAL;
1731         }
1732 
1733         if (current_speed != target_speed
1734             && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) {
1735                 dev_err(hdspm->card->dev,
1736                         "cannot change from %s speed to %s speed mode (capture PID = %d, playback PID = %d)\n",
1737                         hdspm_speed_names[current_speed],
1738                         hdspm_speed_names[target_speed],
1739                         hdspm->capture_pid, hdspm->playback_pid);
1740                 return -EBUSY;
1741         }
1742 
1743         hdspm->control_register &= ~HDSPM_FrequencyMask;
1744         hdspm->control_register |= rate_bits;
1745         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1746 
1747         /* For AES32, need to set DDS value in FREQ register
1748            For MADI, also apparently */
1749         hdspm_set_dds_value(hdspm, rate);
1750 
1751         if (AES32 == hdspm->io_type && rate != current_rate)
1752                 hdspm_write(hdspm, HDSPM_eeprom_wr, 0);
1753 
1754         hdspm->system_sample_rate = rate;
1755 
1756         if (rate <= 48000) {
1757                 hdspm->channel_map_in = hdspm->channel_map_in_ss;
1758                 hdspm->channel_map_out = hdspm->channel_map_out_ss;
1759                 hdspm->max_channels_in = hdspm->ss_in_channels;
1760                 hdspm->max_channels_out = hdspm->ss_out_channels;
1761                 hdspm->port_names_in = hdspm->port_names_in_ss;
1762                 hdspm->port_names_out = hdspm->port_names_out_ss;
1763         } else if (rate <= 96000) {
1764                 hdspm->channel_map_in = hdspm->channel_map_in_ds;
1765                 hdspm->channel_map_out = hdspm->channel_map_out_ds;
1766                 hdspm->max_channels_in = hdspm->ds_in_channels;
1767                 hdspm->max_channels_out = hdspm->ds_out_channels;
1768                 hdspm->port_names_in = hdspm->port_names_in_ds;
1769                 hdspm->port_names_out = hdspm->port_names_out_ds;
1770         } else {
1771                 hdspm->channel_map_in = hdspm->channel_map_in_qs;
1772                 hdspm->channel_map_out = hdspm->channel_map_out_qs;
1773                 hdspm->max_channels_in = hdspm->qs_in_channels;
1774                 hdspm->max_channels_out = hdspm->qs_out_channels;
1775                 hdspm->port_names_in = hdspm->port_names_in_qs;
1776                 hdspm->port_names_out = hdspm->port_names_out_qs;
1777         }
1778 
1779         if (not_set != 0)
1780                 return -1;
1781 
1782         return 0;
1783 }
1784 
1785 /* mainly for init to 0 on load */
1786 static void all_in_all_mixer(struct hdspm * hdspm, int sgain)
1787 {
1788         int i, j;
1789         unsigned int gain;
1790 
1791         if (sgain > UNITY_GAIN)
1792                 gain = UNITY_GAIN;
1793         else if (sgain < 0)
1794                 gain = 0;
1795         else
1796                 gain = sgain;
1797 
1798         for (i = 0; i < HDSPM_MIXER_CHANNELS; i++)
1799                 for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) {
1800                         hdspm_write_in_gain(hdspm, i, j, gain);
1801                         hdspm_write_pb_gain(hdspm, i, j, gain);
1802                 }
1803 }
1804 
1805 /*----------------------------------------------------------------------------
1806    MIDI
1807   ----------------------------------------------------------------------------*/
1808 
1809 static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm,
1810                                                       int id)
1811 {
1812         /* the hardware already does the relevant bit-mask with 0xff */
1813         return hdspm_read(hdspm, hdspm->midi[id].dataIn);
1814 }
1815 
1816 static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id,
1817                                               int val)
1818 {
1819         /* the hardware already does the relevant bit-mask with 0xff */
1820         return hdspm_write(hdspm, hdspm->midi[id].dataOut, val);
1821 }
1822 
1823 static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id)
1824 {
1825         return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF;
1826 }
1827 
1828 static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id)
1829 {
1830         int fifo_bytes_used;
1831 
1832         fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF;
1833 
1834         if (fifo_bytes_used < 128)
1835                 return  128 - fifo_bytes_used;
1836         else
1837                 return 0;
1838 }
1839 
1840 static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id)
1841 {
1842         while (snd_hdspm_midi_input_available (hdspm, id))
1843                 snd_hdspm_midi_read_byte (hdspm, id);
1844 }
1845 
1846 static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi)
1847 {
1848         unsigned long flags;
1849         int n_pending;
1850         int to_write;
1851         int i;
1852         unsigned char buf[128];
1853 
1854         /* Output is not interrupt driven */
1855 
1856         spin_lock_irqsave (&hmidi->lock, flags);
1857         if (hmidi->output &&
1858             !snd_rawmidi_transmit_empty (hmidi->output)) {
1859                 n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm,
1860                                                             hmidi->id);
1861                 if (n_pending > 0) {
1862                         if (n_pending > (int)sizeof (buf))
1863                                 n_pending = sizeof (buf);
1864 
1865                         to_write = snd_rawmidi_transmit (hmidi->output, buf,
1866                                                          n_pending);
1867                         if (to_write > 0) {
1868                                 for (i = 0; i < to_write; ++i)
1869                                         snd_hdspm_midi_write_byte (hmidi->hdspm,
1870                                                                    hmidi->id,
1871                                                                    buf[i]);
1872                         }
1873                 }
1874         }
1875         spin_unlock_irqrestore (&hmidi->lock, flags);
1876         return 0;
1877 }
1878 
1879 static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi)
1880 {
1881         unsigned char buf[128]; /* this buffer is designed to match the MIDI
1882                                  * input FIFO size
1883                                  */
1884         unsigned long flags;
1885         int n_pending;
1886         int i;
1887 
1888         spin_lock_irqsave (&hmidi->lock, flags);
1889         n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id);
1890         if (n_pending > 0) {
1891                 if (hmidi->input) {
1892                         if (n_pending > (int)sizeof (buf))
1893                                 n_pending = sizeof (buf);
1894                         for (i = 0; i < n_pending; ++i)
1895                                 buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm,
1896                                                                    hmidi->id);
1897                         if (n_pending)
1898                                 snd_rawmidi_receive (hmidi->input, buf,
1899                                                      n_pending);
1900                 } else {
1901                         /* flush the MIDI input FIFO */
1902                         while (n_pending--)
1903                                 snd_hdspm_midi_read_byte (hmidi->hdspm,
1904                                                           hmidi->id);
1905                 }
1906         }
1907         hmidi->pending = 0;
1908         spin_unlock_irqrestore(&hmidi->lock, flags);
1909 
1910         spin_lock_irqsave(&hmidi->hdspm->lock, flags);
1911         hmidi->hdspm->control_register |= hmidi->ie;
1912         hdspm_write(hmidi->hdspm, HDSPM_controlRegister,
1913                     hmidi->hdspm->control_register);
1914         spin_unlock_irqrestore(&hmidi->hdspm->lock, flags);
1915 
1916         return snd_hdspm_midi_output_write (hmidi);
1917 }
1918 
1919 static void
1920 snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1921 {
1922         struct hdspm *hdspm;
1923         struct hdspm_midi *hmidi;
1924         unsigned long flags;
1925 
1926         hmidi = substream->rmidi->private_data;
1927         hdspm = hmidi->hdspm;
1928 
1929         spin_lock_irqsave (&hdspm->lock, flags);
1930         if (up) {
1931                 if (!(hdspm->control_register & hmidi->ie)) {
1932                         snd_hdspm_flush_midi_input (hdspm, hmidi->id);
1933                         hdspm->control_register |= hmidi->ie;
1934                 }
1935         } else {
1936                 hdspm->control_register &= ~hmidi->ie;
1937         }
1938 
1939         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1940         spin_unlock_irqrestore (&hdspm->lock, flags);
1941 }
1942 
1943 static void snd_hdspm_midi_output_timer(struct timer_list *t)
1944 {
1945         struct hdspm_midi *hmidi = from_timer(hmidi, t, timer);
1946         unsigned long flags;
1947 
1948         snd_hdspm_midi_output_write(hmidi);
1949         spin_lock_irqsave (&hmidi->lock, flags);
1950 
1951         /* this does not bump hmidi->istimer, because the
1952            kernel automatically removed the timer when it
1953            expired, and we are now adding it back, thus
1954            leaving istimer wherever it was set before.
1955         */
1956 
1957         if (hmidi->istimer)
1958                 mod_timer(&hmidi->timer, 1 + jiffies);
1959 
1960         spin_unlock_irqrestore (&hmidi->lock, flags);
1961 }
1962 
1963 static void
1964 snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1965 {
1966         struct hdspm_midi *hmidi;
1967         unsigned long flags;
1968 
1969         hmidi = substream->rmidi->private_data;
1970         spin_lock_irqsave (&hmidi->lock, flags);
1971         if (up) {
1972                 if (!hmidi->istimer) {
1973                         timer_setup(&hmidi->timer,
1974                                     snd_hdspm_midi_output_timer, 0);
1975                         mod_timer(&hmidi->timer, 1 + jiffies);
1976                         hmidi->istimer++;
1977                 }
1978         } else {
1979                 if (hmidi->istimer && --hmidi->istimer <= 0)
1980                         del_timer (&hmidi->timer);
1981         }
1982         spin_unlock_irqrestore (&hmidi->lock, flags);
1983         if (up)
1984                 snd_hdspm_midi_output_write(hmidi);
1985 }
1986 
1987 static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream)
1988 {
1989         struct hdspm_midi *hmidi;
1990 
1991         hmidi = substream->rmidi->private_data;
1992         spin_lock_irq (&hmidi->lock);
1993         snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id);
1994         hmidi->input = substream;
1995         spin_unlock_irq (&hmidi->lock);
1996 
1997         return 0;
1998 }
1999 
2000 static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream)
2001 {
2002         struct hdspm_midi *hmidi;
2003 
2004         hmidi = substream->rmidi->private_data;
2005         spin_lock_irq (&hmidi->lock);
2006         hmidi->output = substream;
2007         spin_unlock_irq (&hmidi->lock);
2008 
2009         return 0;
2010 }
2011 
2012 static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream)
2013 {
2014         struct hdspm_midi *hmidi;
2015 
2016         snd_hdspm_midi_input_trigger (substream, 0);
2017 
2018         hmidi = substream->rmidi->private_data;
2019         spin_lock_irq (&hmidi->lock);
2020         hmidi->input = NULL;
2021         spin_unlock_irq (&hmidi->lock);
2022 
2023         return 0;
2024 }
2025 
2026 static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream)
2027 {
2028         struct hdspm_midi *hmidi;
2029 
2030         snd_hdspm_midi_output_trigger (substream, 0);
2031 
2032         hmidi = substream->rmidi->private_data;
2033         spin_lock_irq (&hmidi->lock);
2034         hmidi->output = NULL;
2035         spin_unlock_irq (&hmidi->lock);
2036 
2037         return 0;
2038 }
2039 
2040 static const struct snd_rawmidi_ops snd_hdspm_midi_output =
2041 {
2042         .open =         snd_hdspm_midi_output_open,
2043         .close =        snd_hdspm_midi_output_close,
2044         .trigger =      snd_hdspm_midi_output_trigger,
2045 };
2046 
2047 static const struct snd_rawmidi_ops snd_hdspm_midi_input =
2048 {
2049         .open =         snd_hdspm_midi_input_open,
2050         .close =        snd_hdspm_midi_input_close,
2051         .trigger =      snd_hdspm_midi_input_trigger,
2052 };
2053 
2054 static int snd_hdspm_create_midi(struct snd_card *card,
2055                                  struct hdspm *hdspm, int id)
2056 {
2057         int err;
2058         char buf[64];
2059 
2060         hdspm->midi[id].id = id;
2061         hdspm->midi[id].hdspm = hdspm;
2062         spin_lock_init (&hdspm->midi[id].lock);
2063 
2064         if (0 == id) {
2065                 if (MADIface == hdspm->io_type) {
2066                         /* MIDI-over-MADI on HDSPe MADIface */
2067                         hdspm->midi[0].dataIn = HDSPM_midiDataIn2;
2068                         hdspm->midi[0].statusIn = HDSPM_midiStatusIn2;
2069                         hdspm->midi[0].dataOut = HDSPM_midiDataOut2;
2070                         hdspm->midi[0].statusOut = HDSPM_midiStatusOut2;
2071                         hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable;
2072                         hdspm->midi[0].irq = HDSPM_midi2IRQPending;
2073                 } else {
2074                         hdspm->midi[0].dataIn = HDSPM_midiDataIn0;
2075                         hdspm->midi[0].statusIn = HDSPM_midiStatusIn0;
2076                         hdspm->midi[0].dataOut = HDSPM_midiDataOut0;
2077                         hdspm->midi[0].statusOut = HDSPM_midiStatusOut0;
2078                         hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable;
2079                         hdspm->midi[0].irq = HDSPM_midi0IRQPending;
2080                 }
2081         } else if (1 == id) {
2082                 hdspm->midi[1].dataIn = HDSPM_midiDataIn1;
2083                 hdspm->midi[1].statusIn = HDSPM_midiStatusIn1;
2084                 hdspm->midi[1].dataOut = HDSPM_midiDataOut1;
2085                 hdspm->midi[1].statusOut = HDSPM_midiStatusOut1;
2086                 hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable;
2087                 hdspm->midi[1].irq = HDSPM_midi1IRQPending;
2088         } else if ((2 == id) && (MADI == hdspm->io_type)) {
2089                 /* MIDI-over-MADI on HDSPe MADI */
2090                 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
2091                 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
2092                 hdspm->midi[2].dataOut = HDSPM_midiDataOut2;
2093                 hdspm->midi[2].statusOut = HDSPM_midiStatusOut2;
2094                 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
2095                 hdspm->midi[2].irq = HDSPM_midi2IRQPending;
2096         } else if (2 == id) {
2097                 /* TCO MTC, read only */
2098                 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
2099                 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
2100                 hdspm->midi[2].dataOut = -1;
2101                 hdspm->midi[2].statusOut = -1;
2102                 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
2103                 hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES;
2104         } else if (3 == id) {
2105                 /* TCO MTC on HDSPe MADI */
2106                 hdspm->midi[3].dataIn = HDSPM_midiDataIn3;
2107                 hdspm->midi[3].statusIn = HDSPM_midiStatusIn3;
2108                 hdspm->midi[3].dataOut = -1;
2109                 hdspm->midi[3].statusOut = -1;
2110                 hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable;
2111                 hdspm->midi[3].irq = HDSPM_midi3IRQPending;
2112         }
2113 
2114         if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) ||
2115                                         (MADIface == hdspm->io_type)))) {
2116                 if ((id == 0) && (MADIface == hdspm->io_type)) {
2117                         snprintf(buf, sizeof(buf), "%s MIDIoverMADI",
2118                                  card->shortname);
2119                 } else if ((id == 2) && (MADI == hdspm->io_type)) {
2120                         snprintf(buf, sizeof(buf), "%s MIDIoverMADI",
2121                                  card->shortname);
2122                 } else {
2123                         snprintf(buf, sizeof(buf), "%s MIDI %d",
2124                                  card->shortname, id+1);
2125                 }
2126                 err = snd_rawmidi_new(card, buf, id, 1, 1,
2127                                 &hdspm->midi[id].rmidi);
2128                 if (err < 0)
2129                         return err;
2130 
2131                 snprintf(hdspm->midi[id].rmidi->name,
2132                          sizeof(hdspm->midi[id].rmidi->name),
2133                          "%s MIDI %d", card->id, id+1);
2134                 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
2135 
2136                 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2137                                 SNDRV_RAWMIDI_STREAM_OUTPUT,
2138                                 &snd_hdspm_midi_output);
2139                 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2140                                 SNDRV_RAWMIDI_STREAM_INPUT,
2141                                 &snd_hdspm_midi_input);
2142 
2143                 hdspm->midi[id].rmidi->info_flags |=
2144                         SNDRV_RAWMIDI_INFO_OUTPUT |
2145                         SNDRV_RAWMIDI_INFO_INPUT |
2146                         SNDRV_RAWMIDI_INFO_DUPLEX;
2147         } else {
2148                 /* TCO MTC, read only */
2149                 snprintf(buf, sizeof(buf), "%s MTC %d",
2150                          card->shortname, id+1);
2151                 err = snd_rawmidi_new(card, buf, id, 1, 1,
2152                                 &hdspm->midi[id].rmidi);
2153                 if (err < 0)
2154                         return err;
2155 
2156                 snprintf(hdspm->midi[id].rmidi->name,
2157                          sizeof(hdspm->midi[id].rmidi->name),
2158                          "%s MTC %d", card->id, id+1);
2159                 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
2160 
2161                 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2162                                 SNDRV_RAWMIDI_STREAM_INPUT,
2163                                 &snd_hdspm_midi_input);
2164 
2165                 hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT;
2166         }
2167 
2168         return 0;
2169 }
2170 
2171 
2172 static void hdspm_midi_work(struct work_struct *work)
2173 {
2174         struct hdspm *hdspm = container_of(work, struct hdspm, midi_work);
2175         int i = 0;
2176 
2177         while (i < hdspm->midiPorts) {
2178                 if (hdspm->midi[i].pending)
2179                         snd_hdspm_midi_input_read(&hdspm->midi[i]);
2180 
2181                 i++;
2182         }
2183 }
2184 
2185 
2186 /*-----------------------------------------------------------------------------
2187   Status Interface
2188   ----------------------------------------------------------------------------*/
2189 
2190 /* get the system sample rate which is set */
2191 
2192 
2193 static inline int hdspm_get_pll_freq(struct hdspm *hdspm)
2194 {
2195         unsigned int period, rate;
2196 
2197         period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
2198         rate = hdspm_calc_dds_value(hdspm, period);
2199 
2200         return rate;
2201 }
2202 
2203 /*
2204  * Calculate the real sample rate from the
2205  * current DDS value.
2206  */
2207 static int hdspm_get_system_sample_rate(struct hdspm *hdspm)
2208 {
2209         unsigned int rate;
2210 
2211         rate = hdspm_get_pll_freq(hdspm);
2212 
2213         if (rate > 207000) {
2214                 /* Unreasonable high sample rate as seen on PCI MADI cards. */
2215                 if (0 == hdspm_system_clock_mode(hdspm)) {
2216                         /* master mode, return internal sample rate */
2217                         rate = hdspm->system_sample_rate;
2218                 } else {
2219                         /* slave mode, return external sample rate */
2220                         rate = hdspm_external_sample_rate(hdspm);
2221                         if (!rate)
2222                                 rate = hdspm->system_sample_rate;
2223                 }
2224         }
2225 
2226         return rate;
2227 }
2228 
2229 
2230 #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \
2231 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2232         .name = xname, \
2233         .index = xindex, \
2234         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2235                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2236         .info = snd_hdspm_info_system_sample_rate, \
2237         .put = snd_hdspm_put_system_sample_rate, \
2238         .get = snd_hdspm_get_system_sample_rate \
2239 }
2240 
2241 static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol,
2242                                              struct snd_ctl_elem_info *uinfo)
2243 {
2244         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2245         uinfo->count = 1;
2246         uinfo->value.integer.min = 27000;
2247         uinfo->value.integer.max = 207000;
2248         uinfo->value.integer.step = 1;
2249         return 0;
2250 }
2251 
2252 
2253 static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol,
2254                                             struct snd_ctl_elem_value *
2255                                             ucontrol)
2256 {
2257         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2258 
2259         ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm);
2260         return 0;
2261 }
2262 
2263 static int snd_hdspm_put_system_sample_rate(struct snd_kcontrol *kcontrol,
2264                                             struct snd_ctl_elem_value *
2265                                             ucontrol)
2266 {
2267         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2268         int rate = ucontrol->value.integer.value[0];
2269 
2270         if (rate < 27000 || rate > 207000)
2271                 return -EINVAL;
2272         hdspm_set_dds_value(hdspm, ucontrol->value.integer.value[0]);
2273         return 0;
2274 }
2275 
2276 
2277 /*
2278  * Returns the WordClock sample rate class for the given card.
2279  */
2280 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm)
2281 {
2282         int status;
2283 
2284         switch (hdspm->io_type) {
2285         case RayDAT:
2286         case AIO:
2287                 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2288                 return (status >> 16) & 0xF;
2289         case AES32:
2290                 status = hdspm_read(hdspm, HDSPM_statusRegister);
2291                 return (status >> HDSPM_AES32_wcFreq_bit) & 0xF;
2292         default:
2293                 break;
2294         }
2295 
2296 
2297         return 0;
2298 }
2299 
2300 
2301 /*
2302  * Returns the TCO sample rate class for the given card.
2303  */
2304 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm)
2305 {
2306         int status;
2307 
2308         if (hdspm->tco) {
2309                 switch (hdspm->io_type) {
2310                 case RayDAT:
2311                 case AIO:
2312                         status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2313                         return (status >> 20) & 0xF;
2314                 case AES32:
2315                         status = hdspm_read(hdspm, HDSPM_statusRegister);
2316                         return (status >> 1) & 0xF;
2317                 default:
2318                         break;
2319                 }
2320         }
2321 
2322         return 0;
2323 }
2324 
2325 
2326 /*
2327  * Returns the SYNC_IN sample rate class for the given card.
2328  */
2329 static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm)
2330 {
2331         int status;
2332 
2333         if (hdspm->tco) {
2334                 switch (hdspm->io_type) {
2335                 case RayDAT:
2336                 case AIO:
2337                         status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2338                         return (status >> 12) & 0xF;
2339                 default:
2340                         break;
2341                 }
2342         }
2343 
2344         return 0;
2345 }
2346 
2347 /*
2348  * Returns the AES sample rate class for the given card.
2349  */
2350 static int hdspm_get_aes_sample_rate(struct hdspm *hdspm, int index)
2351 {
2352         int timecode;
2353 
2354         switch (hdspm->io_type) {
2355         case AES32:
2356                 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
2357                 return (timecode >> (4*index)) & 0xF;
2358         default:
2359                 break;
2360         }
2361         return 0;
2362 }
2363 
2364 /*
2365  * Returns the sample rate class for input source <idx> for
2366  * 'new style' cards like the AIO and RayDAT.
2367  */
2368 static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx)
2369 {
2370         int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2371 
2372         return (status >> (idx*4)) & 0xF;
2373 }
2374 
2375 #define ENUMERATED_CTL_INFO(info, texts) \
2376         snd_ctl_enum_info(info, 1, ARRAY_SIZE(texts), texts)
2377 
2378 
2379 /* Helper function to query the external sample rate and return the
2380  * corresponding enum to be returned to userspace.
2381  */
2382 static int hdspm_external_rate_to_enum(struct hdspm *hdspm)
2383 {
2384         int rate = hdspm_external_sample_rate(hdspm);
2385         int i, selected_rate = 0;
2386         for (i = 1; i < 10; i++)
2387                 if (HDSPM_bit2freq(i) == rate) {
2388                         selected_rate = i;
2389                         break;
2390                 }
2391         return selected_rate;
2392 }
2393 
2394 
2395 #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
2396 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2397         .name = xname, \
2398         .private_value = xindex, \
2399         .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2400         .info = snd_hdspm_info_autosync_sample_rate, \
2401         .get = snd_hdspm_get_autosync_sample_rate \
2402 }
2403 
2404 
2405 static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2406                                                struct snd_ctl_elem_info *uinfo)
2407 {
2408         ENUMERATED_CTL_INFO(uinfo, texts_freq);
2409         return 0;
2410 }
2411 
2412 
2413 static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2414                                               struct snd_ctl_elem_value *
2415                                               ucontrol)
2416 {
2417         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2418 
2419         switch (hdspm->io_type) {
2420         case RayDAT:
2421                 switch (kcontrol->private_value) {
2422                 case 0:
2423                         ucontrol->value.enumerated.item[0] =
2424                                 hdspm_get_wc_sample_rate(hdspm);
2425                         break;
2426                 case 7:
2427                         ucontrol->value.enumerated.item[0] =
2428                                 hdspm_get_tco_sample_rate(hdspm);
2429                         break;
2430                 case 8:
2431                         ucontrol->value.enumerated.item[0] =
2432                                 hdspm_get_sync_in_sample_rate(hdspm);
2433                         break;
2434                 default:
2435                         ucontrol->value.enumerated.item[0] =
2436                                 hdspm_get_s1_sample_rate(hdspm,
2437                                                 kcontrol->private_value-1);
2438                 }
2439                 break;
2440 
2441         case AIO:
2442                 switch (kcontrol->private_value) {
2443                 case 0: /* WC */
2444                         ucontrol->value.enumerated.item[0] =
2445                                 hdspm_get_wc_sample_rate(hdspm);
2446                         break;
2447                 case 4: /* TCO */
2448                         ucontrol->value.enumerated.item[0] =
2449                                 hdspm_get_tco_sample_rate(hdspm);
2450                         break;
2451                 case 5: /* SYNC_IN */
2452                         ucontrol->value.enumerated.item[0] =
2453                                 hdspm_get_sync_in_sample_rate(hdspm);
2454                         break;
2455                 default:
2456                         ucontrol->value.enumerated.item[0] =
2457                                 hdspm_get_s1_sample_rate(hdspm,
2458                                                 kcontrol->private_value-1);
2459                 }
2460                 break;
2461 
2462         case AES32:
2463 
2464                 switch (kcontrol->private_value) {
2465                 case 0: /* WC */
2466                         ucontrol->value.enumerated.item[0] =
2467                                 hdspm_get_wc_sample_rate(hdspm);
2468                         break;
2469                 case 9: /* TCO */
2470                         ucontrol->value.enumerated.item[0] =
2471                                 hdspm_get_tco_sample_rate(hdspm);
2472                         break;
2473                 case 10: /* SYNC_IN */
2474                         ucontrol->value.enumerated.item[0] =
2475                                 hdspm_get_sync_in_sample_rate(hdspm);
2476                         break;
2477                 case 11: /* External Rate */
2478                         ucontrol->value.enumerated.item[0] =
2479                                 hdspm_external_rate_to_enum(hdspm);
2480                         break;
2481                 default: /* AES1 to AES8 */
2482                         ucontrol->value.enumerated.item[0] =
2483                                 hdspm_get_aes_sample_rate(hdspm,
2484                                                 kcontrol->private_value -
2485                                                 HDSPM_AES32_AUTOSYNC_FROM_AES1);
2486                         break;
2487                 }
2488                 break;
2489 
2490         case MADI:
2491         case MADIface:
2492                 ucontrol->value.enumerated.item[0] =
2493                         hdspm_external_rate_to_enum(hdspm);
2494                 break;
2495         default:
2496                 break;
2497         }
2498 
2499         return 0;
2500 }
2501 
2502 
2503 #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \
2504 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2505         .name = xname, \
2506         .index = xindex, \
2507         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2508                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2509         .info = snd_hdspm_info_system_clock_mode, \
2510         .get = snd_hdspm_get_system_clock_mode, \
2511         .put = snd_hdspm_put_system_clock_mode, \
2512 }
2513 
2514 
2515 /*
2516  * Returns the system clock mode for the given card.
2517  * @returns 0 - master, 1 - slave
2518  */
2519 static int hdspm_system_clock_mode(struct hdspm *hdspm)
2520 {
2521         switch (hdspm->io_type) {
2522         case AIO:
2523         case RayDAT:
2524                 if (hdspm->settings_register & HDSPM_c0Master)
2525                         return 0;
2526                 break;
2527 
2528         default:
2529                 if (hdspm->control_register & HDSPM_ClockModeMaster)
2530                         return 0;
2531         }
2532 
2533         return 1;
2534 }
2535 
2536 
2537 /*
2538  * Sets the system clock mode.
2539  * @param mode 0 - master, 1 - slave
2540  */
2541 static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode)
2542 {
2543         hdspm_set_toggle_setting(hdspm,
2544                         (hdspm_is_raydat_or_aio(hdspm)) ?
2545                         HDSPM_c0Master : HDSPM_ClockModeMaster,
2546                         (0 == mode));
2547 }
2548 
2549 
2550 static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol,
2551                                             struct snd_ctl_elem_info *uinfo)
2552 {
2553         static const char *const texts[] = { "Master", "AutoSync" };
2554         ENUMERATED_CTL_INFO(uinfo, texts);
2555         return 0;
2556 }
2557 
2558 static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol,
2559                                            struct snd_ctl_elem_value *ucontrol)
2560 {
2561         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2562 
2563         ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm);
2564         return 0;
2565 }
2566 
2567 static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol,
2568                                            struct snd_ctl_elem_value *ucontrol)
2569 {
2570         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2571         int val;
2572 
2573         if (!snd_hdspm_use_is_exclusive(hdspm))
2574                 return -EBUSY;
2575 
2576         val = ucontrol->value.enumerated.item[0];
2577         if (val < 0)
2578                 val = 0;
2579         else if (val > 1)
2580                 val = 1;
2581 
2582         hdspm_set_system_clock_mode(hdspm, val);
2583 
2584         return 0;
2585 }
2586 
2587 
2588 #define HDSPM_INTERNAL_CLOCK(xname, xindex) \
2589 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2590         .name = xname, \
2591         .index = xindex, \
2592         .info = snd_hdspm_info_clock_source, \
2593         .get = snd_hdspm_get_clock_source, \
2594         .put = snd_hdspm_put_clock_source \
2595 }
2596 
2597 
2598 static int hdspm_clock_source(struct hdspm * hdspm)
2599 {
2600         switch (hdspm->system_sample_rate) {
2601         case 32000: return 0;
2602         case 44100: return 1;
2603         case 48000: return 2;
2604         case 64000: return 3;
2605         case 88200: return 4;
2606         case 96000: return 5;
2607         case 128000: return 6;
2608         case 176400: return 7;
2609         case 192000: return 8;
2610         }
2611 
2612         return -1;
2613 }
2614 
2615 static int hdspm_set_clock_source(struct hdspm * hdspm, int mode)
2616 {
2617         int rate;
2618         switch (mode) {
2619         case 0:
2620                 rate = 32000; break;
2621         case 1:
2622                 rate = 44100; break;
2623         case 2:
2624                 rate = 48000; break;
2625         case 3:
2626                 rate = 64000; break;
2627         case 4:
2628                 rate = 88200; break;
2629         case 5:
2630                 rate = 96000; break;
2631         case 6:
2632                 rate = 128000; break;
2633         case 7:
2634                 rate = 176400; break;
2635         case 8:
2636                 rate = 192000; break;
2637         default:
2638                 rate = 48000;
2639         }
2640         hdspm_set_rate(hdspm, rate, 1);
2641         return 0;
2642 }
2643 
2644 static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol,
2645                                        struct snd_ctl_elem_info *uinfo)
2646 {
2647         return snd_ctl_enum_info(uinfo, 1, 9, texts_freq + 1);
2648 }
2649 
2650 static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol,
2651                                       struct snd_ctl_elem_value *ucontrol)
2652 {
2653         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2654 
2655         ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm);
2656         return 0;
2657 }
2658 
2659 static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol,
2660                                       struct snd_ctl_elem_value *ucontrol)
2661 {
2662         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2663         int change;
2664         int val;
2665 
2666         if (!snd_hdspm_use_is_exclusive(hdspm))
2667                 return -EBUSY;
2668         val = ucontrol->value.enumerated.item[0];
2669         if (val < 0)
2670                 val = 0;
2671         if (val > 9)
2672                 val = 9;
2673         spin_lock_irq(&hdspm->lock);
2674         if (val != hdspm_clock_source(hdspm))
2675                 change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0;
2676         else
2677                 change = 0;
2678         spin_unlock_irq(&hdspm->lock);
2679         return change;
2680 }
2681 
2682 
2683 #define HDSPM_PREF_SYNC_REF(xname, xindex) \
2684 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2685         .name = xname, \
2686         .index = xindex, \
2687         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2688                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2689         .info = snd_hdspm_info_pref_sync_ref, \
2690         .get = snd_hdspm_get_pref_sync_ref, \
2691         .put = snd_hdspm_put_pref_sync_ref \
2692 }
2693 
2694 
2695 /*
2696  * Returns the current preferred sync reference setting.
2697  * The semantics of the return value are depending on the
2698  * card, please see the comments for clarification.
2699  */
2700 static int hdspm_pref_sync_ref(struct hdspm * hdspm)
2701 {
2702         switch (hdspm->io_type) {
2703         case AES32:
2704                 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2705                 case 0: return 0;  /* WC */
2706                 case HDSPM_SyncRef0: return 1; /* AES 1 */
2707                 case HDSPM_SyncRef1: return 2; /* AES 2 */
2708                 case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */
2709                 case HDSPM_SyncRef2: return 4; /* AES 4 */
2710                 case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */
2711                 case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */
2712                 case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0:
2713                                                     return 7; /* AES 7 */
2714                 case HDSPM_SyncRef3: return 8; /* AES 8 */
2715                 case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */
2716                 }
2717                 break;
2718 
2719         case MADI:
2720         case MADIface:
2721                 if (hdspm->tco) {
2722                         switch (hdspm->control_register & HDSPM_SyncRefMask) {
2723                         case 0: return 0;  /* WC */
2724                         case HDSPM_SyncRef0: return 1;  /* MADI */
2725                         case HDSPM_SyncRef1: return 2;  /* TCO */
2726                         case HDSPM_SyncRef1+HDSPM_SyncRef0:
2727                                              return 3;  /* SYNC_IN */
2728                         }
2729                 } else {
2730                         switch (hdspm->control_register & HDSPM_SyncRefMask) {
2731                         case 0: return 0;  /* WC */
2732                         case HDSPM_SyncRef0: return 1;  /* MADI */
2733                         case HDSPM_SyncRef1+HDSPM_SyncRef0:
2734                                              return 2;  /* SYNC_IN */
2735                         }
2736                 }
2737                 break;
2738 
2739         case RayDAT:
2740                 if (hdspm->tco) {
2741                         switch ((hdspm->settings_register &
2742                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2743                         case 0: return 0;  /* WC */
2744                         case 3: return 1;  /* ADAT 1 */
2745                         case 4: return 2;  /* ADAT 2 */
2746                         case 5: return 3;  /* ADAT 3 */
2747                         case 6: return 4;  /* ADAT 4 */
2748                         case 1: return 5;  /* AES */
2749                         case 2: return 6;  /* SPDIF */
2750                         case 9: return 7;  /* TCO */
2751                         case 10: return 8; /* SYNC_IN */
2752                         }
2753                 } else {
2754                         switch ((hdspm->settings_register &
2755                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2756                         case 0: return 0;  /* WC */
2757                         case 3: return 1;  /* ADAT 1 */
2758                         case 4: return 2;  /* ADAT 2 */
2759                         case 5: return 3;  /* ADAT 3 */
2760                         case 6: return 4;  /* ADAT 4 */
2761                         case 1: return 5;  /* AES */
2762                         case 2: return 6;  /* SPDIF */
2763                         case 10: return 7; /* SYNC_IN */
2764                         }
2765                 }
2766 
2767                 break;
2768 
2769         case AIO:
2770                 if (hdspm->tco) {
2771                         switch ((hdspm->settings_register &
2772                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2773                         case 0: return 0;  /* WC */
2774                         case 3: return 1;  /* ADAT */
2775                         case 1: return 2;  /* AES */
2776                         case 2: return 3;  /* SPDIF */
2777                         case 9: return 4;  /* TCO */
2778                         case 10: return 5; /* SYNC_IN */
2779                         }
2780                 } else {
2781                         switch ((hdspm->settings_register &
2782                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2783                         case 0: return 0;  /* WC */
2784                         case 3: return 1;  /* ADAT */
2785                         case 1: return 2;  /* AES */
2786                         case 2: return 3;  /* SPDIF */
2787                         case 10: return 4; /* SYNC_IN */
2788                         }
2789                 }
2790 
2791                 break;
2792         }
2793 
2794         return -1;
2795 }
2796 
2797 
2798 /*
2799  * Set the preferred sync reference to <pref>. The semantics
2800  * of <pref> are depending on the card type, see the comments
2801  * for clarification.
2802  */
2803 static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref)
2804 {
2805         int p = 0;
2806 
2807         switch (hdspm->io_type) {
2808         case AES32:
2809                 hdspm->control_register &= ~HDSPM_SyncRefMask;
2810                 switch (pref) {
2811                 case 0: /* WC  */
2812                         break;
2813                 case 1: /* AES 1 */
2814                         hdspm->control_register |= HDSPM_SyncRef0;
2815                         break;
2816                 case 2: /* AES 2 */
2817                         hdspm->control_register |= HDSPM_SyncRef1;
2818                         break;
2819                 case 3: /* AES 3 */
2820                         hdspm->control_register |=
2821                                 HDSPM_SyncRef1+HDSPM_SyncRef0;
2822                         break;
2823                 case 4: /* AES 4 */
2824                         hdspm->control_register |= HDSPM_SyncRef2;
2825                         break;
2826                 case 5: /* AES 5 */
2827                         hdspm->control_register |=
2828                                 HDSPM_SyncRef2+HDSPM_SyncRef0;
2829                         break;
2830                 case 6: /* AES 6 */
2831                         hdspm->control_register |=
2832                                 HDSPM_SyncRef2+HDSPM_SyncRef1;
2833                         break;
2834                 case 7: /* AES 7 */
2835                         hdspm->control_register |=
2836                                 HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0;
2837                         break;
2838                 case 8: /* AES 8 */
2839                         hdspm->control_register |= HDSPM_SyncRef3;
2840                         break;
2841                 case 9: /* TCO */
2842                         hdspm->control_register |=
2843                                 HDSPM_SyncRef3+HDSPM_SyncRef0;
2844                         break;
2845                 default:
2846                         return -1;
2847                 }
2848 
2849                 break;
2850 
2851         case MADI:
2852         case MADIface:
2853                 hdspm->control_register &= ~HDSPM_SyncRefMask;
2854                 if (hdspm->tco) {
2855                         switch (pref) {
2856                         case 0: /* WC */
2857                                 break;
2858                         case 1: /* MADI */
2859                                 hdspm->control_register |= HDSPM_SyncRef0;
2860                                 break;
2861                         case 2: /* TCO */
2862                                 hdspm->control_register |= HDSPM_SyncRef1;
2863                                 break;
2864                         case 3: /* SYNC_IN */
2865                                 hdspm->control_register |=
2866                                         HDSPM_SyncRef0+HDSPM_SyncRef1;
2867                                 break;
2868                         default:
2869                                 return -1;
2870                         }
2871                 } else {
2872                         switch (pref) {
2873                         case 0: /* WC */
2874                                 break;
2875                         case 1: /* MADI */
2876                                 hdspm->control_register |= HDSPM_SyncRef0;
2877                                 break;
2878                         case 2: /* SYNC_IN */
2879                                 hdspm->control_register |=
2880                                         HDSPM_SyncRef0+HDSPM_SyncRef1;
2881                                 break;
2882                         default:
2883                                 return -1;
2884                         }
2885                 }
2886 
2887                 break;
2888 
2889         case RayDAT:
2890                 if (hdspm->tco) {
2891                         switch (pref) {
2892                         case 0: p = 0; break;  /* WC */
2893                         case 1: p = 3; break;  /* ADAT 1 */
2894                         case 2: p = 4; break;  /* ADAT 2 */
2895                         case 3: p = 5; break;  /* ADAT 3 */
2896                         case 4: p = 6; break;  /* ADAT 4 */
2897                         case 5: p = 1; break;  /* AES */
2898                         case 6: p = 2; break;  /* SPDIF */
2899                         case 7: p = 9; break;  /* TCO */
2900                         case 8: p = 10; break; /* SYNC_IN */
2901                         default: return -1;
2902                         }
2903                 } else {
2904                         switch (pref) {
2905                         case 0: p = 0; break;  /* WC */
2906                         case 1: p = 3; break;  /* ADAT 1 */
2907                         case 2: p = 4; break;  /* ADAT 2 */
2908                         case 3: p = 5; break;  /* ADAT 3 */
2909                         case 4: p = 6; break;  /* ADAT 4 */
2910                         case 5: p = 1; break;  /* AES */
2911                         case 6: p = 2; break;  /* SPDIF */
2912                         case 7: p = 10; break; /* SYNC_IN */
2913                         default: return -1;
2914                         }
2915                 }
2916                 break;
2917 
2918         case AIO:
2919                 if (hdspm->tco) {
2920                         switch (pref) {
2921                         case 0: p = 0; break;  /* WC */
2922                         case 1: p = 3; break;  /* ADAT */
2923                         case 2: p = 1; break;  /* AES */
2924                         case 3: p = 2; break;  /* SPDIF */
2925                         case 4: p = 9; break;  /* TCO */
2926                         case 5: p = 10; break; /* SYNC_IN */
2927                         default: return -1;
2928                         }
2929                 } else {
2930                         switch (pref) {
2931                         case 0: p = 0; break;  /* WC */
2932                         case 1: p = 3; break;  /* ADAT */
2933                         case 2: p = 1; break;  /* AES */
2934                         case 3: p = 2; break;  /* SPDIF */
2935                         case 4: p = 10; break; /* SYNC_IN */
2936                         default: return -1;
2937                         }
2938                 }
2939                 break;
2940         }
2941 
2942         switch (hdspm->io_type) {
2943         case RayDAT:
2944         case AIO:
2945                 hdspm->settings_register &= ~HDSPM_c0_SyncRefMask;
2946                 hdspm->settings_register |= HDSPM_c0_SyncRef0 * p;
2947                 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2948                 break;
2949 
2950         case MADI:
2951         case MADIface:
2952         case AES32:
2953                 hdspm_write(hdspm, HDSPM_controlRegister,
2954                                 hdspm->control_register);
2955         }
2956 
2957         return 0;
2958 }
2959 
2960 
2961 static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol,
2962                                         struct snd_ctl_elem_info *uinfo)
2963 {
2964         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2965 
2966         snd_ctl_enum_info(uinfo, 1, hdspm->texts_autosync_items, hdspm->texts_autosync);
2967 
2968         return 0;
2969 }
2970 
2971 static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol,
2972                                        struct snd_ctl_elem_value *ucontrol)
2973 {
2974         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2975         int psf = hdspm_pref_sync_ref(hdspm);
2976 
2977         if (psf >= 0) {
2978                 ucontrol->value.enumerated.item[0] = psf;
2979                 return 0;
2980         }
2981 
2982         return -1;
2983 }
2984 
2985 static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol,
2986                                        struct snd_ctl_elem_value *ucontrol)
2987 {
2988         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2989         int val, change = 0;
2990 
2991         if (!snd_hdspm_use_is_exclusive(hdspm))
2992                 return -EBUSY;
2993 
2994         val = ucontrol->value.enumerated.item[0];
2995 
2996         if (val < 0)
2997                 val = 0;
2998         else if (val >= hdspm->texts_autosync_items)
2999                 val = hdspm->texts_autosync_items-1;
3000 
3001         spin_lock_irq(&hdspm->lock);
3002         if (val != hdspm_pref_sync_ref(hdspm))
3003                 change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0;
3004 
3005         spin_unlock_irq(&hdspm->lock);
3006         return change;
3007 }
3008 
3009 
3010 #define HDSPM_AUTOSYNC_REF(xname, xindex) \
3011 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3012         .name = xname, \
3013         .index = xindex, \
3014         .access = SNDRV_CTL_ELEM_ACCESS_READ, \
3015         .info = snd_hdspm_info_autosync_ref, \
3016         .get = snd_hdspm_get_autosync_ref, \
3017 }
3018 
3019 static int hdspm_autosync_ref(struct hdspm *hdspm)
3020 {
3021         /* This looks at the autosync selected sync reference */
3022         if (AES32 == hdspm->io_type) {
3023 
3024                 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister);
3025                 unsigned int syncref = (status >> HDSPM_AES32_syncref_bit) & 0xF;
3026                 /* syncref >= HDSPM_AES32_AUTOSYNC_FROM_WORD is always true */
3027                 if (syncref <= HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN) {
3028                         return syncref;
3029                 }
3030                 return HDSPM_AES32_AUTOSYNC_FROM_NONE;
3031 
3032         } else if (MADI == hdspm->io_type) {
3033 
3034                 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3035                 switch (status2 & HDSPM_SelSyncRefMask) {
3036                 case HDSPM_SelSyncRef_WORD:
3037                         return HDSPM_AUTOSYNC_FROM_WORD;
3038                 case HDSPM_SelSyncRef_MADI:
3039                         return HDSPM_AUTOSYNC_FROM_MADI;
3040                 case HDSPM_SelSyncRef_TCO:
3041                         return HDSPM_AUTOSYNC_FROM_TCO;
3042                 case HDSPM_SelSyncRef_SyncIn:
3043                         return HDSPM_AUTOSYNC_FROM_SYNC_IN;
3044                 case HDSPM_SelSyncRef_NVALID:
3045                         return HDSPM_AUTOSYNC_FROM_NONE;
3046                 default:
3047                         return HDSPM_AUTOSYNC_FROM_NONE;
3048                 }
3049 
3050         }
3051         return 0;
3052 }
3053 
3054 
3055 static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol,
3056                                        struct snd_ctl_elem_info *uinfo)
3057 {
3058         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3059 
3060         if (AES32 == hdspm->io_type) {
3061                 static const char *const texts[] = { "WordClock", "AES1", "AES2", "AES3",
3062                         "AES4", "AES5", "AES6", "AES7", "AES8", "TCO", "Sync In", "None"};
3063 
3064                 ENUMERATED_CTL_INFO(uinfo, texts);
3065         } else if (MADI == hdspm->io_type) {
3066                 static const char *const texts[] = {"Word Clock", "MADI", "TCO",
3067                         "Sync In", "None" };
3068 
3069                 ENUMERATED_CTL_INFO(uinfo, texts);
3070         }
3071         return 0;
3072 }
3073 
3074 static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol,
3075                                       struct snd_ctl_elem_value *ucontrol)
3076 {
3077         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3078 
3079         ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm);
3080         return 0;
3081 }
3082 
3083 
3084 
3085 #define HDSPM_TCO_VIDEO_INPUT_FORMAT(xname, xindex) \
3086 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3087         .name = xname, \
3088         .access = SNDRV_CTL_ELEM_ACCESS_READ |\
3089                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3090         .info = snd_hdspm_info_tco_video_input_format, \
3091         .get = snd_hdspm_get_tco_video_input_format, \
3092 }
3093 
3094 static int snd_hdspm_info_tco_video_input_format(struct snd_kcontrol *kcontrol,
3095                                        struct snd_ctl_elem_info *uinfo)
3096 {
3097         static const char *const texts[] = {"No video", "NTSC", "PAL"};
3098         ENUMERATED_CTL_INFO(uinfo, texts);
3099         return 0;
3100 }
3101 
3102 static int snd_hdspm_get_tco_video_input_format(struct snd_kcontrol *kcontrol,
3103                                       struct snd_ctl_elem_value *ucontrol)
3104 {
3105         u32 status;
3106         int ret = 0;
3107 
3108         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3109         status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3110         switch (status & (HDSPM_TCO1_Video_Input_Format_NTSC |
3111                         HDSPM_TCO1_Video_Input_Format_PAL)) {
3112         case HDSPM_TCO1_Video_Input_Format_NTSC:
3113                 /* ntsc */
3114                 ret = 1;
3115                 break;
3116         case HDSPM_TCO1_Video_Input_Format_PAL:
3117                 /* pal */
3118                 ret = 2;
3119                 break;
3120         default:
3121                 /* no video */
3122                 ret = 0;
3123                 break;
3124         }
3125         ucontrol->value.enumerated.item[0] = ret;
3126         return 0;
3127 }
3128 
3129 
3130 
3131 #define HDSPM_TCO_LTC_FRAMES(xname, xindex) \
3132 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3133         .name = xname, \
3134         .access = SNDRV_CTL_ELEM_ACCESS_READ |\
3135                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3136         .info = snd_hdspm_info_tco_ltc_frames, \
3137         .get = snd_hdspm_get_tco_ltc_frames, \
3138 }
3139 
3140 static int snd_hdspm_info_tco_ltc_frames(struct snd_kcontrol *kcontrol,
3141                                        struct snd_ctl_elem_info *uinfo)
3142 {
3143         static const char *const texts[] = {"No lock", "24 fps", "25 fps", "29.97 fps",
3144                                 "30 fps"};
3145         ENUMERATED_CTL_INFO(uinfo, texts);
3146         return 0;
3147 }
3148 
3149 static int hdspm_tco_ltc_frames(struct hdspm *hdspm)
3150 {
3151         u32 status;
3152         int ret = 0;
3153 
3154         status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3155         if (status & HDSPM_TCO1_LTC_Input_valid) {
3156                 switch (status & (HDSPM_TCO1_LTC_Format_LSB |
3157                                         HDSPM_TCO1_LTC_Format_MSB)) {
3158                 case 0:
3159                         /* 24 fps */
3160                         ret = fps_24;
3161                         break;
3162                 case HDSPM_TCO1_LTC_Format_LSB:
3163                         /* 25 fps */
3164                         ret = fps_25;
3165                         break;
3166                 case HDSPM_TCO1_LTC_Format_MSB:
3167                         /* 29.97 fps */
3168                         ret = fps_2997;
3169                         break;
3170                 default:
3171                         /* 30 fps */
3172                         ret = fps_30;
3173                         break;
3174                 }
3175         }
3176 
3177         return ret;
3178 }
3179 
3180 static int snd_hdspm_get_tco_ltc_frames(struct snd_kcontrol *kcontrol,
3181                                       struct snd_ctl_elem_value *ucontrol)
3182 {
3183         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3184 
3185         ucontrol->value.enumerated.item[0] = hdspm_tco_ltc_frames(hdspm);
3186         return 0;
3187 }
3188 
3189 #define HDSPM_TOGGLE_SETTING(xname, xindex) \
3190 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3191         .name = xname, \
3192         .private_value = xindex, \
3193         .info = snd_hdspm_info_toggle_setting, \
3194         .get = snd_hdspm_get_toggle_setting, \
3195         .put = snd_hdspm_put_toggle_setting \
3196 }
3197 
3198 static int hdspm_toggle_setting(struct hdspm *hdspm, u32 regmask)
3199 {
3200         u32 reg;
3201 
3202         if (hdspm_is_raydat_or_aio(hdspm))
3203                 reg = hdspm->settings_register;
3204         else
3205                 reg = hdspm->control_register;
3206 
3207         return (reg & regmask) ? 1 : 0;
3208 }
3209 
3210 static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out)
3211 {
3212         u32 *reg;
3213         u32 target_reg;
3214 
3215         if (hdspm_is_raydat_or_aio(hdspm)) {
3216                 reg = &(hdspm->settings_register);
3217                 target_reg = HDSPM_WR_SETTINGS;
3218         } else {
3219                 reg = &(hdspm->control_register);
3220                 target_reg = HDSPM_controlRegister;
3221         }
3222 
3223         if (out)
3224                 *reg |= regmask;
3225         else
3226                 *reg &= ~regmask;
3227 
3228         hdspm_write(hdspm, target_reg, *reg);
3229 
3230         return 0;
3231 }
3232 
3233 #define snd_hdspm_info_toggle_setting           snd_ctl_boolean_mono_info
3234 
3235 static int snd_hdspm_get_toggle_setting(struct snd_kcontrol *kcontrol,
3236                                struct snd_ctl_elem_value *ucontrol)
3237 {
3238         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3239         u32 regmask = kcontrol->private_value;
3240 
3241         spin_lock_irq(&hdspm->lock);
3242         ucontrol->value.integer.value[0] = hdspm_toggle_setting(hdspm, regmask);
3243         spin_unlock_irq(&hdspm->lock);
3244         return 0;
3245 }
3246 
3247 static int snd_hdspm_put_toggle_setting(struct snd_kcontrol *kcontrol,
3248                                struct snd_ctl_elem_value *ucontrol)
3249 {
3250         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3251         u32 regmask = kcontrol->private_value;
3252         int change;
3253         unsigned int val;
3254 
3255         if (!snd_hdspm_use_is_exclusive(hdspm))
3256                 return -EBUSY;
3257         val = ucontrol->value.integer.value[0] & 1;
3258         spin_lock_irq(&hdspm->lock);
3259         change = (int) val != hdspm_toggle_setting(hdspm, regmask);
3260         hdspm_set_toggle_setting(hdspm, regmask, val);
3261         spin_unlock_irq(&hdspm->lock);
3262         return change;
3263 }
3264 
3265 #define HDSPM_INPUT_SELECT(xname, xindex) \
3266 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3267         .name = xname, \
3268         .index = xindex, \
3269         .info = snd_hdspm_info_input_select, \
3270         .get = snd_hdspm_get_input_select, \
3271         .put = snd_hdspm_put_input_select \
3272 }
3273 
3274 static int hdspm_input_select(struct hdspm * hdspm)
3275 {
3276         return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0;
3277 }
3278 
3279 static int hdspm_set_input_select(struct hdspm * hdspm, int out)
3280 {
3281         if (out)
3282                 hdspm->control_register |= HDSPM_InputSelect0;
3283         else
3284                 hdspm->control_register &= ~HDSPM_InputSelect0;
3285         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3286 
3287         return 0;
3288 }
3289 
3290 static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol,
3291                                        struct snd_ctl_elem_info *uinfo)
3292 {
3293         static const char *const texts[] = { "optical", "coaxial" };
3294         ENUMERATED_CTL_INFO(uinfo, texts);
3295         return 0;
3296 }
3297 
3298 static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol,
3299                                       struct snd_ctl_elem_value *ucontrol)
3300 {
3301         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3302 
3303         spin_lock_irq(&hdspm->lock);
3304         ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm);
3305         spin_unlock_irq(&hdspm->lock);
3306         return 0;
3307 }
3308 
3309 static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol,
3310                                       struct snd_ctl_elem_value *ucontrol)
3311 {
3312         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3313         int change;
3314         unsigned int val;
3315 
3316         if (!snd_hdspm_use_is_exclusive(hdspm))
3317                 return -EBUSY;
3318         val = ucontrol->value.integer.value[0] & 1;
3319         spin_lock_irq(&hdspm->lock);
3320         change = (int) val != hdspm_input_select(hdspm);
3321         hdspm_set_input_select(hdspm, val);
3322         spin_unlock_irq(&hdspm->lock);
3323         return change;
3324 }
3325 
3326 
3327 #define HDSPM_DS_WIRE(xname, xindex) \
3328 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3329         .name = xname, \
3330         .index = xindex, \
3331         .info = snd_hdspm_info_ds_wire, \
3332         .get = snd_hdspm_get_ds_wire, \
3333         .put = snd_hdspm_put_ds_wire \
3334 }
3335 
3336 static int hdspm_ds_wire(struct hdspm * hdspm)
3337 {
3338         return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0;
3339 }
3340 
3341 static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds)
3342 {
3343         if (ds)
3344                 hdspm->control_register |= HDSPM_DS_DoubleWire;
3345         else
3346                 hdspm->control_register &= ~HDSPM_DS_DoubleWire;
3347         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3348 
3349         return 0;
3350 }
3351 
3352 static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol,
3353                                   struct snd_ctl_elem_info *uinfo)
3354 {
3355         static const char *const texts[] = { "Single", "Double" };
3356         ENUMERATED_CTL_INFO(uinfo, texts);
3357         return 0;
3358 }
3359 
3360 static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol,
3361                                  struct snd_ctl_elem_value *ucontrol)
3362 {
3363         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3364 
3365         spin_lock_irq(&hdspm->lock);
3366         ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm);
3367         spin_unlock_irq(&hdspm->lock);
3368         return 0;
3369 }
3370 
3371 static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol,
3372                                  struct snd_ctl_elem_value *ucontrol)
3373 {
3374         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3375         int change;
3376         unsigned int val;
3377 
3378         if (!snd_hdspm_use_is_exclusive(hdspm))
3379                 return -EBUSY;
3380         val = ucontrol->value.integer.value[0] & 1;
3381         spin_lock_irq(&hdspm->lock);
3382         change = (int) val != hdspm_ds_wire(hdspm);
3383         hdspm_set_ds_wire(hdspm, val);
3384         spin_unlock_irq(&hdspm->lock);
3385         return change;
3386 }
3387 
3388 
3389 #define HDSPM_QS_WIRE(xname, xindex) \
3390 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3391         .name = xname, \
3392         .index = xindex, \
3393         .info = snd_hdspm_info_qs_wire, \
3394         .get = snd_hdspm_get_qs_wire, \
3395         .put = snd_hdspm_put_qs_wire \
3396 }
3397 
3398 static int hdspm_qs_wire(struct hdspm * hdspm)
3399 {
3400         if (hdspm->control_register & HDSPM_QS_DoubleWire)
3401                 return 1;
3402         if (hdspm->control_register & HDSPM_QS_QuadWire)
3403                 return 2;
3404         return 0;
3405 }
3406 
3407 static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode)
3408 {
3409         hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire);
3410         switch (mode) {
3411         case 0:
3412                 break;
3413         case 1:
3414                 hdspm->control_register |= HDSPM_QS_DoubleWire;
3415                 break;
3416         case 2:
3417                 hdspm->control_register |= HDSPM_QS_QuadWire;
3418                 break;
3419         }
3420         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3421 
3422         return 0;
3423 }
3424 
3425 static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol,
3426                                        struct snd_ctl_elem_info *uinfo)
3427 {
3428         static const char *const texts[] = { "Single", "Double", "Quad" };
3429         ENUMERATED_CTL_INFO(uinfo, texts);
3430         return 0;
3431 }
3432 
3433 static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol,
3434                                       struct snd_ctl_elem_value *ucontrol)
3435 {
3436         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3437 
3438         spin_lock_irq(&hdspm->lock);
3439         ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm);
3440         spin_unlock_irq(&hdspm->lock);
3441         return 0;
3442 }
3443 
3444 static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol,
3445                                       struct snd_ctl_elem_value *ucontrol)
3446 {
3447         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3448         int change;
3449         int val;
3450 
3451         if (!snd_hdspm_use_is_exclusive(hdspm))
3452                 return -EBUSY;
3453         val = ucontrol->value.integer.value[0];
3454         if (val < 0)
3455                 val = 0;
3456         if (val > 2)
3457                 val = 2;
3458         spin_lock_irq(&hdspm->lock);
3459         change = val != hdspm_qs_wire(hdspm);
3460         hdspm_set_qs_wire(hdspm, val);
3461         spin_unlock_irq(&hdspm->lock);
3462         return change;
3463 }
3464 
3465 #define HDSPM_CONTROL_TRISTATE(xname, xindex) \
3466 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3467         .name = xname, \
3468         .private_value = xindex, \
3469         .info = snd_hdspm_info_tristate, \
3470         .get = snd_hdspm_get_tristate, \
3471         .put = snd_hdspm_put_tristate \
3472 }
3473 
3474 static int hdspm_tristate(struct hdspm *hdspm, u32 regmask)
3475 {
3476         u32 reg = hdspm->settings_register & (regmask * 3);
3477         return reg / regmask;
3478 }
3479 
3480 static int hdspm_set_tristate(struct hdspm *hdspm, int mode, u32 regmask)
3481 {
3482         hdspm->settings_register &= ~(regmask * 3);
3483         hdspm->settings_register |= (regmask * mode);
3484         hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
3485 
3486         return 0;
3487 }
3488 
3489 static int snd_hdspm_info_tristate(struct snd_kcontrol *kcontrol,
3490                                        struct snd_ctl_elem_info *uinfo)
3491 {
3492         u32 regmask = kcontrol->private_value;
3493 
3494         static const char *const texts_spdif[] = { "Optical", "Coaxial", "Internal" };
3495         static const char *const texts_levels[] = { "Hi Gain", "+4 dBu", "-10 dBV" };
3496 
3497         switch (regmask) {
3498         case HDSPM_c0_Input0:
3499                 ENUMERATED_CTL_INFO(uinfo, texts_spdif);
3500                 break;
3501         default:
3502                 ENUMERATED_CTL_INFO(uinfo, texts_levels);
3503                 break;
3504         }
3505         return 0;
3506 }
3507 
3508 static int snd_hdspm_get_tristate(struct snd_kcontrol *kcontrol,
3509                                       struct snd_ctl_elem_value *ucontrol)
3510 {
3511         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3512         u32 regmask = kcontrol->private_value;
3513 
3514         spin_lock_irq(&hdspm->lock);
3515         ucontrol->value.enumerated.item[0] = hdspm_tristate(hdspm, regmask);
3516         spin_unlock_irq(&hdspm->lock);
3517         return 0;
3518 }
3519 
3520 static int snd_hdspm_put_tristate(struct snd_kcontrol *kcontrol,
3521                                       struct snd_ctl_elem_value *ucontrol)
3522 {
3523         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3524         u32 regmask = kcontrol->private_value;
3525         int change;
3526         int val;
3527 
3528         if (!snd_hdspm_use_is_exclusive(hdspm))
3529                 return -EBUSY;
3530         val = ucontrol->value.integer.value[0];
3531         if (val < 0)
3532                 val = 0;
3533         if (val > 2)
3534                 val = 2;
3535 
3536         spin_lock_irq(&hdspm->lock);
3537         change = val != hdspm_tristate(hdspm, regmask);
3538         hdspm_set_tristate(hdspm, val, regmask);
3539         spin_unlock_irq(&hdspm->lock);
3540         return change;
3541 }
3542 
3543 #define HDSPM_MADI_SPEEDMODE(xname, xindex) \
3544 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3545         .name = xname, \
3546         .index = xindex, \
3547         .info = snd_hdspm_info_madi_speedmode, \
3548         .get = snd_hdspm_get_madi_speedmode, \
3549         .put = snd_hdspm_put_madi_speedmode \
3550 }
3551 
3552 static int hdspm_madi_speedmode(struct hdspm *hdspm)
3553 {
3554         if (hdspm->control_register & HDSPM_QuadSpeed)
3555                 return 2;
3556         if (hdspm->control_register & HDSPM_DoubleSpeed)
3557                 return 1;
3558         return 0;
3559 }
3560 
3561 static int hdspm_set_madi_speedmode(struct hdspm *hdspm, int mode)
3562 {
3563         hdspm->control_register &= ~(HDSPM_DoubleSpeed | HDSPM_QuadSpeed);
3564         switch (mode) {
3565         case 0:
3566                 break;
3567         case 1:
3568                 hdspm->control_register |= HDSPM_DoubleSpeed;
3569                 break;
3570         case 2:
3571                 hdspm->control_register |= HDSPM_QuadSpeed;
3572                 break;
3573         }
3574         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3575 
3576         return 0;
3577 }
3578 
3579 static int snd_hdspm_info_madi_speedmode(struct snd_kcontrol *kcontrol,
3580                                        struct snd_ctl_elem_info *uinfo)
3581 {
3582         static const char *const texts[] = { "Single", "Double", "Quad" };
3583         ENUMERATED_CTL_INFO(uinfo, texts);
3584         return 0;
3585 }
3586 
3587 static int snd_hdspm_get_madi_speedmode(struct snd_kcontrol *kcontrol,
3588                                       struct snd_ctl_elem_value *ucontrol)
3589 {
3590         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3591 
3592         spin_lock_irq(&hdspm->lock);
3593         ucontrol->value.enumerated.item[0] = hdspm_madi_speedmode(hdspm);
3594         spin_unlock_irq(&hdspm->lock);
3595         return 0;
3596 }
3597 
3598 static int snd_hdspm_put_madi_speedmode(struct snd_kcontrol *kcontrol,
3599                                       struct snd_ctl_elem_value *ucontrol)
3600 {
3601         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3602         int change;
3603         int val;
3604 
3605         if (!snd_hdspm_use_is_exclusive(hdspm))
3606                 return -EBUSY;
3607         val = ucontrol->value.integer.value[0];
3608         if (val < 0)
3609                 val = 0;
3610         if (val > 2)
3611                 val = 2;
3612         spin_lock_irq(&hdspm->lock);
3613         change = val != hdspm_madi_speedmode(hdspm);
3614         hdspm_set_madi_speedmode(hdspm, val);
3615         spin_unlock_irq(&hdspm->lock);
3616         return change;
3617 }
3618 
3619 #define HDSPM_MIXER(xname, xindex) \
3620 {       .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3621         .name = xname, \
3622         .index = xindex, \
3623         .device = 0, \
3624         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3625                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3626         .info = snd_hdspm_info_mixer, \
3627         .get = snd_hdspm_get_mixer, \
3628         .put = snd_hdspm_put_mixer \
3629 }
3630 
3631 static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol,
3632                                 struct snd_ctl_elem_info *uinfo)
3633 {
3634         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3635         uinfo->count = 3;
3636         uinfo->value.integer.min = 0;
3637         uinfo->value.integer.max = 65535;
3638         uinfo->value.integer.step = 1;
3639         return 0;
3640 }
3641 
3642 static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol,
3643                                struct snd_ctl_elem_value *ucontrol)
3644 {
3645         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3646         int source;
3647         int destination;
3648 
3649         source = ucontrol->value.integer.value[0];
3650         if (source < 0)
3651                 source = 0;
3652         else if (source >= 2 * HDSPM_MAX_CHANNELS)
3653                 source = 2 * HDSPM_MAX_CHANNELS - 1;
3654 
3655         destination = ucontrol->value.integer.value[1];
3656         if (destination < 0)
3657                 destination = 0;
3658         else if (destination >= HDSPM_MAX_CHANNELS)
3659                 destination = HDSPM_MAX_CHANNELS - 1;
3660 
3661         spin_lock_irq(&hdspm->lock);
3662         if (source >= HDSPM_MAX_CHANNELS)
3663                 ucontrol->value.integer.value[2] =
3664                     hdspm_read_pb_gain(hdspm, destination,
3665                                        source - HDSPM_MAX_CHANNELS);
3666         else
3667                 ucontrol->value.integer.value[2] =
3668                     hdspm_read_in_gain(hdspm, destination, source);
3669 
3670         spin_unlock_irq(&hdspm->lock);
3671 
3672         return 0;
3673 }
3674 
3675 static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol,
3676                                struct snd_ctl_elem_value *ucontrol)
3677 {
3678         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3679         int change;
3680         int source;
3681         int destination;
3682         int gain;
3683 
3684         if (!snd_hdspm_use_is_exclusive(hdspm))
3685                 return -EBUSY;
3686 
3687         source = ucontrol->value.integer.value[0];
3688         destination = ucontrol->value.integer.value[1];
3689 
3690         if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS)
3691                 return -1;
3692         if (destination < 0 || destination >= HDSPM_MAX_CHANNELS)
3693                 return -1;
3694 
3695         gain = ucontrol->value.integer.value[2];
3696 
3697         spin_lock_irq(&hdspm->lock);
3698 
3699         if (source >= HDSPM_MAX_CHANNELS)
3700                 change = gain != hdspm_read_pb_gain(hdspm, destination,
3701                                                     source -
3702                                                     HDSPM_MAX_CHANNELS);
3703         else
3704                 change = gain != hdspm_read_in_gain(hdspm, destination,
3705                                                     source);
3706 
3707         if (change) {
3708                 if (source >= HDSPM_MAX_CHANNELS)
3709                         hdspm_write_pb_gain(hdspm, destination,
3710                                             source - HDSPM_MAX_CHANNELS,
3711                                             gain);
3712                 else
3713                         hdspm_write_in_gain(hdspm, destination, source,
3714                                             gain);
3715         }
3716         spin_unlock_irq(&hdspm->lock);
3717 
3718         return change;
3719 }
3720 
3721 /* The simple mixer control(s) provide gain control for the
3722    basic 1:1 mappings of playback streams to output
3723    streams.
3724 */
3725 
3726 #define HDSPM_PLAYBACK_MIXER \
3727 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3728         .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \
3729                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3730         .info = snd_hdspm_info_playback_mixer, \
3731         .get = snd_hdspm_get_playback_mixer, \
3732         .put = snd_hdspm_put_playback_mixer \
3733 }
3734 
3735 static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol,
3736                                          struct snd_ctl_elem_info *uinfo)
3737 {
3738         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3739         uinfo->count = 1;
3740         uinfo->value.integer.min = 0;
3741         uinfo->value.integer.max = 64;
3742         uinfo->value.integer.step = 1;
3743         return 0;
3744 }
3745 
3746 static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol,
3747                                         struct snd_ctl_elem_value *ucontrol)
3748 {
3749         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3750         int channel;
3751 
3752         channel = ucontrol->id.index - 1;
3753 
3754         if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3755                 return -EINVAL;
3756 
3757         spin_lock_irq(&hdspm->lock);
3758         ucontrol->value.integer.value[0] =
3759           (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN;
3760         spin_unlock_irq(&hdspm->lock);
3761 
3762         return 0;
3763 }
3764 
3765 static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol,
3766                                         struct snd_ctl_elem_value *ucontrol)
3767 {
3768         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3769         int change;
3770         int channel;
3771         int gain;
3772 
3773         if (!snd_hdspm_use_is_exclusive(hdspm))
3774                 return -EBUSY;
3775 
3776         channel = ucontrol->id.index - 1;
3777 
3778         if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3779                 return -EINVAL;
3780 
3781         gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64;
3782 
3783         spin_lock_irq(&hdspm->lock);
3784         change =
3785             gain != hdspm_read_pb_gain(hdspm, channel,
3786                                        channel);
3787         if (change)
3788                 hdspm_write_pb_gain(hdspm, channel, channel,
3789                                     gain);
3790         spin_unlock_irq(&hdspm->lock);
3791         return change;
3792 }
3793 
3794 #define HDSPM_SYNC_CHECK(xname, xindex) \
3795 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3796         .name = xname, \
3797         .private_value = xindex, \
3798         .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3799         .info = snd_hdspm_info_sync_check, \
3800         .get = snd_hdspm_get_sync_check \
3801 }
3802 
3803 #define HDSPM_TCO_LOCK_CHECK(xname, xindex) \
3804 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3805         .name = xname, \
3806         .private_value = xindex, \
3807         .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3808         .info = snd_hdspm_tco_info_lock_check, \
3809         .get = snd_hdspm_get_sync_check \
3810 }
3811 
3812 
3813 
3814 static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol,
3815                                      struct snd_ctl_elem_info *uinfo)
3816 {
3817         static const char *const texts[] = { "No Lock", "Lock", "Sync", "N/A" };
3818         ENUMERATED_CTL_INFO(uinfo, texts);
3819         return 0;
3820 }
3821 
3822 static int snd_hdspm_tco_info_lock_check(struct snd_kcontrol *kcontrol,
3823                                      struct snd_ctl_elem_info *uinfo)
3824 {
3825         static const char *const texts[] = { "No Lock", "Lock" };
3826         ENUMERATED_CTL_INFO(uinfo, texts);
3827         return 0;
3828 }
3829 
3830 static int hdspm_wc_sync_check(struct hdspm *hdspm)
3831 {
3832         int status, status2;
3833 
3834         switch (hdspm->io_type) {
3835         case AES32:
3836                 status = hdspm_read(hdspm, HDSPM_statusRegister);
3837                 if (status & HDSPM_AES32_wcLock) {
3838                         if (status & HDSPM_AES32_wcSync)
3839                                 return 2;
3840                         else
3841                                 return 1;
3842                 }
3843                 return 0;
3844 
3845         case MADI:
3846                 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3847                 if (status2 & HDSPM_wcLock) {
3848                         if (status2 & HDSPM_wcSync)
3849                                 return 2;
3850                         else
3851                                 return 1;
3852                 }
3853                 return 0;
3854 
3855         case RayDAT:
3856         case AIO:
3857                 status = hdspm_read(hdspm, HDSPM_statusRegister);
3858 
3859                 if (status & 0x2000000)
3860                         return 2;
3861                 else if (status & 0x1000000)
3862                         return 1;
3863                 return 0;
3864 
3865         case MADIface:
3866                 break;
3867         }
3868 
3869 
3870         return 3;
3871 }
3872 
3873 
3874 static int hdspm_madi_sync_check(struct hdspm *hdspm)
3875 {
3876         int status = hdspm_read(hdspm, HDSPM_statusRegister);
3877         if (status & HDSPM_madiLock) {
3878                 if (status & HDSPM_madiSync)
3879                         return 2;
3880                 else
3881                         return 1;
3882         }
3883         return 0;
3884 }
3885 
3886 
3887 static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx)
3888 {
3889         int status, lock, sync;
3890 
3891         status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3892 
3893         lock = (status & (0x1<<idx)) ? 1 : 0;
3894         sync = (status & (0x100<<idx)) ? 1 : 0;
3895 
3896         if (lock && sync)
3897                 return 2;
3898         else if (lock)
3899                 return 1;
3900         return 0;
3901 }
3902 
3903 
3904 static int hdspm_sync_in_sync_check(struct hdspm *hdspm)
3905 {
3906         int status, lock = 0, sync = 0;
3907 
3908         switch (hdspm->io_type) {
3909         case RayDAT:
3910         case AIO:
3911                 status = hdspm_read(hdspm, HDSPM_RD_STATUS_3);
3912                 lock = (status & 0x400) ? 1 : 0;
3913                 sync = (status & 0x800) ? 1 : 0;
3914                 break;
3915 
3916         case MADI:
3917                 status = hdspm_read(hdspm, HDSPM_statusRegister);
3918                 lock = (status & HDSPM_syncInLock) ? 1 : 0;
3919                 sync = (status & HDSPM_syncInSync) ? 1 : 0;
3920                 break;
3921 
3922         case AES32:
3923                 status = hdspm_read(hdspm, HDSPM_statusRegister2);
3924                 lock = (status & 0x100000) ? 1 : 0;
3925                 sync = (status & 0x200000) ? 1 : 0;
3926                 break;
3927 
3928         case MADIface:
3929                 break;
3930         }
3931 
3932         if (lock && sync)
3933                 return 2;
3934         else if (lock)
3935                 return 1;
3936 
3937         return 0;
3938 }
3939 
3940 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx)
3941 {
3942         int status2, lock, sync;
3943         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3944 
3945         lock = (status2 & (0x0080 >> idx)) ? 1 : 0;
3946         sync = (status2 & (0x8000 >> idx)) ? 1 : 0;
3947 
3948         if (sync)
3949                 return 2;
3950         else if (lock)
3951                 return 1;
3952         return 0;
3953 }
3954 
3955 static int hdspm_tco_input_check(struct hdspm *hdspm, u32 mask)
3956 {
3957         u32 status;
3958         status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3959 
3960         return (status & mask) ? 1 : 0;
3961 }
3962 
3963 
3964 static int hdspm_tco_sync_check(struct hdspm *hdspm)
3965 {
3966         int status;
3967 
3968         if (hdspm->tco) {
3969                 switch (hdspm->io_type) {
3970                 case MADI:
3971                         status = hdspm_read(hdspm, HDSPM_statusRegister);
3972                         if (status & HDSPM_tcoLockMadi) {
3973                                 if (status & HDSPM_tcoSync)
3974                                         return 2;
3975                                 else
3976                                         return 1;
3977                         }
3978                         return 0;
3979                 case AES32:
3980                         status = hdspm_read(hdspm, HDSPM_statusRegister);
3981                         if (status & HDSPM_tcoLockAes) {
3982                                 if (status & HDSPM_tcoSync)
3983                                         return 2;
3984                                 else
3985                                         return 1;
3986                         }
3987                         return 0;
3988                 case RayDAT:
3989                 case AIO:
3990                         status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3991 
3992                         if (status & 0x8000000)
3993                                 return 2; /* Sync */
3994                         if (status & 0x4000000)
3995                                 return 1; /* Lock */
3996                         return 0; /* No signal */
3997 
3998                 default:
3999                         break;
4000                 }
4001         }
4002 
4003         return 3; /* N/A */
4004 }
4005 
4006 
4007 static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol,
4008                                     struct snd_ctl_elem_value *ucontrol)
4009 {
4010         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4011         int val = -1;
4012 
4013         switch (hdspm->io_type) {
4014         case RayDAT:
4015                 switch (kcontrol->private_value) {
4016                 case 0: /* WC */
4017                         val = hdspm_wc_sync_check(hdspm); break;
4018                 case 7: /* TCO */
4019                         val = hdspm_tco_sync_check(hdspm); break;
4020                 case 8: /* SYNC IN */
4021                         val = hdspm_sync_in_sync_check(hdspm); break;
4022                 default:
4023                         val = hdspm_s1_sync_check(hdspm,
4024                                         kcontrol->private_value-1);
4025                 }
4026                 break;
4027 
4028         case AIO:
4029                 switch (kcontrol->private_value) {
4030                 case 0: /* WC */
4031                         val = hdspm_wc_sync_check(hdspm); break;
4032                 case 4: /* TCO */
4033                         val = hdspm_tco_sync_check(hdspm); break;
4034                 case 5: /* SYNC IN */
4035                         val = hdspm_sync_in_sync_check(hdspm); break;
4036                 default:
4037                         val = hdspm_s1_sync_check(hdspm,
4038                                         kcontrol->private_value-1);
4039                 }
4040                 break;
4041 
4042         case MADI:
4043                 switch (kcontrol->private_value) {
4044                 case 0: /* WC */
4045                         val = hdspm_wc_sync_check(hdspm); break;
4046                 case 1: /* MADI */
4047                         val = hdspm_madi_sync_check(hdspm); break;
4048                 case 2: /* TCO */
4049                         val = hdspm_tco_sync_check(hdspm); break;
4050                 case 3: /* SYNC_IN */
4051                         val = hdspm_sync_in_sync_check(hdspm); break;
4052                 }
4053                 break;
4054 
4055         case MADIface:
4056                 val = hdspm_madi_sync_check(hdspm); /* MADI */
4057                 break;
4058 
4059         case AES32:
4060                 switch (kcontrol->private_value) {
4061                 case 0: /* WC */
4062                         val = hdspm_wc_sync_check(hdspm); break;
4063                 case 9: /* TCO */
4064                         val = hdspm_tco_sync_check(hdspm); break;
4065                 case 10 /* SYNC IN */:
4066                         val = hdspm_sync_in_sync_check(hdspm); break;
4067                 default: /* AES1 to AES8 */
4068                          val = hdspm_aes_sync_check(hdspm,
4069                                          kcontrol->private_value-1);
4070                 }
4071                 break;
4072 
4073         }
4074 
4075         if (hdspm->tco) {
4076                 switch (kcontrol->private_value) {
4077                 case 11:
4078                         /* Check TCO for lock state of its current input */
4079                         val = hdspm_tco_input_check(hdspm, HDSPM_TCO1_TCO_lock);
4080                         break;
4081                 case 12:
4082                         /* Check TCO for valid time code on LTC input. */
4083                         val = hdspm_tco_input_check(hdspm,
4084                                 HDSPM_TCO1_LTC_Input_valid);
4085                         break;
4086                 default:
4087                         break;
4088                 }
4089         }
4090 
4091         if (-1 == val)
4092                 val = 3;
4093 
4094         ucontrol->value.enumerated.item[0] = val;
4095         return 0;
4096 }
4097 
4098 
4099 
4100 /*
4101  * TCO controls
4102  */
4103 static void hdspm_tco_write(struct hdspm *hdspm)
4104 {
4105         unsigned int tc[4] = { 0, 0, 0, 0};
4106 
4107         switch (hdspm->tco->input) {
4108         case 0:
4109                 tc[2] |= HDSPM_TCO2_set_input_MSB;
4110                 break;
4111         case 1:
4112                 tc[2] |= HDSPM_TCO2_set_input_LSB;
4113                 break;
4114         default:
4115                 break;
4116         }
4117 
4118         switch (hdspm->tco->framerate) {
4119         case 1:
4120                 tc[1] |= HDSPM_TCO1_LTC_Format_LSB;
4121                 break;
4122         case 2:
4123                 tc[1] |= HDSPM_TCO1_LTC_Format_MSB;
4124                 break;
4125         case 3:
4126                 tc[1] |= HDSPM_TCO1_LTC_Format_MSB +
4127                         HDSPM_TCO1_set_drop_frame_flag;
4128                 break;
4129         case 4:
4130                 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
4131                         HDSPM_TCO1_LTC_Format_MSB;
4132                 break;
4133         case 5:
4134                 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
4135                         HDSPM_TCO1_LTC_Format_MSB +
4136                         HDSPM_TCO1_set_drop_frame_flag;
4137                 break;
4138         default:
4139                 break;
4140         }
4141 
4142         switch (hdspm->tco->wordclock) {
4143         case 1:
4144                 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB;
4145                 break;
4146         case 2:
4147                 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB;
4148                 break;
4149         default:
4150                 break;
4151         }
4152 
4153         switch (hdspm->tco->samplerate) {
4154         case 1:
4155                 tc[2] |= HDSPM_TCO2_set_freq;
4156                 break;
4157         case 2:
4158                 tc[2] |= HDSPM_TCO2_set_freq_from_app;
4159                 break;
4160         default:
4161                 break;
4162         }
4163 
4164         switch (hdspm->tco->pull) {
4165         case 1:
4166                 tc[2] |= HDSPM_TCO2_set_pull_up;
4167                 break;
4168         case 2:
4169                 tc[2] |= HDSPM_TCO2_set_pull_down;
4170                 break;
4171         case 3:
4172                 tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4;
4173                 break;
4174         case 4:
4175                 tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4;
4176                 break;
4177         default:
4178                 break;
4179         }
4180 
4181         if (1 == hdspm->tco->term) {
4182                 tc[2] |= HDSPM_TCO2_set_term_75R;
4183         }
4184 
4185         hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]);
4186         hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]);
4187         hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]);
4188         hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]);
4189 }
4190 
4191 
4192 #define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \
4193 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4194         .name = xname, \
4195         .index = xindex, \
4196         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4197                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4198         .info = snd_hdspm_info_tco_sample_rate, \
4199         .get = snd_hdspm_get_tco_sample_rate, \
4200         .put = snd_hdspm_put_tco_sample_rate \
4201 }
4202 
4203 static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol,
4204                                           struct snd_ctl_elem_info *uinfo)
4205 {
4206         /* TODO freq from app could be supported here, see tco->samplerate */
4207         static const char *const texts[] = { "44.1 kHz", "48 kHz" };
4208         ENUMERATED_CTL_INFO(uinfo, texts);
4209         return 0;
4210 }
4211 
4212 static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol,
4213                                       struct snd_ctl_elem_value *ucontrol)
4214 {
4215         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4216 
4217         ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate;
4218 
4219         return 0;
4220 }
4221 
4222 static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol,
4223                                          struct snd_ctl_elem_value *ucontrol)
4224 {
4225         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4226 
4227         if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) {
4228                 hdspm->tco->samplerate = ucontrol->value.enumerated.item[0];
4229 
4230                 hdspm_tco_write(hdspm);
4231 
4232                 return 1;
4233         }
4234 
4235         return 0;
4236 }
4237 
4238 
4239 #define HDSPM_TCO_PULL(xname, xindex) \
4240 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4241         .name = xname, \
4242         .index = xindex, \
4243         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4244                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4245         .info = snd_hdspm_info_tco_pull, \
4246         .get = snd_hdspm_get_tco_pull, \
4247         .put = snd_hdspm_put_tco_pull \
4248 }
4249 
4250 static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol,
4251                                    struct snd_ctl_elem_info *uinfo)
4252 {
4253         static const char *const texts[] = { "", "+ 0.1 %", "- 0.1 %",
4254                 "+ 4 %", "- 4 %" };
4255         ENUMERATED_CTL_INFO(uinfo, texts);
4256         return 0;
4257 }
4258 
4259 static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol,
4260                                   struct snd_ctl_elem_value *ucontrol)
4261 {
4262         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4263 
4264         ucontrol->value.enumerated.item[0] = hdspm->tco->pull;
4265 
4266         return 0;
4267 }
4268 
4269 static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol,
4270                                   struct snd_ctl_elem_value *ucontrol)
4271 {
4272         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4273 
4274         if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) {
4275                 hdspm->tco->pull = ucontrol->value.enumerated.item[0];
4276 
4277                 hdspm_tco_write(hdspm);
4278 
4279                 return 1;
4280         }
4281 
4282         return 0;
4283 }
4284 
4285 #define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \
4286 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4287         .name = xname, \
4288         .index = xindex, \
4289         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4290                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4291         .info = snd_hdspm_info_tco_wck_conversion, \
4292         .get = snd_hdspm_get_tco_wck_conversion, \
4293         .put = snd_hdspm_put_tco_wck_conversion \
4294 }
4295 
4296 static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4297                                              struct snd_ctl_elem_info *uinfo)
4298 {
4299         static const char *const texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" };
4300         ENUMERATED_CTL_INFO(uinfo, texts);
4301         return 0;
4302 }
4303 
4304 static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4305                                             struct snd_ctl_elem_value *ucontrol)
4306 {
4307         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4308 
4309         ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock;
4310 
4311         return 0;
4312 }
4313 
4314 static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4315                                             struct snd_ctl_elem_value *ucontrol)
4316 {
4317         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4318 
4319         if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) {
4320                 hdspm->tco->wordclock = ucontrol->value.enumerated.item[0];
4321 
4322                 hdspm_tco_write(hdspm);
4323 
4324                 return 1;
4325         }
4326 
4327         return 0;
4328 }
4329 
4330 
4331 #define HDSPM_TCO_FRAME_RATE(xname, xindex) \
4332 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4333         .name = xname, \
4334         .index = xindex, \
4335         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4336                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4337         .info = snd_hdspm_info_tco_frame_rate, \
4338         .get = snd_hdspm_get_tco_frame_rate, \
4339         .put = snd_hdspm_put_tco_frame_rate \
4340 }
4341 
4342 static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol,
4343                                           struct snd_ctl_elem_info *uinfo)
4344 {
4345         static const char *const texts[] = { "24 fps", "25 fps", "29.97fps",
4346                 "29.97 dfps", "30 fps", "30 dfps" };
4347         ENUMERATED_CTL_INFO(uinfo, texts);
4348         return 0;
4349 }
4350 
4351 static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol,
4352                                         struct snd_ctl_elem_value *ucontrol)
4353 {
4354         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4355 
4356         ucontrol->value.enumerated.item[0] = hdspm->tco->framerate;
4357 
4358         return 0;
4359 }
4360 
4361 static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol,
4362                                         struct snd_ctl_elem_value *ucontrol)
4363 {
4364         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4365 
4366         if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) {
4367                 hdspm->tco->framerate = ucontrol->value.enumerated.item[0];
4368 
4369                 hdspm_tco_write(hdspm);
4370 
4371                 return 1;
4372         }
4373 
4374         return 0;
4375 }
4376 
4377 
4378 #define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \
4379 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4380         .name = xname, \
4381         .index = xindex, \
4382         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4383                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4384         .info = snd_hdspm_info_tco_sync_source, \
4385         .get = snd_hdspm_get_tco_sync_source, \
4386         .put = snd_hdspm_put_tco_sync_source \
4387 }
4388 
4389 static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol,
4390                                           struct snd_ctl_elem_info *uinfo)
4391 {
4392         static const char *const texts[] = { "LTC", "Video", "WCK" };
4393         ENUMERATED_CTL_INFO(uinfo, texts);
4394         return 0;
4395 }
4396 
4397 static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol,
4398                                          struct snd_ctl_elem_value *ucontrol)
4399 {
4400         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4401 
4402         ucontrol->value.enumerated.item[0] = hdspm->tco->input;
4403 
4404         return 0;
4405 }
4406 
4407 static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol,
4408                                          struct snd_ctl_elem_value *ucontrol)
4409 {
4410         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4411 
4412         if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) {
4413                 hdspm->tco->input = ucontrol->value.enumerated.item[0];
4414 
4415                 hdspm_tco_write(hdspm);
4416 
4417                 return 1;
4418         }
4419 
4420         return 0;
4421 }
4422 
4423 
4424 #define HDSPM_TCO_WORD_TERM(xname, xindex) \
4425 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4426         .name = xname, \
4427         .index = xindex, \
4428         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4429                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4430         .info = snd_hdspm_info_tco_word_term, \
4431         .get = snd_hdspm_get_tco_word_term, \
4432         .put = snd_hdspm_put_tco_word_term \
4433 }
4434 
4435 static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol,
4436                                         struct snd_ctl_elem_info *uinfo)
4437 {
4438         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
4439         uinfo->count = 1;
4440         uinfo->value.integer.min = 0;
4441         uinfo->value.integer.max = 1;
4442 
4443         return 0;
4444 }
4445 
4446 
4447 static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol,
4448                                        struct snd_ctl_elem_value *ucontrol)
4449 {
4450         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4451 
4452         ucontrol->value.integer.value[0] = hdspm->tco->term;
4453 
4454         return 0;
4455 }
4456 
4457 
4458 static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol,
4459                                        struct snd_ctl_elem_value *ucontrol)
4460 {
4461         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4462 
4463         if (hdspm->tco->term != ucontrol->value.integer.value[0]) {
4464                 hdspm->tco->term = ucontrol->value.integer.value[0];
4465 
4466                 hdspm_tco_write(hdspm);
4467 
4468                 return 1;
4469         }
4470 
4471         return 0;
4472 }
4473 
4474 
4475 
4476 
4477 static const struct snd_kcontrol_new snd_hdspm_controls_madi[] = {
4478         HDSPM_MIXER("Mixer", 0),
4479         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4480         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4481         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4482         HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4483         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4484         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4485         HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4486         HDSPM_SYNC_CHECK("MADI SyncCheck", 1),
4487         HDSPM_SYNC_CHECK("TCO SyncCheck", 2),
4488         HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3),
4489         HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut),
4490         HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch),
4491         HDSPM_TOGGLE_SETTING("Disable 96K frames", HDSPM_SMUX),
4492         HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
4493         HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp),
4494         HDSPM_INPUT_SELECT("Input Select", 0),
4495         HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4496 };
4497 
4498 
4499 static const struct snd_kcontrol_new snd_hdspm_controls_madiface[] = {
4500         HDSPM_MIXER("Mixer", 0),
4501         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4502         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4503         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4504         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4505         HDSPM_SYNC_CHECK("MADI SyncCheck", 0),
4506         HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch),
4507         HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
4508         HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp),
4509         HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4510 };
4511 
4512 static const struct snd_kcontrol_new snd_hdspm_controls_aio[] = {
4513         HDSPM_MIXER("Mixer", 0),
4514         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4515         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4516         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4517         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4518         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4519         HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4520         HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4521         HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4522         HDSPM_SYNC_CHECK("ADAT SyncCheck", 3),
4523         HDSPM_SYNC_CHECK("TCO SyncCheck", 4),
4524         HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5),
4525         HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4526         HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4527         HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4528         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3),
4529         HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4),
4530         HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5),
4531         HDSPM_CONTROL_TRISTATE("S/PDIF Input", HDSPM_c0_Input0),
4532         HDSPM_TOGGLE_SETTING("S/PDIF Out Optical", HDSPM_c0_Spdif_Opt),
4533         HDSPM_TOGGLE_SETTING("S/PDIF Out Professional", HDSPM_c0_Pro),
4534         HDSPM_TOGGLE_SETTING("ADAT internal (AEB/TEB)", HDSPM_c0_AEB1),
4535         HDSPM_TOGGLE_SETTING("XLR Breakout Cable", HDSPM_c0_Sym6db),
4536         HDSPM_TOGGLE_SETTING("Single Speed WordClock Out", HDSPM_c0_Wck48),
4537         HDSPM_CONTROL_TRISTATE("Input Level", HDSPM_c0_AD_GAIN0),
4538         HDSPM_CONTROL_TRISTATE("Output Level", HDSPM_c0_DA_GAIN0),
4539         HDSPM_CONTROL_TRISTATE("Phones Level", HDSPM_c0_PH_GAIN0)
4540 
4541                 /*
4542                    HDSPM_INPUT_SELECT("Input Select", 0),
4543                    HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0),
4544                    HDSPM_PROFESSIONAL("SPDIF Out Professional", 0);
4545                    HDSPM_SPDIF_IN("SPDIF In", 0);
4546                    HDSPM_BREAKOUT_CABLE("Breakout Cable", 0);
4547                    HDSPM_INPUT_LEVEL("Input Level", 0);
4548                    HDSPM_OUTPUT_LEVEL("Output Level", 0);
4549                    HDSPM_PHONES("Phones", 0);
4550                    */
4551 };
4552 
4553 static const struct snd_kcontrol_new snd_hdspm_controls_raydat[] = {
4554         HDSPM_MIXER("Mixer", 0),
4555         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4556         HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0),
4557         HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0),
4558         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4559         HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4560         HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4561         HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4562         HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3),
4563         HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4),
4564         HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5),
4565         HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6),
4566         HDSPM_SYNC_CHECK("TCO SyncCheck", 7),
4567         HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8),
4568         HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4569         HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4570         HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4571         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3),
4572         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4),
4573         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5),
4574         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6),
4575         HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7),
4576         HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8),
4577         HDSPM_TOGGLE_SETTING("S/PDIF Out Professional", HDSPM_c0_Pro),
4578         HDSPM_TOGGLE_SETTING("Single Speed WordClock Out", HDSPM_c0_Wck48)
4579 };
4580 
4581 static const struct snd_kcontrol_new snd_hdspm_controls_aes32[] = {
4582         HDSPM_MIXER("Mixer", 0),
4583         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4584         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4585         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4586         HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4587         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4588         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 11),
4589         HDSPM_SYNC_CHECK("WC Sync Check", 0),
4590         HDSPM_SYNC_CHECK("AES1 Sync Check", 1),
4591         HDSPM_SYNC_CHECK("AES2 Sync Check", 2),
4592         HDSPM_SYNC_CHECK("AES3 Sync Check", 3),
4593         HDSPM_SYNC_CHECK("AES4 Sync Check", 4),
4594         HDSPM_SYNC_CHECK("AES5 Sync Check", 5),
4595         HDSPM_SYNC_CHECK("AES6 Sync Check", 6),
4596         HDSPM_SYNC_CHECK("AES7 Sync Check", 7),
4597         HDSPM_SYNC_CHECK("AES8 Sync Check", 8),
4598         HDSPM_SYNC_CHECK("TCO Sync Check", 9),
4599         HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10),
4600         HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4601         HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1),
4602         HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2),
4603         HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3),
4604         HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4),
4605         HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5),
4606         HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6),
4607         HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7),
4608         HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8),
4609         HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9),
4610         HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10),
4611         HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut),
4612         HDSPM_TOGGLE_SETTING("Emphasis", HDSPM_Emphasis),
4613         HDSPM_TOGGLE_SETTING("Non Audio", HDSPM_Dolby),
4614         HDSPM_TOGGLE_SETTING("Professional", HDSPM_Professional),
4615         HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
4616         HDSPM_DS_WIRE("Double Speed Wire Mode", 0),
4617         HDSPM_QS_WIRE("Quad Speed Wire Mode", 0),
4618 };
4619 
4620 
4621 
4622 /* Control elements for the optional TCO module */
4623 static const struct snd_kcontrol_new snd_hdspm_controls_tco[] = {
4624         HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0),
4625         HDSPM_TCO_PULL("TCO Pull", 0),
4626         HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0),
4627         HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0),
4628         HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0),
4629         HDSPM_TCO_WORD_TERM("TCO Word Term", 0),
4630         HDSPM_TCO_LOCK_CHECK("TCO Input Check", 11),
4631         HDSPM_TCO_LOCK_CHECK("TCO LTC Valid", 12),
4632         HDSPM_TCO_LTC_FRAMES("TCO Detected Frame Rate", 0),
4633         HDSPM_TCO_VIDEO_INPUT_FORMAT("Video Input Format", 0)
4634 };
4635 
4636 
4637 static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER;
4638 
4639 
4640 static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm)
4641 {
4642         int i;
4643 
4644         for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) {
4645                 if (hdspm->system_sample_rate > 48000) {
4646                         hdspm->playback_mixer_ctls[i]->vd[0].access =
4647                                 SNDRV_CTL_ELEM_ACCESS_INACTIVE |
4648                                 SNDRV_CTL_ELEM_ACCESS_READ |
4649                                 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4650                 } else {
4651                         hdspm->playback_mixer_ctls[i]->vd[0].access =
4652                                 SNDRV_CTL_ELEM_ACCESS_READWRITE |
4653                                 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4654                 }
4655                 snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE |
4656                                 SNDRV_CTL_EVENT_MASK_INFO,
4657                                 &hdspm->playback_mixer_ctls[i]->id);
4658         }
4659 
4660         return 0;
4661 }
4662 
4663 
4664 static int snd_hdspm_create_controls(struct snd_card *card,
4665                                         struct hdspm *hdspm)
4666 {
4667         unsigned int idx, limit;
4668         int err;
4669         struct snd_kcontrol *kctl;
4670         const struct snd_kcontrol_new *list = NULL;
4671 
4672         switch (hdspm->io_type) {
4673         case MADI:
4674                 list = snd_hdspm_controls_madi;
4675                 limit = ARRAY_SIZE(snd_hdspm_controls_madi);
4676                 break;
4677         case MADIface:
4678                 list = snd_hdspm_controls_madiface;
4679                 limit = ARRAY_SIZE(snd_hdspm_controls_madiface);
4680                 break;
4681         case AIO:
4682                 list = snd_hdspm_controls_aio;
4683                 limit = ARRAY_SIZE(snd_hdspm_controls_aio);
4684                 break;
4685         case RayDAT:
4686                 list = snd_hdspm_controls_raydat;
4687                 limit = ARRAY_SIZE(snd_hdspm_controls_raydat);
4688                 break;
4689         case AES32:
4690                 list = snd_hdspm_controls_aes32;
4691                 limit = ARRAY_SIZE(snd_hdspm_controls_aes32);
4692                 break;
4693         }
4694 
4695         if (list) {
4696                 for (idx = 0; idx < limit; idx++) {
4697                         err = snd_ctl_add(card,
4698                                         snd_ctl_new1(&list[idx], hdspm));
4699                         if (err < 0)
4700                                 return err;
4701                 }
4702         }
4703 
4704 
4705         /* create simple 1:1 playback mixer controls */
4706         snd_hdspm_playback_mixer.name = "Chn";
4707         if (hdspm->system_sample_rate >= 128000) {
4708                 limit = hdspm->qs_out_channels;
4709         } else if (hdspm->system_sample_rate >= 64000) {
4710                 limit = hdspm->ds_out_channels;
4711         } else {
4712                 limit = hdspm->ss_out_channels;
4713         }
4714         for (idx = 0; idx < limit; ++idx) {
4715                 snd_hdspm_playback_mixer.index = idx + 1;
4716                 kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm);
4717                 err = snd_ctl_add(card, kctl);
4718                 if (err < 0)
4719                         return err;
4720                 hdspm->playback_mixer_ctls[idx] = kctl;
4721         }
4722 
4723 
4724         if (hdspm->tco) {
4725                 /* add tco control elements */
4726                 list = snd_hdspm_controls_tco;
4727                 limit = ARRAY_SIZE(snd_hdspm_controls_tco);
4728                 for (idx = 0; idx < limit; idx++) {
4729                         err = snd_ctl_add(card,
4730                                         snd_ctl_new1(&list[idx], hdspm));
4731                         if (err < 0)
4732                                 return err;
4733                 }
4734         }
4735 
4736         return 0;
4737 }
4738 
4739 /*------------------------------------------------------------
4740    /proc interface
4741  ------------------------------------------------------------*/
4742 
4743 static void
4744 snd_hdspm_proc_read_tco(struct snd_info_entry *entry,
4745                                         struct snd_info_buffer *buffer)
4746 {
4747         struct hdspm *hdspm = entry->private_data;
4748         unsigned int status, control;
4749         int a, ltc, frames, seconds, minutes, hours;
4750         unsigned int period;
4751         u64 freq_const = 0;
4752         u32 rate;
4753 
4754         snd_iprintf(buffer, "--- TCO ---\n");
4755 
4756         status = hdspm_read(hdspm, HDSPM_statusRegister);
4757         control = hdspm->control_register;
4758 
4759 
4760         if (status & HDSPM_tco_detect) {
4761                 snd_iprintf(buffer, "TCO module detected.\n");
4762                 a = hdspm_read(hdspm, HDSPM_RD_TCO+4);
4763                 if (a & HDSPM_TCO1_LTC_Input_valid) {
4764                         snd_iprintf(buffer, "  LTC valid, ");
4765                         switch (a & (HDSPM_TCO1_LTC_Format_LSB |
4766                                                 HDSPM_TCO1_LTC_Format_MSB)) {
4767                         case 0:
4768                                 snd_iprintf(buffer, "24 fps, ");
4769                                 break;
4770                         case HDSPM_TCO1_LTC_Format_LSB:
4771                                 snd_iprintf(buffer, "25 fps, ");
4772                                 break;
4773                         case HDSPM_TCO1_LTC_Format_MSB:
4774                                 snd_iprintf(buffer, "29.97 fps, ");
4775                                 break;
4776                         default:
4777                                 snd_iprintf(buffer, "30 fps, ");
4778                                 break;
4779                         }
4780                         if (a & HDSPM_TCO1_set_drop_frame_flag) {
4781                                 snd_iprintf(buffer, "drop frame\n");
4782                         } else {
4783                                 snd_iprintf(buffer, "full frame\n");
4784                         }
4785                 } else {
4786                         snd_iprintf(buffer, "  no LTC\n");
4787                 }
4788                 if (a & HDSPM_TCO1_Video_Input_Format_NTSC) {
4789                         snd_iprintf(buffer, "  Video: NTSC\n");
4790                 } else if (a & HDSPM_TCO1_Video_Input_Format_PAL) {
4791                         snd_iprintf(buffer, "  Video: PAL\n");
4792                 } else {
4793                         snd_iprintf(buffer, "  No video\n");
4794                 }
4795                 if (a & HDSPM_TCO1_TCO_lock) {
4796                         snd_iprintf(buffer, "  Sync: lock\n");
4797                 } else {
4798                         snd_iprintf(buffer, "  Sync: no lock\n");
4799                 }
4800 
4801                 switch (hdspm->io_type) {
4802                 case MADI:
4803                 case AES32:
4804                         freq_const = 110069313433624ULL;
4805                         break;
4806                 case RayDAT:
4807                 case AIO:
4808                         freq_const = 104857600000000ULL;
4809                         break;
4810                 case MADIface:
4811                         break; /* no TCO possible */
4812                 }
4813 
4814                 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
4815                 snd_iprintf(buffer, "    period: %u\n", period);
4816 
4817 
4818                 /* rate = freq_const/period; */
4819                 rate = div_u64(freq_const, period);
4820 
4821                 if (control & HDSPM_QuadSpeed) {
4822                         rate *= 4;
4823                 } else if (control & HDSPM_DoubleSpeed) {
4824                         rate *= 2;
4825                 }
4826 
4827                 snd_iprintf(buffer, "  Frequency: %u Hz\n",
4828                                 (unsigned int) rate);
4829 
4830                 ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
4831                 frames = ltc & 0xF;
4832                 ltc >>= 4;
4833                 frames += (ltc & 0x3) * 10;
4834                 ltc >>= 4;
4835                 seconds = ltc & 0xF;
4836                 ltc >>= 4;
4837                 seconds += (ltc & 0x7) * 10;
4838                 ltc >>= 4;
4839                 minutes = ltc & 0xF;
4840                 ltc >>= 4;
4841                 minutes += (ltc & 0x7) * 10;
4842                 ltc >>= 4;
4843                 hours = ltc & 0xF;
4844                 ltc >>= 4;
4845                 hours += (ltc & 0x3) * 10;
4846                 snd_iprintf(buffer,
4847                         "  LTC In: %02d:%02d:%02d:%02d\n",
4848                         hours, minutes, seconds, frames);
4849 
4850         } else {
4851                 snd_iprintf(buffer, "No TCO module detected.\n");
4852         }
4853 }
4854 
4855 static void
4856 snd_hdspm_proc_read_madi(struct snd_info_entry *entry,
4857                          struct snd_info_buffer *buffer)
4858 {
4859         struct hdspm *hdspm = entry->private_data;
4860         unsigned int status, status2;
4861 
4862         char *pref_sync_ref;
4863         char *autosync_ref;
4864         char *system_clock_mode;
4865         int x, x2;
4866 
4867         status = hdspm_read(hdspm, HDSPM_statusRegister);
4868         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4869 
4870         snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n",
4871                         hdspm->card_name, hdspm->card->number + 1,
4872                         hdspm->firmware_rev,
4873                         (status2 & HDSPM_version0) |
4874                         (status2 & HDSPM_version1) | (status2 &
4875                                 HDSPM_version2));
4876 
4877         snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n",
4878                         (hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF,
4879                         hdspm->serial);
4880 
4881         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4882                         hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4883 
4884         snd_iprintf(buffer, "--- System ---\n");
4885 
4886         snd_iprintf(buffer,
4887                 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4888                 status & HDSPM_audioIRQPending,
4889                 (status & HDSPM_midi0IRQPending) ? 1 : 0,
4890                 (status & HDSPM_midi1IRQPending) ? 1 : 0,
4891                 hdspm->irq_count);
4892         snd_iprintf(buffer,
4893                 "HW pointer: id = %d, rawptr = %d (%d->%d) "
4894                 "estimated= %ld (bytes)\n",
4895                 ((status & HDSPM_BufferID) ? 1 : 0),
4896                 (status & HDSPM_BufferPositionMask),
4897                 (status & HDSPM_BufferPositionMask) %
4898                 (2 * (int)hdspm->period_bytes),
4899                 ((status & HDSPM_BufferPositionMask) - 64) %
4900                 (2 * (int)hdspm->period_bytes),
4901                 (long) hdspm_hw_pointer(hdspm) * 4);
4902 
4903         snd_iprintf(buffer,
4904                 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
4905                 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
4906                 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
4907                 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
4908                 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
4909         snd_iprintf(buffer,
4910                 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
4911                 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
4912                 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
4913         snd_iprintf(buffer,
4914                 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
4915                 "status2=0x%x\n",
4916                 hdspm->control_register, hdspm->control2_register,
4917                 status, status2);
4918 
4919 
4920         snd_iprintf(buffer, "--- Settings ---\n");
4921 
4922         x = hdspm_get_latency(hdspm);
4923 
4924         snd_iprintf(buffer,
4925                 "Size (Latency): %d samples (2 periods of %lu bytes)\n",
4926                 x, (unsigned long) hdspm->period_bytes);
4927 
4928         snd_iprintf(buffer, "Line out: %s\n",
4929                 (hdspm->control_register & HDSPM_LineOut) ? "on " : "off");
4930 
4931         snd_iprintf(buffer,
4932                 "ClearTrackMarker = %s, Transmit in %s Channel Mode, "
4933                 "Auto Input %s\n",
4934                 (hdspm->control_register & HDSPM_clr_tms) ? "on" : "off",
4935                 (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56",
4936                 (hdspm->control_register & HDSPM_AutoInp) ? "on" : "off");
4937 
4938 
4939         if (!(hdspm->control_register & HDSPM_ClockModeMaster))
4940                 system_clock_mode = "AutoSync";
4941         else
4942                 system_clock_mode = "Master";
4943         snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode);
4944 
4945         switch (hdspm_pref_sync_ref(hdspm)) {
4946         case HDSPM_SYNC_FROM_WORD:
4947                 pref_sync_ref = "Word Clock";
4948                 break;
4949         case HDSPM_SYNC_FROM_MADI:
4950                 pref_sync_ref = "MADI Sync";
4951                 break;
4952         case HDSPM_SYNC_FROM_TCO:
4953                 pref_sync_ref = "TCO";
4954                 break;
4955         case HDSPM_SYNC_FROM_SYNC_IN:
4956                 pref_sync_ref = "Sync In";
4957                 break;
4958         default:
4959                 pref_sync_ref = "XXXX Clock";
4960                 break;
4961         }
4962         snd_iprintf(buffer, "Preferred Sync Reference: %s\n",
4963                         pref_sync_ref);
4964 
4965         snd_iprintf(buffer, "System Clock Frequency: %d\n",
4966                         hdspm->system_sample_rate);
4967 
4968 
4969         snd_iprintf(buffer, "--- Status:\n");
4970 
4971         x = status & HDSPM_madiSync;
4972         x2 = status2 & HDSPM_wcSync;
4973 
4974         snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n",
4975                         (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") :
4976                         "NoLock",
4977                         (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") :
4978                         "NoLock");
4979 
4980         switch (hdspm_autosync_ref(hdspm)) {
4981         case HDSPM_AUTOSYNC_FROM_SYNC_IN:
4982                 autosync_ref = "Sync In";
4983                 break;
4984         case HDSPM_AUTOSYNC_FROM_TCO:
4985                 autosync_ref = "TCO";
4986                 break;
4987         case HDSPM_AUTOSYNC_FROM_WORD:
4988                 autosync_ref = "Word Clock";
4989                 break;
4990         case HDSPM_AUTOSYNC_FROM_MADI:
4991                 autosync_ref = "MADI Sync";
4992                 break;
4993         case HDSPM_AUTOSYNC_FROM_NONE:
4994                 autosync_ref = "Input not valid";
4995                 break;
4996         default:
4997                 autosync_ref = "---";
4998                 break;
4999         }
5000         snd_iprintf(buffer,
5001                 "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n",
5002                 autosync_ref, hdspm_external_sample_rate(hdspm),
5003                 (status & HDSPM_madiFreqMask) >> 22,
5004                 (status2 & HDSPM_wcFreqMask) >> 5);
5005 
5006         snd_iprintf(buffer, "Input: %s, Mode=%s\n",
5007                 (status & HDSPM_AB_int) ? "Coax" : "Optical",
5008                 (status & HDSPM_RX_64ch) ? "64 channels" :
5009                 "56 channels");
5010 
5011         /* call readout function for TCO specific status */
5012         snd_hdspm_proc_read_tco(entry, buffer);
5013 
5014         snd_iprintf(buffer, "\n");
5015 }
5016 
5017 static void
5018 snd_hdspm_proc_read_aes32(struct snd_info_entry * entry,
5019                           struct snd_info_buffer *buffer)
5020 {
5021         struct hdspm *hdspm = entry->private_data;
5022         unsigned int status;
5023         unsigned int status2;
5024         unsigned int timecode;
5025         unsigned int wcLock, wcSync;
5026         int pref_syncref;
5027         char *autosync_ref;
5028         int x;
5029 
5030         status = hdspm_read(hdspm, HDSPM_statusRegister);
5031         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
5032         timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
5033 
5034         snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n",
5035                     hdspm->card_name, hdspm->card->number + 1,
5036                     hdspm->firmware_rev);
5037 
5038         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
5039                     hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
5040 
5041         snd_iprintf(buffer, "--- System ---\n");
5042 
5043         snd_iprintf(buffer,
5044                     "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
5045                     status & HDSPM_audioIRQPending,
5046                     (status & HDSPM_midi0IRQPending) ? 1 : 0,
5047                     (status & HDSPM_midi1IRQPending) ? 1 : 0,
5048                     hdspm->irq_count);
5049         snd_iprintf(buffer,
5050                     "HW pointer: id = %d, rawptr = %d (%d->%d) "
5051                     "estimated= %ld (bytes)\n",
5052                     ((status & HDSPM_BufferID) ? 1 : 0),
5053                     (status & HDSPM_BufferPositionMask),
5054                     (status & HDSPM_BufferPositionMask) %
5055                     (2 * (int)hdspm->period_bytes),
5056                     ((status & HDSPM_BufferPositionMask) - 64) %
5057                     (2 * (int)hdspm->period_bytes),
5058                     (long) hdspm_hw_pointer(hdspm) * 4);
5059 
5060         snd_iprintf(buffer,
5061                     "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
5062                     hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
5063                     hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
5064                     hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
5065                     hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
5066         snd_iprintf(buffer,
5067                     "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
5068                     hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
5069                     hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
5070         snd_iprintf(buffer,
5071                     "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
5072                     "status2=0x%x\n",
5073                     hdspm->control_register, hdspm->control2_register,
5074                     status, status2);
5075 
5076         snd_iprintf(buffer, "--- Settings ---\n");
5077 
5078         x = hdspm_get_latency(hdspm);
5079 
5080         snd_iprintf(buffer,
5081                     "Size (Latency): %d samples (2 periods of %lu bytes)\n",
5082                     x, (unsigned long) hdspm->period_bytes);
5083 
5084         snd_iprintf(buffer, "Line out: %s\n",
5085                     (hdspm->
5086                      control_register & HDSPM_LineOut) ? "on " : "off");
5087 
5088         snd_iprintf(buffer,
5089                     "ClearTrackMarker %s, Emphasis %s, Dolby %s\n",
5090                     (hdspm->
5091                      control_register & HDSPM_clr_tms) ? "on" : "off",
5092                     (hdspm->
5093                      control_register & HDSPM_Emphasis) ? "on" : "off",
5094                     (hdspm->
5095                      control_register & HDSPM_Dolby) ? "on" : "off");
5096 
5097 
5098         pref_syncref = hdspm_pref_sync_ref(hdspm);
5099         if (pref_syncref == 0)
5100                 snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n");
5101         else
5102                 snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n",
5103                                 pref_syncref);
5104 
5105         snd_iprintf(buffer, "System Clock Frequency: %d\n",
5106                     hdspm->system_sample_rate);
5107 
5108         snd_iprintf(buffer, "Double speed: %s\n",
5109                         hdspm->control_register & HDSPM_DS_DoubleWire?
5110                         "Double wire" : "Single wire");
5111         snd_iprintf(buffer, "Quad speed: %s\n",
5112                         hdspm->control_register & HDSPM_QS_DoubleWire?
5113                         "Double wire" :
5114                         hdspm->control_register & HDSPM_QS_QuadWire?
5115                         "Quad wire" : "Single wire");
5116 
5117         snd_iprintf(buffer, "--- Status:\n");
5118 
5119         wcLock = status & HDSPM_AES32_wcLock;
5120         wcSync = wcLock && (status & HDSPM_AES32_wcSync);
5121 
5122         snd_iprintf(buffer, "Word: %s  Frequency: %d\n",
5123                     (wcLock) ? (wcSync ? "Sync   " : "Lock   ") : "No Lock",
5124                     HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF));
5125 
5126         for (x = 0; x < 8; x++) {
5127                 snd_iprintf(buffer, "AES%d: %s  Frequency: %d\n",
5128                             x+1,
5129                             (status2 & (HDSPM_LockAES >> x)) ?
5130                             "Sync   " : "No Lock",
5131                             HDSPM_bit2freq((timecode >> (4*x)) & 0xF));
5132         }
5133 
5134         switch (hdspm_autosync_ref(hdspm)) {
5135         case HDSPM_AES32_AUTOSYNC_FROM_NONE:
5136                 autosync_ref = "None"; break;
5137         case HDSPM_AES32_AUTOSYNC_FROM_WORD:
5138                 autosync_ref = "Word Clock"; break;
5139         case HDSPM_AES32_AUTOSYNC_FROM_AES1:
5140                 autosync_ref = "AES1"; break;
5141         case HDSPM_AES32_AUTOSYNC_FROM_AES2:
5142                 autosync_ref = "AES2"; break;
5143         case HDSPM_AES32_AUTOSYNC_FROM_AES3:
5144                 autosync_ref = "AES3"; break;
5145         case HDSPM_AES32_AUTOSYNC_FROM_AES4:
5146                 autosync_ref = "AES4"; break;
5147         case HDSPM_AES32_AUTOSYNC_FROM_AES5:
5148                 autosync_ref = "AES5"; break;
5149         case HDSPM_AES32_AUTOSYNC_FROM_AES6:
5150                 autosync_ref = "AES6"; break;
5151         case HDSPM_AES32_AUTOSYNC_FROM_AES7:
5152                 autosync_ref = "AES7"; break;
5153         case HDSPM_AES32_AUTOSYNC_FROM_AES8:
5154                 autosync_ref = "AES8"; break;
5155         case HDSPM_AES32_AUTOSYNC_FROM_TCO:
5156                 autosync_ref = "TCO"; break;
5157         case HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN:
5158                 autosync_ref = "Sync In"; break;
5159         default:
5160                 autosync_ref = "---"; break;
5161         }
5162         snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref);
5163 
5164         /* call readout function for TCO specific status */
5165         snd_hdspm_proc_read_tco(entry, buffer);
5166 
5167         snd_iprintf(buffer, "\n");
5168 }
5169 
5170 static void
5171 snd_hdspm_proc_read_raydat(struct snd_info_entry *entry,
5172                          struct snd_info_buffer *buffer)
5173 {
5174         struct hdspm *hdspm = entry->private_data;
5175         unsigned int status1, status2, status3, i;
5176         unsigned int lock, sync;
5177 
5178         status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */
5179         status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */
5180         status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */
5181 
5182         snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1);
5183         snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2);
5184         snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3);
5185 
5186 
5187         snd_iprintf(buffer, "\n*** CLOCK MODE\n\n");
5188 
5189         snd_iprintf(buffer, "Clock mode      : %s\n",
5190                 (hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave");
5191         snd_iprintf(buffer, "System frequency: %d Hz\n",
5192                 hdspm_get_system_sample_rate(hdspm));
5193 
5194         snd_iprintf(buffer, "\n*** INPUT STATUS\n\n");
5195 
5196         lock = 0x1;
5197         sync = 0x100;
5198 
5199         for (i = 0; i < 8; i++) {
5200                 snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n",
5201                                 i,
5202                                 (status1 & lock) ? 1 : 0,
5203                                 (status1 & sync) ? 1 : 0,
5204                                 texts_freq[(status2 >> (i * 4)) & 0xF]);
5205 
5206                 lock = lock<<1;
5207                 sync = sync<<1;
5208         }
5209 
5210         snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n",
5211                         (status1 & 0x1000000) ? 1 : 0,
5212                         (status1 & 0x2000000) ? 1 : 0,
5213                         texts_freq[(status1 >> 16) & 0xF]);
5214 
5215         snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n",
5216                         (status1 & 0x4000000) ? 1 : 0,
5217                         (status1 & 0x8000000) ? 1 : 0,
5218                         texts_freq[(status1 >> 20) & 0xF]);
5219 
5220         snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n",
5221                         (status3 & 0x400) ? 1 : 0,
5222                         (status3 & 0x800) ? 1 : 0,
5223                         texts_freq[(status2 >> 12) & 0xF]);
5224 
5225 }
5226 
5227 #ifdef CONFIG_SND_DEBUG
5228 static void
5229 snd_hdspm_proc_read_debug(struct snd_info_entry *entry,
5230                           struct snd_info_buffer *buffer)
5231 {
5232         struct hdspm *hdspm = entry->private_data;
5233 
5234         int j,i;
5235 
5236         for (i = 0; i < 256 /* 1024*64 */; i += j) {
5237                 snd_iprintf(buffer, "0x%08X: ", i);
5238                 for (j = 0; j < 16; j += 4)
5239                         snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j));
5240                 snd_iprintf(buffer, "\n");
5241         }
5242 }
5243 #endif
5244 
5245 
5246 static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry,
5247                           struct snd_info_buffer *buffer)
5248 {
5249         struct hdspm *hdspm = entry->private_data;
5250         int i;
5251 
5252         snd_iprintf(buffer, "# generated by hdspm\n");
5253 
5254         for (i = 0; i < hdspm->max_channels_in; i++) {
5255                 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]);
5256         }
5257 }
5258 
5259 static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry,
5260                           struct snd_info_buffer *buffer)
5261 {
5262         struct hdspm *hdspm = entry->private_data;
5263         int i;
5264 
5265         snd_iprintf(buffer, "# generated by hdspm\n");
5266 
5267         for (i = 0; i < hdspm->max_channels_out; i++) {
5268                 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]);
5269         }
5270 }
5271 
5272 
5273 static void snd_hdspm_proc_init(struct hdspm *hdspm)
5274 {
5275         void (*read)(struct snd_info_entry *, struct snd_info_buffer *) = NULL;
5276 
5277         switch (hdspm->io_type) {
5278         case AES32:
5279                 read = snd_hdspm_proc_read_aes32;
5280                 break;
5281         case MADI:
5282                 read = snd_hdspm_proc_read_madi;
5283                 break;
5284         case MADIface:
5285                 /* read = snd_hdspm_proc_read_madiface; */
5286                 break;
5287         case RayDAT:
5288                 read = snd_hdspm_proc_read_raydat;
5289                 break;
5290         case AIO:
5291                 break;
5292         }
5293 
5294         snd_card_ro_proc_new(hdspm->card, "hdspm", hdspm, read);
5295         snd_card_ro_proc_new(hdspm->card, "ports.in", hdspm,
5296                              snd_hdspm_proc_ports_in);
5297         snd_card_ro_proc_new(hdspm->card, "ports.out", hdspm,
5298                              snd_hdspm_proc_ports_out);
5299 
5300 #ifdef CONFIG_SND_DEBUG
5301         /* debug file to read all hdspm registers */
5302         snd_card_ro_proc_new(hdspm->card, "debug", hdspm,
5303                              snd_hdspm_proc_read_debug);
5304 #endif
5305 }
5306 
5307 /*------------------------------------------------------------
5308    hdspm intitialize
5309  ------------------------------------------------------------*/
5310 
5311 static int snd_hdspm_set_defaults(struct hdspm * hdspm)
5312 {
5313         /* ASSUMPTION: hdspm->lock is either held, or there is no need to
5314            hold it (e.g. during module initialization).
5315            */
5316 
5317         /* set defaults:       */
5318 
5319         hdspm->settings_register = 0;
5320 
5321         switch (hdspm->io_type) {
5322         case MADI:
5323         case MADIface:
5324                 hdspm->control_register =
5325                         0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5326                 break;
5327 
5328         case RayDAT:
5329         case AIO:
5330                 hdspm->settings_register = 0x1 + 0x1000;
5331                 /* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0,
5332                  * line_out */
5333                 hdspm->control_register =
5334                         0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5335                 break;
5336 
5337         case AES32:
5338                 hdspm->control_register =
5339                         HDSPM_ClockModeMaster | /* Master Clock Mode on */
5340                         hdspm_encode_latency(7) | /* latency max=8192samples */
5341                         HDSPM_SyncRef0 |        /* AES1 is syncclock */
5342                         HDSPM_LineOut | /* Analog output in */
5343                         HDSPM_Professional;  /* Professional mode */
5344                 break;
5345         }
5346 
5347         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5348 
5349         if (AES32 == hdspm->io_type) {
5350                 /* No control2 register for AES32 */
5351 #ifdef SNDRV_BIG_ENDIAN
5352                 hdspm->control2_register = HDSPM_BIGENDIAN_MODE;
5353 #else
5354                 hdspm->control2_register = 0;
5355 #endif
5356 
5357                 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register);
5358         }
5359         hdspm_compute_period_size(hdspm);
5360 
5361         /* silence everything */
5362 
5363         all_in_all_mixer(hdspm, 0 * UNITY_GAIN);
5364 
5365         if (hdspm_is_raydat_or_aio(hdspm))
5366                 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
5367 
5368         /* set a default rate so that the channel map is set up. */
5369         hdspm_set_rate(hdspm, 48000, 1);
5370 
5371         return 0;
5372 }
5373 
5374 
5375 /*------------------------------------------------------------
5376    interrupt
5377  ------------------------------------------------------------*/
5378 
5379 static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id)
5380 {
5381         struct hdspm *hdspm = (struct hdspm *) dev_id;
5382         unsigned int status;
5383         int i, audio, midi, schedule = 0;
5384         /* cycles_t now; */
5385 
5386         status = hdspm_read(hdspm, HDSPM_statusRegister);
5387 
5388         audio = status & HDSPM_audioIRQPending;
5389         midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending |
5390                         HDSPM_midi2IRQPending | HDSPM_midi3IRQPending);
5391 
5392         /* now = get_cycles(); */
5393         /*
5394          *   LAT_2..LAT_0 period  counter (win)  counter (mac)
5395          *          6       4096   ~256053425     ~514672358
5396          *          5       2048   ~128024983     ~257373821
5397          *          4       1024    ~64023706     ~128718089
5398          *          3        512    ~32005945      ~64385999
5399          *          2        256    ~16003039      ~32260176
5400          *          1        128     ~7998738      ~16194507
5401          *          0         64     ~3998231       ~8191558
5402          */
5403         /*
5404           dev_info(hdspm->card->dev, "snd_hdspm_interrupt %llu @ %llx\n",
5405            now-hdspm->last_interrupt, status & 0xFFC0);
5406            hdspm->last_interrupt = now;
5407         */
5408 
5409         if (!audio && !midi)
5410                 return IRQ_NONE;
5411 
5412         hdspm_write(hdspm, HDSPM_interruptConfirmation, 0);
5413         hdspm->irq_count++;
5414 
5415 
5416         if (audio) {
5417                 if (hdspm->capture_substream)
5418                         snd_pcm_period_elapsed(hdspm->capture_substream);
5419 
5420                 if (hdspm->playback_substream)
5421                         snd_pcm_period_elapsed(hdspm->playback_substream);
5422         }
5423 
5424         if (midi) {
5425                 i = 0;
5426                 while (i < hdspm->midiPorts) {
5427                         if ((hdspm_read(hdspm,
5428                                 hdspm->midi[i].statusIn) & 0xff) &&
5429                                         (status & hdspm->midi[i].irq)) {
5430                                 /* we disable interrupts for this input until
5431                                  * processing is done
5432                                  */
5433                                 hdspm->control_register &= ~hdspm->midi[i].ie;
5434                                 hdspm_write(hdspm, HDSPM_controlRegister,
5435                                                 hdspm->control_register);
5436                                 hdspm->midi[i].pending = 1;
5437                                 schedule = 1;
5438                         }
5439 
5440                         i++;
5441                 }
5442 
5443                 if (schedule)
5444                         queue_work(system_highpri_wq, &hdspm->midi_work);
5445         }
5446 
5447         return IRQ_HANDLED;
5448 }
5449 
5450 /*------------------------------------------------------------
5451    pcm interface
5452   ------------------------------------------------------------*/
5453 
5454 
5455 static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream
5456                                               *substream)
5457 {
5458         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5459         return hdspm_hw_pointer(hdspm);
5460 }
5461 
5462 
5463 static int snd_hdspm_reset(struct snd_pcm_substream *substream)
5464 {
5465         struct snd_pcm_runtime *runtime = substream->runtime;
5466         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5467         struct snd_pcm_substream *other;
5468 
5469         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5470                 other = hdspm->capture_substream;
5471         else
5472                 other = hdspm->playback_substream;
5473 
5474         if (hdspm->running)
5475                 runtime->status->hw_ptr = hdspm_hw_pointer(hdspm);
5476         else
5477                 runtime->status->hw_ptr = 0;
5478         if (other) {
5479                 struct snd_pcm_substream *s;
5480                 struct snd_pcm_runtime *oruntime = other->runtime;
5481                 snd_pcm_group_for_each_entry(s, substream) {
5482                         if (s == other) {
5483                                 oruntime->status->hw_ptr =
5484                                         runtime->status->hw_ptr;
5485                                 break;
5486                         }
5487                 }
5488         }
5489         return 0;
5490 }
5491 
5492 static int snd_hdspm_hw_params(struct snd_pcm_substream *substream,
5493                                struct snd_pcm_hw_params *params)
5494 {
5495         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5496         int err;
5497         int i;
5498         pid_t this_pid;
5499         pid_t other_pid;
5500 
5501         spin_lock_irq(&hdspm->lock);
5502 
5503         if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5504                 this_pid = hdspm->playback_pid;
5505                 other_pid = hdspm->capture_pid;
5506         } else {
5507                 this_pid = hdspm->capture_pid;
5508                 other_pid = hdspm->playback_pid;
5509         }
5510 
5511         if (other_pid > 0 && this_pid != other_pid) {
5512 
5513                 /* The other stream is open, and not by the same
5514                    task as this one. Make sure that the parameters
5515                    that matter are the same.
5516                    */
5517 
5518                 if (params_rate(params) != hdspm->system_sample_rate) {
5519                         spin_unlock_irq(&hdspm->lock);
5520                         _snd_pcm_hw_param_setempty(params,
5521                                         SNDRV_PCM_HW_PARAM_RATE);
5522                         return -EBUSY;
5523                 }
5524 
5525                 if (params_period_size(params) != hdspm->period_bytes / 4) {
5526                         spin_unlock_irq(&hdspm->lock);
5527                         _snd_pcm_hw_param_setempty(params,
5528                                         SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5529                         return -EBUSY;
5530                 }
5531 
5532         }
5533         /* We're fine. */
5534         spin_unlock_irq(&hdspm->lock);
5535 
5536         /* how to make sure that the rate matches an externally-set one ?   */
5537 
5538         spin_lock_irq(&hdspm->lock);
5539         err = hdspm_set_rate(hdspm, params_rate(params), 0);
5540         if (err < 0) {
5541                 dev_info(hdspm->card->dev, "err on hdspm_set_rate: %d\n", err);
5542                 spin_unlock_irq(&hdspm->lock);
5543                 _snd_pcm_hw_param_setempty(params,
5544                                 SNDRV_PCM_HW_PARAM_RATE);
5545                 return err;
5546         }
5547         spin_unlock_irq(&hdspm->lock);
5548 
5549         err = hdspm_set_interrupt_interval(hdspm,
5550                         params_period_size(params));
5551         if (err < 0) {
5552                 dev_info(hdspm->card->dev,
5553                          "err on hdspm_set_interrupt_interval: %d\n", err);
5554                 _snd_pcm_hw_param_setempty(params,
5555                                 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5556                 return err;
5557         }
5558 
5559         /* Memory allocation, takashi's method, dont know if we should
5560          * spinlock
5561          */
5562         /* malloc all buffer even if not enabled to get sure */
5563         /* Update for MADI rev 204: we need to allocate for all channels,
5564          * otherwise it doesn't work at 96kHz */
5565 
5566         err =
5567                 snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES);
5568         if (err < 0) {
5569                 dev_info(hdspm->card->dev,
5570                          "err on snd_pcm_lib_malloc_pages: %d\n", err);
5571                 return err;
5572         }
5573 
5574         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5575 
5576                 for (i = 0; i < params_channels(params); ++i) {
5577                         int c = hdspm->channel_map_out[i];
5578 
5579                         if (c < 0)
5580                                 continue;      /* just make sure */
5581                         hdspm_set_channel_dma_addr(hdspm, substream,
5582                                                    HDSPM_pageAddressBufferOut,
5583                                                    c);
5584                         snd_hdspm_enable_out(hdspm, c, 1);
5585                 }
5586 
5587                 hdspm->playback_buffer =
5588                         (unsigned char *) substream->runtime->dma_area;
5589                 dev_dbg(hdspm->card->dev,
5590                         "Allocated sample buffer for playback at %p\n",
5591                                 hdspm->playback_buffer);
5592         } else {
5593                 for (i = 0; i < params_channels(params); ++i) {
5594                         int c = hdspm->channel_map_in[i];
5595 
5596                         if (c < 0)
5597                                 continue;
5598                         hdspm_set_channel_dma_addr(hdspm, substream,
5599                                                    HDSPM_pageAddressBufferIn,
5600                                                    c);
5601                         snd_hdspm_enable_in(hdspm, c, 1);
5602                 }
5603 
5604                 hdspm->capture_buffer =
5605                         (unsigned char *) substream->runtime->dma_area;
5606                 dev_dbg(hdspm->card->dev,
5607                         "Allocated sample buffer for capture at %p\n",
5608                                 hdspm->capture_buffer);
5609         }
5610 
5611         /*
5612            dev_dbg(hdspm->card->dev,
5613            "Allocated sample buffer for %s at 0x%08X\n",
5614            substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5615            "playback" : "capture",
5616            snd_pcm_sgbuf_get_addr(substream, 0));
5617            */
5618         /*
5619            dev_dbg(hdspm->card->dev,
5620            "set_hwparams: %s %d Hz, %d channels, bs = %d\n",
5621            substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5622            "playback" : "capture",
5623            params_rate(params), params_channels(params),
5624            params_buffer_size(params));
5625            */
5626 
5627 
5628         /*  For AES cards, the float format bit is the same as the
5629          *  preferred sync reference. Since we don't want to break
5630          *  sync settings, we have to skip the remaining part of this
5631          *  function.
5632          */
5633         if (hdspm->io_type == AES32) {
5634                 return 0;
5635         }
5636 
5637 
5638         /* Switch to native float format if requested */
5639         if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) {
5640                 if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT))
5641                         dev_info(hdspm->card->dev,
5642                                  "Switching to native 32bit LE float format.\n");
5643 
5644                 hdspm->control_register |= HDSPe_FLOAT_FORMAT;
5645         } else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) {
5646                 if (hdspm->control_register & HDSPe_FLOAT_FORMAT)
5647                         dev_info(hdspm->card->dev,
5648                                  "Switching to native 32bit LE integer format.\n");
5649 
5650                 hdspm->control_register &= ~HDSPe_FLOAT_FORMAT;
5651         }
5652         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5653 
5654         return 0;
5655 }
5656 
5657 static int snd_hdspm_hw_free(struct snd_pcm_substream *substream)
5658 {
5659         int i;
5660         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5661 
5662         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5663                 /* Just disable all channels. The saving when disabling a */
5664                 /* smaller set is not worth the trouble. */
5665                 for (i = 0; i < HDSPM_MAX_CHANNELS; ++i)
5666                         snd_hdspm_enable_out(hdspm, i, 0);
5667 
5668                 hdspm->playback_buffer = NULL;
5669         } else {
5670                 for (i = 0; i < HDSPM_MAX_CHANNELS; ++i)
5671                         snd_hdspm_enable_in(hdspm, i, 0);
5672 
5673                 hdspm->capture_buffer = NULL;
5674         }
5675 
5676         snd_pcm_lib_free_pages(substream);
5677 
5678         return 0;
5679 }
5680 
5681 
5682 static int snd_hdspm_channel_info(struct snd_pcm_substream *substream,
5683                 struct snd_pcm_channel_info *info)
5684 {
5685         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5686         unsigned int channel = info->channel;
5687 
5688         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5689                 if (snd_BUG_ON(channel >= hdspm->max_channels_out)) {
5690                         dev_info(hdspm->card->dev,
5691                                  "snd_hdspm_channel_info: output channel out of range (%d)\n",
5692                                  channel);
5693                         return -EINVAL;
5694                 }
5695 
5696                 channel = array_index_nospec(channel, hdspm->max_channels_out);
5697                 if (hdspm->channel_map_out[channel] < 0) {
5698                         dev_info(hdspm->card->dev,
5699                                  "snd_hdspm_channel_info: output channel %d mapped out\n",
5700                                  channel);
5701                         return -EINVAL;
5702                 }
5703 
5704                 info->offset = hdspm->channel_map_out[channel] *
5705                         HDSPM_CHANNEL_BUFFER_BYTES;
5706         } else {
5707                 if (snd_BUG_ON(channel >= hdspm->max_channels_in)) {
5708                         dev_info(hdspm->card->dev,
5709                                  "snd_hdspm_channel_info: input channel out of range (%d)\n",
5710                                  channel);
5711                         return -EINVAL;
5712                 }
5713 
5714                 channel = array_index_nospec(channel, hdspm->max_channels_in);
5715                 if (hdspm->channel_map_in[channel] < 0) {
5716                         dev_info(hdspm->card->dev,
5717                                  "snd_hdspm_channel_info: input channel %d mapped out\n",
5718                                  channel);
5719                         return -EINVAL;
5720                 }
5721 
5722                 info->offset = hdspm->channel_map_in[channel] *
5723                         HDSPM_CHANNEL_BUFFER_BYTES;
5724         }
5725 
5726         info->first = 0;
5727         info->step = 32;
5728         return 0;
5729 }
5730 
5731 
5732 static int snd_hdspm_ioctl(struct snd_pcm_substream *substream,
5733                 unsigned int cmd, void *arg)
5734 {
5735         switch (cmd) {
5736         case SNDRV_PCM_IOCTL1_RESET:
5737                 return snd_hdspm_reset(substream);
5738 
5739         case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
5740                 {
5741                         struct snd_pcm_channel_info *info = arg;
5742                         return snd_hdspm_channel_info(substream, info);
5743                 }
5744         default:
5745                 break;
5746         }
5747 
5748         return snd_pcm_lib_ioctl(substream, cmd, arg);
5749 }
5750 
5751 static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd)
5752 {
5753         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5754         struct snd_pcm_substream *other;
5755         int running;
5756 
5757         spin_lock(&hdspm->lock);
5758         running = hdspm->running;
5759         switch (cmd) {
5760         case SNDRV_PCM_TRIGGER_START:
5761                 running |= 1 << substream->stream;
5762                 break;
5763         case SNDRV_PCM_TRIGGER_STOP:
5764                 running &= ~(1 << substream->stream);
5765                 break;
5766         default:
5767                 snd_BUG();
5768                 spin_unlock(&hdspm->lock);
5769                 return -EINVAL;
5770         }
5771         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5772                 other = hdspm->capture_substream;
5773         else
5774                 other = hdspm->playback_substream;
5775 
5776         if (other) {
5777                 struct snd_pcm_substream *s;
5778                 snd_pcm_group_for_each_entry(s, substream) {
5779                         if (s == other) {
5780                                 snd_pcm_trigger_done(s, substream);
5781                                 if (cmd == SNDRV_PCM_TRIGGER_START)
5782                                         running |= 1 << s->stream;
5783                                 else
5784                                         running &= ~(1 << s->stream);
5785                                 goto _ok;
5786                         }
5787                 }
5788                 if (cmd == SNDRV_PCM_TRIGGER_START) {
5789                         if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK))
5790                                         && substream->stream ==
5791                                         SNDRV_PCM_STREAM_CAPTURE)
5792                                 hdspm_silence_playback(hdspm);
5793                 } else {
5794                         if (running &&
5795                                 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5796                                 hdspm_silence_playback(hdspm);
5797                 }
5798         } else {
5799                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
5800                         hdspm_silence_playback(hdspm);
5801         }
5802 _ok:
5803         snd_pcm_trigger_done(substream, substream);
5804         if (!hdspm->running && running)
5805                 hdspm_start_audio(hdspm);
5806         else if (hdspm->running && !running)
5807                 hdspm_stop_audio(hdspm);
5808         hdspm->running = running;
5809         spin_unlock(&hdspm->lock);
5810 
5811         return 0;
5812 }
5813 
5814 static int snd_hdspm_prepare(struct snd_pcm_substream *substream)
5815 {
5816         return 0;
5817 }
5818 
5819 static const struct snd_pcm_hardware snd_hdspm_playback_subinfo = {
5820         .info = (SNDRV_PCM_INFO_MMAP |
5821                  SNDRV_PCM_INFO_MMAP_VALID |
5822                  SNDRV_PCM_INFO_NONINTERLEAVED |
5823                  SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE),
5824         .formats = SNDRV_PCM_FMTBIT_S32_LE,
5825         .rates = (SNDRV_PCM_RATE_32000 |
5826                   SNDRV_PCM_RATE_44100 |
5827                   SNDRV_PCM_RATE_48000 |
5828                   SNDRV_PCM_RATE_64000 |
5829                   SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5830                   SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ),
5831         .rate_min = 32000,
5832         .rate_max = 192000,
5833         .channels_min = 1,
5834         .channels_max = HDSPM_MAX_CHANNELS,
5835         .buffer_bytes_max =
5836             HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5837         .period_bytes_min = (32 * 4),
5838         .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
5839         .periods_min = 2,
5840         .periods_max = 512,
5841         .fifo_size = 0
5842 };
5843 
5844 static const struct snd_pcm_hardware snd_hdspm_capture_subinfo = {
5845         .info = (SNDRV_PCM_INFO_MMAP |
5846                  SNDRV_PCM_INFO_MMAP_VALID |
5847                  SNDRV_PCM_INFO_NONINTERLEAVED |
5848                  SNDRV_PCM_INFO_SYNC_START),
5849         .formats = SNDRV_PCM_FMTBIT_S32_LE,
5850         .rates = (SNDRV_PCM_RATE_32000 |
5851                   SNDRV_PCM_RATE_44100 |
5852                   SNDRV_PCM_RATE_48000 |
5853                   SNDRV_PCM_RATE_64000 |
5854                   SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5855                   SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000),
5856         .rate_min = 32000,
5857         .rate_max = 192000,
5858         .channels_min = 1,
5859         .channels_max = HDSPM_MAX_CHANNELS,
5860         .buffer_bytes_max =
5861             HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5862         .period_bytes_min = (32 * 4),
5863         .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
5864         .periods_min = 2,
5865         .periods_max = 512,
5866         .fifo_size = 0
5867 };
5868 
5869 static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
5870                                            struct snd_pcm_hw_rule *rule)
5871 {
5872         struct hdspm *hdspm = rule->private;
5873         struct snd_interval *c =
5874             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5875         struct snd_interval *r =
5876             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5877 
5878         if (r->min > 96000 && r->max <= 192000) {
5879                 struct snd_interval t = {
5880                         .min = hdspm->qs_in_channels,
5881                         .max = hdspm->qs_in_channels,
5882                         .integer = 1,
5883                 };
5884                 return snd_interval_refine(c, &t);
5885         } else if (r->min > 48000 && r->max <= 96000) {
5886                 struct snd_interval t = {
5887                         .min = hdspm->ds_in_channels,
5888                         .max = hdspm->ds_in_channels,
5889                         .integer = 1,
5890                 };
5891                 return snd_interval_refine(c, &t);
5892         } else if (r->max < 64000) {
5893                 struct snd_interval t = {
5894                         .min = hdspm->ss_in_channels,
5895                         .max = hdspm->ss_in_channels,
5896                         .integer = 1,
5897                 };
5898                 return snd_interval_refine(c, &t);
5899         }
5900 
5901         return 0;
5902 }
5903 
5904 static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
5905                                            struct snd_pcm_hw_rule * rule)
5906 {
5907         struct hdspm *hdspm = rule->private;
5908         struct snd_interval *c =
5909             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5910         struct snd_interval *r =
5911             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5912 
5913         if (r->min > 96000 && r->max <= 192000) {
5914                 struct snd_interval t = {
5915                         .min = hdspm->qs_out_channels,
5916                         .max = hdspm->qs_out_channels,
5917                         .integer = 1,
5918                 };
5919                 return snd_interval_refine(c, &t);
5920         } else if (r->min > 48000 && r->max <= 96000) {
5921                 struct snd_interval t = {
5922                         .min = hdspm->ds_out_channels,
5923                         .max = hdspm->ds_out_channels,
5924                         .integer = 1,
5925                 };
5926                 return snd_interval_refine(c, &t);
5927         } else if (r->max < 64000) {
5928                 struct snd_interval t = {
5929                         .min = hdspm->ss_out_channels,
5930                         .max = hdspm->ss_out_channels,
5931                         .integer = 1,
5932                 };
5933                 return snd_interval_refine(c, &t);
5934         } else {
5935         }
5936         return 0;
5937 }
5938 
5939 static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
5940                                            struct snd_pcm_hw_rule * rule)
5941 {
5942         struct hdspm *hdspm = rule->private;
5943         struct snd_interval *c =
5944             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5945         struct snd_interval *r =
5946             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5947 
5948         if (c->min >= hdspm->ss_in_channels) {
5949                 struct snd_interval t = {
5950                         .min = 32000,
5951                         .max = 48000,
5952                         .integer = 1,
5953                 };
5954                 return snd_interval_refine(r, &t);
5955         } else if (c->max <= hdspm->qs_in_channels) {
5956                 struct snd_interval t = {
5957                         .min = 128000,
5958                         .max = 192000,
5959                         .integer = 1,
5960                 };
5961                 return snd_interval_refine(r, &t);
5962         } else if (c->max <= hdspm->ds_in_channels) {
5963                 struct snd_interval t = {
5964                         .min = 64000,
5965                         .max = 96000,
5966                         .integer = 1,
5967                 };
5968                 return snd_interval_refine(r, &t);
5969         }
5970 
5971         return 0;
5972 }
5973 static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
5974                                            struct snd_pcm_hw_rule *rule)
5975 {
5976         struct hdspm *hdspm = rule->private;
5977         struct snd_interval *c =
5978             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5979         struct snd_interval *r =
5980             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5981 
5982         if (c->min >= hdspm->ss_out_channels) {
5983                 struct snd_interval t = {
5984                         .min = 32000,
5985                         .max = 48000,
5986                         .integer = 1,
5987                 };
5988                 return snd_interval_refine(r, &t);
5989         } else if (c->max <= hdspm->qs_out_channels) {
5990                 struct snd_interval t = {
5991                         .min = 128000,
5992                         .max = 192000,
5993                         .integer = 1,
5994                 };
5995                 return snd_interval_refine(r, &t);
5996         } else if (c->max <= hdspm->ds_out_channels) {
5997                 struct snd_interval t = {
5998                         .min = 64000,
5999                         .max = 96000,
6000                         .integer = 1,
6001                 };
6002                 return snd_interval_refine(r, &t);
6003         }
6004 
6005         return 0;
6006 }
6007 
6008 static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params *params,
6009                                       struct snd_pcm_hw_rule *rule)
6010 {
6011         unsigned int list[3];
6012         struct hdspm *hdspm = rule->private;
6013         struct snd_interval *c = hw_param_interval(params,
6014                         SNDRV_PCM_HW_PARAM_CHANNELS);
6015 
6016         list[0] = hdspm->qs_in_channels;
6017         list[1] = hdspm->ds_in_channels;
6018         list[2] = hdspm->ss_in_channels;
6019         return snd_interval_list(c, 3, list, 0);
6020 }
6021 
6022 static int snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params *params,
6023                                       struct snd_pcm_hw_rule *rule)
6024 {
6025         unsigned int list[3];
6026         struct hdspm *hdspm = rule->private;
6027         struct snd_interval *c = hw_param_interval(params,
6028                         SNDRV_PCM_HW_PARAM_CHANNELS);
6029 
6030         list[0] = hdspm->qs_out_channels;
6031         list[1] = hdspm->ds_out_channels;
6032         list[2] = hdspm->ss_out_channels;
6033         return snd_interval_list(c, 3, list, 0);
6034 }
6035 
6036 
6037 static const unsigned int hdspm_aes32_sample_rates[] = {
6038         32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000
6039 };
6040 
6041 static const struct snd_pcm_hw_constraint_list
6042 hdspm_hw_constraints_aes32_sample_rates = {
6043         .count = ARRAY_SIZE(hdspm_aes32_sample_rates),
6044         .list = hdspm_aes32_sample_rates,
6045         .mask = 0
6046 };
6047 
6048 static int snd_hdspm_open(struct snd_pcm_substream *substream)
6049 {
6050         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6051         struct snd_pcm_runtime *runtime = substream->runtime;
6052         bool playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
6053 
6054         spin_lock_irq(&hdspm->lock);
6055         snd_pcm_set_sync(substream);
6056         runtime->hw = (playback) ? snd_hdspm_playback_subinfo :
6057                 snd_hdspm_capture_subinfo;
6058 
6059         if (playback) {
6060                 if (!hdspm->capture_substream)
6061                         hdspm_stop_audio(hdspm);
6062 
6063                 hdspm->playback_pid = current->pid;
6064                 hdspm->playback_substream = substream;
6065         } else {
6066                 if (!hdspm->playback_substream)
6067                         hdspm_stop_audio(hdspm);
6068 
6069                 hdspm->capture_pid = current->pid;
6070                 hdspm->capture_substream = substream;
6071         }
6072 
6073         spin_unlock_irq(&hdspm->lock);
6074 
6075         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
6076         snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
6077 
6078         switch (hdspm->io_type) {
6079         case AIO:
6080         case RayDAT:
6081                 snd_pcm_hw_constraint_minmax(runtime,
6082                                              SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6083                                              32, 4096);
6084                 /* RayDAT & AIO have a fixed buffer of 16384 samples per channel */
6085                 snd_pcm_hw_constraint_single(runtime,
6086                                              SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
6087                                              16384);
6088                 break;
6089 
6090         default:
6091                 snd_pcm_hw_constraint_minmax(runtime,
6092                                              SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6093                                              64, 8192);
6094                 snd_pcm_hw_constraint_single(runtime,
6095                                              SNDRV_PCM_HW_PARAM_PERIODS, 2);
6096                 break;
6097         }
6098 
6099         if (AES32 == hdspm->io_type) {
6100                 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
6101                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6102                                 &hdspm_hw_constraints_aes32_sample_rates);
6103         } else {
6104                 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6105                                 (playback ?
6106                                  snd_hdspm_hw_rule_rate_out_channels :
6107                                  snd_hdspm_hw_rule_rate_in_channels), hdspm,
6108                                 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6109         }
6110 
6111         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6112                         (playback ? snd_hdspm_hw_rule_out_channels :
6113                          snd_hdspm_hw_rule_in_channels), hdspm,
6114                         SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6115 
6116         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6117                         (playback ? snd_hdspm_hw_rule_out_channels_rate :
6118                          snd_hdspm_hw_rule_in_channels_rate), hdspm,
6119                         SNDRV_PCM_HW_PARAM_RATE, -1);
6120 
6121         return 0;
6122 }
6123 
6124 static int snd_hdspm_release(struct snd_pcm_substream *substream)
6125 {
6126         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6127         bool playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
6128 
6129         spin_lock_irq(&hdspm->lock);
6130 
6131         if (playback) {
6132                 hdspm->playback_pid = -1;
6133                 hdspm->playback_substream = NULL;
6134         } else {
6135                 hdspm->capture_pid = -1;
6136                 hdspm->capture_substream = NULL;
6137         }
6138 
6139         spin_unlock_irq(&hdspm->lock);
6140 
6141         return 0;
6142 }
6143 
6144 static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file)
6145 {
6146         /* we have nothing to initialize but the call is required */
6147         return 0;
6148 }
6149 
6150 static inline int copy_u32_le(void __user *dest, void __iomem *src)
6151 {
6152         u32 val = readl(src);
6153         return copy_to_user(dest, &val, 4);
6154 }
6155 
6156 static int snd_hdspm_hwdep_ioctl(struct snd_hwdep *hw, struct file *file,
6157                 unsigned int cmd, unsigned long arg)
6158 {
6159         void __user *argp = (void __user *)arg;
6160         struct hdspm *hdspm = hw->private_data;
6161         struct hdspm_mixer_ioctl mixer;
6162         struct hdspm_config info;
6163         struct hdspm_status status;
6164         struct hdspm_version hdspm_version;
6165         struct hdspm_peak_rms *levels;
6166         struct hdspm_ltc ltc;
6167         unsigned int statusregister;
6168         long unsigned int s;
6169         int i = 0;
6170 
6171         switch (cmd) {
6172 
6173         case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS:
6174                 levels = &hdspm->peak_rms;
6175                 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
6176                         levels->input_peaks[i] =
6177                                 readl(hdspm->iobase +
6178                                                 HDSPM_MADI_INPUT_PEAK + i*4);
6179                         levels->playback_peaks[i] =
6180                                 readl(hdspm->iobase +
6181                                                 HDSPM_MADI_PLAYBACK_PEAK + i*4);
6182                         levels->output_peaks[i] =
6183                                 readl(hdspm->iobase +
6184                                                 HDSPM_MADI_OUTPUT_PEAK + i*4);
6185 
6186                         levels->input_rms[i] =
6187                                 ((uint64_t) readl(hdspm->iobase +
6188                                         HDSPM_MADI_INPUT_RMS_H + i*4) << 32) |
6189                                 (uint64_t) readl(hdspm->iobase +
6190                                                 HDSPM_MADI_INPUT_RMS_L + i*4);
6191