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TOMOYO Linux Cross Reference
Linux/sound/pci/ymfpci/ymfpci.h

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  1 /* SPDX-License-Identifier: GPL-2.0-or-later */
  2 #ifndef __SOUND_YMFPCI_H
  3 #define __SOUND_YMFPCI_H
  4 
  5 /*
  6  *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>
  7  *  Definitions for Yahama YMF724/740/744/754 chips
  8  */
  9 
 10 #include <sound/pcm.h>
 11 #include <sound/rawmidi.h>
 12 #include <sound/ac97_codec.h>
 13 #include <sound/timer.h>
 14 #include <linux/gameport.h>
 15 
 16 /*
 17  *  Direct registers
 18  */
 19 
 20 #define YMFREG(chip, reg)               (chip->port + YDSXGR_##reg)
 21 
 22 #define YDSXGR_INTFLAG                  0x0004
 23 #define YDSXGR_ACTIVITY                 0x0006
 24 #define YDSXGR_GLOBALCTRL               0x0008
 25 #define YDSXGR_ZVCTRL                   0x000A
 26 #define YDSXGR_TIMERCTRL                0x0010
 27 #define YDSXGR_TIMERCOUNT               0x0012
 28 #define YDSXGR_SPDIFOUTCTRL             0x0018
 29 #define YDSXGR_SPDIFOUTSTATUS           0x001C
 30 #define YDSXGR_EEPROMCTRL               0x0020
 31 #define YDSXGR_SPDIFINCTRL              0x0034
 32 #define YDSXGR_SPDIFINSTATUS            0x0038
 33 #define YDSXGR_DSPPROGRAMDL             0x0048
 34 #define YDSXGR_DLCNTRL                  0x004C
 35 #define YDSXGR_GPIOININTFLAG            0x0050
 36 #define YDSXGR_GPIOININTENABLE          0x0052
 37 #define YDSXGR_GPIOINSTATUS             0x0054
 38 #define YDSXGR_GPIOOUTCTRL              0x0056
 39 #define YDSXGR_GPIOFUNCENABLE           0x0058
 40 #define YDSXGR_GPIOTYPECONFIG           0x005A
 41 #define YDSXGR_AC97CMDDATA              0x0060
 42 #define YDSXGR_AC97CMDADR               0x0062
 43 #define YDSXGR_PRISTATUSDATA            0x0064
 44 #define YDSXGR_PRISTATUSADR             0x0066
 45 #define YDSXGR_SECSTATUSDATA            0x0068
 46 #define YDSXGR_SECSTATUSADR             0x006A
 47 #define YDSXGR_SECCONFIG                0x0070
 48 #define YDSXGR_LEGACYOUTVOL             0x0080
 49 #define YDSXGR_LEGACYOUTVOLL            0x0080
 50 #define YDSXGR_LEGACYOUTVOLR            0x0082
 51 #define YDSXGR_NATIVEDACOUTVOL          0x0084
 52 #define YDSXGR_NATIVEDACOUTVOLL         0x0084
 53 #define YDSXGR_NATIVEDACOUTVOLR         0x0086
 54 #define YDSXGR_ZVOUTVOL                 0x0088
 55 #define YDSXGR_ZVOUTVOLL                0x0088
 56 #define YDSXGR_ZVOUTVOLR                0x008A
 57 #define YDSXGR_SECADCOUTVOL             0x008C
 58 #define YDSXGR_SECADCOUTVOLL            0x008C
 59 #define YDSXGR_SECADCOUTVOLR            0x008E
 60 #define YDSXGR_PRIADCOUTVOL             0x0090
 61 #define YDSXGR_PRIADCOUTVOLL            0x0090
 62 #define YDSXGR_PRIADCOUTVOLR            0x0092
 63 #define YDSXGR_LEGACYLOOPVOL            0x0094
 64 #define YDSXGR_LEGACYLOOPVOLL           0x0094
 65 #define YDSXGR_LEGACYLOOPVOLR           0x0096
 66 #define YDSXGR_NATIVEDACLOOPVOL         0x0098
 67 #define YDSXGR_NATIVEDACLOOPVOLL        0x0098
 68 #define YDSXGR_NATIVEDACLOOPVOLR        0x009A
 69 #define YDSXGR_ZVLOOPVOL                0x009C
 70 #define YDSXGR_ZVLOOPVOLL               0x009E
 71 #define YDSXGR_ZVLOOPVOLR               0x009E
 72 #define YDSXGR_SECADCLOOPVOL            0x00A0
 73 #define YDSXGR_SECADCLOOPVOLL           0x00A0
 74 #define YDSXGR_SECADCLOOPVOLR           0x00A2
 75 #define YDSXGR_PRIADCLOOPVOL            0x00A4
 76 #define YDSXGR_PRIADCLOOPVOLL           0x00A4
 77 #define YDSXGR_PRIADCLOOPVOLR           0x00A6
 78 #define YDSXGR_NATIVEADCINVOL           0x00A8
 79 #define YDSXGR_NATIVEADCINVOLL          0x00A8
 80 #define YDSXGR_NATIVEADCINVOLR          0x00AA
 81 #define YDSXGR_NATIVEDACINVOL           0x00AC
 82 #define YDSXGR_NATIVEDACINVOLL          0x00AC
 83 #define YDSXGR_NATIVEDACINVOLR          0x00AE
 84 #define YDSXGR_BUF441OUTVOL             0x00B0
 85 #define YDSXGR_BUF441OUTVOLL            0x00B0
 86 #define YDSXGR_BUF441OUTVOLR            0x00B2
 87 #define YDSXGR_BUF441LOOPVOL            0x00B4
 88 #define YDSXGR_BUF441LOOPVOLL           0x00B4
 89 #define YDSXGR_BUF441LOOPVOLR           0x00B6
 90 #define YDSXGR_SPDIFOUTVOL              0x00B8
 91 #define YDSXGR_SPDIFOUTVOLL             0x00B8
 92 #define YDSXGR_SPDIFOUTVOLR             0x00BA
 93 #define YDSXGR_SPDIFLOOPVOL             0x00BC
 94 #define YDSXGR_SPDIFLOOPVOLL            0x00BC
 95 #define YDSXGR_SPDIFLOOPVOLR            0x00BE
 96 #define YDSXGR_ADCSLOTSR                0x00C0
 97 #define YDSXGR_RECSLOTSR                0x00C4
 98 #define YDSXGR_ADCFORMAT                0x00C8
 99 #define YDSXGR_RECFORMAT                0x00CC
100 #define YDSXGR_P44SLOTSR                0x00D0
101 #define YDSXGR_STATUS                   0x0100
102 #define YDSXGR_CTRLSELECT               0x0104
103 #define YDSXGR_MODE                     0x0108
104 #define YDSXGR_SAMPLECOUNT              0x010C
105 #define YDSXGR_NUMOFSAMPLES             0x0110
106 #define YDSXGR_CONFIG                   0x0114
107 #define YDSXGR_PLAYCTRLSIZE             0x0140
108 #define YDSXGR_RECCTRLSIZE              0x0144
109 #define YDSXGR_EFFCTRLSIZE              0x0148
110 #define YDSXGR_WORKSIZE                 0x014C
111 #define YDSXGR_MAPOFREC                 0x0150
112 #define YDSXGR_MAPOFEFFECT              0x0154
113 #define YDSXGR_PLAYCTRLBASE             0x0158
114 #define YDSXGR_RECCTRLBASE              0x015C
115 #define YDSXGR_EFFCTRLBASE              0x0160
116 #define YDSXGR_WORKBASE                 0x0164
117 #define YDSXGR_DSPINSTRAM               0x1000
118 #define YDSXGR_CTRLINSTRAM              0x4000
119 
120 #define YDSXG_AC97READCMD               0x8000
121 #define YDSXG_AC97WRITECMD              0x0000
122 
123 #define PCIR_DSXG_LEGACY                0x40
124 #define PCIR_DSXG_ELEGACY               0x42
125 #define PCIR_DSXG_CTRL                  0x48
126 #define PCIR_DSXG_PWRCTRL1              0x4a
127 #define PCIR_DSXG_PWRCTRL2              0x4e
128 #define PCIR_DSXG_FMBASE                0x60
129 #define PCIR_DSXG_SBBASE                0x62
130 #define PCIR_DSXG_MPU401BASE            0x64
131 #define PCIR_DSXG_JOYBASE               0x66
132 
133 #define YDSXG_DSPLENGTH                 0x0080
134 #define YDSXG_CTRLLENGTH                0x3000
135 
136 #define YDSXG_DEFAULT_WORK_SIZE         0x0400
137 
138 #define YDSXG_PLAYBACK_VOICES           64
139 #define YDSXG_CAPTURE_VOICES            2
140 #define YDSXG_EFFECT_VOICES             5
141 
142 #define YMFPCI_LEGACY_SBEN      (1 << 0)        /* soundblaster enable */
143 #define YMFPCI_LEGACY_FMEN      (1 << 1)        /* OPL3 enable */
144 #define YMFPCI_LEGACY_JPEN      (1 << 2)        /* joystick enable */
145 #define YMFPCI_LEGACY_MEN       (1 << 3)        /* MPU401 enable */
146 #define YMFPCI_LEGACY_MIEN      (1 << 4)        /* MPU RX irq enable */
147 #define YMFPCI_LEGACY_IOBITS    (1 << 5)        /* i/o bits range, 0 = 16bit, 1 =10bit */
148 #define YMFPCI_LEGACY_SDMA      (3 << 6)        /* SB DMA select */
149 #define YMFPCI_LEGACY_SBIRQ     (7 << 8)        /* SB IRQ select */
150 #define YMFPCI_LEGACY_MPUIRQ    (7 << 11)       /* MPU IRQ select */
151 #define YMFPCI_LEGACY_SIEN      (1 << 14)       /* serialized IRQ */
152 #define YMFPCI_LEGACY_LAD       (1 << 15)       /* legacy audio disable */
153 
154 #define YMFPCI_LEGACY2_FMIO     (3 << 0)        /* OPL3 i/o address (724/740) */
155 #define YMFPCI_LEGACY2_SBIO     (3 << 2)        /* SB i/o address (724/740) */
156 #define YMFPCI_LEGACY2_MPUIO    (3 << 4)        /* MPU401 i/o address (724/740) */
157 #define YMFPCI_LEGACY2_JSIO     (3 << 6)        /* joystick i/o address (724/740) */
158 #define YMFPCI_LEGACY2_MAIM     (1 << 8)        /* MPU401 ack intr mask */
159 #define YMFPCI_LEGACY2_SMOD     (3 << 11)       /* SB DMA mode */
160 #define YMFPCI_LEGACY2_SBVER    (3 << 13)       /* SB version select */
161 #define YMFPCI_LEGACY2_IMOD     (1 << 15)       /* legacy IRQ mode */
162 /* SIEN:IMOD 0:0 = legacy irq, 0:1 = INTA, 1:0 = serialized IRQ */
163 
164 #if IS_REACHABLE(CONFIG_GAMEPORT)
165 #define SUPPORT_JOYSTICK
166 #endif
167 
168 /*
169  *
170  */
171 
172 struct snd_ymfpci_playback_bank {
173         __le32 format;
174         __le32 loop_default;
175         __le32 base;                    /* 32-bit address */
176         __le32 loop_start;              /* 32-bit offset */
177         __le32 loop_end;                /* 32-bit offset */
178         __le32 loop_frac;               /* 8-bit fraction - loop_start */
179         __le32 delta_end;               /* pitch delta end */
180         __le32 lpfK_end;
181         __le32 eg_gain_end;
182         __le32 left_gain_end;
183         __le32 right_gain_end;
184         __le32 eff1_gain_end;
185         __le32 eff2_gain_end;
186         __le32 eff3_gain_end;
187         __le32 lpfQ;
188         __le32 status;
189         __le32 num_of_frames;
190         __le32 loop_count;
191         __le32 start;
192         __le32 start_frac;
193         __le32 delta;
194         __le32 lpfK;
195         __le32 eg_gain;
196         __le32 left_gain;
197         __le32 right_gain;
198         __le32 eff1_gain;
199         __le32 eff2_gain;
200         __le32 eff3_gain;
201         __le32 lpfD1;
202         __le32 lpfD2;
203  };
204 
205 struct snd_ymfpci_capture_bank {
206         __le32 base;                    /* 32-bit address */
207         __le32 loop_end;                /* 32-bit offset */
208         __le32 start;                   /* 32-bit offset */
209         __le32 num_of_loops;            /* counter */
210 };
211 
212 struct snd_ymfpci_effect_bank {
213         __le32 base;                    /* 32-bit address */
214         __le32 loop_end;                /* 32-bit offset */
215         __le32 start;                   /* 32-bit offset */
216         __le32 temp;
217 };
218 
219 struct snd_ymfpci_pcm;
220 struct snd_ymfpci;
221 
222 enum snd_ymfpci_voice_type {
223         YMFPCI_PCM,
224         YMFPCI_SYNTH,
225         YMFPCI_MIDI
226 };
227 
228 struct snd_ymfpci_voice {
229         struct snd_ymfpci *chip;
230         int number;
231         unsigned int use: 1,
232             pcm: 1,
233             synth: 1,
234             midi: 1;
235         struct snd_ymfpci_playback_bank *bank;
236         dma_addr_t bank_addr;
237         void (*interrupt)(struct snd_ymfpci *chip, struct snd_ymfpci_voice *voice);
238         struct snd_ymfpci_pcm *ypcm;
239 };
240 
241 enum snd_ymfpci_pcm_type {
242         PLAYBACK_VOICE,
243         CAPTURE_REC,
244         CAPTURE_AC97,
245         EFFECT_DRY_LEFT,
246         EFFECT_DRY_RIGHT,
247         EFFECT_EFF1,
248         EFFECT_EFF2,
249         EFFECT_EFF3
250 };
251 
252 struct snd_ymfpci_pcm {
253         struct snd_ymfpci *chip;
254         enum snd_ymfpci_pcm_type type;
255         struct snd_pcm_substream *substream;
256         struct snd_ymfpci_voice *voices[2];     /* playback only */
257         unsigned int running: 1,
258                      use_441_slot: 1,
259                      output_front: 1,
260                      output_rear: 1,
261                      swap_rear: 1;
262         unsigned int update_pcm_vol;
263         u32 period_size;                /* cached from runtime->period_size */
264         u32 buffer_size;                /* cached from runtime->buffer_size */
265         u32 period_pos;
266         u32 last_pos;
267         u32 capture_bank_number;
268         u32 shift;
269 };
270 
271 struct snd_ymfpci {
272         int irq;
273 
274         unsigned int device_id; /* PCI device ID */
275         unsigned char rev;      /* PCI revision */
276         unsigned long reg_area_phys;
277         void __iomem *reg_area_virt;
278         struct resource *res_reg_area;
279         struct resource *fm_res;
280         struct resource *mpu_res;
281 
282         unsigned short old_legacy_ctrl;
283 #ifdef SUPPORT_JOYSTICK
284         struct gameport *gameport;
285 #endif
286 
287         struct snd_dma_buffer work_ptr;
288 
289         unsigned int bank_size_playback;
290         unsigned int bank_size_capture;
291         unsigned int bank_size_effect;
292         unsigned int work_size;
293 
294         void *bank_base_playback;
295         void *bank_base_capture;
296         void *bank_base_effect;
297         void *work_base;
298         dma_addr_t bank_base_playback_addr;
299         dma_addr_t bank_base_capture_addr;
300         dma_addr_t bank_base_effect_addr;
301         dma_addr_t work_base_addr;
302         struct snd_dma_buffer ac3_tmp_base;
303 
304         __le32 *ctrl_playback;
305         struct snd_ymfpci_playback_bank *bank_playback[YDSXG_PLAYBACK_VOICES][2];
306         struct snd_ymfpci_capture_bank *bank_capture[YDSXG_CAPTURE_VOICES][2];
307         struct snd_ymfpci_effect_bank *bank_effect[YDSXG_EFFECT_VOICES][2];
308 
309         int start_count;
310 
311         u32 active_bank;
312         struct snd_ymfpci_voice voices[64];
313         int src441_used;
314 
315         struct snd_ac97_bus *ac97_bus;
316         struct snd_ac97 *ac97;
317         struct snd_rawmidi *rawmidi;
318         struct snd_timer *timer;
319         unsigned int timer_ticks;
320 
321         struct pci_dev *pci;
322         struct snd_card *card;
323         struct snd_pcm *pcm;
324         struct snd_pcm *pcm2;
325         struct snd_pcm *pcm_spdif;
326         struct snd_pcm *pcm_4ch;
327         struct snd_pcm_substream *capture_substream[YDSXG_CAPTURE_VOICES];
328         struct snd_pcm_substream *effect_substream[YDSXG_EFFECT_VOICES];
329         struct snd_kcontrol *ctl_vol_recsrc;
330         struct snd_kcontrol *ctl_vol_adcrec;
331         struct snd_kcontrol *ctl_vol_spdifrec;
332         unsigned short spdif_bits, spdif_pcm_bits;
333         struct snd_kcontrol *spdif_pcm_ctl;
334         int mode_dup4ch;
335         int rear_opened;
336         int spdif_opened;
337         struct snd_ymfpci_pcm_mixer {
338                 u16 left;
339                 u16 right;
340                 struct snd_kcontrol *ctl;
341         } pcm_mixer[32];
342 
343         spinlock_t reg_lock;
344         spinlock_t voice_lock;
345         wait_queue_head_t interrupt_sleep;
346         atomic_t interrupt_sleep_count;
347         struct snd_info_entry *proc_entry;
348         const struct firmware *dsp_microcode;
349         const struct firmware *controller_microcode;
350 
351 #ifdef CONFIG_PM_SLEEP
352         u32 *saved_regs;
353         u32 saved_ydsxgr_mode;
354         u16 saved_dsxg_legacy;
355         u16 saved_dsxg_elegacy;
356 #endif
357 };
358 
359 int snd_ymfpci_create(struct snd_card *card,
360                       struct pci_dev *pci,
361                       unsigned short old_legacy_ctrl,
362                       struct snd_ymfpci ** rcodec);
363 void snd_ymfpci_free_gameport(struct snd_ymfpci *chip);
364 
365 extern const struct dev_pm_ops snd_ymfpci_pm;
366 
367 int snd_ymfpci_pcm(struct snd_ymfpci *chip, int device);
368 int snd_ymfpci_pcm2(struct snd_ymfpci *chip, int device);
369 int snd_ymfpci_pcm_spdif(struct snd_ymfpci *chip, int device);
370 int snd_ymfpci_pcm_4ch(struct snd_ymfpci *chip, int device);
371 int snd_ymfpci_mixer(struct snd_ymfpci *chip, int rear_switch);
372 int snd_ymfpci_timer(struct snd_ymfpci *chip, int device);
373 
374 #endif /* __SOUND_YMFPCI_H */
375 

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