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Linux/sound/soc/amd/acp-pcm-dma.c

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  1 /*
  2  * AMD ALSA SoC PCM Driver for ACP 2.x
  3  *
  4  * Copyright 2014-2015 Advanced Micro Devices, Inc.
  5  *
  6  * This program is free software; you can redistribute it and/or modify it
  7  * under the terms and conditions of the GNU General Public License,
  8  * version 2, as published by the Free Software Foundation.
  9  *
 10  * This program is distributed in the hope it will be useful, but WITHOUT
 11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 13  * more details.
 14  */
 15 
 16 #include <linux/module.h>
 17 #include <linux/delay.h>
 18 #include <linux/io.h>
 19 #include <linux/iopoll.h>
 20 #include <linux/sizes.h>
 21 #include <linux/pm_runtime.h>
 22 
 23 #include <sound/soc.h>
 24 #include <drm/amd_asic_type.h>
 25 #include "acp.h"
 26 
 27 #define DRV_NAME "acp_audio_dma"
 28 
 29 #define PLAYBACK_MIN_NUM_PERIODS    2
 30 #define PLAYBACK_MAX_NUM_PERIODS    2
 31 #define PLAYBACK_MAX_PERIOD_SIZE    16384
 32 #define PLAYBACK_MIN_PERIOD_SIZE    1024
 33 #define CAPTURE_MIN_NUM_PERIODS     2
 34 #define CAPTURE_MAX_NUM_PERIODS     2
 35 #define CAPTURE_MAX_PERIOD_SIZE     16384
 36 #define CAPTURE_MIN_PERIOD_SIZE     1024
 37 
 38 #define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)
 39 #define MIN_BUFFER MAX_BUFFER
 40 
 41 #define ST_PLAYBACK_MAX_PERIOD_SIZE 4096
 42 #define ST_CAPTURE_MAX_PERIOD_SIZE  ST_PLAYBACK_MAX_PERIOD_SIZE
 43 #define ST_MAX_BUFFER (ST_PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)
 44 #define ST_MIN_BUFFER ST_MAX_BUFFER
 45 
 46 #define DRV_NAME "acp_audio_dma"
 47 bool bt_uart_enable = true;
 48 EXPORT_SYMBOL(bt_uart_enable);
 49 
 50 static const struct snd_pcm_hardware acp_pcm_hardware_playback = {
 51         .info = SNDRV_PCM_INFO_INTERLEAVED |
 52                 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
 53                 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
 54                 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
 55         .formats = SNDRV_PCM_FMTBIT_S16_LE |
 56                 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
 57         .channels_min = 1,
 58         .channels_max = 8,
 59         .rates = SNDRV_PCM_RATE_8000_96000,
 60         .rate_min = 8000,
 61         .rate_max = 96000,
 62         .buffer_bytes_max = PLAYBACK_MAX_NUM_PERIODS * PLAYBACK_MAX_PERIOD_SIZE,
 63         .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE,
 64         .period_bytes_max = PLAYBACK_MAX_PERIOD_SIZE,
 65         .periods_min = PLAYBACK_MIN_NUM_PERIODS,
 66         .periods_max = PLAYBACK_MAX_NUM_PERIODS,
 67 };
 68 
 69 static const struct snd_pcm_hardware acp_pcm_hardware_capture = {
 70         .info = SNDRV_PCM_INFO_INTERLEAVED |
 71                 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
 72                 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
 73             SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
 74         .formats = SNDRV_PCM_FMTBIT_S16_LE |
 75                 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
 76         .channels_min = 1,
 77         .channels_max = 2,
 78         .rates = SNDRV_PCM_RATE_8000_48000,
 79         .rate_min = 8000,
 80         .rate_max = 48000,
 81         .buffer_bytes_max = CAPTURE_MAX_NUM_PERIODS * CAPTURE_MAX_PERIOD_SIZE,
 82         .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE,
 83         .period_bytes_max = CAPTURE_MAX_PERIOD_SIZE,
 84         .periods_min = CAPTURE_MIN_NUM_PERIODS,
 85         .periods_max = CAPTURE_MAX_NUM_PERIODS,
 86 };
 87 
 88 static const struct snd_pcm_hardware acp_st_pcm_hardware_playback = {
 89         .info = SNDRV_PCM_INFO_INTERLEAVED |
 90                 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
 91                 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
 92                 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
 93         .formats = SNDRV_PCM_FMTBIT_S16_LE |
 94                 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
 95         .channels_min = 1,
 96         .channels_max = 8,
 97         .rates = SNDRV_PCM_RATE_8000_96000,
 98         .rate_min = 8000,
 99         .rate_max = 96000,
100         .buffer_bytes_max = ST_MAX_BUFFER,
101         .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE,
102         .period_bytes_max = ST_PLAYBACK_MAX_PERIOD_SIZE,
103         .periods_min = PLAYBACK_MIN_NUM_PERIODS,
104         .periods_max = PLAYBACK_MAX_NUM_PERIODS,
105 };
106 
107 static const struct snd_pcm_hardware acp_st_pcm_hardware_capture = {
108         .info = SNDRV_PCM_INFO_INTERLEAVED |
109                 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
110                 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
111                 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
112         .formats = SNDRV_PCM_FMTBIT_S16_LE |
113                 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
114         .channels_min = 1,
115         .channels_max = 2,
116         .rates = SNDRV_PCM_RATE_8000_48000,
117         .rate_min = 8000,
118         .rate_max = 48000,
119         .buffer_bytes_max = ST_MAX_BUFFER,
120         .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE,
121         .period_bytes_max = ST_CAPTURE_MAX_PERIOD_SIZE,
122         .periods_min = CAPTURE_MIN_NUM_PERIODS,
123         .periods_max = CAPTURE_MAX_NUM_PERIODS,
124 };
125 
126 static u32 acp_reg_read(void __iomem *acp_mmio, u32 reg)
127 {
128         return readl(acp_mmio + (reg * 4));
129 }
130 
131 static void acp_reg_write(u32 val, void __iomem *acp_mmio, u32 reg)
132 {
133         writel(val, acp_mmio + (reg * 4));
134 }
135 
136 /*
137  * Configure a given dma channel parameters - enable/disable,
138  * number of descriptors, priority
139  */
140 static void config_acp_dma_channel(void __iomem *acp_mmio, u8 ch_num,
141                                    u16 dscr_strt_idx, u16 num_dscrs,
142                                    enum acp_dma_priority_level priority_level)
143 {
144         u32 dma_ctrl;
145 
146         /* disable the channel run field */
147         dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
148         dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK;
149         acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
150 
151         /* program a DMA channel with first descriptor to be processed. */
152         acp_reg_write((ACP_DMA_DSCR_STRT_IDX_0__DMAChDscrStrtIdx_MASK
153                         & dscr_strt_idx),
154                         acp_mmio, mmACP_DMA_DSCR_STRT_IDX_0 + ch_num);
155 
156         /*
157          * program a DMA channel with the number of descriptors to be
158          * processed in the transfer
159          */
160         acp_reg_write(ACP_DMA_DSCR_CNT_0__DMAChDscrCnt_MASK & num_dscrs,
161                       acp_mmio, mmACP_DMA_DSCR_CNT_0 + ch_num);
162 
163         /* set DMA channel priority */
164         acp_reg_write(priority_level, acp_mmio, mmACP_DMA_PRIO_0 + ch_num);
165 }
166 
167 /* Initialize a dma descriptor in SRAM based on descritor information passed */
168 static void config_dma_descriptor_in_sram(void __iomem *acp_mmio,
169                                           u16 descr_idx,
170                                           acp_dma_dscr_transfer_t *descr_info)
171 {
172         u32 sram_offset;
173 
174         sram_offset = (descr_idx * sizeof(acp_dma_dscr_transfer_t));
175 
176         /* program the source base address. */
177         acp_reg_write(sram_offset, acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
178         acp_reg_write(descr_info->src,  acp_mmio, mmACP_SRBM_Targ_Idx_Data);
179         /* program the destination base address. */
180         acp_reg_write(sram_offset + 4,  acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
181         acp_reg_write(descr_info->dest, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
182 
183         /* program the number of bytes to be transferred for this descriptor. */
184         acp_reg_write(sram_offset + 8,  acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
185         acp_reg_write(descr_info->xfer_val, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
186 }
187 
188 static void pre_config_reset(void __iomem *acp_mmio, u16 ch_num)
189 {
190         u32 dma_ctrl;
191         int ret;
192 
193         /* clear the reset bit */
194         dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
195         dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRst_MASK;
196         acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
197         /* check the reset bit before programming configuration registers */
198         ret = readl_poll_timeout(acp_mmio + ((mmACP_DMA_CNTL_0 + ch_num) * 4),
199                                  dma_ctrl,
200                                  !(dma_ctrl & ACP_DMA_CNTL_0__DMAChRst_MASK),
201                                  100, ACP_DMA_RESET_TIME);
202         if (ret < 0)
203                 pr_err("Failed to clear reset of channel : %d\n", ch_num);
204 }
205 
206 /*
207  * Initialize the DMA descriptor information for transfer between
208  * system memory <-> ACP SRAM
209  */
210 static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio,
211                                            u32 size, int direction,
212                                            u32 pte_offset, u16 ch,
213                                            u32 sram_bank, u16 dma_dscr_idx,
214                                            u32 asic_type)
215 {
216         u16 i;
217         acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL];
218 
219         for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) {
220                 dmadscr[i].xfer_val = 0;
221                 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
222                         dma_dscr_idx = dma_dscr_idx + i;
223                         dmadscr[i].dest = sram_bank + (i * (size / 2));
224                         dmadscr[i].src = ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS
225                                 + (pte_offset * SZ_4K) + (i * (size / 2));
226                         switch (asic_type) {
227                         case CHIP_STONEY:
228                                 dmadscr[i].xfer_val |=
229                                 (ACP_DMA_ATTR_DAGB_GARLIC_TO_SHAREDMEM  << 16) |
230                                 (size / 2);
231                                 break;
232                         default:
233                                 dmadscr[i].xfer_val |=
234                                 (ACP_DMA_ATTR_DAGB_ONION_TO_SHAREDMEM  << 16) |
235                                 (size / 2);
236                         }
237                 } else {
238                         dma_dscr_idx = dma_dscr_idx + i;
239                         dmadscr[i].src = sram_bank + (i * (size / 2));
240                         dmadscr[i].dest =
241                         ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS +
242                         (pte_offset * SZ_4K) + (i * (size / 2));
243                         switch (asic_type) {
244                         case CHIP_STONEY:
245                                 dmadscr[i].xfer_val |=
246                                 BIT(22) |
247                                 (ACP_DMA_ATTR_SHARED_MEM_TO_DAGB_GARLIC << 16) |
248                                 (size / 2);
249                                 break;
250                         default:
251                                 dmadscr[i].xfer_val |=
252                                 BIT(22) |
253                                 (ACP_DMA_ATTR_SHAREDMEM_TO_DAGB_ONION << 16) |
254                                 (size / 2);
255                         }
256                 }
257                 config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx,
258                                               &dmadscr[i]);
259         }
260         pre_config_reset(acp_mmio, ch);
261         config_acp_dma_channel(acp_mmio, ch,
262                                dma_dscr_idx - 1,
263                                NUM_DSCRS_PER_CHANNEL,
264                                ACP_DMA_PRIORITY_LEVEL_NORMAL);
265 }
266 
267 /*
268  * Initialize the DMA descriptor information for transfer between
269  * ACP SRAM <-> I2S
270  */
271 static void set_acp_to_i2s_dma_descriptors(void __iomem *acp_mmio, u32 size,
272                                            int direction, u32 sram_bank,
273                                            u16 destination, u16 ch,
274                                            u16 dma_dscr_idx, u32 asic_type)
275 {
276         u16 i;
277         acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL];
278 
279         for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) {
280                 dmadscr[i].xfer_val = 0;
281                 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
282                         dma_dscr_idx = dma_dscr_idx + i;
283                         dmadscr[i].src = sram_bank  + (i * (size / 2));
284                         /* dmadscr[i].dest is unused by hardware. */
285                         dmadscr[i].dest = 0;
286                         dmadscr[i].xfer_val |= BIT(22) | (destination << 16) |
287                                                 (size / 2);
288                 } else {
289                         dma_dscr_idx = dma_dscr_idx + i;
290                         /* dmadscr[i].src is unused by hardware. */
291                         dmadscr[i].src = 0;
292                         dmadscr[i].dest =
293                                  sram_bank + (i * (size / 2));
294                         dmadscr[i].xfer_val |= BIT(22) |
295                                 (destination << 16) | (size / 2);
296                 }
297                 config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx,
298                                               &dmadscr[i]);
299         }
300         pre_config_reset(acp_mmio, ch);
301         /* Configure the DMA channel with the above descriptore */
302         config_acp_dma_channel(acp_mmio, ch, dma_dscr_idx - 1,
303                                NUM_DSCRS_PER_CHANNEL,
304                                ACP_DMA_PRIORITY_LEVEL_NORMAL);
305 }
306 
307 /* Create page table entries in ACP SRAM for the allocated memory */
308 static void acp_pte_config(void __iomem *acp_mmio, struct page *pg,
309                            u16 num_of_pages, u32 pte_offset)
310 {
311         u16 page_idx;
312         u64 addr;
313         u32 low;
314         u32 high;
315         u32 offset;
316 
317         offset  = ACP_DAGB_GRP_SRBM_SRAM_BASE_OFFSET + (pte_offset * 8);
318         for (page_idx = 0; page_idx < (num_of_pages); page_idx++) {
319                 /* Load the low address of page int ACP SRAM through SRBM */
320                 acp_reg_write((offset + (page_idx * 8)),
321                               acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
322                 addr = page_to_phys(pg);
323 
324                 low = lower_32_bits(addr);
325                 high = upper_32_bits(addr);
326 
327                 acp_reg_write(low, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
328 
329                 /* Load the High address of page int ACP SRAM through SRBM */
330                 acp_reg_write((offset + (page_idx * 8) + 4),
331                               acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
332 
333                 /* page enable in ACP */
334                 high |= BIT(31);
335                 acp_reg_write(high, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
336 
337                 /* Move to next physically contiguos page */
338                 pg++;
339         }
340 }
341 
342 static void config_acp_dma(void __iomem *acp_mmio,
343                            struct audio_substream_data *rtd,
344                            u32 asic_type)
345 {
346         acp_pte_config(acp_mmio, rtd->pg, rtd->num_of_pages,
347                        rtd->pte_offset);
348         /* Configure System memory <-> ACP SRAM DMA descriptors */
349         set_acp_sysmem_dma_descriptors(acp_mmio, rtd->size,
350                                        rtd->direction, rtd->pte_offset,
351                                        rtd->ch1, rtd->sram_bank,
352                                        rtd->dma_dscr_idx_1, asic_type);
353         /* Configure ACP SRAM <-> I2S DMA descriptors */
354         set_acp_to_i2s_dma_descriptors(acp_mmio, rtd->size,
355                                        rtd->direction, rtd->sram_bank,
356                                        rtd->destination, rtd->ch2,
357                                        rtd->dma_dscr_idx_2, asic_type);
358 }
359 
360 /* Start a given DMA channel transfer */
361 static void acp_dma_start(void __iomem *acp_mmio, u16 ch_num)
362 {
363         u32 dma_ctrl;
364 
365         /* read the dma control register and disable the channel run field */
366         dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
367 
368         /* Invalidating the DAGB cache */
369         acp_reg_write(1, acp_mmio, mmACP_DAGB_ATU_CTRL);
370 
371         /*
372          * configure the DMA channel and start the DMA transfer
373          * set dmachrun bit to start the transfer and enable the
374          * interrupt on completion of the dma transfer
375          */
376         dma_ctrl |= ACP_DMA_CNTL_0__DMAChRun_MASK;
377 
378         switch (ch_num) {
379         case ACP_TO_I2S_DMA_CH_NUM:
380         case ACP_TO_SYSRAM_CH_NUM:
381         case I2S_TO_ACP_DMA_CH_NUM:
382         case ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM:
383         case ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM:
384         case I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM:
385                 dma_ctrl |= ACP_DMA_CNTL_0__DMAChIOCEn_MASK;
386                 break;
387         default:
388                 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK;
389                 break;
390         }
391 
392         /* circular for both DMA channel */
393         dma_ctrl |= ACP_DMA_CNTL_0__Circular_DMA_En_MASK;
394 
395         acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
396 }
397 
398 /* Stop a given DMA channel transfer */
399 static int acp_dma_stop(void __iomem *acp_mmio, u8 ch_num)
400 {
401         u32 dma_ctrl;
402         u32 dma_ch_sts;
403         u32 count = ACP_DMA_RESET_TIME;
404 
405         dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
406 
407         /*
408          * clear the dma control register fields before writing zero
409          * in reset bit
410          */
411         dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK;
412         dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK;
413 
414         acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
415         dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS);
416 
417         if (dma_ch_sts & BIT(ch_num)) {
418                 /*
419                  * set the reset bit for this channel to stop the dma
420                  *  transfer
421                  */
422                 dma_ctrl |= ACP_DMA_CNTL_0__DMAChRst_MASK;
423                 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
424         }
425 
426         /* check the channel status bit for some time and return the status */
427         while (true) {
428                 dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS);
429                 if (!(dma_ch_sts & BIT(ch_num))) {
430                         /*
431                          * clear the reset flag after successfully stopping
432                          * the dma transfer and break from the loop
433                          */
434                         dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRst_MASK;
435 
436                         acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0
437                                       + ch_num);
438                         break;
439                 }
440                 if (--count == 0) {
441                         pr_err("Failed to stop ACP DMA channel : %d\n", ch_num);
442                         return -ETIMEDOUT;
443                 }
444                 udelay(100);
445         }
446         return 0;
447 }
448 
449 static void acp_set_sram_bank_state(void __iomem *acp_mmio, u16 bank,
450                                     bool power_on)
451 {
452         u32 val, req_reg, sts_reg, sts_reg_mask;
453         u32 loops = 1000;
454 
455         if (bank < 32) {
456                 req_reg = mmACP_MEM_SHUT_DOWN_REQ_LO;
457                 sts_reg = mmACP_MEM_SHUT_DOWN_STS_LO;
458                 sts_reg_mask = 0xFFFFFFFF;
459 
460         } else {
461                 bank -= 32;
462                 req_reg = mmACP_MEM_SHUT_DOWN_REQ_HI;
463                 sts_reg = mmACP_MEM_SHUT_DOWN_STS_HI;
464                 sts_reg_mask = 0x0000FFFF;
465         }
466 
467         val = acp_reg_read(acp_mmio, req_reg);
468         if (val & (1 << bank)) {
469                 /* bank is in off state */
470                 if (power_on == true)
471                         /* request to on */
472                         val &= ~(1 << bank);
473                 else
474                         /* request to off */
475                         return;
476         } else {
477                 /* bank is in on state */
478                 if (power_on == false)
479                         /* request to off */
480                         val |= 1 << bank;
481                 else
482                         /* request to on */
483                         return;
484         }
485         acp_reg_write(val, acp_mmio, req_reg);
486 
487         while (acp_reg_read(acp_mmio, sts_reg) != sts_reg_mask) {
488                 if (!loops--) {
489                         pr_err("ACP SRAM bank %d state change failed\n", bank);
490                         break;
491                 }
492                 cpu_relax();
493         }
494 }
495 
496 /* Initialize and bring ACP hardware to default state. */
497 static int acp_init(void __iomem *acp_mmio, u32 asic_type)
498 {
499         u16 bank;
500         u32 val, count, sram_pte_offset;
501 
502         /* Assert Soft reset of ACP */
503         val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
504 
505         val |= ACP_SOFT_RESET__SoftResetAud_MASK;
506         acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET);
507 
508         count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE;
509         while (true) {
510                 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
511                 if (ACP_SOFT_RESET__SoftResetAudDone_MASK ==
512                     (val & ACP_SOFT_RESET__SoftResetAudDone_MASK))
513                         break;
514                 if (--count == 0) {
515                         pr_err("Failed to reset ACP\n");
516                         return -ETIMEDOUT;
517                 }
518                 udelay(100);
519         }
520 
521         /* Enable clock to ACP and wait until the clock is enabled */
522         val = acp_reg_read(acp_mmio, mmACP_CONTROL);
523         val = val | ACP_CONTROL__ClkEn_MASK;
524         acp_reg_write(val, acp_mmio, mmACP_CONTROL);
525 
526         count = ACP_CLOCK_EN_TIME_OUT_VALUE;
527 
528         while (true) {
529                 val = acp_reg_read(acp_mmio, mmACP_STATUS);
530                 if (val & (u32)0x1)
531                         break;
532                 if (--count == 0) {
533                         pr_err("Failed to reset ACP\n");
534                         return -ETIMEDOUT;
535                 }
536                 udelay(100);
537         }
538 
539         /* Deassert the SOFT RESET flags */
540         val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
541         val &= ~ACP_SOFT_RESET__SoftResetAud_MASK;
542         acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET);
543 
544         /* For BT instance change pins from UART to BT */
545         if (!bt_uart_enable) {
546                 val = acp_reg_read(acp_mmio, mmACP_BT_UART_PAD_SEL);
547                 val |= ACP_BT_UART_PAD_SELECT_MASK;
548                 acp_reg_write(val, acp_mmio, mmACP_BT_UART_PAD_SEL);
549         }
550 
551         /* initiailize Onion control DAGB register */
552         acp_reg_write(ACP_ONION_CNTL_DEFAULT, acp_mmio,
553                       mmACP_AXI2DAGB_ONION_CNTL);
554 
555         /* initiailize Garlic control DAGB registers */
556         acp_reg_write(ACP_GARLIC_CNTL_DEFAULT, acp_mmio,
557                       mmACP_AXI2DAGB_GARLIC_CNTL);
558 
559         sram_pte_offset = ACP_DAGB_GRP_SRAM_BASE_ADDRESS |
560                         ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBSnoopSel_MASK |
561                         ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBTargetMemSel_MASK |
562                         ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBGrpEnable_MASK;
563         acp_reg_write(sram_pte_offset,  acp_mmio, mmACP_DAGB_BASE_ADDR_GRP_1);
564         acp_reg_write(ACP_PAGE_SIZE_4K_ENABLE, acp_mmio,
565                       mmACP_DAGB_PAGE_SIZE_GRP_1);
566 
567         acp_reg_write(ACP_SRAM_BASE_ADDRESS, acp_mmio,
568                       mmACP_DMA_DESC_BASE_ADDR);
569 
570         /* Num of descriptiors in SRAM 0x4, means 256 descriptors;(64 * 4) */
571         acp_reg_write(0x4, acp_mmio, mmACP_DMA_DESC_MAX_NUM_DSCR);
572         acp_reg_write(ACP_EXTERNAL_INTR_CNTL__DMAIOCMask_MASK,
573                       acp_mmio, mmACP_EXTERNAL_INTR_CNTL);
574 
575        /*
576         * When ACP_TILE_P1 is turned on, all SRAM banks get turned on.
577         * Now, turn off all of them. This can't be done in 'poweron' of
578         * ACP pm domain, as this requires ACP to be initialized.
579         * For Stoney, Memory gating is disabled,i.e SRAM Banks
580         * won't be turned off. The default state for SRAM banks is ON.
581         * Setting SRAM bank state code skipped for STONEY platform.
582         */
583         if (asic_type != CHIP_STONEY) {
584                 for (bank = 1; bank < 48; bank++)
585                         acp_set_sram_bank_state(acp_mmio, bank, false);
586         }
587         return 0;
588 }
589 
590 /* Deinitialize ACP */
591 static int acp_deinit(void __iomem *acp_mmio)
592 {
593         u32 val;
594         u32 count;
595 
596         /* Assert Soft reset of ACP */
597         val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
598 
599         val |= ACP_SOFT_RESET__SoftResetAud_MASK;
600         acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET);
601 
602         count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE;
603         while (true) {
604                 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
605                 if (ACP_SOFT_RESET__SoftResetAudDone_MASK ==
606                     (val & ACP_SOFT_RESET__SoftResetAudDone_MASK))
607                         break;
608                 if (--count == 0) {
609                         pr_err("Failed to reset ACP\n");
610                         return -ETIMEDOUT;
611                 }
612                 udelay(100);
613         }
614         /* Disable ACP clock */
615         val = acp_reg_read(acp_mmio, mmACP_CONTROL);
616         val &= ~ACP_CONTROL__ClkEn_MASK;
617         acp_reg_write(val, acp_mmio, mmACP_CONTROL);
618 
619         count = ACP_CLOCK_EN_TIME_OUT_VALUE;
620 
621         while (true) {
622                 val = acp_reg_read(acp_mmio, mmACP_STATUS);
623                 if (!(val & (u32)0x1))
624                         break;
625                 if (--count == 0) {
626                         pr_err("Failed to reset ACP\n");
627                         return -ETIMEDOUT;
628                 }
629                 udelay(100);
630         }
631         return 0;
632 }
633 
634 /* ACP DMA irq handler routine for playback, capture usecases */
635 static irqreturn_t dma_irq_handler(int irq, void *arg)
636 {
637         u32 intr_flag, ext_intr_status;
638         struct audio_drv_data *irq_data;
639         void __iomem *acp_mmio;
640         struct device *dev = arg;
641         bool valid_irq = false;
642 
643         irq_data = dev_get_drvdata(dev);
644         acp_mmio = irq_data->acp_mmio;
645 
646         ext_intr_status = acp_reg_read(acp_mmio, mmACP_EXTERNAL_INTR_STAT);
647         intr_flag = (((ext_intr_status &
648                       ACP_EXTERNAL_INTR_STAT__DMAIOCStat_MASK) >>
649                      ACP_EXTERNAL_INTR_STAT__DMAIOCStat__SHIFT));
650 
651         if ((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) != 0) {
652                 valid_irq = true;
653                 snd_pcm_period_elapsed(irq_data->play_i2ssp_stream);
654                 acp_reg_write((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) << 16,
655                               acp_mmio, mmACP_EXTERNAL_INTR_STAT);
656         }
657 
658         if ((intr_flag & BIT(ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM)) != 0) {
659                 valid_irq = true;
660                 snd_pcm_period_elapsed(irq_data->play_i2sbt_stream);
661                 acp_reg_write((intr_flag &
662                               BIT(ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM)) << 16,
663                               acp_mmio, mmACP_EXTERNAL_INTR_STAT);
664         }
665 
666         if ((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) != 0) {
667                 valid_irq = true;
668                 snd_pcm_period_elapsed(irq_data->capture_i2ssp_stream);
669                 acp_reg_write((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) << 16,
670                               acp_mmio, mmACP_EXTERNAL_INTR_STAT);
671         }
672 
673         if ((intr_flag & BIT(ACP_TO_SYSRAM_CH_NUM)) != 0) {
674                 valid_irq = true;
675                 acp_reg_write((intr_flag & BIT(ACP_TO_SYSRAM_CH_NUM)) << 16,
676                               acp_mmio, mmACP_EXTERNAL_INTR_STAT);
677         }
678 
679         if ((intr_flag & BIT(I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM)) != 0) {
680                 valid_irq = true;
681                 snd_pcm_period_elapsed(irq_data->capture_i2sbt_stream);
682                 acp_reg_write((intr_flag &
683                               BIT(I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM)) << 16,
684                               acp_mmio, mmACP_EXTERNAL_INTR_STAT);
685         }
686 
687         if ((intr_flag & BIT(ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM)) != 0) {
688                 valid_irq = true;
689                 acp_reg_write((intr_flag &
690                               BIT(ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM)) << 16,
691                               acp_mmio, mmACP_EXTERNAL_INTR_STAT);
692         }
693 
694         if (valid_irq)
695                 return IRQ_HANDLED;
696         else
697                 return IRQ_NONE;
698 }
699 
700 static int acp_dma_open(struct snd_pcm_substream *substream)
701 {
702         u16 bank;
703         int ret = 0;
704         struct snd_pcm_runtime *runtime = substream->runtime;
705         struct snd_soc_pcm_runtime *prtd = substream->private_data;
706         struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd,
707                                                                     DRV_NAME);
708         struct audio_drv_data *intr_data = dev_get_drvdata(component->dev);
709         struct audio_substream_data *adata =
710                 kzalloc(sizeof(struct audio_substream_data), GFP_KERNEL);
711         if (!adata)
712                 return -ENOMEM;
713 
714         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
715                 switch (intr_data->asic_type) {
716                 case CHIP_STONEY:
717                         runtime->hw = acp_st_pcm_hardware_playback;
718                         break;
719                 default:
720                         runtime->hw = acp_pcm_hardware_playback;
721                 }
722         } else {
723                 switch (intr_data->asic_type) {
724                 case CHIP_STONEY:
725                         runtime->hw = acp_st_pcm_hardware_capture;
726                         break;
727                 default:
728                         runtime->hw = acp_pcm_hardware_capture;
729                 }
730         }
731 
732         ret = snd_pcm_hw_constraint_integer(runtime,
733                                             SNDRV_PCM_HW_PARAM_PERIODS);
734         if (ret < 0) {
735                 dev_err(component->dev, "set integer constraint failed\n");
736                 kfree(adata);
737                 return ret;
738         }
739 
740         adata->acp_mmio = intr_data->acp_mmio;
741         runtime->private_data = adata;
742 
743         /*
744          * Enable ACP irq, when neither playback or capture streams are
745          * active by the time when a new stream is being opened.
746          * This enablement is not required for another stream, if current
747          * stream is not closed
748          */
749         if (!intr_data->play_i2ssp_stream && !intr_data->capture_i2ssp_stream &&
750             !intr_data->play_i2sbt_stream && !intr_data->capture_i2sbt_stream)
751                 acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
752 
753         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
754                 /*
755                  * For Stoney, Memory gating is disabled,i.e SRAM Banks
756                  * won't be turned off. The default state for SRAM banks is ON.
757                  * Setting SRAM bank state code skipped for STONEY platform.
758                  */
759                 if (intr_data->asic_type != CHIP_STONEY) {
760                         for (bank = 1; bank <= 4; bank++)
761                                 acp_set_sram_bank_state(intr_data->acp_mmio,
762                                                         bank, true);
763                 }
764         } else {
765                 if (intr_data->asic_type != CHIP_STONEY) {
766                         for (bank = 5; bank <= 8; bank++)
767                                 acp_set_sram_bank_state(intr_data->acp_mmio,
768                                                         bank, true);
769                 }
770         }
771 
772         return 0;
773 }
774 
775 static int acp_dma_hw_params(struct snd_pcm_substream *substream,
776                              struct snd_pcm_hw_params *params)
777 {
778         int status;
779         uint64_t size;
780         u32 val = 0;
781         struct page *pg;
782         struct snd_pcm_runtime *runtime;
783         struct audio_substream_data *rtd;
784         struct snd_soc_pcm_runtime *prtd = substream->private_data;
785         struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd,
786                                                                     DRV_NAME);
787         struct audio_drv_data *adata = dev_get_drvdata(component->dev);
788         struct snd_soc_card *card = prtd->card;
789         struct acp_platform_info *pinfo = snd_soc_card_get_drvdata(card);
790 
791         runtime = substream->runtime;
792         rtd = runtime->private_data;
793 
794         if (WARN_ON(!rtd))
795                 return -EINVAL;
796 
797         rtd->i2s_instance = pinfo->i2s_instance;
798         if (adata->asic_type == CHIP_STONEY) {
799                 val = acp_reg_read(adata->acp_mmio,
800                                    mmACP_I2S_16BIT_RESOLUTION_EN);
801                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
802                         switch (rtd->i2s_instance) {
803                         case I2S_BT_INSTANCE:
804                                 val |= ACP_I2S_BT_16BIT_RESOLUTION_EN;
805                                 break;
806                         case I2S_SP_INSTANCE:
807                         default:
808                                 val |= ACP_I2S_SP_16BIT_RESOLUTION_EN;
809                         }
810                 } else {
811                         switch (rtd->i2s_instance) {
812                         case I2S_BT_INSTANCE:
813                                 val |= ACP_I2S_BT_16BIT_RESOLUTION_EN;
814                                 break;
815                         case I2S_SP_INSTANCE:
816                         default:
817                                 val |= ACP_I2S_MIC_16BIT_RESOLUTION_EN;
818                         }
819                 }
820                 acp_reg_write(val, adata->acp_mmio,
821                               mmACP_I2S_16BIT_RESOLUTION_EN);
822         }
823 
824         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
825                 switch (rtd->i2s_instance) {
826                 case I2S_BT_INSTANCE:
827                         rtd->pte_offset = ACP_ST_BT_PLAYBACK_PTE_OFFSET;
828                         rtd->ch1 = SYSRAM_TO_ACP_BT_INSTANCE_CH_NUM;
829                         rtd->ch2 = ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM;
830                         rtd->sram_bank = ACP_SRAM_BANK_3_ADDRESS;
831                         rtd->destination = TO_BLUETOOTH;
832                         rtd->dma_dscr_idx_1 = PLAYBACK_START_DMA_DESCR_CH8;
833                         rtd->dma_dscr_idx_2 = PLAYBACK_START_DMA_DESCR_CH9;
834                         rtd->byte_cnt_high_reg_offset =
835                                         mmACP_I2S_BT_TRANSMIT_BYTE_CNT_HIGH;
836                         rtd->byte_cnt_low_reg_offset =
837                                         mmACP_I2S_BT_TRANSMIT_BYTE_CNT_LOW;
838                         adata->play_i2sbt_stream = substream;
839                         break;
840                 case I2S_SP_INSTANCE:
841                 default:
842                         switch (adata->asic_type) {
843                         case CHIP_STONEY:
844                                 rtd->pte_offset = ACP_ST_PLAYBACK_PTE_OFFSET;
845                                 break;
846                         default:
847                                 rtd->pte_offset = ACP_PLAYBACK_PTE_OFFSET;
848                         }
849                         rtd->ch1 = SYSRAM_TO_ACP_CH_NUM;
850                         rtd->ch2 = ACP_TO_I2S_DMA_CH_NUM;
851                         rtd->sram_bank = ACP_SRAM_BANK_1_ADDRESS;
852                         rtd->destination = TO_ACP_I2S_1;
853                         rtd->dma_dscr_idx_1 = PLAYBACK_START_DMA_DESCR_CH12;
854                         rtd->dma_dscr_idx_2 = PLAYBACK_START_DMA_DESCR_CH13;
855                         rtd->byte_cnt_high_reg_offset =
856                                         mmACP_I2S_TRANSMIT_BYTE_CNT_HIGH;
857                         rtd->byte_cnt_low_reg_offset =
858                                         mmACP_I2S_TRANSMIT_BYTE_CNT_LOW;
859                         adata->play_i2ssp_stream = substream;
860                 }
861         } else {
862                 switch (rtd->i2s_instance) {
863                 case I2S_BT_INSTANCE:
864                         rtd->pte_offset = ACP_ST_BT_CAPTURE_PTE_OFFSET;
865                         rtd->ch1 = ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM;
866                         rtd->ch2 = I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM;
867                         rtd->sram_bank = ACP_SRAM_BANK_4_ADDRESS;
868                         rtd->destination = FROM_BLUETOOTH;
869                         rtd->dma_dscr_idx_1 = CAPTURE_START_DMA_DESCR_CH10;
870                         rtd->dma_dscr_idx_2 = CAPTURE_START_DMA_DESCR_CH11;
871                         rtd->byte_cnt_high_reg_offset =
872                                         mmACP_I2S_BT_RECEIVE_BYTE_CNT_HIGH;
873                         rtd->byte_cnt_low_reg_offset =
874                                         mmACP_I2S_BT_RECEIVE_BYTE_CNT_LOW;
875                         adata->capture_i2sbt_stream = substream;
876                         break;
877                 case I2S_SP_INSTANCE:
878                 default:
879                         rtd->pte_offset = ACP_CAPTURE_PTE_OFFSET;
880                         rtd->ch1 = ACP_TO_SYSRAM_CH_NUM;
881                         rtd->ch2 = I2S_TO_ACP_DMA_CH_NUM;
882                         switch (adata->asic_type) {
883                         case CHIP_STONEY:
884                                 rtd->pte_offset = ACP_ST_CAPTURE_PTE_OFFSET;
885                                 rtd->sram_bank = ACP_SRAM_BANK_2_ADDRESS;
886                                 break;
887                         default:
888                                 rtd->pte_offset = ACP_CAPTURE_PTE_OFFSET;
889                                 rtd->sram_bank = ACP_SRAM_BANK_5_ADDRESS;
890                         }
891                         rtd->destination = FROM_ACP_I2S_1;
892                         rtd->dma_dscr_idx_1 = CAPTURE_START_DMA_DESCR_CH14;
893                         rtd->dma_dscr_idx_2 = CAPTURE_START_DMA_DESCR_CH15;
894                         rtd->byte_cnt_high_reg_offset =
895                                         mmACP_I2S_RECEIVED_BYTE_CNT_HIGH;
896                         rtd->byte_cnt_low_reg_offset =
897                                         mmACP_I2S_RECEIVED_BYTE_CNT_LOW;
898                         adata->capture_i2ssp_stream = substream;
899                 }
900         }
901 
902         size = params_buffer_bytes(params);
903         status = snd_pcm_lib_malloc_pages(substream, size);
904         if (status < 0)
905                 return status;
906 
907         memset(substream->runtime->dma_area, 0, params_buffer_bytes(params));
908         pg = virt_to_page(substream->dma_buffer.area);
909 
910         if (pg) {
911                 acp_set_sram_bank_state(rtd->acp_mmio, 0, true);
912                 /* Save for runtime private data */
913                 rtd->pg = pg;
914                 rtd->order = get_order(size);
915 
916                 /* Fill the page table entries in ACP SRAM */
917                 rtd->pg = pg;
918                 rtd->size = size;
919                 rtd->num_of_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
920                 rtd->direction = substream->stream;
921 
922                 config_acp_dma(rtd->acp_mmio, rtd, adata->asic_type);
923                 status = 0;
924         } else {
925                 status = -ENOMEM;
926         }
927         return status;
928 }
929 
930 static int acp_dma_hw_free(struct snd_pcm_substream *substream)
931 {
932         return snd_pcm_lib_free_pages(substream);
933 }
934 
935 static u64 acp_get_byte_count(struct audio_substream_data *rtd)
936 {
937         union acp_dma_count byte_count;
938 
939         byte_count.bcount.high = acp_reg_read(rtd->acp_mmio,
940                                               rtd->byte_cnt_high_reg_offset);
941         byte_count.bcount.low  = acp_reg_read(rtd->acp_mmio,
942                                               rtd->byte_cnt_low_reg_offset);
943         return byte_count.bytescount;
944 }
945 
946 static snd_pcm_uframes_t acp_dma_pointer(struct snd_pcm_substream *substream)
947 {
948         u32 buffersize;
949         u32 pos = 0;
950         u64 bytescount = 0;
951 
952         struct snd_pcm_runtime *runtime = substream->runtime;
953         struct audio_substream_data *rtd = runtime->private_data;
954 
955         if (!rtd)
956                 return -EINVAL;
957 
958         buffersize = frames_to_bytes(runtime, runtime->buffer_size);
959         bytescount = acp_get_byte_count(rtd);
960 
961         if (bytescount > rtd->bytescount)
962                 bytescount -= rtd->bytescount;
963         pos = do_div(bytescount, buffersize);
964         return bytes_to_frames(runtime, pos);
965 }
966 
967 static int acp_dma_mmap(struct snd_pcm_substream *substream,
968                         struct vm_area_struct *vma)
969 {
970         return snd_pcm_lib_default_mmap(substream, vma);
971 }
972 
973 static int acp_dma_prepare(struct snd_pcm_substream *substream)
974 {
975         struct snd_pcm_runtime *runtime = substream->runtime;
976         struct audio_substream_data *rtd = runtime->private_data;
977 
978         if (!rtd)
979                 return -EINVAL;
980 
981         config_acp_dma_channel(rtd->acp_mmio,
982                                rtd->ch1,
983                                rtd->dma_dscr_idx_1,
984                                NUM_DSCRS_PER_CHANNEL, 0);
985         config_acp_dma_channel(rtd->acp_mmio,
986                                rtd->ch2,
987                                rtd->dma_dscr_idx_2,
988                                NUM_DSCRS_PER_CHANNEL, 0);
989         return 0;
990 }
991 
992 static int acp_dma_trigger(struct snd_pcm_substream *substream, int cmd)
993 {
994         int ret;
995         u64 bytescount = 0;
996 
997         struct snd_pcm_runtime *runtime = substream->runtime;
998         struct audio_substream_data *rtd = runtime->private_data;
999 
1000         if (!rtd)
1001                 return -EINVAL;
1002         switch (cmd) {
1003         case SNDRV_PCM_TRIGGER_START:
1004         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1005         case SNDRV_PCM_TRIGGER_RESUME:
1006                 bytescount = acp_get_byte_count(rtd);
1007                 if (rtd->bytescount == 0)
1008                         rtd->bytescount = bytescount;
1009                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1010                         acp_dma_start(rtd->acp_mmio, rtd->ch1);
1011                         acp_dma_start(rtd->acp_mmio, rtd->ch2);
1012                 } else {
1013                         acp_dma_start(rtd->acp_mmio, rtd->ch2);
1014                         acp_dma_start(rtd->acp_mmio, rtd->ch1);
1015                 }
1016                 ret = 0;
1017                 break;
1018         case SNDRV_PCM_TRIGGER_STOP:
1019         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1020         case SNDRV_PCM_TRIGGER_SUSPEND:
1021                 /* For playback, non circular dma should be stopped first
1022                  * i.e Sysram to acp dma transfer channel(rtd->ch1) should be
1023                  * stopped before stopping cirular dma which is acp sram to i2s
1024                  * fifo dma transfer channel(rtd->ch2). Where as in Capture
1025                  * scenario, i2s fifo to acp sram dma channel(rtd->ch2) stopped
1026                  * first before stopping acp sram to sysram which is circular
1027                  * dma(rtd->ch1).
1028                  */
1029                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1030                         acp_dma_stop(rtd->acp_mmio, rtd->ch1);
1031                         ret =  acp_dma_stop(rtd->acp_mmio, rtd->ch2);
1032                 } else {
1033                         acp_dma_stop(rtd->acp_mmio, rtd->ch2);
1034                         ret = acp_dma_stop(rtd->acp_mmio, rtd->ch1);
1035                 }
1036                 rtd->bytescount = 0;
1037                 break;
1038         default:
1039                 ret = -EINVAL;
1040         }
1041         return ret;
1042 }
1043 
1044 static int acp_dma_new(struct snd_soc_pcm_runtime *rtd)
1045 {
1046         int ret;
1047         struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd,
1048                                                                     DRV_NAME);
1049         struct audio_drv_data *adata = dev_get_drvdata(component->dev);
1050 
1051         switch (adata->asic_type) {
1052         case CHIP_STONEY:
1053                 ret = snd_pcm_lib_preallocate_pages_for_all(rtd->pcm,
1054                                                             SNDRV_DMA_TYPE_DEV,
1055                                                             NULL, ST_MIN_BUFFER,
1056                                                             ST_MAX_BUFFER);
1057                 break;
1058         default:
1059                 ret = snd_pcm_lib_preallocate_pages_for_all(rtd->pcm,
1060                                                             SNDRV_DMA_TYPE_DEV,
1061                                                             NULL, MIN_BUFFER,
1062                                                             MAX_BUFFER);
1063                 break;
1064         }
1065         if (ret < 0)
1066                 dev_err(component->dev,
1067                         "buffer preallocation failure error:%d\n", ret);
1068         return ret;
1069 }
1070 
1071 static int acp_dma_close(struct snd_pcm_substream *substream)
1072 {
1073         u16 bank;
1074         struct snd_pcm_runtime *runtime = substream->runtime;
1075         struct audio_substream_data *rtd = runtime->private_data;
1076         struct snd_soc_pcm_runtime *prtd = substream->private_data;
1077         struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd,
1078                                                                     DRV_NAME);
1079         struct audio_drv_data *adata = dev_get_drvdata(component->dev);
1080 
1081         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1082                 switch (rtd->i2s_instance) {
1083                 case I2S_BT_INSTANCE:
1084                         adata->play_i2sbt_stream = NULL;
1085                         break;
1086                 case I2S_SP_INSTANCE:
1087                 default:
1088                         adata->play_i2ssp_stream = NULL;
1089                         /*
1090                          * For Stoney, Memory gating is disabled,i.e SRAM Banks
1091                          * won't be turned off. The default state for SRAM banks
1092                          * is ON.Setting SRAM bank state code skipped for STONEY
1093                          * platform. Added condition checks for Carrizo platform
1094                          * only.
1095                          */
1096                         if (adata->asic_type != CHIP_STONEY) {
1097                                 for (bank = 1; bank <= 4; bank++)
1098                                         acp_set_sram_bank_state(adata->acp_mmio,
1099                                                                 bank, false);
1100                         }
1101                 }
1102         } else  {
1103                 switch (rtd->i2s_instance) {
1104                 case I2S_BT_INSTANCE:
1105                         adata->capture_i2sbt_stream = NULL;
1106                         break;
1107                 case I2S_SP_INSTANCE:
1108                 default:
1109                         adata->capture_i2ssp_stream = NULL;
1110                         if (adata->asic_type != CHIP_STONEY) {
1111                                 for (bank = 5; bank <= 8; bank++)
1112                                         acp_set_sram_bank_state(adata->acp_mmio,
1113                                                                 bank, false);
1114                         }
1115                 }
1116         }
1117 
1118         /*
1119          * Disable ACP irq, when the current stream is being closed and
1120          * another stream is also not active.
1121          */
1122         if (!adata->play_i2ssp_stream && !adata->capture_i2ssp_stream &&
1123             !adata->play_i2sbt_stream && !adata->capture_i2sbt_stream)
1124                 acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
1125         kfree(rtd);
1126         return 0;
1127 }
1128 
1129 static const struct snd_pcm_ops acp_dma_ops = {
1130         .open = acp_dma_open,
1131         .close = acp_dma_close,
1132         .ioctl = snd_pcm_lib_ioctl,
1133         .hw_params = acp_dma_hw_params,
1134         .hw_free = acp_dma_hw_free,
1135         .trigger = acp_dma_trigger,
1136         .pointer = acp_dma_pointer,
1137         .mmap = acp_dma_mmap,
1138         .prepare = acp_dma_prepare,
1139 };
1140 
1141 static const struct snd_soc_component_driver acp_asoc_platform = {
1142         .name = DRV_NAME,
1143         .ops = &acp_dma_ops,
1144         .pcm_new = acp_dma_new,
1145 };
1146 
1147 static int acp_audio_probe(struct platform_device *pdev)
1148 {
1149         int status;
1150         struct audio_drv_data *audio_drv_data;
1151         struct resource *res;
1152         const u32 *pdata = pdev->dev.platform_data;
1153 
1154         if (!pdata) {
1155                 dev_err(&pdev->dev, "Missing platform data\n");
1156                 return -ENODEV;
1157         }
1158 
1159         audio_drv_data = devm_kzalloc(&pdev->dev, sizeof(struct audio_drv_data),
1160                                       GFP_KERNEL);
1161         if (!audio_drv_data)
1162                 return -ENOMEM;
1163 
1164         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1165         audio_drv_data->acp_mmio = devm_ioremap_resource(&pdev->dev, res);
1166         if (IS_ERR(audio_drv_data->acp_mmio))
1167                 return PTR_ERR(audio_drv_data->acp_mmio);
1168 
1169         /*
1170          * The following members gets populated in device 'open'
1171          * function. Till then interrupts are disabled in 'acp_init'
1172          * and device doesn't generate any interrupts.
1173          */
1174 
1175         audio_drv_data->play_i2ssp_stream = NULL;
1176         audio_drv_data->capture_i2ssp_stream = NULL;
1177         audio_drv_data->play_i2sbt_stream = NULL;
1178         audio_drv_data->capture_i2sbt_stream = NULL;
1179 
1180         audio_drv_data->asic_type =  *pdata;
1181 
1182         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1183         if (!res) {
1184                 dev_err(&pdev->dev, "IORESOURCE_IRQ FAILED\n");
1185                 return -ENODEV;
1186         }
1187 
1188         status = devm_request_irq(&pdev->dev, res->start, dma_irq_handler,
1189                                   0, "ACP_IRQ", &pdev->dev);
1190         if (status) {
1191                 dev_err(&pdev->dev, "ACP IRQ request failed\n");
1192                 return status;
1193         }
1194 
1195         dev_set_drvdata(&pdev->dev, audio_drv_data);
1196 
1197         /* Initialize the ACP */
1198         status = acp_init(audio_drv_data->acp_mmio, audio_drv_data->asic_type);
1199         if (status) {
1200                 dev_err(&pdev->dev, "ACP Init failed status:%d\n", status);
1201                 return status;
1202         }
1203 
1204         status = devm_snd_soc_register_component(&pdev->dev,
1205                                                  &acp_asoc_platform, NULL, 0);
1206         if (status != 0) {
1207                 dev_err(&pdev->dev, "Fail to register ALSA platform device\n");
1208                 return status;
1209         }
1210 
1211         pm_runtime_set_autosuspend_delay(&pdev->dev, 10000);
1212         pm_runtime_use_autosuspend(&pdev->dev);
1213         pm_runtime_enable(&pdev->dev);
1214 
1215         return status;
1216 }
1217 
1218 static int acp_audio_remove(struct platform_device *pdev)
1219 {
1220         int status;
1221         struct audio_drv_data *adata = dev_get_drvdata(&pdev->dev);
1222 
1223         status = acp_deinit(adata->acp_mmio);
1224         if (status)
1225                 dev_err(&pdev->dev, "ACP Deinit failed status:%d\n", status);
1226         pm_runtime_disable(&pdev->dev);
1227 
1228         return 0;
1229 }
1230 
1231 static int acp_pcm_resume(struct device *dev)
1232 {
1233         u16 bank;
1234         int status;
1235         struct audio_substream_data *rtd;
1236         struct audio_drv_data *adata = dev_get_drvdata(dev);
1237 
1238         status = acp_init(adata->acp_mmio, adata->asic_type);
1239         if (status) {
1240                 dev_err(dev, "ACP Init failed status:%d\n", status);
1241                 return status;
1242         }
1243 
1244         if (adata->play_i2ssp_stream && adata->play_i2ssp_stream->runtime) {
1245                 /*
1246                  * For Stoney, Memory gating is disabled,i.e SRAM Banks
1247                  * won't be turned off. The default state for SRAM banks is ON.
1248                  * Setting SRAM bank state code skipped for STONEY platform.
1249                  */
1250                 if (adata->asic_type != CHIP_STONEY) {
1251                         for (bank = 1; bank <= 4; bank++)
1252                                 acp_set_sram_bank_state(adata->acp_mmio, bank,
1253                                                         true);
1254                 }
1255                 rtd = adata->play_i2ssp_stream->runtime->private_data;
1256                 config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);
1257         }
1258         if (adata->capture_i2ssp_stream &&
1259             adata->capture_i2ssp_stream->runtime) {
1260                 if (adata->asic_type != CHIP_STONEY) {
1261                         for (bank = 5; bank <= 8; bank++)
1262                                 acp_set_sram_bank_state(adata->acp_mmio, bank,
1263                                                         true);
1264                 }
1265                 rtd =  adata->capture_i2ssp_stream->runtime->private_data;
1266                 config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);
1267         }
1268         if (adata->asic_type != CHIP_CARRIZO) {
1269                 if (adata->play_i2sbt_stream &&
1270                     adata->play_i2sbt_stream->runtime) {
1271                         rtd = adata->play_i2sbt_stream->runtime->private_data;
1272                         config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);
1273                 }
1274                 if (adata->capture_i2sbt_stream &&
1275                     adata->capture_i2sbt_stream->runtime) {
1276                         rtd = adata->capture_i2sbt_stream->runtime->private_data;
1277                         config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);
1278                 }
1279         }
1280         acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
1281         return 0;
1282 }
1283 
1284 static int acp_pcm_runtime_suspend(struct device *dev)
1285 {
1286         int status;
1287         struct audio_drv_data *adata = dev_get_drvdata(dev);
1288 
1289         status = acp_deinit(adata->acp_mmio);
1290         if (status)
1291                 dev_err(dev, "ACP Deinit failed status:%d\n", status);
1292         acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
1293         return 0;
1294 }
1295 
1296 static int acp_pcm_runtime_resume(struct device *dev)
1297 {
1298         int status;
1299         struct audio_drv_data *adata = dev_get_drvdata(dev);
1300 
1301         status = acp_init(adata->acp_mmio, adata->asic_type);
1302         if (status) {
1303                 dev_err(dev, "ACP Init failed status:%d\n", status);
1304                 return status;
1305         }
1306         acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
1307         return 0;
1308 }
1309 
1310 static const struct dev_pm_ops acp_pm_ops = {
1311         .resume = acp_pcm_resume,
1312         .runtime_suspend = acp_pcm_runtime_suspend,
1313         .runtime_resume = acp_pcm_runtime_resume,
1314 };
1315 
1316 static struct platform_driver acp_dma_driver = {
1317         .probe = acp_audio_probe,
1318         .remove = acp_audio_remove,
1319         .driver = {
1320                 .name = DRV_NAME,
1321                 .pm = &acp_pm_ops,
1322         },
1323 };
1324 
1325 module_platform_driver(acp_dma_driver);
1326 
1327 MODULE_AUTHOR("Vijendar.Mukunda@amd.com");
1328 MODULE_AUTHOR("Maruthi.Bayyavarapu@amd.com");
1329 MODULE_DESCRIPTION("AMD ACP PCM Driver");
1330 MODULE_LICENSE("GPL v2");
1331 MODULE_ALIAS("platform:"DRV_NAME);
1332 

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