~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

TOMOYO Linux Cross Reference
Linux/sound/soc/amd/acp.h

Version: ~ [ linux-5.11-rc3 ] ~ [ linux-5.10.7 ] ~ [ linux-5.9.16 ] ~ [ linux-5.8.18 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.89 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.167 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.215 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.251 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.251 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.19.8 ] ~ [ linux-3.18.140 ] ~ [ linux-3.17.8 ] ~ [ linux-3.16.85 ] ~ [ linux-3.15.10 ] ~ [ linux-3.14.79 ] ~ [ linux-3.13.11 ] ~ [ linux-3.12.74 ] ~ [ linux-3.11.10 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.5 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /* SPDX-License-Identifier: GPL-2.0 */
  2 #ifndef __ACP_HW_H
  3 #define __ACP_HW_H
  4 
  5 #include "include/acp_2_2_d.h"
  6 #include "include/acp_2_2_sh_mask.h"
  7 
  8 #define ACP_PAGE_SIZE_4K_ENABLE                 0x02
  9 
 10 #define ACP_PLAYBACK_PTE_OFFSET                 10
 11 #define ACP_CAPTURE_PTE_OFFSET                  0
 12 
 13 /* Playback and Capture Offset for Stoney */
 14 #define ACP_ST_PLAYBACK_PTE_OFFSET      0x04
 15 #define ACP_ST_CAPTURE_PTE_OFFSET       0x00
 16 #define ACP_ST_BT_PLAYBACK_PTE_OFFSET   0x08
 17 #define ACP_ST_BT_CAPTURE_PTE_OFFSET    0x0c
 18 
 19 #define ACP_GARLIC_CNTL_DEFAULT                 0x00000FB4
 20 #define ACP_ONION_CNTL_DEFAULT                  0x00000FB4
 21 
 22 #define ACP_PHYSICAL_BASE                       0x14000
 23 
 24 /*
 25  * In case of I2S SP controller instance, Stoney uses SRAM bank 1 for
 26  * playback and SRAM Bank 2 for capture where as in case of BT I2S
 27  * Instance, Stoney uses SRAM Bank 3 for playback & SRAM Bank 4 will
 28  * be used for capture. Carrizo uses I2S SP controller instance. SRAM Banks
 29  * 1, 2, 3, 4 will be used for playback & SRAM Banks 5, 6, 7, 8 will be used
 30  * for capture scenario.
 31  */
 32 #define ACP_SRAM_BANK_1_ADDRESS         0x4002000
 33 #define ACP_SRAM_BANK_2_ADDRESS         0x4004000
 34 #define ACP_SRAM_BANK_3_ADDRESS         0x4006000
 35 #define ACP_SRAM_BANK_4_ADDRESS         0x4008000
 36 #define ACP_SRAM_BANK_5_ADDRESS         0x400A000
 37 
 38 #define ACP_DMA_RESET_TIME                      10000
 39 #define ACP_CLOCK_EN_TIME_OUT_VALUE             0x000000FF
 40 #define ACP_SOFT_RESET_DONE_TIME_OUT_VALUE      0x000000FF
 41 #define ACP_DMA_COMPLETE_TIME_OUT_VALUE         0x000000FF
 42 
 43 #define ACP_SRAM_BASE_ADDRESS                   0x4000000
 44 #define ACP_DAGB_GRP_SRAM_BASE_ADDRESS          0x4001000
 45 #define ACP_DAGB_GRP_SRBM_SRAM_BASE_OFFSET      0x1000
 46 #define ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS  0x00000000
 47 #define ACP_INTERNAL_APERTURE_WINDOW_4_ADDRESS  0x01800000
 48 
 49 #define TO_ACP_I2S_1   0x2
 50 #define TO_ACP_I2S_2   0x4
 51 #define TO_BLUETOOTH   0x3
 52 #define FROM_ACP_I2S_1 0xa
 53 #define FROM_ACP_I2S_2 0xb
 54 #define FROM_BLUETOOTH 0xb
 55 
 56 #define I2S_SP_INSTANCE                 0x01
 57 #define I2S_BT_INSTANCE                 0x02
 58 #define CAP_CHANNEL0                    0x00
 59 #define CAP_CHANNEL1                    0x01
 60 
 61 #define ACP_TILE_ON_MASK                0x03
 62 #define ACP_TILE_OFF_MASK               0x02
 63 #define ACP_TILE_ON_RETAIN_REG_MASK     0x1f
 64 #define ACP_TILE_OFF_RETAIN_REG_MASK    0x20
 65 
 66 #define ACP_TILE_P1_MASK                0x3e
 67 #define ACP_TILE_P2_MASK                0x3d
 68 #define ACP_TILE_DSP0_MASK              0x3b
 69 #define ACP_TILE_DSP1_MASK              0x37
 70 
 71 #define ACP_TILE_DSP2_MASK              0x2f
 72 /* Playback DMA channels */
 73 #define SYSRAM_TO_ACP_CH_NUM 12
 74 #define ACP_TO_I2S_DMA_CH_NUM 13
 75 
 76 /* Capture DMA channels */
 77 #define I2S_TO_ACP_DMA_CH_NUM 14
 78 #define ACP_TO_SYSRAM_CH_NUM 15
 79 
 80 /* Playback DMA Channels for I2S BT instance */
 81 #define SYSRAM_TO_ACP_BT_INSTANCE_CH_NUM  8
 82 #define ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM 9
 83 
 84 /* Capture DMA Channels for I2S BT Instance */
 85 #define I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM 10
 86 #define ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM 11
 87 
 88 #define NUM_DSCRS_PER_CHANNEL 2
 89 
 90 #define PLAYBACK_START_DMA_DESCR_CH12 0
 91 #define PLAYBACK_END_DMA_DESCR_CH12 1
 92 #define PLAYBACK_START_DMA_DESCR_CH13 2
 93 #define PLAYBACK_END_DMA_DESCR_CH13 3
 94 
 95 #define CAPTURE_START_DMA_DESCR_CH14 4
 96 #define CAPTURE_END_DMA_DESCR_CH14 5
 97 #define CAPTURE_START_DMA_DESCR_CH15 6
 98 #define CAPTURE_END_DMA_DESCR_CH15 7
 99 
100 /* I2S BT Instance DMA Descriptors */
101 #define PLAYBACK_START_DMA_DESCR_CH8 8
102 #define PLAYBACK_END_DMA_DESCR_CH8 9
103 #define PLAYBACK_START_DMA_DESCR_CH9 10
104 #define PLAYBACK_END_DMA_DESCR_CH9 11
105 
106 #define CAPTURE_START_DMA_DESCR_CH10 12
107 #define CAPTURE_END_DMA_DESCR_CH10 13
108 #define CAPTURE_START_DMA_DESCR_CH11 14
109 #define CAPTURE_END_DMA_DESCR_CH11 15
110 
111 #define mmACP_I2S_16BIT_RESOLUTION_EN       0x5209
112 #define ACP_I2S_MIC_16BIT_RESOLUTION_EN 0x01
113 #define ACP_I2S_SP_16BIT_RESOLUTION_EN  0x02
114 #define ACP_I2S_BT_16BIT_RESOLUTION_EN  0x04
115 #define ACP_BT_UART_PAD_SELECT_MASK     0x1
116 
117 enum acp_dma_priority_level {
118         /* 0x0 Specifies the DMA channel is given normal priority */
119         ACP_DMA_PRIORITY_LEVEL_NORMAL = 0x0,
120         /* 0x1 Specifies the DMA channel is given high priority */
121         ACP_DMA_PRIORITY_LEVEL_HIGH = 0x1,
122         ACP_DMA_PRIORITY_LEVEL_FORCESIZE = 0xFF
123 };
124 
125 struct audio_substream_data {
126         dma_addr_t dma_addr;
127         unsigned int order;
128         u16 num_of_pages;
129         u16 i2s_instance;
130         u16 capture_channel;
131         u16 direction;
132         u16 ch1;
133         u16 ch2;
134         u16 destination;
135         u16 dma_dscr_idx_1;
136         u16 dma_dscr_idx_2;
137         u32 pte_offset;
138         u32 sram_bank;
139         u32 byte_cnt_high_reg_offset;
140         u32 byte_cnt_low_reg_offset;
141         u32 dma_curr_dscr;
142         uint64_t size;
143         u64 bytescount;
144         void __iomem *acp_mmio;
145 };
146 
147 struct audio_drv_data {
148         struct snd_pcm_substream *play_i2ssp_stream;
149         struct snd_pcm_substream *capture_i2ssp_stream;
150         struct snd_pcm_substream *play_i2sbt_stream;
151         struct snd_pcm_substream *capture_i2sbt_stream;
152         void __iomem *acp_mmio;
153         u32 asic_type;
154 };
155 
156 /*
157  * this structure used for platform data transfer between machine driver
158  * and dma driver
159  */
160 struct acp_platform_info {
161         u16 play_i2s_instance;
162         u16 cap_i2s_instance;
163         u16 capture_channel;
164 };
165 
166 union acp_dma_count {
167         struct {
168         u32 low;
169         u32 high;
170         } bcount;
171         u64 bytescount;
172 };
173 
174 enum {
175         ACP_TILE_P1 = 0,
176         ACP_TILE_P2,
177         ACP_TILE_DSP0,
178         ACP_TILE_DSP1,
179         ACP_TILE_DSP2,
180 };
181 
182 enum {
183         ACP_DMA_ATTR_SHAREDMEM_TO_DAGB_ONION = 0x0,
184         ACP_DMA_ATTR_SHARED_MEM_TO_DAGB_GARLIC = 0x1,
185         ACP_DMA_ATTR_DAGB_ONION_TO_SHAREDMEM = 0x8,
186         ACP_DMA_ATTR_DAGB_GARLIC_TO_SHAREDMEM = 0x9,
187         ACP_DMA_ATTR_FORCE_SIZE = 0xF
188 };
189 
190 typedef struct acp_dma_dscr_transfer {
191         /* Specifies the source memory location for the DMA data transfer. */
192         u32 src;
193         /*
194          * Specifies the destination memory location to where the data will
195          * be transferred.
196          */
197         u32 dest;
198         /*
199          * Specifies the number of bytes need to be transferred
200          * from source to destination memory.Transfer direction & IOC enable
201          */
202         u32 xfer_val;
203         /* Reserved for future use */
204         u32 reserved;
205 } acp_dma_dscr_transfer_t;
206 
207 #endif /*__ACP_HW_H */
208 

~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

kernel.org | git.kernel.org | LWN.net | Project Home | Wiki (Japanese) | Wiki (English) | SVN repository | Mail admin

Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.

osdn.jp