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Linux/sound/soc/atmel/atmel_ssc_dai.c

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  1 /*
  2  * atmel_ssc_dai.c  --  ALSA SoC ATMEL SSC Audio Layer Platform driver
  3  *
  4  * Copyright (C) 2005 SAN People
  5  * Copyright (C) 2008 Atmel
  6  *
  7  * Author: Sedji Gaouaou <sedji.gaouaou@atmel.com>
  8  *         ATMEL CORP.
  9  *
 10  * Based on at91-ssc.c by
 11  * Frank Mandarino <fmandarino@endrelia.com>
 12  * Based on pxa2xx Platform drivers by
 13  * Liam Girdwood <lrg@slimlogic.co.uk>
 14  *
 15  * This program is free software; you can redistribute it and/or modify
 16  * it under the terms of the GNU General Public License as published by
 17  * the Free Software Foundation; either version 2 of the License, or
 18  * (at your option) any later version.
 19  *
 20  * This program is distributed in the hope that it will be useful,
 21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 23  * GNU General Public License for more details.
 24  *
 25  * You should have received a copy of the GNU General Public License
 26  * along with this program; if not, write to the Free Software
 27  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 28  */
 29 
 30 #include <linux/init.h>
 31 #include <linux/module.h>
 32 #include <linux/interrupt.h>
 33 #include <linux/device.h>
 34 #include <linux/delay.h>
 35 #include <linux/clk.h>
 36 #include <linux/atmel_pdc.h>
 37 
 38 #include <linux/atmel-ssc.h>
 39 #include <sound/core.h>
 40 #include <sound/pcm.h>
 41 #include <sound/pcm_params.h>
 42 #include <sound/initval.h>
 43 #include <sound/soc.h>
 44 
 45 #include "atmel-pcm.h"
 46 #include "atmel_ssc_dai.h"
 47 
 48 
 49 #define NUM_SSC_DEVICES         3
 50 
 51 /*
 52  * SSC PDC registers required by the PCM DMA engine.
 53  */
 54 static struct atmel_pdc_regs pdc_tx_reg = {
 55         .xpr            = ATMEL_PDC_TPR,
 56         .xcr            = ATMEL_PDC_TCR,
 57         .xnpr           = ATMEL_PDC_TNPR,
 58         .xncr           = ATMEL_PDC_TNCR,
 59 };
 60 
 61 static struct atmel_pdc_regs pdc_rx_reg = {
 62         .xpr            = ATMEL_PDC_RPR,
 63         .xcr            = ATMEL_PDC_RCR,
 64         .xnpr           = ATMEL_PDC_RNPR,
 65         .xncr           = ATMEL_PDC_RNCR,
 66 };
 67 
 68 /*
 69  * SSC & PDC status bits for transmit and receive.
 70  */
 71 static struct atmel_ssc_mask ssc_tx_mask = {
 72         .ssc_enable     = SSC_BIT(CR_TXEN),
 73         .ssc_disable    = SSC_BIT(CR_TXDIS),
 74         .ssc_endx       = SSC_BIT(SR_ENDTX),
 75         .ssc_endbuf     = SSC_BIT(SR_TXBUFE),
 76         .pdc_enable     = ATMEL_PDC_TXTEN,
 77         .pdc_disable    = ATMEL_PDC_TXTDIS,
 78 };
 79 
 80 static struct atmel_ssc_mask ssc_rx_mask = {
 81         .ssc_enable     = SSC_BIT(CR_RXEN),
 82         .ssc_disable    = SSC_BIT(CR_RXDIS),
 83         .ssc_endx       = SSC_BIT(SR_ENDRX),
 84         .ssc_endbuf     = SSC_BIT(SR_RXBUFF),
 85         .pdc_enable     = ATMEL_PDC_RXTEN,
 86         .pdc_disable    = ATMEL_PDC_RXTDIS,
 87 };
 88 
 89 
 90 /*
 91  * DMA parameters.
 92  */
 93 static struct atmel_pcm_dma_params ssc_dma_params[NUM_SSC_DEVICES][2] = {
 94         {{
 95         .name           = "SSC0 PCM out",
 96         .pdc            = &pdc_tx_reg,
 97         .mask           = &ssc_tx_mask,
 98         },
 99         {
100         .name           = "SSC0 PCM in",
101         .pdc            = &pdc_rx_reg,
102         .mask           = &ssc_rx_mask,
103         } },
104         {{
105         .name           = "SSC1 PCM out",
106         .pdc            = &pdc_tx_reg,
107         .mask           = &ssc_tx_mask,
108         },
109         {
110         .name           = "SSC1 PCM in",
111         .pdc            = &pdc_rx_reg,
112         .mask           = &ssc_rx_mask,
113         } },
114         {{
115         .name           = "SSC2 PCM out",
116         .pdc            = &pdc_tx_reg,
117         .mask           = &ssc_tx_mask,
118         },
119         {
120         .name           = "SSC2 PCM in",
121         .pdc            = &pdc_rx_reg,
122         .mask           = &ssc_rx_mask,
123         } },
124 };
125 
126 
127 static struct atmel_ssc_info ssc_info[NUM_SSC_DEVICES] = {
128         {
129         .name           = "ssc0",
130         .lock           = __SPIN_LOCK_UNLOCKED(ssc_info[0].lock),
131         .dir_mask       = SSC_DIR_MASK_UNUSED,
132         .initialized    = 0,
133         },
134         {
135         .name           = "ssc1",
136         .lock           = __SPIN_LOCK_UNLOCKED(ssc_info[1].lock),
137         .dir_mask       = SSC_DIR_MASK_UNUSED,
138         .initialized    = 0,
139         },
140         {
141         .name           = "ssc2",
142         .lock           = __SPIN_LOCK_UNLOCKED(ssc_info[2].lock),
143         .dir_mask       = SSC_DIR_MASK_UNUSED,
144         .initialized    = 0,
145         },
146 };
147 
148 
149 /*
150  * SSC interrupt handler.  Passes PDC interrupts to the DMA
151  * interrupt handler in the PCM driver.
152  */
153 static irqreturn_t atmel_ssc_interrupt(int irq, void *dev_id)
154 {
155         struct atmel_ssc_info *ssc_p = dev_id;
156         struct atmel_pcm_dma_params *dma_params;
157         u32 ssc_sr;
158         u32 ssc_substream_mask;
159         int i;
160 
161         ssc_sr = (unsigned long)ssc_readl(ssc_p->ssc->regs, SR)
162                         & (unsigned long)ssc_readl(ssc_p->ssc->regs, IMR);
163 
164         /*
165          * Loop through the substreams attached to this SSC.  If
166          * a DMA-related interrupt occurred on that substream, call
167          * the DMA interrupt handler function, if one has been
168          * registered in the dma_params structure by the PCM driver.
169          */
170         for (i = 0; i < ARRAY_SIZE(ssc_p->dma_params); i++) {
171                 dma_params = ssc_p->dma_params[i];
172 
173                 if ((dma_params != NULL) &&
174                         (dma_params->dma_intr_handler != NULL)) {
175                         ssc_substream_mask = (dma_params->mask->ssc_endx |
176                                         dma_params->mask->ssc_endbuf);
177                         if (ssc_sr & ssc_substream_mask) {
178                                 dma_params->dma_intr_handler(ssc_sr,
179                                                 dma_params->
180                                                 substream);
181                         }
182                 }
183         }
184 
185         return IRQ_HANDLED;
186 }
187 
188 
189 /*-------------------------------------------------------------------------*\
190  * DAI functions
191 \*-------------------------------------------------------------------------*/
192 /*
193  * Startup.  Only that one substream allowed in each direction.
194  */
195 static int atmel_ssc_startup(struct snd_pcm_substream *substream,
196                              struct snd_soc_dai *dai)
197 {
198         struct atmel_ssc_info *ssc_p = &ssc_info[dai->id];
199         int dir_mask;
200 
201         pr_debug("atmel_ssc_startup: SSC_SR=0x%u\n",
202                 ssc_readl(ssc_p->ssc->regs, SR));
203 
204         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
205                 dir_mask = SSC_DIR_MASK_PLAYBACK;
206         else
207                 dir_mask = SSC_DIR_MASK_CAPTURE;
208 
209         spin_lock_irq(&ssc_p->lock);
210         if (ssc_p->dir_mask & dir_mask) {
211                 spin_unlock_irq(&ssc_p->lock);
212                 return -EBUSY;
213         }
214         ssc_p->dir_mask |= dir_mask;
215         spin_unlock_irq(&ssc_p->lock);
216 
217         return 0;
218 }
219 
220 /*
221  * Shutdown.  Clear DMA parameters and shutdown the SSC if there
222  * are no other substreams open.
223  */
224 static void atmel_ssc_shutdown(struct snd_pcm_substream *substream,
225                                struct snd_soc_dai *dai)
226 {
227         struct atmel_ssc_info *ssc_p = &ssc_info[dai->id];
228         struct atmel_pcm_dma_params *dma_params;
229         int dir, dir_mask;
230 
231         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
232                 dir = 0;
233         else
234                 dir = 1;
235 
236         dma_params = ssc_p->dma_params[dir];
237 
238         if (dma_params != NULL) {
239                 ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_disable);
240                 pr_debug("atmel_ssc_shutdown: %s disabled SSC_SR=0x%08x\n",
241                         (dir ? "receive" : "transmit"),
242                         ssc_readl(ssc_p->ssc->regs, SR));
243 
244                 dma_params->ssc = NULL;
245                 dma_params->substream = NULL;
246                 ssc_p->dma_params[dir] = NULL;
247         }
248 
249         dir_mask = 1 << dir;
250 
251         spin_lock_irq(&ssc_p->lock);
252         ssc_p->dir_mask &= ~dir_mask;
253         if (!ssc_p->dir_mask) {
254                 if (ssc_p->initialized) {
255                         /* Shutdown the SSC clock. */
256                         pr_debug("atmel_ssc_dau: Stopping clock\n");
257                         clk_disable(ssc_p->ssc->clk);
258 
259                         free_irq(ssc_p->ssc->irq, ssc_p);
260                         ssc_p->initialized = 0;
261                 }
262 
263                 /* Reset the SSC */
264                 ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST));
265                 /* Clear the SSC dividers */
266                 ssc_p->cmr_div = ssc_p->tcmr_period = ssc_p->rcmr_period = 0;
267         }
268         spin_unlock_irq(&ssc_p->lock);
269 }
270 
271 
272 /*
273  * Record the DAI format for use in hw_params().
274  */
275 static int atmel_ssc_set_dai_fmt(struct snd_soc_dai *cpu_dai,
276                 unsigned int fmt)
277 {
278         struct atmel_ssc_info *ssc_p = &ssc_info[cpu_dai->id];
279 
280         ssc_p->daifmt = fmt;
281         return 0;
282 }
283 
284 /*
285  * Record SSC clock dividers for use in hw_params().
286  */
287 static int atmel_ssc_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
288         int div_id, int div)
289 {
290         struct atmel_ssc_info *ssc_p = &ssc_info[cpu_dai->id];
291 
292         switch (div_id) {
293         case ATMEL_SSC_CMR_DIV:
294                 /*
295                  * The same master clock divider is used for both
296                  * transmit and receive, so if a value has already
297                  * been set, it must match this value.
298                  */
299                 if (ssc_p->cmr_div == 0)
300                         ssc_p->cmr_div = div;
301                 else
302                         if (div != ssc_p->cmr_div)
303                                 return -EBUSY;
304                 break;
305 
306         case ATMEL_SSC_TCMR_PERIOD:
307                 ssc_p->tcmr_period = div;
308                 break;
309 
310         case ATMEL_SSC_RCMR_PERIOD:
311                 ssc_p->rcmr_period = div;
312                 break;
313 
314         default:
315                 return -EINVAL;
316         }
317 
318         return 0;
319 }
320 
321 /*
322  * Configure the SSC.
323  */
324 static int atmel_ssc_hw_params(struct snd_pcm_substream *substream,
325         struct snd_pcm_hw_params *params,
326         struct snd_soc_dai *dai)
327 {
328         struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
329         int id = dai->id;
330         struct atmel_ssc_info *ssc_p = &ssc_info[id];
331         struct atmel_pcm_dma_params *dma_params;
332         int dir, channels, bits;
333         u32 tfmr, rfmr, tcmr, rcmr;
334         int ret;
335 
336         /*
337          * Currently, there is only one set of dma params for
338          * each direction.  If more are added, this code will
339          * have to be changed to select the proper set.
340          */
341         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
342                 dir = 0;
343         else
344                 dir = 1;
345 
346         dma_params = &ssc_dma_params[id][dir];
347         dma_params->ssc = ssc_p->ssc;
348         dma_params->substream = substream;
349 
350         ssc_p->dma_params[dir] = dma_params;
351 
352         /*
353          * The snd_soc_pcm_stream->dma_data field is only used to communicate
354          * the appropriate DMA parameters to the pcm driver hw_params()
355          * function.  It should not be used for other purposes
356          * as it is common to all substreams.
357          */
358         snd_soc_dai_set_dma_data(rtd->cpu_dai, substream, dma_params);
359 
360         channels = params_channels(params);
361 
362         /*
363          * Determine sample size in bits and the PDC increment.
364          */
365         switch (params_format(params)) {
366         case SNDRV_PCM_FORMAT_S8:
367                 bits = 8;
368                 dma_params->pdc_xfer_size = 1;
369                 break;
370         case SNDRV_PCM_FORMAT_S16_LE:
371                 bits = 16;
372                 dma_params->pdc_xfer_size = 2;
373                 break;
374         case SNDRV_PCM_FORMAT_S24_LE:
375                 bits = 24;
376                 dma_params->pdc_xfer_size = 4;
377                 break;
378         case SNDRV_PCM_FORMAT_S32_LE:
379                 bits = 32;
380                 dma_params->pdc_xfer_size = 4;
381                 break;
382         default:
383                 printk(KERN_WARNING "atmel_ssc_dai: unsupported PCM format");
384                 return -EINVAL;
385         }
386 
387         /*
388          * The SSC only supports up to 16-bit samples in I2S format, due
389          * to the size of the Frame Mode Register FSLEN field.
390          */
391         if ((ssc_p->daifmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_I2S
392                 && bits > 16) {
393                 printk(KERN_WARNING
394                                 "atmel_ssc_dai: sample size %d "
395                                 "is too large for I2S\n", bits);
396                 return -EINVAL;
397         }
398 
399         /*
400          * Compute SSC register settings.
401          */
402         switch (ssc_p->daifmt
403                 & (SND_SOC_DAIFMT_FORMAT_MASK | SND_SOC_DAIFMT_MASTER_MASK)) {
404 
405         case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS:
406                 /*
407                  * I2S format, SSC provides BCLK and LRC clocks.
408                  *
409                  * The SSC transmit and receive clocks are generated
410                  * from the MCK divider, and the BCLK signal
411                  * is output on the SSC TK line.
412                  */
413                 rcmr =    SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period)
414                         | SSC_BF(RCMR_STTDLY, START_DELAY)
415                         | SSC_BF(RCMR_START, SSC_START_FALLING_RF)
416                         | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
417                         | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
418                         | SSC_BF(RCMR_CKS, SSC_CKS_DIV);
419 
420                 rfmr =    SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
421                         | SSC_BF(RFMR_FSOS, SSC_FSOS_NEGATIVE)
422                         | SSC_BF(RFMR_FSLEN, (bits - 1))
423                         | SSC_BF(RFMR_DATNB, (channels - 1))
424                         | SSC_BIT(RFMR_MSBF)
425                         | SSC_BF(RFMR_LOOP, 0)
426                         | SSC_BF(RFMR_DATLEN, (bits - 1));
427 
428                 tcmr =    SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period)
429                         | SSC_BF(TCMR_STTDLY, START_DELAY)
430                         | SSC_BF(TCMR_START, SSC_START_FALLING_RF)
431                         | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
432                         | SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS)
433                         | SSC_BF(TCMR_CKS, SSC_CKS_DIV);
434 
435                 tfmr =    SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
436                         | SSC_BF(TFMR_FSDEN, 0)
437                         | SSC_BF(TFMR_FSOS, SSC_FSOS_NEGATIVE)
438                         | SSC_BF(TFMR_FSLEN, (bits - 1))
439                         | SSC_BF(TFMR_DATNB, (channels - 1))
440                         | SSC_BIT(TFMR_MSBF)
441                         | SSC_BF(TFMR_DATDEF, 0)
442                         | SSC_BF(TFMR_DATLEN, (bits - 1));
443                 break;
444 
445         case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM:
446                 /*
447                  * I2S format, CODEC supplies BCLK and LRC clocks.
448                  *
449                  * The SSC transmit clock is obtained from the BCLK signal on
450                  * on the TK line, and the SSC receive clock is
451                  * generated from the transmit clock.
452                  */
453                 rcmr =    SSC_BF(RCMR_PERIOD, 0)
454                         | SSC_BF(RCMR_STTDLY, START_DELAY)
455                         | SSC_BF(RCMR_START, SSC_START_FALLING_RF)
456                         | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
457                         | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
458                         | SSC_BF(RCMR_CKS, SSC_CKS_CLOCK);
459 
460                 rfmr =    SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
461                         | SSC_BF(RFMR_FSOS, SSC_FSOS_NONE)
462                         | SSC_BF(RFMR_FSLEN, 0)
463                         | SSC_BF(RFMR_DATNB, (channels - 1))
464                         | SSC_BIT(RFMR_MSBF)
465                         | SSC_BF(RFMR_LOOP, 0)
466                         | SSC_BF(RFMR_DATLEN, (bits - 1));
467 
468                 tcmr =    SSC_BF(TCMR_PERIOD, 0)
469                         | SSC_BF(TCMR_STTDLY, START_DELAY)
470                         | SSC_BF(TCMR_START, SSC_START_FALLING_RF)
471                         | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
472                         | SSC_BF(TCMR_CKO, SSC_CKO_NONE)
473                         | SSC_BF(TCMR_CKS, SSC_CKS_PIN);
474 
475                 tfmr =    SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
476                         | SSC_BF(TFMR_FSDEN, 0)
477                         | SSC_BF(TFMR_FSOS, SSC_FSOS_NONE)
478                         | SSC_BF(TFMR_FSLEN, 0)
479                         | SSC_BF(TFMR_DATNB, (channels - 1))
480                         | SSC_BIT(TFMR_MSBF)
481                         | SSC_BF(TFMR_DATDEF, 0)
482                         | SSC_BF(TFMR_DATLEN, (bits - 1));
483                 break;
484 
485         case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBS_CFS:
486                 /*
487                  * DSP/PCM Mode A format, SSC provides BCLK and LRC clocks.
488                  *
489                  * The SSC transmit and receive clocks are generated from the
490                  * MCK divider, and the BCLK signal is output
491                  * on the SSC TK line.
492                  */
493                 rcmr =    SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period)
494                         | SSC_BF(RCMR_STTDLY, 1)
495                         | SSC_BF(RCMR_START, SSC_START_RISING_RF)
496                         | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
497                         | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
498                         | SSC_BF(RCMR_CKS, SSC_CKS_DIV);
499 
500                 rfmr =    SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
501                         | SSC_BF(RFMR_FSOS, SSC_FSOS_POSITIVE)
502                         | SSC_BF(RFMR_FSLEN, 0)
503                         | SSC_BF(RFMR_DATNB, (channels - 1))
504                         | SSC_BIT(RFMR_MSBF)
505                         | SSC_BF(RFMR_LOOP, 0)
506                         | SSC_BF(RFMR_DATLEN, (bits - 1));
507 
508                 tcmr =    SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period)
509                         | SSC_BF(TCMR_STTDLY, 1)
510                         | SSC_BF(TCMR_START, SSC_START_RISING_RF)
511                         | SSC_BF(TCMR_CKI, SSC_CKI_RISING)
512                         | SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS)
513                         | SSC_BF(TCMR_CKS, SSC_CKS_DIV);
514 
515                 tfmr =    SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
516                         | SSC_BF(TFMR_FSDEN, 0)
517                         | SSC_BF(TFMR_FSOS, SSC_FSOS_POSITIVE)
518                         | SSC_BF(TFMR_FSLEN, 0)
519                         | SSC_BF(TFMR_DATNB, (channels - 1))
520                         | SSC_BIT(TFMR_MSBF)
521                         | SSC_BF(TFMR_DATDEF, 0)
522                         | SSC_BF(TFMR_DATLEN, (bits - 1));
523                 break;
524 
525         case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBM_CFM:
526                 /*
527                  * DSP/PCM Mode A format, CODEC supplies BCLK and LRC clocks.
528                  *
529                  * The SSC transmit clock is obtained from the BCLK signal on
530                  * on the TK line, and the SSC receive clock is
531                  * generated from the transmit clock.
532                  *
533                  * Data is transferred on first BCLK after LRC pulse rising
534                  * edge.If stereo, the right channel data is contiguous with
535                  * the left channel data.
536                  */
537                 rcmr =    SSC_BF(RCMR_PERIOD, 0)
538                         | SSC_BF(RCMR_STTDLY, START_DELAY)
539                         | SSC_BF(RCMR_START, SSC_START_RISING_RF)
540                         | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
541                         | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
542                         | SSC_BF(RCMR_CKS, SSC_CKS_PIN);
543 
544                 rfmr =    SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
545                         | SSC_BF(RFMR_FSOS, SSC_FSOS_NONE)
546                         | SSC_BF(RFMR_FSLEN, 0)
547                         | SSC_BF(RFMR_DATNB, (channels - 1))
548                         | SSC_BIT(RFMR_MSBF)
549                         | SSC_BF(RFMR_LOOP, 0)
550                         | SSC_BF(RFMR_DATLEN, (bits - 1));
551 
552                 tcmr =    SSC_BF(TCMR_PERIOD, 0)
553                         | SSC_BF(TCMR_STTDLY, START_DELAY)
554                         | SSC_BF(TCMR_START, SSC_START_RISING_RF)
555                         | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
556                         | SSC_BF(TCMR_CKO, SSC_CKO_NONE)
557                         | SSC_BF(TCMR_CKS, SSC_CKS_PIN);
558 
559                 tfmr =    SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
560                         | SSC_BF(TFMR_FSDEN, 0)
561                         | SSC_BF(TFMR_FSOS, SSC_FSOS_NONE)
562                         | SSC_BF(TFMR_FSLEN, 0)
563                         | SSC_BF(TFMR_DATNB, (channels - 1))
564                         | SSC_BIT(TFMR_MSBF)
565                         | SSC_BF(TFMR_DATDEF, 0)
566                         | SSC_BF(TFMR_DATLEN, (bits - 1));
567                 break;
568 
569         default:
570                 printk(KERN_WARNING "atmel_ssc_dai: unsupported DAI format 0x%x\n",
571                         ssc_p->daifmt);
572                 return -EINVAL;
573         }
574         pr_debug("atmel_ssc_hw_params: "
575                         "RCMR=%08x RFMR=%08x TCMR=%08x TFMR=%08x\n",
576                         rcmr, rfmr, tcmr, tfmr);
577 
578         if (!ssc_p->initialized) {
579 
580                 /* Enable PMC peripheral clock for this SSC */
581                 pr_debug("atmel_ssc_dai: Starting clock\n");
582                 clk_enable(ssc_p->ssc->clk);
583 
584                 /* Reset the SSC and its PDC registers */
585                 ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST));
586 
587                 ssc_writel(ssc_p->ssc->regs, PDC_RPR, 0);
588                 ssc_writel(ssc_p->ssc->regs, PDC_RCR, 0);
589                 ssc_writel(ssc_p->ssc->regs, PDC_RNPR, 0);
590                 ssc_writel(ssc_p->ssc->regs, PDC_RNCR, 0);
591 
592                 ssc_writel(ssc_p->ssc->regs, PDC_TPR, 0);
593                 ssc_writel(ssc_p->ssc->regs, PDC_TCR, 0);
594                 ssc_writel(ssc_p->ssc->regs, PDC_TNPR, 0);
595                 ssc_writel(ssc_p->ssc->regs, PDC_TNCR, 0);
596 
597                 ret = request_irq(ssc_p->ssc->irq, atmel_ssc_interrupt, 0,
598                                 ssc_p->name, ssc_p);
599                 if (ret < 0) {
600                         printk(KERN_WARNING
601                                         "atmel_ssc_dai: request_irq failure\n");
602                         pr_debug("Atmel_ssc_dai: Stoping clock\n");
603                         clk_disable(ssc_p->ssc->clk);
604                         return ret;
605                 }
606 
607                 ssc_p->initialized = 1;
608         }
609 
610         /* set SSC clock mode register */
611         ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->cmr_div);
612 
613         /* set receive clock mode and format */
614         ssc_writel(ssc_p->ssc->regs, RCMR, rcmr);
615         ssc_writel(ssc_p->ssc->regs, RFMR, rfmr);
616 
617         /* set transmit clock mode and format */
618         ssc_writel(ssc_p->ssc->regs, TCMR, tcmr);
619         ssc_writel(ssc_p->ssc->regs, TFMR, tfmr);
620 
621         pr_debug("atmel_ssc_dai,hw_params: SSC initialized\n");
622         return 0;
623 }
624 
625 
626 static int atmel_ssc_prepare(struct snd_pcm_substream *substream,
627                              struct snd_soc_dai *dai)
628 {
629         struct atmel_ssc_info *ssc_p = &ssc_info[dai->id];
630         struct atmel_pcm_dma_params *dma_params;
631         int dir;
632 
633         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
634                 dir = 0;
635         else
636                 dir = 1;
637 
638         dma_params = ssc_p->dma_params[dir];
639 
640         ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_enable);
641 
642         pr_debug("%s enabled SSC_SR=0x%08x\n",
643                         dir ? "receive" : "transmit",
644                         ssc_readl(ssc_p->ssc->regs, SR));
645         return 0;
646 }
647 
648 
649 #ifdef CONFIG_PM
650 static int atmel_ssc_suspend(struct snd_soc_dai *cpu_dai)
651 {
652         struct atmel_ssc_info *ssc_p;
653 
654         if (!cpu_dai->active)
655                 return 0;
656 
657         ssc_p = &ssc_info[cpu_dai->id];
658 
659         /* Save the status register before disabling transmit and receive */
660         ssc_p->ssc_state.ssc_sr = ssc_readl(ssc_p->ssc->regs, SR);
661         ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_TXDIS) | SSC_BIT(CR_RXDIS));
662 
663         /* Save the current interrupt mask, then disable unmasked interrupts */
664         ssc_p->ssc_state.ssc_imr = ssc_readl(ssc_p->ssc->regs, IMR);
665         ssc_writel(ssc_p->ssc->regs, IDR, ssc_p->ssc_state.ssc_imr);
666 
667         ssc_p->ssc_state.ssc_cmr = ssc_readl(ssc_p->ssc->regs, CMR);
668         ssc_p->ssc_state.ssc_rcmr = ssc_readl(ssc_p->ssc->regs, RCMR);
669         ssc_p->ssc_state.ssc_rfmr = ssc_readl(ssc_p->ssc->regs, RFMR);
670         ssc_p->ssc_state.ssc_tcmr = ssc_readl(ssc_p->ssc->regs, TCMR);
671         ssc_p->ssc_state.ssc_tfmr = ssc_readl(ssc_p->ssc->regs, TFMR);
672 
673         return 0;
674 }
675 
676 
677 
678 static int atmel_ssc_resume(struct snd_soc_dai *cpu_dai)
679 {
680         struct atmel_ssc_info *ssc_p;
681         u32 cr;
682 
683         if (!cpu_dai->active)
684                 return 0;
685 
686         ssc_p = &ssc_info[cpu_dai->id];
687 
688         /* restore SSC register settings */
689         ssc_writel(ssc_p->ssc->regs, TFMR, ssc_p->ssc_state.ssc_tfmr);
690         ssc_writel(ssc_p->ssc->regs, TCMR, ssc_p->ssc_state.ssc_tcmr);
691         ssc_writel(ssc_p->ssc->regs, RFMR, ssc_p->ssc_state.ssc_rfmr);
692         ssc_writel(ssc_p->ssc->regs, RCMR, ssc_p->ssc_state.ssc_rcmr);
693         ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->ssc_state.ssc_cmr);
694 
695         /* re-enable interrupts */
696         ssc_writel(ssc_p->ssc->regs, IER, ssc_p->ssc_state.ssc_imr);
697 
698         /* Re-enable receive and transmit as appropriate */
699         cr = 0;
700         cr |=
701             (ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_RXEN)) ? SSC_BIT(CR_RXEN) : 0;
702         cr |=
703             (ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_TXEN)) ? SSC_BIT(CR_TXEN) : 0;
704         ssc_writel(ssc_p->ssc->regs, CR, cr);
705 
706         return 0;
707 }
708 #else /* CONFIG_PM */
709 #  define atmel_ssc_suspend     NULL
710 #  define atmel_ssc_resume      NULL
711 #endif /* CONFIG_PM */
712 
713 #define ATMEL_SSC_RATES (SNDRV_PCM_RATE_8000_96000)
714 
715 #define ATMEL_SSC_FORMATS (SNDRV_PCM_FMTBIT_S8     | SNDRV_PCM_FMTBIT_S16_LE |\
716                           SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
717 
718 static const struct snd_soc_dai_ops atmel_ssc_dai_ops = {
719         .startup        = atmel_ssc_startup,
720         .shutdown       = atmel_ssc_shutdown,
721         .prepare        = atmel_ssc_prepare,
722         .hw_params      = atmel_ssc_hw_params,
723         .set_fmt        = atmel_ssc_set_dai_fmt,
724         .set_clkdiv     = atmel_ssc_set_dai_clkdiv,
725 };
726 
727 static struct snd_soc_dai_driver atmel_ssc_dai = {
728                 .suspend = atmel_ssc_suspend,
729                 .resume = atmel_ssc_resume,
730                 .playback = {
731                         .channels_min = 1,
732                         .channels_max = 2,
733                         .rates = ATMEL_SSC_RATES,
734                         .formats = ATMEL_SSC_FORMATS,},
735                 .capture = {
736                         .channels_min = 1,
737                         .channels_max = 2,
738                         .rates = ATMEL_SSC_RATES,
739                         .formats = ATMEL_SSC_FORMATS,},
740                 .ops = &atmel_ssc_dai_ops,
741 };
742 
743 static const struct snd_soc_component_driver atmel_ssc_component = {
744         .name           = "atmel-ssc",
745 };
746 
747 static int asoc_ssc_init(struct device *dev)
748 {
749         struct platform_device *pdev = to_platform_device(dev);
750         struct ssc_device *ssc = platform_get_drvdata(pdev);
751         int ret;
752 
753         ret = snd_soc_register_component(dev, &atmel_ssc_component,
754                                          &atmel_ssc_dai, 1);
755         if (ret) {
756                 dev_err(dev, "Could not register DAI: %d\n", ret);
757                 goto err;
758         }
759 
760         if (ssc->pdata->use_dma)
761                 ret = atmel_pcm_dma_platform_register(dev);
762         else
763                 ret = atmel_pcm_pdc_platform_register(dev);
764 
765         if (ret) {
766                 dev_err(dev, "Could not register PCM: %d\n", ret);
767                 goto err_unregister_dai;
768         };
769 
770         return 0;
771 
772 err_unregister_dai:
773         snd_soc_unregister_component(dev);
774 err:
775         return ret;
776 }
777 
778 static void asoc_ssc_exit(struct device *dev)
779 {
780         struct platform_device *pdev = to_platform_device(dev);
781         struct ssc_device *ssc = platform_get_drvdata(pdev);
782 
783         if (ssc->pdata->use_dma)
784                 atmel_pcm_dma_platform_unregister(dev);
785         else
786                 atmel_pcm_pdc_platform_unregister(dev);
787 
788         snd_soc_unregister_component(dev);
789 }
790 
791 /**
792  * atmel_ssc_set_audio - Allocate the specified SSC for audio use.
793  */
794 int atmel_ssc_set_audio(int ssc_id)
795 {
796         struct ssc_device *ssc;
797         int ret;
798 
799         /* If we can grab the SSC briefly to parent the DAI device off it */
800         ssc = ssc_request(ssc_id);
801         if (IS_ERR(ssc)) {
802                 pr_err("Unable to parent ASoC SSC DAI on SSC: %ld\n",
803                         PTR_ERR(ssc));
804                 return PTR_ERR(ssc);
805         } else {
806                 ssc_info[ssc_id].ssc = ssc;
807         }
808 
809         ret = asoc_ssc_init(&ssc->pdev->dev);
810 
811         return ret;
812 }
813 EXPORT_SYMBOL_GPL(atmel_ssc_set_audio);
814 
815 void atmel_ssc_put_audio(int ssc_id)
816 {
817         struct ssc_device *ssc = ssc_info[ssc_id].ssc;
818 
819         asoc_ssc_exit(&ssc->pdev->dev);
820         ssc_free(ssc);
821 }
822 EXPORT_SYMBOL_GPL(atmel_ssc_put_audio);
823 
824 /* Module information */
825 MODULE_AUTHOR("Sedji Gaouaou, sedji.gaouaou@atmel.com, www.atmel.com");
826 MODULE_DESCRIPTION("ATMEL SSC ASoC Interface");
827 MODULE_LICENSE("GPL");
828 

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