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TOMOYO Linux Cross Reference
Linux/sound/soc/codecs/ab8500-codec.c

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  1 // SPDX-License-Identifier: GPL-2.0-only
  2 /*
  3  * Copyright (C) ST-Ericsson SA 2012
  4  *
  5  * Author: Ola Lilja <ola.o.lilja@stericsson.com>,
  6  *         Kristoffer Karlsson <kristoffer.karlsson@stericsson.com>,
  7  *         Roger Nilsson <roger.xr.nilsson@stericsson.com>,
  8  *         for ST-Ericsson.
  9  *
 10  *         Based on the early work done by:
 11  *         Mikko J. Lehto <mikko.lehto@symbio.com>,
 12  *         Mikko Sarmanne <mikko.sarmanne@symbio.com>,
 13  *         Jarmo K. Kuronen <jarmo.kuronen@symbio.com>,
 14  *         for ST-Ericsson.
 15  *
 16  * License terms:
 17  */
 18 
 19 #include <linux/kernel.h>
 20 #include <linux/module.h>
 21 #include <linux/device.h>
 22 #include <linux/slab.h>
 23 #include <linux/moduleparam.h>
 24 #include <linux/init.h>
 25 #include <linux/delay.h>
 26 #include <linux/pm.h>
 27 #include <linux/platform_device.h>
 28 #include <linux/mutex.h>
 29 #include <linux/mfd/abx500/ab8500.h>
 30 #include <linux/mfd/abx500.h>
 31 #include <linux/mfd/abx500/ab8500-sysctrl.h>
 32 #include <linux/mfd/abx500/ab8500-codec.h>
 33 #include <linux/regulator/consumer.h>
 34 #include <linux/of.h>
 35 
 36 #include <sound/core.h>
 37 #include <sound/pcm.h>
 38 #include <sound/pcm_params.h>
 39 #include <sound/initval.h>
 40 #include <sound/soc.h>
 41 #include <sound/soc-dapm.h>
 42 #include <sound/tlv.h>
 43 
 44 #include "ab8500-codec.h"
 45 
 46 /* Macrocell value definitions */
 47 #define CLK_32K_OUT2_DISABLE                    0x01
 48 #define INACTIVE_RESET_AUDIO                    0x02
 49 #define ENABLE_AUDIO_CLK_TO_AUDIO_BLK           0x10
 50 #define ENABLE_VINTCORE12_SUPPLY                0x04
 51 #define GPIO27_DIR_OUTPUT                       0x04
 52 #define GPIO29_DIR_OUTPUT                       0x10
 53 #define GPIO31_DIR_OUTPUT                       0x40
 54 
 55 /* Macrocell register definitions */
 56 #define AB8500_GPIO_DIR4_REG                    0x13 /* Bank AB8500_MISC */
 57 
 58 /* Nr of FIR/IIR-coeff banks in ANC-block */
 59 #define AB8500_NR_OF_ANC_COEFF_BANKS            2
 60 
 61 /* Minimum duration to keep ANC IIR Init bit high or
 62 low before proceeding with the configuration sequence */
 63 #define AB8500_ANC_SM_DELAY                     2000
 64 
 65 #define AB8500_FILTER_CONTROL(xname, xcount, xmin, xmax) \
 66 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
 67         .info = filter_control_info, \
 68         .get = filter_control_get, .put = filter_control_put, \
 69         .private_value = (unsigned long)&(struct filter_control) \
 70                 {.count = xcount, .min = xmin, .max = xmax} }
 71 
 72 struct filter_control {
 73         long min, max;
 74         unsigned int count;
 75         long value[128];
 76 };
 77 
 78 /* Sidetone states */
 79 static const char * const enum_sid_state[] = {
 80         "Unconfigured",
 81         "Apply FIR",
 82         "FIR is configured",
 83 };
 84 enum sid_state {
 85         SID_UNCONFIGURED = 0,
 86         SID_APPLY_FIR = 1,
 87         SID_FIR_CONFIGURED = 2,
 88 };
 89 
 90 static const char * const enum_anc_state[] = {
 91         "Unconfigured",
 92         "Apply FIR and IIR",
 93         "FIR and IIR are configured",
 94         "Apply FIR",
 95         "FIR is configured",
 96         "Apply IIR",
 97         "IIR is configured"
 98 };
 99 enum anc_state {
100         ANC_UNCONFIGURED = 0,
101         ANC_APPLY_FIR_IIR = 1,
102         ANC_FIR_IIR_CONFIGURED = 2,
103         ANC_APPLY_FIR = 3,
104         ANC_FIR_CONFIGURED = 4,
105         ANC_APPLY_IIR = 5,
106         ANC_IIR_CONFIGURED = 6
107 };
108 
109 /* Analog microphones */
110 enum amic_idx {
111         AMIC_IDX_1A,
112         AMIC_IDX_1B,
113         AMIC_IDX_2
114 };
115 
116 struct ab8500_codec_drvdata_dbg {
117         struct regulator *vaud;
118         struct regulator *vamic1;
119         struct regulator *vamic2;
120         struct regulator *vdmic;
121 };
122 
123 /* Private data for AB8500 device-driver */
124 struct ab8500_codec_drvdata {
125         struct regmap *regmap;
126         struct mutex ctrl_lock;
127 
128         /* Sidetone */
129         long *sid_fir_values;
130         enum sid_state sid_status;
131 
132         /* ANC */
133         long *anc_fir_values;
134         long *anc_iir_values;
135         enum anc_state anc_status;
136 };
137 
138 static inline const char *amic_micbias_str(enum amic_micbias micbias)
139 {
140         switch (micbias) {
141         case AMIC_MICBIAS_VAMIC1:
142                 return "VAMIC1";
143         case AMIC_MICBIAS_VAMIC2:
144                 return "VAMIC2";
145         default:
146                 return "Unknown";
147         }
148 }
149 
150 static inline const char *amic_type_str(enum amic_type type)
151 {
152         switch (type) {
153         case AMIC_TYPE_DIFFERENTIAL:
154                 return "DIFFERENTIAL";
155         case AMIC_TYPE_SINGLE_ENDED:
156                 return "SINGLE ENDED";
157         default:
158                 return "Unknown";
159         }
160 }
161 
162 /*
163  * Read'n'write functions
164  */
165 
166 /* Read a register from the audio-bank of AB8500 */
167 static int ab8500_codec_read_reg(void *context, unsigned int reg,
168                                  unsigned int *value)
169 {
170         struct device *dev = context;
171         int status;
172 
173         u8 value8;
174         status = abx500_get_register_interruptible(dev, AB8500_AUDIO,
175                                                    reg, &value8);
176         *value = (unsigned int)value8;
177 
178         return status;
179 }
180 
181 /* Write to a register in the audio-bank of AB8500 */
182 static int ab8500_codec_write_reg(void *context, unsigned int reg,
183                                   unsigned int value)
184 {
185         struct device *dev = context;
186 
187         return abx500_set_register_interruptible(dev, AB8500_AUDIO,
188                                                  reg, value);
189 }
190 
191 static const struct regmap_config ab8500_codec_regmap = {
192         .reg_read = ab8500_codec_read_reg,
193         .reg_write = ab8500_codec_write_reg,
194 };
195 
196 /*
197  * Controls - DAPM
198  */
199 
200 /* Earpiece */
201 
202 /* Earpiece source selector */
203 static const char * const enum_ear_lineout_source[] = {"Headset Left",
204                                                 "Speaker Left"};
205 static SOC_ENUM_SINGLE_DECL(dapm_enum_ear_lineout_source, AB8500_DMICFILTCONF,
206                         AB8500_DMICFILTCONF_DA3TOEAR, enum_ear_lineout_source);
207 static const struct snd_kcontrol_new dapm_ear_lineout_source =
208         SOC_DAPM_ENUM("Earpiece or LineOut Mono Source",
209                 dapm_enum_ear_lineout_source);
210 
211 /* LineOut */
212 
213 /* LineOut source selector */
214 static const char * const enum_lineout_source[] = {"Mono Path", "Stereo Path"};
215 static SOC_ENUM_DOUBLE_DECL(dapm_enum_lineout_source, AB8500_ANACONF5,
216                         AB8500_ANACONF5_HSLDACTOLOL,
217                         AB8500_ANACONF5_HSRDACTOLOR, enum_lineout_source);
218 static const struct snd_kcontrol_new dapm_lineout_source[] = {
219         SOC_DAPM_ENUM("LineOut Source", dapm_enum_lineout_source),
220 };
221 
222 /* Handsfree */
223 
224 /* Speaker Left - ANC selector */
225 static const char * const enum_HFx_sel[] = {"Audio Path", "ANC"};
226 static SOC_ENUM_SINGLE_DECL(dapm_enum_HFl_sel, AB8500_DIGMULTCONF2,
227                         AB8500_DIGMULTCONF2_HFLSEL, enum_HFx_sel);
228 static const struct snd_kcontrol_new dapm_HFl_select[] = {
229         SOC_DAPM_ENUM("Speaker Left Source", dapm_enum_HFl_sel),
230 };
231 
232 /* Speaker Right - ANC selector */
233 static SOC_ENUM_SINGLE_DECL(dapm_enum_HFr_sel, AB8500_DIGMULTCONF2,
234                         AB8500_DIGMULTCONF2_HFRSEL, enum_HFx_sel);
235 static const struct snd_kcontrol_new dapm_HFr_select[] = {
236         SOC_DAPM_ENUM("Speaker Right Source", dapm_enum_HFr_sel),
237 };
238 
239 /* Mic 1 */
240 
241 /* Mic 1 - Mic 1a or 1b selector */
242 static const char * const enum_mic1ab_sel[] = {"Mic 1b", "Mic 1a"};
243 static SOC_ENUM_SINGLE_DECL(dapm_enum_mic1ab_sel, AB8500_ANACONF3,
244                         AB8500_ANACONF3_MIC1SEL, enum_mic1ab_sel);
245 static const struct snd_kcontrol_new dapm_mic1ab_mux[] = {
246         SOC_DAPM_ENUM("Mic 1a or 1b Select", dapm_enum_mic1ab_sel),
247 };
248 
249 /* Mic 1 - AD3 - Mic 1 or DMic 3 selector */
250 static const char * const enum_ad3_sel[] = {"Mic 1", "DMic 3"};
251 static SOC_ENUM_SINGLE_DECL(dapm_enum_ad3_sel, AB8500_DIGMULTCONF1,
252                         AB8500_DIGMULTCONF1_AD3SEL, enum_ad3_sel);
253 static const struct snd_kcontrol_new dapm_ad3_select[] = {
254         SOC_DAPM_ENUM("AD3 Source Select", dapm_enum_ad3_sel),
255 };
256 
257 /* Mic 1 - AD6 - Mic 1 or DMic 6 selector */
258 static const char * const enum_ad6_sel[] = {"Mic 1", "DMic 6"};
259 static SOC_ENUM_SINGLE_DECL(dapm_enum_ad6_sel, AB8500_DIGMULTCONF1,
260                         AB8500_DIGMULTCONF1_AD6SEL, enum_ad6_sel);
261 static const struct snd_kcontrol_new dapm_ad6_select[] = {
262         SOC_DAPM_ENUM("AD6 Source Select", dapm_enum_ad6_sel),
263 };
264 
265 /* Mic 2 */
266 
267 /* Mic 2 - AD5 - Mic 2 or DMic 5 selector */
268 static const char * const enum_ad5_sel[] = {"Mic 2", "DMic 5"};
269 static SOC_ENUM_SINGLE_DECL(dapm_enum_ad5_sel, AB8500_DIGMULTCONF1,
270                         AB8500_DIGMULTCONF1_AD5SEL, enum_ad5_sel);
271 static const struct snd_kcontrol_new dapm_ad5_select[] = {
272         SOC_DAPM_ENUM("AD5 Source Select", dapm_enum_ad5_sel),
273 };
274 
275 /* LineIn */
276 
277 /* LineIn left - AD1 - LineIn Left or DMic 1 selector */
278 static const char * const enum_ad1_sel[] = {"LineIn Left", "DMic 1"};
279 static SOC_ENUM_SINGLE_DECL(dapm_enum_ad1_sel, AB8500_DIGMULTCONF1,
280                         AB8500_DIGMULTCONF1_AD1SEL, enum_ad1_sel);
281 static const struct snd_kcontrol_new dapm_ad1_select[] = {
282         SOC_DAPM_ENUM("AD1 Source Select", dapm_enum_ad1_sel),
283 };
284 
285 /* LineIn right - Mic 2 or LineIn Right selector */
286 static const char * const enum_mic2lr_sel[] = {"Mic 2", "LineIn Right"};
287 static SOC_ENUM_SINGLE_DECL(dapm_enum_mic2lr_sel, AB8500_ANACONF3,
288                         AB8500_ANACONF3_LINRSEL, enum_mic2lr_sel);
289 static const struct snd_kcontrol_new dapm_mic2lr_select[] = {
290         SOC_DAPM_ENUM("Mic 2 or LINR Select", dapm_enum_mic2lr_sel),
291 };
292 
293 /* LineIn right - AD2 - LineIn Right or DMic2 selector */
294 static const char * const enum_ad2_sel[] = {"LineIn Right", "DMic 2"};
295 static SOC_ENUM_SINGLE_DECL(dapm_enum_ad2_sel, AB8500_DIGMULTCONF1,
296                         AB8500_DIGMULTCONF1_AD2SEL, enum_ad2_sel);
297 static const struct snd_kcontrol_new dapm_ad2_select[] = {
298         SOC_DAPM_ENUM("AD2 Source Select", dapm_enum_ad2_sel),
299 };
300 
301 
302 /* ANC */
303 
304 static const char * const enum_anc_in_sel[] = {"Mic 1 / DMic 6",
305                                         "Mic 2 / DMic 5"};
306 static SOC_ENUM_SINGLE_DECL(dapm_enum_anc_in_sel, AB8500_DMICFILTCONF,
307                         AB8500_DMICFILTCONF_ANCINSEL, enum_anc_in_sel);
308 static const struct snd_kcontrol_new dapm_anc_in_select[] = {
309         SOC_DAPM_ENUM("ANC Source", dapm_enum_anc_in_sel),
310 };
311 
312 /* ANC - Enable/Disable */
313 static const struct snd_kcontrol_new dapm_anc_enable[] = {
314         SOC_DAPM_SINGLE("Switch", AB8500_ANCCONF1,
315                         AB8500_ANCCONF1_ENANC, 0, 0),
316 };
317 
318 /* ANC to Earpiece - Mute */
319 static const struct snd_kcontrol_new dapm_anc_ear_mute[] = {
320         SOC_DAPM_SINGLE("Switch", AB8500_DIGMULTCONF1,
321                         AB8500_DIGMULTCONF1_ANCSEL, 1, 0),
322 };
323 
324 
325 
326 /* Sidetone left */
327 
328 /* Sidetone left - Input selector */
329 static const char * const enum_stfir1_in_sel[] = {
330         "LineIn Left", "LineIn Right", "Mic 1", "Headset Left"
331 };
332 static SOC_ENUM_SINGLE_DECL(dapm_enum_stfir1_in_sel, AB8500_DIGMULTCONF2,
333                         AB8500_DIGMULTCONF2_FIRSID1SEL, enum_stfir1_in_sel);
334 static const struct snd_kcontrol_new dapm_stfir1_in_select[] = {
335         SOC_DAPM_ENUM("Sidetone Left Source", dapm_enum_stfir1_in_sel),
336 };
337 
338 /* Sidetone right path */
339 
340 /* Sidetone right - Input selector */
341 static const char * const enum_stfir2_in_sel[] = {
342         "LineIn Right", "Mic 1", "DMic 4", "Headset Right"
343 };
344 static SOC_ENUM_SINGLE_DECL(dapm_enum_stfir2_in_sel, AB8500_DIGMULTCONF2,
345                         AB8500_DIGMULTCONF2_FIRSID2SEL, enum_stfir2_in_sel);
346 static const struct snd_kcontrol_new dapm_stfir2_in_select[] = {
347         SOC_DAPM_ENUM("Sidetone Right Source", dapm_enum_stfir2_in_sel),
348 };
349 
350 /* Vibra */
351 
352 static const char * const enum_pwm2vibx[] = {"Audio Path", "PWM Generator"};
353 
354 static SOC_ENUM_SINGLE_DECL(dapm_enum_pwm2vib1, AB8500_PWMGENCONF1,
355                         AB8500_PWMGENCONF1_PWMTOVIB1, enum_pwm2vibx);
356 
357 static const struct snd_kcontrol_new dapm_pwm2vib1[] = {
358         SOC_DAPM_ENUM("Vibra 1 Controller", dapm_enum_pwm2vib1),
359 };
360 
361 static SOC_ENUM_SINGLE_DECL(dapm_enum_pwm2vib2, AB8500_PWMGENCONF1,
362                         AB8500_PWMGENCONF1_PWMTOVIB2, enum_pwm2vibx);
363 
364 static const struct snd_kcontrol_new dapm_pwm2vib2[] = {
365         SOC_DAPM_ENUM("Vibra 2 Controller", dapm_enum_pwm2vib2),
366 };
367 
368 /*
369  * DAPM-widgets
370  */
371 
372 static const struct snd_soc_dapm_widget ab8500_dapm_widgets[] = {
373 
374         /* Clocks */
375         SND_SOC_DAPM_CLOCK_SUPPLY("audioclk"),
376 
377         /* Regulators */
378         SND_SOC_DAPM_REGULATOR_SUPPLY("V-AUD", 0, 0),
379         SND_SOC_DAPM_REGULATOR_SUPPLY("V-AMIC1", 0, 0),
380         SND_SOC_DAPM_REGULATOR_SUPPLY("V-AMIC2", 0, 0),
381         SND_SOC_DAPM_REGULATOR_SUPPLY("V-DMIC", 0, 0),
382 
383         /* Power */
384         SND_SOC_DAPM_SUPPLY("Audio Power",
385                         AB8500_POWERUP, AB8500_POWERUP_POWERUP, 0,
386                         NULL, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
387         SND_SOC_DAPM_SUPPLY("Audio Analog Power",
388                         AB8500_POWERUP, AB8500_POWERUP_ENANA, 0,
389                         NULL, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
390 
391         /* Main supply node */
392         SND_SOC_DAPM_SUPPLY("Main Supply", SND_SOC_NOPM, 0, 0,
393                         NULL, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
394 
395         /* DA/AD */
396 
397         SND_SOC_DAPM_INPUT("ADC Input"),
398         SND_SOC_DAPM_ADC("ADC", "ab8500_0c", SND_SOC_NOPM, 0, 0),
399 
400         SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0),
401         SND_SOC_DAPM_OUTPUT("DAC Output"),
402 
403         SND_SOC_DAPM_AIF_IN("DA_IN1", NULL, 0, SND_SOC_NOPM, 0, 0),
404         SND_SOC_DAPM_AIF_IN("DA_IN2", NULL, 0, SND_SOC_NOPM, 0, 0),
405         SND_SOC_DAPM_AIF_IN("DA_IN3", NULL, 0, SND_SOC_NOPM, 0, 0),
406         SND_SOC_DAPM_AIF_IN("DA_IN4", NULL, 0, SND_SOC_NOPM, 0, 0),
407         SND_SOC_DAPM_AIF_IN("DA_IN5", NULL, 0, SND_SOC_NOPM, 0, 0),
408         SND_SOC_DAPM_AIF_IN("DA_IN6", NULL, 0, SND_SOC_NOPM, 0, 0),
409         SND_SOC_DAPM_AIF_OUT("AD_OUT1", NULL, 0, SND_SOC_NOPM, 0, 0),
410         SND_SOC_DAPM_AIF_OUT("AD_OUT2", NULL, 0, SND_SOC_NOPM, 0, 0),
411         SND_SOC_DAPM_AIF_OUT("AD_OUT3", NULL, 0, SND_SOC_NOPM, 0, 0),
412         SND_SOC_DAPM_AIF_OUT("AD_OUT4", NULL, 0, SND_SOC_NOPM, 0, 0),
413         SND_SOC_DAPM_AIF_OUT("AD_OUT57", NULL, 0, SND_SOC_NOPM, 0, 0),
414         SND_SOC_DAPM_AIF_OUT("AD_OUT68", NULL, 0, SND_SOC_NOPM, 0, 0),
415 
416         /* Headset path */
417 
418         SND_SOC_DAPM_SUPPLY("Charge Pump", AB8500_ANACONF5,
419                         AB8500_ANACONF5_ENCPHS, 0, NULL, 0),
420 
421         SND_SOC_DAPM_DAC("DA1 Enable", "ab8500_0p",
422                         AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA1, 0),
423         SND_SOC_DAPM_DAC("DA2 Enable", "ab8500_0p",
424                         AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA2, 0),
425 
426         SND_SOC_DAPM_PGA("HSL Digital Volume", SND_SOC_NOPM, 0, 0,
427                         NULL, 0),
428         SND_SOC_DAPM_PGA("HSR Digital Volume", SND_SOC_NOPM, 0, 0,
429                         NULL, 0),
430 
431         SND_SOC_DAPM_DAC("HSL DAC", "ab8500_0p",
432                         AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACHSL, 0),
433         SND_SOC_DAPM_DAC("HSR DAC", "ab8500_0p",
434                         AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACHSR, 0),
435         SND_SOC_DAPM_MIXER("HSL DAC Mute", AB8500_MUTECONF,
436                         AB8500_MUTECONF_MUTDACHSL, 1,
437                         NULL, 0),
438         SND_SOC_DAPM_MIXER("HSR DAC Mute", AB8500_MUTECONF,
439                         AB8500_MUTECONF_MUTDACHSR, 1,
440                         NULL, 0),
441         SND_SOC_DAPM_DAC("HSL DAC Driver", "ab8500_0p",
442                         AB8500_ANACONF3, AB8500_ANACONF3_ENDRVHSL, 0),
443         SND_SOC_DAPM_DAC("HSR DAC Driver", "ab8500_0p",
444                         AB8500_ANACONF3, AB8500_ANACONF3_ENDRVHSR, 0),
445 
446         SND_SOC_DAPM_MIXER("HSL Mute",
447                         AB8500_MUTECONF, AB8500_MUTECONF_MUTHSL, 1,
448                         NULL, 0),
449         SND_SOC_DAPM_MIXER("HSR Mute",
450                         AB8500_MUTECONF, AB8500_MUTECONF_MUTHSR, 1,
451                         NULL, 0),
452         SND_SOC_DAPM_MIXER("HSL Enable",
453                         AB8500_ANACONF4, AB8500_ANACONF4_ENHSL, 0,
454                         NULL, 0),
455         SND_SOC_DAPM_MIXER("HSR Enable",
456                         AB8500_ANACONF4, AB8500_ANACONF4_ENHSR, 0,
457                         NULL, 0),
458         SND_SOC_DAPM_PGA("HSL Volume",
459                         SND_SOC_NOPM, 0, 0,
460                         NULL, 0),
461         SND_SOC_DAPM_PGA("HSR Volume",
462                         SND_SOC_NOPM, 0, 0,
463                         NULL, 0),
464 
465         SND_SOC_DAPM_OUTPUT("Headset Left"),
466         SND_SOC_DAPM_OUTPUT("Headset Right"),
467 
468         /* LineOut path */
469 
470         SND_SOC_DAPM_MUX("LineOut Source",
471                         SND_SOC_NOPM, 0, 0, dapm_lineout_source),
472 
473         SND_SOC_DAPM_MIXER("LOL Disable HFL",
474                         AB8500_ANACONF4, AB8500_ANACONF4_ENHFL, 1,
475                         NULL, 0),
476         SND_SOC_DAPM_MIXER("LOR Disable HFR",
477                         AB8500_ANACONF4, AB8500_ANACONF4_ENHFR, 1,
478                         NULL, 0),
479 
480         SND_SOC_DAPM_MIXER("LOL Enable",
481                         AB8500_ANACONF5, AB8500_ANACONF5_ENLOL, 0,
482                         NULL, 0),
483         SND_SOC_DAPM_MIXER("LOR Enable",
484                         AB8500_ANACONF5, AB8500_ANACONF5_ENLOR, 0,
485                         NULL, 0),
486 
487         SND_SOC_DAPM_OUTPUT("LineOut Left"),
488         SND_SOC_DAPM_OUTPUT("LineOut Right"),
489 
490         /* Earpiece path */
491 
492         SND_SOC_DAPM_MUX("Earpiece or LineOut Mono Source",
493                         SND_SOC_NOPM, 0, 0, &dapm_ear_lineout_source),
494         SND_SOC_DAPM_MIXER("EAR DAC",
495                         AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACEAR, 0,
496                         NULL, 0),
497         SND_SOC_DAPM_MIXER("EAR Mute",
498                         AB8500_MUTECONF, AB8500_MUTECONF_MUTEAR, 1,
499                         NULL, 0),
500         SND_SOC_DAPM_MIXER("EAR Enable",
501                         AB8500_ANACONF4, AB8500_ANACONF4_ENEAR, 0,
502                         NULL, 0),
503 
504         SND_SOC_DAPM_OUTPUT("Earpiece"),
505 
506         /* Handsfree path */
507 
508         SND_SOC_DAPM_MIXER("DA3 Channel Volume",
509                         AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA3, 0,
510                         NULL, 0),
511         SND_SOC_DAPM_MIXER("DA4 Channel Volume",
512                         AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA4, 0,
513                         NULL, 0),
514         SND_SOC_DAPM_MUX("Speaker Left Source",
515                         SND_SOC_NOPM, 0, 0, dapm_HFl_select),
516         SND_SOC_DAPM_MUX("Speaker Right Source",
517                         SND_SOC_NOPM, 0, 0, dapm_HFr_select),
518         SND_SOC_DAPM_MIXER("HFL DAC", AB8500_DAPATHCONF,
519                         AB8500_DAPATHCONF_ENDACHFL, 0,
520                         NULL, 0),
521         SND_SOC_DAPM_MIXER("HFR DAC",
522                         AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACHFR, 0,
523                         NULL, 0),
524         SND_SOC_DAPM_MIXER("DA4 or ANC path to HfR",
525                         AB8500_DIGMULTCONF2, AB8500_DIGMULTCONF2_DATOHFREN, 0,
526                         NULL, 0),
527         SND_SOC_DAPM_MIXER("DA3 or ANC path to HfL",
528                         AB8500_DIGMULTCONF2, AB8500_DIGMULTCONF2_DATOHFLEN, 0,
529                         NULL, 0),
530         SND_SOC_DAPM_MIXER("HFL Enable",
531                         AB8500_ANACONF4, AB8500_ANACONF4_ENHFL, 0,
532                         NULL, 0),
533         SND_SOC_DAPM_MIXER("HFR Enable",
534                         AB8500_ANACONF4, AB8500_ANACONF4_ENHFR, 0,
535                         NULL, 0),
536 
537         SND_SOC_DAPM_OUTPUT("Speaker Left"),
538         SND_SOC_DAPM_OUTPUT("Speaker Right"),
539 
540         /* Vibrator path */
541 
542         SND_SOC_DAPM_INPUT("PWMGEN1"),
543         SND_SOC_DAPM_INPUT("PWMGEN2"),
544 
545         SND_SOC_DAPM_MIXER("DA5 Channel Volume",
546                         AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA5, 0,
547                         NULL, 0),
548         SND_SOC_DAPM_MIXER("DA6 Channel Volume",
549                         AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA6, 0,
550                         NULL, 0),
551         SND_SOC_DAPM_MIXER("VIB1 DAC",
552                         AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACVIB1, 0,
553                         NULL, 0),
554         SND_SOC_DAPM_MIXER("VIB2 DAC",
555                         AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACVIB2, 0,
556                         NULL, 0),
557         SND_SOC_DAPM_MUX("Vibra 1 Controller",
558                         SND_SOC_NOPM, 0, 0, dapm_pwm2vib1),
559         SND_SOC_DAPM_MUX("Vibra 2 Controller",
560                         SND_SOC_NOPM, 0, 0, dapm_pwm2vib2),
561         SND_SOC_DAPM_MIXER("VIB1 Enable",
562                         AB8500_ANACONF4, AB8500_ANACONF4_ENVIB1, 0,
563                         NULL, 0),
564         SND_SOC_DAPM_MIXER("VIB2 Enable",
565                         AB8500_ANACONF4, AB8500_ANACONF4_ENVIB2, 0,
566                         NULL, 0),
567 
568         SND_SOC_DAPM_OUTPUT("Vibra 1"),
569         SND_SOC_DAPM_OUTPUT("Vibra 2"),
570 
571         /* Mic 1 */
572 
573         SND_SOC_DAPM_INPUT("Mic 1"),
574 
575         SND_SOC_DAPM_MUX("Mic 1a or 1b Select",
576                         SND_SOC_NOPM, 0, 0, dapm_mic1ab_mux),
577         SND_SOC_DAPM_MIXER("MIC1 Mute",
578                         AB8500_ANACONF2, AB8500_ANACONF2_MUTMIC1, 1,
579                         NULL, 0),
580         SND_SOC_DAPM_MIXER("MIC1A V-AMICx Enable",
581                         AB8500_ANACONF2, AB8500_ANACONF2_ENMIC1, 0,
582                         NULL, 0),
583         SND_SOC_DAPM_MIXER("MIC1B V-AMICx Enable",
584                         AB8500_ANACONF2, AB8500_ANACONF2_ENMIC1, 0,
585                         NULL, 0),
586         SND_SOC_DAPM_MIXER("MIC1 ADC",
587                         AB8500_ANACONF3, AB8500_ANACONF3_ENADCMIC, 0,
588                         NULL, 0),
589         SND_SOC_DAPM_MUX("AD3 Source Select",
590                         SND_SOC_NOPM, 0, 0, dapm_ad3_select),
591         SND_SOC_DAPM_MIXER("AD3 Channel Volume",
592                         SND_SOC_NOPM, 0, 0,
593                         NULL, 0),
594         SND_SOC_DAPM_MIXER("AD3 Enable",
595                         AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD34, 0,
596                         NULL, 0),
597 
598         /* Mic 2 */
599 
600         SND_SOC_DAPM_INPUT("Mic 2"),
601 
602         SND_SOC_DAPM_MIXER("MIC2 Mute",
603                         AB8500_ANACONF2, AB8500_ANACONF2_MUTMIC2, 1,
604                         NULL, 0),
605         SND_SOC_DAPM_MIXER("MIC2 V-AMICx Enable", AB8500_ANACONF2,
606                         AB8500_ANACONF2_ENMIC2, 0,
607                         NULL, 0),
608 
609         /* LineIn */
610 
611         SND_SOC_DAPM_INPUT("LineIn Left"),
612         SND_SOC_DAPM_INPUT("LineIn Right"),
613 
614         SND_SOC_DAPM_MIXER("LINL Mute",
615                         AB8500_ANACONF2, AB8500_ANACONF2_MUTLINL, 1,
616                         NULL, 0),
617         SND_SOC_DAPM_MIXER("LINR Mute",
618                         AB8500_ANACONF2, AB8500_ANACONF2_MUTLINR, 1,
619                         NULL, 0),
620         SND_SOC_DAPM_MIXER("LINL Enable", AB8500_ANACONF2,
621                         AB8500_ANACONF2_ENLINL, 0,
622                         NULL, 0),
623         SND_SOC_DAPM_MIXER("LINR Enable", AB8500_ANACONF2,
624                         AB8500_ANACONF2_ENLINR, 0,
625                         NULL, 0),
626 
627         /* LineIn Bypass path */
628         SND_SOC_DAPM_MIXER("LINL to HSL Volume",
629                         SND_SOC_NOPM, 0, 0,
630                         NULL, 0),
631         SND_SOC_DAPM_MIXER("LINR to HSR Volume",
632                         SND_SOC_NOPM, 0, 0,
633                         NULL, 0),
634 
635         /* LineIn, Mic 2 */
636         SND_SOC_DAPM_MUX("Mic 2 or LINR Select",
637                         SND_SOC_NOPM, 0, 0, dapm_mic2lr_select),
638         SND_SOC_DAPM_MIXER("LINL ADC", AB8500_ANACONF3,
639                         AB8500_ANACONF3_ENADCLINL, 0,
640                         NULL, 0),
641         SND_SOC_DAPM_MIXER("LINR ADC", AB8500_ANACONF3,
642                         AB8500_ANACONF3_ENADCLINR, 0,
643                         NULL, 0),
644         SND_SOC_DAPM_MUX("AD1 Source Select",
645                         SND_SOC_NOPM, 0, 0, dapm_ad1_select),
646         SND_SOC_DAPM_MUX("AD2 Source Select",
647                         SND_SOC_NOPM, 0, 0, dapm_ad2_select),
648         SND_SOC_DAPM_MIXER("AD1 Channel Volume",
649                         SND_SOC_NOPM, 0, 0,
650                         NULL, 0),
651         SND_SOC_DAPM_MIXER("AD2 Channel Volume",
652                         SND_SOC_NOPM, 0, 0,
653                         NULL, 0),
654 
655         SND_SOC_DAPM_MIXER("AD12 Enable",
656                         AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD12, 0,
657                         NULL, 0),
658 
659         /* HD Capture path */
660 
661         SND_SOC_DAPM_MUX("AD5 Source Select",
662                         SND_SOC_NOPM, 0, 0, dapm_ad5_select),
663         SND_SOC_DAPM_MUX("AD6 Source Select",
664                         SND_SOC_NOPM, 0, 0, dapm_ad6_select),
665         SND_SOC_DAPM_MIXER("AD5 Channel Volume",
666                         SND_SOC_NOPM, 0, 0,
667                         NULL, 0),
668         SND_SOC_DAPM_MIXER("AD6 Channel Volume",
669                         SND_SOC_NOPM, 0, 0,
670                         NULL, 0),
671         SND_SOC_DAPM_MIXER("AD57 Enable",
672                         AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD5768, 0,
673                         NULL, 0),
674         SND_SOC_DAPM_MIXER("AD68 Enable",
675                         AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD5768, 0,
676                         NULL, 0),
677 
678         /* Digital Microphone path */
679 
680         SND_SOC_DAPM_INPUT("DMic 1"),
681         SND_SOC_DAPM_INPUT("DMic 2"),
682         SND_SOC_DAPM_INPUT("DMic 3"),
683         SND_SOC_DAPM_INPUT("DMic 4"),
684         SND_SOC_DAPM_INPUT("DMic 5"),
685         SND_SOC_DAPM_INPUT("DMic 6"),
686 
687         SND_SOC_DAPM_MIXER("DMIC1",
688                         AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC1, 0,
689                         NULL, 0),
690         SND_SOC_DAPM_MIXER("DMIC2",
691                         AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC2, 0,
692                         NULL, 0),
693         SND_SOC_DAPM_MIXER("DMIC3",
694                         AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC3, 0,
695                         NULL, 0),
696         SND_SOC_DAPM_MIXER("DMIC4",
697                         AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC4, 0,
698                         NULL, 0),
699         SND_SOC_DAPM_MIXER("DMIC5",
700                         AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC5, 0,
701                         NULL, 0),
702         SND_SOC_DAPM_MIXER("DMIC6",
703                         AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC6, 0,
704                         NULL, 0),
705         SND_SOC_DAPM_MIXER("AD4 Channel Volume",
706                         SND_SOC_NOPM, 0, 0,
707                         NULL, 0),
708         SND_SOC_DAPM_MIXER("AD4 Enable",
709                         AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD34,
710                         0, NULL, 0),
711 
712         /* Acoustical Noise Cancellation path */
713 
714         SND_SOC_DAPM_INPUT("ANC Configure Input"),
715         SND_SOC_DAPM_OUTPUT("ANC Configure Output"),
716 
717         SND_SOC_DAPM_MUX("ANC Source",
718                         SND_SOC_NOPM, 0, 0,
719                         dapm_anc_in_select),
720         SND_SOC_DAPM_SWITCH("ANC",
721                         SND_SOC_NOPM, 0, 0,
722                         dapm_anc_enable),
723         SND_SOC_DAPM_SWITCH("ANC to Earpiece",
724                         SND_SOC_NOPM, 0, 0,
725                         dapm_anc_ear_mute),
726 
727         /* Sidetone Filter path */
728 
729         SND_SOC_DAPM_MUX("Sidetone Left Source",
730                         SND_SOC_NOPM, 0, 0,
731                         dapm_stfir1_in_select),
732         SND_SOC_DAPM_MUX("Sidetone Right Source",
733                         SND_SOC_NOPM, 0, 0,
734                         dapm_stfir2_in_select),
735         SND_SOC_DAPM_MIXER("STFIR1 Control",
736                         SND_SOC_NOPM, 0, 0,
737                         NULL, 0),
738         SND_SOC_DAPM_MIXER("STFIR2 Control",
739                         SND_SOC_NOPM, 0, 0,
740                         NULL, 0),
741         SND_SOC_DAPM_MIXER("STFIR1 Volume",
742                         SND_SOC_NOPM, 0, 0,
743                         NULL, 0),
744         SND_SOC_DAPM_MIXER("STFIR2 Volume",
745                         SND_SOC_NOPM, 0, 0,
746                         NULL, 0),
747 };
748 
749 /*
750  * DAPM-routes
751  */
752 static const struct snd_soc_dapm_route ab8500_dapm_routes[] = {
753         /* Power AB8500 audio-block when AD/DA is active */
754         {"Main Supply", NULL, "V-AUD"},
755         {"Main Supply", NULL, "audioclk"},
756         {"Main Supply", NULL, "Audio Power"},
757         {"Main Supply", NULL, "Audio Analog Power"},
758 
759         {"DAC", NULL, "ab8500_0p"},
760         {"DAC", NULL, "Main Supply"},
761         {"ADC", NULL, "ab8500_0c"},
762         {"ADC", NULL, "Main Supply"},
763 
764         /* ANC Configure */
765         {"ANC Configure Input", NULL, "Main Supply"},
766         {"ANC Configure Output", NULL, "ANC Configure Input"},
767 
768         /* AD/DA */
769         {"ADC", NULL, "ADC Input"},
770         {"DAC Output", NULL, "DAC"},
771 
772         /* Powerup charge pump if DA1/2 is in use */
773 
774         {"DA_IN1", NULL, "ab8500_0p"},
775         {"DA_IN1", NULL, "Charge Pump"},
776         {"DA_IN2", NULL, "ab8500_0p"},
777         {"DA_IN2", NULL, "Charge Pump"},
778 
779         /* Headset path */
780 
781         {"DA1 Enable", NULL, "DA_IN1"},
782         {"DA2 Enable", NULL, "DA_IN2"},
783 
784         {"HSL Digital Volume", NULL, "DA1 Enable"},
785         {"HSR Digital Volume", NULL, "DA2 Enable"},
786 
787         {"HSL DAC", NULL, "HSL Digital Volume"},
788         {"HSR DAC", NULL, "HSR Digital Volume"},
789 
790         {"HSL DAC Mute", NULL, "HSL DAC"},
791         {"HSR DAC Mute", NULL, "HSR DAC"},
792 
793         {"HSL DAC Driver", NULL, "HSL DAC Mute"},
794         {"HSR DAC Driver", NULL, "HSR DAC Mute"},
795 
796         {"HSL Mute", NULL, "HSL DAC Driver"},
797         {"HSR Mute", NULL, "HSR DAC Driver"},
798 
799         {"HSL Enable", NULL, "HSL Mute"},
800         {"HSR Enable", NULL, "HSR Mute"},
801 
802         {"HSL Volume", NULL, "HSL Enable"},
803         {"HSR Volume", NULL, "HSR Enable"},
804 
805         {"Headset Left", NULL, "HSL Volume"},
806         {"Headset Right", NULL, "HSR Volume"},
807 
808         /* HF or LineOut path */
809 
810         {"DA_IN3", NULL, "ab8500_0p"},
811         {"DA3 Channel Volume", NULL, "DA_IN3"},
812         {"DA_IN4", NULL, "ab8500_0p"},
813         {"DA4 Channel Volume", NULL, "DA_IN4"},
814 
815         {"Speaker Left Source", "Audio Path", "DA3 Channel Volume"},
816         {"Speaker Right Source", "Audio Path", "DA4 Channel Volume"},
817 
818         {"DA3 or ANC path to HfL", NULL, "Speaker Left Source"},
819         {"DA4 or ANC path to HfR", NULL, "Speaker Right Source"},
820 
821         /* HF path */
822 
823         {"HFL DAC", NULL, "DA3 or ANC path to HfL"},
824         {"HFR DAC", NULL, "DA4 or ANC path to HfR"},
825 
826         {"HFL Enable", NULL, "HFL DAC"},
827         {"HFR Enable", NULL, "HFR DAC"},
828 
829         {"Speaker Left", NULL, "HFL Enable"},
830         {"Speaker Right", NULL, "HFR Enable"},
831 
832         /* Earpiece path */
833 
834         {"Earpiece or LineOut Mono Source", "Headset Left",
835                 "HSL Digital Volume"},
836         {"Earpiece or LineOut Mono Source", "Speaker Left",
837                 "DA3 or ANC path to HfL"},
838 
839         {"EAR DAC", NULL, "Earpiece or LineOut Mono Source"},
840 
841         {"EAR Mute", NULL, "EAR DAC"},
842 
843         {"EAR Enable", NULL, "EAR Mute"},
844 
845         {"Earpiece", NULL, "EAR Enable"},
846 
847         /* LineOut path stereo */
848 
849         {"LineOut Source", "Stereo Path", "HSL DAC Driver"},
850         {"LineOut Source", "Stereo Path", "HSR DAC Driver"},
851 
852         /* LineOut path mono */
853 
854         {"LineOut Source", "Mono Path", "EAR DAC"},
855 
856         /* LineOut path */
857 
858         {"LOL Disable HFL", NULL, "LineOut Source"},
859         {"LOR Disable HFR", NULL, "LineOut Source"},
860 
861         {"LOL Enable", NULL, "LOL Disable HFL"},
862         {"LOR Enable", NULL, "LOR Disable HFR"},
863 
864         {"LineOut Left", NULL, "LOL Enable"},
865         {"LineOut Right", NULL, "LOR Enable"},
866 
867         /* Vibrator path */
868 
869         {"DA_IN5", NULL, "ab8500_0p"},
870         {"DA5 Channel Volume", NULL, "DA_IN5"},
871         {"DA_IN6", NULL, "ab8500_0p"},
872         {"DA6 Channel Volume", NULL, "DA_IN6"},
873 
874         {"VIB1 DAC", NULL, "DA5 Channel Volume"},
875         {"VIB2 DAC", NULL, "DA6 Channel Volume"},
876 
877         {"Vibra 1 Controller", "Audio Path", "VIB1 DAC"},
878         {"Vibra 2 Controller", "Audio Path", "VIB2 DAC"},
879         {"Vibra 1 Controller", "PWM Generator", "PWMGEN1"},
880         {"Vibra 2 Controller", "PWM Generator", "PWMGEN2"},
881 
882         {"VIB1 Enable", NULL, "Vibra 1 Controller"},
883         {"VIB2 Enable", NULL, "Vibra 2 Controller"},
884 
885         {"Vibra 1", NULL, "VIB1 Enable"},
886         {"Vibra 2", NULL, "VIB2 Enable"},
887 
888 
889         /* Mic 2 */
890 
891         {"MIC2 V-AMICx Enable", NULL, "Mic 2"},
892 
893         /* LineIn */
894         {"LINL Mute", NULL, "LineIn Left"},
895         {"LINR Mute", NULL, "LineIn Right"},
896 
897         {"LINL Enable", NULL, "LINL Mute"},
898         {"LINR Enable", NULL, "LINR Mute"},
899 
900         /* LineIn, Mic 2 */
901         {"Mic 2 or LINR Select", "LineIn Right", "LINR Enable"},
902         {"Mic 2 or LINR Select", "Mic 2", "MIC2 V-AMICx Enable"},
903 
904         {"LINL ADC", NULL, "LINL Enable"},
905         {"LINR ADC", NULL, "Mic 2 or LINR Select"},
906 
907         {"AD1 Source Select", "LineIn Left", "LINL ADC"},
908         {"AD2 Source Select", "LineIn Right", "LINR ADC"},
909 
910         {"AD1 Channel Volume", NULL, "AD1 Source Select"},
911         {"AD2 Channel Volume", NULL, "AD2 Source Select"},
912 
913         {"AD12 Enable", NULL, "AD1 Channel Volume"},
914         {"AD12 Enable", NULL, "AD2 Channel Volume"},
915 
916         {"AD_OUT1", NULL, "ab8500_0c"},
917         {"AD_OUT1", NULL, "AD12 Enable"},
918         {"AD_OUT2", NULL, "ab8500_0c"},
919         {"AD_OUT2", NULL, "AD12 Enable"},
920 
921         /* Mic 1 */
922 
923         {"MIC1 Mute", NULL, "Mic 1"},
924 
925         {"MIC1A V-AMICx Enable", NULL, "MIC1 Mute"},
926         {"MIC1B V-AMICx Enable", NULL, "MIC1 Mute"},
927 
928         {"Mic 1a or 1b Select", "Mic 1a", "MIC1A V-AMICx Enable"},
929         {"Mic 1a or 1b Select", "Mic 1b", "MIC1B V-AMICx Enable"},
930 
931         {"MIC1 ADC", NULL, "Mic 1a or 1b Select"},
932 
933         {"AD3 Source Select", "Mic 1", "MIC1 ADC"},
934 
935         {"AD3 Channel Volume", NULL, "AD3 Source Select"},
936 
937         {"AD3 Enable", NULL, "AD3 Channel Volume"},
938 
939         {"AD_OUT3", NULL, "ab8500_0c"},
940         {"AD_OUT3", NULL, "AD3 Enable"},
941 
942         /* HD Capture path */
943 
944         {"AD5 Source Select", "Mic 2", "LINR ADC"},
945         {"AD6 Source Select", "Mic 1", "MIC1 ADC"},
946 
947         {"AD5 Channel Volume", NULL, "AD5 Source Select"},
948         {"AD6 Channel Volume", NULL, "AD6 Source Select"},
949 
950         {"AD57 Enable", NULL, "AD5 Channel Volume"},
951         {"AD68 Enable", NULL, "AD6 Channel Volume"},
952 
953         {"AD_OUT57", NULL, "ab8500_0c"},
954         {"AD_OUT57", NULL, "AD57 Enable"},
955         {"AD_OUT68", NULL, "ab8500_0c"},
956         {"AD_OUT68", NULL, "AD68 Enable"},
957 
958         /* Digital Microphone path */
959 
960         {"DMic 1", NULL, "V-DMIC"},
961         {"DMic 2", NULL, "V-DMIC"},
962         {"DMic 3", NULL, "V-DMIC"},
963         {"DMic 4", NULL, "V-DMIC"},
964         {"DMic 5", NULL, "V-DMIC"},
965         {"DMic 6", NULL, "V-DMIC"},
966 
967         {"AD1 Source Select", NULL, "DMic 1"},
968         {"AD2 Source Select", NULL, "DMic 2"},
969         {"AD3 Source Select", NULL, "DMic 3"},
970         {"AD5 Source Select", NULL, "DMic 5"},
971         {"AD6 Source Select", NULL, "DMic 6"},
972 
973         {"AD4 Channel Volume", NULL, "DMic 4"},
974         {"AD4 Enable", NULL, "AD4 Channel Volume"},
975 
976         {"AD_OUT4", NULL, "ab8500_0c"},
977         {"AD_OUT4", NULL, "AD4 Enable"},
978 
979         /* LineIn Bypass path */
980 
981         {"LINL to HSL Volume", NULL, "LINL Enable"},
982         {"LINR to HSR Volume", NULL, "LINR Enable"},
983 
984         {"HSL DAC Driver", NULL, "LINL to HSL Volume"},
985         {"HSR DAC Driver", NULL, "LINR to HSR Volume"},
986 
987         /* ANC path (Acoustic Noise Cancellation) */
988 
989         {"ANC Source", "Mic 2 / DMic 5", "AD5 Channel Volume"},
990         {"ANC Source", "Mic 1 / DMic 6", "AD6 Channel Volume"},
991 
992         {"ANC", "Switch", "ANC Source"},
993 
994         {"Speaker Left Source", "ANC", "ANC"},
995         {"Speaker Right Source", "ANC", "ANC"},
996         {"ANC to Earpiece", "Switch", "ANC"},
997 
998         {"HSL Digital Volume", NULL, "ANC to Earpiece"},
999 
1000         /* Sidetone Filter path */
1001 
1002         {"Sidetone Left Source", "LineIn Left", "AD12 Enable"},
1003         {"Sidetone Left Source", "LineIn Right", "AD12 Enable"},
1004         {"Sidetone Left Source", "Mic 1", "AD3 Enable"},
1005         {"Sidetone Left Source", "Headset Left", "DA_IN1"},
1006         {"Sidetone Right Source", "LineIn Right", "AD12 Enable"},
1007         {"Sidetone Right Source", "Mic 1", "AD3 Enable"},
1008         {"Sidetone Right Source", "DMic 4", "AD4 Enable"},
1009         {"Sidetone Right Source", "Headset Right", "DA_IN2"},
1010 
1011         {"STFIR1 Control", NULL, "Sidetone Left Source"},
1012         {"STFIR2 Control", NULL, "Sidetone Right Source"},
1013 
1014         {"STFIR1 Volume", NULL, "STFIR1 Control"},
1015         {"STFIR2 Volume", NULL, "STFIR2 Control"},
1016 
1017         {"DA1 Enable", NULL, "STFIR1 Volume"},
1018         {"DA2 Enable", NULL, "STFIR2 Volume"},
1019 };
1020 
1021 static const struct snd_soc_dapm_route ab8500_dapm_routes_mic1a_vamicx[] = {
1022         {"MIC1A V-AMICx Enable", NULL, "V-AMIC1"},
1023         {"MIC1A V-AMICx Enable", NULL, "V-AMIC2"},
1024 };
1025 
1026 static const struct snd_soc_dapm_route ab8500_dapm_routes_mic1b_vamicx[] = {
1027         {"MIC1B V-AMICx Enable", NULL, "V-AMIC1"},
1028         {"MIC1B V-AMICx Enable", NULL, "V-AMIC2"},
1029 };
1030 
1031 static const struct snd_soc_dapm_route ab8500_dapm_routes_mic2_vamicx[] = {
1032         {"MIC2 V-AMICx Enable", NULL, "V-AMIC1"},
1033         {"MIC2 V-AMICx Enable", NULL, "V-AMIC2"},
1034 };
1035 
1036 /* ANC FIR-coefficients configuration sequence */
1037 static void anc_fir(struct snd_soc_component *component,
1038                 unsigned int bnk, unsigned int par, unsigned int val)
1039 {
1040         if (par == 0 && bnk == 0)
1041                 snd_soc_component_update_bits(component, AB8500_ANCCONF1,
1042                         BIT(AB8500_ANCCONF1_ANCFIRUPDATE),
1043                         BIT(AB8500_ANCCONF1_ANCFIRUPDATE));
1044 
1045         snd_soc_component_write(component, AB8500_ANCCONF5, val >> 8 & 0xff);
1046         snd_soc_component_write(component, AB8500_ANCCONF6, val &  0xff);
1047 
1048         if (par == AB8500_ANC_FIR_COEFFS - 1 && bnk == 1)
1049                 snd_soc_component_update_bits(component, AB8500_ANCCONF1,
1050                         BIT(AB8500_ANCCONF1_ANCFIRUPDATE), 0);
1051 }
1052 
1053 /* ANC IIR-coefficients configuration sequence */
1054 static void anc_iir(struct snd_soc_component *component, unsigned int bnk,
1055                 unsigned int par, unsigned int val)
1056 {
1057         if (par == 0) {
1058                 if (bnk == 0) {
1059                         snd_soc_component_update_bits(component, AB8500_ANCCONF1,
1060                                         BIT(AB8500_ANCCONF1_ANCIIRINIT),
1061                                         BIT(AB8500_ANCCONF1_ANCIIRINIT));
1062                         usleep_range(AB8500_ANC_SM_DELAY, AB8500_ANC_SM_DELAY*2);
1063                         snd_soc_component_update_bits(component, AB8500_ANCCONF1,
1064                                         BIT(AB8500_ANCCONF1_ANCIIRINIT), 0);
1065                         usleep_range(AB8500_ANC_SM_DELAY, AB8500_ANC_SM_DELAY*2);
1066                 } else {
1067                         snd_soc_component_update_bits(component, AB8500_ANCCONF1,
1068                                         BIT(AB8500_ANCCONF1_ANCIIRUPDATE),
1069                                         BIT(AB8500_ANCCONF1_ANCIIRUPDATE));
1070                 }
1071         } else if (par > 3) {
1072                 snd_soc_component_write(component, AB8500_ANCCONF7, 0);
1073                 snd_soc_component_write(component, AB8500_ANCCONF8, val >> 16 & 0xff);
1074         }
1075 
1076         snd_soc_component_write(component, AB8500_ANCCONF7, val >> 8 & 0xff);
1077         snd_soc_component_write(component, AB8500_ANCCONF8, val & 0xff);
1078 
1079         if (par == AB8500_ANC_IIR_COEFFS - 1 && bnk == 1)
1080                 snd_soc_component_update_bits(component, AB8500_ANCCONF1,
1081                         BIT(AB8500_ANCCONF1_ANCIIRUPDATE), 0);
1082 }
1083 
1084 /* ANC IIR-/FIR-coefficients configuration sequence */
1085 static void anc_configure(struct snd_soc_component *component,
1086                         bool apply_fir, bool apply_iir)
1087 {
1088         struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(component->dev);
1089         unsigned int bnk, par, val;
1090 
1091         dev_dbg(component->dev, "%s: Enter.\n", __func__);
1092 
1093         if (apply_fir)
1094                 snd_soc_component_update_bits(component, AB8500_ANCCONF1,
1095                         BIT(AB8500_ANCCONF1_ENANC), 0);
1096 
1097         snd_soc_component_update_bits(component, AB8500_ANCCONF1,
1098                 BIT(AB8500_ANCCONF1_ENANC), BIT(AB8500_ANCCONF1_ENANC));
1099 
1100         if (apply_fir)
1101                 for (bnk = 0; bnk < AB8500_NR_OF_ANC_COEFF_BANKS; bnk++)
1102                         for (par = 0; par < AB8500_ANC_FIR_COEFFS; par++) {
1103                                 val = snd_soc_component_read32(component,
1104                                                 drvdata->anc_fir_values[par]);
1105                                 anc_fir(component, bnk, par, val);
1106                         }
1107 
1108         if (apply_iir)
1109                 for (bnk = 0; bnk < AB8500_NR_OF_ANC_COEFF_BANKS; bnk++)
1110                         for (par = 0; par < AB8500_ANC_IIR_COEFFS; par++) {
1111                                 val = snd_soc_component_read32(component,
1112                                                 drvdata->anc_iir_values[par]);
1113                                 anc_iir(component, bnk, par, val);
1114                         }
1115 
1116         dev_dbg(component->dev, "%s: Exit.\n", __func__);
1117 }
1118 
1119 /*
1120  * Control-events
1121  */
1122 
1123 static int sid_status_control_get(struct snd_kcontrol *kcontrol,
1124                 struct snd_ctl_elem_value *ucontrol)
1125 {
1126         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1127         struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(component->dev);
1128 
1129         mutex_lock(&drvdata->ctrl_lock);
1130         ucontrol->value.enumerated.item[0] = drvdata->sid_status;
1131         mutex_unlock(&drvdata->ctrl_lock);
1132 
1133         return 0;
1134 }
1135 
1136 /* Write sidetone FIR-coefficients configuration sequence */
1137 static int sid_status_control_put(struct snd_kcontrol *kcontrol,
1138                                 struct snd_ctl_elem_value *ucontrol)
1139 {
1140         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1141         struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(component->dev);
1142         unsigned int param, sidconf, val;
1143         int status = 1;
1144 
1145         dev_dbg(component->dev, "%s: Enter\n", __func__);
1146 
1147         if (ucontrol->value.enumerated.item[0] != SID_APPLY_FIR) {
1148                 dev_err(component->dev,
1149                         "%s: ERROR: This control supports '%s' only!\n",
1150                         __func__, enum_sid_state[SID_APPLY_FIR]);
1151                 return -EIO;
1152         }
1153 
1154         mutex_lock(&drvdata->ctrl_lock);
1155 
1156         sidconf = snd_soc_component_read32(component, AB8500_SIDFIRCONF);
1157         if (((sidconf & BIT(AB8500_SIDFIRCONF_FIRSIDBUSY)) != 0)) {
1158                 if ((sidconf & BIT(AB8500_SIDFIRCONF_ENFIRSIDS)) == 0) {
1159                         dev_err(component->dev, "%s: Sidetone busy while off!\n",
1160                                 __func__);
1161                         status = -EPERM;
1162                 } else {
1163                         status = -EBUSY;
1164                 }
1165                 goto out;
1166         }
1167 
1168         snd_soc_component_write(component, AB8500_SIDFIRADR, 0);
1169 
1170         for (param = 0; param < AB8500_SID_FIR_COEFFS; param++) {
1171                 val = snd_soc_component_read32(component, drvdata->sid_fir_values[param]);
1172                 snd_soc_component_write(component, AB8500_SIDFIRCOEF1, val >> 8 & 0xff);
1173                 snd_soc_component_write(component, AB8500_SIDFIRCOEF2, val & 0xff);
1174         }
1175 
1176         snd_soc_component_update_bits(component, AB8500_SIDFIRADR,
1177                 BIT(AB8500_SIDFIRADR_FIRSIDSET),
1178                 BIT(AB8500_SIDFIRADR_FIRSIDSET));
1179         snd_soc_component_update_bits(component, AB8500_SIDFIRADR,
1180                 BIT(AB8500_SIDFIRADR_FIRSIDSET), 0);
1181 
1182         drvdata->sid_status = SID_FIR_CONFIGURED;
1183 
1184 out:
1185         mutex_unlock(&drvdata->ctrl_lock);
1186 
1187         dev_dbg(component->dev, "%s: Exit\n", __func__);
1188 
1189         return status;
1190 }
1191 
1192 static int anc_status_control_get(struct snd_kcontrol *kcontrol,
1193                                 struct snd_ctl_elem_value *ucontrol)
1194 {
1195         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1196         struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(component->dev);
1197 
1198         mutex_lock(&drvdata->ctrl_lock);
1199         ucontrol->value.enumerated.item[0] = drvdata->anc_status;
1200         mutex_unlock(&drvdata->ctrl_lock);
1201 
1202         return 0;
1203 }
1204 
1205 static int anc_status_control_put(struct snd_kcontrol *kcontrol,
1206                                 struct snd_ctl_elem_value *ucontrol)
1207 {
1208         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1209         struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
1210         struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(component->dev);
1211         struct device *dev = component->dev;
1212         bool apply_fir, apply_iir;
1213         unsigned int req;
1214         int status;
1215 
1216         dev_dbg(dev, "%s: Enter.\n", __func__);
1217 
1218         mutex_lock(&drvdata->ctrl_lock);
1219 
1220         req = ucontrol->value.enumerated.item[0];
1221         if (req >= ARRAY_SIZE(enum_anc_state)) {
1222                 status = -EINVAL;
1223                 goto cleanup;
1224         }
1225         if (req != ANC_APPLY_FIR_IIR && req != ANC_APPLY_FIR &&
1226                 req != ANC_APPLY_IIR) {
1227                 dev_err(dev, "%s: ERROR: Unsupported status to set '%s'!\n",
1228                         __func__, enum_anc_state[req]);
1229                 status = -EINVAL;
1230                 goto cleanup;
1231         }
1232         apply_fir = req == ANC_APPLY_FIR || req == ANC_APPLY_FIR_IIR;
1233         apply_iir = req == ANC_APPLY_IIR || req == ANC_APPLY_FIR_IIR;
1234 
1235         status = snd_soc_dapm_force_enable_pin(dapm, "ANC Configure Input");
1236         if (status < 0) {
1237                 dev_err(dev,
1238                         "%s: ERROR: Failed to enable power (status = %d)!\n",
1239                         __func__, status);
1240                 goto cleanup;
1241         }
1242         snd_soc_dapm_sync(dapm);
1243 
1244         anc_configure(component, apply_fir, apply_iir);
1245 
1246         if (apply_fir) {
1247                 if (drvdata->anc_status == ANC_IIR_CONFIGURED)
1248                         drvdata->anc_status = ANC_FIR_IIR_CONFIGURED;
1249                 else if (drvdata->anc_status != ANC_FIR_IIR_CONFIGURED)
1250                         drvdata->anc_status =  ANC_FIR_CONFIGURED;
1251         }
1252         if (apply_iir) {
1253                 if (drvdata->anc_status == ANC_FIR_CONFIGURED)
1254                         drvdata->anc_status = ANC_FIR_IIR_CONFIGURED;
1255                 else if (drvdata->anc_status != ANC_FIR_IIR_CONFIGURED)
1256                         drvdata->anc_status =  ANC_IIR_CONFIGURED;
1257         }
1258 
1259         status = snd_soc_dapm_disable_pin(dapm, "ANC Configure Input");
1260         snd_soc_dapm_sync(dapm);
1261 
1262 cleanup:
1263         mutex_unlock(&drvdata->ctrl_lock);
1264 
1265         if (status < 0)
1266                 dev_err(dev, "%s: Unable to configure ANC! (status = %d)\n",
1267                         __func__, status);
1268 
1269         dev_dbg(dev, "%s: Exit.\n", __func__);
1270 
1271         return (status < 0) ? status : 1;
1272 }
1273 
1274 static int filter_control_info(struct snd_kcontrol *kcontrol,
1275                         struct snd_ctl_elem_info *uinfo)
1276 {
1277         struct filter_control *fc =
1278                         (struct filter_control *)kcontrol->private_value;
1279 
1280         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1281         uinfo->count = fc->count;
1282         uinfo->value.integer.min = fc->min;
1283         uinfo->value.integer.max = fc->max;
1284 
1285         return 0;
1286 }
1287 
1288 static int filter_control_get(struct snd_kcontrol *kcontrol,
1289                         struct snd_ctl_elem_value *ucontrol)
1290 {
1291         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1292         struct ab8500_codec_drvdata *drvdata = snd_soc_component_get_drvdata(component);
1293         struct filter_control *fc =
1294                         (struct filter_control *)kcontrol->private_value;
1295         unsigned int i;
1296 
1297         mutex_lock(&drvdata->ctrl_lock);
1298         for (i = 0; i < fc->count; i++)
1299                 ucontrol->value.integer.value[i] = fc->value[i];
1300         mutex_unlock(&drvdata->ctrl_lock);
1301 
1302         return 0;
1303 }
1304 
1305 static int filter_control_put(struct snd_kcontrol *kcontrol,
1306                 struct snd_ctl_elem_value *ucontrol)
1307 {
1308         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1309         struct ab8500_codec_drvdata *drvdata = snd_soc_component_get_drvdata(component);
1310         struct filter_control *fc =
1311                         (struct filter_control *)kcontrol->private_value;
1312         unsigned int i;
1313 
1314         mutex_lock(&drvdata->ctrl_lock);
1315         for (i = 0; i < fc->count; i++)
1316                 fc->value[i] = ucontrol->value.integer.value[i];
1317         mutex_unlock(&drvdata->ctrl_lock);
1318 
1319         return 0;
1320 }
1321 
1322 /*
1323  * Controls - Non-DAPM ASoC
1324  */
1325 
1326 static DECLARE_TLV_DB_SCALE(adx_dig_gain_tlv, -3200, 100, 1);
1327 /* -32dB = Mute */
1328 
1329 static DECLARE_TLV_DB_SCALE(dax_dig_gain_tlv, -6300, 100, 1);
1330 /* -63dB = Mute */
1331 
1332 static DECLARE_TLV_DB_SCALE(hs_ear_dig_gain_tlv, -100, 100, 1);
1333 /* -1dB = Mute */
1334 
1335 static const DECLARE_TLV_DB_RANGE(hs_gain_tlv,
1336         0, 3, TLV_DB_SCALE_ITEM(-3200, 400, 0),
1337         4, 15, TLV_DB_SCALE_ITEM(-1800, 200, 0)
1338 );
1339 
1340 static DECLARE_TLV_DB_SCALE(mic_gain_tlv, 0, 100, 0);
1341 
1342 static DECLARE_TLV_DB_SCALE(lin_gain_tlv, -1000, 200, 0);
1343 
1344 static DECLARE_TLV_DB_SCALE(lin2hs_gain_tlv, -3800, 200, 1);
1345 /* -38dB = Mute */
1346 
1347 static const char * const enum_hsfadspeed[] = {"2ms", "0.5ms", "10.6ms",
1348                                         "5ms"};
1349 static SOC_ENUM_SINGLE_DECL(soc_enum_hsfadspeed,
1350         AB8500_DIGMICCONF, AB8500_DIGMICCONF_HSFADSPEED, enum_hsfadspeed);
1351 
1352 static const char * const enum_envdetthre[] = {
1353         "250mV", "300mV", "350mV", "400mV",
1354         "450mV", "500mV", "550mV", "600mV",
1355         "650mV", "700mV", "750mV", "800mV",
1356         "850mV", "900mV", "950mV", "1.00V" };
1357 static SOC_ENUM_SINGLE_DECL(soc_enum_envdeththre,
1358         AB8500_ENVCPCONF, AB8500_ENVCPCONF_ENVDETHTHRE, enum_envdetthre);
1359 static SOC_ENUM_SINGLE_DECL(soc_enum_envdetlthre,
1360         AB8500_ENVCPCONF, AB8500_ENVCPCONF_ENVDETLTHRE, enum_envdetthre);
1361 static const char * const enum_envdettime[] = {
1362         "26.6us", "53.2us", "106us",  "213us",
1363         "426us",  "851us",  "1.70ms", "3.40ms",
1364         "6.81ms", "13.6ms", "27.2ms", "54.5ms",
1365         "109ms",  "218ms",  "436ms",  "872ms" };
1366 static SOC_ENUM_SINGLE_DECL(soc_enum_envdettime,
1367         AB8500_SIGENVCONF, AB8500_SIGENVCONF_ENVDETTIME, enum_envdettime);
1368 
1369 static const char * const enum_sinc31[] = {"Sinc 3", "Sinc 1"};
1370 static SOC_ENUM_SINGLE_DECL(soc_enum_hsesinc, AB8500_HSLEARDIGGAIN,
1371                         AB8500_HSLEARDIGGAIN_HSSINC1, enum_sinc31);
1372 
1373 static const char * const enum_fadespeed[] = {"1ms", "4ms", "8ms", "16ms"};
1374 static SOC_ENUM_SINGLE_DECL(soc_enum_fadespeed, AB8500_HSRDIGGAIN,
1375                         AB8500_HSRDIGGAIN_FADESPEED, enum_fadespeed);
1376 
1377 /* Earpiece */
1378 
1379 static const char * const enum_lowpow[] = {"Normal", "Low Power"};
1380 static SOC_ENUM_SINGLE_DECL(soc_enum_eardaclowpow, AB8500_ANACONF1,
1381                         AB8500_ANACONF1_EARDACLOWPOW, enum_lowpow);
1382 static SOC_ENUM_SINGLE_DECL(soc_enum_eardrvlowpow, AB8500_ANACONF1,
1383                         AB8500_ANACONF1_EARDRVLOWPOW, enum_lowpow);
1384 
1385 static const char * const enum_av_mode[] = {"Audio", "Voice"};
1386 static SOC_ENUM_DOUBLE_DECL(soc_enum_ad12voice, AB8500_ADFILTCONF,
1387         AB8500_ADFILTCONF_AD1VOICE, AB8500_ADFILTCONF_AD2VOICE, enum_av_mode);
1388 static SOC_ENUM_DOUBLE_DECL(soc_enum_ad34voice, AB8500_ADFILTCONF,
1389         AB8500_ADFILTCONF_AD3VOICE, AB8500_ADFILTCONF_AD4VOICE, enum_av_mode);
1390 
1391 /* DA */
1392 
1393 static SOC_ENUM_SINGLE_DECL(soc_enum_da12voice,
1394                         AB8500_DASLOTCONF1, AB8500_DASLOTCONF1_DA12VOICE,
1395                         enum_av_mode);
1396 static SOC_ENUM_SINGLE_DECL(soc_enum_da34voice,
1397                         AB8500_DASLOTCONF3, AB8500_DASLOTCONF3_DA34VOICE,
1398                         enum_av_mode);
1399 static SOC_ENUM_SINGLE_DECL(soc_enum_da56voice,
1400                         AB8500_DASLOTCONF5, AB8500_DASLOTCONF5_DA56VOICE,
1401                         enum_av_mode);
1402 
1403 static const char * const enum_da2hslr[] = {"Sidetone", "Audio Path"};
1404 static SOC_ENUM_DOUBLE_DECL(soc_enum_da2hslr, AB8500_DIGMULTCONF1,
1405                         AB8500_DIGMULTCONF1_DATOHSLEN,
1406                         AB8500_DIGMULTCONF1_DATOHSREN, enum_da2hslr);
1407 
1408 static const char * const enum_sinc53[] = {"Sinc 5", "Sinc 3"};
1409 static SOC_ENUM_DOUBLE_DECL(soc_enum_dmic12sinc, AB8500_DMICFILTCONF,
1410                         AB8500_DMICFILTCONF_DMIC1SINC3,
1411                         AB8500_DMICFILTCONF_DMIC2SINC3, enum_sinc53);
1412 static SOC_ENUM_DOUBLE_DECL(soc_enum_dmic34sinc, AB8500_DMICFILTCONF,
1413                         AB8500_DMICFILTCONF_DMIC3SINC3,
1414                         AB8500_DMICFILTCONF_DMIC4SINC3, enum_sinc53);
1415 static SOC_ENUM_DOUBLE_DECL(soc_enum_dmic56sinc, AB8500_DMICFILTCONF,
1416                         AB8500_DMICFILTCONF_DMIC5SINC3,
1417                         AB8500_DMICFILTCONF_DMIC6SINC3, enum_sinc53);
1418 
1419 /* Digital interface - DA from slot mapping */
1420 static const char * const enum_da_from_slot_map[] = {"SLOT0",
1421                                         "SLOT1",
1422                                         "SLOT2",
1423                                         "SLOT3",
1424                                         "SLOT4",
1425                                         "SLOT5",
1426                                         "SLOT6",
1427                                         "SLOT7",
1428                                         "SLOT8",
1429                                         "SLOT9",
1430                                         "SLOT10",
1431                                         "SLOT11",
1432                                         "SLOT12",
1433                                         "SLOT13",
1434                                         "SLOT14",
1435                                         "SLOT15",
1436                                         "SLOT16",
1437                                         "SLOT17",
1438                                         "SLOT18",
1439                                         "SLOT19",
1440                                         "SLOT20",
1441                                         "SLOT21",
1442                                         "SLOT22",
1443                                         "SLOT23",
1444                                         "SLOT24",
1445                                         "SLOT25",
1446                                         "SLOT26",
1447                                         "SLOT27",
1448                                         "SLOT28",
1449                                         "SLOT29",
1450                                         "SLOT30",
1451                                         "SLOT31"};
1452 static SOC_ENUM_SINGLE_DECL(soc_enum_da1slotmap,
1453                         AB8500_DASLOTCONF1, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1454                         enum_da_from_slot_map);
1455 static SOC_ENUM_SINGLE_DECL(soc_enum_da2slotmap,
1456                         AB8500_DASLOTCONF2, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1457                         enum_da_from_slot_map);
1458 static SOC_ENUM_SINGLE_DECL(soc_enum_da3slotmap,
1459                         AB8500_DASLOTCONF3, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1460                         enum_da_from_slot_map);
1461 static SOC_ENUM_SINGLE_DECL(soc_enum_da4slotmap,
1462                         AB8500_DASLOTCONF4, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1463                         enum_da_from_slot_map);
1464 static SOC_ENUM_SINGLE_DECL(soc_enum_da5slotmap,
1465                         AB8500_DASLOTCONF5, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1466                         enum_da_from_slot_map);
1467 static SOC_ENUM_SINGLE_DECL(soc_enum_da6slotmap,
1468                         AB8500_DASLOTCONF6, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1469                         enum_da_from_slot_map);
1470 static SOC_ENUM_SINGLE_DECL(soc_enum_da7slotmap,
1471                         AB8500_DASLOTCONF7, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1472                         enum_da_from_slot_map);
1473 static SOC_ENUM_SINGLE_DECL(soc_enum_da8slotmap,
1474                         AB8500_DASLOTCONF8, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1475                         enum_da_from_slot_map);
1476 
1477 /* Digital interface - AD to slot mapping */
1478 static const char * const enum_ad_to_slot_map[] = {"AD_OUT1",
1479                                         "AD_OUT2",
1480                                         "AD_OUT3",
1481                                         "AD_OUT4",
1482                                         "AD_OUT5",
1483                                         "AD_OUT6",
1484                                         "AD_OUT7",
1485                                         "AD_OUT8",
1486                                         "zeroes",
1487                                         "zeroes",
1488                                         "zeroes",
1489                                         "zeroes",
1490                                         "tristate",
1491                                         "tristate",
1492                                         "tristate",
1493                                         "tristate"};
1494 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot0map,
1495                         AB8500_ADSLOTSEL1, AB8500_ADSLOTSELX_EVEN_SHIFT,
1496                         enum_ad_to_slot_map);
1497 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot1map,
1498                         AB8500_ADSLOTSEL1, AB8500_ADSLOTSELX_ODD_SHIFT,
1499                         enum_ad_to_slot_map);
1500 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot2map,
1501                         AB8500_ADSLOTSEL2, AB8500_ADSLOTSELX_EVEN_SHIFT,
1502                         enum_ad_to_slot_map);
1503 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot3map,
1504                         AB8500_ADSLOTSEL2, AB8500_ADSLOTSELX_ODD_SHIFT,
1505                         enum_ad_to_slot_map);
1506 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot4map,
1507                         AB8500_ADSLOTSEL3, AB8500_ADSLOTSELX_EVEN_SHIFT,
1508                         enum_ad_to_slot_map);
1509 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot5map,
1510                         AB8500_ADSLOTSEL3, AB8500_ADSLOTSELX_ODD_SHIFT,
1511                         enum_ad_to_slot_map);
1512 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot6map,
1513                         AB8500_ADSLOTSEL4, AB8500_ADSLOTSELX_EVEN_SHIFT,
1514                         enum_ad_to_slot_map);
1515 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot7map,
1516                         AB8500_ADSLOTSEL4, AB8500_ADSLOTSELX_ODD_SHIFT,
1517                         enum_ad_to_slot_map);
1518 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot8map,
1519                         AB8500_ADSLOTSEL5, AB8500_ADSLOTSELX_EVEN_SHIFT,
1520                         enum_ad_to_slot_map);
1521 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot9map,
1522                         AB8500_ADSLOTSEL5, AB8500_ADSLOTSELX_ODD_SHIFT,
1523                         enum_ad_to_slot_map);
1524 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot10map,
1525                         AB8500_ADSLOTSEL6, AB8500_ADSLOTSELX_EVEN_SHIFT,
1526                         enum_ad_to_slot_map);
1527 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot11map,
1528                         AB8500_ADSLOTSEL6, AB8500_ADSLOTSELX_ODD_SHIFT,
1529                         enum_ad_to_slot_map);
1530 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot12map,
1531                         AB8500_ADSLOTSEL7, AB8500_ADSLOTSELX_EVEN_SHIFT,
1532                         enum_ad_to_slot_map);
1533 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot13map,
1534                         AB8500_ADSLOTSEL7, AB8500_ADSLOTSELX_ODD_SHIFT,
1535                         enum_ad_to_slot_map);
1536 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot14map,
1537                         AB8500_ADSLOTSEL8, AB8500_ADSLOTSELX_EVEN_SHIFT,
1538                         enum_ad_to_slot_map);
1539 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot15map,
1540                         AB8500_ADSLOTSEL8, AB8500_ADSLOTSELX_ODD_SHIFT,
1541                         enum_ad_to_slot_map);
1542 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot16map,
1543                         AB8500_ADSLOTSEL9, AB8500_ADSLOTSELX_EVEN_SHIFT,
1544                         enum_ad_to_slot_map);
1545 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot17map,
1546                         AB8500_ADSLOTSEL9, AB8500_ADSLOTSELX_ODD_SHIFT,
1547                         enum_ad_to_slot_map);
1548 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot18map,
1549                         AB8500_ADSLOTSEL10, AB8500_ADSLOTSELX_EVEN_SHIFT,
1550                         enum_ad_to_slot_map);
1551 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot19map,
1552                         AB8500_ADSLOTSEL10, AB8500_ADSLOTSELX_ODD_SHIFT,
1553                         enum_ad_to_slot_map);
1554 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot20map,
1555                         AB8500_ADSLOTSEL11, AB8500_ADSLOTSELX_EVEN_SHIFT,
1556                         enum_ad_to_slot_map);
1557 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot21map,
1558                         AB8500_ADSLOTSEL11, AB8500_ADSLOTSELX_ODD_SHIFT,
1559                         enum_ad_to_slot_map);
1560 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot22map,
1561                         AB8500_ADSLOTSEL12, AB8500_ADSLOTSELX_EVEN_SHIFT,
1562                         enum_ad_to_slot_map);
1563 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot23map,
1564                         AB8500_ADSLOTSEL12, AB8500_ADSLOTSELX_ODD_SHIFT,
1565                         enum_ad_to_slot_map);
1566 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot24map,
1567                         AB8500_ADSLOTSEL13, AB8500_ADSLOTSELX_EVEN_SHIFT,
1568                         enum_ad_to_slot_map);
1569 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot25map,
1570                         AB8500_ADSLOTSEL13, AB8500_ADSLOTSELX_ODD_SHIFT,
1571                         enum_ad_to_slot_map);
1572 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot26map,
1573                         AB8500_ADSLOTSEL14, AB8500_ADSLOTSELX_EVEN_SHIFT,
1574                         enum_ad_to_slot_map);
1575 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot27map,
1576                         AB8500_ADSLOTSEL14, AB8500_ADSLOTSELX_ODD_SHIFT,
1577                         enum_ad_to_slot_map);
1578 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot28map,
1579                         AB8500_ADSLOTSEL15, AB8500_ADSLOTSELX_EVEN_SHIFT,
1580                         enum_ad_to_slot_map);
1581 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot29map,
1582                         AB8500_ADSLOTSEL15, AB8500_ADSLOTSELX_ODD_SHIFT,
1583                         enum_ad_to_slot_map);
1584 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot30map,
1585                         AB8500_ADSLOTSEL16, AB8500_ADSLOTSELX_EVEN_SHIFT,
1586                         enum_ad_to_slot_map);
1587 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot31map,
1588                         AB8500_ADSLOTSEL16, AB8500_ADSLOTSELX_ODD_SHIFT,
1589                         enum_ad_to_slot_map);
1590 
1591 /* Digital interface - Burst mode */
1592 static const char * const enum_mask[] = {"Unmasked", "Masked"};
1593 static SOC_ENUM_SINGLE_DECL(soc_enum_bfifomask,
1594                         AB8500_FIFOCONF1, AB8500_FIFOCONF1_BFIFOMASK,
1595                         enum_mask);
1596 static const char * const enum_bitclk0[] = {"19_2_MHz", "38_4_MHz"};
1597 static SOC_ENUM_SINGLE_DECL(soc_enum_bfifo19m2,
1598                         AB8500_FIFOCONF1, AB8500_FIFOCONF1_BFIFO19M2,
1599                         enum_bitclk0);
1600 static const char * const enum_slavemaster[] = {"Slave", "Master"};
1601 static SOC_ENUM_SINGLE_DECL(soc_enum_bfifomast,
1602                         AB8500_FIFOCONF3, AB8500_FIFOCONF3_BFIFOMAST_SHIFT,
1603                         enum_slavemaster);
1604 
1605 /* Sidetone */
1606 static SOC_ENUM_SINGLE_EXT_DECL(soc_enum_sidstate, enum_sid_state);
1607 
1608 /* ANC */
1609 static SOC_ENUM_SINGLE_EXT_DECL(soc_enum_ancstate, enum_anc_state);
1610 
1611 static struct snd_kcontrol_new ab8500_ctrls[] = {
1612         /* Charge pump */
1613         SOC_ENUM("Charge Pump High Threshold For Low Voltage",
1614                 soc_enum_envdeththre),
1615         SOC_ENUM("Charge Pump Low Threshold For Low Voltage",
1616                 soc_enum_envdetlthre),
1617         SOC_SINGLE("Charge Pump Envelope Detection Switch",
1618                 AB8500_SIGENVCONF, AB8500_SIGENVCONF_ENVDETCPEN,
1619                 1, 0),
1620         SOC_ENUM("Charge Pump Envelope Detection Decay Time",
1621                 soc_enum_envdettime),
1622 
1623         /* Headset */
1624         SOC_ENUM("Headset Mode", soc_enum_da12voice),
1625         SOC_SINGLE("Headset High Pass Switch",
1626                 AB8500_ANACONF1, AB8500_ANACONF1_HSHPEN,
1627                 1, 0),
1628         SOC_SINGLE("Headset Low Power Switch",
1629                 AB8500_ANACONF1, AB8500_ANACONF1_HSLOWPOW,
1630                 1, 0),
1631         SOC_SINGLE("Headset DAC Low Power Switch",
1632                 AB8500_ANACONF1, AB8500_ANACONF1_DACLOWPOW1,
1633                 1, 0),
1634         SOC_SINGLE("Headset DAC Drv Low Power Switch",
1635                 AB8500_ANACONF1, AB8500_ANACONF1_DACLOWPOW0,
1636                 1, 0),
1637         SOC_ENUM("Headset Fade Speed", soc_enum_hsfadspeed),
1638         SOC_ENUM("Headset Source", soc_enum_da2hslr),
1639         SOC_ENUM("Headset Filter", soc_enum_hsesinc),
1640         SOC_DOUBLE_R_TLV("Headset Master Volume",
1641                 AB8500_DADIGGAIN1, AB8500_DADIGGAIN2,
1642                 0, AB8500_DADIGGAINX_DAXGAIN_MAX, 1, dax_dig_gain_tlv),
1643         SOC_DOUBLE_R_TLV("Headset Digital Volume",
1644                 AB8500_HSLEARDIGGAIN, AB8500_HSRDIGGAIN,
1645                 0, AB8500_HSLEARDIGGAIN_HSLDGAIN_MAX, 1, hs_ear_dig_gain_tlv),
1646         SOC_DOUBLE_TLV("Headset Volume",
1647                 AB8500_ANAGAIN3,
1648                 AB8500_ANAGAIN3_HSLGAIN, AB8500_ANAGAIN3_HSRGAIN,
1649                 AB8500_ANAGAIN3_HSXGAIN_MAX, 1, hs_gain_tlv),
1650 
1651         /* Earpiece */
1652         SOC_ENUM("Earpiece DAC Mode",
1653                 soc_enum_eardaclowpow),
1654         SOC_ENUM("Earpiece DAC Drv Mode",
1655                 soc_enum_eardrvlowpow),
1656 
1657         /* HandsFree */
1658         SOC_ENUM("HF Mode", soc_enum_da34voice),
1659         SOC_SINGLE("HF and Headset Swap Switch",
1660                 AB8500_DASLOTCONF1, AB8500_DASLOTCONF1_SWAPDA12_34,
1661                 1, 0),
1662         SOC_DOUBLE("HF Low EMI Mode Switch",
1663                 AB8500_CLASSDCONF1,
1664                 AB8500_CLASSDCONF1_HFLSWAPEN, AB8500_CLASSDCONF1_HFRSWAPEN,
1665                 1, 0),
1666         SOC_DOUBLE("HF FIR Bypass Switch",
1667                 AB8500_CLASSDCONF2,
1668                 AB8500_CLASSDCONF2_FIRBYP0, AB8500_CLASSDCONF2_FIRBYP1,
1669                 1, 0),
1670         SOC_DOUBLE("HF High Volume Switch",
1671                 AB8500_CLASSDCONF2,
1672                 AB8500_CLASSDCONF2_HIGHVOLEN0, AB8500_CLASSDCONF2_HIGHVOLEN1,
1673                 1, 0),
1674         SOC_SINGLE("HF L and R Bridge Switch",
1675                 AB8500_CLASSDCONF1, AB8500_CLASSDCONF1_PARLHF,
1676                 1, 0),
1677         SOC_DOUBLE_R_TLV("HF Master Volume",
1678                 AB8500_DADIGGAIN3, AB8500_DADIGGAIN4,
1679                 0, AB8500_DADIGGAINX_DAXGAIN_MAX, 1, dax_dig_gain_tlv),
1680 
1681         /* Vibra */
1682         SOC_DOUBLE("Vibra High Volume Switch",
1683                 AB8500_CLASSDCONF2,
1684                 AB8500_CLASSDCONF2_HIGHVOLEN2, AB8500_CLASSDCONF2_HIGHVOLEN3,
1685                 1, 0),
1686         SOC_DOUBLE("Vibra Low EMI Mode Switch",
1687                 AB8500_CLASSDCONF1,
1688                 AB8500_CLASSDCONF1_VIB1SWAPEN, AB8500_CLASSDCONF1_VIB2SWAPEN,
1689                 1, 0),
1690         SOC_DOUBLE("Vibra FIR Bypass Switch",
1691                 AB8500_CLASSDCONF2,
1692                 AB8500_CLASSDCONF2_FIRBYP2, AB8500_CLASSDCONF2_FIRBYP3,
1693                 1, 0),
1694         SOC_ENUM("Vibra Mode", soc_enum_da56voice),
1695         SOC_DOUBLE_R("Vibra PWM Duty Cycle N",
1696                 AB8500_PWMGENCONF3, AB8500_PWMGENCONF5,
1697                 AB8500_PWMGENCONFX_PWMVIBXDUTCYC,
1698                 AB8500_PWMGENCONFX_PWMVIBXDUTCYC_MAX, 0),
1699         SOC_DOUBLE_R("Vibra PWM Duty Cycle P",
1700                 AB8500_PWMGENCONF2, AB8500_PWMGENCONF4,
1701                 AB8500_PWMGENCONFX_PWMVIBXDUTCYC,
1702                 AB8500_PWMGENCONFX_PWMVIBXDUTCYC_MAX, 0),
1703         SOC_SINGLE("Vibra 1 and 2 Bridge Switch",
1704                 AB8500_CLASSDCONF1, AB8500_CLASSDCONF1_PARLVIB,
1705                 1, 0),
1706         SOC_DOUBLE_R_TLV("Vibra Master Volume",
1707                 AB8500_DADIGGAIN5, AB8500_DADIGGAIN6,
1708                 0, AB8500_DADIGGAINX_DAXGAIN_MAX, 1, dax_dig_gain_tlv),
1709 
1710         /* HandsFree, Vibra */
1711         SOC_SINGLE("ClassD High Pass Volume",
1712                 AB8500_CLASSDCONF3, AB8500_CLASSDCONF3_DITHHPGAIN,
1713                 AB8500_CLASSDCONF3_DITHHPGAIN_MAX, 0),
1714         SOC_SINGLE("ClassD White Volume",
1715                 AB8500_CLASSDCONF3, AB8500_CLASSDCONF3_DITHWGAIN,
1716                 AB8500_CLASSDCONF3_DITHWGAIN_MAX, 0),
1717 
1718         /* Mic 1, Mic 2, LineIn */
1719         SOC_DOUBLE_R_TLV("Mic Master Volume",
1720                 AB8500_ADDIGGAIN3, AB8500_ADDIGGAIN4,
1721                 0, AB8500_ADDIGGAINX_ADXGAIN_MAX, 1, adx_dig_gain_tlv),
1722 
1723         /* Mic 1 */
1724         SOC_SINGLE_TLV("Mic 1",
1725                 AB8500_ANAGAIN1,
1726                 AB8500_ANAGAINX_MICXGAIN,
1727                 AB8500_ANAGAINX_MICXGAIN_MAX, 0, mic_gain_tlv),
1728         SOC_SINGLE("Mic 1 Low Power Switch",
1729                 AB8500_ANAGAIN1, AB8500_ANAGAINX_LOWPOWMICX,
1730                 1, 0),
1731 
1732         /* Mic 2 */
1733         SOC_DOUBLE("Mic High Pass Switch",
1734                 AB8500_ADFILTCONF,
1735                 AB8500_ADFILTCONF_AD3NH, AB8500_ADFILTCONF_AD4NH,
1736                 1, 1),
1737         SOC_ENUM("Mic Mode", soc_enum_ad34voice),
1738         SOC_ENUM("Mic Filter", soc_enum_dmic34sinc),
1739         SOC_SINGLE_TLV("Mic 2",
1740                 AB8500_ANAGAIN2,
1741                 AB8500_ANAGAINX_MICXGAIN,
1742                 AB8500_ANAGAINX_MICXGAIN_MAX, 0, mic_gain_tlv),
1743         SOC_SINGLE("Mic 2 Low Power Switch",
1744                 AB8500_ANAGAIN2, AB8500_ANAGAINX_LOWPOWMICX,
1745                 1, 0),
1746 
1747         /* LineIn */
1748         SOC_DOUBLE("LineIn High Pass Switch",
1749                 AB8500_ADFILTCONF,
1750                 AB8500_ADFILTCONF_AD1NH, AB8500_ADFILTCONF_AD2NH,
1751                 1, 1),
1752         SOC_ENUM("LineIn Filter", soc_enum_dmic12sinc),
1753         SOC_ENUM("LineIn Mode", soc_enum_ad12voice),
1754         SOC_DOUBLE_R_TLV("LineIn Master Volume",
1755                 AB8500_ADDIGGAIN1, AB8500_ADDIGGAIN2,
1756                 0, AB8500_ADDIGGAINX_ADXGAIN_MAX, 1, adx_dig_gain_tlv),
1757         SOC_DOUBLE_TLV("LineIn",
1758                 AB8500_ANAGAIN4,
1759                 AB8500_ANAGAIN4_LINLGAIN, AB8500_ANAGAIN4_LINRGAIN,
1760                 AB8500_ANAGAIN4_LINXGAIN_MAX, 0, lin_gain_tlv),
1761         SOC_DOUBLE_R_TLV("LineIn to Headset Volume",
1762                 AB8500_DIGLINHSLGAIN, AB8500_DIGLINHSRGAIN,
1763                 AB8500_DIGLINHSXGAIN_LINTOHSXGAIN,
1764                 AB8500_DIGLINHSXGAIN_LINTOHSXGAIN_MAX,
1765                 1, lin2hs_gain_tlv),
1766 
1767         /* DMic */
1768         SOC_ENUM("DMic Filter", soc_enum_dmic56sinc),
1769         SOC_DOUBLE_R_TLV("DMic Master Volume",
1770                 AB8500_ADDIGGAIN5, AB8500_ADDIGGAIN6,
1771                 0, AB8500_ADDIGGAINX_ADXGAIN_MAX, 1, adx_dig_gain_tlv),
1772 
1773         /* Digital gains */
1774         SOC_ENUM("Digital Gain Fade Speed", soc_enum_fadespeed),
1775 
1776         /* Analog loopback */
1777         SOC_DOUBLE_R_TLV("Analog Loopback Volume",
1778                 AB8500_ADDIGLOOPGAIN1, AB8500_ADDIGLOOPGAIN2,
1779                 0, AB8500_ADDIGLOOPGAINX_ADXLBGAIN_MAX, 1, dax_dig_gain_tlv),
1780 
1781         /* Digital interface - DA from slot mapping */
1782         SOC_ENUM("Digital Interface DA 1 From Slot Map", soc_enum_da1slotmap),
1783         SOC_ENUM("Digital Interface DA 2 From Slot Map", soc_enum_da2slotmap),
1784         SOC_ENUM("Digital Interface DA 3 From Slot Map", soc_enum_da3slotmap),
1785         SOC_ENUM("Digital Interface DA 4 From Slot Map", soc_enum_da4slotmap),
1786         SOC_ENUM("Digital Interface DA 5 From Slot Map", soc_enum_da5slotmap),
1787         SOC_ENUM("Digital Interface DA 6 From Slot Map", soc_enum_da6slotmap),
1788         SOC_ENUM("Digital Interface DA 7 From Slot Map", soc_enum_da7slotmap),
1789         SOC_ENUM("Digital Interface DA 8 From Slot Map", soc_enum_da8slotmap),
1790 
1791         /* Digital interface - AD to slot mapping */
1792         SOC_ENUM("Digital Interface AD To Slot 0 Map", soc_enum_adslot0map),
1793         SOC_ENUM("Digital Interface AD To Slot 1 Map", soc_enum_adslot1map),
1794         SOC_ENUM("Digital Interface AD To Slot 2 Map", soc_enum_adslot2map),
1795         SOC_ENUM("Digital Interface AD To Slot 3 Map", soc_enum_adslot3map),
1796         SOC_ENUM("Digital Interface AD To Slot 4 Map", soc_enum_adslot4map),
1797         SOC_ENUM("Digital Interface AD To Slot 5 Map", soc_enum_adslot5map),
1798         SOC_ENUM("Digital Interface AD To Slot 6 Map", soc_enum_adslot6map),
1799         SOC_ENUM("Digital Interface AD To Slot 7 Map", soc_enum_adslot7map),
1800         SOC_ENUM("Digital Interface AD To Slot 8 Map", soc_enum_adslot8map),
1801         SOC_ENUM("Digital Interface AD To Slot 9 Map", soc_enum_adslot9map),
1802         SOC_ENUM("Digital Interface AD To Slot 10 Map", soc_enum_adslot10map),
1803         SOC_ENUM("Digital Interface AD To Slot 11 Map", soc_enum_adslot11map),
1804         SOC_ENUM("Digital Interface AD To Slot 12 Map", soc_enum_adslot12map),
1805         SOC_ENUM("Digital Interface AD To Slot 13 Map", soc_enum_adslot13map),
1806         SOC_ENUM("Digital Interface AD To Slot 14 Map", soc_enum_adslot14map),
1807         SOC_ENUM("Digital Interface AD To Slot 15 Map", soc_enum_adslot15map),
1808         SOC_ENUM("Digital Interface AD To Slot 16 Map", soc_enum_adslot16map),
1809         SOC_ENUM("Digital Interface AD To Slot 17 Map", soc_enum_adslot17map),
1810         SOC_ENUM("Digital Interface AD To Slot 18 Map", soc_enum_adslot18map),
1811         SOC_ENUM("Digital Interface AD To Slot 19 Map", soc_enum_adslot19map),
1812         SOC_ENUM("Digital Interface AD To Slot 20 Map", soc_enum_adslot20map),
1813         SOC_ENUM("Digital Interface AD To Slot 21 Map", soc_enum_adslot21map),
1814         SOC_ENUM("Digital Interface AD To Slot 22 Map", soc_enum_adslot22map),
1815         SOC_ENUM("Digital Interface AD To Slot 23 Map", soc_enum_adslot23map),
1816         SOC_ENUM("Digital Interface AD To Slot 24 Map", soc_enum_adslot24map),
1817         SOC_ENUM("Digital Interface AD To Slot 25 Map", soc_enum_adslot25map),
1818         SOC_ENUM("Digital Interface AD To Slot 26 Map", soc_enum_adslot26map),
1819         SOC_ENUM("Digital Interface AD To Slot 27 Map", soc_enum_adslot27map),
1820         SOC_ENUM("Digital Interface AD To Slot 28 Map", soc_enum_adslot28map),
1821         SOC_ENUM("Digital Interface AD To Slot 29 Map", soc_enum_adslot29map),
1822         SOC_ENUM("Digital Interface AD To Slot 30 Map", soc_enum_adslot30map),
1823         SOC_ENUM("Digital Interface AD To Slot 31 Map", soc_enum_adslot31map),
1824 
1825         /* Digital interface - Loopback */
1826         SOC_SINGLE("Digital Interface AD 1 Loopback Switch",
1827                 AB8500_DASLOTCONF1, AB8500_DASLOTCONF1_DAI7TOADO1,
1828                 1, 0),
1829         SOC_SINGLE("Digital Interface AD 2 Loopback Switch",
1830                 AB8500_DASLOTCONF2, AB8500_DASLOTCONF2_DAI8TOADO2,
1831                 1, 0),
1832         SOC_SINGLE("Digital Interface AD 3 Loopback Switch",
1833                 AB8500_DASLOTCONF3, AB8500_DASLOTCONF3_DAI7TOADO3,
1834                 1, 0),
1835         SOC_SINGLE("Digital Interface AD 4 Loopback Switch",
1836                 AB8500_DASLOTCONF4, AB8500_DASLOTCONF4_DAI8TOADO4,
1837                 1, 0),
1838         SOC_SINGLE("Digital Interface AD 5 Loopback Switch",
1839                 AB8500_DASLOTCONF5, AB8500_DASLOTCONF5_DAI7TOADO5,
1840                 1, 0),
1841         SOC_SINGLE("Digital Interface AD 6 Loopback Switch",
1842                 AB8500_DASLOTCONF6, AB8500_DASLOTCONF6_DAI8TOADO6,
1843                 1, 0),
1844         SOC_SINGLE("Digital Interface AD 7 Loopback Switch",
1845                 AB8500_DASLOTCONF7, AB8500_DASLOTCONF7_DAI8TOADO7,
1846                 1, 0),
1847         SOC_SINGLE("Digital Interface AD 8 Loopback Switch",
1848                 AB8500_DASLOTCONF8, AB8500_DASLOTCONF8_DAI7TOADO8,
1849                 1, 0),
1850 
1851         /* Digital interface - Burst FIFO */
1852         SOC_SINGLE("Digital Interface 0 FIFO Enable Switch",
1853                 AB8500_DIGIFCONF3, AB8500_DIGIFCONF3_IF0BFIFOEN,
1854                 1, 0),
1855         SOC_ENUM("Burst FIFO Mask", soc_enum_bfifomask),
1856         SOC_ENUM("Burst FIFO Bit-clock Frequency", soc_enum_bfifo19m2),
1857         SOC_SINGLE("Burst FIFO Threshold",
1858                 AB8500_FIFOCONF1, AB8500_FIFOCONF1_BFIFOINT_SHIFT,
1859                 AB8500_FIFOCONF1_BFIFOINT_MAX, 0),
1860         SOC_SINGLE("Burst FIFO Length",
1861                 AB8500_FIFOCONF2, AB8500_FIFOCONF2_BFIFOTX_SHIFT,
1862                 AB8500_FIFOCONF2_BFIFOTX_MAX, 0),
1863         SOC_SINGLE("Burst FIFO EOS Extra Slots",
1864                 AB8500_FIFOCONF3, AB8500_FIFOCONF3_BFIFOEXSL_SHIFT,
1865                 AB8500_FIFOCONF3_BFIFOEXSL_MAX, 0),
1866         SOC_SINGLE("Burst FIFO FS Extra Bit-clocks",
1867                 AB8500_FIFOCONF3, AB8500_FIFOCONF3_PREBITCLK0_SHIFT,
1868                 AB8500_FIFOCONF3_PREBITCLK0_MAX, 0),
1869         SOC_ENUM("Burst FIFO Interface Mode", soc_enum_bfifomast),
1870 
1871         SOC_SINGLE("Burst FIFO Interface Switch",
1872                 AB8500_FIFOCONF3, AB8500_FIFOCONF3_BFIFORUN_SHIFT,
1873                 1, 0),
1874         SOC_SINGLE("Burst FIFO Switch Frame Number",
1875                 AB8500_FIFOCONF4, AB8500_FIFOCONF4_BFIFOFRAMSW_SHIFT,
1876                 AB8500_FIFOCONF4_BFIFOFRAMSW_MAX, 0),
1877         SOC_SINGLE("Burst FIFO Wake Up Delay",
1878                 AB8500_FIFOCONF5, AB8500_FIFOCONF5_BFIFOWAKEUP_SHIFT,
1879                 AB8500_FIFOCONF5_BFIFOWAKEUP_MAX, 0),
1880         SOC_SINGLE("Burst FIFO Samples In FIFO",
1881                 AB8500_FIFOCONF6, AB8500_FIFOCONF6_BFIFOSAMPLE_SHIFT,
1882                 AB8500_FIFOCONF6_BFIFOSAMPLE_MAX, 0),
1883 
1884         /* ANC */
1885         SOC_ENUM_EXT("ANC Status", soc_enum_ancstate,
1886                 anc_status_control_get, anc_status_control_put),
1887         SOC_SINGLE_XR_SX("ANC Warp Delay Shift",
1888                 AB8500_ANCCONF2, 1, AB8500_ANCCONF2_SHIFT,
1889                 AB8500_ANCCONF2_MIN, AB8500_ANCCONF2_MAX, 0),
1890         SOC_SINGLE_XR_SX("ANC FIR Output Shift",
1891                 AB8500_ANCCONF3, 1, AB8500_ANCCONF3_SHIFT,
1892                 AB8500_ANCCONF3_MIN, AB8500_ANCCONF3_MAX, 0),
1893         SOC_SINGLE_XR_SX("ANC IIR Output Shift",
1894                 AB8500_ANCCONF4, 1, AB8500_ANCCONF4_SHIFT,
1895                 AB8500_ANCCONF4_MIN, AB8500_ANCCONF4_MAX, 0),
1896         SOC_SINGLE_XR_SX("ANC Warp Delay",
1897                 AB8500_ANCCONF9, 2, AB8500_ANC_WARP_DELAY_SHIFT,
1898                 AB8500_ANC_WARP_DELAY_MIN, AB8500_ANC_WARP_DELAY_MAX, 0),
1899 
1900         /* Sidetone */
1901         SOC_ENUM_EXT("Sidetone Status", soc_enum_sidstate,
1902                 sid_status_control_get, sid_status_control_put),
1903         SOC_SINGLE_STROBE("Sidetone Reset",
1904                 AB8500_SIDFIRADR, AB8500_SIDFIRADR_FIRSIDSET, 0),
1905 };
1906 
1907 static struct snd_kcontrol_new ab8500_filter_controls[] = {
1908         AB8500_FILTER_CONTROL("ANC FIR Coefficients", AB8500_ANC_FIR_COEFFS,
1909                 AB8500_ANC_FIR_COEFF_MIN, AB8500_ANC_FIR_COEFF_MAX),
1910         AB8500_FILTER_CONTROL("ANC IIR Coefficients", AB8500_ANC_IIR_COEFFS,
1911                 AB8500_ANC_IIR_COEFF_MIN, AB8500_ANC_IIR_COEFF_MAX),
1912         AB8500_FILTER_CONTROL("Sidetone FIR Coefficients",
1913                         AB8500_SID_FIR_COEFFS, AB8500_SID_FIR_COEFF_MIN,
1914                         AB8500_SID_FIR_COEFF_MAX)
1915 };
1916 enum ab8500_filter {
1917         AB8500_FILTER_ANC_FIR = 0,
1918         AB8500_FILTER_ANC_IIR = 1,
1919         AB8500_FILTER_SID_FIR = 2,
1920 };
1921 
1922 /*
1923  * Extended interface for codec-driver
1924  */
1925 
1926 static int ab8500_audio_init_audioblock(struct snd_soc_component *component)
1927 {
1928         int status;
1929 
1930         dev_dbg(component->dev, "%s: Enter.\n", __func__);
1931 
1932         /* Reset audio-registers and disable 32kHz-clock output 2 */
1933         status = ab8500_sysctrl_write(AB8500_STW4500CTRL3,
1934                                 AB8500_STW4500CTRL3_CLK32KOUT2DIS |
1935                                         AB8500_STW4500CTRL3_RESETAUDN,
1936                                 AB8500_STW4500CTRL3_RESETAUDN);
1937         if (status < 0)
1938                 return status;
1939 
1940         return 0;
1941 }
1942 
1943 static int ab8500_audio_setup_mics(struct snd_soc_component *component,
1944                         struct amic_settings *amics)
1945 {
1946         struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
1947         u8 value8;
1948         unsigned int value;
1949         int status;
1950         const struct snd_soc_dapm_route *route;
1951 
1952         dev_dbg(component->dev, "%s: Enter.\n", __func__);
1953 
1954         /* Set DMic-clocks to outputs */
1955         status = abx500_get_register_interruptible(component->dev, AB8500_MISC,
1956                                                 AB8500_GPIO_DIR4_REG,
1957                                                 &value8);
1958         if (status < 0)
1959                 return status;
1960         value = value8 | GPIO27_DIR_OUTPUT | GPIO29_DIR_OUTPUT |
1961                 GPIO31_DIR_OUTPUT;
1962         status = abx500_set_register_interruptible(component->dev,
1963                                                 AB8500_MISC,
1964                                                 AB8500_GPIO_DIR4_REG,
1965                                                 value);
1966         if (status < 0)
1967                 return status;
1968 
1969         /* Attach regulators to AMic DAPM-paths */
1970         dev_dbg(component->dev, "%s: Mic 1a regulator: %s\n", __func__,
1971                 amic_micbias_str(amics->mic1a_micbias));
1972         route = &ab8500_dapm_routes_mic1a_vamicx[amics->mic1a_micbias];
1973         status = snd_soc_dapm_add_routes(dapm, route, 1);
1974         dev_dbg(component->dev, "%s: Mic 1b regulator: %s\n", __func__,
1975                 amic_micbias_str(amics->mic1b_micbias));
1976         route = &ab8500_dapm_routes_mic1b_vamicx[amics->mic1b_micbias];
1977         status |= snd_soc_dapm_add_routes(dapm, route, 1);
1978         dev_dbg(component->dev, "%s: Mic 2 regulator: %s\n", __func__,
1979                 amic_micbias_str(amics->mic2_micbias));
1980         route = &ab8500_dapm_routes_mic2_vamicx[amics->mic2_micbias];
1981         status |= snd_soc_dapm_add_routes(dapm, route, 1);
1982         if (status < 0) {
1983                 dev_err(component->dev,
1984                         "%s: Failed to add AMic-regulator DAPM-routes (%d).\n",
1985                         __func__, status);
1986                 return status;
1987         }
1988 
1989         /* Set AMic-configuration */
1990         dev_dbg(component->dev, "%s: Mic 1 mic-type: %s\n", __func__,
1991                 amic_type_str(amics->mic1_type));
1992         snd_soc_component_update_bits(component, AB8500_ANAGAIN1, AB8500_ANAGAINX_ENSEMICX,
1993                         amics->mic1_type == AMIC_TYPE_DIFFERENTIAL ?
1994                                 0 : AB8500_ANAGAINX_ENSEMICX);
1995         dev_dbg(component->dev, "%s: Mic 2 mic-type: %s\n", __func__,
1996                 amic_type_str(amics->mic2_type));
1997         snd_soc_component_update_bits(component, AB8500_ANAGAIN2, AB8500_ANAGAINX_ENSEMICX,
1998                         amics->mic2_type == AMIC_TYPE_DIFFERENTIAL ?
1999                                 0 : AB8500_ANAGAINX_ENSEMICX);
2000 
2001         return 0;
2002 }
2003 
2004 static int ab8500_audio_set_ear_cmv(struct snd_soc_component *component,
2005                                 enum ear_cm_voltage ear_cmv)
2006 {
2007         char *cmv_str;
2008 
2009         switch (ear_cmv) {
2010         case EAR_CMV_0_95V:
2011                 cmv_str = "0.95V";
2012                 break;
2013         case EAR_CMV_1_10V:
2014                 cmv_str = "1.10V";
2015                 break;
2016         case EAR_CMV_1_27V:
2017                 cmv_str = "1.27V";
2018                 break;
2019         case EAR_CMV_1_58V:
2020                 cmv_str = "1.58V";
2021                 break;
2022         default:
2023                 dev_err(component->dev,
2024                         "%s: Unknown earpiece CM-voltage (%d)!\n",
2025                         __func__, (int)ear_cmv);
2026                 return -EINVAL;
2027         }
2028         dev_dbg(component->dev, "%s: Earpiece CM-voltage: %s\n", __func__,
2029                 cmv_str);
2030         snd_soc_component_update_bits(component, AB8500_ANACONF1, AB8500_ANACONF1_EARSELCM,
2031                         ear_cmv);
2032 
2033         return 0;
2034 }
2035 
2036 static int ab8500_audio_set_bit_delay(struct snd_soc_dai *dai,
2037                                 unsigned int delay)
2038 {
2039         unsigned int mask, val;
2040         struct snd_soc_component *component = dai->component;
2041 
2042         mask = BIT(AB8500_DIGIFCONF2_IF0DEL);
2043         val = 0;
2044 
2045         switch (delay) {
2046         case 0:
2047                 break;
2048         case 1:
2049                 val |= BIT(AB8500_DIGIFCONF2_IF0DEL);
2050                 break;
2051         default:
2052                 dev_err(dai->component->dev,
2053                         "%s: ERROR: Unsupported bit-delay (0x%x)!\n",
2054                         __func__, delay);
2055                 return -EINVAL;
2056         }
2057 
2058         dev_dbg(dai->component->dev, "%s: IF0 Bit-delay: %d bits.\n",
2059                 __func__, delay);
2060         snd_soc_component_update_bits(component, AB8500_DIGIFCONF2, mask, val);
2061 
2062         return 0;
2063 }
2064 
2065 /* Gates clocking according format mask */
2066 static int ab8500_codec_set_dai_clock_gate(struct snd_soc_component *component,
2067                                         unsigned int fmt)
2068 {
2069         unsigned int mask;
2070         unsigned int val;
2071 
2072         mask = BIT(AB8500_DIGIFCONF1_ENMASTGEN) |
2073                         BIT(AB8500_DIGIFCONF1_ENFSBITCLK0);
2074 
2075         val = BIT(AB8500_DIGIFCONF1_ENMASTGEN);
2076 
2077         switch (fmt & SND_SOC_DAIFMT_CLOCK_MASK) {
2078         case SND_SOC_DAIFMT_CONT: /* continuous clock */
2079                 dev_dbg(component->dev, "%s: IF0 Clock is continuous.\n",
2080                         __func__);
2081                 val |= BIT(AB8500_DIGIFCONF1_ENFSBITCLK0);
2082                 break;
2083         case SND_SOC_DAIFMT_GATED: /* clock is gated */
2084                 dev_dbg(component->dev, "%s: IF0 Clock is gated.\n",
2085                         __func__);
2086                 break;
2087         default:
2088                 dev_err(component->dev,
2089                         "%s: ERROR: Unsupported clock mask (0x%x)!\n",
2090                         __func__, fmt & SND_SOC_DAIFMT_CLOCK_MASK);
2091                 return -EINVAL;
2092         }
2093 
2094         snd_soc_component_update_bits(component, AB8500_DIGIFCONF1, mask, val);
2095 
2096         return 0;
2097 }
2098 
2099 static int ab8500_codec_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2100 {
2101         unsigned int mask;
2102         unsigned int val;
2103         struct snd_soc_component *component = dai->component;
2104         int status;
2105 
2106         dev_dbg(component->dev, "%s: Enter (fmt = 0x%x)\n", __func__, fmt);
2107 
2108         mask = BIT(AB8500_DIGIFCONF3_IF1DATOIF0AD) |
2109                         BIT(AB8500_DIGIFCONF3_IF1CLKTOIF0CLK) |
2110                         BIT(AB8500_DIGIFCONF3_IF0BFIFOEN) |
2111                         BIT(AB8500_DIGIFCONF3_IF0MASTER);
2112         val = 0;
2113 
2114         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2115         case SND_SOC_DAIFMT_CBM_CFM: /* codec clk & FRM master */
2116                 dev_dbg(dai->component->dev,
2117                         "%s: IF0 Master-mode: AB8500 master.\n", __func__);
2118                 val |= BIT(AB8500_DIGIFCONF3_IF0MASTER);
2119                 break;
2120         case SND_SOC_DAIFMT_CBS_CFS: /* codec clk & FRM slave */
2121                 dev_dbg(dai->component->dev,
2122                         "%s: IF0 Master-mode: AB8500 slave.\n", __func__);
2123                 break;
2124         case SND_SOC_DAIFMT_CBS_CFM: /* codec clk slave & FRM master */
2125         case SND_SOC_DAIFMT_CBM_CFS: /* codec clk master & frame slave */
2126                 dev_err(dai->component->dev,
2127                         "%s: ERROR: The device is either a master or a slave.\n",
2128                         __func__);
2129                 /* fall through */
2130         default:
2131                 dev_err(dai->component->dev,
2132                         "%s: ERROR: Unsupporter master mask 0x%x\n",
2133                         __func__, fmt & SND_SOC_DAIFMT_MASTER_MASK);
2134                 return -EINVAL;
2135         }
2136 
2137         snd_soc_component_update_bits(component, AB8500_DIGIFCONF3, mask, val);
2138 
2139         /* Set clock gating */
2140         status = ab8500_codec_set_dai_clock_gate(component, fmt);
2141         if (status) {
2142                 dev_err(dai->component->dev,
2143                         "%s: ERROR: Failed to set clock gate (%d).\n",
2144                         __func__, status);
2145                 return status;
2146         }
2147 
2148         /* Setting data transfer format */
2149 
2150         mask = BIT(AB8500_DIGIFCONF2_IF0FORMAT0) |
2151                 BIT(AB8500_DIGIFCONF2_IF0FORMAT1) |
2152                 BIT(AB8500_DIGIFCONF2_FSYNC0P) |
2153                 BIT(AB8500_DIGIFCONF2_BITCLK0P);
2154         val = 0;
2155 
2156         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2157         case SND_SOC_DAIFMT_I2S: /* I2S mode */
2158                 dev_dbg(dai->component->dev, "%s: IF0 Protocol: I2S\n", __func__);
2159                 val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT1);
2160                 ab8500_audio_set_bit_delay(dai, 0);
2161                 break;
2162 
2163         case SND_SOC_DAIFMT_DSP_A: /* L data MSB after FRM LRC */
2164                 dev_dbg(dai->component->dev,
2165                         "%s: IF0 Protocol: DSP A (TDM)\n", __func__);
2166                 val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT0);
2167                 ab8500_audio_set_bit_delay(dai, 1);
2168                 break;
2169 
2170         case SND_SOC_DAIFMT_DSP_B: /* L data MSB during FRM LRC */
2171                 dev_dbg(dai->component->dev,
2172                         "%s: IF0 Protocol: DSP B (TDM)\n", __func__);
2173                 val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT0);
2174                 ab8500_audio_set_bit_delay(dai, 0);
2175                 break;
2176 
2177         default:
2178                 dev_err(dai->component->dev,
2179                         "%s: ERROR: Unsupported format (0x%x)!\n",
2180                         __func__, fmt & SND_SOC_DAIFMT_FORMAT_MASK);
2181                 return -EINVAL;
2182         }
2183 
2184         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2185         case SND_SOC_DAIFMT_NB_NF: /* normal bit clock + frame */
2186                 dev_dbg(dai->component->dev,
2187                         "%s: IF0: Normal bit clock, normal frame\n",
2188                         __func__);
2189                 break;
2190         case SND_SOC_DAIFMT_NB_IF: /* normal BCLK + inv FRM */
2191                 dev_dbg(dai->component->dev,
2192                         "%s: IF0: Normal bit clock, inverted frame\n",
2193                         __func__);
2194                 val |= BIT(AB8500_DIGIFCONF2_FSYNC0P);
2195                 break;
2196         case SND_SOC_DAIFMT_IB_NF: /* invert BCLK + nor FRM */
2197                 dev_dbg(dai->component->dev,
2198                         "%s: IF0: Inverted bit clock, normal frame\n",
2199                         __func__);
2200                 val |= BIT(AB8500_DIGIFCONF2_BITCLK0P);
2201                 break;
2202         case SND_SOC_DAIFMT_IB_IF: /* invert BCLK + FRM */
2203                 dev_dbg(dai->component->dev,
2204                         "%s: IF0: Inverted bit clock, inverted frame\n",
2205                         __func__);
2206                 val |= BIT(AB8500_DIGIFCONF2_FSYNC0P);
2207                 val |= BIT(AB8500_DIGIFCONF2_BITCLK0P);
2208                 break;
2209         default:
2210                 dev_err(dai->component->dev,
2211                         "%s: ERROR: Unsupported INV mask 0x%x\n",
2212                         __func__, fmt & SND_SOC_DAIFMT_INV_MASK);
2213                 return -EINVAL;
2214         }
2215 
2216         snd_soc_component_update_bits(component, AB8500_DIGIFCONF2, mask, val);
2217 
2218         return 0;
2219 }
2220 
2221 static int ab8500_codec_set_dai_tdm_slot(struct snd_soc_dai *dai,
2222                 unsigned int tx_mask, unsigned int rx_mask,
2223                 int slots, int slot_width)
2224 {
2225         struct snd_soc_component *component = dai->component;
2226         unsigned int val, mask, slot, slots_active;
2227 
2228         mask = BIT(AB8500_DIGIFCONF2_IF0WL0) |
2229                 BIT(AB8500_DIGIFCONF2_IF0WL1);
2230         val = 0;
2231 
2232         switch (slot_width) {
2233         case 16:
2234                 break;
2235         case 20:
2236                 val |= BIT(AB8500_DIGIFCONF2_IF0WL0);
2237                 break;
2238         case 24:
2239                 val |= BIT(AB8500_DIGIFCONF2_IF0WL1);
2240                 break;
2241         case 32:
2242                 val |= BIT(AB8500_DIGIFCONF2_IF0WL1) |
2243                         BIT(AB8500_DIGIFCONF2_IF0WL0);
2244                 break;
2245         default:
2246                 dev_err(dai->component->dev, "%s: Unsupported slot-width 0x%x\n",
2247                         __func__, slot_width);
2248                 return -EINVAL;
2249         }
2250 
2251         dev_dbg(dai->component->dev, "%s: IF0 slot-width: %d bits.\n",
2252                 __func__, slot_width);
2253         snd_soc_component_update_bits(component, AB8500_DIGIFCONF2, mask, val);
2254 
2255         /* Setup TDM clocking according to slot count */
2256         dev_dbg(dai->component->dev, "%s: Slots, total: %d\n", __func__, slots);
2257         mask = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS0) |
2258                         BIT(AB8500_DIGIFCONF1_IF0BITCLKOS1);
2259         switch (slots) {
2260         case 2:
2261                 val = AB8500_MASK_NONE;
2262                 break;
2263         case 4:
2264                 val = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS0);
2265                 break;
2266         case 8:
2267                 val = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS1);
2268                 break;
2269         case 16:
2270                 val = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS0) |
2271                         BIT(AB8500_DIGIFCONF1_IF0BITCLKOS1);
2272                 break;
2273         default:
2274                 dev_err(dai->component->dev,
2275                         "%s: ERROR: Unsupported number of slots (%d)!\n",
2276                         __func__, slots);
2277                 return -EINVAL;
2278         }
2279         snd_soc_component_update_bits(component, AB8500_DIGIFCONF1, mask, val);
2280 
2281         /* Setup TDM DA according to active tx slots */
2282 
2283         if (tx_mask & ~0xff)
2284                 return -EINVAL;
2285 
2286         mask = AB8500_DASLOTCONFX_SLTODAX_MASK;
2287         tx_mask = tx_mask << AB8500_DA_DATA0_OFFSET;
2288         slots_active = hweight32(tx_mask);
2289 
2290         dev_dbg(dai->component->dev, "%s: Slots, active, TX: %d\n", __func__,
2291                 slots_active);
2292 
2293         switch (slots_active) {
2294         case 0:
2295                 break;
2296         case 1:
2297                 slot = ffs(tx_mask);
2298                 snd_soc_component_update_bits(component, AB8500_DASLOTCONF1, mask, slot);
2299                 snd_soc_component_update_bits(component, AB8500_DASLOTCONF3, mask, slot);
2300                 snd_soc_component_update_bits(component, AB8500_DASLOTCONF2, mask, slot);
2301                 snd_soc_component_update_bits(component, AB8500_DASLOTCONF4, mask, slot);
2302                 break;
2303         case 2:
2304                 slot = ffs(tx_mask);
2305                 snd_soc_component_update_bits(component, AB8500_DASLOTCONF1, mask, slot);
2306                 snd_soc_component_update_bits(component, AB8500_DASLOTCONF3, mask, slot);
2307                 slot = fls(tx_mask);
2308                 snd_soc_component_update_bits(component, AB8500_DASLOTCONF2, mask, slot);
2309                 snd_soc_component_update_bits(component, AB8500_DASLOTCONF4, mask, slot);
2310                 break;
2311         case 8:
2312                 dev_dbg(dai->component->dev,
2313                         "%s: In 8-channel mode DA-from-slot mapping is set manually.",
2314                         __func__);
2315                 break;
2316         default:
2317                 dev_err(dai->component->dev,
2318                         "%s: Unsupported number of active TX-slots (%d)!\n",
2319                         __func__, slots_active);
2320                 return -EINVAL;
2321         }
2322 
2323         /* Setup TDM AD according to active RX-slots */
2324 
2325         if (rx_mask & ~0xff)
2326                 return -EINVAL;
2327 
2328         rx_mask = rx_mask << AB8500_AD_DATA0_OFFSET;
2329         slots_active = hweight32(rx_mask);
2330 
2331         dev_dbg(dai->component->dev, "%s: Slots, active, RX: %d\n", __func__,
2332                 slots_active);
2333 
2334         switch (slots_active) {
2335         case 0:
2336                 break;
2337         case 1:
2338                 slot = ffs(rx_mask);
2339                 snd_soc_component_update_bits(component, AB8500_ADSLOTSEL(slot),
2340                                 AB8500_MASK_SLOT(slot),
2341                                 AB8500_ADSLOTSELX_AD_OUT_TO_SLOT(AB8500_AD_OUT3, slot));
2342                 break;
2343         case 2:
2344                 slot = ffs(rx_mask);
2345                 snd_soc_component_update_bits(component,
2346                                 AB8500_ADSLOTSEL(slot),
2347                                 AB8500_MASK_SLOT(slot),
2348                                 AB8500_ADSLOTSELX_AD_OUT_TO_SLOT(AB8500_AD_OUT3, slot));
2349                 slot = fls(rx_mask);
2350                 snd_soc_component_update_bits(component,
2351                                 AB8500_ADSLOTSEL(slot),
2352                                 AB8500_MASK_SLOT(slot),
2353                                 AB8500_ADSLOTSELX_AD_OUT_TO_SLOT(AB8500_AD_OUT2, slot));
2354                 break;
2355         case 8:
2356                 dev_dbg(dai->component->dev,
2357                         "%s: In 8-channel mode AD-to-slot mapping is set manually.",
2358                         __func__);
2359                 break;
2360         default:
2361                 dev_err(dai->component->dev,
2362                         "%s: Unsupported number of active RX-slots (%d)!\n",
2363                         __func__, slots_active);
2364                 return -EINVAL;
2365         }
2366 
2367         return 0;
2368 }
2369 
2370 static const struct snd_soc_dai_ops ab8500_codec_ops = {
2371         .set_fmt = ab8500_codec_set_dai_fmt,
2372         .set_tdm_slot = ab8500_codec_set_dai_tdm_slot,
2373 };
2374 
2375 static struct snd_soc_dai_driver ab8500_codec_dai[] = {
2376         {
2377                 .name = "ab8500-codec-dai.0",
2378                 .id = 0,
2379                 .playback = {
2380                         .stream_name = "ab8500_0p",
2381                         .channels_min = 1,
2382                         .channels_max = 8,
2383                         .rates = AB8500_SUPPORTED_RATE,
2384                         .formats = AB8500_SUPPORTED_FMT,
2385                 },
2386                 .ops = &ab8500_codec_ops,
2387                 .symmetric_rates = 1
2388         },
2389         {
2390                 .name = "ab8500-codec-dai.1",
2391                 .id = 1,
2392                 .capture = {
2393                         .stream_name = "ab8500_0c",
2394                         .channels_min = 1,
2395                         .channels_max = 8,
2396                         .rates = AB8500_SUPPORTED_RATE,
2397                         .formats = AB8500_SUPPORTED_FMT,
2398                 },
2399                 .ops = &ab8500_codec_ops,
2400                 .symmetric_rates = 1
2401         }
2402 };
2403 
2404 static void ab8500_codec_of_probe(struct device *dev, struct device_node *np,
2405                                 struct ab8500_codec_platform_data *codec)
2406 {
2407         u32 value;
2408 
2409         if (of_property_read_bool(np, "stericsson,amic1-type-single-ended"))
2410                 codec->amics.mic1_type = AMIC_TYPE_SINGLE_ENDED;
2411         else
2412                 codec->amics.mic1_type = AMIC_TYPE_DIFFERENTIAL;
2413 
2414         if (of_property_read_bool(np, "stericsson,amic2-type-single-ended"))
2415                 codec->amics.mic2_type = AMIC_TYPE_SINGLE_ENDED;
2416         else
2417                 codec->amics.mic2_type = AMIC_TYPE_DIFFERENTIAL;
2418 
2419         /* Has a non-standard Vamic been requested? */
2420         if (of_property_read_bool(np, "stericsson,amic1a-bias-vamic2"))
2421                 codec->amics.mic1a_micbias = AMIC_MICBIAS_VAMIC2;
2422         else
2423                 codec->amics.mic1a_micbias = AMIC_MICBIAS_VAMIC1;
2424 
2425         if (of_property_read_bool(np, "stericsson,amic1b-bias-vamic2"))
2426                 codec->amics.mic1b_micbias = AMIC_MICBIAS_VAMIC2;
2427         else
2428                 codec->amics.mic1b_micbias = AMIC_MICBIAS_VAMIC1;
2429 
2430         if (of_property_read_bool(np, "stericsson,amic2-bias-vamic1"))
2431                 codec->amics.mic2_micbias = AMIC_MICBIAS_VAMIC1;
2432         else
2433                 codec->amics.mic2_micbias = AMIC_MICBIAS_VAMIC2;
2434 
2435         if (!of_property_read_u32(np, "stericsson,earpeice-cmv", &value)) {
2436                 switch (value) {
2437                 case 950 :
2438                         codec->ear_cmv = EAR_CMV_0_95V;
2439                         break;
2440                 case 1100 :
2441                         codec->ear_cmv = EAR_CMV_1_10V;
2442                         break;
2443                 case 1270 :
2444                         codec->ear_cmv = EAR_CMV_1_27V;
2445                         break;
2446                 case 1580 :
2447                         codec->ear_cmv = EAR_CMV_1_58V;
2448                         break;
2449                 default :
2450                         codec->ear_cmv = EAR_CMV_UNKNOWN;
2451                         dev_err(dev, "Unsuitable earpiece voltage found in DT\n");
2452                 }
2453         } else {
2454                 dev_warn(dev, "No earpiece voltage found in DT - using default\n");
2455                 codec->ear_cmv = EAR_CMV_0_95V;
2456         }
2457 }
2458 
2459 static int ab8500_codec_probe(struct snd_soc_component *component)
2460 {
2461         struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
2462         struct device *dev = component->dev;
2463         struct device_node *np = dev->of_node;
2464         struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(dev);
2465         struct ab8500_codec_platform_data codec_pdata;
2466         struct filter_control *fc;
2467         int status;
2468 
2469         dev_dbg(dev, "%s: Enter.\n", __func__);
2470 
2471         ab8500_codec_of_probe(dev, np, &codec_pdata);
2472 
2473         status = ab8500_audio_setup_mics(component, &codec_pdata.amics);
2474         if (status < 0) {
2475                 pr_err("%s: Failed to setup mics (%d)!\n", __func__, status);
2476                 return status;
2477         }
2478         status = ab8500_audio_set_ear_cmv(component, codec_pdata.ear_cmv);
2479         if (status < 0) {
2480                 pr_err("%s: Failed to set earpiece CM-voltage (%d)!\n",
2481                         __func__, status);
2482                 return status;
2483         }
2484 
2485         status = ab8500_audio_init_audioblock(component);
2486         if (status < 0) {
2487                 dev_err(dev, "%s: failed to init audio-block (%d)!\n",
2488                         __func__, status);
2489                 return status;
2490         }
2491 
2492         /* Override HW-defaults */
2493         snd_soc_component_write(component, AB8500_ANACONF5,
2494                       BIT(AB8500_ANACONF5_HSAUTOEN));
2495         snd_soc_component_write(component, AB8500_SHORTCIRCONF,
2496                       BIT(AB8500_SHORTCIRCONF_HSZCDDIS));
2497 
2498         /* Add filter controls */
2499         status = snd_soc_add_component_controls(component, ab8500_filter_controls,
2500                                 ARRAY_SIZE(ab8500_filter_controls));
2501         if (status < 0) {
2502                 dev_err(dev,
2503                         "%s: failed to add ab8500 filter controls (%d).\n",
2504                         __func__, status);
2505                 return status;
2506         }
2507         fc = (struct filter_control *)
2508                 &ab8500_filter_controls[AB8500_FILTER_ANC_FIR].private_value;
2509         drvdata->anc_fir_values = (long *)fc->value;
2510         fc = (struct filter_control *)
2511                 &ab8500_filter_controls[AB8500_FILTER_ANC_IIR].private_value;
2512         drvdata->anc_iir_values = (long *)fc->value;
2513         fc = (struct filter_control *)
2514                 &ab8500_filter_controls[AB8500_FILTER_SID_FIR].private_value;
2515         drvdata->sid_fir_values = (long *)fc->value;
2516 
2517         snd_soc_dapm_disable_pin(dapm, "ANC Configure Input");
2518 
2519         mutex_init(&drvdata->ctrl_lock);
2520 
2521         return status;
2522 }
2523 
2524 static const struct snd_soc_component_driver ab8500_component_driver = {
2525         .probe                  = ab8500_codec_probe,
2526         .controls               = ab8500_ctrls,
2527         .num_controls           = ARRAY_SIZE(ab8500_ctrls),
2528         .dapm_widgets           = ab8500_dapm_widgets,
2529         .num_dapm_widgets       = ARRAY_SIZE(ab8500_dapm_widgets),
2530         .dapm_routes            = ab8500_dapm_routes,
2531         .num_dapm_routes        = ARRAY_SIZE(ab8500_dapm_routes),
2532         .idle_bias_on           = 1,
2533         .use_pmdown_time        = 1,
2534         .endianness             = 1,
2535         .non_legacy_dai_naming  = 1,
2536 };
2537 
2538 static int ab8500_codec_driver_probe(struct platform_device *pdev)
2539 {
2540         int status;
2541         struct ab8500_codec_drvdata *drvdata;
2542 
2543         dev_dbg(&pdev->dev, "%s: Enter.\n", __func__);
2544 
2545         /* Create driver private-data struct */
2546         drvdata = devm_kzalloc(&pdev->dev, sizeof(struct ab8500_codec_drvdata),
2547                         GFP_KERNEL);
2548         if (!drvdata)
2549                 return -ENOMEM;
2550         drvdata->sid_status = SID_UNCONFIGURED;
2551         drvdata->anc_status = ANC_UNCONFIGURED;
2552         dev_set_drvdata(&pdev->dev, drvdata);
2553 
2554         drvdata->regmap = devm_regmap_init(&pdev->dev, NULL, &pdev->dev,
2555                                            &ab8500_codec_regmap);
2556         if (IS_ERR(drvdata->regmap)) {
2557                 status = PTR_ERR(drvdata->regmap);
2558                 dev_err(&pdev->dev, "%s: Failed to allocate regmap: %d\n",
2559                         __func__, status);
2560                 return status;
2561         }
2562 
2563         dev_dbg(&pdev->dev, "%s: Register codec.\n", __func__);
2564         status = devm_snd_soc_register_component(&pdev->dev,
2565                                 &ab8500_component_driver,
2566                                 ab8500_codec_dai,
2567                                 ARRAY_SIZE(ab8500_codec_dai));
2568         if (status < 0)
2569                 dev_err(&pdev->dev,
2570                         "%s: Error: Failed to register codec (%d).\n",
2571                         __func__, status);
2572 
2573         return status;
2574 }
2575 
2576 static struct platform_driver ab8500_codec_platform_driver = {
2577         .driver = {
2578                 .name   = "ab8500-codec",
2579         },
2580         .probe          = ab8500_codec_driver_probe,
2581 };
2582 module_platform_driver(ab8500_codec_platform_driver);
2583 
2584 MODULE_LICENSE("GPL v2");
2585 

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