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TOMOYO Linux Cross Reference
Linux/sound/soc/codecs/adau1373.c

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  1 /*
  2  * Analog Devices ADAU1373 Audio Codec drive
  3  *
  4  * Copyright 2011 Analog Devices Inc.
  5  * Author: Lars-Peter Clausen <lars@metafoo.de>
  6  *
  7  * Licensed under the GPL-2 or later.
  8  */
  9 
 10 #include <linux/module.h>
 11 #include <linux/init.h>
 12 #include <linux/delay.h>
 13 #include <linux/pm.h>
 14 #include <linux/i2c.h>
 15 #include <linux/slab.h>
 16 #include <linux/gcd.h>
 17 
 18 #include <sound/core.h>
 19 #include <sound/pcm.h>
 20 #include <sound/pcm_params.h>
 21 #include <sound/tlv.h>
 22 #include <sound/soc.h>
 23 #include <sound/adau1373.h>
 24 
 25 #include "adau1373.h"
 26 
 27 struct adau1373_dai {
 28         unsigned int clk_src;
 29         unsigned int sysclk;
 30         bool enable_src;
 31         bool master;
 32 };
 33 
 34 struct adau1373 {
 35         struct regmap *regmap;
 36         struct adau1373_dai dais[3];
 37 };
 38 
 39 #define ADAU1373_INPUT_MODE     0x00
 40 #define ADAU1373_AINL_CTRL(x)   (0x01 + (x) * 2)
 41 #define ADAU1373_AINR_CTRL(x)   (0x02 + (x) * 2)
 42 #define ADAU1373_LLINE_OUT(x)   (0x9 + (x) * 2)
 43 #define ADAU1373_RLINE_OUT(x)   (0xa + (x) * 2)
 44 #define ADAU1373_LSPK_OUT       0x0d
 45 #define ADAU1373_RSPK_OUT       0x0e
 46 #define ADAU1373_LHP_OUT        0x0f
 47 #define ADAU1373_RHP_OUT        0x10
 48 #define ADAU1373_ADC_GAIN       0x11
 49 #define ADAU1373_LADC_MIXER     0x12
 50 #define ADAU1373_RADC_MIXER     0x13
 51 #define ADAU1373_LLINE1_MIX     0x14
 52 #define ADAU1373_RLINE1_MIX     0x15
 53 #define ADAU1373_LLINE2_MIX     0x16
 54 #define ADAU1373_RLINE2_MIX     0x17
 55 #define ADAU1373_LSPK_MIX       0x18
 56 #define ADAU1373_RSPK_MIX       0x19
 57 #define ADAU1373_LHP_MIX        0x1a
 58 #define ADAU1373_RHP_MIX        0x1b
 59 #define ADAU1373_EP_MIX         0x1c
 60 #define ADAU1373_HP_CTRL        0x1d
 61 #define ADAU1373_HP_CTRL2       0x1e
 62 #define ADAU1373_LS_CTRL        0x1f
 63 #define ADAU1373_EP_CTRL        0x21
 64 #define ADAU1373_MICBIAS_CTRL1  0x22
 65 #define ADAU1373_MICBIAS_CTRL2  0x23
 66 #define ADAU1373_OUTPUT_CTRL    0x24
 67 #define ADAU1373_PWDN_CTRL1     0x25
 68 #define ADAU1373_PWDN_CTRL2     0x26
 69 #define ADAU1373_PWDN_CTRL3     0x27
 70 #define ADAU1373_DPLL_CTRL(x)   (0x28 + (x) * 7)
 71 #define ADAU1373_PLL_CTRL1(x)   (0x29 + (x) * 7)
 72 #define ADAU1373_PLL_CTRL2(x)   (0x2a + (x) * 7)
 73 #define ADAU1373_PLL_CTRL3(x)   (0x2b + (x) * 7)
 74 #define ADAU1373_PLL_CTRL4(x)   (0x2c + (x) * 7)
 75 #define ADAU1373_PLL_CTRL5(x)   (0x2d + (x) * 7)
 76 #define ADAU1373_PLL_CTRL6(x)   (0x2e + (x) * 7)
 77 #define ADAU1373_HEADDECT       0x36
 78 #define ADAU1373_ADC_DAC_STATUS 0x37
 79 #define ADAU1373_ADC_CTRL       0x3c
 80 #define ADAU1373_DAI(x)         (0x44 + (x))
 81 #define ADAU1373_CLK_SRC_DIV(x) (0x40 + (x) * 2)
 82 #define ADAU1373_BCLKDIV(x)     (0x47 + (x))
 83 #define ADAU1373_SRC_RATIOA(x)  (0x4a + (x) * 2)
 84 #define ADAU1373_SRC_RATIOB(x)  (0x4b + (x) * 2)
 85 #define ADAU1373_DEEMP_CTRL     0x50
 86 #define ADAU1373_SRC_DAI_CTRL(x) (0x51 + (x))
 87 #define ADAU1373_DIN_MIX_CTRL(x) (0x56 + (x))
 88 #define ADAU1373_DOUT_MIX_CTRL(x) (0x5b + (x))
 89 #define ADAU1373_DAI_PBL_VOL(x) (0x62 + (x) * 2)
 90 #define ADAU1373_DAI_PBR_VOL(x) (0x63 + (x) * 2)
 91 #define ADAU1373_DAI_RECL_VOL(x) (0x68 + (x) * 2)
 92 #define ADAU1373_DAI_RECR_VOL(x) (0x69 + (x) * 2)
 93 #define ADAU1373_DAC1_PBL_VOL   0x6e
 94 #define ADAU1373_DAC1_PBR_VOL   0x6f
 95 #define ADAU1373_DAC2_PBL_VOL   0x70
 96 #define ADAU1373_DAC2_PBR_VOL   0x71
 97 #define ADAU1373_ADC_RECL_VOL   0x72
 98 #define ADAU1373_ADC_RECR_VOL   0x73
 99 #define ADAU1373_DMIC_RECL_VOL  0x74
100 #define ADAU1373_DMIC_RECR_VOL  0x75
101 #define ADAU1373_VOL_GAIN1      0x76
102 #define ADAU1373_VOL_GAIN2      0x77
103 #define ADAU1373_VOL_GAIN3      0x78
104 #define ADAU1373_HPF_CTRL       0x7d
105 #define ADAU1373_BASS1          0x7e
106 #define ADAU1373_BASS2          0x7f
107 #define ADAU1373_DRC(x)         (0x80 + (x) * 0x10)
108 #define ADAU1373_3D_CTRL1       0xc0
109 #define ADAU1373_3D_CTRL2       0xc1
110 #define ADAU1373_FDSP_SEL1      0xdc
111 #define ADAU1373_FDSP_SEL2      0xdd
112 #define ADAU1373_FDSP_SEL3      0xde
113 #define ADAU1373_FDSP_SEL4      0xdf
114 #define ADAU1373_DIGMICCTRL     0xe2
115 #define ADAU1373_DIGEN          0xeb
116 #define ADAU1373_SOFT_RESET     0xff
117 
118 
119 #define ADAU1373_PLL_CTRL6_DPLL_BYPASS  BIT(1)
120 #define ADAU1373_PLL_CTRL6_PLL_EN       BIT(0)
121 
122 #define ADAU1373_DAI_INVERT_BCLK        BIT(7)
123 #define ADAU1373_DAI_MASTER             BIT(6)
124 #define ADAU1373_DAI_INVERT_LRCLK       BIT(4)
125 #define ADAU1373_DAI_WLEN_16            0x0
126 #define ADAU1373_DAI_WLEN_20            0x4
127 #define ADAU1373_DAI_WLEN_24            0x8
128 #define ADAU1373_DAI_WLEN_32            0xc
129 #define ADAU1373_DAI_WLEN_MASK          0xc
130 #define ADAU1373_DAI_FORMAT_RIGHT_J     0x0
131 #define ADAU1373_DAI_FORMAT_LEFT_J      0x1
132 #define ADAU1373_DAI_FORMAT_I2S         0x2
133 #define ADAU1373_DAI_FORMAT_DSP         0x3
134 
135 #define ADAU1373_BCLKDIV_SOURCE         BIT(5)
136 #define ADAU1373_BCLKDIV_SR_MASK        (0x07 << 2)
137 #define ADAU1373_BCLKDIV_BCLK_MASK      0x03
138 #define ADAU1373_BCLKDIV_32             0x03
139 #define ADAU1373_BCLKDIV_64             0x02
140 #define ADAU1373_BCLKDIV_128            0x01
141 #define ADAU1373_BCLKDIV_256            0x00
142 
143 #define ADAU1373_ADC_CTRL_PEAK_DETECT   BIT(0)
144 #define ADAU1373_ADC_CTRL_RESET         BIT(1)
145 #define ADAU1373_ADC_CTRL_RESET_FORCE   BIT(2)
146 
147 #define ADAU1373_OUTPUT_CTRL_LDIFF      BIT(3)
148 #define ADAU1373_OUTPUT_CTRL_LNFBEN     BIT(2)
149 
150 #define ADAU1373_PWDN_CTRL3_PWR_EN BIT(0)
151 
152 #define ADAU1373_EP_CTRL_MICBIAS1_OFFSET 4
153 #define ADAU1373_EP_CTRL_MICBIAS2_OFFSET 2
154 
155 static const struct reg_default adau1373_reg_defaults[] = {
156         { ADAU1373_INPUT_MODE,          0x00 },
157         { ADAU1373_AINL_CTRL(0),        0x00 },
158         { ADAU1373_AINR_CTRL(0),        0x00 },
159         { ADAU1373_AINL_CTRL(1),        0x00 },
160         { ADAU1373_AINR_CTRL(1),        0x00 },
161         { ADAU1373_AINL_CTRL(2),        0x00 },
162         { ADAU1373_AINR_CTRL(2),        0x00 },
163         { ADAU1373_AINL_CTRL(3),        0x00 },
164         { ADAU1373_AINR_CTRL(3),        0x00 },
165         { ADAU1373_LLINE_OUT(0),        0x00 },
166         { ADAU1373_RLINE_OUT(0),        0x00 },
167         { ADAU1373_LLINE_OUT(1),        0x00 },
168         { ADAU1373_RLINE_OUT(1),        0x00 },
169         { ADAU1373_LSPK_OUT,            0x00 },
170         { ADAU1373_RSPK_OUT,            0x00 },
171         { ADAU1373_LHP_OUT,             0x00 },
172         { ADAU1373_RHP_OUT,             0x00 },
173         { ADAU1373_ADC_GAIN,            0x00 },
174         { ADAU1373_LADC_MIXER,          0x00 },
175         { ADAU1373_RADC_MIXER,          0x00 },
176         { ADAU1373_LLINE1_MIX,          0x00 },
177         { ADAU1373_RLINE1_MIX,          0x00 },
178         { ADAU1373_LLINE2_MIX,          0x00 },
179         { ADAU1373_RLINE2_MIX,          0x00 },
180         { ADAU1373_LSPK_MIX,            0x00 },
181         { ADAU1373_RSPK_MIX,            0x00 },
182         { ADAU1373_LHP_MIX,             0x00 },
183         { ADAU1373_RHP_MIX,             0x00 },
184         { ADAU1373_EP_MIX,              0x00 },
185         { ADAU1373_HP_CTRL,             0x00 },
186         { ADAU1373_HP_CTRL2,            0x00 },
187         { ADAU1373_LS_CTRL,             0x00 },
188         { ADAU1373_EP_CTRL,             0x00 },
189         { ADAU1373_MICBIAS_CTRL1,       0x00 },
190         { ADAU1373_MICBIAS_CTRL2,       0x00 },
191         { ADAU1373_OUTPUT_CTRL,         0x00 },
192         { ADAU1373_PWDN_CTRL1,          0x00 },
193         { ADAU1373_PWDN_CTRL2,          0x00 },
194         { ADAU1373_PWDN_CTRL3,          0x00 },
195         { ADAU1373_DPLL_CTRL(0),        0x00 },
196         { ADAU1373_PLL_CTRL1(0),        0x00 },
197         { ADAU1373_PLL_CTRL2(0),        0x00 },
198         { ADAU1373_PLL_CTRL3(0),        0x00 },
199         { ADAU1373_PLL_CTRL4(0),        0x00 },
200         { ADAU1373_PLL_CTRL5(0),        0x00 },
201         { ADAU1373_PLL_CTRL6(0),        0x02 },
202         { ADAU1373_DPLL_CTRL(1),        0x00 },
203         { ADAU1373_PLL_CTRL1(1),        0x00 },
204         { ADAU1373_PLL_CTRL2(1),        0x00 },
205         { ADAU1373_PLL_CTRL3(1),        0x00 },
206         { ADAU1373_PLL_CTRL4(1),        0x00 },
207         { ADAU1373_PLL_CTRL5(1),        0x00 },
208         { ADAU1373_PLL_CTRL6(1),        0x02 },
209         { ADAU1373_HEADDECT,            0x00 },
210         { ADAU1373_ADC_CTRL,            0x00 },
211         { ADAU1373_CLK_SRC_DIV(0),      0x00 },
212         { ADAU1373_CLK_SRC_DIV(1),      0x00 },
213         { ADAU1373_DAI(0),              0x0a },
214         { ADAU1373_DAI(1),              0x0a },
215         { ADAU1373_DAI(2),              0x0a },
216         { ADAU1373_BCLKDIV(0),          0x00 },
217         { ADAU1373_BCLKDIV(1),          0x00 },
218         { ADAU1373_BCLKDIV(2),          0x00 },
219         { ADAU1373_SRC_RATIOA(0),       0x00 },
220         { ADAU1373_SRC_RATIOB(0),       0x00 },
221         { ADAU1373_SRC_RATIOA(1),       0x00 },
222         { ADAU1373_SRC_RATIOB(1),       0x00 },
223         { ADAU1373_SRC_RATIOA(2),       0x00 },
224         { ADAU1373_SRC_RATIOB(2),       0x00 },
225         { ADAU1373_DEEMP_CTRL,          0x00 },
226         { ADAU1373_SRC_DAI_CTRL(0),     0x08 },
227         { ADAU1373_SRC_DAI_CTRL(1),     0x08 },
228         { ADAU1373_SRC_DAI_CTRL(2),     0x08 },
229         { ADAU1373_DIN_MIX_CTRL(0),     0x00 },
230         { ADAU1373_DIN_MIX_CTRL(1),     0x00 },
231         { ADAU1373_DIN_MIX_CTRL(2),     0x00 },
232         { ADAU1373_DIN_MIX_CTRL(3),     0x00 },
233         { ADAU1373_DIN_MIX_CTRL(4),     0x00 },
234         { ADAU1373_DOUT_MIX_CTRL(0),    0x00 },
235         { ADAU1373_DOUT_MIX_CTRL(1),    0x00 },
236         { ADAU1373_DOUT_MIX_CTRL(2),    0x00 },
237         { ADAU1373_DOUT_MIX_CTRL(3),    0x00 },
238         { ADAU1373_DOUT_MIX_CTRL(4),    0x00 },
239         { ADAU1373_DAI_PBL_VOL(0),      0x00 },
240         { ADAU1373_DAI_PBR_VOL(0),      0x00 },
241         { ADAU1373_DAI_PBL_VOL(1),      0x00 },
242         { ADAU1373_DAI_PBR_VOL(1),      0x00 },
243         { ADAU1373_DAI_PBL_VOL(2),      0x00 },
244         { ADAU1373_DAI_PBR_VOL(2),      0x00 },
245         { ADAU1373_DAI_RECL_VOL(0),     0x00 },
246         { ADAU1373_DAI_RECR_VOL(0),     0x00 },
247         { ADAU1373_DAI_RECL_VOL(1),     0x00 },
248         { ADAU1373_DAI_RECR_VOL(1),     0x00 },
249         { ADAU1373_DAI_RECL_VOL(2),     0x00 },
250         { ADAU1373_DAI_RECR_VOL(2),     0x00 },
251         { ADAU1373_DAC1_PBL_VOL,        0x00 },
252         { ADAU1373_DAC1_PBR_VOL,        0x00 },
253         { ADAU1373_DAC2_PBL_VOL,        0x00 },
254         { ADAU1373_DAC2_PBR_VOL,        0x00 },
255         { ADAU1373_ADC_RECL_VOL,        0x00 },
256         { ADAU1373_ADC_RECR_VOL,        0x00 },
257         { ADAU1373_DMIC_RECL_VOL,       0x00 },
258         { ADAU1373_DMIC_RECR_VOL,       0x00 },
259         { ADAU1373_VOL_GAIN1,           0x00 },
260         { ADAU1373_VOL_GAIN2,           0x00 },
261         { ADAU1373_VOL_GAIN3,           0x00 },
262         { ADAU1373_HPF_CTRL,            0x00 },
263         { ADAU1373_BASS1,               0x00 },
264         { ADAU1373_BASS2,               0x00 },
265         { ADAU1373_DRC(0) + 0x0,        0x78 },
266         { ADAU1373_DRC(0) + 0x1,        0x18 },
267         { ADAU1373_DRC(0) + 0x2,        0x00 },
268         { ADAU1373_DRC(0) + 0x3,        0x00 },
269         { ADAU1373_DRC(0) + 0x4,        0x00 },
270         { ADAU1373_DRC(0) + 0x5,        0xc0 },
271         { ADAU1373_DRC(0) + 0x6,        0x00 },
272         { ADAU1373_DRC(0) + 0x7,        0x00 },
273         { ADAU1373_DRC(0) + 0x8,        0x00 },
274         { ADAU1373_DRC(0) + 0x9,        0xc0 },
275         { ADAU1373_DRC(0) + 0xa,        0x88 },
276         { ADAU1373_DRC(0) + 0xb,        0x7a },
277         { ADAU1373_DRC(0) + 0xc,        0xdf },
278         { ADAU1373_DRC(0) + 0xd,        0x20 },
279         { ADAU1373_DRC(0) + 0xe,        0x00 },
280         { ADAU1373_DRC(0) + 0xf,        0x00 },
281         { ADAU1373_DRC(1) + 0x0,        0x78 },
282         { ADAU1373_DRC(1) + 0x1,        0x18 },
283         { ADAU1373_DRC(1) + 0x2,        0x00 },
284         { ADAU1373_DRC(1) + 0x3,        0x00 },
285         { ADAU1373_DRC(1) + 0x4,        0x00 },
286         { ADAU1373_DRC(1) + 0x5,        0xc0 },
287         { ADAU1373_DRC(1) + 0x6,        0x00 },
288         { ADAU1373_DRC(1) + 0x7,        0x00 },
289         { ADAU1373_DRC(1) + 0x8,        0x00 },
290         { ADAU1373_DRC(1) + 0x9,        0xc0 },
291         { ADAU1373_DRC(1) + 0xa,        0x88 },
292         { ADAU1373_DRC(1) + 0xb,        0x7a },
293         { ADAU1373_DRC(1) + 0xc,        0xdf },
294         { ADAU1373_DRC(1) + 0xd,        0x20 },
295         { ADAU1373_DRC(1) + 0xe,        0x00 },
296         { ADAU1373_DRC(1) + 0xf,        0x00 },
297         { ADAU1373_DRC(2) + 0x0,        0x78 },
298         { ADAU1373_DRC(2) + 0x1,        0x18 },
299         { ADAU1373_DRC(2) + 0x2,        0x00 },
300         { ADAU1373_DRC(2) + 0x3,        0x00 },
301         { ADAU1373_DRC(2) + 0x4,        0x00 },
302         { ADAU1373_DRC(2) + 0x5,        0xc0 },
303         { ADAU1373_DRC(2) + 0x6,        0x00 },
304         { ADAU1373_DRC(2) + 0x7,        0x00 },
305         { ADAU1373_DRC(2) + 0x8,        0x00 },
306         { ADAU1373_DRC(2) + 0x9,        0xc0 },
307         { ADAU1373_DRC(2) + 0xa,        0x88 },
308         { ADAU1373_DRC(2) + 0xb,        0x7a },
309         { ADAU1373_DRC(2) + 0xc,        0xdf },
310         { ADAU1373_DRC(2) + 0xd,        0x20 },
311         { ADAU1373_DRC(2) + 0xe,        0x00 },
312         { ADAU1373_DRC(2) + 0xf,        0x00 },
313         { ADAU1373_3D_CTRL1,            0x00 },
314         { ADAU1373_3D_CTRL2,            0x00 },
315         { ADAU1373_FDSP_SEL1,           0x00 },
316         { ADAU1373_FDSP_SEL2,           0x00 },
317         { ADAU1373_FDSP_SEL2,           0x00 },
318         { ADAU1373_FDSP_SEL4,           0x00 },
319         { ADAU1373_DIGMICCTRL,          0x00 },
320         { ADAU1373_DIGEN,               0x00 },
321 };
322 
323 static const unsigned int adau1373_out_tlv[] = {
324         TLV_DB_RANGE_HEAD(4),
325         0, 7, TLV_DB_SCALE_ITEM(-7900, 400, 1),
326         8, 15, TLV_DB_SCALE_ITEM(-4700, 300, 0),
327         16, 23, TLV_DB_SCALE_ITEM(-2300, 200, 0),
328         24, 31, TLV_DB_SCALE_ITEM(-700, 100, 0),
329 };
330 
331 static const DECLARE_TLV_DB_MINMAX(adau1373_digital_tlv, -9563, 0);
332 static const DECLARE_TLV_DB_SCALE(adau1373_in_pga_tlv, -1300, 100, 1);
333 static const DECLARE_TLV_DB_SCALE(adau1373_ep_tlv, -600, 600, 1);
334 
335 static const DECLARE_TLV_DB_SCALE(adau1373_input_boost_tlv, 0, 2000, 0);
336 static const DECLARE_TLV_DB_SCALE(adau1373_gain_boost_tlv, 0, 600, 0);
337 static const DECLARE_TLV_DB_SCALE(adau1373_speaker_boost_tlv, 1200, 600, 0);
338 
339 static const char *adau1373_fdsp_sel_text[] = {
340         "None",
341         "Channel 1",
342         "Channel 2",
343         "Channel 3",
344         "Channel 4",
345         "Channel 5",
346 };
347 
348 static SOC_ENUM_SINGLE_DECL(adau1373_drc1_channel_enum,
349         ADAU1373_FDSP_SEL1, 4, adau1373_fdsp_sel_text);
350 static SOC_ENUM_SINGLE_DECL(adau1373_drc2_channel_enum,
351         ADAU1373_FDSP_SEL1, 0, adau1373_fdsp_sel_text);
352 static SOC_ENUM_SINGLE_DECL(adau1373_drc3_channel_enum,
353         ADAU1373_FDSP_SEL2, 0, adau1373_fdsp_sel_text);
354 static SOC_ENUM_SINGLE_DECL(adau1373_hpf_channel_enum,
355         ADAU1373_FDSP_SEL3, 0, adau1373_fdsp_sel_text);
356 static SOC_ENUM_SINGLE_DECL(adau1373_bass_channel_enum,
357         ADAU1373_FDSP_SEL4, 4, adau1373_fdsp_sel_text);
358 
359 static const char *adau1373_hpf_cutoff_text[] = {
360         "3.7Hz", "50Hz", "100Hz", "150Hz", "200Hz", "250Hz", "300Hz", "350Hz",
361         "400Hz", "450Hz", "500Hz", "550Hz", "600Hz", "650Hz", "700Hz", "750Hz",
362         "800Hz",
363 };
364 
365 static SOC_ENUM_SINGLE_DECL(adau1373_hpf_cutoff_enum,
366         ADAU1373_HPF_CTRL, 3, adau1373_hpf_cutoff_text);
367 
368 static const char *adau1373_bass_lpf_cutoff_text[] = {
369         "801Hz", "1001Hz",
370 };
371 
372 static const char *adau1373_bass_clip_level_text[] = {
373         "0.125", "0.250", "0.370", "0.500", "0.625", "0.750", "0.875",
374 };
375 
376 static const unsigned int adau1373_bass_clip_level_values[] = {
377         1, 2, 3, 4, 5, 6, 7,
378 };
379 
380 static const char *adau1373_bass_hpf_cutoff_text[] = {
381         "158Hz", "232Hz", "347Hz", "520Hz",
382 };
383 
384 static const unsigned int adau1373_bass_tlv[] = {
385         TLV_DB_RANGE_HEAD(3),
386         0, 2, TLV_DB_SCALE_ITEM(-600, 600, 1),
387         3, 4, TLV_DB_SCALE_ITEM(950, 250, 0),
388         5, 7, TLV_DB_SCALE_ITEM(1400, 150, 0),
389 };
390 
391 static SOC_ENUM_SINGLE_DECL(adau1373_bass_lpf_cutoff_enum,
392         ADAU1373_BASS1, 5, adau1373_bass_lpf_cutoff_text);
393 
394 static SOC_VALUE_ENUM_SINGLE_DECL(adau1373_bass_clip_level_enum,
395         ADAU1373_BASS1, 2, 7, adau1373_bass_clip_level_text,
396         adau1373_bass_clip_level_values);
397 
398 static SOC_ENUM_SINGLE_DECL(adau1373_bass_hpf_cutoff_enum,
399         ADAU1373_BASS1, 0, adau1373_bass_hpf_cutoff_text);
400 
401 static const char *adau1373_3d_level_text[] = {
402         "0%", "6.67%", "13.33%", "20%", "26.67%", "33.33%",
403         "40%", "46.67%", "53.33%", "60%", "66.67%", "73.33%",
404         "80%", "86.67", "99.33%", "100%"
405 };
406 
407 static const char *adau1373_3d_cutoff_text[] = {
408         "No 3D", "0.03125 fs", "0.04583 fs", "0.075 fs", "0.11458 fs",
409         "0.16875 fs", "0.27083 fs"
410 };
411 
412 static SOC_ENUM_SINGLE_DECL(adau1373_3d_level_enum,
413         ADAU1373_3D_CTRL1, 4, adau1373_3d_level_text);
414 static SOC_ENUM_SINGLE_DECL(adau1373_3d_cutoff_enum,
415         ADAU1373_3D_CTRL1, 0, adau1373_3d_cutoff_text);
416 
417 static const unsigned int adau1373_3d_tlv[] = {
418         TLV_DB_RANGE_HEAD(2),
419         0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
420         1, 7, TLV_DB_LINEAR_ITEM(-1800, -120),
421 };
422 
423 static const char *adau1373_lr_mux_text[] = {
424         "Mute",
425         "Right Channel (L+R)",
426         "Left Channel (L+R)",
427         "Stereo",
428 };
429 
430 static SOC_ENUM_SINGLE_DECL(adau1373_lineout1_lr_mux_enum,
431         ADAU1373_OUTPUT_CTRL, 4, adau1373_lr_mux_text);
432 static SOC_ENUM_SINGLE_DECL(adau1373_lineout2_lr_mux_enum,
433         ADAU1373_OUTPUT_CTRL, 6, adau1373_lr_mux_text);
434 static SOC_ENUM_SINGLE_DECL(adau1373_speaker_lr_mux_enum,
435         ADAU1373_LS_CTRL, 4, adau1373_lr_mux_text);
436 
437 static const struct snd_kcontrol_new adau1373_controls[] = {
438         SOC_DOUBLE_R_TLV("AIF1 Capture Volume", ADAU1373_DAI_RECL_VOL(0),
439                 ADAU1373_DAI_RECR_VOL(0), 0, 0xff, 1, adau1373_digital_tlv),
440         SOC_DOUBLE_R_TLV("AIF2 Capture Volume", ADAU1373_DAI_RECL_VOL(1),
441                 ADAU1373_DAI_RECR_VOL(1), 0, 0xff, 1, adau1373_digital_tlv),
442         SOC_DOUBLE_R_TLV("AIF3 Capture Volume", ADAU1373_DAI_RECL_VOL(2),
443                 ADAU1373_DAI_RECR_VOL(2), 0, 0xff, 1, adau1373_digital_tlv),
444 
445         SOC_DOUBLE_R_TLV("ADC Capture Volume", ADAU1373_ADC_RECL_VOL,
446                 ADAU1373_ADC_RECR_VOL, 0, 0xff, 1, adau1373_digital_tlv),
447         SOC_DOUBLE_R_TLV("DMIC Capture Volume", ADAU1373_DMIC_RECL_VOL,
448                 ADAU1373_DMIC_RECR_VOL, 0, 0xff, 1, adau1373_digital_tlv),
449 
450         SOC_DOUBLE_R_TLV("AIF1 Playback Volume", ADAU1373_DAI_PBL_VOL(0),
451                 ADAU1373_DAI_PBR_VOL(0), 0, 0xff, 1, adau1373_digital_tlv),
452         SOC_DOUBLE_R_TLV("AIF2 Playback Volume", ADAU1373_DAI_PBL_VOL(1),
453                 ADAU1373_DAI_PBR_VOL(1), 0, 0xff, 1, adau1373_digital_tlv),
454         SOC_DOUBLE_R_TLV("AIF3 Playback Volume", ADAU1373_DAI_PBL_VOL(2),
455                 ADAU1373_DAI_PBR_VOL(2), 0, 0xff, 1, adau1373_digital_tlv),
456 
457         SOC_DOUBLE_R_TLV("DAC1 Playback Volume", ADAU1373_DAC1_PBL_VOL,
458                 ADAU1373_DAC1_PBR_VOL, 0, 0xff, 1, adau1373_digital_tlv),
459         SOC_DOUBLE_R_TLV("DAC2 Playback Volume", ADAU1373_DAC2_PBL_VOL,
460                 ADAU1373_DAC2_PBR_VOL, 0, 0xff, 1, adau1373_digital_tlv),
461 
462         SOC_DOUBLE_R_TLV("Lineout1 Playback Volume", ADAU1373_LLINE_OUT(0),
463                 ADAU1373_RLINE_OUT(0), 0, 0x1f, 0, adau1373_out_tlv),
464         SOC_DOUBLE_R_TLV("Speaker Playback Volume", ADAU1373_LSPK_OUT,
465                 ADAU1373_RSPK_OUT, 0, 0x1f, 0, adau1373_out_tlv),
466         SOC_DOUBLE_R_TLV("Headphone Playback Volume", ADAU1373_LHP_OUT,
467                 ADAU1373_RHP_OUT, 0, 0x1f, 0, adau1373_out_tlv),
468 
469         SOC_DOUBLE_R_TLV("Input 1 Capture Volume", ADAU1373_AINL_CTRL(0),
470                 ADAU1373_AINR_CTRL(0), 0, 0x1f, 0, adau1373_in_pga_tlv),
471         SOC_DOUBLE_R_TLV("Input 2 Capture Volume", ADAU1373_AINL_CTRL(1),
472                 ADAU1373_AINR_CTRL(1), 0, 0x1f, 0, adau1373_in_pga_tlv),
473         SOC_DOUBLE_R_TLV("Input 3 Capture Volume", ADAU1373_AINL_CTRL(2),
474                 ADAU1373_AINR_CTRL(2), 0, 0x1f, 0, adau1373_in_pga_tlv),
475         SOC_DOUBLE_R_TLV("Input 4 Capture Volume", ADAU1373_AINL_CTRL(3),
476                 ADAU1373_AINR_CTRL(3), 0, 0x1f, 0, adau1373_in_pga_tlv),
477 
478         SOC_SINGLE_TLV("Earpiece Playback Volume", ADAU1373_EP_CTRL, 0, 3, 0,
479                 adau1373_ep_tlv),
480 
481         SOC_DOUBLE_TLV("AIF3 Boost Playback Volume", ADAU1373_VOL_GAIN1, 4, 5,
482                 1, 0, adau1373_gain_boost_tlv),
483         SOC_DOUBLE_TLV("AIF2 Boost Playback Volume", ADAU1373_VOL_GAIN1, 2, 3,
484                 1, 0, adau1373_gain_boost_tlv),
485         SOC_DOUBLE_TLV("AIF1 Boost Playback Volume", ADAU1373_VOL_GAIN1, 0, 1,
486                 1, 0, adau1373_gain_boost_tlv),
487         SOC_DOUBLE_TLV("AIF3 Boost Capture Volume", ADAU1373_VOL_GAIN2, 4, 5,
488                 1, 0, adau1373_gain_boost_tlv),
489         SOC_DOUBLE_TLV("AIF2 Boost Capture Volume", ADAU1373_VOL_GAIN2, 2, 3,
490                 1, 0, adau1373_gain_boost_tlv),
491         SOC_DOUBLE_TLV("AIF1 Boost Capture Volume", ADAU1373_VOL_GAIN2, 0, 1,
492                 1, 0, adau1373_gain_boost_tlv),
493         SOC_DOUBLE_TLV("DMIC Boost Capture Volume", ADAU1373_VOL_GAIN3, 6, 7,
494                 1, 0, adau1373_gain_boost_tlv),
495         SOC_DOUBLE_TLV("ADC Boost Capture Volume", ADAU1373_VOL_GAIN3, 4, 5,
496                 1, 0, adau1373_gain_boost_tlv),
497         SOC_DOUBLE_TLV("DAC2 Boost Playback Volume", ADAU1373_VOL_GAIN3, 2, 3,
498                 1, 0, adau1373_gain_boost_tlv),
499         SOC_DOUBLE_TLV("DAC1 Boost Playback Volume", ADAU1373_VOL_GAIN3, 0, 1,
500                 1, 0, adau1373_gain_boost_tlv),
501 
502         SOC_DOUBLE_TLV("Input 1 Boost Capture Volume", ADAU1373_ADC_GAIN, 0, 4,
503                 1, 0, adau1373_input_boost_tlv),
504         SOC_DOUBLE_TLV("Input 2 Boost Capture Volume", ADAU1373_ADC_GAIN, 1, 5,
505                 1, 0, adau1373_input_boost_tlv),
506         SOC_DOUBLE_TLV("Input 3 Boost Capture Volume", ADAU1373_ADC_GAIN, 2, 6,
507                 1, 0, adau1373_input_boost_tlv),
508         SOC_DOUBLE_TLV("Input 4 Boost Capture Volume", ADAU1373_ADC_GAIN, 3, 7,
509                 1, 0, adau1373_input_boost_tlv),
510 
511         SOC_DOUBLE_TLV("Speaker Boost Playback Volume", ADAU1373_LS_CTRL, 2, 3,
512                 1, 0, adau1373_speaker_boost_tlv),
513 
514         SOC_ENUM("Lineout1 LR Mux", adau1373_lineout1_lr_mux_enum),
515         SOC_ENUM("Speaker LR Mux", adau1373_speaker_lr_mux_enum),
516 
517         SOC_ENUM("HPF Cutoff", adau1373_hpf_cutoff_enum),
518         SOC_DOUBLE("HPF Switch", ADAU1373_HPF_CTRL, 1, 0, 1, 0),
519         SOC_ENUM("HPF Channel", adau1373_hpf_channel_enum),
520 
521         SOC_ENUM("Bass HPF Cutoff", adau1373_bass_hpf_cutoff_enum),
522         SOC_VALUE_ENUM("Bass Clip Level Threshold",
523             adau1373_bass_clip_level_enum),
524         SOC_ENUM("Bass LPF Cutoff", adau1373_bass_lpf_cutoff_enum),
525         SOC_DOUBLE("Bass Playback Switch", ADAU1373_BASS2, 0, 1, 1, 0),
526         SOC_SINGLE_TLV("Bass Playback Volume", ADAU1373_BASS2, 2, 7, 0,
527             adau1373_bass_tlv),
528         SOC_ENUM("Bass Channel", adau1373_bass_channel_enum),
529 
530         SOC_ENUM("3D Freq", adau1373_3d_cutoff_enum),
531         SOC_ENUM("3D Level", adau1373_3d_level_enum),
532         SOC_SINGLE("3D Playback Switch", ADAU1373_3D_CTRL2, 0, 1, 0),
533         SOC_SINGLE_TLV("3D Playback Volume", ADAU1373_3D_CTRL2, 2, 7, 0,
534                 adau1373_3d_tlv),
535         SOC_ENUM("3D Channel", adau1373_bass_channel_enum),
536 
537         SOC_SINGLE("Zero Cross Switch", ADAU1373_PWDN_CTRL3, 7, 1, 0),
538 };
539 
540 static const struct snd_kcontrol_new adau1373_lineout2_controls[] = {
541         SOC_DOUBLE_R_TLV("Lineout2 Playback Volume", ADAU1373_LLINE_OUT(1),
542                 ADAU1373_RLINE_OUT(1), 0, 0x1f, 0, adau1373_out_tlv),
543         SOC_ENUM("Lineout2 LR Mux", adau1373_lineout2_lr_mux_enum),
544 };
545 
546 static const struct snd_kcontrol_new adau1373_drc_controls[] = {
547         SOC_ENUM("DRC1 Channel", adau1373_drc1_channel_enum),
548         SOC_ENUM("DRC2 Channel", adau1373_drc2_channel_enum),
549         SOC_ENUM("DRC3 Channel", adau1373_drc3_channel_enum),
550 };
551 
552 static int adau1373_pll_event(struct snd_soc_dapm_widget *w,
553         struct snd_kcontrol *kcontrol, int event)
554 {
555         struct snd_soc_codec *codec = w->codec;
556         struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(codec);
557         unsigned int pll_id = w->name[3] - '1';
558         unsigned int val;
559 
560         if (SND_SOC_DAPM_EVENT_ON(event))
561                 val = ADAU1373_PLL_CTRL6_PLL_EN;
562         else
563                 val = 0;
564 
565         regmap_update_bits(adau1373->regmap, ADAU1373_PLL_CTRL6(pll_id),
566                 ADAU1373_PLL_CTRL6_PLL_EN, val);
567 
568         if (SND_SOC_DAPM_EVENT_ON(event))
569                 mdelay(5);
570 
571         return 0;
572 }
573 
574 static const char *adau1373_decimator_text[] = {
575         "ADC",
576         "DMIC1",
577 };
578 
579 static SOC_ENUM_SINGLE_VIRT_DECL(adau1373_decimator_enum,
580         adau1373_decimator_text);
581 
582 static const struct snd_kcontrol_new adau1373_decimator_mux =
583         SOC_DAPM_ENUM_VIRT("Decimator Mux", adau1373_decimator_enum);
584 
585 static const struct snd_kcontrol_new adau1373_left_adc_mixer_controls[] = {
586         SOC_DAPM_SINGLE("DAC1 Switch", ADAU1373_LADC_MIXER, 4, 1, 0),
587         SOC_DAPM_SINGLE("Input 4 Switch", ADAU1373_LADC_MIXER, 3, 1, 0),
588         SOC_DAPM_SINGLE("Input 3 Switch", ADAU1373_LADC_MIXER, 2, 1, 0),
589         SOC_DAPM_SINGLE("Input 2 Switch", ADAU1373_LADC_MIXER, 1, 1, 0),
590         SOC_DAPM_SINGLE("Input 1 Switch", ADAU1373_LADC_MIXER, 0, 1, 0),
591 };
592 
593 static const struct snd_kcontrol_new adau1373_right_adc_mixer_controls[] = {
594         SOC_DAPM_SINGLE("DAC1 Switch", ADAU1373_RADC_MIXER, 4, 1, 0),
595         SOC_DAPM_SINGLE("Input 4 Switch", ADAU1373_RADC_MIXER, 3, 1, 0),
596         SOC_DAPM_SINGLE("Input 3 Switch", ADAU1373_RADC_MIXER, 2, 1, 0),
597         SOC_DAPM_SINGLE("Input 2 Switch", ADAU1373_RADC_MIXER, 1, 1, 0),
598         SOC_DAPM_SINGLE("Input 1 Switch", ADAU1373_RADC_MIXER, 0, 1, 0),
599 };
600 
601 #define DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(_name, _reg) \
602 const struct snd_kcontrol_new _name[] = { \
603         SOC_DAPM_SINGLE("Left DAC2 Switch", _reg, 7, 1, 0), \
604         SOC_DAPM_SINGLE("Right DAC2 Switch", _reg, 6, 1, 0), \
605         SOC_DAPM_SINGLE("Left DAC1 Switch", _reg, 5, 1, 0), \
606         SOC_DAPM_SINGLE("Right DAC1 Switch", _reg, 4, 1, 0), \
607         SOC_DAPM_SINGLE("Input 4 Bypass Switch", _reg, 3, 1, 0), \
608         SOC_DAPM_SINGLE("Input 3 Bypass Switch", _reg, 2, 1, 0), \
609         SOC_DAPM_SINGLE("Input 2 Bypass Switch", _reg, 1, 1, 0), \
610         SOC_DAPM_SINGLE("Input 1 Bypass Switch", _reg, 0, 1, 0), \
611 }
612 
613 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_left_line1_mixer_controls,
614         ADAU1373_LLINE1_MIX);
615 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_right_line1_mixer_controls,
616         ADAU1373_RLINE1_MIX);
617 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_left_line2_mixer_controls,
618         ADAU1373_LLINE2_MIX);
619 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_right_line2_mixer_controls,
620         ADAU1373_RLINE2_MIX);
621 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_left_spk_mixer_controls,
622         ADAU1373_LSPK_MIX);
623 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_right_spk_mixer_controls,
624         ADAU1373_RSPK_MIX);
625 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_ep_mixer_controls,
626         ADAU1373_EP_MIX);
627 
628 static const struct snd_kcontrol_new adau1373_left_hp_mixer_controls[] = {
629         SOC_DAPM_SINGLE("Left DAC1 Switch", ADAU1373_LHP_MIX, 5, 1, 0),
630         SOC_DAPM_SINGLE("Left DAC2 Switch", ADAU1373_LHP_MIX, 4, 1, 0),
631         SOC_DAPM_SINGLE("Input 4 Bypass Switch", ADAU1373_LHP_MIX, 3, 1, 0),
632         SOC_DAPM_SINGLE("Input 3 Bypass Switch", ADAU1373_LHP_MIX, 2, 1, 0),
633         SOC_DAPM_SINGLE("Input 2 Bypass Switch", ADAU1373_LHP_MIX, 1, 1, 0),
634         SOC_DAPM_SINGLE("Input 1 Bypass Switch", ADAU1373_LHP_MIX, 0, 1, 0),
635 };
636 
637 static const struct snd_kcontrol_new adau1373_right_hp_mixer_controls[] = {
638         SOC_DAPM_SINGLE("Right DAC1 Switch", ADAU1373_RHP_MIX, 5, 1, 0),
639         SOC_DAPM_SINGLE("Right DAC2 Switch", ADAU1373_RHP_MIX, 4, 1, 0),
640         SOC_DAPM_SINGLE("Input 4 Bypass Switch", ADAU1373_RHP_MIX, 3, 1, 0),
641         SOC_DAPM_SINGLE("Input 3 Bypass Switch", ADAU1373_RHP_MIX, 2, 1, 0),
642         SOC_DAPM_SINGLE("Input 2 Bypass Switch", ADAU1373_RHP_MIX, 1, 1, 0),
643         SOC_DAPM_SINGLE("Input 1 Bypass Switch", ADAU1373_RHP_MIX, 0, 1, 0),
644 };
645 
646 #define DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(_name, _reg) \
647 const struct snd_kcontrol_new _name[] = { \
648         SOC_DAPM_SINGLE("DMIC2 Swapped Switch", _reg, 6, 1, 0), \
649         SOC_DAPM_SINGLE("DMIC2 Switch", _reg, 5, 1, 0), \
650         SOC_DAPM_SINGLE("ADC/DMIC1 Swapped Switch", _reg, 4, 1, 0), \
651         SOC_DAPM_SINGLE("ADC/DMIC1 Switch", _reg, 3, 1, 0), \
652         SOC_DAPM_SINGLE("AIF3 Switch", _reg, 2, 1, 0), \
653         SOC_DAPM_SINGLE("AIF2 Switch", _reg, 1, 1, 0), \
654         SOC_DAPM_SINGLE("AIF1 Switch", _reg, 0, 1, 0), \
655 }
656 
657 static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel1_mixer_controls,
658         ADAU1373_DIN_MIX_CTRL(0));
659 static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel2_mixer_controls,
660         ADAU1373_DIN_MIX_CTRL(1));
661 static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel3_mixer_controls,
662         ADAU1373_DIN_MIX_CTRL(2));
663 static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel4_mixer_controls,
664         ADAU1373_DIN_MIX_CTRL(3));
665 static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel5_mixer_controls,
666         ADAU1373_DIN_MIX_CTRL(4));
667 
668 #define DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(_name, _reg) \
669 const struct snd_kcontrol_new _name[] = { \
670         SOC_DAPM_SINGLE("DSP Channel5 Switch", _reg, 4, 1, 0), \
671         SOC_DAPM_SINGLE("DSP Channel4 Switch", _reg, 3, 1, 0), \
672         SOC_DAPM_SINGLE("DSP Channel3 Switch", _reg, 2, 1, 0), \
673         SOC_DAPM_SINGLE("DSP Channel2 Switch", _reg, 1, 1, 0), \
674         SOC_DAPM_SINGLE("DSP Channel1 Switch", _reg, 0, 1, 0), \
675 }
676 
677 static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_aif1_mixer_controls,
678         ADAU1373_DOUT_MIX_CTRL(0));
679 static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_aif2_mixer_controls,
680         ADAU1373_DOUT_MIX_CTRL(1));
681 static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_aif3_mixer_controls,
682         ADAU1373_DOUT_MIX_CTRL(2));
683 static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_dac1_mixer_controls,
684         ADAU1373_DOUT_MIX_CTRL(3));
685 static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_dac2_mixer_controls,
686         ADAU1373_DOUT_MIX_CTRL(4));
687 
688 static const struct snd_soc_dapm_widget adau1373_dapm_widgets[] = {
689         /* Datasheet claims Left ADC is bit 6 and Right ADC is bit 7, but that
690          * doesn't seem to be the case. */
691         SND_SOC_DAPM_ADC("Left ADC", NULL, ADAU1373_PWDN_CTRL1, 7, 0),
692         SND_SOC_DAPM_ADC("Right ADC", NULL, ADAU1373_PWDN_CTRL1, 6, 0),
693 
694         SND_SOC_DAPM_ADC("DMIC1", NULL, ADAU1373_DIGMICCTRL, 0, 0),
695         SND_SOC_DAPM_ADC("DMIC2", NULL, ADAU1373_DIGMICCTRL, 2, 0),
696 
697         SND_SOC_DAPM_VIRT_MUX("Decimator Mux", SND_SOC_NOPM, 0, 0,
698                 &adau1373_decimator_mux),
699 
700         SND_SOC_DAPM_SUPPLY("MICBIAS2", ADAU1373_PWDN_CTRL1, 5, 0, NULL, 0),
701         SND_SOC_DAPM_SUPPLY("MICBIAS1", ADAU1373_PWDN_CTRL1, 4, 0, NULL, 0),
702 
703         SND_SOC_DAPM_PGA("IN4PGA", ADAU1373_PWDN_CTRL1, 3, 0, NULL, 0),
704         SND_SOC_DAPM_PGA("IN3PGA", ADAU1373_PWDN_CTRL1, 2, 0, NULL, 0),
705         SND_SOC_DAPM_PGA("IN2PGA", ADAU1373_PWDN_CTRL1, 1, 0, NULL, 0),
706         SND_SOC_DAPM_PGA("IN1PGA", ADAU1373_PWDN_CTRL1, 0, 0, NULL, 0),
707 
708         SND_SOC_DAPM_DAC("Left DAC2", NULL, ADAU1373_PWDN_CTRL2, 7, 0),
709         SND_SOC_DAPM_DAC("Right DAC2", NULL, ADAU1373_PWDN_CTRL2, 6, 0),
710         SND_SOC_DAPM_DAC("Left DAC1", NULL, ADAU1373_PWDN_CTRL2, 5, 0),
711         SND_SOC_DAPM_DAC("Right DAC1", NULL, ADAU1373_PWDN_CTRL2, 4, 0),
712 
713         SOC_MIXER_ARRAY("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
714                 adau1373_left_adc_mixer_controls),
715         SOC_MIXER_ARRAY("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
716                 adau1373_right_adc_mixer_controls),
717 
718         SOC_MIXER_ARRAY("Left Lineout2 Mixer", ADAU1373_PWDN_CTRL2, 3, 0,
719                 adau1373_left_line2_mixer_controls),
720         SOC_MIXER_ARRAY("Right Lineout2 Mixer", ADAU1373_PWDN_CTRL2, 2, 0,
721                 adau1373_right_line2_mixer_controls),
722         SOC_MIXER_ARRAY("Left Lineout1 Mixer", ADAU1373_PWDN_CTRL2, 1, 0,
723                 adau1373_left_line1_mixer_controls),
724         SOC_MIXER_ARRAY("Right Lineout1 Mixer", ADAU1373_PWDN_CTRL2, 0, 0,
725                 adau1373_right_line1_mixer_controls),
726 
727         SOC_MIXER_ARRAY("Earpiece Mixer", ADAU1373_PWDN_CTRL3, 4, 0,
728                 adau1373_ep_mixer_controls),
729         SOC_MIXER_ARRAY("Left Speaker Mixer", ADAU1373_PWDN_CTRL3, 3, 0,
730                 adau1373_left_spk_mixer_controls),
731         SOC_MIXER_ARRAY("Right Speaker Mixer", ADAU1373_PWDN_CTRL3, 2, 0,
732                 adau1373_right_spk_mixer_controls),
733         SOC_MIXER_ARRAY("Left Headphone Mixer", SND_SOC_NOPM, 0, 0,
734                 adau1373_left_hp_mixer_controls),
735         SOC_MIXER_ARRAY("Right Headphone Mixer", SND_SOC_NOPM, 0, 0,
736                 adau1373_right_hp_mixer_controls),
737         SND_SOC_DAPM_SUPPLY("Headphone Enable", ADAU1373_PWDN_CTRL3, 1, 0,
738                 NULL, 0),
739 
740         SND_SOC_DAPM_SUPPLY("AIF1 CLK", ADAU1373_SRC_DAI_CTRL(0), 0, 0,
741             NULL, 0),
742         SND_SOC_DAPM_SUPPLY("AIF2 CLK", ADAU1373_SRC_DAI_CTRL(1), 0, 0,
743             NULL, 0),
744         SND_SOC_DAPM_SUPPLY("AIF3 CLK", ADAU1373_SRC_DAI_CTRL(2), 0, 0,
745             NULL, 0),
746         SND_SOC_DAPM_SUPPLY("AIF1 IN SRC", ADAU1373_SRC_DAI_CTRL(0), 2, 0,
747             NULL, 0),
748         SND_SOC_DAPM_SUPPLY("AIF1 OUT SRC", ADAU1373_SRC_DAI_CTRL(0), 1, 0,
749             NULL, 0),
750         SND_SOC_DAPM_SUPPLY("AIF2 IN SRC", ADAU1373_SRC_DAI_CTRL(1), 2, 0,
751             NULL, 0),
752         SND_SOC_DAPM_SUPPLY("AIF2 OUT SRC", ADAU1373_SRC_DAI_CTRL(1), 1, 0,
753             NULL, 0),
754         SND_SOC_DAPM_SUPPLY("AIF3 IN SRC", ADAU1373_SRC_DAI_CTRL(2), 2, 0,
755             NULL, 0),
756         SND_SOC_DAPM_SUPPLY("AIF3 OUT SRC", ADAU1373_SRC_DAI_CTRL(2), 1, 0,
757             NULL, 0),
758 
759         SND_SOC_DAPM_AIF_IN("AIF1 IN", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
760         SND_SOC_DAPM_AIF_OUT("AIF1 OUT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
761         SND_SOC_DAPM_AIF_IN("AIF2 IN", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
762         SND_SOC_DAPM_AIF_OUT("AIF2 OUT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
763         SND_SOC_DAPM_AIF_IN("AIF3 IN", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
764         SND_SOC_DAPM_AIF_OUT("AIF3 OUT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
765 
766         SOC_MIXER_ARRAY("DSP Channel1 Mixer", SND_SOC_NOPM, 0, 0,
767                 adau1373_dsp_channel1_mixer_controls),
768         SOC_MIXER_ARRAY("DSP Channel2 Mixer", SND_SOC_NOPM, 0, 0,
769                 adau1373_dsp_channel2_mixer_controls),
770         SOC_MIXER_ARRAY("DSP Channel3 Mixer", SND_SOC_NOPM, 0, 0,
771                 adau1373_dsp_channel3_mixer_controls),
772         SOC_MIXER_ARRAY("DSP Channel4 Mixer", SND_SOC_NOPM, 0, 0,
773                 adau1373_dsp_channel4_mixer_controls),
774         SOC_MIXER_ARRAY("DSP Channel5 Mixer", SND_SOC_NOPM, 0, 0,
775                 adau1373_dsp_channel5_mixer_controls),
776 
777         SOC_MIXER_ARRAY("AIF1 Mixer", SND_SOC_NOPM, 0, 0,
778                 adau1373_aif1_mixer_controls),
779         SOC_MIXER_ARRAY("AIF2 Mixer", SND_SOC_NOPM, 0, 0,
780                 adau1373_aif2_mixer_controls),
781         SOC_MIXER_ARRAY("AIF3 Mixer", SND_SOC_NOPM, 0, 0,
782                 adau1373_aif3_mixer_controls),
783         SOC_MIXER_ARRAY("DAC1 Mixer", SND_SOC_NOPM, 0, 0,
784                 adau1373_dac1_mixer_controls),
785         SOC_MIXER_ARRAY("DAC2 Mixer", SND_SOC_NOPM, 0, 0,
786                 adau1373_dac2_mixer_controls),
787 
788         SND_SOC_DAPM_SUPPLY("DSP", ADAU1373_DIGEN, 4, 0, NULL, 0),
789         SND_SOC_DAPM_SUPPLY("Recording Engine B", ADAU1373_DIGEN, 3, 0, NULL, 0),
790         SND_SOC_DAPM_SUPPLY("Recording Engine A", ADAU1373_DIGEN, 2, 0, NULL, 0),
791         SND_SOC_DAPM_SUPPLY("Playback Engine B", ADAU1373_DIGEN, 1, 0, NULL, 0),
792         SND_SOC_DAPM_SUPPLY("Playback Engine A", ADAU1373_DIGEN, 0, 0, NULL, 0),
793 
794         SND_SOC_DAPM_SUPPLY("PLL1", SND_SOC_NOPM, 0, 0, adau1373_pll_event,
795                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
796         SND_SOC_DAPM_SUPPLY("PLL2", SND_SOC_NOPM, 0, 0, adau1373_pll_event,
797                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
798         SND_SOC_DAPM_SUPPLY("SYSCLK1", ADAU1373_CLK_SRC_DIV(0), 7, 0, NULL, 0),
799         SND_SOC_DAPM_SUPPLY("SYSCLK2", ADAU1373_CLK_SRC_DIV(1), 7, 0, NULL, 0),
800 
801         SND_SOC_DAPM_INPUT("AIN1L"),
802         SND_SOC_DAPM_INPUT("AIN1R"),
803         SND_SOC_DAPM_INPUT("AIN2L"),
804         SND_SOC_DAPM_INPUT("AIN2R"),
805         SND_SOC_DAPM_INPUT("AIN3L"),
806         SND_SOC_DAPM_INPUT("AIN3R"),
807         SND_SOC_DAPM_INPUT("AIN4L"),
808         SND_SOC_DAPM_INPUT("AIN4R"),
809 
810         SND_SOC_DAPM_INPUT("DMIC1DAT"),
811         SND_SOC_DAPM_INPUT("DMIC2DAT"),
812 
813         SND_SOC_DAPM_OUTPUT("LOUT1L"),
814         SND_SOC_DAPM_OUTPUT("LOUT1R"),
815         SND_SOC_DAPM_OUTPUT("LOUT2L"),
816         SND_SOC_DAPM_OUTPUT("LOUT2R"),
817         SND_SOC_DAPM_OUTPUT("HPL"),
818         SND_SOC_DAPM_OUTPUT("HPR"),
819         SND_SOC_DAPM_OUTPUT("SPKL"),
820         SND_SOC_DAPM_OUTPUT("SPKR"),
821         SND_SOC_DAPM_OUTPUT("EP"),
822 };
823 
824 static int adau1373_check_aif_clk(struct snd_soc_dapm_widget *source,
825         struct snd_soc_dapm_widget *sink)
826 {
827         struct snd_soc_codec *codec = source->codec;
828         struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(codec);
829         unsigned int dai;
830         const char *clk;
831 
832         dai = sink->name[3] - '1';
833 
834         if (!adau1373->dais[dai].master)
835                 return 0;
836 
837         if (adau1373->dais[dai].clk_src == ADAU1373_CLK_SRC_PLL1)
838                 clk = "SYSCLK1";
839         else
840                 clk = "SYSCLK2";
841 
842         return strcmp(source->name, clk) == 0;
843 }
844 
845 static int adau1373_check_src(struct snd_soc_dapm_widget *source,
846         struct snd_soc_dapm_widget *sink)
847 {
848         struct snd_soc_codec *codec = source->codec;
849         struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(codec);
850         unsigned int dai;
851 
852         dai = sink->name[3] - '1';
853 
854         return adau1373->dais[dai].enable_src;
855 }
856 
857 #define DSP_CHANNEL_MIXER_ROUTES(_sink) \
858         { _sink, "DMIC2 Swapped Switch", "DMIC2" }, \
859         { _sink, "DMIC2 Switch", "DMIC2" }, \
860         { _sink, "ADC/DMIC1 Swapped Switch", "Decimator Mux" }, \
861         { _sink, "ADC/DMIC1 Switch", "Decimator Mux" }, \
862         { _sink, "AIF1 Switch", "AIF1 IN" }, \
863         { _sink, "AIF2 Switch", "AIF2 IN" }, \
864         { _sink, "AIF3 Switch", "AIF3 IN" }
865 
866 #define DSP_OUTPUT_MIXER_ROUTES(_sink) \
867         { _sink, "DSP Channel1 Switch", "DSP Channel1 Mixer" }, \
868         { _sink, "DSP Channel2 Switch", "DSP Channel2 Mixer" }, \
869         { _sink, "DSP Channel3 Switch", "DSP Channel3 Mixer" }, \
870         { _sink, "DSP Channel4 Switch", "DSP Channel4 Mixer" }, \
871         { _sink, "DSP Channel5 Switch", "DSP Channel5 Mixer" }
872 
873 #define LEFT_OUTPUT_MIXER_ROUTES(_sink) \
874         { _sink, "Right DAC2 Switch", "Right DAC2" }, \
875         { _sink, "Left DAC2 Switch", "Left DAC2" }, \
876         { _sink, "Right DAC1 Switch", "Right DAC1" }, \
877         { _sink, "Left DAC1 Switch", "Left DAC1" }, \
878         { _sink, "Input 1 Bypass Switch", "IN1PGA" }, \
879         { _sink, "Input 2 Bypass Switch", "IN2PGA" }, \
880         { _sink, "Input 3 Bypass Switch", "IN3PGA" }, \
881         { _sink, "Input 4 Bypass Switch", "IN4PGA" }
882 
883 #define RIGHT_OUTPUT_MIXER_ROUTES(_sink) \
884         { _sink, "Right DAC2 Switch", "Right DAC2" }, \
885         { _sink, "Left DAC2 Switch", "Left DAC2" }, \
886         { _sink, "Right DAC1 Switch", "Right DAC1" }, \
887         { _sink, "Left DAC1 Switch", "Left DAC1" }, \
888         { _sink, "Input 1 Bypass Switch", "IN1PGA" }, \
889         { _sink, "Input 2 Bypass Switch", "IN2PGA" }, \
890         { _sink, "Input 3 Bypass Switch", "IN3PGA" }, \
891         { _sink, "Input 4 Bypass Switch", "IN4PGA" }
892 
893 static const struct snd_soc_dapm_route adau1373_dapm_routes[] = {
894         { "Left ADC Mixer", "DAC1 Switch", "Left DAC1" },
895         { "Left ADC Mixer", "Input 1 Switch", "IN1PGA" },
896         { "Left ADC Mixer", "Input 2 Switch", "IN2PGA" },
897         { "Left ADC Mixer", "Input 3 Switch", "IN3PGA" },
898         { "Left ADC Mixer", "Input 4 Switch", "IN4PGA" },
899 
900         { "Right ADC Mixer", "DAC1 Switch", "Right DAC1" },
901         { "Right ADC Mixer", "Input 1 Switch", "IN1PGA" },
902         { "Right ADC Mixer", "Input 2 Switch", "IN2PGA" },
903         { "Right ADC Mixer", "Input 3 Switch", "IN3PGA" },
904         { "Right ADC Mixer", "Input 4 Switch", "IN4PGA" },
905 
906         { "Left ADC", NULL, "Left ADC Mixer" },
907         { "Right ADC", NULL, "Right ADC Mixer" },
908 
909         { "Decimator Mux", "ADC", "Left ADC" },
910         { "Decimator Mux", "ADC", "Right ADC" },
911         { "Decimator Mux", "DMIC1", "DMIC1" },
912 
913         DSP_CHANNEL_MIXER_ROUTES("DSP Channel1 Mixer"),
914         DSP_CHANNEL_MIXER_ROUTES("DSP Channel2 Mixer"),
915         DSP_CHANNEL_MIXER_ROUTES("DSP Channel3 Mixer"),
916         DSP_CHANNEL_MIXER_ROUTES("DSP Channel4 Mixer"),
917         DSP_CHANNEL_MIXER_ROUTES("DSP Channel5 Mixer"),
918 
919         DSP_OUTPUT_MIXER_ROUTES("AIF1 Mixer"),
920         DSP_OUTPUT_MIXER_ROUTES("AIF2 Mixer"),
921         DSP_OUTPUT_MIXER_ROUTES("AIF3 Mixer"),
922         DSP_OUTPUT_MIXER_ROUTES("DAC1 Mixer"),
923         DSP_OUTPUT_MIXER_ROUTES("DAC2 Mixer"),
924 
925         { "AIF1 OUT", NULL, "AIF1 Mixer" },
926         { "AIF2 OUT", NULL, "AIF2 Mixer" },
927         { "AIF3 OUT", NULL, "AIF3 Mixer" },
928         { "Left DAC1", NULL, "DAC1 Mixer" },
929         { "Right DAC1", NULL, "DAC1 Mixer" },
930         { "Left DAC2", NULL, "DAC2 Mixer" },
931         { "Right DAC2", NULL, "DAC2 Mixer" },
932 
933         LEFT_OUTPUT_MIXER_ROUTES("Left Lineout1 Mixer"),
934         RIGHT_OUTPUT_MIXER_ROUTES("Right Lineout1 Mixer"),
935         LEFT_OUTPUT_MIXER_ROUTES("Left Lineout2 Mixer"),
936         RIGHT_OUTPUT_MIXER_ROUTES("Right Lineout2 Mixer"),
937         LEFT_OUTPUT_MIXER_ROUTES("Left Speaker Mixer"),
938         RIGHT_OUTPUT_MIXER_ROUTES("Right Speaker Mixer"),
939 
940         { "Left Headphone Mixer", "Left DAC2 Switch", "Left DAC2" },
941         { "Left Headphone Mixer", "Left DAC1 Switch", "Left DAC1" },
942         { "Left Headphone Mixer", "Input 1 Bypass Switch", "IN1PGA" },
943         { "Left Headphone Mixer", "Input 2 Bypass Switch", "IN2PGA" },
944         { "Left Headphone Mixer", "Input 3 Bypass Switch", "IN3PGA" },
945         { "Left Headphone Mixer", "Input 4 Bypass Switch", "IN4PGA" },
946         { "Right Headphone Mixer", "Right DAC2 Switch", "Right DAC2" },
947         { "Right Headphone Mixer", "Right DAC1 Switch", "Right DAC1" },
948         { "Right Headphone Mixer", "Input 1 Bypass Switch", "IN1PGA" },
949         { "Right Headphone Mixer", "Input 2 Bypass Switch", "IN2PGA" },
950         { "Right Headphone Mixer", "Input 3 Bypass Switch", "IN3PGA" },
951         { "Right Headphone Mixer", "Input 4 Bypass Switch", "IN4PGA" },
952 
953         { "Left Headphone Mixer", NULL, "Headphone Enable" },
954         { "Right Headphone Mixer", NULL, "Headphone Enable" },
955 
956         { "Earpiece Mixer", "Right DAC2 Switch", "Right DAC2" },
957         { "Earpiece Mixer", "Left DAC2 Switch", "Left DAC2" },
958         { "Earpiece Mixer", "Right DAC1 Switch", "Right DAC1" },
959         { "Earpiece Mixer", "Left DAC1 Switch", "Left DAC1" },
960         { "Earpiece Mixer", "Input 1 Bypass Switch", "IN1PGA" },
961         { "Earpiece Mixer", "Input 2 Bypass Switch", "IN2PGA" },
962         { "Earpiece Mixer", "Input 3 Bypass Switch", "IN3PGA" },
963         { "Earpiece Mixer", "Input 4 Bypass Switch", "IN4PGA" },
964 
965         { "LOUT1L", NULL, "Left Lineout1 Mixer" },
966         { "LOUT1R", NULL, "Right Lineout1 Mixer" },
967         { "LOUT2L", NULL, "Left Lineout2 Mixer" },
968         { "LOUT2R", NULL, "Right Lineout2 Mixer" },
969         { "SPKL", NULL, "Left Speaker Mixer" },
970         { "SPKR", NULL, "Right Speaker Mixer" },
971         { "HPL", NULL, "Left Headphone Mixer" },
972         { "HPR", NULL, "Right Headphone Mixer" },
973         { "EP", NULL, "Earpiece Mixer" },
974 
975         { "IN1PGA", NULL, "AIN1L" },
976         { "IN2PGA", NULL, "AIN2L" },
977         { "IN3PGA", NULL, "AIN3L" },
978         { "IN4PGA", NULL, "AIN4L" },
979         { "IN1PGA", NULL, "AIN1R" },
980         { "IN2PGA", NULL, "AIN2R" },
981         { "IN3PGA", NULL, "AIN3R" },
982         { "IN4PGA", NULL, "AIN4R" },
983 
984         { "SYSCLK1", NULL, "PLL1" },
985         { "SYSCLK2", NULL, "PLL2" },
986 
987         { "Left DAC1", NULL, "SYSCLK1" },
988         { "Right DAC1", NULL, "SYSCLK1" },
989         { "Left DAC2", NULL, "SYSCLK1" },
990         { "Right DAC2", NULL, "SYSCLK1" },
991         { "Left ADC", NULL, "SYSCLK1" },
992         { "Right ADC", NULL, "SYSCLK1" },
993 
994         { "DSP", NULL, "SYSCLK1" },
995 
996         { "AIF1 Mixer", NULL, "DSP" },
997         { "AIF2 Mixer", NULL, "DSP" },
998         { "AIF3 Mixer", NULL, "DSP" },
999         { "DAC1 Mixer", NULL, "DSP" },
1000         { "DAC2 Mixer", NULL, "DSP" },
1001         { "DAC1 Mixer", NULL, "Playback Engine A" },
1002         { "DAC2 Mixer", NULL, "Playback Engine B" },
1003         { "Left ADC Mixer", NULL, "Recording Engine A" },
1004         { "Right ADC Mixer", NULL, "Recording Engine A" },
1005 
1006         { "AIF1 CLK", NULL, "SYSCLK1", adau1373_check_aif_clk },
1007         { "AIF2 CLK", NULL, "SYSCLK1", adau1373_check_aif_clk },
1008         { "AIF3 CLK", NULL, "SYSCLK1", adau1373_check_aif_clk },
1009         { "AIF1 CLK", NULL, "SYSCLK2", adau1373_check_aif_clk },
1010         { "AIF2 CLK", NULL, "SYSCLK2", adau1373_check_aif_clk },
1011         { "AIF3 CLK", NULL, "SYSCLK2", adau1373_check_aif_clk },
1012 
1013         { "AIF1 IN", NULL, "AIF1 CLK" },
1014         { "AIF1 OUT", NULL, "AIF1 CLK" },
1015         { "AIF2 IN", NULL, "AIF2 CLK" },
1016         { "AIF2 OUT", NULL, "AIF2 CLK" },
1017         { "AIF3 IN", NULL, "AIF3 CLK" },
1018         { "AIF3 OUT", NULL, "AIF3 CLK" },
1019         { "AIF1 IN", NULL, "AIF1 IN SRC", adau1373_check_src },
1020         { "AIF1 OUT", NULL, "AIF1 OUT SRC", adau1373_check_src },
1021         { "AIF2 IN", NULL, "AIF2 IN SRC", adau1373_check_src },
1022         { "AIF2 OUT", NULL, "AIF2 OUT SRC", adau1373_check_src },
1023         { "AIF3 IN", NULL, "AIF3 IN SRC", adau1373_check_src },
1024         { "AIF3 OUT", NULL, "AIF3 OUT SRC", adau1373_check_src },
1025 
1026         { "DMIC1", NULL, "DMIC1DAT" },
1027         { "DMIC1", NULL, "SYSCLK1" },
1028         { "DMIC1", NULL, "Recording Engine A" },
1029         { "DMIC2", NULL, "DMIC2DAT" },
1030         { "DMIC2", NULL, "SYSCLK1" },
1031         { "DMIC2", NULL, "Recording Engine B" },
1032 };
1033 
1034 static int adau1373_hw_params(struct snd_pcm_substream *substream,
1035         struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1036 {
1037         struct snd_soc_codec *codec = dai->codec;
1038         struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(codec);
1039         struct adau1373_dai *adau1373_dai = &adau1373->dais[dai->id];
1040         unsigned int div;
1041         unsigned int freq;
1042         unsigned int ctrl;
1043 
1044         freq = adau1373_dai->sysclk;
1045 
1046         if (freq % params_rate(params) != 0)
1047                 return -EINVAL;
1048 
1049         switch (freq / params_rate(params)) {
1050         case 1024: /* sysclk / 256 */
1051                 div = 0;
1052                 break;
1053         case 1536: /* 2/3 sysclk / 256 */
1054                 div = 1;
1055                 break;
1056         case 2048: /* 1/2 sysclk / 256 */
1057                 div = 2;
1058                 break;
1059         case 3072: /* 1/3 sysclk / 256 */
1060                 div = 3;
1061                 break;
1062         case 4096: /* 1/4 sysclk / 256 */
1063                 div = 4;
1064                 break;
1065         case 6144: /* 1/6 sysclk / 256 */
1066                 div = 5;
1067                 break;
1068         case 5632: /* 2/11 sysclk / 256 */
1069                 div = 6;
1070                 break;
1071         default:
1072                 return -EINVAL;
1073         }
1074 
1075         adau1373_dai->enable_src = (div != 0);
1076 
1077         regmap_update_bits(adau1373->regmap, ADAU1373_BCLKDIV(dai->id),
1078                 ADAU1373_BCLKDIV_SR_MASK | ADAU1373_BCLKDIV_BCLK_MASK,
1079                 (div << 2) | ADAU1373_BCLKDIV_64);
1080 
1081         switch (params_width(params)) {
1082         case 16:
1083                 ctrl = ADAU1373_DAI_WLEN_16;
1084                 break;
1085         case 20:
1086                 ctrl = ADAU1373_DAI_WLEN_20;
1087                 break;
1088         case 24:
1089                 ctrl = ADAU1373_DAI_WLEN_24;
1090                 break;
1091         case 32:
1092                 ctrl = ADAU1373_DAI_WLEN_32;
1093                 break;
1094         default:
1095                 return -EINVAL;
1096         }
1097 
1098         return regmap_update_bits(adau1373->regmap, ADAU1373_DAI(dai->id),
1099                         ADAU1373_DAI_WLEN_MASK, ctrl);
1100 }
1101 
1102 static int adau1373_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1103 {
1104         struct snd_soc_codec *codec = dai->codec;
1105         struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(codec);
1106         struct adau1373_dai *adau1373_dai = &adau1373->dais[dai->id];
1107         unsigned int ctrl;
1108 
1109         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1110         case SND_SOC_DAIFMT_CBM_CFM:
1111                 ctrl = ADAU1373_DAI_MASTER;
1112                 adau1373_dai->master = true;
1113                 break;
1114         case SND_SOC_DAIFMT_CBS_CFS:
1115                 ctrl = 0;
1116                 adau1373_dai->master = false;
1117                 break;
1118         default:
1119                 return -EINVAL;
1120         }
1121 
1122         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1123         case SND_SOC_DAIFMT_I2S:
1124                 ctrl |= ADAU1373_DAI_FORMAT_I2S;
1125                 break;
1126         case SND_SOC_DAIFMT_LEFT_J:
1127                 ctrl |= ADAU1373_DAI_FORMAT_LEFT_J;
1128                 break;
1129         case SND_SOC_DAIFMT_RIGHT_J:
1130                 ctrl |= ADAU1373_DAI_FORMAT_RIGHT_J;
1131                 break;
1132         case SND_SOC_DAIFMT_DSP_B:
1133                 ctrl |= ADAU1373_DAI_FORMAT_DSP;
1134                 break;
1135         default:
1136                 return -EINVAL;
1137         }
1138 
1139         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1140         case SND_SOC_DAIFMT_NB_NF:
1141                 break;
1142         case SND_SOC_DAIFMT_IB_NF:
1143                 ctrl |= ADAU1373_DAI_INVERT_BCLK;
1144                 break;
1145         case SND_SOC_DAIFMT_NB_IF:
1146                 ctrl |= ADAU1373_DAI_INVERT_LRCLK;
1147                 break;
1148         case SND_SOC_DAIFMT_IB_IF:
1149                 ctrl |= ADAU1373_DAI_INVERT_LRCLK | ADAU1373_DAI_INVERT_BCLK;
1150                 break;
1151         default:
1152                 return -EINVAL;
1153         }
1154 
1155         regmap_update_bits(adau1373->regmap, ADAU1373_DAI(dai->id),
1156                 ~ADAU1373_DAI_WLEN_MASK, ctrl);
1157 
1158         return 0;
1159 }
1160 
1161 static int adau1373_set_dai_sysclk(struct snd_soc_dai *dai,
1162         int clk_id, unsigned int freq, int dir)
1163 {
1164         struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(dai->codec);
1165         struct adau1373_dai *adau1373_dai = &adau1373->dais[dai->id];
1166 
1167         switch (clk_id) {
1168         case ADAU1373_CLK_SRC_PLL1:
1169         case ADAU1373_CLK_SRC_PLL2:
1170                 break;
1171         default:
1172                 return -EINVAL;
1173         }
1174 
1175         adau1373_dai->sysclk = freq;
1176         adau1373_dai->clk_src = clk_id;
1177 
1178         regmap_update_bits(adau1373->regmap, ADAU1373_BCLKDIV(dai->id),
1179                 ADAU1373_BCLKDIV_SOURCE, clk_id << 5);
1180 
1181         return 0;
1182 }
1183 
1184 static const struct snd_soc_dai_ops adau1373_dai_ops = {
1185         .hw_params      = adau1373_hw_params,
1186         .set_sysclk     = adau1373_set_dai_sysclk,
1187         .set_fmt        = adau1373_set_dai_fmt,
1188 };
1189 
1190 #define ADAU1373_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1191         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1192 
1193 static struct snd_soc_dai_driver adau1373_dai_driver[] = {
1194         {
1195                 .id = 0,
1196                 .name = "adau1373-aif1",
1197                 .playback = {
1198                         .stream_name = "AIF1 Playback",
1199                         .channels_min = 2,
1200                         .channels_max = 2,
1201                         .rates = SNDRV_PCM_RATE_8000_48000,
1202                         .formats = ADAU1373_FORMATS,
1203                 },
1204                 .capture = {
1205                         .stream_name = "AIF1 Capture",
1206                         .channels_min = 2,
1207                         .channels_max = 2,
1208                         .rates = SNDRV_PCM_RATE_8000_48000,
1209                         .formats = ADAU1373_FORMATS,
1210                 },
1211                 .ops = &adau1373_dai_ops,
1212                 .symmetric_rates = 1,
1213         },
1214         {
1215                 .id = 1,
1216                 .name = "adau1373-aif2",
1217                 .playback = {
1218                         .stream_name = "AIF2 Playback",
1219                         .channels_min = 2,
1220                         .channels_max = 2,
1221                         .rates = SNDRV_PCM_RATE_8000_48000,
1222                         .formats = ADAU1373_FORMATS,
1223                 },
1224                 .capture = {
1225                         .stream_name = "AIF2 Capture",
1226                         .channels_min = 2,
1227                         .channels_max = 2,
1228                         .rates = SNDRV_PCM_RATE_8000_48000,
1229                         .formats = ADAU1373_FORMATS,
1230                 },
1231                 .ops = &adau1373_dai_ops,
1232                 .symmetric_rates = 1,
1233         },
1234         {
1235                 .id = 2,
1236                 .name = "adau1373-aif3",
1237                 .playback = {
1238                         .stream_name = "AIF3 Playback",
1239                         .channels_min = 2,
1240                         .channels_max = 2,
1241                         .rates = SNDRV_PCM_RATE_8000_48000,
1242                         .formats = ADAU1373_FORMATS,
1243                 },
1244                 .capture = {
1245                         .stream_name = "AIF3 Capture",
1246                         .channels_min = 2,
1247                         .channels_max = 2,
1248                         .rates = SNDRV_PCM_RATE_8000_48000,
1249                         .formats = ADAU1373_FORMATS,
1250                 },
1251                 .ops = &adau1373_dai_ops,
1252                 .symmetric_rates = 1,
1253         },
1254 };
1255 
1256 static int adau1373_set_pll(struct snd_soc_codec *codec, int pll_id,
1257         int source, unsigned int freq_in, unsigned int freq_out)
1258 {
1259         struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(codec);
1260         unsigned int dpll_div = 0;
1261         unsigned int x, r, n, m, i, j, mode;
1262 
1263         switch (pll_id) {
1264         case ADAU1373_PLL1:
1265         case ADAU1373_PLL2:
1266                 break;
1267         default:
1268                 return -EINVAL;
1269         }
1270 
1271         switch (source) {
1272         case ADAU1373_PLL_SRC_BCLK1:
1273         case ADAU1373_PLL_SRC_BCLK2:
1274         case ADAU1373_PLL_SRC_BCLK3:
1275         case ADAU1373_PLL_SRC_LRCLK1:
1276         case ADAU1373_PLL_SRC_LRCLK2:
1277         case ADAU1373_PLL_SRC_LRCLK3:
1278         case ADAU1373_PLL_SRC_MCLK1:
1279         case ADAU1373_PLL_SRC_MCLK2:
1280         case ADAU1373_PLL_SRC_GPIO1:
1281         case ADAU1373_PLL_SRC_GPIO2:
1282         case ADAU1373_PLL_SRC_GPIO3:
1283         case ADAU1373_PLL_SRC_GPIO4:
1284                 break;
1285         default:
1286                 return -EINVAL;
1287         }
1288 
1289         if (freq_in < 7813 || freq_in > 27000000)
1290                 return -EINVAL;
1291 
1292         if (freq_out < 45158000 || freq_out > 49152000)
1293                 return -EINVAL;
1294 
1295         /* APLL input needs to be >= 8Mhz, so in case freq_in is less we use the
1296          * DPLL to get it there. DPLL_out = (DPLL_in / div) * 1024 */
1297         while (freq_in < 8000000) {
1298                 freq_in *= 2;
1299                 dpll_div++;
1300         }
1301 
1302         if (freq_out % freq_in != 0) {
1303                 /* fout = fin * (r + (n/m)) / x */
1304                 x = DIV_ROUND_UP(freq_in, 13500000);
1305                 freq_in /= x;
1306                 r = freq_out / freq_in;
1307                 i = freq_out % freq_in;
1308                 j = gcd(i, freq_in);
1309                 n = i / j;
1310                 m = freq_in / j;
1311                 x--;
1312                 mode = 1;
1313         } else {
1314                 /* fout = fin / r */
1315                 r = freq_out / freq_in;
1316                 n = 0;
1317                 m = 0;
1318                 x = 0;
1319                 mode = 0;
1320         }
1321 
1322         if (r < 2 || r > 8 || x > 3 || m > 0xffff || n > 0xffff)
1323                 return -EINVAL;
1324 
1325         if (dpll_div) {
1326                 dpll_div = 11 - dpll_div;
1327                 regmap_update_bits(adau1373->regmap, ADAU1373_PLL_CTRL6(pll_id),
1328                         ADAU1373_PLL_CTRL6_DPLL_BYPASS, 0);
1329         } else {
1330                 regmap_update_bits(adau1373->regmap, ADAU1373_PLL_CTRL6(pll_id),
1331                         ADAU1373_PLL_CTRL6_DPLL_BYPASS,
1332                         ADAU1373_PLL_CTRL6_DPLL_BYPASS);
1333         }
1334 
1335         regmap_write(adau1373->regmap, ADAU1373_DPLL_CTRL(pll_id),
1336                 (source << 4) | dpll_div);
1337         regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL1(pll_id), (m >> 8) & 0xff);
1338         regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL2(pll_id), m & 0xff);
1339         regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL3(pll_id), (n >> 8) & 0xff);
1340         regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL4(pll_id), n & 0xff);
1341         regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL5(pll_id),
1342                 (r << 3) | (x << 1) | mode);
1343 
1344         /* Set sysclk to pll_rate / 4 */
1345         regmap_update_bits(adau1373->regmap, ADAU1373_CLK_SRC_DIV(pll_id), 0x3f, 0x09);
1346 
1347         return 0;
1348 }
1349 
1350 static void adau1373_load_drc_settings(struct adau1373 *adau1373,
1351         unsigned int nr, uint8_t *drc)
1352 {
1353         unsigned int i;
1354 
1355         for (i = 0; i < ADAU1373_DRC_SIZE; ++i)
1356                 regmap_write(adau1373->regmap, ADAU1373_DRC(nr) + i, drc[i]);
1357 }
1358 
1359 static bool adau1373_valid_micbias(enum adau1373_micbias_voltage micbias)
1360 {
1361         switch (micbias) {
1362         case ADAU1373_MICBIAS_2_9V:
1363         case ADAU1373_MICBIAS_2_2V:
1364         case ADAU1373_MICBIAS_2_6V:
1365         case ADAU1373_MICBIAS_1_8V:
1366                 return true;
1367         default:
1368                 break;
1369         }
1370         return false;
1371 }
1372 
1373 static int adau1373_probe(struct snd_soc_codec *codec)
1374 {
1375         struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(codec);
1376         struct adau1373_platform_data *pdata = codec->dev->platform_data;
1377         bool lineout_differential = false;
1378         unsigned int val;
1379         int i;
1380 
1381         if (pdata) {
1382                 if (pdata->num_drc > ARRAY_SIZE(pdata->drc_setting))
1383                         return -EINVAL;
1384 
1385                 if (!adau1373_valid_micbias(pdata->micbias1) ||
1386                         !adau1373_valid_micbias(pdata->micbias2))
1387                         return -EINVAL;
1388 
1389                 for (i = 0; i < pdata->num_drc; ++i) {
1390                         adau1373_load_drc_settings(adau1373, i,
1391                                 pdata->drc_setting[i]);
1392                 }
1393 
1394                 snd_soc_add_codec_controls(codec, adau1373_drc_controls,
1395                         pdata->num_drc);
1396 
1397                 val = 0;
1398                 for (i = 0; i < 4; ++i) {
1399                         if (pdata->input_differential[i])
1400                                 val |= BIT(i);
1401                 }
1402                 regmap_write(adau1373->regmap, ADAU1373_INPUT_MODE, val);
1403 
1404                 val = 0;
1405                 if (pdata->lineout_differential)
1406                         val |= ADAU1373_OUTPUT_CTRL_LDIFF;
1407                 if (pdata->lineout_ground_sense)
1408                         val |= ADAU1373_OUTPUT_CTRL_LNFBEN;
1409                 regmap_write(adau1373->regmap, ADAU1373_OUTPUT_CTRL, val);
1410 
1411                 lineout_differential = pdata->lineout_differential;
1412 
1413                 regmap_write(adau1373->regmap, ADAU1373_EP_CTRL,
1414                         (pdata->micbias1 << ADAU1373_EP_CTRL_MICBIAS1_OFFSET) |
1415                         (pdata->micbias2 << ADAU1373_EP_CTRL_MICBIAS2_OFFSET));
1416         }
1417 
1418         if (!lineout_differential) {
1419                 snd_soc_add_codec_controls(codec, adau1373_lineout2_controls,
1420                         ARRAY_SIZE(adau1373_lineout2_controls));
1421         }
1422 
1423         regmap_write(adau1373->regmap, ADAU1373_ADC_CTRL,
1424             ADAU1373_ADC_CTRL_RESET_FORCE | ADAU1373_ADC_CTRL_PEAK_DETECT);
1425 
1426         return 0;
1427 }
1428 
1429 static int adau1373_set_bias_level(struct snd_soc_codec *codec,
1430         enum snd_soc_bias_level level)
1431 {
1432         struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(codec);
1433 
1434         switch (level) {
1435         case SND_SOC_BIAS_ON:
1436                 break;
1437         case SND_SOC_BIAS_PREPARE:
1438                 break;
1439         case SND_SOC_BIAS_STANDBY:
1440                 regmap_update_bits(adau1373->regmap, ADAU1373_PWDN_CTRL3,
1441                         ADAU1373_PWDN_CTRL3_PWR_EN, ADAU1373_PWDN_CTRL3_PWR_EN);
1442                 break;
1443         case SND_SOC_BIAS_OFF:
1444                 regmap_update_bits(adau1373->regmap, ADAU1373_PWDN_CTRL3,
1445                         ADAU1373_PWDN_CTRL3_PWR_EN, 0);
1446                 break;
1447         }
1448         codec->dapm.bias_level = level;
1449         return 0;
1450 }
1451 
1452 static int adau1373_remove(struct snd_soc_codec *codec)
1453 {
1454         adau1373_set_bias_level(codec, SND_SOC_BIAS_OFF);
1455         return 0;
1456 }
1457 
1458 static int adau1373_suspend(struct snd_soc_codec *codec)
1459 {
1460         struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(codec);
1461         int ret;
1462 
1463         ret = adau1373_set_bias_level(codec, SND_SOC_BIAS_OFF);
1464         regcache_cache_only(adau1373->regmap, true);
1465 
1466         return ret;
1467 }
1468 
1469 static int adau1373_resume(struct snd_soc_codec *codec)
1470 {
1471         struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(codec);
1472 
1473         regcache_cache_only(adau1373->regmap, false);
1474         adau1373_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1475         regcache_sync(adau1373->regmap);
1476 
1477         return 0;
1478 }
1479 
1480 static bool adau1373_register_volatile(struct device *dev, unsigned int reg)
1481 {
1482         switch (reg) {
1483         case ADAU1373_SOFT_RESET:
1484         case ADAU1373_ADC_DAC_STATUS:
1485                 return true;
1486         default:
1487                 return false;
1488         }
1489 }
1490 
1491 static const struct regmap_config adau1373_regmap_config = {
1492         .val_bits = 8,
1493         .reg_bits = 8,
1494 
1495         .volatile_reg = adau1373_register_volatile,
1496         .max_register = ADAU1373_SOFT_RESET,
1497 
1498         .cache_type = REGCACHE_RBTREE,
1499         .reg_defaults = adau1373_reg_defaults,
1500         .num_reg_defaults = ARRAY_SIZE(adau1373_reg_defaults),
1501 };
1502 
1503 static struct snd_soc_codec_driver adau1373_codec_driver = {
1504         .probe =        adau1373_probe,
1505         .remove =       adau1373_remove,
1506         .suspend =      adau1373_suspend,
1507         .resume =       adau1373_resume,
1508         .set_bias_level = adau1373_set_bias_level,
1509         .idle_bias_off = true,
1510 
1511         .set_pll = adau1373_set_pll,
1512 
1513         .controls = adau1373_controls,
1514         .num_controls = ARRAY_SIZE(adau1373_controls),
1515         .dapm_widgets = adau1373_dapm_widgets,
1516         .num_dapm_widgets = ARRAY_SIZE(adau1373_dapm_widgets),
1517         .dapm_routes = adau1373_dapm_routes,
1518         .num_dapm_routes = ARRAY_SIZE(adau1373_dapm_routes),
1519 };
1520 
1521 static int adau1373_i2c_probe(struct i2c_client *client,
1522                               const struct i2c_device_id *id)
1523 {
1524         struct adau1373 *adau1373;
1525         int ret;
1526 
1527         adau1373 = devm_kzalloc(&client->dev, sizeof(*adau1373), GFP_KERNEL);
1528         if (!adau1373)
1529                 return -ENOMEM;
1530 
1531         adau1373->regmap = devm_regmap_init_i2c(client,
1532                 &adau1373_regmap_config);
1533         if (IS_ERR(adau1373->regmap))
1534                 return PTR_ERR(adau1373->regmap);
1535 
1536         regmap_write(adau1373->regmap, ADAU1373_SOFT_RESET, 0x00);
1537 
1538         dev_set_drvdata(&client->dev, adau1373);
1539 
1540         ret = snd_soc_register_codec(&client->dev, &adau1373_codec_driver,
1541                         adau1373_dai_driver, ARRAY_SIZE(adau1373_dai_driver));
1542         return ret;
1543 }
1544 
1545 static int adau1373_i2c_remove(struct i2c_client *client)
1546 {
1547         snd_soc_unregister_codec(&client->dev);
1548         return 0;
1549 }
1550 
1551 static const struct i2c_device_id adau1373_i2c_id[] = {
1552         { "adau1373", 0 },
1553         { }
1554 };
1555 MODULE_DEVICE_TABLE(i2c, adau1373_i2c_id);
1556 
1557 static struct i2c_driver adau1373_i2c_driver = {
1558         .driver = {
1559                 .name = "adau1373",
1560                 .owner = THIS_MODULE,
1561         },
1562         .probe = adau1373_i2c_probe,
1563         .remove = adau1373_i2c_remove,
1564         .id_table = adau1373_i2c_id,
1565 };
1566 
1567 module_i2c_driver(adau1373_i2c_driver);
1568 
1569 MODULE_DESCRIPTION("ASoC ADAU1373 driver");
1570 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
1571 MODULE_LICENSE("GPL");
1572 

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