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Linux/sound/soc/codecs/adau1977.c

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  1 /*
  2  * ADAU1977/ADAU1978/ADAU1979 driver
  3  *
  4  * Copyright 2014 Analog Devices Inc.
  5  *  Author: Lars-Peter Clausen <lars@metafoo.de>
  6  *
  7  * Licensed under the GPL-2.
  8  */
  9 
 10 #include <linux/delay.h>
 11 #include <linux/device.h>
 12 #include <linux/gpio/consumer.h>
 13 #include <linux/i2c.h>
 14 #include <linux/init.h>
 15 #include <linux/module.h>
 16 #include <linux/platform_data/adau1977.h>
 17 #include <linux/regmap.h>
 18 #include <linux/regulator/consumer.h>
 19 #include <linux/slab.h>
 20 
 21 #include <sound/core.h>
 22 #include <sound/initval.h>
 23 #include <sound/pcm.h>
 24 #include <sound/pcm_params.h>
 25 #include <sound/soc.h>
 26 #include <sound/tlv.h>
 27 
 28 #include "adau1977.h"
 29 
 30 #define ADAU1977_REG_POWER              0x00
 31 #define ADAU1977_REG_PLL                0x01
 32 #define ADAU1977_REG_BOOST              0x02
 33 #define ADAU1977_REG_MICBIAS            0x03
 34 #define ADAU1977_REG_BLOCK_POWER_SAI    0x04
 35 #define ADAU1977_REG_SAI_CTRL0          0x05
 36 #define ADAU1977_REG_SAI_CTRL1          0x06
 37 #define ADAU1977_REG_CMAP12             0x07
 38 #define ADAU1977_REG_CMAP34             0x08
 39 #define ADAU1977_REG_SAI_OVERTEMP       0x09
 40 #define ADAU1977_REG_POST_ADC_GAIN(x)   (0x0a + (x))
 41 #define ADAU1977_REG_MISC_CONTROL       0x0e
 42 #define ADAU1977_REG_DIAG_CONTROL       0x10
 43 #define ADAU1977_REG_STATUS(x)          (0x11 + (x))
 44 #define ADAU1977_REG_DIAG_IRQ1          0x15
 45 #define ADAU1977_REG_DIAG_IRQ2          0x16
 46 #define ADAU1977_REG_ADJUST1            0x17
 47 #define ADAU1977_REG_ADJUST2            0x18
 48 #define ADAU1977_REG_ADC_CLIP           0x19
 49 #define ADAU1977_REG_DC_HPF_CAL         0x1a
 50 
 51 #define ADAU1977_POWER_RESET                    BIT(7)
 52 #define ADAU1977_POWER_PWUP                     BIT(0)
 53 
 54 #define ADAU1977_PLL_CLK_S                      BIT(4)
 55 #define ADAU1977_PLL_MCS_MASK                   0x7
 56 
 57 #define ADAU1977_MICBIAS_MB_VOLTS_MASK          0xf0
 58 #define ADAU1977_MICBIAS_MB_VOLTS_OFFSET        4
 59 
 60 #define ADAU1977_BLOCK_POWER_SAI_LR_POL         BIT(7)
 61 #define ADAU1977_BLOCK_POWER_SAI_BCLK_EDGE      BIT(6)
 62 #define ADAU1977_BLOCK_POWER_SAI_LDO_EN         BIT(5)
 63 
 64 #define ADAU1977_SAI_CTRL0_FMT_MASK             (0x3 << 6)
 65 #define ADAU1977_SAI_CTRL0_FMT_I2S              (0x0 << 6)
 66 #define ADAU1977_SAI_CTRL0_FMT_LJ               (0x1 << 6)
 67 #define ADAU1977_SAI_CTRL0_FMT_RJ_24BIT         (0x2 << 6)
 68 #define ADAU1977_SAI_CTRL0_FMT_RJ_16BIT         (0x3 << 6)
 69 
 70 #define ADAU1977_SAI_CTRL0_SAI_MASK             (0x7 << 3)
 71 #define ADAU1977_SAI_CTRL0_SAI_I2S              (0x0 << 3)
 72 #define ADAU1977_SAI_CTRL0_SAI_TDM_2            (0x1 << 3)
 73 #define ADAU1977_SAI_CTRL0_SAI_TDM_4            (0x2 << 3)
 74 #define ADAU1977_SAI_CTRL0_SAI_TDM_8            (0x3 << 3)
 75 #define ADAU1977_SAI_CTRL0_SAI_TDM_16           (0x4 << 3)
 76 
 77 #define ADAU1977_SAI_CTRL0_FS_MASK              (0x7)
 78 #define ADAU1977_SAI_CTRL0_FS_8000_12000        (0x0)
 79 #define ADAU1977_SAI_CTRL0_FS_16000_24000       (0x1)
 80 #define ADAU1977_SAI_CTRL0_FS_32000_48000       (0x2)
 81 #define ADAU1977_SAI_CTRL0_FS_64000_96000       (0x3)
 82 #define ADAU1977_SAI_CTRL0_FS_128000_192000     (0x4)
 83 
 84 #define ADAU1977_SAI_CTRL1_SLOT_WIDTH_MASK      (0x3 << 5)
 85 #define ADAU1977_SAI_CTRL1_SLOT_WIDTH_32        (0x0 << 5)
 86 #define ADAU1977_SAI_CTRL1_SLOT_WIDTH_24        (0x1 << 5)
 87 #define ADAU1977_SAI_CTRL1_SLOT_WIDTH_16        (0x2 << 5)
 88 #define ADAU1977_SAI_CTRL1_DATA_WIDTH_MASK      (0x1 << 4)
 89 #define ADAU1977_SAI_CTRL1_DATA_WIDTH_16BIT     (0x1 << 4)
 90 #define ADAU1977_SAI_CTRL1_DATA_WIDTH_24BIT     (0x0 << 4)
 91 #define ADAU1977_SAI_CTRL1_LRCLK_PULSE          BIT(3)
 92 #define ADAU1977_SAI_CTRL1_MSB                  BIT(2)
 93 #define ADAU1977_SAI_CTRL1_BCLKRATE_16          (0x1 << 1)
 94 #define ADAU1977_SAI_CTRL1_BCLKRATE_32          (0x0 << 1)
 95 #define ADAU1977_SAI_CTRL1_BCLKRATE_MASK        (0x1 << 1)
 96 #define ADAU1977_SAI_CTRL1_MASTER               BIT(0)
 97 
 98 #define ADAU1977_SAI_OVERTEMP_DRV_C(x)          BIT(4 + (x))
 99 #define ADAU1977_SAI_OVERTEMP_DRV_HIZ           BIT(3)
100 
101 #define ADAU1977_MISC_CONTROL_SUM_MODE_MASK     (0x3 << 6)
102 #define ADAU1977_MISC_CONTROL_SUM_MODE_1CH      (0x2 << 6)
103 #define ADAU1977_MISC_CONTROL_SUM_MODE_2CH      (0x1 << 6)
104 #define ADAU1977_MISC_CONTROL_SUM_MODE_4CH      (0x0 << 6)
105 #define ADAU1977_MISC_CONTROL_MMUTE             BIT(4)
106 #define ADAU1977_MISC_CONTROL_DC_CAL            BIT(0)
107 
108 #define ADAU1977_CHAN_MAP_SECOND_SLOT_OFFSET    4
109 #define ADAU1977_CHAN_MAP_FIRST_SLOT_OFFSET     0
110 
111 struct adau1977 {
112         struct regmap *regmap;
113         bool right_j;
114         unsigned int sysclk;
115         enum adau1977_sysclk_src sysclk_src;
116         struct gpio_desc *reset_gpio;
117         enum adau1977_type type;
118 
119         struct regulator *avdd_reg;
120         struct regulator *dvdd_reg;
121 
122         struct snd_pcm_hw_constraint_list constraints;
123 
124         struct device *dev;
125         void (*switch_mode)(struct device *dev);
126 
127         unsigned int max_master_fs;
128         unsigned int slot_width;
129         bool enabled;
130         bool master;
131 };
132 
133 static const struct reg_default adau1977_reg_defaults[] = {
134         { 0x00, 0x00 },
135         { 0x01, 0x41 },
136         { 0x02, 0x4a },
137         { 0x03, 0x7d },
138         { 0x04, 0x3d },
139         { 0x05, 0x02 },
140         { 0x06, 0x00 },
141         { 0x07, 0x10 },
142         { 0x08, 0x32 },
143         { 0x09, 0xf0 },
144         { 0x0a, 0xa0 },
145         { 0x0b, 0xa0 },
146         { 0x0c, 0xa0 },
147         { 0x0d, 0xa0 },
148         { 0x0e, 0x02 },
149         { 0x10, 0x0f },
150         { 0x15, 0x20 },
151         { 0x16, 0x00 },
152         { 0x17, 0x00 },
153         { 0x18, 0x00 },
154         { 0x1a, 0x00 },
155 };
156 
157 static const DECLARE_TLV_DB_MINMAX_MUTE(adau1977_adc_gain, -3562, 6000);
158 
159 static const struct snd_soc_dapm_widget adau1977_micbias_dapm_widgets[] = {
160         SND_SOC_DAPM_SUPPLY("MICBIAS", ADAU1977_REG_MICBIAS,
161                 3, 0, NULL, 0)
162 };
163 
164 static const struct snd_soc_dapm_widget adau1977_dapm_widgets[] = {
165         SND_SOC_DAPM_SUPPLY("Vref", ADAU1977_REG_BLOCK_POWER_SAI,
166                 4, 0, NULL, 0),
167 
168         SND_SOC_DAPM_ADC("ADC1", "Capture", ADAU1977_REG_BLOCK_POWER_SAI, 0, 0),
169         SND_SOC_DAPM_ADC("ADC2", "Capture", ADAU1977_REG_BLOCK_POWER_SAI, 1, 0),
170         SND_SOC_DAPM_ADC("ADC3", "Capture", ADAU1977_REG_BLOCK_POWER_SAI, 2, 0),
171         SND_SOC_DAPM_ADC("ADC4", "Capture", ADAU1977_REG_BLOCK_POWER_SAI, 3, 0),
172 
173         SND_SOC_DAPM_INPUT("AIN1"),
174         SND_SOC_DAPM_INPUT("AIN2"),
175         SND_SOC_DAPM_INPUT("AIN3"),
176         SND_SOC_DAPM_INPUT("AIN4"),
177 
178         SND_SOC_DAPM_OUTPUT("VREF"),
179 };
180 
181 static const struct snd_soc_dapm_route adau1977_dapm_routes[] = {
182         { "ADC1", NULL, "AIN1" },
183         { "ADC2", NULL, "AIN2" },
184         { "ADC3", NULL, "AIN3" },
185         { "ADC4", NULL, "AIN4" },
186 
187         { "ADC1", NULL, "Vref" },
188         { "ADC2", NULL, "Vref" },
189         { "ADC3", NULL, "Vref" },
190         { "ADC4", NULL, "Vref" },
191 
192         { "VREF", NULL, "Vref" },
193 };
194 
195 #define ADAU1977_VOLUME(x) \
196         SOC_SINGLE_TLV("ADC" #x " Capture Volume", \
197                 ADAU1977_REG_POST_ADC_GAIN((x) - 1), \
198                 0, 255, 1, adau1977_adc_gain)
199 
200 #define ADAU1977_HPF_SWITCH(x) \
201         SOC_SINGLE("ADC" #x " Highpass-Filter Capture Switch", \
202                 ADAU1977_REG_DC_HPF_CAL, (x) - 1, 1, 0)
203 
204 #define ADAU1977_DC_SUB_SWITCH(x) \
205         SOC_SINGLE("ADC" #x " DC Subtraction Capture Switch", \
206                 ADAU1977_REG_DC_HPF_CAL, (x) + 3, 1, 0)
207 
208 static const struct snd_kcontrol_new adau1977_snd_controls[] = {
209         ADAU1977_VOLUME(1),
210         ADAU1977_VOLUME(2),
211         ADAU1977_VOLUME(3),
212         ADAU1977_VOLUME(4),
213 
214         ADAU1977_HPF_SWITCH(1),
215         ADAU1977_HPF_SWITCH(2),
216         ADAU1977_HPF_SWITCH(3),
217         ADAU1977_HPF_SWITCH(4),
218 
219         ADAU1977_DC_SUB_SWITCH(1),
220         ADAU1977_DC_SUB_SWITCH(2),
221         ADAU1977_DC_SUB_SWITCH(3),
222         ADAU1977_DC_SUB_SWITCH(4),
223 };
224 
225 static int adau1977_reset(struct adau1977 *adau1977)
226 {
227         int ret;
228 
229         /*
230          * The reset bit is obviously volatile, but we need to be able to cache
231          * the other bits in the register, so we can't just mark the whole
232          * register as volatile. Since this is the only place where we'll ever
233          * touch the reset bit just bypass the cache for this operation.
234          */
235         regcache_cache_bypass(adau1977->regmap, true);
236         ret = regmap_write(adau1977->regmap, ADAU1977_REG_POWER,
237                         ADAU1977_POWER_RESET);
238         regcache_cache_bypass(adau1977->regmap, false);
239         if (ret)
240                 return ret;
241 
242         return ret;
243 }
244 
245 /*
246  * Returns the appropriate setting for ths FS field in the CTRL0 register
247  * depending on the rate.
248  */
249 static int adau1977_lookup_fs(unsigned int rate)
250 {
251         if (rate >= 8000 && rate <= 12000)
252                 return ADAU1977_SAI_CTRL0_FS_8000_12000;
253         else if (rate >= 16000 && rate <= 24000)
254                 return ADAU1977_SAI_CTRL0_FS_16000_24000;
255         else if (rate >= 32000 && rate <= 48000)
256                 return ADAU1977_SAI_CTRL0_FS_32000_48000;
257         else if (rate >= 64000 && rate <= 96000)
258                 return ADAU1977_SAI_CTRL0_FS_64000_96000;
259         else if (rate >= 128000 && rate <= 192000)
260                 return ADAU1977_SAI_CTRL0_FS_128000_192000;
261         else
262                 return -EINVAL;
263 }
264 
265 static int adau1977_lookup_mcs(struct adau1977 *adau1977, unsigned int rate,
266         unsigned int fs)
267 {
268         unsigned int mcs;
269 
270         /*
271          * rate = sysclk / (512 * mcs_lut[mcs]) * 2**fs
272          * => mcs_lut[mcs] = sysclk / (512 * rate) * 2**fs
273          * => mcs_lut[mcs] = sysclk / ((512 / 2**fs) * rate)
274          */
275 
276         rate *= 512 >> fs;
277 
278         if (adau1977->sysclk % rate != 0)
279                 return -EINVAL;
280 
281         mcs = adau1977->sysclk / rate;
282 
283         /* The factors configured by MCS are 1, 2, 3, 4, 6 */
284         if (mcs < 1 || mcs > 6 || mcs == 5)
285                 return -EINVAL;
286 
287         mcs = mcs - 1;
288         if (mcs == 5)
289                 mcs = 4;
290 
291         return mcs;
292 }
293 
294 static int adau1977_hw_params(struct snd_pcm_substream *substream,
295         struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
296 {
297         struct snd_soc_codec *codec = dai->codec;
298         struct adau1977 *adau1977 = snd_soc_codec_get_drvdata(codec);
299         unsigned int rate = params_rate(params);
300         unsigned int slot_width;
301         unsigned int ctrl0, ctrl0_mask;
302         unsigned int ctrl1;
303         int mcs, fs;
304         int ret;
305 
306         fs = adau1977_lookup_fs(rate);
307         if (fs < 0)
308                 return fs;
309 
310         if (adau1977->sysclk_src == ADAU1977_SYSCLK_SRC_MCLK) {
311                 mcs = adau1977_lookup_mcs(adau1977, rate, fs);
312                 if (mcs < 0)
313                         return mcs;
314         } else {
315                 mcs = 0;
316         }
317 
318         ctrl0_mask = ADAU1977_SAI_CTRL0_FS_MASK;
319         ctrl0 = fs;
320 
321         if (adau1977->right_j) {
322                 switch (params_width(params)) {
323                 case 16:
324                         ctrl0 |= ADAU1977_SAI_CTRL0_FMT_RJ_16BIT;
325                         break;
326                 case 24:
327                         ctrl0 |= ADAU1977_SAI_CTRL0_FMT_RJ_24BIT;
328                         break;
329                 default:
330                         return -EINVAL;
331                 }
332                 ctrl0_mask |= ADAU1977_SAI_CTRL0_FMT_MASK;
333         }
334 
335         if (adau1977->master) {
336                 switch (params_width(params)) {
337                 case 16:
338                         ctrl1 = ADAU1977_SAI_CTRL1_DATA_WIDTH_16BIT;
339                         slot_width = 16;
340                         break;
341                 case 24:
342                 case 32:
343                         ctrl1 = ADAU1977_SAI_CTRL1_DATA_WIDTH_24BIT;
344                         slot_width = 32;
345                         break;
346                 default:
347                         return -EINVAL;
348                 }
349 
350                 /* In TDM mode there is a fixed slot width */
351                 if (adau1977->slot_width)
352                         slot_width = adau1977->slot_width;
353 
354                 if (slot_width == 16)
355                         ctrl1 |= ADAU1977_SAI_CTRL1_BCLKRATE_16;
356                 else
357                         ctrl1 |= ADAU1977_SAI_CTRL1_BCLKRATE_32;
358 
359                 ret = regmap_update_bits(adau1977->regmap,
360                         ADAU1977_REG_SAI_CTRL1,
361                         ADAU1977_SAI_CTRL1_DATA_WIDTH_MASK |
362                         ADAU1977_SAI_CTRL1_BCLKRATE_MASK,
363                         ctrl1);
364                 if (ret < 0)
365                         return ret;
366         }
367 
368         ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_CTRL0,
369                                 ctrl0_mask, ctrl0);
370         if (ret < 0)
371                 return ret;
372 
373         return regmap_update_bits(adau1977->regmap, ADAU1977_REG_PLL,
374                                 ADAU1977_PLL_MCS_MASK, mcs);
375 }
376 
377 static int adau1977_power_disable(struct adau1977 *adau1977)
378 {
379         int ret = 0;
380 
381         if (!adau1977->enabled)
382                 return 0;
383 
384         ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_POWER,
385                 ADAU1977_POWER_PWUP, 0);
386         if (ret)
387                 return ret;
388 
389         regcache_mark_dirty(adau1977->regmap);
390 
391         if (adau1977->reset_gpio)
392                 gpiod_set_value_cansleep(adau1977->reset_gpio, 0);
393 
394         regcache_cache_only(adau1977->regmap, true);
395 
396         regulator_disable(adau1977->avdd_reg);
397         if (adau1977->dvdd_reg)
398                 regulator_disable(adau1977->dvdd_reg);
399 
400         adau1977->enabled = false;
401 
402         return 0;
403 }
404 
405 static int adau1977_power_enable(struct adau1977 *adau1977)
406 {
407         unsigned int val;
408         int ret = 0;
409 
410         if (adau1977->enabled)
411                 return 0;
412 
413         ret = regulator_enable(adau1977->avdd_reg);
414         if (ret)
415                 return ret;
416 
417         if (adau1977->dvdd_reg) {
418                 ret = regulator_enable(adau1977->dvdd_reg);
419                 if (ret)
420                         goto err_disable_avdd;
421         }
422 
423         if (adau1977->reset_gpio)
424                 gpiod_set_value_cansleep(adau1977->reset_gpio, 1);
425 
426         regcache_cache_only(adau1977->regmap, false);
427 
428         if (adau1977->switch_mode)
429                 adau1977->switch_mode(adau1977->dev);
430 
431         ret = adau1977_reset(adau1977);
432         if (ret)
433                 goto err_disable_dvdd;
434 
435         ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_POWER,
436                 ADAU1977_POWER_PWUP, ADAU1977_POWER_PWUP);
437         if (ret)
438                 goto err_disable_dvdd;
439 
440         ret = regcache_sync(adau1977->regmap);
441         if (ret)
442                 goto err_disable_dvdd;
443 
444         /*
445          * The PLL register is not affected by the software reset. It is
446          * possible that the value of the register was changed to the
447          * default value while we were in cache only mode. In this case
448          * regcache_sync will skip over it and we have to manually sync
449          * it.
450          */
451         ret = regmap_read(adau1977->regmap, ADAU1977_REG_PLL, &val);
452         if (ret)
453                 goto err_disable_dvdd;
454 
455         if (val == 0x41) {
456                 regcache_cache_bypass(adau1977->regmap, true);
457                 ret = regmap_write(adau1977->regmap, ADAU1977_REG_PLL,
458                         0x41);
459                 if (ret)
460                         goto err_disable_dvdd;
461                 regcache_cache_bypass(adau1977->regmap, false);
462         }
463 
464         adau1977->enabled = true;
465 
466         return ret;
467 
468 err_disable_dvdd:
469         if (adau1977->dvdd_reg)
470                 regulator_disable(adau1977->dvdd_reg);
471 err_disable_avdd:
472                 regulator_disable(adau1977->avdd_reg);
473         return ret;
474 }
475 
476 static int adau1977_set_bias_level(struct snd_soc_codec *codec,
477         enum snd_soc_bias_level level)
478 {
479         struct adau1977 *adau1977 = snd_soc_codec_get_drvdata(codec);
480         int ret = 0;
481 
482         switch (level) {
483         case SND_SOC_BIAS_ON:
484                 break;
485         case SND_SOC_BIAS_PREPARE:
486                 break;
487         case SND_SOC_BIAS_STANDBY:
488                 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF)
489                         ret = adau1977_power_enable(adau1977);
490                 break;
491         case SND_SOC_BIAS_OFF:
492                 ret = adau1977_power_disable(adau1977);
493                 break;
494         }
495 
496         return ret;
497 }
498 
499 static int adau1977_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
500         unsigned int rx_mask, int slots, int width)
501 {
502         struct adau1977 *adau1977 = snd_soc_codec_get_drvdata(dai->codec);
503         unsigned int ctrl0, ctrl1, drv;
504         unsigned int slot[4];
505         unsigned int i;
506         int ret;
507 
508         if (slots == 0) {
509                 /* 0 = No fixed slot width */
510                 adau1977->slot_width = 0;
511                 adau1977->max_master_fs = 192000;
512                 return regmap_update_bits(adau1977->regmap,
513                         ADAU1977_REG_SAI_CTRL0, ADAU1977_SAI_CTRL0_SAI_MASK,
514                         ADAU1977_SAI_CTRL0_SAI_I2S);
515         }
516 
517         if (rx_mask == 0 || tx_mask != 0)
518                 return -EINVAL;
519 
520         drv = 0;
521         for (i = 0; i < 4; i++) {
522                 slot[i] = __ffs(rx_mask);
523                 drv |= ADAU1977_SAI_OVERTEMP_DRV_C(i);
524                 rx_mask &= ~(1 << slot[i]);
525                 if (slot[i] >= slots)
526                         return -EINVAL;
527                 if (rx_mask == 0)
528                         break;
529         }
530 
531         if (rx_mask != 0)
532                 return -EINVAL;
533 
534         switch (width) {
535         case 16:
536                 ctrl1 = ADAU1977_SAI_CTRL1_SLOT_WIDTH_16;
537                 break;
538         case 24:
539                 /* We can only generate 16 bit or 32 bit wide slots */
540                 if (adau1977->master)
541                         return -EINVAL;
542                 ctrl1 = ADAU1977_SAI_CTRL1_SLOT_WIDTH_24;
543                 break;
544         case 32:
545                 ctrl1 = ADAU1977_SAI_CTRL1_SLOT_WIDTH_32;
546                 break;
547         default:
548                 return -EINVAL;
549         }
550 
551         switch (slots) {
552         case 2:
553                 ctrl0 = ADAU1977_SAI_CTRL0_SAI_TDM_2;
554                 break;
555         case 4:
556                 ctrl0 = ADAU1977_SAI_CTRL0_SAI_TDM_4;
557                 break;
558         case 8:
559                 ctrl0 = ADAU1977_SAI_CTRL0_SAI_TDM_8;
560                 break;
561         case 16:
562                 ctrl0 = ADAU1977_SAI_CTRL0_SAI_TDM_16;
563                 break;
564         default:
565                 return -EINVAL;
566         }
567 
568         ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_OVERTEMP,
569                 ADAU1977_SAI_OVERTEMP_DRV_C(0) |
570                 ADAU1977_SAI_OVERTEMP_DRV_C(1) |
571                 ADAU1977_SAI_OVERTEMP_DRV_C(2) |
572                 ADAU1977_SAI_OVERTEMP_DRV_C(3), drv);
573         if (ret)
574                 return ret;
575 
576         ret = regmap_write(adau1977->regmap, ADAU1977_REG_CMAP12,
577                 (slot[1] << ADAU1977_CHAN_MAP_SECOND_SLOT_OFFSET) |
578                 (slot[0] << ADAU1977_CHAN_MAP_FIRST_SLOT_OFFSET));
579         if (ret)
580                 return ret;
581 
582         ret = regmap_write(adau1977->regmap, ADAU1977_REG_CMAP34,
583                 (slot[3] << ADAU1977_CHAN_MAP_SECOND_SLOT_OFFSET) |
584                 (slot[2] << ADAU1977_CHAN_MAP_FIRST_SLOT_OFFSET));
585         if (ret)
586                 return ret;
587 
588         ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_CTRL0,
589                 ADAU1977_SAI_CTRL0_SAI_MASK, ctrl0);
590         if (ret)
591                 return ret;
592 
593         ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_CTRL1,
594                 ADAU1977_SAI_CTRL1_SLOT_WIDTH_MASK, ctrl1);
595         if (ret)
596                 return ret;
597 
598         adau1977->slot_width = width;
599 
600         /* In master mode the maximum bitclock is 24.576 MHz */
601         adau1977->max_master_fs = min(192000, 24576000 / width / slots);
602 
603         return 0;
604 }
605 
606 static int adau1977_mute(struct snd_soc_dai *dai, int mute, int stream)
607 {
608         struct adau1977 *adau1977 = snd_soc_codec_get_drvdata(dai->codec);
609         unsigned int val;
610 
611         if (mute)
612                 val = ADAU1977_MISC_CONTROL_MMUTE;
613         else
614                 val = 0;
615 
616         return regmap_update_bits(adau1977->regmap, ADAU1977_REG_MISC_CONTROL,
617                         ADAU1977_MISC_CONTROL_MMUTE, val);
618 }
619 
620 static int adau1977_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
621 {
622         struct adau1977 *adau1977 = snd_soc_codec_get_drvdata(dai->codec);
623         unsigned int ctrl0 = 0, ctrl1 = 0, block_power = 0;
624         bool invert_lrclk;
625         int ret;
626 
627         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
628         case SND_SOC_DAIFMT_CBS_CFS:
629                 adau1977->master = false;
630                 break;
631         case SND_SOC_DAIFMT_CBM_CFM:
632                 ctrl1 |= ADAU1977_SAI_CTRL1_MASTER;
633                 adau1977->master = true;
634                 break;
635         default:
636                 return -EINVAL;
637         }
638 
639         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
640         case SND_SOC_DAIFMT_NB_NF:
641                 invert_lrclk = false;
642                 break;
643         case SND_SOC_DAIFMT_IB_NF:
644                 block_power |= ADAU1977_BLOCK_POWER_SAI_BCLK_EDGE;
645                 invert_lrclk = false;
646                 break;
647         case SND_SOC_DAIFMT_NB_IF:
648                 invert_lrclk = true;
649                 break;
650         case SND_SOC_DAIFMT_IB_IF:
651                 block_power |= ADAU1977_BLOCK_POWER_SAI_BCLK_EDGE;
652                 invert_lrclk = true;
653                 break;
654         default:
655                 return -EINVAL;
656         }
657 
658         adau1977->right_j = false;
659         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
660         case SND_SOC_DAIFMT_I2S:
661                 ctrl0 |= ADAU1977_SAI_CTRL0_FMT_I2S;
662                 break;
663         case SND_SOC_DAIFMT_LEFT_J:
664                 ctrl0 |= ADAU1977_SAI_CTRL0_FMT_LJ;
665                 invert_lrclk = !invert_lrclk;
666                 break;
667         case SND_SOC_DAIFMT_RIGHT_J:
668                 ctrl0 |= ADAU1977_SAI_CTRL0_FMT_RJ_24BIT;
669                 adau1977->right_j = true;
670                 invert_lrclk = !invert_lrclk;
671                 break;
672         case SND_SOC_DAIFMT_DSP_A:
673                 ctrl1 |= ADAU1977_SAI_CTRL1_LRCLK_PULSE;
674                 ctrl0 |= ADAU1977_SAI_CTRL0_FMT_I2S;
675                 invert_lrclk = false;
676                 break;
677         case SND_SOC_DAIFMT_DSP_B:
678                 ctrl1 |= ADAU1977_SAI_CTRL1_LRCLK_PULSE;
679                 ctrl0 |= ADAU1977_SAI_CTRL0_FMT_LJ;
680                 invert_lrclk = false;
681                 break;
682         default:
683                 return -EINVAL;
684         }
685 
686         if (invert_lrclk)
687                 block_power |= ADAU1977_BLOCK_POWER_SAI_LR_POL;
688 
689         ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_BLOCK_POWER_SAI,
690                 ADAU1977_BLOCK_POWER_SAI_LR_POL |
691                 ADAU1977_BLOCK_POWER_SAI_BCLK_EDGE, block_power);
692         if (ret)
693                 return ret;
694 
695         ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_CTRL0,
696                 ADAU1977_SAI_CTRL0_FMT_MASK,
697                 ctrl0);
698         if (ret)
699                 return ret;
700 
701         return regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_CTRL1,
702                 ADAU1977_SAI_CTRL1_MASTER | ADAU1977_SAI_CTRL1_LRCLK_PULSE,
703                 ctrl1);
704 }
705 
706 static int adau1977_startup(struct snd_pcm_substream *substream,
707         struct snd_soc_dai *dai)
708 {
709         struct adau1977 *adau1977 = snd_soc_codec_get_drvdata(dai->codec);
710         u64 formats = 0;
711 
712         if (adau1977->slot_width == 16)
713                 formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE;
714         else if (adau1977->right_j || adau1977->slot_width == 24)
715                 formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |
716                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE;
717 
718         snd_pcm_hw_constraint_list(substream->runtime, 0,
719                 SNDRV_PCM_HW_PARAM_RATE, &adau1977->constraints);
720 
721         if (adau1977->master)
722                 snd_pcm_hw_constraint_minmax(substream->runtime,
723                         SNDRV_PCM_HW_PARAM_RATE, 8000, adau1977->max_master_fs);
724 
725         if (formats != 0)
726                 snd_pcm_hw_constraint_mask64(substream->runtime,
727                         SNDRV_PCM_HW_PARAM_FORMAT, formats);
728 
729         return 0;
730 }
731 
732 static int adau1977_set_tristate(struct snd_soc_dai *dai, int tristate)
733 {
734         struct adau1977 *adau1977 = snd_soc_codec_get_drvdata(dai->codec);
735         unsigned int val;
736 
737         if (tristate)
738                 val = ADAU1977_SAI_OVERTEMP_DRV_HIZ;
739         else
740                 val = 0;
741 
742         return regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_OVERTEMP,
743                 ADAU1977_SAI_OVERTEMP_DRV_HIZ, val);
744 }
745 
746 static const struct snd_soc_dai_ops adau1977_dai_ops = {
747         .startup        = adau1977_startup,
748         .hw_params      = adau1977_hw_params,
749         .mute_stream    = adau1977_mute,
750         .set_fmt        = adau1977_set_dai_fmt,
751         .set_tdm_slot   = adau1977_set_tdm_slot,
752         .set_tristate   = adau1977_set_tristate,
753 };
754 
755 static struct snd_soc_dai_driver adau1977_dai = {
756         .name = "adau1977-hifi",
757         .capture = {
758                 .stream_name = "Capture",
759                 .channels_min = 1,
760                 .channels_max = 4,
761                 .rates = SNDRV_PCM_RATE_KNOT,
762                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
763                     SNDRV_PCM_FMTBIT_S32_LE,
764                 .sig_bits = 24,
765         },
766         .ops = &adau1977_dai_ops,
767 };
768 
769 static const unsigned int adau1977_rates[] = {
770         8000, 16000, 32000, 64000, 128000,
771         11025, 22050, 44100, 88200, 172400,
772         12000, 24000, 48000, 96000, 192000,
773 };
774 
775 #define ADAU1977_RATE_CONSTRAINT_MASK_32000 0x001f
776 #define ADAU1977_RATE_CONSTRAINT_MASK_44100 0x03e0
777 #define ADAU1977_RATE_CONSTRAINT_MASK_48000 0x7c00
778 /* All rates >= 32000 */
779 #define ADAU1977_RATE_CONSTRAINT_MASK_LRCLK 0x739c
780 
781 static bool adau1977_check_sysclk(unsigned int mclk, unsigned int base_freq)
782 {
783         unsigned int mcs;
784 
785         if (mclk % (base_freq * 128) != 0)
786                 return false;
787 
788         mcs = mclk / (128 * base_freq);
789         if (mcs < 1 || mcs > 6 || mcs == 5)
790                 return false;
791 
792         return true;
793 }
794 
795 static int adau1977_set_sysclk(struct snd_soc_codec *codec,
796         int clk_id, int source, unsigned int freq, int dir)
797 {
798         struct adau1977 *adau1977 = snd_soc_codec_get_drvdata(codec);
799         unsigned int mask = 0;
800         unsigned int clk_src;
801         unsigned int ret;
802 
803         if (dir != SND_SOC_CLOCK_IN)
804                 return -EINVAL;
805 
806         if (clk_id != ADAU1977_SYSCLK)
807                 return -EINVAL;
808 
809         switch (source) {
810         case ADAU1977_SYSCLK_SRC_MCLK:
811                 clk_src = 0;
812                 break;
813         case ADAU1977_SYSCLK_SRC_LRCLK:
814                 clk_src = ADAU1977_PLL_CLK_S;
815                 break;
816         default:
817                 return -EINVAL;
818         }
819 
820         if (freq != 0 && source == ADAU1977_SYSCLK_SRC_MCLK) {
821                 if (freq < 4000000 || freq > 36864000)
822                         return -EINVAL;
823 
824                 if (adau1977_check_sysclk(freq, 32000))
825                         mask |= ADAU1977_RATE_CONSTRAINT_MASK_32000;
826                 if (adau1977_check_sysclk(freq, 44100))
827                         mask |= ADAU1977_RATE_CONSTRAINT_MASK_44100;
828                 if (adau1977_check_sysclk(freq, 48000))
829                         mask |= ADAU1977_RATE_CONSTRAINT_MASK_48000;
830 
831                 if (mask == 0)
832                         return -EINVAL;
833         } else if (source == ADAU1977_SYSCLK_SRC_LRCLK) {
834                 mask = ADAU1977_RATE_CONSTRAINT_MASK_LRCLK;
835         }
836 
837         ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_PLL,
838                 ADAU1977_PLL_CLK_S, clk_src);
839         if (ret)
840                 return ret;
841 
842         adau1977->constraints.mask = mask;
843         adau1977->sysclk_src = source;
844         adau1977->sysclk = freq;
845 
846         return 0;
847 }
848 
849 static int adau1977_codec_probe(struct snd_soc_codec *codec)
850 {
851         struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
852         struct adau1977 *adau1977 = snd_soc_codec_get_drvdata(codec);
853         int ret;
854 
855         switch (adau1977->type) {
856         case ADAU1977:
857                 ret = snd_soc_dapm_new_controls(dapm,
858                         adau1977_micbias_dapm_widgets,
859                         ARRAY_SIZE(adau1977_micbias_dapm_widgets));
860                 if (ret < 0)
861                         return ret;
862                 break;
863         default:
864                 break;
865         }
866 
867         return 0;
868 }
869 
870 static struct snd_soc_codec_driver adau1977_codec_driver = {
871         .probe = adau1977_codec_probe,
872         .set_bias_level = adau1977_set_bias_level,
873         .set_sysclk = adau1977_set_sysclk,
874         .idle_bias_off = true,
875 
876         .controls = adau1977_snd_controls,
877         .num_controls = ARRAY_SIZE(adau1977_snd_controls),
878         .dapm_widgets = adau1977_dapm_widgets,
879         .num_dapm_widgets = ARRAY_SIZE(adau1977_dapm_widgets),
880         .dapm_routes = adau1977_dapm_routes,
881         .num_dapm_routes = ARRAY_SIZE(adau1977_dapm_routes),
882 };
883 
884 static int adau1977_setup_micbias(struct adau1977 *adau1977)
885 {
886         struct adau1977_platform_data *pdata = adau1977->dev->platform_data;
887         unsigned int micbias;
888 
889         if (pdata) {
890                 micbias = pdata->micbias;
891                 if (micbias > ADAU1977_MICBIAS_9V0)
892                         return -EINVAL;
893 
894         } else {
895                 micbias = ADAU1977_MICBIAS_8V5;
896         }
897 
898         return regmap_update_bits(adau1977->regmap, ADAU1977_REG_MICBIAS,
899                 ADAU1977_MICBIAS_MB_VOLTS_MASK,
900                 micbias << ADAU1977_MICBIAS_MB_VOLTS_OFFSET);
901 }
902 
903 int adau1977_probe(struct device *dev, struct regmap *regmap,
904         enum adau1977_type type, void (*switch_mode)(struct device *dev))
905 {
906         unsigned int power_off_mask;
907         struct adau1977 *adau1977;
908         int ret;
909 
910         if (IS_ERR(regmap))
911                 return PTR_ERR(regmap);
912 
913         adau1977 = devm_kzalloc(dev, sizeof(*adau1977), GFP_KERNEL);
914         if (adau1977 == NULL)
915                 return -ENOMEM;
916 
917         adau1977->dev = dev;
918         adau1977->type = type;
919         adau1977->regmap = regmap;
920         adau1977->switch_mode = switch_mode;
921         adau1977->max_master_fs = 192000;
922 
923         adau1977->constraints.list = adau1977_rates;
924         adau1977->constraints.count = ARRAY_SIZE(adau1977_rates);
925 
926         adau1977->avdd_reg = devm_regulator_get(dev, "AVDD");
927         if (IS_ERR(adau1977->avdd_reg))
928                 return PTR_ERR(adau1977->avdd_reg);
929 
930         adau1977->dvdd_reg = devm_regulator_get_optional(dev, "DVDD");
931         if (IS_ERR(adau1977->dvdd_reg)) {
932                 if (PTR_ERR(adau1977->dvdd_reg) != -ENODEV)
933                         return PTR_ERR(adau1977->dvdd_reg);
934                 adau1977->dvdd_reg = NULL;
935         }
936 
937         adau1977->reset_gpio = devm_gpiod_get_optional(dev, "reset",
938                                                        GPIOD_OUT_LOW);
939         if (IS_ERR(adau1977->reset_gpio))
940                 return PTR_ERR(adau1977->reset_gpio);
941 
942         dev_set_drvdata(dev, adau1977);
943 
944         if (adau1977->reset_gpio)
945                 ndelay(100);
946 
947         ret = adau1977_power_enable(adau1977);
948         if (ret)
949                 return ret;
950 
951         if (type == ADAU1977) {
952                 ret = adau1977_setup_micbias(adau1977);
953                 if (ret)
954                         goto err_poweroff;
955         }
956 
957         if (adau1977->dvdd_reg)
958                 power_off_mask = ~0;
959         else
960                 power_off_mask = (unsigned int)~ADAU1977_BLOCK_POWER_SAI_LDO_EN;
961 
962         ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_BLOCK_POWER_SAI,
963                                 power_off_mask, 0x00);
964         if (ret)
965                 goto err_poweroff;
966 
967         ret = adau1977_power_disable(adau1977);
968         if (ret)
969                 return ret;
970 
971         return snd_soc_register_codec(dev, &adau1977_codec_driver,
972                         &adau1977_dai, 1);
973 
974 err_poweroff:
975         adau1977_power_disable(adau1977);
976         return ret;
977 
978 }
979 EXPORT_SYMBOL_GPL(adau1977_probe);
980 
981 static bool adau1977_register_volatile(struct device *dev, unsigned int reg)
982 {
983         switch (reg) {
984         case ADAU1977_REG_STATUS(0):
985         case ADAU1977_REG_STATUS(1):
986         case ADAU1977_REG_STATUS(2):
987         case ADAU1977_REG_STATUS(3):
988         case ADAU1977_REG_ADC_CLIP:
989                 return true;
990         }
991 
992         return false;
993 }
994 
995 const struct regmap_config adau1977_regmap_config = {
996         .max_register = ADAU1977_REG_DC_HPF_CAL,
997         .volatile_reg = adau1977_register_volatile,
998 
999         .cache_type = REGCACHE_RBTREE,
1000         .reg_defaults = adau1977_reg_defaults,
1001         .num_reg_defaults = ARRAY_SIZE(adau1977_reg_defaults),
1002 };
1003 EXPORT_SYMBOL_GPL(adau1977_regmap_config);
1004 
1005 MODULE_DESCRIPTION("ASoC ADAU1977/ADAU1978/ADAU1979 driver");
1006 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
1007 MODULE_LICENSE("GPL");
1008 

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