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TOMOYO Linux Cross Reference
Linux/sound/soc/codecs/cpcap.c

Version: ~ [ linux-5.5-rc7 ] ~ [ linux-5.4.13 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.97 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.166 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.210 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.210 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.19.8 ] ~ [ linux-3.18.140 ] ~ [ linux-3.17.8 ] ~ [ linux-3.16.81 ] ~ [ linux-3.15.10 ] ~ [ linux-3.14.79 ] ~ [ linux-3.13.11 ] ~ [ linux-3.12.74 ] ~ [ linux-3.11.10 ] ~ [ linux-3.10.108 ] ~ [ linux-3.9.11 ] ~ [ linux-3.8.13 ] ~ [ linux-3.7.10 ] ~ [ linux-3.6.11 ] ~ [ linux-3.5.7 ] ~ [ linux-3.4.113 ] ~ [ linux-3.3.8 ] ~ [ linux-3.2.102 ] ~ [ linux-3.1.10 ] ~ [ linux-3.0.101 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.5 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 // SPDX-License-Identifier: GPL-2.0
  2 /*
  3  * ALSA SoC CPCAP codec driver
  4  *
  5  * Copyright (C) 2017 - 2018 Sebastian Reichel <sre@kernel.org>
  6  *
  7  * Very loosely based on original driver from Motorola:
  8  * Copyright (C) 2007 - 2009 Motorola, Inc.
  9  */
 10 
 11 #include <linux/module.h>
 12 #include <linux/regmap.h>
 13 #include <linux/platform_device.h>
 14 #include <linux/mfd/motorola-cpcap.h>
 15 #include <sound/core.h>
 16 #include <sound/soc.h>
 17 #include <sound/tlv.h>
 18 
 19 /* Register 513 CPCAP_REG_CC     --- CODEC */
 20 #define CPCAP_BIT_CDC_CLK2                15
 21 #define CPCAP_BIT_CDC_CLK1                14
 22 #define CPCAP_BIT_CDC_CLK0                13
 23 #define CPCAP_BIT_CDC_SR3                 12
 24 #define CPCAP_BIT_CDC_SR2                 11
 25 #define CPCAP_BIT_CDC_SR1                 10
 26 #define CPCAP_BIT_CDC_SR0                 9
 27 #define CPCAP_BIT_CDC_CLOCK_TREE_RESET    8
 28 #define CPCAP_BIT_MIC2_CDC_EN             7
 29 #define CPCAP_BIT_CDC_EN_RX               6
 30 #define CPCAP_BIT_DF_RESET                5
 31 #define CPCAP_BIT_MIC1_CDC_EN             4
 32 #define CPCAP_BIT_AUDOHPF_1               3
 33 #define CPCAP_BIT_AUDOHPF_0               2
 34 #define CPCAP_BIT_AUDIHPF_1               1
 35 #define CPCAP_BIT_AUDIHPF_0               0
 36 
 37 /* Register 514 CPCAP_REG_CDI    --- CODEC Digital Audio Interface */
 38 #define CPCAP_BIT_CDC_PLL_SEL             15
 39 #define CPCAP_BIT_CLK_IN_SEL              13
 40 #define CPCAP_BIT_DIG_AUD_IN              12
 41 #define CPCAP_BIT_CDC_CLK_EN              11
 42 #define CPCAP_BIT_CDC_DIG_AUD_FS1         10
 43 #define CPCAP_BIT_CDC_DIG_AUD_FS0         9
 44 #define CPCAP_BIT_MIC2_TIMESLOT2          8
 45 #define CPCAP_BIT_MIC2_TIMESLOT1          7
 46 #define CPCAP_BIT_MIC2_TIMESLOT0          6
 47 #define CPCAP_BIT_MIC1_RX_TIMESLOT2       5
 48 #define CPCAP_BIT_MIC1_RX_TIMESLOT1       4
 49 #define CPCAP_BIT_MIC1_RX_TIMESLOT0       3
 50 #define CPCAP_BIT_FS_INV                  2
 51 #define CPCAP_BIT_CLK_INV                 1
 52 #define CPCAP_BIT_SMB_CDC                 0
 53 
 54 /* Register 515 CPCAP_REG_SDAC   --- Stereo DAC */
 55 #define CPCAP_BIT_FSYNC_CLK_IN_COMMON     11
 56 #define CPCAP_BIT_SLAVE_PLL_CLK_INPUT     10
 57 #define CPCAP_BIT_ST_CLOCK_TREE_RESET     9
 58 #define CPCAP_BIT_DF_RESET_ST_DAC         8
 59 #define CPCAP_BIT_ST_SR3                  7
 60 #define CPCAP_BIT_ST_SR2                  6
 61 #define CPCAP_BIT_ST_SR1                  5
 62 #define CPCAP_BIT_ST_SR0                  4
 63 #define CPCAP_BIT_ST_DAC_CLK2             3
 64 #define CPCAP_BIT_ST_DAC_CLK1             2
 65 #define CPCAP_BIT_ST_DAC_CLK0             1
 66 #define CPCAP_BIT_ST_DAC_EN               0
 67 
 68 /* Register 516 CPCAP_REG_SDACDI --- Stereo DAC Digital Audio Interface */
 69 #define CPCAP_BIT_ST_L_TIMESLOT2          13
 70 #define CPCAP_BIT_ST_L_TIMESLOT1          12
 71 #define CPCAP_BIT_ST_L_TIMESLOT0          11
 72 #define CPCAP_BIT_ST_R_TIMESLOT2          10
 73 #define CPCAP_BIT_ST_R_TIMESLOT1          9
 74 #define CPCAP_BIT_ST_R_TIMESLOT0          8
 75 #define CPCAP_BIT_ST_DAC_CLK_IN_SEL       7
 76 #define CPCAP_BIT_ST_FS_INV               6
 77 #define CPCAP_BIT_ST_CLK_INV              5
 78 #define CPCAP_BIT_ST_DIG_AUD_FS1          4
 79 #define CPCAP_BIT_ST_DIG_AUD_FS0          3
 80 #define CPCAP_BIT_DIG_AUD_IN_ST_DAC       2
 81 #define CPCAP_BIT_ST_CLK_EN               1
 82 #define CPCAP_BIT_SMB_ST_DAC              0
 83 
 84 /* Register 517 CPCAP_REG_TXI    --- TX Interface */
 85 #define CPCAP_BIT_PTT_TH                15
 86 #define CPCAP_BIT_PTT_CMP_EN            14
 87 #define CPCAP_BIT_HS_ID_TX              13
 88 #define CPCAP_BIT_MB_ON2                12
 89 #define CPCAP_BIT_MB_ON1L               11
 90 #define CPCAP_BIT_MB_ON1R               10
 91 #define CPCAP_BIT_RX_L_ENCODE           9
 92 #define CPCAP_BIT_RX_R_ENCODE           8
 93 #define CPCAP_BIT_MIC2_MUX              7
 94 #define CPCAP_BIT_MIC2_PGA_EN           6
 95 #define CPCAP_BIT_CDET_DIS              5
 96 #define CPCAP_BIT_EMU_MIC_MUX           4
 97 #define CPCAP_BIT_HS_MIC_MUX            3
 98 #define CPCAP_BIT_MIC1_MUX              2
 99 #define CPCAP_BIT_MIC1_PGA_EN           1
100 #define CPCAP_BIT_DLM                   0
101 
102 /* Register 518 CPCAP_REG_TXMP   --- Mic Gain */
103 #define CPCAP_BIT_MB_BIAS_R1              11
104 #define CPCAP_BIT_MB_BIAS_R0              10
105 #define CPCAP_BIT_MIC2_GAIN_4             9
106 #define CPCAP_BIT_MIC2_GAIN_3             8
107 #define CPCAP_BIT_MIC2_GAIN_2             7
108 #define CPCAP_BIT_MIC2_GAIN_1             6
109 #define CPCAP_BIT_MIC2_GAIN_0             5
110 #define CPCAP_BIT_MIC1_GAIN_4             4
111 #define CPCAP_BIT_MIC1_GAIN_3             3
112 #define CPCAP_BIT_MIC1_GAIN_2             2
113 #define CPCAP_BIT_MIC1_GAIN_1             1
114 #define CPCAP_BIT_MIC1_GAIN_0             0
115 
116 /* Register 519 CPCAP_REG_RXOA   --- RX Output Amplifier */
117 #define CPCAP_BIT_UNUSED_519_15         15
118 #define CPCAP_BIT_UNUSED_519_14         14
119 #define CPCAP_BIT_UNUSED_519_13         13
120 #define CPCAP_BIT_STDAC_LOW_PWR_DISABLE 12
121 #define CPCAP_BIT_HS_LOW_PWR            11
122 #define CPCAP_BIT_HS_ID_RX              10
123 #define CPCAP_BIT_ST_HS_CP_EN           9
124 #define CPCAP_BIT_EMU_SPKR_R_EN         8
125 #define CPCAP_BIT_EMU_SPKR_L_EN         7
126 #define CPCAP_BIT_HS_L_EN               6
127 #define CPCAP_BIT_HS_R_EN               5
128 #define CPCAP_BIT_A4_LINEOUT_L_EN       4
129 #define CPCAP_BIT_A4_LINEOUT_R_EN       3
130 #define CPCAP_BIT_A2_LDSP_L_EN          2
131 #define CPCAP_BIT_A2_LDSP_R_EN          1
132 #define CPCAP_BIT_A1_EAR_EN             0
133 
134 /* Register 520 CPCAP_REG_RXVC   --- RX Volume Control */
135 #define CPCAP_BIT_VOL_EXT3                15
136 #define CPCAP_BIT_VOL_EXT2                14
137 #define CPCAP_BIT_VOL_EXT1                13
138 #define CPCAP_BIT_VOL_EXT0                12
139 #define CPCAP_BIT_VOL_DAC3                11
140 #define CPCAP_BIT_VOL_DAC2                10
141 #define CPCAP_BIT_VOL_DAC1                9
142 #define CPCAP_BIT_VOL_DAC0                8
143 #define CPCAP_BIT_VOL_DAC_LSB_1dB1        7
144 #define CPCAP_BIT_VOL_DAC_LSB_1dB0        6
145 #define CPCAP_BIT_VOL_CDC3                5
146 #define CPCAP_BIT_VOL_CDC2                4
147 #define CPCAP_BIT_VOL_CDC1                3
148 #define CPCAP_BIT_VOL_CDC0                2
149 #define CPCAP_BIT_VOL_CDC_LSB_1dB1        1
150 #define CPCAP_BIT_VOL_CDC_LSB_1dB0        0
151 
152 /* Register 521 CPCAP_REG_RXCOA  --- Codec to Output Amp Switches */
153 #define CPCAP_BIT_PGA_CDC_EN              10
154 #define CPCAP_BIT_CDC_SW                  9
155 #define CPCAP_BIT_PGA_OUTR_USBDP_CDC_SW   8
156 #define CPCAP_BIT_PGA_OUTL_USBDN_CDC_SW   7
157 #define CPCAP_BIT_ALEFT_HS_CDC_SW         6
158 #define CPCAP_BIT_ARIGHT_HS_CDC_SW        5
159 #define CPCAP_BIT_A4_LINEOUT_L_CDC_SW     4
160 #define CPCAP_BIT_A4_LINEOUT_R_CDC_SW     3
161 #define CPCAP_BIT_A2_LDSP_L_CDC_SW        2
162 #define CPCAP_BIT_A2_LDSP_R_CDC_SW        1
163 #define CPCAP_BIT_A1_EAR_CDC_SW           0
164 
165 /* Register 522 CPCAP_REG_RXSDOA --- RX Stereo DAC to Output Amp Switches */
166 #define CPCAP_BIT_PGA_DAC_EN              12
167 #define CPCAP_BIT_ST_DAC_SW               11
168 #define CPCAP_BIT_MONO_DAC1               10
169 #define CPCAP_BIT_MONO_DAC0               9
170 #define CPCAP_BIT_PGA_OUTR_USBDP_DAC_SW   8
171 #define CPCAP_BIT_PGA_OUTL_USBDN_DAC_SW   7
172 #define CPCAP_BIT_ALEFT_HS_DAC_SW         6
173 #define CPCAP_BIT_ARIGHT_HS_DAC_SW        5
174 #define CPCAP_BIT_A4_LINEOUT_L_DAC_SW     4
175 #define CPCAP_BIT_A4_LINEOUT_R_DAC_SW     3
176 #define CPCAP_BIT_A2_LDSP_L_DAC_SW        2
177 #define CPCAP_BIT_A2_LDSP_R_DAC_SW        1
178 #define CPCAP_BIT_A1_EAR_DAC_SW           0
179 
180 /* Register 523 CPCAP_REG_RXEPOA --- RX External PGA to Output Amp Switches */
181 #define CPCAP_BIT_PGA_EXT_L_EN            14
182 #define CPCAP_BIT_PGA_EXT_R_EN            13
183 #define CPCAP_BIT_PGA_IN_L_SW             12
184 #define CPCAP_BIT_PGA_IN_R_SW             11
185 #define CPCAP_BIT_MONO_EXT1               10
186 #define CPCAP_BIT_MONO_EXT0               9
187 #define CPCAP_BIT_PGA_OUTR_USBDP_EXT_SW   8
188 #define CPCAP_BIT_PGA_OUTL_USBDN_EXT_SW   7
189 #define CPCAP_BIT_ALEFT_HS_EXT_SW         6
190 #define CPCAP_BIT_ARIGHT_HS_EXT_SW        5
191 #define CPCAP_BIT_A4_LINEOUT_L_EXT_SW     4
192 #define CPCAP_BIT_A4_LINEOUT_R_EXT_SW     3
193 #define CPCAP_BIT_A2_LDSP_L_EXT_SW        2
194 #define CPCAP_BIT_A2_LDSP_R_EXT_SW        1
195 #define CPCAP_BIT_A1_EAR_EXT_SW           0
196 
197 /* Register 525 CPCAP_REG_A2LA --- SPK Amplifier and Clock Config for Headset */
198 #define CPCAP_BIT_NCP_CLK_SYNC            7
199 #define CPCAP_BIT_A2_CLK_SYNC             6
200 #define CPCAP_BIT_A2_FREE_RUN             5
201 #define CPCAP_BIT_A2_CLK2                 4
202 #define CPCAP_BIT_A2_CLK1                 3
203 #define CPCAP_BIT_A2_CLK0                 2
204 #define CPCAP_BIT_A2_CLK_IN               1
205 #define CPCAP_BIT_A2_CONFIG               0
206 
207 #define SLEEP_ACTIVATE_POWER 2
208 #define CLOCK_TREE_RESET_TIME 1
209 
210 /* constants for ST delay workaround */
211 #define STM_STDAC_ACTIVATE_RAMP_TIME   1
212 #define STM_STDAC_EN_TEST_PRE          0x090C
213 #define STM_STDAC_EN_TEST_POST         0x0000
214 #define STM_STDAC_EN_ST_TEST1_PRE      0x2400
215 #define STM_STDAC_EN_ST_TEST1_POST     0x0400
216 
217 struct cpcap_reg_info {
218         u16 reg;
219         u16 mask;
220         u16 val;
221 };
222 
223 static const struct cpcap_reg_info cpcap_default_regs[] = {
224         { CPCAP_REG_CC, 0xFFFF, 0x0000 },
225         { CPCAP_REG_CC, 0xFFFF, 0x0000 },
226         { CPCAP_REG_CDI, 0xBFFF, 0x0000 },
227         { CPCAP_REG_SDAC, 0x0FFF, 0x0000 },
228         { CPCAP_REG_SDACDI, 0x3FFF, 0x0000 },
229         { CPCAP_REG_TXI, 0x0FDF, 0x0000 },
230         { CPCAP_REG_TXMP, 0x0FFF, 0x0400 },
231         { CPCAP_REG_RXOA, 0x01FF, 0x0000 },
232         { CPCAP_REG_RXVC, 0xFF3C, 0x0000 },
233         { CPCAP_REG_RXCOA, 0x07FF, 0x0000 },
234         { CPCAP_REG_RXSDOA, 0x1FFF, 0x0000 },
235         { CPCAP_REG_RXEPOA, 0x7FFF, 0x0000 },
236         { CPCAP_REG_A2LA, BIT(CPCAP_BIT_A2_FREE_RUN),
237           BIT(CPCAP_BIT_A2_FREE_RUN) },
238 };
239 
240 enum cpcap_dai {
241         CPCAP_DAI_HIFI,
242         CPCAP_DAI_VOICE,
243 };
244 
245 struct cpcap_audio {
246         struct snd_soc_component *component;
247         struct regmap *regmap;
248 
249         u16 vendor;
250 
251         int codec_clk_id;
252         int codec_freq;
253         int codec_format;
254 };
255 
256 static int cpcap_st_workaround(struct snd_soc_dapm_widget *w,
257                                struct snd_kcontrol *kcontrol, int event)
258 {
259         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
260         struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
261         int err = 0;
262 
263         /* Only CPCAP from ST requires workaround */
264         if (cpcap->vendor != CPCAP_VENDOR_ST)
265                 return 0;
266 
267         switch (event) {
268         case SND_SOC_DAPM_PRE_PMU:
269                 err = regmap_write(cpcap->regmap, CPCAP_REG_TEST,
270                                    STM_STDAC_EN_TEST_PRE);
271                 if (err)
272                         return err;
273                 err = regmap_write(cpcap->regmap, CPCAP_REG_ST_TEST1,
274                                    STM_STDAC_EN_ST_TEST1_PRE);
275                 break;
276         case SND_SOC_DAPM_POST_PMU:
277                 msleep(STM_STDAC_ACTIVATE_RAMP_TIME);
278 
279                 err = regmap_write(cpcap->regmap, CPCAP_REG_ST_TEST1,
280                                    STM_STDAC_EN_ST_TEST1_POST);
281                 if (err)
282                         return err;
283                 err = regmap_write(cpcap->regmap, CPCAP_REG_TEST,
284                                    STM_STDAC_EN_TEST_POST);
285                 break;
286         default:
287                 break;
288         }
289 
290         return err;
291 }
292 
293 /* Capture Gain Control: 0dB to 31dB in 1dB steps */
294 static const DECLARE_TLV_DB_SCALE(mic_gain_tlv, 0, 100, 0);
295 
296 /* Playback Gain Control: -33dB to 12dB in 3dB steps */
297 static const DECLARE_TLV_DB_SCALE(vol_tlv, -3300, 300, 0);
298 
299 static const struct snd_kcontrol_new cpcap_snd_controls[] = {
300         /* Playback Gain */
301         SOC_SINGLE_TLV("HiFi Playback Volume",
302                 CPCAP_REG_RXVC, CPCAP_BIT_VOL_DAC0, 0xF, 0, vol_tlv),
303         SOC_SINGLE_TLV("Voice Playback Volume",
304                 CPCAP_REG_RXVC, CPCAP_BIT_VOL_CDC0, 0xF, 0, vol_tlv),
305         SOC_SINGLE_TLV("Ext Playback Volume",
306                 CPCAP_REG_RXVC, CPCAP_BIT_VOL_EXT0, 0xF, 0, vol_tlv),
307 
308         /* Capture Gain */
309         SOC_SINGLE_TLV("Mic1 Capture Volume",
310                 CPCAP_REG_TXMP, CPCAP_BIT_MIC1_GAIN_0, 0x1F, 0, mic_gain_tlv),
311         SOC_SINGLE_TLV("Mic2 Capture Volume",
312                 CPCAP_REG_TXMP, CPCAP_BIT_MIC2_GAIN_0, 0x1F, 0, mic_gain_tlv),
313 
314         /* Phase Invert */
315         SOC_SINGLE("Hifi Left Phase Invert Switch",
316                 CPCAP_REG_RXSDOA, CPCAP_BIT_MONO_DAC0, 1, 0),
317         SOC_SINGLE("Ext Left Phase Invert Switch",
318                 CPCAP_REG_RXEPOA, CPCAP_BIT_MONO_EXT0, 1, 0),
319 };
320 
321 static const char * const cpcap_out_mux_texts[] = {
322         "Off", "Voice", "HiFi", "Ext"
323 };
324 
325 static const char * const cpcap_in_right_mux_texts[] = {
326         "Off", "Mic 1", "Headset Mic", "EMU Mic", "Ext Right"
327 };
328 
329 static const char * const cpcap_in_left_mux_texts[] = {
330         "Off", "Mic 2", "Ext Left"
331 };
332 
333 /*
334  * input muxes use unusual register layout, so that we need to use custom
335  * getter/setter methods
336  */
337 static SOC_ENUM_SINGLE_EXT_DECL(cpcap_input_left_mux_enum,
338                                 cpcap_in_left_mux_texts);
339 static SOC_ENUM_SINGLE_EXT_DECL(cpcap_input_right_mux_enum,
340                                 cpcap_in_right_mux_texts);
341 
342 /*
343  * mux uses same bit in CPCAP_REG_RXCOA, CPCAP_REG_RXSDOA & CPCAP_REG_RXEPOA;
344  * even though the register layout makes it look like a mixer, this is a mux.
345  * Enabling multiple inputs will result in no audio being forwarded.
346  */
347 static SOC_ENUM_SINGLE_DECL(cpcap_earpiece_mux_enum, 0, 0, cpcap_out_mux_texts);
348 static SOC_ENUM_SINGLE_DECL(cpcap_spkr_r_mux_enum, 0, 1, cpcap_out_mux_texts);
349 static SOC_ENUM_SINGLE_DECL(cpcap_spkr_l_mux_enum, 0, 2, cpcap_out_mux_texts);
350 static SOC_ENUM_SINGLE_DECL(cpcap_line_r_mux_enum, 0, 3, cpcap_out_mux_texts);
351 static SOC_ENUM_SINGLE_DECL(cpcap_line_l_mux_enum, 0, 4, cpcap_out_mux_texts);
352 static SOC_ENUM_SINGLE_DECL(cpcap_hs_r_mux_enum, 0, 5, cpcap_out_mux_texts);
353 static SOC_ENUM_SINGLE_DECL(cpcap_hs_l_mux_enum, 0, 6, cpcap_out_mux_texts);
354 static SOC_ENUM_SINGLE_DECL(cpcap_emu_l_mux_enum, 0, 7, cpcap_out_mux_texts);
355 static SOC_ENUM_SINGLE_DECL(cpcap_emu_r_mux_enum, 0, 8, cpcap_out_mux_texts);
356 
357 static int cpcap_output_mux_get_enum(struct snd_kcontrol *kcontrol,
358                                      struct snd_ctl_elem_value *ucontrol)
359 {
360         struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
361         struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
362         struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
363         unsigned int shift = e->shift_l;
364         int reg_voice, reg_hifi, reg_ext, status;
365         int err;
366 
367         err = regmap_read(cpcap->regmap, CPCAP_REG_RXCOA, &reg_voice);
368         if (err)
369                 return err;
370         err = regmap_read(cpcap->regmap, CPCAP_REG_RXSDOA, &reg_hifi);
371         if (err)
372                 return err;
373         err = regmap_read(cpcap->regmap, CPCAP_REG_RXEPOA, &reg_ext);
374         if (err)
375                 return err;
376 
377         reg_voice = (reg_voice >> shift) & 1;
378         reg_hifi = (reg_hifi >> shift) & 1;
379         reg_ext = (reg_ext >> shift) & 1;
380         status = reg_ext << 2 | reg_hifi << 1 | reg_voice;
381 
382         switch (status) {
383         case 0x04:
384                 ucontrol->value.enumerated.item[0] = 3;
385                 break;
386         case 0x02:
387                 ucontrol->value.enumerated.item[0] = 2;
388                 break;
389         case 0x01:
390                 ucontrol->value.enumerated.item[0] = 1;
391                 break;
392         default:
393                 ucontrol->value.enumerated.item[0] = 0;
394                 break;
395         }
396 
397         return 0;
398 }
399 
400 static int cpcap_output_mux_put_enum(struct snd_kcontrol *kcontrol,
401                                      struct snd_ctl_elem_value *ucontrol)
402 {
403         struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
404         struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
405         struct snd_soc_dapm_context *dapm =
406                 snd_soc_dapm_kcontrol_dapm(kcontrol);
407         struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
408         unsigned int muxval = ucontrol->value.enumerated.item[0];
409         unsigned int mask = BIT(e->shift_l);
410         u16 reg_voice = 0x00, reg_hifi = 0x00, reg_ext = 0x00;
411         int err;
412 
413         switch (muxval) {
414         case 1:
415                 reg_voice = mask;
416                 break;
417         case 2:
418                 reg_hifi = mask;
419                 break;
420         case 3:
421                 reg_ext = mask;
422                 break;
423         default:
424                 break;
425         }
426 
427         err = regmap_update_bits(cpcap->regmap, CPCAP_REG_RXCOA,
428                                  mask, reg_voice);
429         if (err)
430                 return err;
431         err = regmap_update_bits(cpcap->regmap, CPCAP_REG_RXSDOA,
432                                  mask, reg_hifi);
433         if (err)
434                 return err;
435         err = regmap_update_bits(cpcap->regmap, CPCAP_REG_RXEPOA,
436                                  mask, reg_ext);
437         if (err)
438                 return err;
439 
440         snd_soc_dapm_mux_update_power(dapm, kcontrol, muxval, e, NULL);
441 
442         return 0;
443 }
444 
445 static int cpcap_input_right_mux_get_enum(struct snd_kcontrol *kcontrol,
446                                           struct snd_ctl_elem_value *ucontrol)
447 {
448         struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
449         struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
450         int regval, mask;
451         int err;
452 
453         err = regmap_read(cpcap->regmap, CPCAP_REG_TXI, &regval);
454         if (err)
455                 return err;
456 
457         mask = 0;
458         mask |= BIT(CPCAP_BIT_MIC1_MUX);
459         mask |= BIT(CPCAP_BIT_HS_MIC_MUX);
460         mask |= BIT(CPCAP_BIT_EMU_MIC_MUX);
461         mask |= BIT(CPCAP_BIT_RX_R_ENCODE);
462 
463         switch (regval & mask) {
464         case BIT(CPCAP_BIT_RX_R_ENCODE):
465                 ucontrol->value.enumerated.item[0] = 4;
466                 break;
467         case BIT(CPCAP_BIT_EMU_MIC_MUX):
468                 ucontrol->value.enumerated.item[0] = 3;
469                 break;
470         case BIT(CPCAP_BIT_HS_MIC_MUX):
471                 ucontrol->value.enumerated.item[0] = 2;
472                 break;
473         case BIT(CPCAP_BIT_MIC1_MUX):
474                 ucontrol->value.enumerated.item[0] = 1;
475                 break;
476         default:
477                 ucontrol->value.enumerated.item[0] = 0;
478                 break;
479         }
480 
481         return 0;
482 }
483 
484 static int cpcap_input_right_mux_put_enum(struct snd_kcontrol *kcontrol,
485                                           struct snd_ctl_elem_value *ucontrol)
486 {
487         struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
488         struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
489         struct snd_soc_dapm_context *dapm =
490                 snd_soc_dapm_kcontrol_dapm(kcontrol);
491         struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
492         unsigned int muxval = ucontrol->value.enumerated.item[0];
493         int regval = 0, mask;
494         int err;
495 
496         mask = 0;
497         mask |= BIT(CPCAP_BIT_MIC1_MUX);
498         mask |= BIT(CPCAP_BIT_HS_MIC_MUX);
499         mask |= BIT(CPCAP_BIT_EMU_MIC_MUX);
500         mask |= BIT(CPCAP_BIT_RX_R_ENCODE);
501 
502         switch (muxval) {
503         case 1:
504                 regval = BIT(CPCAP_BIT_MIC1_MUX);
505                 break;
506         case 2:
507                 regval = BIT(CPCAP_BIT_HS_MIC_MUX);
508                 break;
509         case 3:
510                 regval = BIT(CPCAP_BIT_EMU_MIC_MUX);
511                 break;
512         case 4:
513                 regval = BIT(CPCAP_BIT_RX_R_ENCODE);
514                 break;
515         default:
516                 break;
517         }
518 
519         err = regmap_update_bits(cpcap->regmap, CPCAP_REG_TXI,
520                                  mask, regval);
521         if (err)
522                 return err;
523 
524         snd_soc_dapm_mux_update_power(dapm, kcontrol, muxval, e, NULL);
525 
526         return 0;
527 }
528 
529 static int cpcap_input_left_mux_get_enum(struct snd_kcontrol *kcontrol,
530                                          struct snd_ctl_elem_value *ucontrol)
531 {
532         struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
533         struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
534         int regval, mask;
535         int err;
536 
537         err = regmap_read(cpcap->regmap, CPCAP_REG_TXI, &regval);
538         if (err)
539                 return err;
540 
541         mask = 0;
542         mask |= BIT(CPCAP_BIT_MIC2_MUX);
543         mask |= BIT(CPCAP_BIT_RX_L_ENCODE);
544 
545         switch (regval & mask) {
546         case BIT(CPCAP_BIT_RX_L_ENCODE):
547                 ucontrol->value.enumerated.item[0] = 2;
548                 break;
549         case BIT(CPCAP_BIT_MIC2_MUX):
550                 ucontrol->value.enumerated.item[0] = 1;
551                 break;
552         default:
553                 ucontrol->value.enumerated.item[0] = 0;
554                 break;
555         }
556 
557         return 0;
558 }
559 
560 static int cpcap_input_left_mux_put_enum(struct snd_kcontrol *kcontrol,
561                                          struct snd_ctl_elem_value *ucontrol)
562 {
563         struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
564         struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
565         struct snd_soc_dapm_context *dapm =
566                 snd_soc_dapm_kcontrol_dapm(kcontrol);
567         struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
568         unsigned int muxval = ucontrol->value.enumerated.item[0];
569         int regval = 0, mask;
570         int err;
571 
572         mask = 0;
573         mask |= BIT(CPCAP_BIT_MIC2_MUX);
574         mask |= BIT(CPCAP_BIT_RX_L_ENCODE);
575 
576         switch (muxval) {
577         case 1:
578                 regval = BIT(CPCAP_BIT_MIC2_MUX);
579                 break;
580         case 2:
581                 regval = BIT(CPCAP_BIT_RX_L_ENCODE);
582                 break;
583         default:
584                 break;
585         }
586 
587         err = regmap_update_bits(cpcap->regmap, CPCAP_REG_TXI,
588                                  mask, regval);
589         if (err)
590                 return err;
591 
592         snd_soc_dapm_mux_update_power(dapm, kcontrol, muxval, e, NULL);
593 
594         return 0;
595 }
596 
597 static const struct snd_kcontrol_new cpcap_input_left_mux =
598         SOC_DAPM_ENUM_EXT("Input Left", cpcap_input_left_mux_enum,
599                           cpcap_input_left_mux_get_enum,
600                           cpcap_input_left_mux_put_enum);
601 static const struct snd_kcontrol_new cpcap_input_right_mux =
602         SOC_DAPM_ENUM_EXT("Input Right", cpcap_input_right_mux_enum,
603                           cpcap_input_right_mux_get_enum,
604                           cpcap_input_right_mux_put_enum);
605 static const struct snd_kcontrol_new cpcap_emu_left_mux =
606         SOC_DAPM_ENUM_EXT("EMU Left", cpcap_emu_l_mux_enum,
607                           cpcap_output_mux_get_enum, cpcap_output_mux_put_enum);
608 static const struct snd_kcontrol_new cpcap_emu_right_mux =
609         SOC_DAPM_ENUM_EXT("EMU Right", cpcap_emu_r_mux_enum,
610                           cpcap_output_mux_get_enum, cpcap_output_mux_put_enum);
611 static const struct snd_kcontrol_new cpcap_hs_left_mux =
612         SOC_DAPM_ENUM_EXT("Headset Left", cpcap_hs_l_mux_enum,
613                           cpcap_output_mux_get_enum, cpcap_output_mux_put_enum);
614 static const struct snd_kcontrol_new cpcap_hs_right_mux =
615         SOC_DAPM_ENUM_EXT("Headset Right", cpcap_hs_r_mux_enum,
616                           cpcap_output_mux_get_enum, cpcap_output_mux_put_enum);
617 static const struct snd_kcontrol_new cpcap_line_left_mux =
618         SOC_DAPM_ENUM_EXT("Line Left", cpcap_line_l_mux_enum,
619                           cpcap_output_mux_get_enum, cpcap_output_mux_put_enum);
620 static const struct snd_kcontrol_new cpcap_line_right_mux =
621         SOC_DAPM_ENUM_EXT("Line Right", cpcap_line_r_mux_enum,
622                           cpcap_output_mux_get_enum, cpcap_output_mux_put_enum);
623 static const struct snd_kcontrol_new cpcap_speaker_left_mux =
624         SOC_DAPM_ENUM_EXT("Speaker Left", cpcap_spkr_l_mux_enum,
625                           cpcap_output_mux_get_enum, cpcap_output_mux_put_enum);
626 static const struct snd_kcontrol_new cpcap_speaker_right_mux =
627         SOC_DAPM_ENUM_EXT("Speaker Right", cpcap_spkr_r_mux_enum,
628                           cpcap_output_mux_get_enum, cpcap_output_mux_put_enum);
629 static const struct snd_kcontrol_new cpcap_earpiece_mux =
630         SOC_DAPM_ENUM_EXT("Earpiece", cpcap_earpiece_mux_enum,
631                           cpcap_output_mux_get_enum, cpcap_output_mux_put_enum);
632 
633 static const struct snd_kcontrol_new cpcap_hifi_mono_mixer_controls[] = {
634         SOC_DAPM_SINGLE("HiFi Mono Playback Switch",
635                 CPCAP_REG_RXSDOA, CPCAP_BIT_MONO_DAC1, 1, 0),
636 };
637 static const struct snd_kcontrol_new cpcap_ext_mono_mixer_controls[] = {
638         SOC_DAPM_SINGLE("Ext Mono Playback Switch",
639                 CPCAP_REG_RXEPOA, CPCAP_BIT_MONO_EXT0, 1, 0),
640 };
641 
642 static const struct snd_kcontrol_new cpcap_extr_mute_control =
643         SOC_DAPM_SINGLE("Switch",
644                 CPCAP_REG_RXEPOA, CPCAP_BIT_PGA_IN_R_SW, 1, 0);
645 static const struct snd_kcontrol_new cpcap_extl_mute_control =
646         SOC_DAPM_SINGLE("Switch",
647                 CPCAP_REG_RXEPOA, CPCAP_BIT_PGA_IN_L_SW, 1, 0);
648 
649 static const struct snd_kcontrol_new cpcap_voice_loopback =
650         SOC_DAPM_SINGLE("Switch",
651                 CPCAP_REG_TXI, CPCAP_BIT_DLM, 1, 0);
652 
653 static const struct snd_soc_dapm_widget cpcap_dapm_widgets[] = {
654         /* DAIs */
655         SND_SOC_DAPM_AIF_IN("HiFi RX", NULL, 0, SND_SOC_NOPM, 0, 0),
656         SND_SOC_DAPM_AIF_IN("Voice RX", NULL, 0, SND_SOC_NOPM, 0, 0),
657         SND_SOC_DAPM_AIF_OUT("Voice TX", NULL, 0, SND_SOC_NOPM, 0, 0),
658 
659         /* Power Supply */
660         SND_SOC_DAPM_REGULATOR_SUPPLY("VAUDIO", SLEEP_ACTIVATE_POWER, 0),
661 
662         /* Highpass Filters */
663         SND_SOC_DAPM_REG(snd_soc_dapm_pga, "Highpass Filter RX",
664                 CPCAP_REG_CC, CPCAP_BIT_AUDIHPF_0, 0x3, 0x3, 0x0),
665         SND_SOC_DAPM_REG(snd_soc_dapm_pga, "Highpass Filter TX",
666                 CPCAP_REG_CC, CPCAP_BIT_AUDOHPF_0, 0x3, 0x3, 0x0),
667 
668         /* Clocks */
669         SND_SOC_DAPM_SUPPLY("HiFi DAI Clock",
670                 CPCAP_REG_SDACDI, CPCAP_BIT_ST_CLK_EN, 0, NULL, 0),
671         SND_SOC_DAPM_SUPPLY("Voice DAI Clock",
672                 CPCAP_REG_CDI, CPCAP_BIT_CDC_CLK_EN, 0, NULL, 0),
673 
674         /* Microphone Bias */
675         SND_SOC_DAPM_SUPPLY("MIC1R Bias",
676                 CPCAP_REG_TXI, CPCAP_BIT_MB_ON1R, 0, NULL, 0),
677         SND_SOC_DAPM_SUPPLY("MIC1L Bias",
678                 CPCAP_REG_TXI, CPCAP_BIT_MB_ON1L, 0, NULL, 0),
679         SND_SOC_DAPM_SUPPLY("MIC2 Bias",
680                 CPCAP_REG_TXI, CPCAP_BIT_MB_ON2, 0, NULL, 0),
681 
682         /* Inputs */
683         SND_SOC_DAPM_INPUT("MICR"),
684         SND_SOC_DAPM_INPUT("HSMIC"),
685         SND_SOC_DAPM_INPUT("EMUMIC"),
686         SND_SOC_DAPM_INPUT("MICL"),
687         SND_SOC_DAPM_INPUT("EXTR"),
688         SND_SOC_DAPM_INPUT("EXTL"),
689 
690         /* Capture Route */
691         SND_SOC_DAPM_MUX("Right Capture Route",
692                 SND_SOC_NOPM, 0, 0, &cpcap_input_right_mux),
693         SND_SOC_DAPM_MUX("Left Capture Route",
694                 SND_SOC_NOPM, 0, 0, &cpcap_input_left_mux),
695 
696         /* Capture PGAs */
697         SND_SOC_DAPM_PGA("Microphone 1 PGA",
698                 CPCAP_REG_TXI, CPCAP_BIT_MIC1_PGA_EN, 0, NULL, 0),
699         SND_SOC_DAPM_PGA("Microphone 2 PGA",
700                 CPCAP_REG_TXI, CPCAP_BIT_MIC2_PGA_EN, 0, NULL, 0),
701 
702         /* ADC */
703         SND_SOC_DAPM_ADC("ADC Right", NULL,
704                 CPCAP_REG_CC, CPCAP_BIT_MIC1_CDC_EN, 0),
705         SND_SOC_DAPM_ADC("ADC Left", NULL,
706                 CPCAP_REG_CC, CPCAP_BIT_MIC2_CDC_EN, 0),
707 
708         /* DAC */
709         SND_SOC_DAPM_DAC_E("DAC HiFi", NULL,
710                 CPCAP_REG_SDAC, CPCAP_BIT_ST_DAC_EN, 0,
711                 cpcap_st_workaround,
712                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
713         SND_SOC_DAPM_DAC_E("DAC Voice", NULL,
714                 CPCAP_REG_CC, CPCAP_BIT_CDC_EN_RX, 0,
715                 cpcap_st_workaround,
716                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
717 
718         /* Playback PGA */
719         SND_SOC_DAPM_PGA("HiFi PGA",
720                 CPCAP_REG_RXSDOA, CPCAP_BIT_PGA_DAC_EN, 0, NULL, 0),
721         SND_SOC_DAPM_PGA("Voice PGA",
722                 CPCAP_REG_RXCOA, CPCAP_BIT_PGA_CDC_EN, 0, NULL, 0),
723         SND_SOC_DAPM_PGA_E("Ext Right PGA",
724                 CPCAP_REG_RXEPOA, CPCAP_BIT_PGA_EXT_R_EN, 0,
725                 NULL, 0,
726                 cpcap_st_workaround,
727                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
728         SND_SOC_DAPM_PGA_E("Ext Left PGA",
729                 CPCAP_REG_RXEPOA, CPCAP_BIT_PGA_EXT_L_EN, 0,
730                 NULL, 0,
731                 cpcap_st_workaround,
732                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
733 
734         /* Playback Switch */
735         SND_SOC_DAPM_SWITCH("Ext Right Enable", SND_SOC_NOPM, 0, 0,
736                 &cpcap_extr_mute_control),
737         SND_SOC_DAPM_SWITCH("Ext Left Enable", SND_SOC_NOPM, 0, 0,
738                 &cpcap_extl_mute_control),
739 
740         /* Loopback Switch */
741         SND_SOC_DAPM_SWITCH("Voice Loopback", SND_SOC_NOPM, 0, 0,
742                 &cpcap_voice_loopback),
743 
744         /* Mono Mixer */
745         SOC_MIXER_ARRAY("HiFi Mono Left Mixer", SND_SOC_NOPM, 0, 0,
746                 cpcap_hifi_mono_mixer_controls),
747         SOC_MIXER_ARRAY("HiFi Mono Right Mixer", SND_SOC_NOPM, 0, 0,
748                 cpcap_hifi_mono_mixer_controls),
749         SOC_MIXER_ARRAY("Ext Mono Left Mixer", SND_SOC_NOPM, 0, 0,
750                 cpcap_ext_mono_mixer_controls),
751         SOC_MIXER_ARRAY("Ext Mono Right Mixer", SND_SOC_NOPM, 0, 0,
752                 cpcap_ext_mono_mixer_controls),
753 
754         /* Output Routes */
755         SND_SOC_DAPM_MUX("Earpiece Playback Route", SND_SOC_NOPM, 0, 0,
756                 &cpcap_earpiece_mux),
757         SND_SOC_DAPM_MUX("Speaker Right Playback Route", SND_SOC_NOPM, 0, 0,
758                 &cpcap_speaker_right_mux),
759         SND_SOC_DAPM_MUX("Speaker Left Playback Route", SND_SOC_NOPM, 0, 0,
760                 &cpcap_speaker_left_mux),
761         SND_SOC_DAPM_MUX("Lineout Right Playback Route", SND_SOC_NOPM, 0, 0,
762                 &cpcap_line_right_mux),
763         SND_SOC_DAPM_MUX("Lineout Left Playback Route", SND_SOC_NOPM, 0, 0,
764                 &cpcap_line_left_mux),
765         SND_SOC_DAPM_MUX("Headset Right Playback Route", SND_SOC_NOPM, 0, 0,
766                 &cpcap_hs_right_mux),
767         SND_SOC_DAPM_MUX("Headset Left Playback Route", SND_SOC_NOPM, 0, 0,
768                 &cpcap_hs_left_mux),
769         SND_SOC_DAPM_MUX("EMU Right Playback Route", SND_SOC_NOPM, 0, 0,
770                 &cpcap_emu_right_mux),
771         SND_SOC_DAPM_MUX("EMU Left Playback Route", SND_SOC_NOPM, 0, 0,
772                 &cpcap_emu_left_mux),
773 
774         /* Output Amplifier */
775         SND_SOC_DAPM_PGA("Earpiece PGA",
776                 CPCAP_REG_RXOA, CPCAP_BIT_A1_EAR_EN, 0, NULL, 0),
777         SND_SOC_DAPM_PGA("Speaker Right PGA",
778                 CPCAP_REG_RXOA, CPCAP_BIT_A2_LDSP_R_EN, 0, NULL, 0),
779         SND_SOC_DAPM_PGA("Speaker Left PGA",
780                 CPCAP_REG_RXOA, CPCAP_BIT_A2_LDSP_L_EN, 0, NULL, 0),
781         SND_SOC_DAPM_PGA("Lineout Right PGA",
782                 CPCAP_REG_RXOA, CPCAP_BIT_A4_LINEOUT_R_EN, 0, NULL, 0),
783         SND_SOC_DAPM_PGA("Lineout Left PGA",
784                 CPCAP_REG_RXOA, CPCAP_BIT_A4_LINEOUT_L_EN, 0, NULL, 0),
785         SND_SOC_DAPM_PGA("Headset Right PGA",
786                 CPCAP_REG_RXOA, CPCAP_BIT_HS_R_EN, 0, NULL, 0),
787         SND_SOC_DAPM_PGA("Headset Left PGA",
788                 CPCAP_REG_RXOA, CPCAP_BIT_HS_L_EN, 0, NULL, 0),
789         SND_SOC_DAPM_PGA("EMU Right PGA",
790                 CPCAP_REG_RXOA, CPCAP_BIT_EMU_SPKR_R_EN, 0, NULL, 0),
791         SND_SOC_DAPM_PGA("EMU Left PGA",
792                 CPCAP_REG_RXOA, CPCAP_BIT_EMU_SPKR_L_EN, 0, NULL, 0),
793 
794         /* Headet Charge Pump */
795         SND_SOC_DAPM_SUPPLY("Headset Charge Pump",
796                 CPCAP_REG_RXOA, CPCAP_BIT_ST_HS_CP_EN, 0, NULL, 0),
797 
798         /* Outputs */
799         SND_SOC_DAPM_OUTPUT("EP"),
800         SND_SOC_DAPM_OUTPUT("SPKR"),
801         SND_SOC_DAPM_OUTPUT("SPKL"),
802         SND_SOC_DAPM_OUTPUT("LINER"),
803         SND_SOC_DAPM_OUTPUT("LINEL"),
804         SND_SOC_DAPM_OUTPUT("HSR"),
805         SND_SOC_DAPM_OUTPUT("HSL"),
806         SND_SOC_DAPM_OUTPUT("EMUR"),
807         SND_SOC_DAPM_OUTPUT("EMUL"),
808 };
809 
810 static const struct snd_soc_dapm_route intercon[] = {
811         /* Power Supply */
812         {"HiFi PGA", NULL, "VAUDIO"},
813         {"Voice PGA", NULL, "VAUDIO"},
814         {"Ext Right PGA", NULL, "VAUDIO"},
815         {"Ext Left PGA", NULL, "VAUDIO"},
816         {"Microphone 1 PGA", NULL, "VAUDIO"},
817         {"Microphone 2 PGA", NULL, "VAUDIO"},
818 
819         /* Stream -> AIF */
820         {"HiFi RX", NULL, "HiFi Playback"},
821         {"Voice RX", NULL, "Voice Playback"},
822         {"Voice Capture", NULL, "Voice TX"},
823 
824         /* AIF clocks */
825         {"HiFi RX", NULL, "HiFi DAI Clock"},
826         {"Voice RX", NULL, "Voice DAI Clock"},
827         {"Voice TX", NULL, "Voice DAI Clock"},
828 
829         /* Digital Loopback */
830         {"Voice Loopback", "Switch", "Voice TX"},
831         {"Voice RX", NULL, "Voice Loopback"},
832 
833         /* Highpass Filters */
834         {"Highpass Filter RX", NULL, "Voice RX"},
835         {"Voice TX", NULL, "Highpass Filter TX"},
836 
837         /* AIF -> DAC mapping */
838         {"DAC HiFi", NULL, "HiFi RX"},
839         {"DAC Voice", NULL, "Highpass Filter RX"},
840 
841         /* DAC -> PGA */
842         {"HiFi PGA", NULL, "DAC HiFi"},
843         {"Voice PGA", NULL, "DAC Voice"},
844 
845         /* Ext Input -> PGA */
846         {"Ext Right PGA", NULL, "EXTR"},
847         {"Ext Left PGA", NULL, "EXTL"},
848 
849         /* Ext PGA -> Ext Playback Switch */
850         {"Ext Right Enable", "Switch", "Ext Right PGA"},
851         {"Ext Left Enable", "Switch", "Ext Left PGA"},
852 
853         /* HiFi PGA -> Mono Mixer */
854         {"HiFi Mono Left Mixer", NULL, "HiFi PGA"},
855         {"HiFi Mono Left Mixer", "HiFi Mono Playback Switch", "HiFi PGA"},
856         {"HiFi Mono Right Mixer", NULL, "HiFi PGA"},
857         {"HiFi Mono Right Mixer", "HiFi Mono Playback Switch", "HiFi PGA"},
858 
859         /* Ext Playback Switch -> Ext Mono Mixer */
860         {"Ext Mono Right Mixer", NULL, "Ext Right Enable"},
861         {"Ext Mono Right Mixer", "Ext Mono Playback Switch", "Ext Left Enable"},
862         {"Ext Mono Left Mixer", NULL, "Ext Left Enable"},
863         {"Ext Mono Left Mixer", "Ext Mono Playback Switch", "Ext Right Enable"},
864 
865         /* HiFi Mono Mixer -> Output Route */
866         {"Earpiece Playback Route", "HiFi", "HiFi Mono Right Mixer"},
867         {"Speaker Right Playback Route", "HiFi", "HiFi Mono Right Mixer"},
868         {"Speaker Left Playback Route", "HiFi", "HiFi Mono Left Mixer"},
869         {"Lineout Right Playback Route", "HiFi", "HiFi Mono Right Mixer"},
870         {"Lineout Left Playback Route", "HiFi", "HiFi Mono Left Mixer"},
871         {"Headset Right Playback Route", "HiFi", "HiFi Mono Right Mixer"},
872         {"Headset Left Playback Route", "HiFi", "HiFi Mono Left Mixer"},
873         {"EMU Right Playback Route", "HiFi", "HiFi Mono Right Mixer"},
874         {"EMU Left Playback Route", "HiFi", "HiFi Mono Left Mixer"},
875 
876         /* Voice PGA -> Output Route */
877         {"Earpiece Playback Route", "Voice", "Voice PGA"},
878         {"Speaker Right Playback Route", "Voice", "Voice PGA"},
879         {"Speaker Left Playback Route", "Voice", "Voice PGA"},
880         {"Lineout Right Playback Route", "Voice", "Voice PGA"},
881         {"Lineout Left Playback Route", "Voice", "Voice PGA"},
882         {"Headset Right Playback Route", "Voice", "Voice PGA"},
883         {"Headset Left Playback Route", "Voice", "Voice PGA"},
884         {"EMU Right Playback Route", "Voice", "Voice PGA"},
885         {"EMU Left Playback Route", "Voice", "Voice PGA"},
886 
887         /* Ext Mono Mixer -> Output Route */
888         {"Earpiece Playback Route", "Ext", "Ext Mono Right Mixer"},
889         {"Speaker Right Playback Route", "Ext", "Ext Mono Right Mixer"},
890         {"Speaker Left Playback Route", "Ext", "Ext Mono Left Mixer"},
891         {"Lineout Right Playback Route", "Ext", "Ext Mono Right Mixer"},
892         {"Lineout Left Playback Route", "Ext", "Ext Mono Left Mixer"},
893         {"Headset Right Playback Route", "Ext", "Ext Mono Right Mixer"},
894         {"Headset Left Playback Route", "Ext", "Ext Mono Left Mixer"},
895         {"EMU Right Playback Route", "Ext", "Ext Mono Right Mixer"},
896         {"EMU Left Playback Route", "Ext", "Ext Mono Left Mixer"},
897 
898         /* Output Route -> Output Amplifier */
899         {"Earpiece PGA", NULL, "Earpiece Playback Route"},
900         {"Speaker Right PGA", NULL, "Speaker Right Playback Route"},
901         {"Speaker Left PGA", NULL, "Speaker Left Playback Route"},
902         {"Lineout Right PGA", NULL, "Lineout Right Playback Route"},
903         {"Lineout Left PGA", NULL, "Lineout Left Playback Route"},
904         {"Headset Right PGA", NULL, "Headset Right Playback Route"},
905         {"Headset Left PGA", NULL, "Headset Left Playback Route"},
906         {"EMU Right PGA", NULL, "EMU Right Playback Route"},
907         {"EMU Left PGA", NULL, "EMU Left Playback Route"},
908 
909         /* Output Amplifier -> Output */
910         {"EP", NULL, "Earpiece PGA"},
911         {"SPKR", NULL, "Speaker Right PGA"},
912         {"SPKL", NULL, "Speaker Left PGA"},
913         {"LINER", NULL, "Lineout Right PGA"},
914         {"LINEL", NULL, "Lineout Left PGA"},
915         {"HSR", NULL, "Headset Right PGA"},
916         {"HSL", NULL, "Headset Left PGA"},
917         {"EMUR", NULL, "EMU Right PGA"},
918         {"EMUL", NULL, "EMU Left PGA"},
919 
920         /* Headset Charge Pump -> Headset */
921         {"HSR", NULL, "Headset Charge Pump"},
922         {"HSL", NULL, "Headset Charge Pump"},
923 
924         /* Mic -> Mic Route */
925         {"Right Capture Route", "Mic 1", "MICR"},
926         {"Right Capture Route", "Headset Mic", "HSMIC"},
927         {"Right Capture Route", "EMU Mic", "EMUMIC"},
928         {"Right Capture Route", "Ext Right", "EXTR"},
929         {"Left Capture Route", "Mic 2", "MICL"},
930         {"Left Capture Route", "Ext Left", "EXTL"},
931 
932         /* Input Route -> Microphone PGA */
933         {"Microphone 1 PGA", NULL, "Right Capture Route"},
934         {"Microphone 2 PGA", NULL, "Left Capture Route"},
935 
936         /* Microphone PGA -> ADC */
937         {"ADC Right", NULL, "Microphone 1 PGA"},
938         {"ADC Left", NULL, "Microphone 2 PGA"},
939 
940         /* ADC -> Stream */
941         {"Highpass Filter TX", NULL, "ADC Right"},
942         {"Highpass Filter TX", NULL, "ADC Left"},
943 
944         /* Mic Bias */
945         {"MICL", NULL, "MIC1L Bias"},
946         {"MICR", NULL, "MIC1R Bias"},
947 };
948 
949 static int cpcap_set_sysclk(struct cpcap_audio *cpcap, enum cpcap_dai dai,
950                             int clk_id, int freq)
951 {
952         u16 clkfreqreg, clkfreqshift;
953         u16 clkfreqmask, clkfreqval;
954         u16 clkidreg, clkidshift;
955         u16 mask, val;
956         int err;
957 
958         switch (dai) {
959         case CPCAP_DAI_HIFI:
960                 clkfreqreg = CPCAP_REG_SDAC;
961                 clkfreqshift = CPCAP_BIT_ST_DAC_CLK0;
962                 clkidreg = CPCAP_REG_SDACDI;
963                 clkidshift = CPCAP_BIT_ST_DAC_CLK_IN_SEL;
964                 break;
965         case CPCAP_DAI_VOICE:
966                 clkfreqreg = CPCAP_REG_CC;
967                 clkfreqshift = CPCAP_BIT_CDC_CLK0;
968                 clkidreg = CPCAP_REG_CDI;
969                 clkidshift = CPCAP_BIT_CLK_IN_SEL;
970                 break;
971         default:
972                 dev_err(cpcap->component->dev, "invalid DAI: %d", dai);
973                 return -EINVAL;
974         }
975 
976         /* setup clk id */
977         if (clk_id < 0 || clk_id > 1) {
978                 dev_err(cpcap->component->dev, "invalid clk id %d", clk_id);
979                 return -EINVAL;
980         }
981         err = regmap_update_bits(cpcap->regmap, clkidreg, BIT(clkidshift),
982                                  clk_id ? BIT(clkidshift) : 0);
983         if (err)
984                 return err;
985 
986         /* enable PLL for Voice DAI */
987         if (dai == CPCAP_DAI_VOICE) {
988                 mask = BIT(CPCAP_BIT_CDC_PLL_SEL);
989                 val = BIT(CPCAP_BIT_CDC_PLL_SEL);
990                 err = regmap_update_bits(cpcap->regmap, CPCAP_REG_CDI,
991                                          mask, val);
992                 if (err)
993                         return err;
994         }
995 
996         /* setup frequency */
997         clkfreqmask = 0x7 << clkfreqshift;
998         switch (freq) {
999         case 15360000:
1000                 clkfreqval = 0x01 << clkfreqshift;
1001                 break;
1002         case 16800000:
1003                 clkfreqval = 0x02 << clkfreqshift;
1004                 break;
1005         case 19200000:
1006                 clkfreqval = 0x03 << clkfreqshift;
1007                 break;
1008         case 26000000:
1009                 clkfreqval = 0x04 << clkfreqshift;
1010                 break;
1011         case 33600000:
1012                 clkfreqval = 0x05 << clkfreqshift;
1013                 break;
1014         case 38400000:
1015                 clkfreqval = 0x06 << clkfreqshift;
1016                 break;
1017         default:
1018                 dev_err(cpcap->component->dev, "unsupported freq %u", freq);
1019                 return -EINVAL;
1020         }
1021 
1022         err = regmap_update_bits(cpcap->regmap, clkfreqreg,
1023                                  clkfreqmask, clkfreqval);
1024         if (err)
1025                 return err;
1026 
1027         if (dai == CPCAP_DAI_VOICE) {
1028                 cpcap->codec_clk_id = clk_id;
1029                 cpcap->codec_freq = freq;
1030         }
1031 
1032         return 0;
1033 }
1034 
1035 static int cpcap_set_samprate(struct cpcap_audio *cpcap, enum cpcap_dai dai,
1036                               int samplerate)
1037 {
1038         struct snd_soc_component *component = cpcap->component;
1039         u16 sampreg, sampmask, sampshift, sampval, sampreset;
1040         int err, sampreadval;
1041 
1042         switch (dai) {
1043         case CPCAP_DAI_HIFI:
1044                 sampreg = CPCAP_REG_SDAC;
1045                 sampshift = CPCAP_BIT_ST_SR0;
1046                 sampreset = BIT(CPCAP_BIT_DF_RESET_ST_DAC) |
1047                             BIT(CPCAP_BIT_ST_CLOCK_TREE_RESET);
1048                 break;
1049         case CPCAP_DAI_VOICE:
1050                 sampreg = CPCAP_REG_CC;
1051                 sampshift = CPCAP_BIT_CDC_SR0;
1052                 sampreset = BIT(CPCAP_BIT_DF_RESET) |
1053                             BIT(CPCAP_BIT_CDC_CLOCK_TREE_RESET);
1054                 break;
1055         default:
1056                 dev_err(component->dev, "invalid DAI: %d", dai);
1057                 return -EINVAL;
1058         }
1059 
1060         sampmask = 0xF << sampshift | sampreset;
1061         switch (samplerate) {
1062         case 48000:
1063                 sampval = 0x8 << sampshift;
1064                 break;
1065         case 44100:
1066                 sampval = 0x7 << sampshift;
1067                 break;
1068         case 32000:
1069                 sampval = 0x6 << sampshift;
1070                 break;
1071         case 24000:
1072                 sampval = 0x5 << sampshift;
1073                 break;
1074         case 22050:
1075                 sampval = 0x4 << sampshift;
1076                 break;
1077         case 16000:
1078                 sampval = 0x3 << sampshift;
1079                 break;
1080         case 12000:
1081                 sampval = 0x2 << sampshift;
1082                 break;
1083         case 11025:
1084                 sampval = 0x1 << sampshift;
1085                 break;
1086         case 8000:
1087                 sampval = 0x0 << sampshift;
1088                 break;
1089         default:
1090                 dev_err(component->dev, "unsupported samplerate %d", samplerate);
1091                 return -EINVAL;
1092         }
1093         err = regmap_update_bits(cpcap->regmap, sampreg,
1094                                  sampmask, sampval | sampreset);
1095         if (err)
1096                 return err;
1097 
1098         /* Wait for clock tree reset to complete */
1099         mdelay(CLOCK_TREE_RESET_TIME);
1100 
1101         err = regmap_read(cpcap->regmap, sampreg, &sampreadval);
1102         if (err)
1103                 return err;
1104 
1105         if (sampreadval & sampreset) {
1106                 dev_err(component->dev, "reset self-clear failed: %04x",
1107                         sampreadval);
1108                 return -EIO;
1109         }
1110 
1111         return 0;
1112 }
1113 
1114 static int cpcap_hifi_hw_params(struct snd_pcm_substream *substream,
1115                                 struct snd_pcm_hw_params *params,
1116                                 struct snd_soc_dai *dai)
1117 {
1118         struct snd_soc_component *component = dai->component;
1119         struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
1120         int rate = params_rate(params);
1121 
1122         dev_dbg(component->dev, "HiFi setup HW params: rate=%d", rate);
1123         return cpcap_set_samprate(cpcap, CPCAP_DAI_HIFI, rate);
1124 }
1125 
1126 static int cpcap_hifi_set_dai_sysclk(struct snd_soc_dai *codec_dai, int clk_id,
1127                                      unsigned int freq, int dir)
1128 {
1129         struct snd_soc_component *component = codec_dai->component;
1130         struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
1131         struct device *dev = component->dev;
1132 
1133         dev_dbg(dev, "HiFi setup sysclk: clk_id=%u, freq=%u", clk_id, freq);
1134         return cpcap_set_sysclk(cpcap, CPCAP_DAI_HIFI, clk_id, freq);
1135 }
1136 
1137 static int cpcap_hifi_set_dai_fmt(struct snd_soc_dai *codec_dai,
1138                                   unsigned int fmt)
1139 {
1140         struct snd_soc_component *component = codec_dai->component;
1141         struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
1142         struct device *dev = component->dev;
1143         static const u16 reg = CPCAP_REG_SDACDI;
1144         static const u16 mask =
1145                 BIT(CPCAP_BIT_SMB_ST_DAC) |
1146                 BIT(CPCAP_BIT_ST_CLK_INV) |
1147                 BIT(CPCAP_BIT_ST_FS_INV) |
1148                 BIT(CPCAP_BIT_ST_DIG_AUD_FS0) |
1149                 BIT(CPCAP_BIT_ST_DIG_AUD_FS1) |
1150                 BIT(CPCAP_BIT_ST_L_TIMESLOT0) |
1151                 BIT(CPCAP_BIT_ST_L_TIMESLOT1) |
1152                 BIT(CPCAP_BIT_ST_L_TIMESLOT2) |
1153                 BIT(CPCAP_BIT_ST_R_TIMESLOT0) |
1154                 BIT(CPCAP_BIT_ST_R_TIMESLOT1) |
1155                 BIT(CPCAP_BIT_ST_R_TIMESLOT2);
1156         u16 val = 0x0000;
1157 
1158         dev_dbg(dev, "HiFi setup dai format (%08x)", fmt);
1159 
1160         /*
1161          * "HiFi Playback" should always be configured as
1162          * SND_SOC_DAIFMT_CBM_CFM - codec clk & frm master
1163          * SND_SOC_DAIFMT_I2S - I2S mode
1164          */
1165         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1166         case SND_SOC_DAIFMT_CBM_CFM:
1167                 val &= ~BIT(CPCAP_BIT_SMB_ST_DAC);
1168                 break;
1169         default:
1170                 dev_err(dev, "HiFi dai fmt failed: CPCAP should be master");
1171                 return -EINVAL;
1172         }
1173 
1174         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1175         case SND_SOC_DAIFMT_IB_IF:
1176                 val |= BIT(CPCAP_BIT_ST_FS_INV);
1177                 val |= BIT(CPCAP_BIT_ST_CLK_INV);
1178                 break;
1179         case SND_SOC_DAIFMT_IB_NF:
1180                 val &= ~BIT(CPCAP_BIT_ST_FS_INV);
1181                 val |= BIT(CPCAP_BIT_ST_CLK_INV);
1182                 break;
1183         case SND_SOC_DAIFMT_NB_IF:
1184                 val |= BIT(CPCAP_BIT_ST_FS_INV);
1185                 val &= ~BIT(CPCAP_BIT_ST_CLK_INV);
1186                 break;
1187         case SND_SOC_DAIFMT_NB_NF:
1188                 val &= ~BIT(CPCAP_BIT_ST_FS_INV);
1189                 val &= ~BIT(CPCAP_BIT_ST_CLK_INV);
1190                 break;
1191         default:
1192                 dev_err(dev, "HiFi dai fmt failed: unsupported clock invert mode");
1193                 return -EINVAL;
1194         }
1195 
1196         if (val & BIT(CPCAP_BIT_ST_CLK_INV))
1197                 val &= ~BIT(CPCAP_BIT_ST_CLK_INV);
1198         else
1199                 val |= BIT(CPCAP_BIT_ST_CLK_INV);
1200 
1201         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1202         case SND_SOC_DAIFMT_I2S:
1203                 val |= BIT(CPCAP_BIT_ST_DIG_AUD_FS0);
1204                 val |= BIT(CPCAP_BIT_ST_DIG_AUD_FS1);
1205                 break;
1206         default:
1207                 /* 01 - 4 slots network mode */
1208                 val |= BIT(CPCAP_BIT_ST_DIG_AUD_FS0);
1209                 val &= ~BIT(CPCAP_BIT_ST_DIG_AUD_FS1);
1210                 /* L on slot 1 */
1211                 val |= BIT(CPCAP_BIT_ST_L_TIMESLOT0);
1212                 break;
1213         }
1214 
1215         dev_dbg(dev, "HiFi dai format: val=%04x", val);
1216         return regmap_update_bits(cpcap->regmap, reg, mask, val);
1217 }
1218 
1219 static int cpcap_hifi_set_mute(struct snd_soc_dai *dai, int mute)
1220 {
1221         struct snd_soc_component *component = dai->component;
1222         struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
1223         static const u16 reg = CPCAP_REG_RXSDOA;
1224         static const u16 mask = BIT(CPCAP_BIT_ST_DAC_SW);
1225         u16 val;
1226 
1227         if (mute)
1228                 val = 0;
1229         else
1230                 val = BIT(CPCAP_BIT_ST_DAC_SW);
1231 
1232         dev_dbg(component->dev, "HiFi mute: %d", mute);
1233         return regmap_update_bits(cpcap->regmap, reg, mask, val);
1234 }
1235 
1236 static const struct snd_soc_dai_ops cpcap_dai_hifi_ops = {
1237         .hw_params      = cpcap_hifi_hw_params,
1238         .set_sysclk     = cpcap_hifi_set_dai_sysclk,
1239         .set_fmt        = cpcap_hifi_set_dai_fmt,
1240         .digital_mute   = cpcap_hifi_set_mute,
1241 };
1242 
1243 static int cpcap_voice_hw_params(struct snd_pcm_substream *substream,
1244                                  struct snd_pcm_hw_params *params,
1245                                  struct snd_soc_dai *dai)
1246 {
1247         struct snd_soc_component *component = dai->component;
1248         struct device *dev = component->dev;
1249         struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
1250         static const u16 reg_cdi = CPCAP_REG_CDI;
1251         int rate = params_rate(params);
1252         int channels = params_channels(params);
1253         int direction = substream->stream;
1254         u16 val, mask;
1255         int err;
1256 
1257         dev_dbg(dev, "Voice setup HW params: rate=%d, direction=%d, chan=%d",
1258                 rate, direction, channels);
1259 
1260         err = cpcap_set_samprate(cpcap, CPCAP_DAI_VOICE, rate);
1261         if (err)
1262                 return err;
1263 
1264         if (direction == SNDRV_PCM_STREAM_CAPTURE) {
1265                 mask = 0x0000;
1266                 mask |= CPCAP_BIT_MIC1_RX_TIMESLOT0;
1267                 mask |= CPCAP_BIT_MIC1_RX_TIMESLOT1;
1268                 mask |= CPCAP_BIT_MIC1_RX_TIMESLOT2;
1269                 mask |= CPCAP_BIT_MIC2_TIMESLOT0;
1270                 mask |= CPCAP_BIT_MIC2_TIMESLOT1;
1271                 mask |= CPCAP_BIT_MIC2_TIMESLOT2;
1272                 val = 0x0000;
1273                 if (channels >= 2)
1274                         val = BIT(CPCAP_BIT_MIC1_RX_TIMESLOT0);
1275                 err = regmap_update_bits(cpcap->regmap, reg_cdi, mask, val);
1276                 if (err)
1277                         return err;
1278         }
1279 
1280         return 0;
1281 }
1282 
1283 static int cpcap_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai, int clk_id,
1284                                       unsigned int freq, int dir)
1285 {
1286         struct snd_soc_component *component = codec_dai->component;
1287         struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
1288 
1289         dev_dbg(component->dev, "Voice setup sysclk: clk_id=%u, freq=%u",
1290                 clk_id, freq);
1291         return cpcap_set_sysclk(cpcap, CPCAP_DAI_VOICE, clk_id, freq);
1292 }
1293 
1294 static int cpcap_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
1295                                    unsigned int fmt)
1296 {
1297         struct snd_soc_component *component = codec_dai->component;
1298         struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
1299         static const u16 mask = BIT(CPCAP_BIT_SMB_CDC) |
1300                                 BIT(CPCAP_BIT_CLK_INV) |
1301                                 BIT(CPCAP_BIT_FS_INV) |
1302                                 BIT(CPCAP_BIT_CDC_DIG_AUD_FS0) |
1303                                 BIT(CPCAP_BIT_CDC_DIG_AUD_FS1);
1304         u16 val = 0x0000;
1305         int err;
1306 
1307         dev_dbg(component->dev, "Voice setup dai format (%08x)", fmt);
1308 
1309         /*
1310          * "Voice Playback" and "Voice Capture" should always be
1311          * configured as SND_SOC_DAIFMT_CBM_CFM - codec clk & frm
1312          * master
1313          */
1314         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1315         case SND_SOC_DAIFMT_CBM_CFM:
1316                 val &= ~BIT(CPCAP_BIT_SMB_CDC);
1317                 break;
1318         default:
1319                 dev_err(component->dev, "Voice dai fmt failed: CPCAP should be the master");
1320                 val &= ~BIT(CPCAP_BIT_SMB_CDC);
1321                 break;
1322         }
1323 
1324         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1325         case SND_SOC_DAIFMT_IB_IF:
1326                 val |= BIT(CPCAP_BIT_CLK_INV);
1327                 val |= BIT(CPCAP_BIT_FS_INV);
1328                 break;
1329         case SND_SOC_DAIFMT_IB_NF:
1330                 val |= BIT(CPCAP_BIT_CLK_INV);
1331                 val &= ~BIT(CPCAP_BIT_FS_INV);
1332                 break;
1333         case SND_SOC_DAIFMT_NB_IF:
1334                 val &= ~BIT(CPCAP_BIT_CLK_INV);
1335                 val |= BIT(CPCAP_BIT_FS_INV);
1336                 break;
1337         case SND_SOC_DAIFMT_NB_NF:
1338                 val &= ~BIT(CPCAP_BIT_CLK_INV);
1339                 val &= ~BIT(CPCAP_BIT_FS_INV);
1340                 break;
1341         default:
1342                 dev_err(component->dev, "Voice dai fmt failed: unsupported clock invert mode");
1343                 break;
1344         }
1345 
1346         if (val & BIT(CPCAP_BIT_CLK_INV))
1347                 val &= ~BIT(CPCAP_BIT_CLK_INV);
1348         else
1349                 val |= BIT(CPCAP_BIT_CLK_INV);
1350 
1351         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1352         case SND_SOC_DAIFMT_I2S:
1353                 /* 11 - true I2S mode */
1354                 val |= BIT(CPCAP_BIT_CDC_DIG_AUD_FS0);
1355                 val |= BIT(CPCAP_BIT_CDC_DIG_AUD_FS1);
1356                 break;
1357         default:
1358                 /* 4 timeslots network mode */
1359                 val |= BIT(CPCAP_BIT_CDC_DIG_AUD_FS0);
1360                 val &= ~BIT(CPCAP_BIT_CDC_DIG_AUD_FS1);
1361                 break;
1362         }
1363 
1364         dev_dbg(component->dev, "Voice dai format: val=%04x", val);
1365         err = regmap_update_bits(cpcap->regmap, CPCAP_REG_CDI, mask, val);
1366         if (err)
1367                 return err;
1368 
1369         cpcap->codec_format = val;
1370         return 0;
1371 }
1372 
1373 static int cpcap_voice_set_mute(struct snd_soc_dai *dai, int mute)
1374 {
1375         struct snd_soc_component *component = dai->component;
1376         struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
1377         static const u16 reg = CPCAP_REG_RXCOA;
1378         static const u16 mask = BIT(CPCAP_BIT_CDC_SW);
1379         u16 val;
1380 
1381         if (mute)
1382                 val = 0;
1383         else
1384                 val = BIT(CPCAP_BIT_CDC_SW);
1385 
1386         dev_dbg(component->dev, "Voice mute: %d", mute);
1387         return regmap_update_bits(cpcap->regmap, reg, mask, val);
1388 };
1389 
1390 static const struct snd_soc_dai_ops cpcap_dai_voice_ops = {
1391         .hw_params      = cpcap_voice_hw_params,
1392         .set_sysclk     = cpcap_voice_set_dai_sysclk,
1393         .set_fmt        = cpcap_voice_set_dai_fmt,
1394         .digital_mute   = cpcap_voice_set_mute,
1395 };
1396 
1397 static struct snd_soc_dai_driver cpcap_dai[] = {
1398 {
1399         .id = 0,
1400         .name = "cpcap-hifi",
1401         .playback = {
1402                 .stream_name = "HiFi Playback",
1403                 .channels_min = 2,
1404                 .channels_max = 2,
1405                 .rates = SNDRV_PCM_RATE_8000_48000,
1406                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE,
1407         },
1408         .ops = &cpcap_dai_hifi_ops,
1409 },
1410 {
1411         .id = 1,
1412         .name = "cpcap-voice",
1413         .playback = {
1414                 .stream_name = "Voice Playback",
1415                 .channels_min = 1,
1416                 .channels_max = 1,
1417                 .rates = SNDRV_PCM_RATE_8000_48000,
1418                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1419         },
1420         .capture = {
1421                 .stream_name = "Voice Capture",
1422                 .channels_min = 1,
1423                 .channels_max = 2,
1424                 .rates = SNDRV_PCM_RATE_8000_48000,
1425                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1426         },
1427         .ops = &cpcap_dai_voice_ops,
1428 },
1429 };
1430 
1431 static int cpcap_dai_mux(struct cpcap_audio *cpcap, bool swap_dai_configuration)
1432 {
1433         u16 hifi_val, voice_val;
1434         u16 hifi_mask = BIT(CPCAP_BIT_DIG_AUD_IN_ST_DAC);
1435         u16 voice_mask = BIT(CPCAP_BIT_DIG_AUD_IN);
1436         int err;
1437 
1438 
1439 
1440         if (!swap_dai_configuration) {
1441                 /* Codec on DAI0, HiFi on DAI1 */
1442                 voice_val = 0;
1443                 hifi_val = hifi_mask;
1444         } else {
1445                 /* Codec on DAI1, HiFi on DAI0 */
1446                 voice_val = voice_mask;
1447                 hifi_val = 0;
1448         }
1449 
1450         err = regmap_update_bits(cpcap->regmap, CPCAP_REG_CDI,
1451                                  voice_mask, voice_val);
1452         if (err)
1453                 return err;
1454 
1455         err = regmap_update_bits(cpcap->regmap, CPCAP_REG_SDACDI,
1456                                  hifi_mask, hifi_val);
1457         if (err)
1458                 return err;
1459 
1460         return 0;
1461 }
1462 
1463 static int cpcap_audio_reset(struct snd_soc_component *component,
1464                              bool swap_dai_configuration)
1465 {
1466         struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
1467         int i, err = 0;
1468 
1469         dev_dbg(component->dev, "init audio codec");
1470 
1471         for (i = 0; i < ARRAY_SIZE(cpcap_default_regs); i++) {
1472                 err = regmap_update_bits(cpcap->regmap,
1473                                          cpcap_default_regs[i].reg,
1474                                          cpcap_default_regs[i].mask,
1475                                          cpcap_default_regs[i].val);
1476                 if (err)
1477                         return err;
1478         }
1479 
1480         /* setup default settings */
1481         err = cpcap_dai_mux(cpcap, swap_dai_configuration);
1482         if (err)
1483                 return err;
1484 
1485         err = cpcap_set_sysclk(cpcap, CPCAP_DAI_HIFI, 0, 26000000);
1486         if (err)
1487                 return err;
1488         err = cpcap_set_sysclk(cpcap, CPCAP_DAI_VOICE, 0, 26000000);
1489         if (err)
1490                 return err;
1491 
1492         err = cpcap_set_samprate(cpcap, CPCAP_DAI_HIFI, 48000);
1493         if (err)
1494                 return err;
1495 
1496         err = cpcap_set_samprate(cpcap, CPCAP_DAI_VOICE, 48000);
1497         if (err)
1498                 return err;
1499 
1500         return 0;
1501 }
1502 
1503 static int cpcap_soc_probe(struct snd_soc_component *component)
1504 {
1505         struct cpcap_audio *cpcap;
1506         int err;
1507 
1508         cpcap = devm_kzalloc(component->dev, sizeof(*cpcap), GFP_KERNEL);
1509         if (!cpcap)
1510                 return -ENOMEM;
1511         snd_soc_component_set_drvdata(component, cpcap);
1512         cpcap->component = component;
1513 
1514         cpcap->regmap = dev_get_regmap(component->dev->parent, NULL);
1515         if (!cpcap->regmap)
1516                 return -ENODEV;
1517         snd_soc_component_init_regmap(component, cpcap->regmap);
1518 
1519         err = cpcap_get_vendor(component->dev, cpcap->regmap, &cpcap->vendor);
1520         if (err)
1521                 return err;
1522 
1523         return cpcap_audio_reset(component, false);
1524 }
1525 
1526 static struct snd_soc_component_driver soc_codec_dev_cpcap = {
1527         .probe                  = cpcap_soc_probe,
1528         .controls               = cpcap_snd_controls,
1529         .num_controls           = ARRAY_SIZE(cpcap_snd_controls),
1530         .dapm_widgets           = cpcap_dapm_widgets,
1531         .num_dapm_widgets       = ARRAY_SIZE(cpcap_dapm_widgets),
1532         .dapm_routes            = intercon,
1533         .num_dapm_routes        = ARRAY_SIZE(intercon),
1534         .idle_bias_on           = 1,
1535         .use_pmdown_time        = 1,
1536         .endianness             = 1,
1537         .non_legacy_dai_naming  = 1,
1538 };
1539 
1540 static int cpcap_codec_probe(struct platform_device *pdev)
1541 {
1542         struct device_node *codec_node =
1543                 of_get_child_by_name(pdev->dev.parent->of_node, "audio-codec");
1544 
1545         pdev->dev.of_node = codec_node;
1546 
1547         return devm_snd_soc_register_component(&pdev->dev, &soc_codec_dev_cpcap,
1548                                       cpcap_dai, ARRAY_SIZE(cpcap_dai));
1549 }
1550 
1551 static struct platform_driver cpcap_codec_driver = {
1552         .probe          = cpcap_codec_probe,
1553         .driver         = {
1554                 .name   = "cpcap-codec",
1555         },
1556 };
1557 module_platform_driver(cpcap_codec_driver);
1558 
1559 MODULE_ALIAS("platform:cpcap-codec");
1560 MODULE_DESCRIPTION("ASoC CPCAP codec driver");
1561 MODULE_AUTHOR("Sebastian Reichel");
1562 MODULE_LICENSE("GPL v2");
1563 

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