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Linux/sound/soc/codecs/cs35l33.c

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  1 // SPDX-License-Identifier: GPL-2.0-only
  2 /*
  3  * cs35l33.c -- CS35L33 ALSA SoC audio driver
  4  *
  5  * Copyright 2016 Cirrus Logic, Inc.
  6  *
  7  * Author: Paul Handrigan <paul.handrigan@cirrus.com>
  8  */
  9 #include <linux/module.h>
 10 #include <linux/moduleparam.h>
 11 #include <linux/kernel.h>
 12 #include <linux/init.h>
 13 #include <linux/delay.h>
 14 #include <linux/i2c.h>
 15 #include <linux/slab.h>
 16 #include <linux/workqueue.h>
 17 #include <linux/platform_device.h>
 18 #include <sound/core.h>
 19 #include <sound/pcm.h>
 20 #include <sound/pcm_params.h>
 21 #include <sound/soc.h>
 22 #include <sound/soc-dapm.h>
 23 #include <sound/initval.h>
 24 #include <sound/tlv.h>
 25 #include <linux/gpio.h>
 26 #include <linux/gpio/consumer.h>
 27 #include <sound/cs35l33.h>
 28 #include <linux/pm_runtime.h>
 29 #include <linux/regulator/consumer.h>
 30 #include <linux/regulator/machine.h>
 31 #include <linux/of_gpio.h>
 32 #include <linux/of.h>
 33 #include <linux/of_device.h>
 34 #include <linux/of_irq.h>
 35 
 36 #include "cs35l33.h"
 37 
 38 #define CS35L33_BOOT_DELAY      50
 39 
 40 struct cs35l33_private {
 41         struct snd_soc_component *component;
 42         struct cs35l33_pdata pdata;
 43         struct regmap *regmap;
 44         struct gpio_desc *reset_gpio;
 45         bool amp_cal;
 46         int mclk_int;
 47         struct regulator_bulk_data core_supplies[2];
 48         int num_core_supplies;
 49         bool is_tdm_mode;
 50         bool enable_soft_ramp;
 51 };
 52 
 53 static const struct reg_default cs35l33_reg[] = {
 54         {CS35L33_PWRCTL1, 0x85},
 55         {CS35L33_PWRCTL2, 0xFE},
 56         {CS35L33_CLK_CTL, 0x0C},
 57         {CS35L33_BST_PEAK_CTL, 0x90},
 58         {CS35L33_PROTECT_CTL, 0x55},
 59         {CS35L33_BST_CTL1, 0x00},
 60         {CS35L33_BST_CTL2, 0x01},
 61         {CS35L33_ADSP_CTL, 0x00},
 62         {CS35L33_ADC_CTL, 0xC8},
 63         {CS35L33_DAC_CTL, 0x14},
 64         {CS35L33_DIG_VOL_CTL, 0x00},
 65         {CS35L33_CLASSD_CTL, 0x04},
 66         {CS35L33_AMP_CTL, 0x90},
 67         {CS35L33_INT_MASK_1, 0xFF},
 68         {CS35L33_INT_MASK_2, 0xFF},
 69         {CS35L33_DIAG_LOCK, 0x00},
 70         {CS35L33_DIAG_CTRL_1, 0x40},
 71         {CS35L33_DIAG_CTRL_2, 0x00},
 72         {CS35L33_HG_MEMLDO_CTL, 0x62},
 73         {CS35L33_HG_REL_RATE, 0x03},
 74         {CS35L33_LDO_DEL, 0x12},
 75         {CS35L33_HG_HEAD, 0x0A},
 76         {CS35L33_HG_EN, 0x05},
 77         {CS35L33_TX_VMON, 0x00},
 78         {CS35L33_TX_IMON, 0x03},
 79         {CS35L33_TX_VPMON, 0x02},
 80         {CS35L33_TX_VBSTMON, 0x05},
 81         {CS35L33_TX_FLAG, 0x06},
 82         {CS35L33_TX_EN1, 0x00},
 83         {CS35L33_TX_EN2, 0x00},
 84         {CS35L33_TX_EN3, 0x00},
 85         {CS35L33_TX_EN4, 0x00},
 86         {CS35L33_RX_AUD, 0x40},
 87         {CS35L33_RX_SPLY, 0x03},
 88         {CS35L33_RX_ALIVE, 0x04},
 89         {CS35L33_BST_CTL4, 0x63},
 90 };
 91 
 92 static const struct reg_sequence cs35l33_patch[] = {
 93         { 0x00,  0x99, 0 },
 94         { 0x59,  0x02, 0 },
 95         { 0x52,  0x30, 0 },
 96         { 0x39,  0x45, 0 },
 97         { 0x57,  0x30, 0 },
 98         { 0x2C,  0x68, 0 },
 99         { 0x00,  0x00, 0 },
100 };
101 
102 static bool cs35l33_volatile_register(struct device *dev, unsigned int reg)
103 {
104         switch (reg) {
105         case CS35L33_DEVID_AB:
106         case CS35L33_DEVID_CD:
107         case CS35L33_DEVID_E:
108         case CS35L33_REV_ID:
109         case CS35L33_INT_STATUS_1:
110         case CS35L33_INT_STATUS_2:
111         case CS35L33_HG_STATUS:
112                 return true;
113         default:
114                 return false;
115         }
116 }
117 
118 static bool cs35l33_writeable_register(struct device *dev, unsigned int reg)
119 {
120         switch (reg) {
121         /* these are read only registers */
122         case CS35L33_DEVID_AB:
123         case CS35L33_DEVID_CD:
124         case CS35L33_DEVID_E:
125         case CS35L33_REV_ID:
126         case CS35L33_INT_STATUS_1:
127         case CS35L33_INT_STATUS_2:
128         case CS35L33_HG_STATUS:
129                 return false;
130         default:
131                 return true;
132         }
133 }
134 
135 static bool cs35l33_readable_register(struct device *dev, unsigned int reg)
136 {
137         switch (reg) {
138         case CS35L33_DEVID_AB:
139         case CS35L33_DEVID_CD:
140         case CS35L33_DEVID_E:
141         case CS35L33_REV_ID:
142         case CS35L33_PWRCTL1:
143         case CS35L33_PWRCTL2:
144         case CS35L33_CLK_CTL:
145         case CS35L33_BST_PEAK_CTL:
146         case CS35L33_PROTECT_CTL:
147         case CS35L33_BST_CTL1:
148         case CS35L33_BST_CTL2:
149         case CS35L33_ADSP_CTL:
150         case CS35L33_ADC_CTL:
151         case CS35L33_DAC_CTL:
152         case CS35L33_DIG_VOL_CTL:
153         case CS35L33_CLASSD_CTL:
154         case CS35L33_AMP_CTL:
155         case CS35L33_INT_MASK_1:
156         case CS35L33_INT_MASK_2:
157         case CS35L33_INT_STATUS_1:
158         case CS35L33_INT_STATUS_2:
159         case CS35L33_DIAG_LOCK:
160         case CS35L33_DIAG_CTRL_1:
161         case CS35L33_DIAG_CTRL_2:
162         case CS35L33_HG_MEMLDO_CTL:
163         case CS35L33_HG_REL_RATE:
164         case CS35L33_LDO_DEL:
165         case CS35L33_HG_HEAD:
166         case CS35L33_HG_EN:
167         case CS35L33_TX_VMON:
168         case CS35L33_TX_IMON:
169         case CS35L33_TX_VPMON:
170         case CS35L33_TX_VBSTMON:
171         case CS35L33_TX_FLAG:
172         case CS35L33_TX_EN1:
173         case CS35L33_TX_EN2:
174         case CS35L33_TX_EN3:
175         case CS35L33_TX_EN4:
176         case CS35L33_RX_AUD:
177         case CS35L33_RX_SPLY:
178         case CS35L33_RX_ALIVE:
179         case CS35L33_BST_CTL4:
180                 return true;
181         default:
182                 return false;
183         }
184 }
185 
186 static DECLARE_TLV_DB_SCALE(classd_ctl_tlv, 900, 100, 0);
187 static DECLARE_TLV_DB_SCALE(dac_tlv, -10200, 50, 0);
188 
189 static const struct snd_kcontrol_new cs35l33_snd_controls[] = {
190 
191         SOC_SINGLE_TLV("SPK Amp Volume", CS35L33_AMP_CTL,
192                        4, 0x09, 0, classd_ctl_tlv),
193         SOC_SINGLE_SX_TLV("DAC Volume", CS35L33_DIG_VOL_CTL,
194                         0, 0x34, 0xE4, dac_tlv),
195 };
196 
197 static int cs35l33_spkrdrv_event(struct snd_soc_dapm_widget *w,
198         struct snd_kcontrol *kcontrol, int event)
199 {
200         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
201         struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
202 
203         switch (event) {
204         case SND_SOC_DAPM_POST_PMU:
205                 if (!priv->amp_cal) {
206                         usleep_range(8000, 9000);
207                         priv->amp_cal = true;
208                         regmap_update_bits(priv->regmap, CS35L33_CLASSD_CTL,
209                                     CS35L33_AMP_CAL, 0);
210                         dev_dbg(component->dev, "Amp calibration done\n");
211                 }
212                 dev_dbg(component->dev, "Amp turned on\n");
213                 break;
214         case SND_SOC_DAPM_POST_PMD:
215                 dev_dbg(component->dev, "Amp turned off\n");
216                 break;
217         default:
218                 dev_err(component->dev, "Invalid event = 0x%x\n", event);
219                 break;
220         }
221 
222         return 0;
223 }
224 
225 static int cs35l33_sdin_event(struct snd_soc_dapm_widget *w,
226         struct snd_kcontrol *kcontrol, int event)
227 {
228         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
229         struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
230         unsigned int val;
231 
232         switch (event) {
233         case SND_SOC_DAPM_PRE_PMU:
234                 regmap_update_bits(priv->regmap, CS35L33_PWRCTL1,
235                                     CS35L33_PDN_BST, 0);
236                 val = priv->is_tdm_mode ? 0 : CS35L33_PDN_TDM;
237                 regmap_update_bits(priv->regmap, CS35L33_PWRCTL2,
238                                     CS35L33_PDN_TDM, val);
239                 dev_dbg(component->dev, "BST turned on\n");
240                 break;
241         case SND_SOC_DAPM_POST_PMU:
242                 dev_dbg(component->dev, "SDIN turned on\n");
243                 if (!priv->amp_cal) {
244                         regmap_update_bits(priv->regmap, CS35L33_CLASSD_CTL,
245                                     CS35L33_AMP_CAL, CS35L33_AMP_CAL);
246                         dev_dbg(component->dev, "Amp calibration started\n");
247                         usleep_range(10000, 11000);
248                 }
249                 break;
250         case SND_SOC_DAPM_POST_PMD:
251                 regmap_update_bits(priv->regmap, CS35L33_PWRCTL2,
252                                     CS35L33_PDN_TDM, CS35L33_PDN_TDM);
253                 usleep_range(4000, 4100);
254                 regmap_update_bits(priv->regmap, CS35L33_PWRCTL1,
255                                     CS35L33_PDN_BST, CS35L33_PDN_BST);
256                 dev_dbg(component->dev, "BST and SDIN turned off\n");
257                 break;
258         default:
259                 dev_err(component->dev, "Invalid event = 0x%x\n", event);
260 
261         }
262 
263         return 0;
264 }
265 
266 static int cs35l33_sdout_event(struct snd_soc_dapm_widget *w,
267         struct snd_kcontrol *kcontrol, int event)
268 {
269         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
270         struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
271         unsigned int mask = CS35L33_SDOUT_3ST_I2S | CS35L33_PDN_TDM;
272         unsigned int mask2 = CS35L33_SDOUT_3ST_TDM;
273         unsigned int val, val2;
274 
275         switch (event) {
276         case SND_SOC_DAPM_PRE_PMU:
277                 if (priv->is_tdm_mode) {
278                         /* set sdout_3st_i2s and reset pdn_tdm */
279                         val = CS35L33_SDOUT_3ST_I2S;
280                         /* reset sdout_3st_tdm */
281                         val2 = 0;
282                 } else {
283                         /* reset sdout_3st_i2s and set pdn_tdm */
284                         val = CS35L33_PDN_TDM;
285                         /* set sdout_3st_tdm */
286                         val2 = CS35L33_SDOUT_3ST_TDM;
287                 }
288                 dev_dbg(component->dev, "SDOUT turned on\n");
289                 break;
290         case SND_SOC_DAPM_PRE_PMD:
291                 val = CS35L33_SDOUT_3ST_I2S | CS35L33_PDN_TDM;
292                 val2 = CS35L33_SDOUT_3ST_TDM;
293                 dev_dbg(component->dev, "SDOUT turned off\n");
294                 break;
295         default:
296                 dev_err(component->dev, "Invalid event = 0x%x\n", event);
297                 return 0;
298         }
299 
300         regmap_update_bits(priv->regmap, CS35L33_PWRCTL2,
301                 mask, val);
302         regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
303                 mask2, val2);
304 
305         return 0;
306 }
307 
308 static const struct snd_soc_dapm_widget cs35l33_dapm_widgets[] = {
309 
310         SND_SOC_DAPM_OUTPUT("SPK"),
311         SND_SOC_DAPM_OUT_DRV_E("SPKDRV", CS35L33_PWRCTL1, 7, 1, NULL, 0,
312                 cs35l33_spkrdrv_event,
313                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
314         SND_SOC_DAPM_AIF_IN_E("SDIN", NULL, 0, CS35L33_PWRCTL2,
315                 2, 1, cs35l33_sdin_event, SND_SOC_DAPM_PRE_PMU |
316                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
317 
318         SND_SOC_DAPM_INPUT("MON"),
319 
320         SND_SOC_DAPM_ADC("VMON", NULL,
321                 CS35L33_PWRCTL2, CS35L33_PDN_VMON_SHIFT, 1),
322         SND_SOC_DAPM_ADC("IMON", NULL,
323                 CS35L33_PWRCTL2, CS35L33_PDN_IMON_SHIFT, 1),
324         SND_SOC_DAPM_ADC("VPMON", NULL,
325                 CS35L33_PWRCTL2, CS35L33_PDN_VPMON_SHIFT, 1),
326         SND_SOC_DAPM_ADC("VBSTMON", NULL,
327                 CS35L33_PWRCTL2, CS35L33_PDN_VBSTMON_SHIFT, 1),
328 
329         SND_SOC_DAPM_AIF_OUT_E("SDOUT", NULL, 0, SND_SOC_NOPM, 0, 0,
330                 cs35l33_sdout_event, SND_SOC_DAPM_PRE_PMU |
331                 SND_SOC_DAPM_PRE_PMD),
332 };
333 
334 static const struct snd_soc_dapm_route cs35l33_audio_map[] = {
335         {"SDIN", NULL, "CS35L33 Playback"},
336         {"SPKDRV", NULL, "SDIN"},
337         {"SPK", NULL, "SPKDRV"},
338 
339         {"VMON", NULL, "MON"},
340         {"IMON", NULL, "MON"},
341 
342         {"SDOUT", NULL, "VMON"},
343         {"SDOUT", NULL, "IMON"},
344         {"CS35L33 Capture", NULL, "SDOUT"},
345 };
346 
347 static const struct snd_soc_dapm_route cs35l33_vphg_auto_route[] = {
348         {"SPKDRV", NULL, "VPMON"},
349         {"VPMON", NULL, "CS35L33 Playback"},
350 };
351 
352 static const struct snd_soc_dapm_route cs35l33_vp_vbst_mon_route[] = {
353         {"SDOUT", NULL, "VPMON"},
354         {"VPMON", NULL, "MON"},
355         {"SDOUT", NULL, "VBSTMON"},
356         {"VBSTMON", NULL, "MON"},
357 };
358 
359 static int cs35l33_set_bias_level(struct snd_soc_component *component,
360                                   enum snd_soc_bias_level level)
361 {
362         unsigned int val;
363         struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
364 
365         switch (level) {
366         case SND_SOC_BIAS_ON:
367                 break;
368         case SND_SOC_BIAS_PREPARE:
369                 regmap_update_bits(priv->regmap, CS35L33_PWRCTL1,
370                                     CS35L33_PDN_ALL, 0);
371                 regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
372                                     CS35L33_MCLKDIS, 0);
373                 break;
374         case SND_SOC_BIAS_STANDBY:
375                 regmap_update_bits(priv->regmap, CS35L33_PWRCTL1,
376                                     CS35L33_PDN_ALL, CS35L33_PDN_ALL);
377                 regmap_read(priv->regmap, CS35L33_INT_STATUS_2, &val);
378                 usleep_range(1000, 1100);
379                 if (val & CS35L33_PDN_DONE)
380                         regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
381                                             CS35L33_MCLKDIS, CS35L33_MCLKDIS);
382                 break;
383         case SND_SOC_BIAS_OFF:
384                 break;
385         default:
386                 return -EINVAL;
387         }
388 
389         return 0;
390 }
391 
392 struct cs35l33_mclk_div {
393         int mclk;
394         int srate;
395         u8 adsp_rate;
396         u8 int_fs_ratio;
397 };
398 
399 static const struct cs35l33_mclk_div cs35l33_mclk_coeffs[] = {
400         /* MCLK, Sample Rate, adsp_rate, int_fs_ratio */
401         {5644800, 11025, 0x4, CS35L33_INT_FS_RATE},
402         {5644800, 22050, 0x8, CS35L33_INT_FS_RATE},
403         {5644800, 44100, 0xC, CS35L33_INT_FS_RATE},
404 
405         {6000000,  8000, 0x1, 0},
406         {6000000, 11025, 0x2, 0},
407         {6000000, 11029, 0x3, 0},
408         {6000000, 12000, 0x4, 0},
409         {6000000, 16000, 0x5, 0},
410         {6000000, 22050, 0x6, 0},
411         {6000000, 22059, 0x7, 0},
412         {6000000, 24000, 0x8, 0},
413         {6000000, 32000, 0x9, 0},
414         {6000000, 44100, 0xA, 0},
415         {6000000, 44118, 0xB, 0},
416         {6000000, 48000, 0xC, 0},
417 
418         {6144000,  8000, 0x1, CS35L33_INT_FS_RATE},
419         {6144000, 12000, 0x4, CS35L33_INT_FS_RATE},
420         {6144000, 16000, 0x5, CS35L33_INT_FS_RATE},
421         {6144000, 24000, 0x8, CS35L33_INT_FS_RATE},
422         {6144000, 32000, 0x9, CS35L33_INT_FS_RATE},
423         {6144000, 48000, 0xC, CS35L33_INT_FS_RATE},
424 };
425 
426 static int cs35l33_get_mclk_coeff(int mclk, int srate)
427 {
428         int i;
429 
430         for (i = 0; i < ARRAY_SIZE(cs35l33_mclk_coeffs); i++) {
431                 if (cs35l33_mclk_coeffs[i].mclk == mclk &&
432                         cs35l33_mclk_coeffs[i].srate == srate)
433                         return i;
434         }
435         return -EINVAL;
436 }
437 
438 static int cs35l33_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
439 {
440         struct snd_soc_component *component = codec_dai->component;
441         struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
442 
443         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
444         case SND_SOC_DAIFMT_CBM_CFM:
445                 regmap_update_bits(priv->regmap, CS35L33_ADSP_CTL,
446                         CS35L33_MS_MASK, CS35L33_MS_MASK);
447                 dev_dbg(component->dev, "Audio port in master mode\n");
448                 break;
449         case SND_SOC_DAIFMT_CBS_CFS:
450                 regmap_update_bits(priv->regmap, CS35L33_ADSP_CTL,
451                         CS35L33_MS_MASK, 0);
452                 dev_dbg(component->dev, "Audio port in slave mode\n");
453                 break;
454         default:
455                 return -EINVAL;
456         }
457 
458         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
459         case SND_SOC_DAIFMT_DSP_A:
460                 /*
461                  * tdm mode in cs35l33 resembles dsp-a mode very
462                  * closely, it is dsp-a with fsync shifted left by half bclk
463                  */
464                 priv->is_tdm_mode = true;
465                 dev_dbg(component->dev, "Audio port in TDM mode\n");
466                 break;
467         case SND_SOC_DAIFMT_I2S:
468                 priv->is_tdm_mode = false;
469                 dev_dbg(component->dev, "Audio port in I2S mode\n");
470                 break;
471         default:
472                 return -EINVAL;
473         }
474 
475         return 0;
476 }
477 
478 static int cs35l33_pcm_hw_params(struct snd_pcm_substream *substream,
479                                  struct snd_pcm_hw_params *params,
480                                  struct snd_soc_dai *dai)
481 {
482         struct snd_soc_component *component = dai->component;
483         struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
484         int sample_size = params_width(params);
485         int coeff = cs35l33_get_mclk_coeff(priv->mclk_int, params_rate(params));
486 
487         if (coeff < 0)
488                 return coeff;
489 
490         regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
491                 CS35L33_ADSP_FS | CS35L33_INT_FS_RATE,
492                 cs35l33_mclk_coeffs[coeff].int_fs_ratio
493                 | cs35l33_mclk_coeffs[coeff].adsp_rate);
494 
495         if (priv->is_tdm_mode) {
496                 sample_size = (sample_size / 8) - 1;
497                 if (sample_size > 2)
498                         sample_size = 2;
499                 regmap_update_bits(priv->regmap, CS35L33_RX_AUD,
500                         CS35L33_AUDIN_RX_DEPTH,
501                         sample_size << CS35L33_AUDIN_RX_DEPTH_SHIFT);
502         }
503 
504         dev_dbg(component->dev, "sample rate=%d, bits per sample=%d\n",
505                 params_rate(params), params_width(params));
506 
507         return 0;
508 }
509 
510 static const unsigned int cs35l33_src_rates[] = {
511         8000, 11025, 11029, 12000, 16000, 22050,
512         22059, 24000, 32000, 44100, 44118, 48000
513 };
514 
515 static const struct snd_pcm_hw_constraint_list cs35l33_constraints = {
516         .count  = ARRAY_SIZE(cs35l33_src_rates),
517         .list   = cs35l33_src_rates,
518 };
519 
520 static int cs35l33_pcm_startup(struct snd_pcm_substream *substream,
521                                struct snd_soc_dai *dai)
522 {
523         snd_pcm_hw_constraint_list(substream->runtime, 0,
524                                         SNDRV_PCM_HW_PARAM_RATE,
525                                         &cs35l33_constraints);
526         return 0;
527 }
528 
529 static int cs35l33_set_tristate(struct snd_soc_dai *dai, int tristate)
530 {
531         struct snd_soc_component *component = dai->component;
532         struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
533 
534         if (tristate) {
535                 regmap_update_bits(priv->regmap, CS35L33_PWRCTL2,
536                         CS35L33_SDOUT_3ST_I2S, CS35L33_SDOUT_3ST_I2S);
537                 regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
538                         CS35L33_SDOUT_3ST_TDM, CS35L33_SDOUT_3ST_TDM);
539         } else {
540                 regmap_update_bits(priv->regmap, CS35L33_PWRCTL2,
541                         CS35L33_SDOUT_3ST_I2S, 0);
542                 regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
543                         CS35L33_SDOUT_3ST_TDM, 0);
544         }
545 
546         return 0;
547 }
548 
549 static int cs35l33_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
550                                 unsigned int rx_mask, int slots, int slot_width)
551 {
552         struct snd_soc_component *component = dai->component;
553         struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
554         struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
555         unsigned int reg, bit_pos, i;
556         int slot, slot_num;
557 
558         if (slot_width != 8)
559                 return -EINVAL;
560 
561         /* scan rx_mask for aud slot */
562         slot = ffs(rx_mask) - 1;
563         if (slot >= 0) {
564                 regmap_update_bits(priv->regmap, CS35L33_RX_AUD,
565                         CS35L33_X_LOC, slot);
566                 dev_dbg(component->dev, "Audio starts from slots %d", slot);
567         }
568 
569         /*
570          * scan tx_mask: vmon(2 slots); imon (2 slots);
571          * vpmon (1 slot) vbstmon (1 slot)
572          */
573         slot = ffs(tx_mask) - 1;
574         slot_num = 0;
575 
576         for (i = 0; i < 2 ; i++) {
577                 /* disable vpmon/vbstmon: enable later if set in tx_mask */
578                 regmap_update_bits(priv->regmap, CS35L33_TX_VPMON + i,
579                         CS35L33_X_STATE | CS35L33_X_LOC, CS35L33_X_STATE
580                         | CS35L33_X_LOC);
581         }
582 
583         /* disconnect {vp,vbst}_mon routes: eanble later if set in tx_mask*/
584         snd_soc_dapm_del_routes(dapm, cs35l33_vp_vbst_mon_route,
585                 ARRAY_SIZE(cs35l33_vp_vbst_mon_route));
586 
587         while (slot >= 0) {
588                 /* configure VMON_TX_LOC */
589                 if (slot_num == 0) {
590                         regmap_update_bits(priv->regmap, CS35L33_TX_VMON,
591                                 CS35L33_X_STATE | CS35L33_X_LOC, slot);
592                         dev_dbg(component->dev, "VMON enabled in slots %d-%d",
593                                 slot, slot + 1);
594                 }
595 
596                 /* configure IMON_TX_LOC */
597                 if (slot_num == 3) {
598                         regmap_update_bits(priv->regmap, CS35L33_TX_IMON,
599                                 CS35L33_X_STATE | CS35L33_X_LOC, slot);
600                         dev_dbg(component->dev, "IMON enabled in slots %d-%d",
601                                 slot, slot + 1);
602                 }
603 
604                 /* configure VPMON_TX_LOC */
605                 if (slot_num == 4) {
606                         regmap_update_bits(priv->regmap, CS35L33_TX_VPMON,
607                                 CS35L33_X_STATE | CS35L33_X_LOC, slot);
608                         snd_soc_dapm_add_routes(dapm,
609                                 &cs35l33_vp_vbst_mon_route[0], 2);
610                         dev_dbg(component->dev, "VPMON enabled in slots %d", slot);
611                 }
612 
613                 /* configure VBSTMON_TX_LOC */
614                 if (slot_num == 5) {
615                         regmap_update_bits(priv->regmap, CS35L33_TX_VBSTMON,
616                                 CS35L33_X_STATE | CS35L33_X_LOC, slot);
617                         snd_soc_dapm_add_routes(dapm,
618                                 &cs35l33_vp_vbst_mon_route[2], 2);
619                         dev_dbg(component->dev,
620                                 "VBSTMON enabled in slots %d", slot);
621                 }
622 
623                 /* Enable the relevant tx slot */
624                 reg = CS35L33_TX_EN4 - (slot/8);
625                 bit_pos = slot - ((slot / 8) * (8));
626                 regmap_update_bits(priv->regmap, reg,
627                         1 << bit_pos, 1 << bit_pos);
628 
629                 tx_mask &= ~(1 << slot);
630                 slot = ffs(tx_mask) - 1;
631                 slot_num++;
632         }
633 
634         return 0;
635 }
636 
637 static int cs35l33_component_set_sysclk(struct snd_soc_component *component,
638                 int clk_id, int source, unsigned int freq, int dir)
639 {
640         struct cs35l33_private *cs35l33 = snd_soc_component_get_drvdata(component);
641 
642         switch (freq) {
643         case CS35L33_MCLK_5644:
644         case CS35L33_MCLK_6:
645         case CS35L33_MCLK_6144:
646                 regmap_update_bits(cs35l33->regmap, CS35L33_CLK_CTL,
647                         CS35L33_MCLKDIV2, 0);
648                 cs35l33->mclk_int = freq;
649                 break;
650         case CS35L33_MCLK_11289:
651         case CS35L33_MCLK_12:
652         case CS35L33_MCLK_12288:
653                 regmap_update_bits(cs35l33->regmap, CS35L33_CLK_CTL,
654                         CS35L33_MCLKDIV2, CS35L33_MCLKDIV2);
655                 cs35l33->mclk_int = freq/2;
656                 break;
657         default:
658                 cs35l33->mclk_int = 0;
659                 return -EINVAL;
660         }
661 
662         dev_dbg(component->dev, "external mclk freq=%d, internal mclk freq=%d\n",
663                 freq, cs35l33->mclk_int);
664 
665         return 0;
666 }
667 
668 static const struct snd_soc_dai_ops cs35l33_ops = {
669         .startup = cs35l33_pcm_startup,
670         .set_tristate = cs35l33_set_tristate,
671         .set_fmt = cs35l33_set_dai_fmt,
672         .hw_params = cs35l33_pcm_hw_params,
673         .set_tdm_slot = cs35l33_set_tdm_slot,
674 };
675 
676 static struct snd_soc_dai_driver cs35l33_dai = {
677                 .name = "cs35l33-dai",
678                 .id = 0,
679                 .playback = {
680                         .stream_name = "CS35L33 Playback",
681                         .channels_min = 1,
682                         .channels_max = 1,
683                         .rates = CS35L33_RATES,
684                         .formats = CS35L33_FORMATS,
685                 },
686                 .capture = {
687                         .stream_name = "CS35L33 Capture",
688                         .channels_min = 2,
689                         .channels_max = 2,
690                         .rates = CS35L33_RATES,
691                         .formats = CS35L33_FORMATS,
692                 },
693                 .ops = &cs35l33_ops,
694                 .symmetric_rates = 1,
695 };
696 
697 static int cs35l33_set_hg_data(struct snd_soc_component *component,
698                                struct cs35l33_pdata *pdata)
699 {
700         struct cs35l33_hg *hg_config = &pdata->hg_config;
701         struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
702         struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
703 
704         if (hg_config->enable_hg_algo) {
705                 regmap_update_bits(priv->regmap, CS35L33_HG_MEMLDO_CTL,
706                         CS35L33_MEM_DEPTH_MASK,
707                         hg_config->mem_depth << CS35L33_MEM_DEPTH_SHIFT);
708                 regmap_write(priv->regmap, CS35L33_HG_REL_RATE,
709                         hg_config->release_rate);
710                 regmap_update_bits(priv->regmap, CS35L33_HG_HEAD,
711                         CS35L33_HD_RM_MASK,
712                         hg_config->hd_rm << CS35L33_HD_RM_SHIFT);
713                 regmap_update_bits(priv->regmap, CS35L33_HG_MEMLDO_CTL,
714                         CS35L33_LDO_THLD_MASK,
715                         hg_config->ldo_thld << CS35L33_LDO_THLD_SHIFT);
716                 regmap_update_bits(priv->regmap, CS35L33_HG_MEMLDO_CTL,
717                         CS35L33_LDO_DISABLE_MASK,
718                         hg_config->ldo_path_disable <<
719                                 CS35L33_LDO_DISABLE_SHIFT);
720                 regmap_update_bits(priv->regmap, CS35L33_LDO_DEL,
721                         CS35L33_LDO_ENTRY_DELAY_MASK,
722                         hg_config->ldo_entry_delay <<
723                                 CS35L33_LDO_ENTRY_DELAY_SHIFT);
724                 if (hg_config->vp_hg_auto) {
725                         regmap_update_bits(priv->regmap, CS35L33_HG_EN,
726                                 CS35L33_VP_HG_AUTO_MASK,
727                                 CS35L33_VP_HG_AUTO_MASK);
728                         snd_soc_dapm_add_routes(dapm, cs35l33_vphg_auto_route,
729                                 ARRAY_SIZE(cs35l33_vphg_auto_route));
730                 }
731                 regmap_update_bits(priv->regmap, CS35L33_HG_EN,
732                         CS35L33_VP_HG_MASK,
733                         hg_config->vp_hg << CS35L33_VP_HG_SHIFT);
734                 regmap_update_bits(priv->regmap, CS35L33_LDO_DEL,
735                         CS35L33_VP_HG_RATE_MASK,
736                         hg_config->vp_hg_rate << CS35L33_VP_HG_RATE_SHIFT);
737                 regmap_update_bits(priv->regmap, CS35L33_LDO_DEL,
738                         CS35L33_VP_HG_VA_MASK,
739                         hg_config->vp_hg_va << CS35L33_VP_HG_VA_SHIFT);
740                 regmap_update_bits(priv->regmap, CS35L33_HG_EN,
741                         CS35L33_CLASS_HG_EN_MASK, CS35L33_CLASS_HG_EN_MASK);
742         }
743         return 0;
744 }
745 
746 static int cs35l33_set_bst_ipk(struct snd_soc_component *component, unsigned int bst)
747 {
748         struct cs35l33_private *cs35l33 = snd_soc_component_get_drvdata(component);
749         int ret = 0, steps = 0;
750 
751         /* Boost current in uA */
752         if (bst > 3600000 || bst < 1850000) {
753                 dev_err(component->dev, "Invalid boost current %d\n", bst);
754                 ret = -EINVAL;
755                 goto err;
756         }
757 
758         if (bst % 15625) {
759                 dev_err(component->dev, "Current not a multiple of 15625uA (%d)\n",
760                         bst);
761                 ret = -EINVAL;
762                 goto err;
763         }
764 
765         while (bst > 1850000) {
766                 bst -= 15625;
767                 steps++;
768         }
769 
770         regmap_write(cs35l33->regmap, CS35L33_BST_PEAK_CTL,
771                 steps+0x70);
772 
773 err:
774         return ret;
775 }
776 
777 static int cs35l33_probe(struct snd_soc_component *component)
778 {
779         struct cs35l33_private *cs35l33 = snd_soc_component_get_drvdata(component);
780 
781         cs35l33->component = component;
782         pm_runtime_get_sync(component->dev);
783 
784         regmap_update_bits(cs35l33->regmap, CS35L33_PROTECT_CTL,
785                 CS35L33_ALIVE_WD_DIS, 0x8);
786         regmap_update_bits(cs35l33->regmap, CS35L33_BST_CTL2,
787                                 CS35L33_ALIVE_WD_DIS2,
788                                 CS35L33_ALIVE_WD_DIS2);
789 
790         /* Set Platform Data */
791         regmap_update_bits(cs35l33->regmap, CS35L33_BST_CTL1,
792                 CS35L33_BST_CTL_MASK, cs35l33->pdata.boost_ctl);
793         regmap_update_bits(cs35l33->regmap, CS35L33_CLASSD_CTL,
794                 CS35L33_AMP_DRV_SEL_MASK,
795                 cs35l33->pdata.amp_drv_sel << CS35L33_AMP_DRV_SEL_SHIFT);
796 
797         if (cs35l33->pdata.boost_ipk)
798                 cs35l33_set_bst_ipk(component, cs35l33->pdata.boost_ipk);
799 
800         if (cs35l33->enable_soft_ramp) {
801                 snd_soc_component_update_bits(component, CS35L33_DAC_CTL,
802                         CS35L33_DIGSFT, CS35L33_DIGSFT);
803                 snd_soc_component_update_bits(component, CS35L33_DAC_CTL,
804                         CS35L33_DSR_RATE, cs35l33->pdata.ramp_rate);
805         } else {
806                 snd_soc_component_update_bits(component, CS35L33_DAC_CTL,
807                         CS35L33_DIGSFT, 0);
808         }
809 
810         /* update IMON scaling rate if different from default of 0x8 */
811         if (cs35l33->pdata.imon_adc_scale != 0x8)
812                 snd_soc_component_update_bits(component, CS35L33_ADC_CTL,
813                         CS35L33_IMON_SCALE, cs35l33->pdata.imon_adc_scale);
814 
815         cs35l33_set_hg_data(component, &(cs35l33->pdata));
816 
817         /*
818          * unmask important interrupts that causes the chip to enter
819          * speaker safe mode and hence deserves user attention
820          */
821         regmap_update_bits(cs35l33->regmap, CS35L33_INT_MASK_1,
822                 CS35L33_M_OTE | CS35L33_M_OTW | CS35L33_M_AMP_SHORT |
823                 CS35L33_M_CAL_ERR, 0);
824 
825         pm_runtime_put_sync(component->dev);
826 
827         return 0;
828 }
829 
830 static const struct snd_soc_component_driver soc_component_dev_cs35l33 = {
831         .probe                  = cs35l33_probe,
832         .set_bias_level         = cs35l33_set_bias_level,
833         .set_sysclk             = cs35l33_component_set_sysclk,
834         .controls               = cs35l33_snd_controls,
835         .num_controls           = ARRAY_SIZE(cs35l33_snd_controls),
836         .dapm_widgets           = cs35l33_dapm_widgets,
837         .num_dapm_widgets       = ARRAY_SIZE(cs35l33_dapm_widgets),
838         .dapm_routes            = cs35l33_audio_map,
839         .num_dapm_routes        = ARRAY_SIZE(cs35l33_audio_map),
840         .use_pmdown_time        = 1,
841         .endianness             = 1,
842         .non_legacy_dai_naming  = 1,
843 };
844 
845 static const struct regmap_config cs35l33_regmap = {
846         .reg_bits = 8,
847         .val_bits = 8,
848 
849         .max_register = CS35L33_MAX_REGISTER,
850         .reg_defaults = cs35l33_reg,
851         .num_reg_defaults = ARRAY_SIZE(cs35l33_reg),
852         .volatile_reg = cs35l33_volatile_register,
853         .readable_reg = cs35l33_readable_register,
854         .writeable_reg = cs35l33_writeable_register,
855         .cache_type = REGCACHE_RBTREE,
856         .use_single_read = true,
857         .use_single_write = true,
858 };
859 
860 static int __maybe_unused cs35l33_runtime_resume(struct device *dev)
861 {
862         struct cs35l33_private *cs35l33 = dev_get_drvdata(dev);
863         int ret;
864 
865         dev_dbg(dev, "%s\n", __func__);
866 
867         gpiod_set_value_cansleep(cs35l33->reset_gpio, 0);
868 
869         ret = regulator_bulk_enable(cs35l33->num_core_supplies,
870                 cs35l33->core_supplies);
871         if (ret != 0) {
872                 dev_err(dev, "Failed to enable core supplies: %d\n", ret);
873                 return ret;
874         }
875 
876         regcache_cache_only(cs35l33->regmap, false);
877 
878         gpiod_set_value_cansleep(cs35l33->reset_gpio, 1);
879 
880         msleep(CS35L33_BOOT_DELAY);
881 
882         ret = regcache_sync(cs35l33->regmap);
883         if (ret != 0) {
884                 dev_err(dev, "Failed to restore register cache\n");
885                 goto err;
886         }
887 
888         return 0;
889 
890 err:
891         regcache_cache_only(cs35l33->regmap, true);
892         regulator_bulk_disable(cs35l33->num_core_supplies,
893                 cs35l33->core_supplies);
894 
895         return ret;
896 }
897 
898 static int __maybe_unused cs35l33_runtime_suspend(struct device *dev)
899 {
900         struct cs35l33_private *cs35l33 = dev_get_drvdata(dev);
901 
902         dev_dbg(dev, "%s\n", __func__);
903 
904         /* redo the calibration in next power up */
905         cs35l33->amp_cal = false;
906 
907         regcache_cache_only(cs35l33->regmap, true);
908         regcache_mark_dirty(cs35l33->regmap);
909         regulator_bulk_disable(cs35l33->num_core_supplies,
910                 cs35l33->core_supplies);
911 
912         return 0;
913 }
914 
915 static const struct dev_pm_ops cs35l33_pm_ops = {
916         SET_RUNTIME_PM_OPS(cs35l33_runtime_suspend,
917                            cs35l33_runtime_resume,
918                            NULL)
919 };
920 
921 static int cs35l33_get_hg_data(const struct device_node *np,
922                                struct cs35l33_pdata *pdata)
923 {
924         struct device_node *hg;
925         struct cs35l33_hg *hg_config = &pdata->hg_config;
926         u32 val32;
927 
928         hg = of_get_child_by_name(np, "cirrus,hg-algo");
929         hg_config->enable_hg_algo = hg ? true : false;
930 
931         if (hg_config->enable_hg_algo) {
932                 if (of_property_read_u32(hg, "cirrus,mem-depth", &val32) >= 0)
933                         hg_config->mem_depth = val32;
934                 if (of_property_read_u32(hg, "cirrus,release-rate",
935                                 &val32) >= 0)
936                         hg_config->release_rate = val32;
937                 if (of_property_read_u32(hg, "cirrus,ldo-thld", &val32) >= 0)
938                         hg_config->ldo_thld = val32;
939                 if (of_property_read_u32(hg, "cirrus,ldo-path-disable",
940                                 &val32) >= 0)
941                         hg_config->ldo_path_disable = val32;
942                 if (of_property_read_u32(hg, "cirrus,ldo-entry-delay",
943                                 &val32) >= 0)
944                         hg_config->ldo_entry_delay = val32;
945 
946                 hg_config->vp_hg_auto = of_property_read_bool(hg,
947                         "cirrus,vp-hg-auto");
948 
949                 if (of_property_read_u32(hg, "cirrus,vp-hg", &val32) >= 0)
950                         hg_config->vp_hg = val32;
951                 if (of_property_read_u32(hg, "cirrus,vp-hg-rate", &val32) >= 0)
952                         hg_config->vp_hg_rate = val32;
953                 if (of_property_read_u32(hg, "cirrus,vp-hg-va", &val32) >= 0)
954                         hg_config->vp_hg_va = val32;
955         }
956 
957         of_node_put(hg);
958 
959         return 0;
960 }
961 
962 static irqreturn_t cs35l33_irq_thread(int irq, void *data)
963 {
964         struct cs35l33_private *cs35l33 = data;
965         struct snd_soc_component *component = cs35l33->component;
966         unsigned int sticky_val1, sticky_val2, current_val, mask1, mask2;
967 
968         regmap_read(cs35l33->regmap, CS35L33_INT_STATUS_2,
969                 &sticky_val2);
970         regmap_read(cs35l33->regmap, CS35L33_INT_STATUS_1,
971                 &sticky_val1);
972         regmap_read(cs35l33->regmap, CS35L33_INT_MASK_2, &mask2);
973         regmap_read(cs35l33->regmap, CS35L33_INT_MASK_1, &mask1);
974 
975         /* Check to see if the unmasked bits are active,
976          *  if not then exit.
977          */
978         if (!(sticky_val1 & ~mask1) && !(sticky_val2 & ~mask2))
979                 return IRQ_NONE;
980 
981         regmap_read(cs35l33->regmap, CS35L33_INT_STATUS_1,
982                 &current_val);
983 
984         /* handle the interrupts */
985 
986         if (sticky_val1 & CS35L33_AMP_SHORT) {
987                 dev_crit(component->dev, "Amp short error\n");
988                 if (!(current_val & CS35L33_AMP_SHORT)) {
989                         dev_dbg(component->dev,
990                                 "Amp short error release\n");
991                         regmap_update_bits(cs35l33->regmap,
992                                 CS35L33_AMP_CTL,
993                                 CS35L33_AMP_SHORT_RLS, 0);
994                         regmap_update_bits(cs35l33->regmap,
995                                 CS35L33_AMP_CTL,
996                                 CS35L33_AMP_SHORT_RLS,
997                                 CS35L33_AMP_SHORT_RLS);
998                         regmap_update_bits(cs35l33->regmap,
999                                 CS35L33_AMP_CTL, CS35L33_AMP_SHORT_RLS,
1000                                 0);
1001                 }
1002         }
1003 
1004         if (sticky_val1 & CS35L33_CAL_ERR) {
1005                 dev_err(component->dev, "Cal error\n");
1006 
1007                 /* redo the calibration in next power up */
1008                 cs35l33->amp_cal = false;
1009 
1010                 if (!(current_val & CS35L33_CAL_ERR)) {
1011                         dev_dbg(component->dev, "Cal error release\n");
1012                         regmap_update_bits(cs35l33->regmap,
1013                                 CS35L33_AMP_CTL, CS35L33_CAL_ERR_RLS,
1014                                 0);
1015                         regmap_update_bits(cs35l33->regmap,
1016                                 CS35L33_AMP_CTL, CS35L33_CAL_ERR_RLS,
1017                                 CS35L33_CAL_ERR_RLS);
1018                         regmap_update_bits(cs35l33->regmap,
1019                                 CS35L33_AMP_CTL, CS35L33_CAL_ERR_RLS,
1020                                 0);
1021                 }
1022         }
1023 
1024         if (sticky_val1 & CS35L33_OTE) {
1025                 dev_crit(component->dev, "Over temperature error\n");
1026                 if (!(current_val & CS35L33_OTE)) {
1027                         dev_dbg(component->dev,
1028                                 "Over temperature error release\n");
1029                         regmap_update_bits(cs35l33->regmap,
1030                                 CS35L33_AMP_CTL, CS35L33_OTE_RLS, 0);
1031                         regmap_update_bits(cs35l33->regmap,
1032                                 CS35L33_AMP_CTL, CS35L33_OTE_RLS,
1033                                 CS35L33_OTE_RLS);
1034                         regmap_update_bits(cs35l33->regmap,
1035                                 CS35L33_AMP_CTL, CS35L33_OTE_RLS, 0);
1036                 }
1037         }
1038 
1039         if (sticky_val1 & CS35L33_OTW) {
1040                 dev_err(component->dev, "Over temperature warning\n");
1041                 if (!(current_val & CS35L33_OTW)) {
1042                         dev_dbg(component->dev,
1043                                 "Over temperature warning release\n");
1044                         regmap_update_bits(cs35l33->regmap,
1045                                 CS35L33_AMP_CTL, CS35L33_OTW_RLS, 0);
1046                         regmap_update_bits(cs35l33->regmap,
1047                                 CS35L33_AMP_CTL, CS35L33_OTW_RLS,
1048                                 CS35L33_OTW_RLS);
1049                         regmap_update_bits(cs35l33->regmap,
1050                                 CS35L33_AMP_CTL, CS35L33_OTW_RLS, 0);
1051                 }
1052         }
1053         if (CS35L33_ALIVE_ERR & sticky_val1)
1054                 dev_err(component->dev, "ERROR: ADSPCLK Interrupt\n");
1055 
1056         if (CS35L33_MCLK_ERR & sticky_val1)
1057                 dev_err(component->dev, "ERROR: MCLK Interrupt\n");
1058 
1059         if (CS35L33_VMON_OVFL & sticky_val2)
1060                 dev_err(component->dev,
1061                         "ERROR: VMON Overflow Interrupt\n");
1062 
1063         if (CS35L33_IMON_OVFL & sticky_val2)
1064                 dev_err(component->dev,
1065                         "ERROR: IMON Overflow Interrupt\n");
1066 
1067         if (CS35L33_VPMON_OVFL & sticky_val2)
1068                 dev_err(component->dev,
1069                         "ERROR: VPMON Overflow Interrupt\n");
1070 
1071         return IRQ_HANDLED;
1072 }
1073 
1074 static const char * const cs35l33_core_supplies[] = {
1075         "VA",
1076         "VP",
1077 };
1078 
1079 static int cs35l33_of_get_pdata(struct device *dev,
1080                                 struct cs35l33_private *cs35l33)
1081 {
1082         struct device_node *np = dev->of_node;
1083         struct cs35l33_pdata *pdata = &cs35l33->pdata;
1084         u32 val32;
1085 
1086         if (!np)
1087                 return 0;
1088 
1089         if (of_property_read_u32(np, "cirrus,boost-ctl", &val32) >= 0) {
1090                 pdata->boost_ctl = val32;
1091                 pdata->amp_drv_sel = 1;
1092         }
1093 
1094         if (of_property_read_u32(np, "cirrus,ramp-rate", &val32) >= 0) {
1095                 pdata->ramp_rate = val32;
1096                 cs35l33->enable_soft_ramp = true;
1097         }
1098 
1099         if (of_property_read_u32(np, "cirrus,boost-ipk", &val32) >= 0)
1100                 pdata->boost_ipk = val32;
1101 
1102         if (of_property_read_u32(np, "cirrus,imon-adc-scale", &val32) >= 0) {
1103                 if ((val32 == 0x0) || (val32 == 0x7) || (val32 == 0x6))
1104                         pdata->imon_adc_scale = val32;
1105                 else
1106                         /* use default value */
1107                         pdata->imon_adc_scale = 0x8;
1108         } else {
1109                 /* use default value */
1110                 pdata->imon_adc_scale = 0x8;
1111         }
1112 
1113         cs35l33_get_hg_data(np, pdata);
1114 
1115         return 0;
1116 }
1117 
1118 static int cs35l33_i2c_probe(struct i2c_client *i2c_client,
1119                                        const struct i2c_device_id *id)
1120 {
1121         struct cs35l33_private *cs35l33;
1122         struct cs35l33_pdata *pdata = dev_get_platdata(&i2c_client->dev);
1123         int ret, devid, i;
1124         unsigned int reg;
1125 
1126         cs35l33 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs35l33_private),
1127                                GFP_KERNEL);
1128         if (!cs35l33)
1129                 return -ENOMEM;
1130 
1131         i2c_set_clientdata(i2c_client, cs35l33);
1132         cs35l33->regmap = devm_regmap_init_i2c(i2c_client, &cs35l33_regmap);
1133         if (IS_ERR(cs35l33->regmap)) {
1134                 ret = PTR_ERR(cs35l33->regmap);
1135                 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
1136                 return ret;
1137         }
1138 
1139         regcache_cache_only(cs35l33->regmap, true);
1140 
1141         for (i = 0; i < ARRAY_SIZE(cs35l33_core_supplies); i++)
1142                 cs35l33->core_supplies[i].supply
1143                         = cs35l33_core_supplies[i];
1144         cs35l33->num_core_supplies = ARRAY_SIZE(cs35l33_core_supplies);
1145 
1146         ret = devm_regulator_bulk_get(&i2c_client->dev,
1147                         cs35l33->num_core_supplies,
1148                         cs35l33->core_supplies);
1149         if (ret != 0) {
1150                 dev_err(&i2c_client->dev,
1151                         "Failed to request core supplies: %d\n",
1152                         ret);
1153                 return ret;
1154         }
1155 
1156         if (pdata) {
1157                 cs35l33->pdata = *pdata;
1158         } else {
1159                 cs35l33_of_get_pdata(&i2c_client->dev, cs35l33);
1160                 pdata = &cs35l33->pdata;
1161         }
1162 
1163         ret = devm_request_threaded_irq(&i2c_client->dev, i2c_client->irq, NULL,
1164                         cs35l33_irq_thread, IRQF_ONESHOT | IRQF_TRIGGER_LOW,
1165                         "cs35l33", cs35l33);
1166         if (ret != 0)
1167                 dev_warn(&i2c_client->dev, "Failed to request IRQ: %d\n", ret);
1168 
1169         /* We could issue !RST or skip it based on AMP topology */
1170         cs35l33->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev,
1171                         "reset-gpios", GPIOD_OUT_HIGH);
1172         if (IS_ERR(cs35l33->reset_gpio)) {
1173                 dev_err(&i2c_client->dev, "%s ERROR: Can't get reset GPIO\n",
1174                         __func__);
1175                 return PTR_ERR(cs35l33->reset_gpio);
1176         }
1177 
1178         ret = regulator_bulk_enable(cs35l33->num_core_supplies,
1179                                         cs35l33->core_supplies);
1180         if (ret != 0) {
1181                 dev_err(&i2c_client->dev,
1182                         "Failed to enable core supplies: %d\n",
1183                         ret);
1184                 return ret;
1185         }
1186 
1187         gpiod_set_value_cansleep(cs35l33->reset_gpio, 1);
1188 
1189         msleep(CS35L33_BOOT_DELAY);
1190         regcache_cache_only(cs35l33->regmap, false);
1191 
1192         /* initialize codec */
1193         ret = regmap_read(cs35l33->regmap, CS35L33_DEVID_AB, &reg);
1194         devid = (reg & 0xFF) << 12;
1195         ret = regmap_read(cs35l33->regmap, CS35L33_DEVID_CD, &reg);
1196         devid |= (reg & 0xFF) << 4;
1197         ret = regmap_read(cs35l33->regmap, CS35L33_DEVID_E, &reg);
1198         devid |= (reg & 0xF0) >> 4;
1199 
1200         if (devid != CS35L33_CHIP_ID) {
1201                 dev_err(&i2c_client->dev,
1202                         "CS35L33 Device ID (%X). Expected ID %X\n",
1203                         devid, CS35L33_CHIP_ID);
1204                 goto err_enable;
1205         }
1206 
1207         ret = regmap_read(cs35l33->regmap, CS35L33_REV_ID, &reg);
1208         if (ret < 0) {
1209                 dev_err(&i2c_client->dev, "Get Revision ID failed\n");
1210                 goto err_enable;
1211         }
1212 
1213         dev_info(&i2c_client->dev,
1214                  "Cirrus Logic CS35L33, Revision: %02X\n", reg & 0xFF);
1215 
1216         ret = regmap_register_patch(cs35l33->regmap,
1217                         cs35l33_patch, ARRAY_SIZE(cs35l33_patch));
1218         if (ret < 0) {
1219                 dev_err(&i2c_client->dev,
1220                         "Error in applying regmap patch: %d\n", ret);
1221                 goto err_enable;
1222         }
1223 
1224         /* disable mclk and tdm */
1225         regmap_update_bits(cs35l33->regmap, CS35L33_CLK_CTL,
1226                 CS35L33_MCLKDIS | CS35L33_SDOUT_3ST_TDM,
1227                 CS35L33_MCLKDIS | CS35L33_SDOUT_3ST_TDM);
1228 
1229         pm_runtime_set_autosuspend_delay(&i2c_client->dev, 100);
1230         pm_runtime_use_autosuspend(&i2c_client->dev);
1231         pm_runtime_set_active(&i2c_client->dev);
1232         pm_runtime_enable(&i2c_client->dev);
1233 
1234         ret = devm_snd_soc_register_component(&i2c_client->dev,
1235                         &soc_component_dev_cs35l33, &cs35l33_dai, 1);
1236         if (ret < 0) {
1237                 dev_err(&i2c_client->dev, "%s: Register component failed\n",
1238                         __func__);
1239                 goto err_enable;
1240         }
1241 
1242         return 0;
1243 
1244 err_enable:
1245         regulator_bulk_disable(cs35l33->num_core_supplies,
1246                                cs35l33->core_supplies);
1247 
1248         return ret;
1249 }
1250 
1251 static int cs35l33_i2c_remove(struct i2c_client *client)
1252 {
1253         struct cs35l33_private *cs35l33 = i2c_get_clientdata(client);
1254 
1255         gpiod_set_value_cansleep(cs35l33->reset_gpio, 0);
1256 
1257         pm_runtime_disable(&client->dev);
1258         regulator_bulk_disable(cs35l33->num_core_supplies,
1259                 cs35l33->core_supplies);
1260 
1261         return 0;
1262 }
1263 
1264 static const struct of_device_id cs35l33_of_match[] = {
1265         { .compatible = "cirrus,cs35l33", },
1266         {},
1267 };
1268 MODULE_DEVICE_TABLE(of, cs35l33_of_match);
1269 
1270 static const struct i2c_device_id cs35l33_id[] = {
1271         {"cs35l33", 0},
1272         {}
1273 };
1274 
1275 MODULE_DEVICE_TABLE(i2c, cs35l33_id);
1276 
1277 static struct i2c_driver cs35l33_i2c_driver = {
1278         .driver = {
1279                 .name = "cs35l33",
1280                 .pm = &cs35l33_pm_ops,
1281                 .of_match_table = cs35l33_of_match,
1282 
1283                 },
1284         .id_table = cs35l33_id,
1285         .probe = cs35l33_i2c_probe,
1286         .remove = cs35l33_i2c_remove,
1287 
1288 };
1289 module_i2c_driver(cs35l33_i2c_driver);
1290 
1291 MODULE_DESCRIPTION("ASoC CS35L33 driver");
1292 MODULE_AUTHOR("Paul Handrigan, Cirrus Logic Inc, <paul.handrigan@cirrus.com>");
1293 MODULE_LICENSE("GPL");
1294 

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