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TOMOYO Linux Cross Reference
Linux/sound/soc/codecs/cs35l36.c

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  1 // SPDX-License-Identifier: GPL-2.0
  2 //
  3 // cs35l36.c -- CS35L36 ALSA SoC audio driver
  4 //
  5 // Copyright 2018 Cirrus Logic, Inc.
  6 //
  7 // Author: James Schulman <james.schulman@cirrus.com>
  8 
  9 #include <linux/module.h>
 10 #include <linux/moduleparam.h>
 11 #include <linux/kernel.h>
 12 #include <linux/init.h>
 13 #include <linux/delay.h>
 14 #include <linux/i2c.h>
 15 #include <linux/slab.h>
 16 #include <linux/workqueue.h>
 17 #include <linux/platform_device.h>
 18 #include <linux/regulator/consumer.h>
 19 #include <linux/gpio/consumer.h>
 20 #include <linux/of_device.h>
 21 #include <linux/of_gpio.h>
 22 #include <linux/regmap.h>
 23 #include <sound/core.h>
 24 #include <sound/pcm.h>
 25 #include <sound/pcm_params.h>
 26 #include <sound/soc.h>
 27 #include <sound/soc-dapm.h>
 28 #include <linux/gpio.h>
 29 #include <sound/initval.h>
 30 #include <sound/tlv.h>
 31 #include <sound/cs35l36.h>
 32 #include <linux/of_irq.h>
 33 #include <linux/completion.h>
 34 
 35 #include "cs35l36.h"
 36 
 37 /*
 38  * Some fields take zero as a valid value so use a high bit flag that won't
 39  * get written to the device to mark those.
 40  */
 41 #define CS35L36_VALID_PDATA 0x80000000
 42 
 43 static const char * const cs35l36_supplies[] = {
 44         "VA",
 45         "VP",
 46 };
 47 
 48 struct  cs35l36_private {
 49         struct device *dev;
 50         struct cs35l36_platform_data pdata;
 51         struct regmap *regmap;
 52         struct regulator_bulk_data supplies[2];
 53         int num_supplies;
 54         int clksrc;
 55         int chip_version;
 56         int rev_id;
 57         int ldm_mode_sel;
 58         struct gpio_desc *reset_gpio;
 59 };
 60 
 61 struct cs35l36_pll_config {
 62         int freq;
 63         int clk_cfg;
 64         int fll_igain;
 65 };
 66 
 67 static const struct cs35l36_pll_config cs35l36_pll_sysclk[] = {
 68         {32768,         0x00, 0x05},
 69         {8000,          0x01, 0x03},
 70         {11025,         0x02, 0x03},
 71         {12000,         0x03, 0x03},
 72         {16000,         0x04, 0x04},
 73         {22050,         0x05, 0x04},
 74         {24000,         0x06, 0x04},
 75         {32000,         0x07, 0x05},
 76         {44100,         0x08, 0x05},
 77         {48000,         0x09, 0x05},
 78         {88200,         0x0A, 0x06},
 79         {96000,         0x0B, 0x06},
 80         {128000,        0x0C, 0x07},
 81         {176400,        0x0D, 0x07},
 82         {192000,        0x0E, 0x07},
 83         {256000,        0x0F, 0x08},
 84         {352800,        0x10, 0x08},
 85         {384000,        0x11, 0x08},
 86         {512000,        0x12, 0x09},
 87         {705600,        0x13, 0x09},
 88         {750000,        0x14, 0x09},
 89         {768000,        0x15, 0x09},
 90         {1000000,       0x16, 0x0A},
 91         {1024000,       0x17, 0x0A},
 92         {1200000,       0x18, 0x0A},
 93         {1411200,       0x19, 0x0A},
 94         {1500000,       0x1A, 0x0A},
 95         {1536000,       0x1B, 0x0A},
 96         {2000000,       0x1C, 0x0A},
 97         {2048000,       0x1D, 0x0A},
 98         {2400000,       0x1E, 0x0A},
 99         {2822400,       0x1F, 0x0A},
100         {3000000,       0x20, 0x0A},
101         {3072000,       0x21, 0x0A},
102         {3200000,       0x22, 0x0A},
103         {4000000,       0x23, 0x0A},
104         {4096000,       0x24, 0x0A},
105         {4800000,       0x25, 0x0A},
106         {5644800,       0x26, 0x0A},
107         {6000000,       0x27, 0x0A},
108         {6144000,       0x28, 0x0A},
109         {6250000,       0x29, 0x08},
110         {6400000,       0x2A, 0x0A},
111         {6500000,       0x2B, 0x08},
112         {6750000,       0x2C, 0x09},
113         {7526400,       0x2D, 0x0A},
114         {8000000,       0x2E, 0x0A},
115         {8192000,       0x2F, 0x0A},
116         {9600000,       0x30, 0x0A},
117         {11289600,      0x31, 0x0A},
118         {12000000,      0x32, 0x0A},
119         {12288000,      0x33, 0x0A},
120         {12500000,      0x34, 0x08},
121         {12800000,      0x35, 0x0A},
122         {13000000,      0x36, 0x0A},
123         {13500000,      0x37, 0x0A},
124         {19200000,      0x38, 0x0A},
125         {22579200,      0x39, 0x0A},
126         {24000000,      0x3A, 0x0A},
127         {24576000,      0x3B, 0x0A},
128         {25000000,      0x3C, 0x0A},
129         {25600000,      0x3D, 0x0A},
130         {26000000,      0x3E, 0x0A},
131         {27000000,      0x3F, 0x0A},
132 };
133 
134 static struct reg_default cs35l36_reg[] = {
135         {CS35L36_TESTKEY_CTRL,                  0x00000000},
136         {CS35L36_USERKEY_CTL,                   0x00000000},
137         {CS35L36_OTP_CTRL1,                     0x00002460},
138         {CS35L36_OTP_CTRL2,                     0x00000000},
139         {CS35L36_OTP_CTRL3,                     0x00000000},
140         {CS35L36_OTP_CTRL4,                     0x00000000},
141         {CS35L36_OTP_CTRL5,                     0x00000000},
142         {CS35L36_PAC_CTL1,                      0x00000004},
143         {CS35L36_PAC_CTL2,                      0x00000000},
144         {CS35L36_PAC_CTL3,                      0x00000000},
145         {CS35L36_PWR_CTRL1,                     0x00000000},
146         {CS35L36_PWR_CTRL2,                     0x00003321},
147         {CS35L36_PWR_CTRL3,                     0x01000010},
148         {CS35L36_CTRL_OVRRIDE,                  0x00000002},
149         {CS35L36_AMP_OUT_MUTE,                  0x00000000},
150         {CS35L36_OTP_TRIM_STATUS,               0x00000000},
151         {CS35L36_DISCH_FILT,                    0x00000000},
152         {CS35L36_PROTECT_REL_ERR,               0x00000000},
153         {CS35L36_PAD_INTERFACE,                 0x00000038},
154         {CS35L36_PLL_CLK_CTRL,                  0x00000010},
155         {CS35L36_GLOBAL_CLK_CTRL,               0x00000003},
156         {CS35L36_ADC_CLK_CTRL,                  0x00000000},
157         {CS35L36_SWIRE_CLK_CTRL,                0x00000000},
158         {CS35L36_SP_SCLK_CLK_CTRL,              0x00000000},
159         {CS35L36_MDSYNC_EN,                     0x00000000},
160         {CS35L36_MDSYNC_TX_ID,                  0x00000000},
161         {CS35L36_MDSYNC_PWR_CTRL,               0x00000000},
162         {CS35L36_MDSYNC_DATA_TX,                0x00000000},
163         {CS35L36_MDSYNC_TX_STATUS,              0x00000002},
164         {CS35L36_MDSYNC_RX_STATUS,              0x00000000},
165         {CS35L36_MDSYNC_ERR_STATUS,             0x00000000},
166         {CS35L36_BSTCVRT_VCTRL1,                0x00000000},
167         {CS35L36_BSTCVRT_VCTRL2,                0x00000001},
168         {CS35L36_BSTCVRT_PEAK_CUR,              0x0000004A},
169         {CS35L36_BSTCVRT_SFT_RAMP,              0x00000003},
170         {CS35L36_BSTCVRT_COEFF,                 0x00002424},
171         {CS35L36_BSTCVRT_SLOPE_LBST,            0x00005800},
172         {CS35L36_BSTCVRT_SW_FREQ,               0x00010000},
173         {CS35L36_BSTCVRT_DCM_CTRL,              0x00002001},
174         {CS35L36_BSTCVRT_DCM_MODE_FORCE,        0x00000000},
175         {CS35L36_BSTCVRT_OVERVOLT_CTRL,         0x00000130},
176         {CS35L36_VPI_LIMIT_MODE,                0x00000000},
177         {CS35L36_VPI_LIMIT_MINMAX,              0x00003000},
178         {CS35L36_VPI_VP_THLD,                   0x00101010},
179         {CS35L36_VPI_TRACK_CTRL,                0x00000000},
180         {CS35L36_VPI_TRIG_MODE_CTRL,            0x00000000},
181         {CS35L36_VPI_TRIG_STEPS,                0x00000000},
182         {CS35L36_VI_SPKMON_FILT,                0x00000003},
183         {CS35L36_VI_SPKMON_GAIN,                0x00000909},
184         {CS35L36_VI_SPKMON_IP_SEL,              0x00000000},
185         {CS35L36_DTEMP_WARN_THLD,               0x00000002},
186         {CS35L36_DTEMP_STATUS,                  0x00000000},
187         {CS35L36_VPVBST_FS_SEL,                 0x00000001},
188         {CS35L36_VPVBST_VP_CTRL,                0x000001C0},
189         {CS35L36_VPVBST_VBST_CTRL,              0x000001C0},
190         {CS35L36_ASP_TX_PIN_CTRL,               0x00000028},
191         {CS35L36_ASP_RATE_CTRL,                 0x00090000},
192         {CS35L36_ASP_FORMAT,                    0x00000002},
193         {CS35L36_ASP_FRAME_CTRL,                0x00180018},
194         {CS35L36_ASP_TX1_TX2_SLOT,              0x00010000},
195         {CS35L36_ASP_TX3_TX4_SLOT,              0x00030002},
196         {CS35L36_ASP_TX5_TX6_SLOT,              0x00050004},
197         {CS35L36_ASP_TX7_TX8_SLOT,              0x00070006},
198         {CS35L36_ASP_RX1_SLOT,                  0x00000000},
199         {CS35L36_ASP_RX_TX_EN,                  0x00000000},
200         {CS35L36_ASP_RX1_SEL,                   0x00000008},
201         {CS35L36_ASP_TX1_SEL,                   0x00000018},
202         {CS35L36_ASP_TX2_SEL,                   0x00000019},
203         {CS35L36_ASP_TX3_SEL,                   0x00000028},
204         {CS35L36_ASP_TX4_SEL,                   0x00000029},
205         {CS35L36_ASP_TX5_SEL,                   0x00000020},
206         {CS35L36_ASP_TX6_SEL,                   0x00000000},
207         {CS35L36_SWIRE_P1_TX1_SEL,              0x00000018},
208         {CS35L36_SWIRE_P1_TX2_SEL,              0x00000019},
209         {CS35L36_SWIRE_P2_TX1_SEL,              0x00000028},
210         {CS35L36_SWIRE_P2_TX2_SEL,              0x00000029},
211         {CS35L36_SWIRE_P2_TX3_SEL,              0x00000020},
212         {CS35L36_SWIRE_DP1_FIFO_CFG,            0x0000001B},
213         {CS35L36_SWIRE_DP2_FIFO_CFG,            0x0000001B},
214         {CS35L36_SWIRE_DP3_FIFO_CFG,            0x0000001B},
215         {CS35L36_SWIRE_PCM_RX_DATA,             0x00000000},
216         {CS35L36_SWIRE_FS_SEL,                  0x00000001},
217         {CS35L36_AMP_DIG_VOL_CTRL,              0x00008000},
218         {CS35L36_VPBR_CFG,                      0x02AA1905},
219         {CS35L36_VBBR_CFG,                      0x02AA1905},
220         {CS35L36_VPBR_STATUS,                   0x00000000},
221         {CS35L36_VBBR_STATUS,                   0x00000000},
222         {CS35L36_OVERTEMP_CFG,                  0x00000001},
223         {CS35L36_AMP_ERR_VOL,                   0x00000000},
224         {CS35L36_CLASSH_CFG,                    0x000B0405},
225         {CS35L36_CLASSH_FET_DRV_CFG,            0x00000111},
226         {CS35L36_NG_CFG,                        0x00000033},
227         {CS35L36_AMP_GAIN_CTRL,                 0x00000273},
228         {CS35L36_PWM_MOD_IO_CTRL,               0x00000000},
229         {CS35L36_PWM_MOD_STATUS,                0x00000000},
230         {CS35L36_DAC_MSM_CFG,                   0x00000000},
231         {CS35L36_AMP_SLOPE_CTRL,                0x00000B00},
232         {CS35L36_AMP_PDM_VOLUME,                0x00000000},
233         {CS35L36_AMP_PDM_RATE_CTRL,             0x00000000},
234         {CS35L36_PDM_CH_SEL,                    0x00000000},
235         {CS35L36_AMP_NG_CTRL,                   0x0000212F},
236         {CS35L36_PDM_HIGHFILT_CTRL,             0x00000000},
237         {CS35L36_PAC_INT0_CTRL,                 0x00000001},
238         {CS35L36_PAC_INT1_CTRL,                 0x00000001},
239         {CS35L36_PAC_INT2_CTRL,                 0x00000001},
240         {CS35L36_PAC_INT3_CTRL,                 0x00000001},
241         {CS35L36_PAC_INT4_CTRL,                 0x00000001},
242         {CS35L36_PAC_INT5_CTRL,                 0x00000001},
243         {CS35L36_PAC_INT6_CTRL,                 0x00000001},
244         {CS35L36_PAC_INT7_CTRL,                 0x00000001},
245 };
246 
247 static bool cs35l36_readable_reg(struct device *dev, unsigned int reg)
248 {
249         switch (reg) {
250         case CS35L36_SW_RESET:
251         case CS35L36_SW_REV:
252         case CS35L36_HW_REV:
253         case CS35L36_TESTKEY_CTRL:
254         case CS35L36_USERKEY_CTL:
255         case CS35L36_OTP_MEM30:
256         case CS35L36_OTP_CTRL1:
257         case CS35L36_OTP_CTRL2:
258         case CS35L36_OTP_CTRL3:
259         case CS35L36_OTP_CTRL4:
260         case CS35L36_OTP_CTRL5:
261         case CS35L36_PAC_CTL1:
262         case CS35L36_PAC_CTL2:
263         case CS35L36_PAC_CTL3:
264         case CS35L36_DEVICE_ID:
265         case CS35L36_FAB_ID:
266         case CS35L36_REV_ID:
267         case CS35L36_PWR_CTRL1:
268         case CS35L36_PWR_CTRL2:
269         case CS35L36_PWR_CTRL3:
270         case CS35L36_CTRL_OVRRIDE:
271         case CS35L36_AMP_OUT_MUTE:
272         case CS35L36_OTP_TRIM_STATUS:
273         case CS35L36_DISCH_FILT:
274         case CS35L36_PROTECT_REL_ERR:
275         case CS35L36_PAD_INTERFACE:
276         case CS35L36_PLL_CLK_CTRL:
277         case CS35L36_GLOBAL_CLK_CTRL:
278         case CS35L36_ADC_CLK_CTRL:
279         case CS35L36_SWIRE_CLK_CTRL:
280         case CS35L36_SP_SCLK_CLK_CTRL:
281         case CS35L36_TST_FS_MON0:
282         case CS35L36_MDSYNC_EN:
283         case CS35L36_MDSYNC_TX_ID:
284         case CS35L36_MDSYNC_PWR_CTRL:
285         case CS35L36_MDSYNC_DATA_TX:
286         case CS35L36_MDSYNC_TX_STATUS:
287         case CS35L36_MDSYNC_RX_STATUS:
288         case CS35L36_MDSYNC_ERR_STATUS:
289         case CS35L36_BSTCVRT_VCTRL1:
290         case CS35L36_BSTCVRT_VCTRL2:
291         case CS35L36_BSTCVRT_PEAK_CUR:
292         case CS35L36_BSTCVRT_SFT_RAMP:
293         case CS35L36_BSTCVRT_COEFF:
294         case CS35L36_BSTCVRT_SLOPE_LBST:
295         case CS35L36_BSTCVRT_SW_FREQ:
296         case CS35L36_BSTCVRT_DCM_CTRL:
297         case CS35L36_BSTCVRT_DCM_MODE_FORCE:
298         case CS35L36_BSTCVRT_OVERVOLT_CTRL:
299         case CS35L36_BST_TST_MANUAL:
300         case CS35L36_BST_ANA2_TEST:
301         case CS35L36_VPI_LIMIT_MODE:
302         case CS35L36_VPI_LIMIT_MINMAX:
303         case CS35L36_VPI_VP_THLD:
304         case CS35L36_VPI_TRACK_CTRL:
305         case CS35L36_VPI_TRIG_MODE_CTRL:
306         case CS35L36_VPI_TRIG_STEPS:
307         case CS35L36_VI_SPKMON_FILT:
308         case CS35L36_VI_SPKMON_GAIN:
309         case CS35L36_VI_SPKMON_IP_SEL:
310         case CS35L36_DTEMP_WARN_THLD:
311         case CS35L36_DTEMP_STATUS:
312         case CS35L36_VPVBST_FS_SEL:
313         case CS35L36_VPVBST_VP_CTRL:
314         case CS35L36_VPVBST_VBST_CTRL:
315         case CS35L36_ASP_TX_PIN_CTRL:
316         case CS35L36_ASP_RATE_CTRL:
317         case CS35L36_ASP_FORMAT:
318         case CS35L36_ASP_FRAME_CTRL:
319         case CS35L36_ASP_TX1_TX2_SLOT:
320         case CS35L36_ASP_TX3_TX4_SLOT:
321         case CS35L36_ASP_TX5_TX6_SLOT:
322         case CS35L36_ASP_TX7_TX8_SLOT:
323         case CS35L36_ASP_RX1_SLOT:
324         case CS35L36_ASP_RX_TX_EN:
325         case CS35L36_ASP_RX1_SEL:
326         case CS35L36_ASP_TX1_SEL:
327         case CS35L36_ASP_TX2_SEL:
328         case CS35L36_ASP_TX3_SEL:
329         case CS35L36_ASP_TX4_SEL:
330         case CS35L36_ASP_TX5_SEL:
331         case CS35L36_ASP_TX6_SEL:
332         case CS35L36_SWIRE_P1_TX1_SEL:
333         case CS35L36_SWIRE_P1_TX2_SEL:
334         case CS35L36_SWIRE_P2_TX1_SEL:
335         case CS35L36_SWIRE_P2_TX2_SEL:
336         case CS35L36_SWIRE_P2_TX3_SEL:
337         case CS35L36_SWIRE_DP1_FIFO_CFG:
338         case CS35L36_SWIRE_DP2_FIFO_CFG:
339         case CS35L36_SWIRE_DP3_FIFO_CFG:
340         case CS35L36_SWIRE_PCM_RX_DATA:
341         case CS35L36_SWIRE_FS_SEL:
342         case CS35L36_AMP_DIG_VOL_CTRL:
343         case CS35L36_VPBR_CFG:
344         case CS35L36_VBBR_CFG:
345         case CS35L36_VPBR_STATUS:
346         case CS35L36_VBBR_STATUS:
347         case CS35L36_OVERTEMP_CFG:
348         case CS35L36_AMP_ERR_VOL:
349         case CS35L36_CLASSH_CFG:
350         case CS35L36_CLASSH_FET_DRV_CFG:
351         case CS35L36_NG_CFG:
352         case CS35L36_AMP_GAIN_CTRL:
353         case CS35L36_PWM_MOD_IO_CTRL:
354         case CS35L36_PWM_MOD_STATUS:
355         case CS35L36_DAC_MSM_CFG:
356         case CS35L36_AMP_SLOPE_CTRL:
357         case CS35L36_AMP_PDM_VOLUME:
358         case CS35L36_AMP_PDM_RATE_CTRL:
359         case CS35L36_PDM_CH_SEL:
360         case CS35L36_AMP_NG_CTRL:
361         case CS35L36_PDM_HIGHFILT_CTRL:
362         case CS35L36_INT1_STATUS:
363         case CS35L36_INT2_STATUS:
364         case CS35L36_INT3_STATUS:
365         case CS35L36_INT4_STATUS:
366         case CS35L36_INT1_RAW_STATUS:
367         case CS35L36_INT2_RAW_STATUS:
368         case CS35L36_INT3_RAW_STATUS:
369         case CS35L36_INT4_RAW_STATUS:
370         case CS35L36_INT1_MASK:
371         case CS35L36_INT2_MASK:
372         case CS35L36_INT3_MASK:
373         case CS35L36_INT4_MASK:
374         case CS35L36_INT1_EDGE_LVL_CTRL:
375         case CS35L36_INT3_EDGE_LVL_CTRL:
376         case CS35L36_PAC_INT_STATUS:
377         case CS35L36_PAC_INT_RAW_STATUS:
378         case CS35L36_PAC_INT_FLUSH_CTRL:
379         case CS35L36_PAC_INT0_CTRL:
380         case CS35L36_PAC_INT1_CTRL:
381         case CS35L36_PAC_INT2_CTRL:
382         case CS35L36_PAC_INT3_CTRL:
383         case CS35L36_PAC_INT4_CTRL:
384         case CS35L36_PAC_INT5_CTRL:
385         case CS35L36_PAC_INT6_CTRL:
386         case CS35L36_PAC_INT7_CTRL:
387                 return true;
388         default:
389                 if (reg >= CS35L36_PAC_PMEM_WORD0 &&
390                         reg <= CS35L36_PAC_PMEM_WORD1023)
391                         return true;
392                 else
393                         return false;
394         }
395 }
396 
397 static bool cs35l36_precious_reg(struct device *dev, unsigned int reg)
398 {
399         switch (reg) {
400         case CS35L36_TESTKEY_CTRL:
401         case CS35L36_USERKEY_CTL:
402         case CS35L36_TST_FS_MON0:
403                 return true;
404         default:
405                 return false;
406         }
407 }
408 
409 static bool cs35l36_volatile_reg(struct device *dev, unsigned int reg)
410 {
411         switch (reg) {
412         case CS35L36_SW_RESET:
413         case CS35L36_SW_REV:
414         case CS35L36_HW_REV:
415         case CS35L36_TESTKEY_CTRL:
416         case CS35L36_USERKEY_CTL:
417         case CS35L36_DEVICE_ID:
418         case CS35L36_FAB_ID:
419         case CS35L36_REV_ID:
420         case CS35L36_INT1_STATUS:
421         case CS35L36_INT2_STATUS:
422         case CS35L36_INT3_STATUS:
423         case CS35L36_INT4_STATUS:
424         case CS35L36_INT1_RAW_STATUS:
425         case CS35L36_INT2_RAW_STATUS:
426         case CS35L36_INT3_RAW_STATUS:
427         case CS35L36_INT4_RAW_STATUS:
428         case CS35L36_INT1_MASK:
429         case CS35L36_INT2_MASK:
430         case CS35L36_INT3_MASK:
431         case CS35L36_INT4_MASK:
432         case CS35L36_INT1_EDGE_LVL_CTRL:
433         case CS35L36_INT3_EDGE_LVL_CTRL:
434         case CS35L36_PAC_INT_STATUS:
435         case CS35L36_PAC_INT_RAW_STATUS:
436         case CS35L36_PAC_INT_FLUSH_CTRL:
437                 return true;
438         default:
439                 if (reg >= CS35L36_PAC_PMEM_WORD0 &&
440                         reg <= CS35L36_PAC_PMEM_WORD1023)
441                         return true;
442                 else
443                         return false;
444         }
445 }
446 
447 static DECLARE_TLV_DB_SCALE(dig_vol_tlv, -10200, 25, 0);
448 static DECLARE_TLV_DB_SCALE(amp_gain_tlv, 0, 1, 1);
449 
450 static const char * const cs35l36_pcm_sftramp_text[] =  {
451         "Off", ".5ms", "1ms", "2ms", "4ms", "8ms", "15ms", "30ms"};
452 
453 static SOC_ENUM_SINGLE_DECL(pcm_sft_ramp, CS35L36_AMP_DIG_VOL_CTRL, 0,
454                             cs35l36_pcm_sftramp_text);
455 
456 static int cs35l36_ldm_sel_get(struct snd_kcontrol *kcontrol,
457                                struct snd_ctl_elem_value *ucontrol)
458 {
459         struct snd_soc_component *component =
460                         snd_soc_kcontrol_component(kcontrol);
461         struct cs35l36_private *cs35l36 =
462                         snd_soc_component_get_drvdata(component);
463 
464         ucontrol->value.integer.value[0] = cs35l36->ldm_mode_sel;
465 
466         return 0;
467 }
468 
469 static int cs35l36_ldm_sel_put(struct snd_kcontrol *kcontrol,
470                                struct snd_ctl_elem_value *ucontrol)
471 {
472         struct snd_soc_component *component =
473                         snd_soc_kcontrol_component(kcontrol);
474         struct cs35l36_private *cs35l36 =
475                         snd_soc_component_get_drvdata(component);
476         int val = (ucontrol->value.integer.value[0]) ? CS35L36_NG_AMP_EN_MASK :
477                                                        0;
478 
479         cs35l36->ldm_mode_sel = val;
480 
481         regmap_update_bits(cs35l36->regmap, CS35L36_NG_CFG,
482                            CS35L36_NG_AMP_EN_MASK, val);
483 
484         return 0;
485 }
486 
487 static const struct snd_kcontrol_new cs35l36_aud_controls[] = {
488         SOC_SINGLE_SX_TLV("Digital PCM Volume", CS35L36_AMP_DIG_VOL_CTRL,
489                 3, 0x4D0, 0x390, dig_vol_tlv),
490         SOC_SINGLE_TLV("Analog PCM Volume", CS35L36_AMP_GAIN_CTRL, 5, 0x13, 0,
491                 amp_gain_tlv),
492         SOC_ENUM("PCM Soft Ramp", pcm_sft_ramp),
493         SOC_SINGLE("Amp Gain Zero-Cross Switch", CS35L36_AMP_GAIN_CTRL,
494                 CS35L36_AMP_ZC_SHIFT, 1, 0),
495         SOC_SINGLE("PDM LDM Enter Ramp Switch", CS35L36_DAC_MSM_CFG,
496                 CS35L36_PDM_LDM_ENTER_SHIFT, 1, 0),
497         SOC_SINGLE("PDM LDM Exit Ramp Switch", CS35L36_DAC_MSM_CFG,
498                 CS35L36_PDM_LDM_EXIT_SHIFT, 1, 0),
499         SOC_SINGLE_BOOL_EXT("LDM Select Switch", 0, cs35l36_ldm_sel_get,
500                 cs35l36_ldm_sel_put),
501 };
502 
503 static int cs35l36_main_amp_event(struct snd_soc_dapm_widget *w,
504                                   struct snd_kcontrol *kcontrol, int event)
505 {
506         struct snd_soc_component *component =
507                         snd_soc_dapm_to_component(w->dapm);
508         struct cs35l36_private *cs35l36 =
509                         snd_soc_component_get_drvdata(component);
510         u32 reg;
511 
512         switch (event) {
513         case SND_SOC_DAPM_POST_PMU:
514                 regmap_update_bits(cs35l36->regmap, CS35L36_PWR_CTRL1,
515                                    CS35L36_GLOBAL_EN_MASK,
516                                    1 << CS35L36_GLOBAL_EN_SHIFT);
517 
518                 usleep_range(2000, 2100);
519 
520                 regmap_read(cs35l36->regmap, CS35L36_INT4_RAW_STATUS, &reg);
521 
522                 if (WARN_ON_ONCE(reg & CS35L36_PLL_UNLOCK_MASK))
523                         dev_crit(cs35l36->dev, "PLL Unlocked\n");
524 
525                 regmap_update_bits(cs35l36->regmap, CS35L36_ASP_RX1_SEL,
526                                    CS35L36_PCM_RX_SEL_MASK,
527                                    CS35L36_PCM_RX_SEL_PCM);
528                 regmap_update_bits(cs35l36->regmap, CS35L36_AMP_OUT_MUTE,
529                                    CS35L36_AMP_MUTE_MASK,
530                                    0 << CS35L36_AMP_MUTE_SHIFT);
531                 break;
532         case SND_SOC_DAPM_PRE_PMD:
533                 regmap_update_bits(cs35l36->regmap, CS35L36_ASP_RX1_SEL,
534                                    CS35L36_PCM_RX_SEL_MASK,
535                                    CS35L36_PCM_RX_SEL_ZERO);
536                 regmap_update_bits(cs35l36->regmap, CS35L36_AMP_OUT_MUTE,
537                                    CS35L36_AMP_MUTE_MASK,
538                                    1 << CS35L36_AMP_MUTE_SHIFT);
539                 break;
540         case SND_SOC_DAPM_POST_PMD:
541                 regmap_update_bits(cs35l36->regmap, CS35L36_PWR_CTRL1,
542                                    CS35L36_GLOBAL_EN_MASK,
543                                    0 << CS35L36_GLOBAL_EN_SHIFT);
544 
545                 usleep_range(2000, 2100);
546                 break;
547         default:
548                 dev_dbg(component->dev, "Invalid event = 0x%x\n", event);
549                 return -EINVAL;
550         }
551 
552         return 0;
553 }
554 
555 static int cs35l36_boost_event(struct snd_soc_dapm_widget *w,
556                                struct snd_kcontrol *kcontrol, int event)
557 {
558         struct snd_soc_component *component =
559                         snd_soc_dapm_to_component(w->dapm);
560         struct cs35l36_private *cs35l36 =
561                         snd_soc_component_get_drvdata(component);
562 
563         switch (event) {
564         case SND_SOC_DAPM_POST_PMU:
565                 if (!cs35l36->pdata.extern_boost)
566                         regmap_update_bits(cs35l36->regmap, CS35L36_PWR_CTRL2,
567                                            CS35L36_BST_EN_MASK,
568                                            CS35L36_BST_EN <<
569                                            CS35L36_BST_EN_SHIFT);
570                 break;
571         case SND_SOC_DAPM_POST_PMD:
572                 if (!cs35l36->pdata.extern_boost)
573                         regmap_update_bits(cs35l36->regmap, CS35L36_PWR_CTRL2,
574                                            CS35L36_BST_EN_MASK,
575                                            CS35L36_BST_DIS_VP <<
576                                            CS35L36_BST_EN_SHIFT);
577                 break;
578         default:
579                 dev_dbg(component->dev, "Invalid event = 0x%x\n", event);
580                 return -EINVAL;
581         }
582 
583         return 0;
584 }
585 
586 static const char * const cs35l36_chan_text[] = {
587         "RX1",
588         "RX2",
589 };
590 
591 static SOC_ENUM_SINGLE_DECL(chansel_enum, CS35L36_ASP_RX1_SLOT, 0,
592                             cs35l36_chan_text);
593 
594 static const struct snd_kcontrol_new cs35l36_chan_mux =
595                 SOC_DAPM_ENUM("Input Mux", chansel_enum);
596 
597 static const struct snd_kcontrol_new amp_enable_ctrl =
598                 SOC_DAPM_SINGLE_AUTODISABLE("Switch", CS35L36_AMP_OUT_MUTE,
599                                             CS35L36_AMP_MUTE_SHIFT, 1, 1);
600 
601 static const struct snd_kcontrol_new boost_ctrl =
602                 SOC_DAPM_SINGLE_VIRT("Switch", 1);
603 
604 static const char * const asp_tx_src_text[] = {
605         "Zero Fill", "ASPRX1", "VMON", "IMON", "ERRVOL", "VPMON", "VBSTMON"
606 };
607 
608 static const unsigned int asp_tx_src_values[] = {
609         0x00, 0x08, 0x18, 0x19, 0x20, 0x28, 0x29
610 };
611 
612 static SOC_VALUE_ENUM_SINGLE_DECL(asp_tx1_src_enum, CS35L36_ASP_TX1_SEL, 0,
613                                   CS35L36_APS_TX_SEL_MASK, asp_tx_src_text,
614                                   asp_tx_src_values);
615 
616 static const struct snd_kcontrol_new asp_tx1_src =
617                 SOC_DAPM_ENUM("ASPTX1SRC", asp_tx1_src_enum);
618 
619 static SOC_VALUE_ENUM_SINGLE_DECL(asp_tx2_src_enum, CS35L36_ASP_TX2_SEL, 0,
620                                   CS35L36_APS_TX_SEL_MASK, asp_tx_src_text,
621                                   asp_tx_src_values);
622 
623 static const struct snd_kcontrol_new asp_tx2_src =
624                 SOC_DAPM_ENUM("ASPTX2SRC", asp_tx2_src_enum);
625 
626 static SOC_VALUE_ENUM_SINGLE_DECL(asp_tx3_src_enum, CS35L36_ASP_TX3_SEL, 0,
627                                   CS35L36_APS_TX_SEL_MASK, asp_tx_src_text,
628                                   asp_tx_src_values);
629 
630 static const struct snd_kcontrol_new asp_tx3_src =
631                 SOC_DAPM_ENUM("ASPTX3SRC", asp_tx3_src_enum);
632 
633 static SOC_VALUE_ENUM_SINGLE_DECL(asp_tx4_src_enum, CS35L36_ASP_TX4_SEL, 0,
634                                   CS35L36_APS_TX_SEL_MASK, asp_tx_src_text,
635                                   asp_tx_src_values);
636 
637 static const struct snd_kcontrol_new asp_tx4_src =
638                 SOC_DAPM_ENUM("ASPTX4SRC", asp_tx4_src_enum);
639 
640 static SOC_VALUE_ENUM_SINGLE_DECL(asp_tx5_src_enum, CS35L36_ASP_TX5_SEL, 0,
641                                   CS35L36_APS_TX_SEL_MASK, asp_tx_src_text,
642                                   asp_tx_src_values);
643 
644 static const struct snd_kcontrol_new asp_tx5_src =
645                 SOC_DAPM_ENUM("ASPTX5SRC", asp_tx5_src_enum);
646 
647 static SOC_VALUE_ENUM_SINGLE_DECL(asp_tx6_src_enum, CS35L36_ASP_TX6_SEL, 0,
648                                   CS35L36_APS_TX_SEL_MASK, asp_tx_src_text,
649                                   asp_tx_src_values);
650 
651 static const struct snd_kcontrol_new asp_tx6_src =
652                 SOC_DAPM_ENUM("ASPTX6SRC", asp_tx6_src_enum);
653 
654 static const struct snd_soc_dapm_widget cs35l36_dapm_widgets[] = {
655         SND_SOC_DAPM_MUX("Channel Mux", SND_SOC_NOPM, 0, 0, &cs35l36_chan_mux),
656         SND_SOC_DAPM_AIF_IN("SDIN", NULL, 0, CS35L36_ASP_RX_TX_EN, 16, 0),
657 
658         SND_SOC_DAPM_OUT_DRV_E("Main AMP", CS35L36_PWR_CTRL2, 0, 0, NULL, 0,
659                                cs35l36_main_amp_event, SND_SOC_DAPM_POST_PMD |
660                                SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
661 
662         SND_SOC_DAPM_OUTPUT("SPK"),
663         SND_SOC_DAPM_SWITCH("AMP Enable", SND_SOC_NOPM, 0, 1, &amp_enable_ctrl),
664         SND_SOC_DAPM_MIXER("CLASS H", CS35L36_PWR_CTRL3, 4, 0, NULL, 0),
665         SND_SOC_DAPM_SWITCH_E("BOOST Enable", SND_SOC_NOPM, 0, 0, &boost_ctrl,
666                               cs35l36_boost_event, SND_SOC_DAPM_POST_PMD |
667                               SND_SOC_DAPM_POST_PMU),
668 
669         SND_SOC_DAPM_AIF_OUT("ASPTX1", NULL, 0, CS35L36_ASP_RX_TX_EN, 0, 0),
670         SND_SOC_DAPM_AIF_OUT("ASPTX2", NULL, 1, CS35L36_ASP_RX_TX_EN, 1, 0),
671         SND_SOC_DAPM_AIF_OUT("ASPTX3", NULL, 2, CS35L36_ASP_RX_TX_EN, 2, 0),
672         SND_SOC_DAPM_AIF_OUT("ASPTX4", NULL, 3, CS35L36_ASP_RX_TX_EN, 3, 0),
673         SND_SOC_DAPM_AIF_OUT("ASPTX5", NULL, 4, CS35L36_ASP_RX_TX_EN, 4, 0),
674         SND_SOC_DAPM_AIF_OUT("ASPTX6", NULL, 5, CS35L36_ASP_RX_TX_EN, 5, 0),
675 
676         SND_SOC_DAPM_MUX("ASPTX1SRC", SND_SOC_NOPM, 0, 0, &asp_tx1_src),
677         SND_SOC_DAPM_MUX("ASPTX2SRC", SND_SOC_NOPM, 0, 0, &asp_tx2_src),
678         SND_SOC_DAPM_MUX("ASPTX3SRC", SND_SOC_NOPM, 0, 0, &asp_tx3_src),
679         SND_SOC_DAPM_MUX("ASPTX4SRC", SND_SOC_NOPM, 0, 0, &asp_tx4_src),
680         SND_SOC_DAPM_MUX("ASPTX5SRC", SND_SOC_NOPM, 0, 0, &asp_tx5_src),
681         SND_SOC_DAPM_MUX("ASPTX6SRC", SND_SOC_NOPM, 0, 0, &asp_tx6_src),
682 
683         SND_SOC_DAPM_ADC("VMON ADC", NULL, CS35L36_PWR_CTRL2, 12, 0),
684         SND_SOC_DAPM_ADC("IMON ADC", NULL, CS35L36_PWR_CTRL2, 13, 0),
685         SND_SOC_DAPM_ADC("VPMON ADC", NULL, CS35L36_PWR_CTRL2, 8, 0),
686         SND_SOC_DAPM_ADC("VBSTMON ADC", NULL, CS35L36_PWR_CTRL2, 9, 0),
687 
688         SND_SOC_DAPM_INPUT("VP"),
689         SND_SOC_DAPM_INPUT("VBST"),
690         SND_SOC_DAPM_INPUT("VSENSE"),
691 };
692 
693 static const struct snd_soc_dapm_route cs35l36_audio_map[] = {
694         {"VPMON ADC", NULL, "VP"},
695         {"VBSTMON ADC", NULL, "VBST"},
696         {"IMON ADC", NULL, "VSENSE"},
697         {"VMON ADC", NULL, "VSENSE"},
698 
699         {"ASPTX1SRC", "IMON", "IMON ADC"},
700         {"ASPTX1SRC", "VMON", "VMON ADC"},
701         {"ASPTX1SRC", "VBSTMON", "VBSTMON ADC"},
702         {"ASPTX1SRC", "VPMON", "VPMON ADC"},
703 
704         {"ASPTX2SRC", "IMON", "IMON ADC"},
705         {"ASPTX2SRC", "VMON", "VMON ADC"},
706         {"ASPTX2SRC", "VBSTMON", "VBSTMON ADC"},
707         {"ASPTX2SRC", "VPMON", "VPMON ADC"},
708 
709         {"ASPTX3SRC", "IMON", "IMON ADC"},
710         {"ASPTX3SRC", "VMON", "VMON ADC"},
711         {"ASPTX3SRC", "VBSTMON", "VBSTMON ADC"},
712         {"ASPTX3SRC", "VPMON", "VPMON ADC"},
713 
714         {"ASPTX4SRC", "IMON", "IMON ADC"},
715         {"ASPTX4SRC", "VMON", "VMON ADC"},
716         {"ASPTX4SRC", "VBSTMON", "VBSTMON ADC"},
717         {"ASPTX4SRC", "VPMON", "VPMON ADC"},
718 
719         {"ASPTX5SRC", "IMON", "IMON ADC"},
720         {"ASPTX5SRC", "VMON", "VMON ADC"},
721         {"ASPTX5SRC", "VBSTMON", "VBSTMON ADC"},
722         {"ASPTX5SRC", "VPMON", "VPMON ADC"},
723 
724         {"ASPTX6SRC", "IMON", "IMON ADC"},
725         {"ASPTX6SRC", "VMON", "VMON ADC"},
726         {"ASPTX6SRC", "VBSTMON", "VBSTMON ADC"},
727         {"ASPTX6SRC", "VPMON", "VPMON ADC"},
728 
729         {"ASPTX1", NULL, "ASPTX1SRC"},
730         {"ASPTX2", NULL, "ASPTX2SRC"},
731         {"ASPTX3", NULL, "ASPTX3SRC"},
732         {"ASPTX4", NULL, "ASPTX4SRC"},
733         {"ASPTX5", NULL, "ASPTX5SRC"},
734         {"ASPTX6", NULL, "ASPTX6SRC"},
735 
736         {"AMP Capture", NULL, "ASPTX1"},
737         {"AMP Capture", NULL, "ASPTX2"},
738         {"AMP Capture", NULL, "ASPTX3"},
739         {"AMP Capture", NULL, "ASPTX4"},
740         {"AMP Capture", NULL, "ASPTX5"},
741         {"AMP Capture", NULL, "ASPTX6"},
742 
743         {"AMP Enable", "Switch", "AMP Playback"},
744         {"SDIN", NULL, "AMP Enable"},
745         {"Channel Mux", "RX1", "SDIN"},
746         {"Channel Mux", "RX2", "SDIN"},
747         {"BOOST Enable", "Switch", "Channel Mux"},
748         {"CLASS H", NULL, "BOOST Enable"},
749         {"Main AMP", NULL, "Channel Mux"},
750         {"Main AMP", NULL, "CLASS H"},
751         {"SPK", NULL, "Main AMP"},
752 };
753 
754 static int cs35l36_set_dai_fmt(struct snd_soc_dai *component_dai,
755                                unsigned int fmt)
756 {
757         struct cs35l36_private *cs35l36 =
758                         snd_soc_component_get_drvdata(component_dai->component);
759         unsigned int asp_fmt, lrclk_fmt, sclk_fmt, slave_mode, clk_frc;
760 
761         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
762         case SND_SOC_DAIFMT_CBM_CFM:
763                 slave_mode = 1;
764                 break;
765         case SND_SOC_DAIFMT_CBS_CFS:
766                 slave_mode = 0;
767                 break;
768         default:
769                 return -EINVAL;
770         }
771 
772         regmap_update_bits(cs35l36->regmap, CS35L36_ASP_TX_PIN_CTRL,
773                                 CS35L36_SCLK_MSTR_MASK,
774                                 slave_mode << CS35L36_SCLK_MSTR_SHIFT);
775         regmap_update_bits(cs35l36->regmap, CS35L36_ASP_RATE_CTRL,
776                                 CS35L36_LRCLK_MSTR_MASK,
777                                 slave_mode << CS35L36_LRCLK_MSTR_SHIFT);
778 
779         switch (fmt & SND_SOC_DAIFMT_CLOCK_MASK) {
780         case SND_SOC_DAIFMT_CONT:
781                 clk_frc = 1;
782                 break;
783         case SND_SOC_DAIFMT_GATED:
784                 clk_frc = 0;
785                 break;
786         default:
787                 return -EINVAL;
788         }
789 
790         regmap_update_bits(cs35l36->regmap, CS35L36_ASP_TX_PIN_CTRL,
791                            CS35L36_SCLK_FRC_MASK, clk_frc <<
792                            CS35L36_SCLK_FRC_SHIFT);
793         regmap_update_bits(cs35l36->regmap, CS35L36_ASP_RATE_CTRL,
794                            CS35L36_LRCLK_FRC_MASK, clk_frc <<
795                            CS35L36_LRCLK_FRC_SHIFT);
796 
797         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
798         case SND_SOC_DAIFMT_DSP_A:
799                 asp_fmt = 0;
800                 break;
801         case SND_SOC_DAIFMT_I2S:
802                 asp_fmt = 2;
803                 break;
804         default:
805                 return -EINVAL;
806         }
807 
808         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
809         case SND_SOC_DAIFMT_NB_IF:
810                 lrclk_fmt = 1;
811                 sclk_fmt = 0;
812                 break;
813         case SND_SOC_DAIFMT_IB_NF:
814                 lrclk_fmt = 0;
815                 sclk_fmt = 1;
816                 break;
817         case SND_SOC_DAIFMT_IB_IF:
818                 lrclk_fmt = 1;
819                 sclk_fmt = 1;
820                 break;
821         case SND_SOC_DAIFMT_NB_NF:
822                 lrclk_fmt = 0;
823                 sclk_fmt = 0;
824                 break;
825         default:
826                 return -EINVAL;
827         }
828 
829         regmap_update_bits(cs35l36->regmap, CS35L36_ASP_RATE_CTRL,
830                            CS35L36_LRCLK_INV_MASK,
831                            lrclk_fmt << CS35L36_LRCLK_INV_SHIFT);
832         regmap_update_bits(cs35l36->regmap, CS35L36_ASP_TX_PIN_CTRL,
833                            CS35L36_SCLK_INV_MASK,
834                            sclk_fmt << CS35L36_SCLK_INV_SHIFT);
835         regmap_update_bits(cs35l36->regmap, CS35L36_ASP_FORMAT,
836                            CS35L36_ASP_FMT_MASK, asp_fmt);
837 
838         return 0;
839 }
840 
841 struct cs35l36_global_fs_config {
842         int rate;
843         int fs_cfg;
844 };
845 
846 static const struct cs35l36_global_fs_config cs35l36_fs_rates[] = {
847         {12000, 0x01},
848         {24000, 0x02},
849         {48000, 0x03},
850         {96000, 0x04},
851         {192000, 0x05},
852         {384000, 0x06},
853         {11025, 0x09},
854         {22050, 0x0A},
855         {44100, 0x0B},
856         {88200, 0x0C},
857         {176400, 0x0D},
858         {8000, 0x11},
859         {16000, 0x12},
860         {32000, 0x13},
861 };
862 
863 static int cs35l36_pcm_hw_params(struct snd_pcm_substream *substream,
864                                  struct snd_pcm_hw_params *params,
865                                  struct snd_soc_dai *dai)
866 {
867         struct cs35l36_private *cs35l36 =
868                         snd_soc_component_get_drvdata(dai->component);
869         unsigned int asp_width, global_fs = params_rate(params);
870         int i;
871 
872         for (i = 0; i < ARRAY_SIZE(cs35l36_fs_rates); i++) {
873                 if (global_fs == cs35l36_fs_rates[i].rate)
874                         regmap_update_bits(cs35l36->regmap,
875                                            CS35L36_GLOBAL_CLK_CTRL,
876                                            CS35L36_GLOBAL_FS_MASK,
877                                            cs35l36_fs_rates[i].fs_cfg <<
878                                            CS35L36_GLOBAL_FS_SHIFT);
879         }
880 
881         switch (params_width(params)) {
882         case 16:
883                 asp_width = CS35L36_ASP_WIDTH_16;
884                 break;
885         case 24:
886                 asp_width = CS35L36_ASP_WIDTH_24;
887                 break;
888         case 32:
889                 asp_width = CS35L36_ASP_WIDTH_32;
890                 break;
891         default:
892                 return -EINVAL;
893         }
894 
895         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
896                 regmap_update_bits(cs35l36->regmap, CS35L36_ASP_FRAME_CTRL,
897                                    CS35L36_ASP_RX_WIDTH_MASK,
898                                    asp_width << CS35L36_ASP_RX_WIDTH_SHIFT);
899         } else {
900                 regmap_update_bits(cs35l36->regmap, CS35L36_ASP_FRAME_CTRL,
901                                    CS35L36_ASP_TX_WIDTH_MASK,
902                                    asp_width << CS35L36_ASP_TX_WIDTH_SHIFT);
903         }
904 
905         return 0;
906 }
907 
908 static int cs35l36_dai_set_sysclk(struct snd_soc_dai *dai, int clk_id,
909                                   unsigned int freq, int dir)
910 {
911         struct snd_soc_component *component = dai->component;
912         struct cs35l36_private *cs35l36 =
913                         snd_soc_component_get_drvdata(component);
914         int fs1, fs2;
915 
916         if (freq > CS35L36_FS_NOM_6MHZ) {
917                 fs1 = CS35L36_FS1_DEFAULT_VAL;
918                 fs2 = CS35L36_FS2_DEFAULT_VAL;
919         } else {
920                 fs1 = 3 * ((CS35L36_FS_NOM_6MHZ * 4 + freq - 1) / freq) + 4;
921                 fs2 = 5 * ((CS35L36_FS_NOM_6MHZ * 4 + freq - 1) / freq) + 4;
922         }
923 
924         regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
925                         CS35L36_TEST_UNLOCK1);
926         regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
927                         CS35L36_TEST_UNLOCK2);
928 
929         regmap_update_bits(cs35l36->regmap, CS35L36_TST_FS_MON0,
930                            CS35L36_FS1_WINDOW_MASK | CS35L36_FS2_WINDOW_MASK,
931                            fs1 | (fs2 << CS35L36_FS2_WINDOW_SHIFT));
932 
933         regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
934                         CS35L36_TEST_LOCK1);
935         regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
936                         CS35L36_TEST_LOCK2);
937         return 0;
938 }
939 
940 static const struct cs35l36_pll_config *cs35l36_get_clk_config(
941                 struct cs35l36_private *cs35l36, int freq)
942 {
943         int i;
944 
945         for (i = 0; i < ARRAY_SIZE(cs35l36_pll_sysclk); i++) {
946                 if (cs35l36_pll_sysclk[i].freq == freq)
947                         return &cs35l36_pll_sysclk[i];
948         }
949 
950         return NULL;
951 }
952 
953 static const unsigned int cs35l36_src_rates[] = {
954         8000, 12000, 11025, 16000, 22050, 24000, 32000,
955         44100, 48000, 88200, 96000, 176400, 192000, 384000
956 };
957 
958 static const struct snd_pcm_hw_constraint_list cs35l36_constraints = {
959         .count  = ARRAY_SIZE(cs35l36_src_rates),
960         .list   = cs35l36_src_rates,
961 };
962 
963 static int cs35l36_pcm_startup(struct snd_pcm_substream *substream,
964                                struct snd_soc_dai *dai)
965 {
966         snd_pcm_hw_constraint_list(substream->runtime, 0,
967                                 SNDRV_PCM_HW_PARAM_RATE, &cs35l36_constraints);
968 
969         return 0;
970 }
971 
972 static const struct snd_soc_dai_ops cs35l36_ops = {
973         .startup = cs35l36_pcm_startup,
974         .set_fmt = cs35l36_set_dai_fmt,
975         .hw_params = cs35l36_pcm_hw_params,
976         .set_sysclk = cs35l36_dai_set_sysclk,
977 };
978 
979 static struct snd_soc_dai_driver cs35l36_dai[] = {
980         {
981                 .name = "cs35l36-pcm",
982                 .id = 0,
983                 .playback = {
984                         .stream_name = "AMP Playback",
985                         .channels_min = 1,
986                         .channels_max = 8,
987                         .rates = SNDRV_PCM_RATE_KNOT,
988                         .formats = CS35L36_RX_FORMATS,
989                 },
990                 .capture = {
991                         .stream_name = "AMP Capture",
992                         .channels_min = 1,
993                         .channels_max = 8,
994                         .rates = SNDRV_PCM_RATE_KNOT,
995                         .formats = CS35L36_TX_FORMATS,
996                 },
997                 .ops = &cs35l36_ops,
998                 .symmetric_rates = 1,
999         },
1000 };
1001 
1002 static int cs35l36_component_set_sysclk(struct snd_soc_component *component,
1003                                 int clk_id, int source, unsigned int freq,
1004                                 int dir)
1005 {
1006         struct cs35l36_private *cs35l36 =
1007                         snd_soc_component_get_drvdata(component);
1008         const struct cs35l36_pll_config *clk_cfg;
1009         int prev_clksrc;
1010         bool pdm_switch;
1011 
1012         prev_clksrc = cs35l36->clksrc;
1013 
1014         switch (clk_id) {
1015         case 0:
1016                 cs35l36->clksrc = CS35L36_PLLSRC_SCLK;
1017                 break;
1018         case 1:
1019                 cs35l36->clksrc = CS35L36_PLLSRC_LRCLK;
1020                 break;
1021         case 2:
1022                 cs35l36->clksrc = CS35L36_PLLSRC_PDMCLK;
1023                 break;
1024         case 3:
1025                 cs35l36->clksrc = CS35L36_PLLSRC_SELF;
1026                 break;
1027         case 4:
1028                 cs35l36->clksrc = CS35L36_PLLSRC_MCLK;
1029                 break;
1030         default:
1031                 return -EINVAL;
1032         }
1033 
1034         clk_cfg = cs35l36_get_clk_config(cs35l36, freq);
1035         if (clk_cfg == NULL) {
1036                 dev_err(component->dev, "Invalid CLK Config Freq: %d\n", freq);
1037                 return -EINVAL;
1038         }
1039 
1040         regmap_update_bits(cs35l36->regmap, CS35L36_PLL_CLK_CTRL,
1041                            CS35L36_PLL_OPENLOOP_MASK,
1042                            1 << CS35L36_PLL_OPENLOOP_SHIFT);
1043         regmap_update_bits(cs35l36->regmap, CS35L36_PLL_CLK_CTRL,
1044                            CS35L36_REFCLK_FREQ_MASK,
1045                            clk_cfg->clk_cfg << CS35L36_REFCLK_FREQ_SHIFT);
1046         regmap_update_bits(cs35l36->regmap, CS35L36_PLL_CLK_CTRL,
1047                            CS35L36_PLL_REFCLK_EN_MASK,
1048                            0 << CS35L36_PLL_REFCLK_EN_SHIFT);
1049         regmap_update_bits(cs35l36->regmap, CS35L36_PLL_CLK_CTRL,
1050                            CS35L36_PLL_CLK_SEL_MASK,
1051                            cs35l36->clksrc);
1052         regmap_update_bits(cs35l36->regmap, CS35L36_PLL_CLK_CTRL,
1053                            CS35L36_PLL_OPENLOOP_MASK,
1054                            0 << CS35L36_PLL_OPENLOOP_SHIFT);
1055         regmap_update_bits(cs35l36->regmap, CS35L36_PLL_CLK_CTRL,
1056                            CS35L36_PLL_REFCLK_EN_MASK,
1057                            1 << CS35L36_PLL_REFCLK_EN_SHIFT);
1058 
1059         if (cs35l36->rev_id == CS35L36_REV_A0) {
1060                 regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1061                              CS35L36_TEST_UNLOCK1);
1062                 regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1063                              CS35L36_TEST_UNLOCK2);
1064 
1065                 regmap_write(cs35l36->regmap, CS35L36_DCO_CTRL, 0x00036DA8);
1066                 regmap_write(cs35l36->regmap, CS35L36_MISC_CTRL, 0x0100EE0E);
1067 
1068                 regmap_update_bits(cs35l36->regmap, CS35L36_PLL_LOOP_PARAMS,
1069                                    CS35L36_PLL_IGAIN_MASK,
1070                                    CS35L36_PLL_IGAIN <<
1071                                    CS35L36_PLL_IGAIN_SHIFT);
1072                 regmap_update_bits(cs35l36->regmap, CS35L36_PLL_LOOP_PARAMS,
1073                                    CS35L36_PLL_FFL_IGAIN_MASK,
1074                                    clk_cfg->fll_igain);
1075 
1076                 regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1077                              CS35L36_TEST_LOCK1);
1078                 regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1079                              CS35L36_TEST_LOCK2);
1080         }
1081 
1082         if (cs35l36->clksrc == CS35L36_PLLSRC_PDMCLK) {
1083                 pdm_switch = cs35l36->ldm_mode_sel &&
1084                              (prev_clksrc != CS35L36_PLLSRC_PDMCLK);
1085 
1086                 if (pdm_switch)
1087                         regmap_update_bits(cs35l36->regmap, CS35L36_NG_CFG,
1088                                            CS35L36_NG_DELAY_MASK,
1089                                            0 << CS35L36_NG_DELAY_SHIFT);
1090 
1091                 regmap_update_bits(cs35l36->regmap, CS35L36_DAC_MSM_CFG,
1092                                    CS35L36_PDM_MODE_MASK,
1093                                    1 << CS35L36_PDM_MODE_SHIFT);
1094 
1095                 if (pdm_switch)
1096                         regmap_update_bits(cs35l36->regmap, CS35L36_NG_CFG,
1097                                            CS35L36_NG_DELAY_MASK,
1098                                            3 << CS35L36_NG_DELAY_SHIFT);
1099         } else {
1100                 pdm_switch = cs35l36->ldm_mode_sel &&
1101                              (prev_clksrc == CS35L36_PLLSRC_PDMCLK);
1102 
1103                 if (pdm_switch)
1104                         regmap_update_bits(cs35l36->regmap, CS35L36_NG_CFG,
1105                                            CS35L36_NG_DELAY_MASK,
1106                                            0 << CS35L36_NG_DELAY_SHIFT);
1107 
1108                 regmap_update_bits(cs35l36->regmap, CS35L36_DAC_MSM_CFG,
1109                                    CS35L36_PDM_MODE_MASK,
1110                                    0 << CS35L36_PDM_MODE_SHIFT);
1111 
1112                 if (pdm_switch)
1113                         regmap_update_bits(cs35l36->regmap, CS35L36_NG_CFG,
1114                                            CS35L36_NG_DELAY_MASK,
1115                                            3 << CS35L36_NG_DELAY_SHIFT);
1116         }
1117 
1118         return 0;
1119 }
1120 
1121 static int cs35l36_boost_inductor(struct cs35l36_private *cs35l36, int inductor)
1122 {
1123         regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_COEFF,
1124                            CS35L36_BSTCVRT_K1_MASK, 0x3C);
1125         regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_COEFF,
1126                            CS35L36_BSTCVRT_K2_MASK,
1127                            0x3C << CS35L36_BSTCVRT_K2_SHIFT);
1128         regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_SW_FREQ,
1129                            CS35L36_BSTCVRT_CCMFREQ_MASK, 0x00);
1130 
1131         switch (inductor) {
1132         case 1000: /* 1 uH */
1133                 regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_SLOPE_LBST,
1134                                    CS35L36_BSTCVRT_SLOPE_MASK,
1135                                    0x75 << CS35L36_BSTCVRT_SLOPE_SHIFT);
1136                 regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_SLOPE_LBST,
1137                                    CS35L36_BSTCVRT_LBSTVAL_MASK, 0x00);
1138                 break;
1139         case 1200: /* 1.2 uH */
1140                 regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_SLOPE_LBST,
1141                                    CS35L36_BSTCVRT_SLOPE_MASK,
1142                                    0x6B << CS35L36_BSTCVRT_SLOPE_SHIFT);
1143                 regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_SLOPE_LBST,
1144                                    CS35L36_BSTCVRT_LBSTVAL_MASK, 0x01);
1145                 break;
1146         default:
1147                 dev_err(cs35l36->dev, "%s Invalid Inductor Value %d uH\n",
1148                         __func__, inductor);
1149                 return -EINVAL;
1150         }
1151 
1152         return 0;
1153 }
1154 
1155 static int cs35l36_component_probe(struct snd_soc_component *component)
1156 {
1157         struct cs35l36_private *cs35l36 =
1158                         snd_soc_component_get_drvdata(component);
1159         int ret = 0;
1160 
1161         if ((cs35l36->rev_id == CS35L36_REV_A0) && cs35l36->pdata.dcm_mode) {
1162                 regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_DCM_CTRL,
1163                                    CS35L36_DCM_AUTO_MASK,
1164                                    CS35L36_DCM_AUTO_MASK);
1165 
1166                 regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1167                              CS35L36_TEST_UNLOCK1);
1168                 regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1169                              CS35L36_TEST_UNLOCK2);
1170 
1171                 regmap_update_bits(cs35l36->regmap, CS35L36_BST_TST_MANUAL,
1172                                    CS35L36_BST_MAN_IPKCOMP_MASK,
1173                                    0 << CS35L36_BST_MAN_IPKCOMP_SHIFT);
1174                 regmap_update_bits(cs35l36->regmap, CS35L36_BST_TST_MANUAL,
1175                                    CS35L36_BST_MAN_IPKCOMP_EN_MASK,
1176                                    CS35L36_BST_MAN_IPKCOMP_EN_MASK);
1177 
1178                 regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1179                                 CS35L36_TEST_LOCK1);
1180                 regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1181                                 CS35L36_TEST_LOCK2);
1182         }
1183 
1184         if (cs35l36->pdata.amp_pcm_inv)
1185                 regmap_update_bits(cs35l36->regmap, CS35L36_AMP_DIG_VOL_CTRL,
1186                                    CS35L36_AMP_PCM_INV_MASK,
1187                                    CS35L36_AMP_PCM_INV_MASK);
1188 
1189         if (cs35l36->pdata.multi_amp_mode)
1190                 regmap_update_bits(cs35l36->regmap, CS35L36_ASP_TX_PIN_CTRL,
1191                                    CS35L36_ASP_TX_HIZ_MASK,
1192                                    CS35L36_ASP_TX_HIZ_MASK);
1193 
1194         if (cs35l36->pdata.imon_pol_inv)
1195                 regmap_update_bits(cs35l36->regmap, CS35L36_VI_SPKMON_FILT,
1196                                    CS35L36_IMON_POL_MASK, 0);
1197 
1198         if (cs35l36->pdata.vmon_pol_inv)
1199                 regmap_update_bits(cs35l36->regmap, CS35L36_VI_SPKMON_FILT,
1200                                    CS35L36_VMON_POL_MASK, 0);
1201 
1202         if (cs35l36->pdata.bst_vctl)
1203                 regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_VCTRL1,
1204                                    CS35L35_BSTCVRT_CTL_MASK,
1205                                    cs35l36->pdata.bst_vctl);
1206 
1207         if (cs35l36->pdata.bst_vctl_sel)
1208                 regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_VCTRL2,
1209                                    CS35L35_BSTCVRT_CTL_SEL_MASK,
1210                                    cs35l36->pdata.bst_vctl_sel);
1211 
1212         if (cs35l36->pdata.bst_ipk)
1213                 regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_PEAK_CUR,
1214                                    CS35L36_BST_IPK_MASK,
1215                                    cs35l36->pdata.bst_ipk);
1216 
1217         if (cs35l36->pdata.boost_ind) {
1218                 ret = cs35l36_boost_inductor(cs35l36, cs35l36->pdata.boost_ind);
1219                 if (ret < 0) {
1220                         dev_err(cs35l36->dev,
1221                                 "Boost inductor config failed(%d)\n", ret);
1222                         return ret;
1223                 }
1224         }
1225 
1226         if (cs35l36->pdata.temp_warn_thld)
1227                 regmap_update_bits(cs35l36->regmap, CS35L36_DTEMP_WARN_THLD,
1228                                    CS35L36_TEMP_THLD_MASK,
1229                                    cs35l36->pdata.temp_warn_thld);
1230 
1231         if (cs35l36->pdata.irq_drv_sel)
1232                 regmap_update_bits(cs35l36->regmap, CS35L36_PAD_INTERFACE,
1233                                    CS35L36_INT_DRV_SEL_MASK,
1234                                    cs35l36->pdata.irq_drv_sel <<
1235                                    CS35L36_INT_DRV_SEL_SHIFT);
1236 
1237         if (cs35l36->pdata.irq_gpio_sel)
1238                 regmap_update_bits(cs35l36->regmap, CS35L36_PAD_INTERFACE,
1239                                    CS35L36_INT_GPIO_SEL_MASK,
1240                                    cs35l36->pdata.irq_gpio_sel <<
1241                                    CS35L36_INT_GPIO_SEL_SHIFT);
1242 
1243         /*
1244          * Rev B0 has 2 versions
1245          * L36 is 10V
1246          * L37 is 12V
1247          * If L36 we need to clamp some values for safety
1248          * after probe has setup dt values. We want to make
1249          * sure we dont miss any values set in probe
1250          */
1251         if (cs35l36->chip_version == CS35L36_10V_L36) {
1252                 regmap_update_bits(cs35l36->regmap,
1253                                    CS35L36_BSTCVRT_OVERVOLT_CTRL,
1254                                    CS35L36_BST_OVP_THLD_MASK,
1255                                    CS35L36_BST_OVP_THLD_11V);
1256 
1257                 regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1258                              CS35L36_TEST_UNLOCK1);
1259                 regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1260                              CS35L36_TEST_UNLOCK2);
1261 
1262                 regmap_update_bits(cs35l36->regmap, CS35L36_BST_ANA2_TEST,
1263                                    CS35L36_BST_OVP_TRIM_MASK,
1264                                    CS35L36_BST_OVP_TRIM_11V <<
1265                                    CS35L36_BST_OVP_TRIM_SHIFT);
1266                 regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_VCTRL2,
1267                                    CS35L36_BST_CTRL_LIM_MASK,
1268                                    1 << CS35L36_BST_CTRL_LIM_SHIFT);
1269                 regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_VCTRL1,
1270                                    CS35L35_BSTCVRT_CTL_MASK,
1271                                    CS35L36_BST_CTRL_10V_CLAMP);
1272                 regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1273                              CS35L36_TEST_LOCK1);
1274                 regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1275                              CS35L36_TEST_LOCK2);
1276         }
1277 
1278         /*
1279          * RevA and B require the disabling of
1280          * SYNC_GLOBAL_OVR when GLOBAL_EN = 0.
1281          * Just turn it off from default
1282          */
1283         regmap_update_bits(cs35l36->regmap, CS35L36_CTRL_OVRRIDE,
1284                            CS35L36_SYNC_GLOBAL_OVR_MASK,
1285                            0 << CS35L36_SYNC_GLOBAL_OVR_SHIFT);
1286 
1287         return 0;
1288 }
1289 
1290 static const struct snd_soc_component_driver soc_component_dev_cs35l36 = {
1291         .probe                  = &cs35l36_component_probe,
1292         .set_sysclk             = cs35l36_component_set_sysclk,
1293         .dapm_widgets           = cs35l36_dapm_widgets,
1294         .num_dapm_widgets       = ARRAY_SIZE(cs35l36_dapm_widgets),
1295         .dapm_routes            = cs35l36_audio_map,
1296         .num_dapm_routes        = ARRAY_SIZE(cs35l36_audio_map),
1297         .controls               = cs35l36_aud_controls,
1298         .num_controls           = ARRAY_SIZE(cs35l36_aud_controls),
1299         .idle_bias_on           = 1,
1300         .use_pmdown_time        = 1,
1301         .endianness             = 1,
1302         .non_legacy_dai_naming  = 1,
1303 };
1304 
1305 static struct regmap_config cs35l36_regmap = {
1306         .reg_bits = 32,
1307         .val_bits = 32,
1308         .reg_stride = 4,
1309         .max_register = CS35L36_PAC_PMEM_WORD1023,
1310         .reg_defaults = cs35l36_reg,
1311         .num_reg_defaults = ARRAY_SIZE(cs35l36_reg),
1312         .precious_reg = cs35l36_precious_reg,
1313         .volatile_reg = cs35l36_volatile_reg,
1314         .readable_reg = cs35l36_readable_reg,
1315         .cache_type = REGCACHE_RBTREE,
1316 };
1317 
1318 static irqreturn_t cs35l36_irq(int irq, void *data)
1319 {
1320         struct cs35l36_private *cs35l36 = data;
1321         unsigned int status[4];
1322         unsigned int masks[4];
1323         int ret = IRQ_NONE;
1324 
1325         /* ack the irq by reading all status registers */
1326         regmap_bulk_read(cs35l36->regmap, CS35L36_INT1_STATUS, status,
1327                          ARRAY_SIZE(status));
1328 
1329         regmap_bulk_read(cs35l36->regmap, CS35L36_INT1_MASK, masks,
1330                          ARRAY_SIZE(masks));
1331 
1332         /* Check to see if unmasked bits are active */
1333         if (!(status[0] & ~masks[0]) && !(status[1] & ~masks[1]) &&
1334                 !(status[2] & ~masks[2]) && !(status[3] & ~masks[3])) {
1335                 return IRQ_NONE;
1336         }
1337 
1338         /*
1339          * The following interrupts require a
1340          * protection release cycle to get the
1341          * speaker out of Safe-Mode.
1342          */
1343         if (status[2] & CS35L36_AMP_SHORT_ERR) {
1344                 dev_crit(cs35l36->dev, "Amp short error\n");
1345                 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1346                                    CS35L36_AMP_SHORT_ERR_RLS, 0);
1347                 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1348                                    CS35L36_AMP_SHORT_ERR_RLS,
1349                                    CS35L36_AMP_SHORT_ERR_RLS);
1350                 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1351                                    CS35L36_AMP_SHORT_ERR_RLS, 0);
1352                 regmap_update_bits(cs35l36->regmap, CS35L36_INT3_STATUS,
1353                                    CS35L36_AMP_SHORT_ERR,
1354                                    CS35L36_AMP_SHORT_ERR);
1355                 ret = IRQ_HANDLED;
1356         }
1357 
1358         if (status[0] & CS35L36_TEMP_WARN) {
1359                 dev_crit(cs35l36->dev, "Over temperature warning\n");
1360                 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1361                                    CS35L36_TEMP_WARN_ERR_RLS, 0);
1362                 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1363                                    CS35L36_TEMP_WARN_ERR_RLS,
1364                                    CS35L36_TEMP_WARN_ERR_RLS);
1365                 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1366                                    CS35L36_TEMP_WARN_ERR_RLS, 0);
1367                 regmap_update_bits(cs35l36->regmap, CS35L36_INT1_STATUS,
1368                                    CS35L36_TEMP_WARN, CS35L36_TEMP_WARN);
1369                 ret = IRQ_HANDLED;
1370         }
1371 
1372         if (status[0] & CS35L36_TEMP_ERR) {
1373                 dev_crit(cs35l36->dev, "Over temperature error\n");
1374                 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1375                                    CS35L36_TEMP_ERR_RLS, 0);
1376                 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1377                                    CS35L36_TEMP_ERR_RLS, CS35L36_TEMP_ERR_RLS);
1378                 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1379                                    CS35L36_TEMP_ERR_RLS, 0);
1380                 regmap_update_bits(cs35l36->regmap, CS35L36_INT1_STATUS,
1381                                    CS35L36_TEMP_ERR, CS35L36_TEMP_ERR);
1382                 ret = IRQ_HANDLED;
1383         }
1384 
1385         if (status[0] & CS35L36_BST_OVP_ERR) {
1386                 dev_crit(cs35l36->dev, "VBST Over Voltage error\n");
1387                 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1388                                    CS35L36_TEMP_ERR_RLS, 0);
1389                 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1390                                    CS35L36_TEMP_ERR_RLS, CS35L36_TEMP_ERR_RLS);
1391                 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1392                                    CS35L36_TEMP_ERR_RLS, 0);
1393                 regmap_update_bits(cs35l36->regmap, CS35L36_INT1_STATUS,
1394                                    CS35L36_BST_OVP_ERR, CS35L36_BST_OVP_ERR);
1395                 ret = IRQ_HANDLED;
1396         }
1397 
1398         if (status[0] & CS35L36_BST_DCM_UVP_ERR) {
1399                 dev_crit(cs35l36->dev, "DCM VBST Under Voltage Error\n");
1400                 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1401                                    CS35L36_BST_UVP_ERR_RLS, 0);
1402                 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1403                                    CS35L36_BST_UVP_ERR_RLS,
1404                                    CS35L36_BST_UVP_ERR_RLS);
1405                 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1406                                    CS35L36_BST_UVP_ERR_RLS, 0);
1407                 regmap_update_bits(cs35l36->regmap, CS35L36_INT1_STATUS,
1408                                    CS35L36_BST_DCM_UVP_ERR,
1409                                    CS35L36_BST_DCM_UVP_ERR);
1410                 ret = IRQ_HANDLED;
1411         }
1412 
1413         if (status[0] & CS35L36_BST_SHORT_ERR) {
1414                 dev_crit(cs35l36->dev, "LBST SHORT error!\n");
1415                 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1416                                    CS35L36_BST_SHORT_ERR_RLS, 0);
1417                 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1418                                    CS35L36_BST_SHORT_ERR_RLS,
1419                                    CS35L36_BST_SHORT_ERR_RLS);
1420                 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1421                                    CS35L36_BST_SHORT_ERR_RLS, 0);
1422                 regmap_update_bits(cs35l36->regmap, CS35L36_INT1_STATUS,
1423                                    CS35L36_BST_SHORT_ERR,
1424                                    CS35L36_BST_SHORT_ERR);
1425                 ret = IRQ_HANDLED;
1426         }
1427 
1428         return ret;
1429 }
1430 
1431 static int cs35l36_handle_of_data(struct i2c_client *i2c_client,
1432                                 struct cs35l36_platform_data *pdata)
1433 {
1434         struct device_node *np = i2c_client->dev.of_node;
1435         struct cs35l36_vpbr_cfg *vpbr_config = &pdata->vpbr_config;
1436         struct device_node *vpbr_node;
1437         unsigned int val;
1438         int ret;
1439 
1440         if (!np)
1441                 return 0;
1442 
1443         ret = of_property_read_u32(np, "cirrus,boost-ctl-millivolt", &val);
1444         if (!ret) {
1445                 if (val < 2550 || val > 12000) {
1446                         dev_err(&i2c_client->dev,
1447                                 "Invalid Boost Voltage %d mV\n", val);
1448                         return -EINVAL;
1449                 }
1450                 pdata->bst_vctl = (((val - 2550) / 100) + 1) << 1;
1451         } else {
1452                 dev_err(&i2c_client->dev,
1453                         "Unable to find required parameter 'cirrus,boost-ctl-millivolt'");
1454                 return -EINVAL;
1455         }
1456 
1457         ret = of_property_read_u32(np, "cirrus,boost-ctl-select", &val);
1458         if (!ret)
1459                 pdata->bst_vctl_sel = val | CS35L36_VALID_PDATA;
1460 
1461         ret = of_property_read_u32(np, "cirrus,boost-peak-milliamp", &val);
1462         if (!ret) {
1463                 if (val < 1600 || val > 4500) {
1464                         dev_err(&i2c_client->dev,
1465                                 "Invalid Boost Peak Current %u mA\n", val);
1466                         return -EINVAL;
1467                 }
1468 
1469                 pdata->bst_ipk = (val - 1600) / 50;
1470         } else {
1471                 dev_err(&i2c_client->dev,
1472                         "Unable to find required parameter 'cirrus,boost-peak-milliamp'");
1473                 return -EINVAL;
1474         }
1475 
1476         pdata->multi_amp_mode = of_property_read_bool(np,
1477                                         "cirrus,multi-amp-mode");
1478 
1479         pdata->dcm_mode = of_property_read_bool(np,
1480                                         "cirrus,dcm-mode-enable");
1481 
1482         pdata->amp_pcm_inv = of_property_read_bool(np,
1483                                         "cirrus,amp-pcm-inv");
1484 
1485         pdata->imon_pol_inv = of_property_read_bool(np,
1486                                         "cirrus,imon-pol-inv");
1487 
1488         pdata->vmon_pol_inv = of_property_read_bool(np,
1489                                         "cirrus,vmon-pol-inv");
1490 
1491         if (of_property_read_u32(np, "cirrus,temp-warn-threshold", &val) >= 0)
1492                 pdata->temp_warn_thld = val | CS35L36_VALID_PDATA;
1493 
1494         if (of_property_read_u32(np, "cirrus,boost-ind-nanohenry", &val) >= 0) {
1495                 pdata->boost_ind = val;
1496         } else {
1497                 dev_err(&i2c_client->dev, "Inductor not specified.\n");
1498                 return -EINVAL;
1499         }
1500 
1501         if (of_property_read_u32(np, "cirrus,irq-drive-select", &val) >= 0)
1502                 pdata->irq_drv_sel = val | CS35L36_VALID_PDATA;
1503 
1504         if (of_property_read_u32(np, "cirrus,irq-gpio-select", &val) >= 0)
1505                 pdata->irq_gpio_sel = val | CS35L36_VALID_PDATA;
1506 
1507         /* VPBR Config */
1508         vpbr_node = of_get_child_by_name(np, "cirrus,vpbr-config");
1509         vpbr_config->is_present = vpbr_node ? true : false;
1510         if (vpbr_config->is_present) {
1511                 if (of_property_read_u32(vpbr_node, "cirrus,vpbr-en",
1512                                          &val) >= 0)
1513                         vpbr_config->vpbr_en = val;
1514                 if (of_property_read_u32(vpbr_node, "cirrus,vpbr-thld",
1515                                          &val) >= 0)
1516                         vpbr_config->vpbr_thld = val;
1517                 if (of_property_read_u32(vpbr_node, "cirrus,vpbr-atk-rate",
1518                                          &val) >= 0)
1519                         vpbr_config->vpbr_atk_rate = val;
1520                 if (of_property_read_u32(vpbr_node, "cirrus,vpbr-atk-vol",
1521                                          &val) >= 0)
1522                         vpbr_config->vpbr_atk_vol = val;
1523                 if (of_property_read_u32(vpbr_node, "cirrus,vpbr-max-attn",
1524                                          &val) >= 0)
1525                         vpbr_config->vpbr_max_attn = val;
1526                 if (of_property_read_u32(vpbr_node, "cirrus,vpbr-wait",
1527                                          &val) >= 0)
1528                         vpbr_config->vpbr_wait = val;
1529                 if (of_property_read_u32(vpbr_node, "cirrus,vpbr-rel-rate",
1530                                          &val) >= 0)
1531                         vpbr_config->vpbr_rel_rate = val;
1532                 if (of_property_read_u32(vpbr_node, "cirrus,vpbr-mute-en",
1533                                          &val) >= 0)
1534                         vpbr_config->vpbr_mute_en = val;
1535         }
1536         of_node_put(vpbr_node);
1537 
1538         return 0;
1539 }
1540 
1541 static int cs35l36_pac(struct cs35l36_private *cs35l36)
1542 {
1543         int ret, count;
1544         unsigned int val;
1545 
1546         if (cs35l36->rev_id != CS35L36_REV_B0)
1547                 return 0;
1548 
1549         /*
1550          * Magic code for internal PAC
1551          */
1552         regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1553                      CS35L36_TEST_UNLOCK1);
1554         regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1555                      CS35L36_TEST_UNLOCK2);
1556 
1557         usleep_range(9500, 10500);
1558 
1559         regmap_write(cs35l36->regmap, CS35L36_PAC_CTL1,
1560                      CS35L36_PAC_RESET);
1561         regmap_write(cs35l36->regmap, CS35L36_PAC_CTL3,
1562                      CS35L36_PAC_MEM_ACCESS);
1563         regmap_write(cs35l36->regmap, CS35L36_PAC_PMEM_WORD0,
1564                      CS35L36_B0_PAC_PATCH);
1565 
1566         regmap_write(cs35l36->regmap, CS35L36_PAC_CTL3,
1567                      CS35L36_PAC_MEM_ACCESS_CLR);
1568         regmap_write(cs35l36->regmap, CS35L36_PAC_CTL1,
1569                      CS35L36_PAC_ENABLE_MASK);
1570 
1571         usleep_range(9500, 10500);
1572 
1573         ret = regmap_read(cs35l36->regmap, CS35L36_INT4_STATUS, &val);
1574         if (ret < 0) {
1575                 dev_err(cs35l36->dev, "Failed to read int4_status %d\n", ret);
1576                 return ret;
1577         }
1578 
1579         count = 0;
1580         while (!(val & CS35L36_MCU_CONFIG_CLR)) {
1581                 usleep_range(100, 200);
1582                 count++;
1583 
1584                 ret = regmap_read(cs35l36->regmap, CS35L36_INT4_STATUS,
1585                                   &val);
1586                 if (ret < 0) {
1587                         dev_err(cs35l36->dev, "Failed to read int4_status %d\n",
1588                                 ret);
1589                         return ret;
1590                 }
1591 
1592                 if (count >= 100)
1593                         return -EINVAL;
1594         }
1595 
1596         regmap_write(cs35l36->regmap, CS35L36_INT4_STATUS,
1597                      CS35L36_MCU_CONFIG_CLR);
1598         regmap_update_bits(cs35l36->regmap, CS35L36_PAC_CTL1,
1599                            CS35L36_PAC_ENABLE_MASK, 0);
1600 
1601         regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1602                      CS35L36_TEST_LOCK1);
1603         regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1604                      CS35L36_TEST_LOCK2);
1605 
1606         return 0;
1607 }
1608 
1609 static void cs35l36_apply_vpbr_config(struct cs35l36_private *cs35l36)
1610 {
1611         struct cs35l36_platform_data *pdata = &cs35l36->pdata;
1612         struct cs35l36_vpbr_cfg *vpbr_config = &pdata->vpbr_config;
1613 
1614         regmap_update_bits(cs35l36->regmap, CS35L36_PWR_CTRL3,
1615                            CS35L36_VPBR_EN_MASK,
1616                            vpbr_config->vpbr_en <<
1617                            CS35L36_VPBR_EN_SHIFT);
1618         regmap_update_bits(cs35l36->regmap, CS35L36_VPBR_CFG,
1619                            CS35L36_VPBR_THLD_MASK,
1620                            vpbr_config->vpbr_thld <<
1621                            CS35L36_VPBR_THLD_SHIFT);
1622         regmap_update_bits(cs35l36->regmap, CS35L36_VPBR_CFG,
1623                            CS35L36_VPBR_MAX_ATTN_MASK,
1624                            vpbr_config->vpbr_max_attn <<
1625                            CS35L36_VPBR_MAX_ATTN_SHIFT);
1626         regmap_update_bits(cs35l36->regmap, CS35L36_VPBR_CFG,
1627                            CS35L36_VPBR_ATK_VOL_MASK,
1628                            vpbr_config->vpbr_atk_vol <<
1629                            CS35L36_VPBR_ATK_VOL_SHIFT);
1630         regmap_update_bits(cs35l36->regmap, CS35L36_VPBR_CFG,
1631                            CS35L36_VPBR_ATK_RATE_MASK,
1632                            vpbr_config->vpbr_atk_rate <<
1633                            CS35L36_VPBR_ATK_RATE_SHIFT);
1634         regmap_update_bits(cs35l36->regmap, CS35L36_VPBR_CFG,
1635                            CS35L36_VPBR_WAIT_MASK,
1636                            vpbr_config->vpbr_wait <<
1637                            CS35L36_VPBR_WAIT_SHIFT);
1638         regmap_update_bits(cs35l36->regmap, CS35L36_VPBR_CFG,
1639                            CS35L36_VPBR_REL_RATE_MASK,
1640                            vpbr_config->vpbr_rel_rate <<
1641                            CS35L36_VPBR_REL_RATE_SHIFT);
1642         regmap_update_bits(cs35l36->regmap, CS35L36_VPBR_CFG,
1643                            CS35L36_VPBR_MUTE_EN_MASK,
1644                            vpbr_config->vpbr_mute_en <<
1645                            CS35L36_VPBR_MUTE_EN_SHIFT);
1646 }
1647 
1648 static const struct reg_sequence cs35l36_reva0_errata_patch[] = {
1649         { CS35L36_TESTKEY_CTRL,         CS35L36_TEST_UNLOCK1 },
1650         { CS35L36_TESTKEY_CTRL,         CS35L36_TEST_UNLOCK2 },
1651         /* Errata Writes */
1652         { CS35L36_OTP_CTRL1,            0x00002060 },
1653         { CS35L36_OTP_CTRL2,            0x00000001 },
1654         { CS35L36_OTP_CTRL1,            0x00002460 },
1655         { CS35L36_OTP_CTRL2,            0x00000001 },
1656         { 0x00002088,                   0x012A1838 },
1657         { 0x00003014,                   0x0100EE0E },
1658         { 0x00003008,                   0x0008184A },
1659         { 0x00007418,                   0x509001C8 },
1660         { 0x00007064,                   0x0929A800 },
1661         { 0x00002D10,                   0x0002C01C },
1662         { 0x0000410C,                   0x00000A11 },
1663         { 0x00006E08,                   0x8B19140C },
1664         { 0x00006454,                   0x0300000A },
1665         { CS35L36_AMP_NG_CTRL,          0x000020EF },
1666         { 0x00007E34,                   0x0000000E },
1667         { 0x0000410C,                   0x00000A11 },
1668         { 0x00007410,                   0x20514B00 },
1669         /* PAC Config */
1670         { CS35L36_CTRL_OVRRIDE,         0x00000000 },
1671         { CS35L36_PAC_INT0_CTRL,        0x00860001 },
1672         { CS35L36_PAC_INT1_CTRL,        0x00860001 },
1673         { CS35L36_PAC_INT2_CTRL,        0x00860001 },
1674         { CS35L36_PAC_INT3_CTRL,        0x00860001 },
1675         { CS35L36_PAC_INT4_CTRL,        0x00860001 },
1676         { CS35L36_PAC_INT5_CTRL,        0x00860001 },
1677         { CS35L36_PAC_INT6_CTRL,        0x00860001 },
1678         { CS35L36_PAC_INT7_CTRL,        0x00860001 },
1679         { CS35L36_PAC_INT_FLUSH_CTRL,   0x000000FF },
1680         { CS35L36_TESTKEY_CTRL,         CS35L36_TEST_LOCK1 },
1681         { CS35L36_TESTKEY_CTRL,         CS35L36_TEST_LOCK2 },
1682 };
1683 
1684 static const struct reg_sequence cs35l36_revb0_errata_patch[] = {
1685         { CS35L36_TESTKEY_CTRL, CS35L36_TEST_UNLOCK1 },
1686         { CS35L36_TESTKEY_CTRL, CS35L36_TEST_UNLOCK2 },
1687         { 0x00007064,           0x0929A800 },
1688         { 0x00007850,           0x00002FA9 },
1689         { 0x00007854,           0x0003F1D5 },
1690         { 0x00007858,           0x0003F5E3 },
1691         { 0x0000785C,           0x00001137 },
1692         { 0x00007860,           0x0001A7A5 },
1693         { 0x00007864,           0x0002F16A },
1694         { 0x00007868,           0x00003E21 },
1695         { 0x00007848,           0x00000001 },
1696         { 0x00003854,           0x05180240 },
1697         { 0x00007418,           0x509001C8 },
1698         { 0x0000394C,           0x028764BD },
1699         { CS35L36_TESTKEY_CTRL, CS35L36_TEST_LOCK1 },
1700         { CS35L36_TESTKEY_CTRL, CS35L36_TEST_LOCK2 },
1701 };
1702 
1703 static int cs35l36_i2c_probe(struct i2c_client *i2c_client,
1704                               const struct i2c_device_id *id)
1705 {
1706         struct cs35l36_private *cs35l36;
1707         struct device *dev = &i2c_client->dev;
1708         struct cs35l36_platform_data *pdata = dev_get_platdata(dev);
1709         struct irq_data *irq_d;
1710         int ret, irq_pol, chip_irq_pol, i;
1711         u32 reg_id, reg_revid, l37_id_reg;
1712 
1713         cs35l36 = devm_kzalloc(dev, sizeof(struct cs35l36_private), GFP_KERNEL);
1714         if (!cs35l36)
1715                 return -ENOMEM;
1716 
1717         cs35l36->dev = dev;
1718 
1719         i2c_set_clientdata(i2c_client, cs35l36);
1720         cs35l36->regmap = devm_regmap_init_i2c(i2c_client, &cs35l36_regmap);
1721         if (IS_ERR(cs35l36->regmap)) {
1722                 ret = PTR_ERR(cs35l36->regmap);
1723                 dev_err(dev, "regmap_init() failed: %d\n", ret);
1724                 goto err;
1725         }
1726 
1727         cs35l36->num_supplies = ARRAY_SIZE(cs35l36_supplies);
1728         for (i = 0; i < ARRAY_SIZE(cs35l36_supplies); i++)
1729                 cs35l36->supplies[i].supply = cs35l36_supplies[i];
1730 
1731         ret = devm_regulator_bulk_get(dev, cs35l36->num_supplies,
1732                                       cs35l36->supplies);
1733         if (ret != 0) {
1734                 dev_err(dev, "Failed to request core supplies: %d\n", ret);
1735                 return ret;
1736         }
1737 
1738         if (pdata) {
1739                 cs35l36->pdata = *pdata;
1740         } else {
1741                 pdata = devm_kzalloc(dev, sizeof(struct cs35l36_platform_data),
1742                                      GFP_KERNEL);
1743                 if (!pdata)
1744                         return -ENOMEM;
1745 
1746                 if (i2c_client->dev.of_node) {
1747                         ret = cs35l36_handle_of_data(i2c_client, pdata);
1748                         if (ret != 0)
1749                                 return ret;
1750 
1751                 }
1752 
1753                 cs35l36->pdata = *pdata;
1754         }
1755 
1756         ret = regulator_bulk_enable(cs35l36->num_supplies, cs35l36->supplies);
1757         if (ret != 0) {
1758                 dev_err(dev, "Failed to enable core supplies: %d\n", ret);
1759                 return ret;
1760         }
1761 
1762         /* returning NULL can be an option if in stereo mode */
1763         cs35l36->reset_gpio = devm_gpiod_get_optional(dev, "reset",
1764                                                       GPIOD_OUT_LOW);
1765         if (IS_ERR(cs35l36->reset_gpio)) {
1766                 ret = PTR_ERR(cs35l36->reset_gpio);
1767                 cs35l36->reset_gpio = NULL;
1768                 if (ret == -EBUSY) {
1769                         dev_info(dev, "Reset line busy, assuming shared reset\n");
1770                 } else {
1771                         dev_err(dev, "Failed to get reset GPIO: %d\n", ret);
1772                         goto err_disable_regs;
1773                 }
1774         }
1775 
1776         if (cs35l36->reset_gpio)
1777                 gpiod_set_value_cansleep(cs35l36->reset_gpio, 1);
1778 
1779         usleep_range(2000, 2100);
1780 
1781         /* initialize amplifier */
1782         ret = regmap_read(cs35l36->regmap, CS35L36_SW_RESET, &reg_id);
1783         if (ret < 0) {
1784                 dev_err(dev, "Get Device ID failed %d\n", ret);
1785                 goto err;
1786         }
1787 
1788         if (reg_id != CS35L36_CHIP_ID) {
1789                 dev_err(dev, "Device ID (%X). Expected ID %X\n", reg_id,
1790                         CS35L36_CHIP_ID);
1791                 ret = -ENODEV;
1792                 goto err;
1793         }
1794 
1795         ret = regmap_read(cs35l36->regmap, CS35L36_REV_ID, &reg_revid);
1796         if (ret < 0) {
1797                 dev_err(&i2c_client->dev, "Get Revision ID failed %d\n", ret);
1798                 goto err;
1799         }
1800 
1801         cs35l36->rev_id = reg_revid >> 8;
1802 
1803         ret = regmap_read(cs35l36->regmap, CS35L36_OTP_MEM30, &l37_id_reg);
1804         if (ret < 0) {
1805                 dev_err(&i2c_client->dev, "Failed to read otp_id Register %d\n",
1806                         ret);
1807                 return ret;
1808         }
1809 
1810         if ((l37_id_reg & CS35L36_OTP_REV_MASK) == CS35L36_OTP_REV_L37)
1811                 cs35l36->chip_version = CS35L36_12V_L37;
1812         else
1813                 cs35l36->chip_version = CS35L36_10V_L36;
1814 
1815         switch (cs35l36->rev_id) {
1816         case CS35L36_REV_A0:
1817                 ret = regmap_register_patch(cs35l36->regmap,
1818                                 cs35l36_reva0_errata_patch,
1819                                 ARRAY_SIZE(cs35l36_reva0_errata_patch));
1820                 if (ret < 0) {
1821                         dev_err(dev, "Failed to apply A0 errata patch %d\n",
1822                                 ret);
1823                         goto err;
1824                 }
1825                 break;
1826         case CS35L36_REV_B0:
1827                 ret = cs35l36_pac(cs35l36);
1828                 if (ret < 0) {
1829                         dev_err(dev, "Failed to Trim OTP %d\n", ret);
1830                         goto err;
1831                 }
1832 
1833                 ret = regmap_register_patch(cs35l36->regmap,
1834                                 cs35l36_revb0_errata_patch,
1835                                 ARRAY_SIZE(cs35l36_revb0_errata_patch));
1836                 if (ret < 0) {
1837                         dev_err(dev, "Failed to apply B0 errata patch %d\n",
1838                                 ret);
1839                         goto err;
1840                 }
1841                 break;
1842         }
1843 
1844         if (pdata->vpbr_config.is_present)
1845                 cs35l36_apply_vpbr_config(cs35l36);
1846 
1847         irq_d = irq_get_irq_data(i2c_client->irq);
1848         if (!irq_d) {
1849                 dev_err(&i2c_client->dev, "Invalid IRQ: %d\n", i2c_client->irq);
1850                 ret = -ENODEV;
1851                 goto err;
1852         }
1853 
1854         irq_pol = irqd_get_trigger_type(irq_d);
1855 
1856         switch (irq_pol) {
1857         case IRQF_TRIGGER_FALLING:
1858         case IRQF_TRIGGER_LOW:
1859                 chip_irq_pol = 0;
1860                 break;
1861         case IRQF_TRIGGER_RISING:
1862         case IRQF_TRIGGER_HIGH:
1863                 chip_irq_pol = 1;
1864                 break;
1865         default:
1866                 dev_err(cs35l36->dev, "Invalid IRQ polarity: %d\n", irq_pol);
1867                 ret = -EINVAL;
1868                 goto err;
1869         }
1870 
1871         regmap_update_bits(cs35l36->regmap, CS35L36_PAD_INTERFACE,
1872                            CS35L36_INT_POL_SEL_MASK,
1873                            chip_irq_pol << CS35L36_INT_POL_SEL_SHIFT);
1874 
1875         ret = devm_request_threaded_irq(dev, i2c_client->irq, NULL, cs35l36_irq,
1876                                         IRQF_ONESHOT | irq_pol, "cs35l36",
1877                                         cs35l36);
1878         if (ret != 0) {
1879                 dev_err(dev, "Failed to request IRQ: %d\n", ret);
1880                 goto err;
1881         }
1882 
1883         regmap_update_bits(cs35l36->regmap, CS35L36_PAD_INTERFACE,
1884                            CS35L36_INT_OUTPUT_EN_MASK, 1);
1885 
1886         /* Set interrupt masks for critical errors */
1887         regmap_write(cs35l36->regmap, CS35L36_INT1_MASK,
1888                      CS35L36_INT1_MASK_DEFAULT);
1889         regmap_write(cs35l36->regmap, CS35L36_INT3_MASK,
1890                      CS35L36_INT3_MASK_DEFAULT);
1891 
1892         dev_info(&i2c_client->dev, "Cirrus Logic CS35L%d, Revision: %02X\n",
1893                  cs35l36->chip_version, reg_revid >> 8);
1894 
1895         ret =  devm_snd_soc_register_component(dev, &soc_component_dev_cs35l36,
1896                                                cs35l36_dai,
1897                                                ARRAY_SIZE(cs35l36_dai));
1898         if (ret < 0) {
1899                 dev_err(dev, "%s: Register component failed %d\n", __func__,
1900                         ret);
1901                 goto err;
1902         }
1903 
1904         return 0;
1905 
1906 err:
1907         gpiod_set_value_cansleep(cs35l36->reset_gpio, 0);
1908 
1909 err_disable_regs:
1910         regulator_bulk_disable(cs35l36->num_supplies, cs35l36->supplies);
1911         return ret;
1912 }
1913 
1914 static int cs35l36_i2c_remove(struct i2c_client *client)
1915 {
1916         struct cs35l36_private *cs35l36 = i2c_get_clientdata(client);
1917 
1918         /* Reset interrupt masks for device removal */
1919         regmap_write(cs35l36->regmap, CS35L36_INT1_MASK,
1920                      CS35L36_INT1_MASK_RESET);
1921         regmap_write(cs35l36->regmap, CS35L36_INT3_MASK,
1922                      CS35L36_INT3_MASK_RESET);
1923 
1924         if (cs35l36->reset_gpio)
1925                 gpiod_set_value_cansleep(cs35l36->reset_gpio, 0);
1926 
1927         regulator_bulk_disable(cs35l36->num_supplies, cs35l36->supplies);
1928 
1929         return 0;
1930 }
1931 static const struct of_device_id cs35l36_of_match[] = {
1932         {.compatible = "cirrus,cs35l36"},
1933         {},
1934 };
1935 MODULE_DEVICE_TABLE(of, cs35l36_of_match);
1936 
1937 static const struct i2c_device_id cs35l36_id[] = {
1938         {"cs35l36", 0},
1939         {}
1940 };
1941 
1942 MODULE_DEVICE_TABLE(i2c, cs35l36_id);
1943 
1944 static struct i2c_driver cs35l36_i2c_driver = {
1945         .driver = {
1946                 .name = "cs35l36",
1947                 .of_match_table = cs35l36_of_match,
1948         },
1949         .id_table = cs35l36_id,
1950         .probe = cs35l36_i2c_probe,
1951         .remove = cs35l36_i2c_remove,
1952 };
1953 module_i2c_driver(cs35l36_i2c_driver);
1954 
1955 MODULE_DESCRIPTION("ASoC CS35L36 driver");
1956 MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <james.schulman@cirrus.com>");
1957 MODULE_LICENSE("GPL");
1958 

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