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TOMOYO Linux Cross Reference
Linux/sound/soc/codecs/cs4271.c

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  1 /*
  2  * CS4271 ASoC codec driver
  3  *
  4  * Copyright (c) 2010 Alexander Sverdlin <subaparts@yandex.ru>
  5  *
  6  * This program is free software; you can redistribute it and/or
  7  * modify it under the terms of the GNU General Public License
  8  * as published by the Free Software Foundation; either version 2
  9  * of the License, or (at your option) any later version.
 10  *
 11  * This program is distributed in the hope that it will be useful,
 12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 14  * GNU General Public License for more details.
 15  *
 16  * This driver support CS4271 codec being master or slave, working
 17  * in control port mode, connected either via SPI or I2C.
 18  * The data format accepted is I2S or left-justified.
 19  * DAPM support not implemented.
 20  */
 21 
 22 #include <linux/module.h>
 23 #include <linux/slab.h>
 24 #include <linux/delay.h>
 25 #include <sound/pcm.h>
 26 #include <sound/soc.h>
 27 #include <sound/tlv.h>
 28 #include <linux/gpio.h>
 29 #include <linux/i2c.h>
 30 #include <linux/spi/spi.h>
 31 #include <sound/cs4271.h>
 32 
 33 #define CS4271_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
 34                             SNDRV_PCM_FMTBIT_S24_LE | \
 35                             SNDRV_PCM_FMTBIT_S32_LE)
 36 #define CS4271_PCM_RATES SNDRV_PCM_RATE_8000_192000
 37 
 38 /*
 39  * CS4271 registers
 40  * High byte represents SPI chip address (0x10) + write command (0)
 41  * Low byte - codec register address
 42  */
 43 #define CS4271_MODE1    0x2001  /* Mode Control 1 */
 44 #define CS4271_DACCTL   0x2002  /* DAC Control */
 45 #define CS4271_DACVOL   0x2003  /* DAC Volume & Mixing Control */
 46 #define CS4271_VOLA     0x2004  /* DAC Channel A Volume Control */
 47 #define CS4271_VOLB     0x2005  /* DAC Channel B Volume Control */
 48 #define CS4271_ADCCTL   0x2006  /* ADC Control */
 49 #define CS4271_MODE2    0x2007  /* Mode Control 2 */
 50 #define CS4271_CHIPID   0x2008  /* Chip ID */
 51 
 52 #define CS4271_FIRSTREG CS4271_MODE1
 53 #define CS4271_LASTREG  CS4271_MODE2
 54 #define CS4271_NR_REGS  ((CS4271_LASTREG & 0xFF) + 1)
 55 
 56 /* Bit masks for the CS4271 registers */
 57 #define CS4271_MODE1_MODE_MASK  0xC0
 58 #define CS4271_MODE1_MODE_1X    0x00
 59 #define CS4271_MODE1_MODE_2X    0x80
 60 #define CS4271_MODE1_MODE_4X    0xC0
 61 
 62 #define CS4271_MODE1_DIV_MASK   0x30
 63 #define CS4271_MODE1_DIV_1      0x00
 64 #define CS4271_MODE1_DIV_15     0x10
 65 #define CS4271_MODE1_DIV_2      0x20
 66 #define CS4271_MODE1_DIV_3      0x30
 67 
 68 #define CS4271_MODE1_MASTER     0x08
 69 
 70 #define CS4271_MODE1_DAC_DIF_MASK       0x07
 71 #define CS4271_MODE1_DAC_DIF_LJ         0x00
 72 #define CS4271_MODE1_DAC_DIF_I2S        0x01
 73 #define CS4271_MODE1_DAC_DIF_RJ16       0x02
 74 #define CS4271_MODE1_DAC_DIF_RJ24       0x03
 75 #define CS4271_MODE1_DAC_DIF_RJ20       0x04
 76 #define CS4271_MODE1_DAC_DIF_RJ18       0x05
 77 
 78 #define CS4271_DACCTL_AMUTE     0x80
 79 #define CS4271_DACCTL_IF_SLOW   0x40
 80 
 81 #define CS4271_DACCTL_DEM_MASK  0x30
 82 #define CS4271_DACCTL_DEM_DIS   0x00
 83 #define CS4271_DACCTL_DEM_441   0x10
 84 #define CS4271_DACCTL_DEM_48    0x20
 85 #define CS4271_DACCTL_DEM_32    0x30
 86 
 87 #define CS4271_DACCTL_SVRU      0x08
 88 #define CS4271_DACCTL_SRD       0x04
 89 #define CS4271_DACCTL_INVA      0x02
 90 #define CS4271_DACCTL_INVB      0x01
 91 
 92 #define CS4271_DACVOL_BEQUA     0x40
 93 #define CS4271_DACVOL_SOFT      0x20
 94 #define CS4271_DACVOL_ZEROC     0x10
 95 
 96 #define CS4271_DACVOL_ATAPI_MASK        0x0F
 97 #define CS4271_DACVOL_ATAPI_M_M         0x00
 98 #define CS4271_DACVOL_ATAPI_M_BR        0x01
 99 #define CS4271_DACVOL_ATAPI_M_BL        0x02
100 #define CS4271_DACVOL_ATAPI_M_BLR2      0x03
101 #define CS4271_DACVOL_ATAPI_AR_M        0x04
102 #define CS4271_DACVOL_ATAPI_AR_BR       0x05
103 #define CS4271_DACVOL_ATAPI_AR_BL       0x06
104 #define CS4271_DACVOL_ATAPI_AR_BLR2     0x07
105 #define CS4271_DACVOL_ATAPI_AL_M        0x08
106 #define CS4271_DACVOL_ATAPI_AL_BR       0x09
107 #define CS4271_DACVOL_ATAPI_AL_BL       0x0A
108 #define CS4271_DACVOL_ATAPI_AL_BLR2     0x0B
109 #define CS4271_DACVOL_ATAPI_ALR2_M      0x0C
110 #define CS4271_DACVOL_ATAPI_ALR2_BR     0x0D
111 #define CS4271_DACVOL_ATAPI_ALR2_BL     0x0E
112 #define CS4271_DACVOL_ATAPI_ALR2_BLR2   0x0F
113 
114 #define CS4271_VOLA_MUTE        0x80
115 #define CS4271_VOLA_VOL_MASK    0x7F
116 #define CS4271_VOLB_MUTE        0x80
117 #define CS4271_VOLB_VOL_MASK    0x7F
118 
119 #define CS4271_ADCCTL_DITHER16  0x20
120 
121 #define CS4271_ADCCTL_ADC_DIF_MASK      0x10
122 #define CS4271_ADCCTL_ADC_DIF_LJ        0x00
123 #define CS4271_ADCCTL_ADC_DIF_I2S       0x10
124 
125 #define CS4271_ADCCTL_MUTEA     0x08
126 #define CS4271_ADCCTL_MUTEB     0x04
127 #define CS4271_ADCCTL_HPFDA     0x02
128 #define CS4271_ADCCTL_HPFDB     0x01
129 
130 #define CS4271_MODE2_LOOP       0x10
131 #define CS4271_MODE2_MUTECAEQUB 0x08
132 #define CS4271_MODE2_FREEZE     0x04
133 #define CS4271_MODE2_CPEN       0x02
134 #define CS4271_MODE2_PDN        0x01
135 
136 #define CS4271_CHIPID_PART_MASK 0xF0
137 #define CS4271_CHIPID_REV_MASK  0x0F
138 
139 /*
140  * Default CS4271 power-up configuration
141  * Array contains non-existing in hw register at address 0
142  * Array do not include Chip ID, as codec driver does not use
143  * registers read operations at all
144  */
145 static const u8 cs4271_dflt_reg[CS4271_NR_REGS] = {
146         0,
147         0,
148         CS4271_DACCTL_AMUTE,
149         CS4271_DACVOL_SOFT | CS4271_DACVOL_ATAPI_AL_BR,
150         0,
151         0,
152         0,
153         0,
154 };
155 
156 struct cs4271_private {
157         /* SND_SOC_I2C or SND_SOC_SPI */
158         enum snd_soc_control_type       bus_type;
159         unsigned int                    mclk;
160         bool                            master;
161         bool                            deemph;
162         /* Current sample rate for de-emphasis control */
163         int                             rate;
164         /* GPIO driving Reset pin, if any */
165         int                             gpio_nreset;
166         /* GPIO that disable serial bus, if any */
167         int                             gpio_disable;
168 };
169 
170 /*
171  * @freq is the desired MCLK rate
172  * MCLK rate should (c) be the sample rate, multiplied by one of the
173  * ratios listed in cs4271_mclk_fs_ratios table
174  */
175 static int cs4271_set_dai_sysclk(struct snd_soc_dai *codec_dai,
176                                  int clk_id, unsigned int freq, int dir)
177 {
178         struct snd_soc_codec *codec = codec_dai->codec;
179         struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
180 
181         cs4271->mclk = freq;
182         return 0;
183 }
184 
185 static int cs4271_set_dai_fmt(struct snd_soc_dai *codec_dai,
186                               unsigned int format)
187 {
188         struct snd_soc_codec *codec = codec_dai->codec;
189         struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
190         unsigned int val = 0;
191         int ret;
192 
193         switch (format & SND_SOC_DAIFMT_MASTER_MASK) {
194         case SND_SOC_DAIFMT_CBS_CFS:
195                 cs4271->master = 0;
196                 break;
197         case SND_SOC_DAIFMT_CBM_CFM:
198                 cs4271->master = 1;
199                 val |= CS4271_MODE1_MASTER;
200                 break;
201         default:
202                 dev_err(codec->dev, "Invalid DAI format\n");
203                 return -EINVAL;
204         }
205 
206         switch (format & SND_SOC_DAIFMT_FORMAT_MASK) {
207         case SND_SOC_DAIFMT_LEFT_J:
208                 val |= CS4271_MODE1_DAC_DIF_LJ;
209                 ret = snd_soc_update_bits(codec, CS4271_ADCCTL,
210                         CS4271_ADCCTL_ADC_DIF_MASK, CS4271_ADCCTL_ADC_DIF_LJ);
211                 if (ret < 0)
212                         return ret;
213                 break;
214         case SND_SOC_DAIFMT_I2S:
215                 val |= CS4271_MODE1_DAC_DIF_I2S;
216                 ret = snd_soc_update_bits(codec, CS4271_ADCCTL,
217                         CS4271_ADCCTL_ADC_DIF_MASK, CS4271_ADCCTL_ADC_DIF_I2S);
218                 if (ret < 0)
219                         return ret;
220                 break;
221         default:
222                 dev_err(codec->dev, "Invalid DAI format\n");
223                 return -EINVAL;
224         }
225 
226         ret = snd_soc_update_bits(codec, CS4271_MODE1,
227                 CS4271_MODE1_DAC_DIF_MASK | CS4271_MODE1_MASTER, val);
228         if (ret < 0)
229                 return ret;
230         return 0;
231 }
232 
233 static int cs4271_deemph[] = {0, 44100, 48000, 32000};
234 
235 static int cs4271_set_deemph(struct snd_soc_codec *codec)
236 {
237         struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
238         int i, ret;
239         int val = CS4271_DACCTL_DEM_DIS;
240 
241         if (cs4271->deemph) {
242                 /* Find closest de-emphasis freq */
243                 val = 1;
244                 for (i = 2; i < ARRAY_SIZE(cs4271_deemph); i++)
245                         if (abs(cs4271_deemph[i] - cs4271->rate) <
246                             abs(cs4271_deemph[val] - cs4271->rate))
247                                 val = i;
248                 val <<= 4;
249         }
250 
251         ret = snd_soc_update_bits(codec, CS4271_DACCTL,
252                 CS4271_DACCTL_DEM_MASK, val);
253         if (ret < 0)
254                 return ret;
255         return 0;
256 }
257 
258 static int cs4271_get_deemph(struct snd_kcontrol *kcontrol,
259                              struct snd_ctl_elem_value *ucontrol)
260 {
261         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
262         struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
263 
264         ucontrol->value.integer.value[0] = cs4271->deemph;
265         return 0;
266 }
267 
268 static int cs4271_put_deemph(struct snd_kcontrol *kcontrol,
269                              struct snd_ctl_elem_value *ucontrol)
270 {
271         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
272         struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
273 
274         cs4271->deemph = ucontrol->value.integer.value[0];
275         return cs4271_set_deemph(codec);
276 }
277 
278 struct cs4271_clk_cfg {
279         bool            master;         /* codec mode */
280         u8              speed_mode;     /* codec speed mode: 1x, 2x, 4x */
281         unsigned short  ratio;          /* MCLK / sample rate */
282         u8              ratio_mask;     /* ratio bit mask for Master mode */
283 };
284 
285 static struct cs4271_clk_cfg cs4271_clk_tab[] = {
286         {1, CS4271_MODE1_MODE_1X, 256,  CS4271_MODE1_DIV_1},
287         {1, CS4271_MODE1_MODE_1X, 384,  CS4271_MODE1_DIV_15},
288         {1, CS4271_MODE1_MODE_1X, 512,  CS4271_MODE1_DIV_2},
289         {1, CS4271_MODE1_MODE_1X, 768,  CS4271_MODE1_DIV_3},
290         {1, CS4271_MODE1_MODE_2X, 128,  CS4271_MODE1_DIV_1},
291         {1, CS4271_MODE1_MODE_2X, 192,  CS4271_MODE1_DIV_15},
292         {1, CS4271_MODE1_MODE_2X, 256,  CS4271_MODE1_DIV_2},
293         {1, CS4271_MODE1_MODE_2X, 384,  CS4271_MODE1_DIV_3},
294         {1, CS4271_MODE1_MODE_4X, 64,   CS4271_MODE1_DIV_1},
295         {1, CS4271_MODE1_MODE_4X, 96,   CS4271_MODE1_DIV_15},
296         {1, CS4271_MODE1_MODE_4X, 128,  CS4271_MODE1_DIV_2},
297         {1, CS4271_MODE1_MODE_4X, 192,  CS4271_MODE1_DIV_3},
298         {0, CS4271_MODE1_MODE_1X, 256,  CS4271_MODE1_DIV_1},
299         {0, CS4271_MODE1_MODE_1X, 384,  CS4271_MODE1_DIV_1},
300         {0, CS4271_MODE1_MODE_1X, 512,  CS4271_MODE1_DIV_1},
301         {0, CS4271_MODE1_MODE_1X, 768,  CS4271_MODE1_DIV_2},
302         {0, CS4271_MODE1_MODE_1X, 1024, CS4271_MODE1_DIV_2},
303         {0, CS4271_MODE1_MODE_2X, 128,  CS4271_MODE1_DIV_1},
304         {0, CS4271_MODE1_MODE_2X, 192,  CS4271_MODE1_DIV_1},
305         {0, CS4271_MODE1_MODE_2X, 256,  CS4271_MODE1_DIV_1},
306         {0, CS4271_MODE1_MODE_2X, 384,  CS4271_MODE1_DIV_2},
307         {0, CS4271_MODE1_MODE_2X, 512,  CS4271_MODE1_DIV_2},
308         {0, CS4271_MODE1_MODE_4X, 64,   CS4271_MODE1_DIV_1},
309         {0, CS4271_MODE1_MODE_4X, 96,   CS4271_MODE1_DIV_1},
310         {0, CS4271_MODE1_MODE_4X, 128,  CS4271_MODE1_DIV_1},
311         {0, CS4271_MODE1_MODE_4X, 192,  CS4271_MODE1_DIV_2},
312         {0, CS4271_MODE1_MODE_4X, 256,  CS4271_MODE1_DIV_2},
313 };
314 
315 #define CS4171_NR_RATIOS ARRAY_SIZE(cs4271_clk_tab)
316 
317 static int cs4271_hw_params(struct snd_pcm_substream *substream,
318                             struct snd_pcm_hw_params *params,
319                             struct snd_soc_dai *dai)
320 {
321         struct snd_soc_pcm_runtime *rtd = substream->private_data;
322         struct snd_soc_codec *codec = rtd->codec;
323         struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
324         int i, ret;
325         unsigned int ratio, val;
326 
327         cs4271->rate = params_rate(params);
328 
329         /* Configure DAC */
330         if (cs4271->rate < 50000)
331                 val = CS4271_MODE1_MODE_1X;
332         else if (cs4271->rate < 100000)
333                 val = CS4271_MODE1_MODE_2X;
334         else
335                 val = CS4271_MODE1_MODE_4X;
336 
337         ratio = cs4271->mclk / cs4271->rate;
338         for (i = 0; i < CS4171_NR_RATIOS; i++)
339                 if ((cs4271_clk_tab[i].master == cs4271->master) &&
340                     (cs4271_clk_tab[i].speed_mode == val) &&
341                     (cs4271_clk_tab[i].ratio == ratio))
342                         break;
343 
344         if (i == CS4171_NR_RATIOS) {
345                 dev_err(codec->dev, "Invalid sample rate\n");
346                 return -EINVAL;
347         }
348 
349         val |= cs4271_clk_tab[i].ratio_mask;
350 
351         ret = snd_soc_update_bits(codec, CS4271_MODE1,
352                 CS4271_MODE1_MODE_MASK | CS4271_MODE1_DIV_MASK, val);
353         if (ret < 0)
354                 return ret;
355 
356         return cs4271_set_deemph(codec);
357 }
358 
359 static int cs4271_digital_mute(struct snd_soc_dai *dai, int mute)
360 {
361         struct snd_soc_codec *codec = dai->codec;
362         int ret;
363         int val_a = 0;
364         int val_b = 0;
365 
366         if (mute) {
367                 val_a = CS4271_VOLA_MUTE;
368                 val_b = CS4271_VOLB_MUTE;
369         }
370 
371         ret = snd_soc_update_bits(codec, CS4271_VOLA, CS4271_VOLA_MUTE, val_a);
372         if (ret < 0)
373                 return ret;
374         ret = snd_soc_update_bits(codec, CS4271_VOLB, CS4271_VOLB_MUTE, val_b);
375         if (ret < 0)
376                 return ret;
377 
378         return 0;
379 }
380 
381 /* CS4271 controls */
382 static DECLARE_TLV_DB_SCALE(cs4271_dac_tlv, -12700, 100, 0);
383 
384 static const struct snd_kcontrol_new cs4271_snd_controls[] = {
385         SOC_DOUBLE_R_TLV("Master Playback Volume", CS4271_VOLA, CS4271_VOLB,
386                 0, 0x7F, 1, cs4271_dac_tlv),
387         SOC_SINGLE("Digital Loopback Switch", CS4271_MODE2, 4, 1, 0),
388         SOC_SINGLE("Soft Ramp Switch", CS4271_DACVOL, 5, 1, 0),
389         SOC_SINGLE("Zero Cross Switch", CS4271_DACVOL, 4, 1, 0),
390         SOC_SINGLE_BOOL_EXT("De-emphasis Switch", 0,
391                 cs4271_get_deemph, cs4271_put_deemph),
392         SOC_SINGLE("Auto-Mute Switch", CS4271_DACCTL, 7, 1, 0),
393         SOC_SINGLE("Slow Roll Off Filter Switch", CS4271_DACCTL, 6, 1, 0),
394         SOC_SINGLE("Soft Volume Ramp-Up Switch", CS4271_DACCTL, 3, 1, 0),
395         SOC_SINGLE("Soft Ramp-Down Switch", CS4271_DACCTL, 2, 1, 0),
396         SOC_SINGLE("Left Channel Inversion Switch", CS4271_DACCTL, 1, 1, 0),
397         SOC_SINGLE("Right Channel Inversion Switch", CS4271_DACCTL, 0, 1, 0),
398         SOC_DOUBLE("Master Capture Switch", CS4271_ADCCTL, 3, 2, 1, 1),
399         SOC_SINGLE("Dither 16-Bit Data Switch", CS4271_ADCCTL, 5, 1, 0),
400         SOC_DOUBLE("High Pass Filter Switch", CS4271_ADCCTL, 1, 0, 1, 1),
401         SOC_DOUBLE_R("Master Playback Switch", CS4271_VOLA, CS4271_VOLB,
402                 7, 1, 1),
403 };
404 
405 static const struct snd_soc_dai_ops cs4271_dai_ops = {
406         .hw_params      = cs4271_hw_params,
407         .set_sysclk     = cs4271_set_dai_sysclk,
408         .set_fmt        = cs4271_set_dai_fmt,
409         .digital_mute   = cs4271_digital_mute,
410 };
411 
412 static struct snd_soc_dai_driver cs4271_dai = {
413         .name = "cs4271-hifi",
414         .playback = {
415                 .stream_name    = "Playback",
416                 .channels_min   = 2,
417                 .channels_max   = 2,
418                 .rates          = CS4271_PCM_RATES,
419                 .formats        = CS4271_PCM_FORMATS,
420         },
421         .capture = {
422                 .stream_name    = "Capture",
423                 .channels_min   = 2,
424                 .channels_max   = 2,
425                 .rates          = CS4271_PCM_RATES,
426                 .formats        = CS4271_PCM_FORMATS,
427         },
428         .ops = &cs4271_dai_ops,
429         .symmetric_rates = 1,
430 };
431 
432 #ifdef CONFIG_PM
433 static int cs4271_soc_suspend(struct snd_soc_codec *codec)
434 {
435         int ret;
436         /* Set power-down bit */
437         ret = snd_soc_update_bits(codec, CS4271_MODE2, CS4271_MODE2_PDN,
438                                   CS4271_MODE2_PDN);
439         if (ret < 0)
440                 return ret;
441         return 0;
442 }
443 
444 static int cs4271_soc_resume(struct snd_soc_codec *codec)
445 {
446         int ret;
447         /* Restore codec state */
448         ret = snd_soc_cache_sync(codec);
449         if (ret < 0)
450                 return ret;
451         /* then disable the power-down bit */
452         ret = snd_soc_update_bits(codec, CS4271_MODE2, CS4271_MODE2_PDN, 0);
453         if (ret < 0)
454                 return ret;
455         return 0;
456 }
457 #else
458 #define cs4271_soc_suspend      NULL
459 #define cs4271_soc_resume       NULL
460 #endif /* CONFIG_PM */
461 
462 static int cs4271_probe(struct snd_soc_codec *codec)
463 {
464         struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
465         struct cs4271_platform_data *cs4271plat = codec->dev->platform_data;
466         int ret;
467         int gpio_nreset = -EINVAL;
468 
469         if (cs4271plat && gpio_is_valid(cs4271plat->gpio_nreset))
470                 gpio_nreset = cs4271plat->gpio_nreset;
471 
472         if (gpio_nreset >= 0)
473                 if (gpio_request(gpio_nreset, "CS4271 Reset"))
474                         gpio_nreset = -EINVAL;
475         if (gpio_nreset >= 0) {
476                 /* Reset codec */
477                 gpio_direction_output(gpio_nreset, 0);
478                 mdelay(1);
479                 gpio_set_value(gpio_nreset, 1);
480                 /* Give the codec time to wake up */
481                 mdelay(1);
482         }
483 
484         cs4271->gpio_nreset = gpio_nreset;
485 
486         /*
487          * In case of I2C, chip address specified in board data.
488          * So cache IO operations use 8 bit codec register address.
489          * In case of SPI, chip address and register address
490          * passed together as 16 bit value.
491          * Anyway, register address is masked with 0xFF inside
492          * soc-cache code.
493          */
494         if (cs4271->bus_type == SND_SOC_SPI)
495                 ret = snd_soc_codec_set_cache_io(codec, 16, 8,
496                         cs4271->bus_type);
497         else
498                 ret = snd_soc_codec_set_cache_io(codec, 8, 8,
499                         cs4271->bus_type);
500         if (ret) {
501                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
502                 return ret;
503         }
504 
505         ret = snd_soc_update_bits(codec, CS4271_MODE2,
506                                   CS4271_MODE2_PDN | CS4271_MODE2_CPEN,
507                                   CS4271_MODE2_PDN | CS4271_MODE2_CPEN);
508         if (ret < 0)
509                 return ret;
510         ret = snd_soc_update_bits(codec, CS4271_MODE2, CS4271_MODE2_PDN, 0);
511         if (ret < 0)
512                 return ret;
513         /* Power-up sequence requires 85 uS */
514         udelay(85);
515 
516         return snd_soc_add_codec_controls(codec, cs4271_snd_controls,
517                 ARRAY_SIZE(cs4271_snd_controls));
518 }
519 
520 static int cs4271_remove(struct snd_soc_codec *codec)
521 {
522         struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
523         int gpio_nreset;
524 
525         gpio_nreset = cs4271->gpio_nreset;
526 
527         if (gpio_is_valid(gpio_nreset)) {
528                 /* Set codec to the reset state */
529                 gpio_set_value(gpio_nreset, 0);
530                 gpio_free(gpio_nreset);
531         }
532 
533         return 0;
534 };
535 
536 static struct snd_soc_codec_driver soc_codec_dev_cs4271 = {
537         .probe                  = cs4271_probe,
538         .remove                 = cs4271_remove,
539         .suspend                = cs4271_soc_suspend,
540         .resume                 = cs4271_soc_resume,
541         .reg_cache_default      = cs4271_dflt_reg,
542         .reg_cache_size         = ARRAY_SIZE(cs4271_dflt_reg),
543         .reg_word_size          = sizeof(cs4271_dflt_reg[0]),
544         .compress_type          = SND_SOC_FLAT_COMPRESSION,
545 };
546 
547 #if defined(CONFIG_SPI_MASTER)
548 static int __devinit cs4271_spi_probe(struct spi_device *spi)
549 {
550         struct cs4271_private *cs4271;
551 
552         cs4271 = devm_kzalloc(&spi->dev, sizeof(*cs4271), GFP_KERNEL);
553         if (!cs4271)
554                 return -ENOMEM;
555 
556         spi_set_drvdata(spi, cs4271);
557         cs4271->bus_type = SND_SOC_SPI;
558 
559         return snd_soc_register_codec(&spi->dev, &soc_codec_dev_cs4271,
560                 &cs4271_dai, 1);
561 }
562 
563 static int __devexit cs4271_spi_remove(struct spi_device *spi)
564 {
565         snd_soc_unregister_codec(&spi->dev);
566         return 0;
567 }
568 
569 static struct spi_driver cs4271_spi_driver = {
570         .driver = {
571                 .name   = "cs4271",
572                 .owner  = THIS_MODULE,
573         },
574         .probe          = cs4271_spi_probe,
575         .remove         = __devexit_p(cs4271_spi_remove),
576 };
577 #endif /* defined(CONFIG_SPI_MASTER) */
578 
579 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
580 static const struct i2c_device_id cs4271_i2c_id[] = {
581         {"cs4271", 0},
582         {}
583 };
584 MODULE_DEVICE_TABLE(i2c, cs4271_i2c_id);
585 
586 static int __devinit cs4271_i2c_probe(struct i2c_client *client,
587                                       const struct i2c_device_id *id)
588 {
589         struct cs4271_private *cs4271;
590 
591         cs4271 = devm_kzalloc(&client->dev, sizeof(*cs4271), GFP_KERNEL);
592         if (!cs4271)
593                 return -ENOMEM;
594 
595         i2c_set_clientdata(client, cs4271);
596         cs4271->bus_type = SND_SOC_I2C;
597 
598         return snd_soc_register_codec(&client->dev, &soc_codec_dev_cs4271,
599                 &cs4271_dai, 1);
600 }
601 
602 static int __devexit cs4271_i2c_remove(struct i2c_client *client)
603 {
604         snd_soc_unregister_codec(&client->dev);
605         return 0;
606 }
607 
608 static struct i2c_driver cs4271_i2c_driver = {
609         .driver = {
610                 .name   = "cs4271",
611                 .owner  = THIS_MODULE,
612         },
613         .id_table       = cs4271_i2c_id,
614         .probe          = cs4271_i2c_probe,
615         .remove         = __devexit_p(cs4271_i2c_remove),
616 };
617 #endif /* defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) */
618 
619 /*
620  * We only register our serial bus driver here without
621  * assignment to particular chip. So if any of the below
622  * fails, there is some problem with I2C or SPI subsystem.
623  * In most cases this module will be compiled with support
624  * of only one serial bus.
625  */
626 static int __init cs4271_modinit(void)
627 {
628         int ret;
629 
630 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
631         ret = i2c_add_driver(&cs4271_i2c_driver);
632         if (ret) {
633                 pr_err("Failed to register CS4271 I2C driver: %d\n", ret);
634                 return ret;
635         }
636 #endif
637 
638 #if defined(CONFIG_SPI_MASTER)
639         ret = spi_register_driver(&cs4271_spi_driver);
640         if (ret) {
641                 pr_err("Failed to register CS4271 SPI driver: %d\n", ret);
642                 return ret;
643         }
644 #endif
645 
646         return 0;
647 }
648 module_init(cs4271_modinit);
649 
650 static void __exit cs4271_modexit(void)
651 {
652 #if defined(CONFIG_SPI_MASTER)
653         spi_unregister_driver(&cs4271_spi_driver);
654 #endif
655 
656 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
657         i2c_del_driver(&cs4271_i2c_driver);
658 #endif
659 }
660 module_exit(cs4271_modexit);
661 
662 MODULE_AUTHOR("Alexander Sverdlin <subaparts@yandex.ru>");
663 MODULE_DESCRIPTION("Cirrus Logic CS4271 ALSA SoC Codec Driver");
664 MODULE_LICENSE("GPL");
665 

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