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TOMOYO Linux Cross Reference
Linux/sound/soc/codecs/cs42l42.c

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  1 // SPDX-License-Identifier: GPL-2.0-only
  2 /*
  3  * cs42l42.c -- CS42L42 ALSA SoC audio driver
  4  *
  5  * Copyright 2016 Cirrus Logic, Inc.
  6  *
  7  * Author: James Schulman <james.schulman@cirrus.com>
  8  * Author: Brian Austin <brian.austin@cirrus.com>
  9  * Author: Michael White <michael.white@cirrus.com>
 10  */
 11 
 12 #include <linux/module.h>
 13 #include <linux/moduleparam.h>
 14 #include <linux/version.h>
 15 #include <linux/kernel.h>
 16 #include <linux/init.h>
 17 #include <linux/delay.h>
 18 #include <linux/i2c.h>
 19 #include <linux/gpio.h>
 20 #include <linux/regmap.h>
 21 #include <linux/slab.h>
 22 #include <linux/acpi.h>
 23 #include <linux/platform_device.h>
 24 #include <linux/property.h>
 25 #include <linux/regulator/consumer.h>
 26 #include <linux/gpio/consumer.h>
 27 #include <linux/of_device.h>
 28 #include <sound/core.h>
 29 #include <sound/pcm.h>
 30 #include <sound/pcm_params.h>
 31 #include <sound/soc.h>
 32 #include <sound/soc-dapm.h>
 33 #include <sound/initval.h>
 34 #include <sound/tlv.h>
 35 #include <dt-bindings/sound/cs42l42.h>
 36 
 37 #include "cs42l42.h"
 38 #include "cirrus_legacy.h"
 39 
 40 static const struct reg_default cs42l42_reg_defaults[] = {
 41         { CS42L42_FRZ_CTL,                      0x00 },
 42         { CS42L42_SRC_CTL,                      0x10 },
 43         { CS42L42_MCLK_CTL,                     0x02 },
 44         { CS42L42_SFTRAMP_RATE,                 0xA4 },
 45         { CS42L42_I2C_DEBOUNCE,                 0x88 },
 46         { CS42L42_I2C_STRETCH,                  0x03 },
 47         { CS42L42_I2C_TIMEOUT,                  0xB7 },
 48         { CS42L42_PWR_CTL1,                     0xFF },
 49         { CS42L42_PWR_CTL2,                     0x84 },
 50         { CS42L42_PWR_CTL3,                     0x20 },
 51         { CS42L42_RSENSE_CTL1,                  0x40 },
 52         { CS42L42_RSENSE_CTL2,                  0x00 },
 53         { CS42L42_OSC_SWITCH,                   0x00 },
 54         { CS42L42_RSENSE_CTL3,                  0x1B },
 55         { CS42L42_TSENSE_CTL,                   0x1B },
 56         { CS42L42_TSRS_INT_DISABLE,             0x00 },
 57         { CS42L42_HSDET_CTL1,                   0x77 },
 58         { CS42L42_HSDET_CTL2,                   0x00 },
 59         { CS42L42_HS_SWITCH_CTL,                0xF3 },
 60         { CS42L42_HS_CLAMP_DISABLE,             0x00 },
 61         { CS42L42_MCLK_SRC_SEL,                 0x00 },
 62         { CS42L42_SPDIF_CLK_CFG,                0x00 },
 63         { CS42L42_FSYNC_PW_LOWER,               0x00 },
 64         { CS42L42_FSYNC_PW_UPPER,               0x00 },
 65         { CS42L42_FSYNC_P_LOWER,                0xF9 },
 66         { CS42L42_FSYNC_P_UPPER,                0x00 },
 67         { CS42L42_ASP_CLK_CFG,                  0x00 },
 68         { CS42L42_ASP_FRM_CFG,                  0x10 },
 69         { CS42L42_FS_RATE_EN,                   0x00 },
 70         { CS42L42_IN_ASRC_CLK,                  0x00 },
 71         { CS42L42_OUT_ASRC_CLK,                 0x00 },
 72         { CS42L42_PLL_DIV_CFG1,                 0x00 },
 73         { CS42L42_ADC_OVFL_INT_MASK,            0x01 },
 74         { CS42L42_MIXER_INT_MASK,               0x0F },
 75         { CS42L42_SRC_INT_MASK,                 0x0F },
 76         { CS42L42_ASP_RX_INT_MASK,              0x1F },
 77         { CS42L42_ASP_TX_INT_MASK,              0x0F },
 78         { CS42L42_CODEC_INT_MASK,               0x03 },
 79         { CS42L42_SRCPL_INT_MASK,               0x7F },
 80         { CS42L42_VPMON_INT_MASK,               0x01 },
 81         { CS42L42_PLL_LOCK_INT_MASK,            0x01 },
 82         { CS42L42_TSRS_PLUG_INT_MASK,           0x0F },
 83         { CS42L42_PLL_CTL1,                     0x00 },
 84         { CS42L42_PLL_DIV_FRAC0,                0x00 },
 85         { CS42L42_PLL_DIV_FRAC1,                0x00 },
 86         { CS42L42_PLL_DIV_FRAC2,                0x00 },
 87         { CS42L42_PLL_DIV_INT,                  0x40 },
 88         { CS42L42_PLL_CTL3,                     0x10 },
 89         { CS42L42_PLL_CAL_RATIO,                0x80 },
 90         { CS42L42_PLL_CTL4,                     0x03 },
 91         { CS42L42_LOAD_DET_EN,                  0x00 },
 92         { CS42L42_HSBIAS_SC_AUTOCTL,            0x03 },
 93         { CS42L42_WAKE_CTL,                     0xC0 },
 94         { CS42L42_ADC_DISABLE_MUTE,             0x00 },
 95         { CS42L42_TIPSENSE_CTL,                 0x02 },
 96         { CS42L42_MISC_DET_CTL,                 0x03 },
 97         { CS42L42_MIC_DET_CTL1,                 0x1F },
 98         { CS42L42_MIC_DET_CTL2,                 0x2F },
 99         { CS42L42_DET_INT1_MASK,                0xE0 },
100         { CS42L42_DET_INT2_MASK,                0xFF },
101         { CS42L42_HS_BIAS_CTL,                  0xC2 },
102         { CS42L42_ADC_CTL,                      0x00 },
103         { CS42L42_ADC_VOLUME,                   0x00 },
104         { CS42L42_ADC_WNF_HPF_CTL,              0x71 },
105         { CS42L42_DAC_CTL1,                     0x00 },
106         { CS42L42_DAC_CTL2,                     0x02 },
107         { CS42L42_HP_CTL,                       0x0D },
108         { CS42L42_CLASSH_CTL,                   0x07 },
109         { CS42L42_MIXER_CHA_VOL,                0x3F },
110         { CS42L42_MIXER_ADC_VOL,                0x3F },
111         { CS42L42_MIXER_CHB_VOL,                0x3F },
112         { CS42L42_EQ_COEF_IN0,                  0x00 },
113         { CS42L42_EQ_COEF_IN1,                  0x00 },
114         { CS42L42_EQ_COEF_IN2,                  0x00 },
115         { CS42L42_EQ_COEF_IN3,                  0x00 },
116         { CS42L42_EQ_COEF_RW,                   0x00 },
117         { CS42L42_EQ_COEF_OUT0,                 0x00 },
118         { CS42L42_EQ_COEF_OUT1,                 0x00 },
119         { CS42L42_EQ_COEF_OUT2,                 0x00 },
120         { CS42L42_EQ_COEF_OUT3,                 0x00 },
121         { CS42L42_EQ_INIT_STAT,                 0x00 },
122         { CS42L42_EQ_START_FILT,                0x00 },
123         { CS42L42_EQ_MUTE_CTL,                  0x00 },
124         { CS42L42_SP_RX_CH_SEL,                 0x04 },
125         { CS42L42_SP_RX_ISOC_CTL,               0x04 },
126         { CS42L42_SP_RX_FS,                     0x8C },
127         { CS42l42_SPDIF_CH_SEL,                 0x0E },
128         { CS42L42_SP_TX_ISOC_CTL,               0x04 },
129         { CS42L42_SP_TX_FS,                     0xCC },
130         { CS42L42_SPDIF_SW_CTL1,                0x3F },
131         { CS42L42_SRC_SDIN_FS,                  0x40 },
132         { CS42L42_SRC_SDOUT_FS,                 0x40 },
133         { CS42L42_SPDIF_CTL1,                   0x01 },
134         { CS42L42_SPDIF_CTL2,                   0x00 },
135         { CS42L42_SPDIF_CTL3,                   0x00 },
136         { CS42L42_SPDIF_CTL4,                   0x42 },
137         { CS42L42_ASP_TX_SZ_EN,                 0x00 },
138         { CS42L42_ASP_TX_CH_EN,                 0x00 },
139         { CS42L42_ASP_TX_CH_AP_RES,             0x0F },
140         { CS42L42_ASP_TX_CH1_BIT_MSB,           0x00 },
141         { CS42L42_ASP_TX_CH1_BIT_LSB,           0x00 },
142         { CS42L42_ASP_TX_HIZ_DLY_CFG,           0x00 },
143         { CS42L42_ASP_TX_CH2_BIT_MSB,           0x00 },
144         { CS42L42_ASP_TX_CH2_BIT_LSB,           0x00 },
145         { CS42L42_ASP_RX_DAI0_EN,               0x00 },
146         { CS42L42_ASP_RX_DAI0_CH1_AP_RES,       0x03 },
147         { CS42L42_ASP_RX_DAI0_CH1_BIT_MSB,      0x00 },
148         { CS42L42_ASP_RX_DAI0_CH1_BIT_LSB,      0x00 },
149         { CS42L42_ASP_RX_DAI0_CH2_AP_RES,       0x03 },
150         { CS42L42_ASP_RX_DAI0_CH2_BIT_MSB,      0x00 },
151         { CS42L42_ASP_RX_DAI0_CH2_BIT_LSB,      0x00 },
152         { CS42L42_ASP_RX_DAI0_CH3_AP_RES,       0x03 },
153         { CS42L42_ASP_RX_DAI0_CH3_BIT_MSB,      0x00 },
154         { CS42L42_ASP_RX_DAI0_CH3_BIT_LSB,      0x00 },
155         { CS42L42_ASP_RX_DAI0_CH4_AP_RES,       0x03 },
156         { CS42L42_ASP_RX_DAI0_CH4_BIT_MSB,      0x00 },
157         { CS42L42_ASP_RX_DAI0_CH4_BIT_LSB,      0x00 },
158         { CS42L42_ASP_RX_DAI1_CH1_AP_RES,       0x03 },
159         { CS42L42_ASP_RX_DAI1_CH1_BIT_MSB,      0x00 },
160         { CS42L42_ASP_RX_DAI1_CH1_BIT_LSB,      0x00 },
161         { CS42L42_ASP_RX_DAI1_CH2_AP_RES,       0x03 },
162         { CS42L42_ASP_RX_DAI1_CH2_BIT_MSB,      0x00 },
163         { CS42L42_ASP_RX_DAI1_CH2_BIT_LSB,      0x00 },
164 };
165 
166 static bool cs42l42_readable_register(struct device *dev, unsigned int reg)
167 {
168         switch (reg) {
169         case CS42L42_PAGE_REGISTER:
170         case CS42L42_DEVID_AB:
171         case CS42L42_DEVID_CD:
172         case CS42L42_DEVID_E:
173         case CS42L42_FABID:
174         case CS42L42_REVID:
175         case CS42L42_FRZ_CTL:
176         case CS42L42_SRC_CTL:
177         case CS42L42_MCLK_STATUS:
178         case CS42L42_MCLK_CTL:
179         case CS42L42_SFTRAMP_RATE:
180         case CS42L42_I2C_DEBOUNCE:
181         case CS42L42_I2C_STRETCH:
182         case CS42L42_I2C_TIMEOUT:
183         case CS42L42_PWR_CTL1:
184         case CS42L42_PWR_CTL2:
185         case CS42L42_PWR_CTL3:
186         case CS42L42_RSENSE_CTL1:
187         case CS42L42_RSENSE_CTL2:
188         case CS42L42_OSC_SWITCH:
189         case CS42L42_OSC_SWITCH_STATUS:
190         case CS42L42_RSENSE_CTL3:
191         case CS42L42_TSENSE_CTL:
192         case CS42L42_TSRS_INT_DISABLE:
193         case CS42L42_TRSENSE_STATUS:
194         case CS42L42_HSDET_CTL1:
195         case CS42L42_HSDET_CTL2:
196         case CS42L42_HS_SWITCH_CTL:
197         case CS42L42_HS_DET_STATUS:
198         case CS42L42_HS_CLAMP_DISABLE:
199         case CS42L42_MCLK_SRC_SEL:
200         case CS42L42_SPDIF_CLK_CFG:
201         case CS42L42_FSYNC_PW_LOWER:
202         case CS42L42_FSYNC_PW_UPPER:
203         case CS42L42_FSYNC_P_LOWER:
204         case CS42L42_FSYNC_P_UPPER:
205         case CS42L42_ASP_CLK_CFG:
206         case CS42L42_ASP_FRM_CFG:
207         case CS42L42_FS_RATE_EN:
208         case CS42L42_IN_ASRC_CLK:
209         case CS42L42_OUT_ASRC_CLK:
210         case CS42L42_PLL_DIV_CFG1:
211         case CS42L42_ADC_OVFL_STATUS:
212         case CS42L42_MIXER_STATUS:
213         case CS42L42_SRC_STATUS:
214         case CS42L42_ASP_RX_STATUS:
215         case CS42L42_ASP_TX_STATUS:
216         case CS42L42_CODEC_STATUS:
217         case CS42L42_DET_INT_STATUS1:
218         case CS42L42_DET_INT_STATUS2:
219         case CS42L42_SRCPL_INT_STATUS:
220         case CS42L42_VPMON_STATUS:
221         case CS42L42_PLL_LOCK_STATUS:
222         case CS42L42_TSRS_PLUG_STATUS:
223         case CS42L42_ADC_OVFL_INT_MASK:
224         case CS42L42_MIXER_INT_MASK:
225         case CS42L42_SRC_INT_MASK:
226         case CS42L42_ASP_RX_INT_MASK:
227         case CS42L42_ASP_TX_INT_MASK:
228         case CS42L42_CODEC_INT_MASK:
229         case CS42L42_SRCPL_INT_MASK:
230         case CS42L42_VPMON_INT_MASK:
231         case CS42L42_PLL_LOCK_INT_MASK:
232         case CS42L42_TSRS_PLUG_INT_MASK:
233         case CS42L42_PLL_CTL1:
234         case CS42L42_PLL_DIV_FRAC0:
235         case CS42L42_PLL_DIV_FRAC1:
236         case CS42L42_PLL_DIV_FRAC2:
237         case CS42L42_PLL_DIV_INT:
238         case CS42L42_PLL_CTL3:
239         case CS42L42_PLL_CAL_RATIO:
240         case CS42L42_PLL_CTL4:
241         case CS42L42_LOAD_DET_RCSTAT:
242         case CS42L42_LOAD_DET_DONE:
243         case CS42L42_LOAD_DET_EN:
244         case CS42L42_HSBIAS_SC_AUTOCTL:
245         case CS42L42_WAKE_CTL:
246         case CS42L42_ADC_DISABLE_MUTE:
247         case CS42L42_TIPSENSE_CTL:
248         case CS42L42_MISC_DET_CTL:
249         case CS42L42_MIC_DET_CTL1:
250         case CS42L42_MIC_DET_CTL2:
251         case CS42L42_DET_STATUS1:
252         case CS42L42_DET_STATUS2:
253         case CS42L42_DET_INT1_MASK:
254         case CS42L42_DET_INT2_MASK:
255         case CS42L42_HS_BIAS_CTL:
256         case CS42L42_ADC_CTL:
257         case CS42L42_ADC_VOLUME:
258         case CS42L42_ADC_WNF_HPF_CTL:
259         case CS42L42_DAC_CTL1:
260         case CS42L42_DAC_CTL2:
261         case CS42L42_HP_CTL:
262         case CS42L42_CLASSH_CTL:
263         case CS42L42_MIXER_CHA_VOL:
264         case CS42L42_MIXER_ADC_VOL:
265         case CS42L42_MIXER_CHB_VOL:
266         case CS42L42_EQ_COEF_IN0:
267         case CS42L42_EQ_COEF_IN1:
268         case CS42L42_EQ_COEF_IN2:
269         case CS42L42_EQ_COEF_IN3:
270         case CS42L42_EQ_COEF_RW:
271         case CS42L42_EQ_COEF_OUT0:
272         case CS42L42_EQ_COEF_OUT1:
273         case CS42L42_EQ_COEF_OUT2:
274         case CS42L42_EQ_COEF_OUT3:
275         case CS42L42_EQ_INIT_STAT:
276         case CS42L42_EQ_START_FILT:
277         case CS42L42_EQ_MUTE_CTL:
278         case CS42L42_SP_RX_CH_SEL:
279         case CS42L42_SP_RX_ISOC_CTL:
280         case CS42L42_SP_RX_FS:
281         case CS42l42_SPDIF_CH_SEL:
282         case CS42L42_SP_TX_ISOC_CTL:
283         case CS42L42_SP_TX_FS:
284         case CS42L42_SPDIF_SW_CTL1:
285         case CS42L42_SRC_SDIN_FS:
286         case CS42L42_SRC_SDOUT_FS:
287         case CS42L42_SPDIF_CTL1:
288         case CS42L42_SPDIF_CTL2:
289         case CS42L42_SPDIF_CTL3:
290         case CS42L42_SPDIF_CTL4:
291         case CS42L42_ASP_TX_SZ_EN:
292         case CS42L42_ASP_TX_CH_EN:
293         case CS42L42_ASP_TX_CH_AP_RES:
294         case CS42L42_ASP_TX_CH1_BIT_MSB:
295         case CS42L42_ASP_TX_CH1_BIT_LSB:
296         case CS42L42_ASP_TX_HIZ_DLY_CFG:
297         case CS42L42_ASP_TX_CH2_BIT_MSB:
298         case CS42L42_ASP_TX_CH2_BIT_LSB:
299         case CS42L42_ASP_RX_DAI0_EN:
300         case CS42L42_ASP_RX_DAI0_CH1_AP_RES:
301         case CS42L42_ASP_RX_DAI0_CH1_BIT_MSB:
302         case CS42L42_ASP_RX_DAI0_CH1_BIT_LSB:
303         case CS42L42_ASP_RX_DAI0_CH2_AP_RES:
304         case CS42L42_ASP_RX_DAI0_CH2_BIT_MSB:
305         case CS42L42_ASP_RX_DAI0_CH2_BIT_LSB:
306         case CS42L42_ASP_RX_DAI0_CH3_AP_RES:
307         case CS42L42_ASP_RX_DAI0_CH3_BIT_MSB:
308         case CS42L42_ASP_RX_DAI0_CH3_BIT_LSB:
309         case CS42L42_ASP_RX_DAI0_CH4_AP_RES:
310         case CS42L42_ASP_RX_DAI0_CH4_BIT_MSB:
311         case CS42L42_ASP_RX_DAI0_CH4_BIT_LSB:
312         case CS42L42_ASP_RX_DAI1_CH1_AP_RES:
313         case CS42L42_ASP_RX_DAI1_CH1_BIT_MSB:
314         case CS42L42_ASP_RX_DAI1_CH1_BIT_LSB:
315         case CS42L42_ASP_RX_DAI1_CH2_AP_RES:
316         case CS42L42_ASP_RX_DAI1_CH2_BIT_MSB:
317         case CS42L42_ASP_RX_DAI1_CH2_BIT_LSB:
318         case CS42L42_SUB_REVID:
319                 return true;
320         default:
321                 return false;
322         }
323 }
324 
325 static bool cs42l42_volatile_register(struct device *dev, unsigned int reg)
326 {
327         switch (reg) {
328         case CS42L42_DEVID_AB:
329         case CS42L42_DEVID_CD:
330         case CS42L42_DEVID_E:
331         case CS42L42_MCLK_STATUS:
332         case CS42L42_OSC_SWITCH_STATUS:
333         case CS42L42_TRSENSE_STATUS:
334         case CS42L42_HS_DET_STATUS:
335         case CS42L42_ADC_OVFL_STATUS:
336         case CS42L42_MIXER_STATUS:
337         case CS42L42_SRC_STATUS:
338         case CS42L42_ASP_RX_STATUS:
339         case CS42L42_ASP_TX_STATUS:
340         case CS42L42_CODEC_STATUS:
341         case CS42L42_DET_INT_STATUS1:
342         case CS42L42_DET_INT_STATUS2:
343         case CS42L42_SRCPL_INT_STATUS:
344         case CS42L42_VPMON_STATUS:
345         case CS42L42_PLL_LOCK_STATUS:
346         case CS42L42_TSRS_PLUG_STATUS:
347         case CS42L42_LOAD_DET_RCSTAT:
348         case CS42L42_LOAD_DET_DONE:
349         case CS42L42_DET_STATUS1:
350         case CS42L42_DET_STATUS2:
351                 return true;
352         default:
353                 return false;
354         }
355 }
356 
357 static const struct regmap_range_cfg cs42l42_page_range = {
358         .name = "Pages",
359         .range_min = 0,
360         .range_max = CS42L42_MAX_REGISTER,
361         .selector_reg = CS42L42_PAGE_REGISTER,
362         .selector_mask = 0xff,
363         .selector_shift = 0,
364         .window_start = 0,
365         .window_len = 256,
366 };
367 
368 static const struct regmap_config cs42l42_regmap = {
369         .reg_bits = 8,
370         .val_bits = 8,
371 
372         .readable_reg = cs42l42_readable_register,
373         .volatile_reg = cs42l42_volatile_register,
374 
375         .ranges = &cs42l42_page_range,
376         .num_ranges = 1,
377 
378         .max_register = CS42L42_MAX_REGISTER,
379         .reg_defaults = cs42l42_reg_defaults,
380         .num_reg_defaults = ARRAY_SIZE(cs42l42_reg_defaults),
381         .cache_type = REGCACHE_RBTREE,
382 
383         .use_single_read = true,
384         .use_single_write = true,
385 };
386 
387 static DECLARE_TLV_DB_SCALE(adc_tlv, -9700, 100, true);
388 static DECLARE_TLV_DB_SCALE(mixer_tlv, -6300, 100, true);
389 
390 static const char * const cs42l42_hpf_freq_text[] = {
391         "1.86Hz", "120Hz", "235Hz", "466Hz"
392 };
393 
394 static SOC_ENUM_SINGLE_DECL(cs42l42_hpf_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
395                             CS42L42_ADC_HPF_CF_SHIFT,
396                             cs42l42_hpf_freq_text);
397 
398 static const char * const cs42l42_wnf3_freq_text[] = {
399         "160Hz", "180Hz", "200Hz", "220Hz",
400         "240Hz", "260Hz", "280Hz", "300Hz"
401 };
402 
403 static SOC_ENUM_SINGLE_DECL(cs42l42_wnf3_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
404                             CS42L42_ADC_WNF_CF_SHIFT,
405                             cs42l42_wnf3_freq_text);
406 
407 static const struct snd_kcontrol_new cs42l42_snd_controls[] = {
408         /* ADC Volume and Filter Controls */
409         SOC_SINGLE("ADC Notch Switch", CS42L42_ADC_CTL,
410                                 CS42L42_ADC_NOTCH_DIS_SHIFT, true, true),
411         SOC_SINGLE("ADC Weak Force Switch", CS42L42_ADC_CTL,
412                                 CS42L42_ADC_FORCE_WEAK_VCM_SHIFT, true, false),
413         SOC_SINGLE("ADC Invert Switch", CS42L42_ADC_CTL,
414                                 CS42L42_ADC_INV_SHIFT, true, false),
415         SOC_SINGLE("ADC Boost Switch", CS42L42_ADC_CTL,
416                                 CS42L42_ADC_DIG_BOOST_SHIFT, true, false),
417         SOC_SINGLE_S8_TLV("ADC Volume", CS42L42_ADC_VOLUME, -97, 12, adc_tlv),
418         SOC_SINGLE("ADC WNF Switch", CS42L42_ADC_WNF_HPF_CTL,
419                                 CS42L42_ADC_WNF_EN_SHIFT, true, false),
420         SOC_SINGLE("ADC HPF Switch", CS42L42_ADC_WNF_HPF_CTL,
421                                 CS42L42_ADC_HPF_EN_SHIFT, true, false),
422         SOC_ENUM("HPF Corner Freq", cs42l42_hpf_freq_enum),
423         SOC_ENUM("WNF 3dB Freq", cs42l42_wnf3_freq_enum),
424 
425         /* DAC Volume and Filter Controls */
426         SOC_SINGLE("DACA Invert Switch", CS42L42_DAC_CTL1,
427                                 CS42L42_DACA_INV_SHIFT, true, false),
428         SOC_SINGLE("DACB Invert Switch", CS42L42_DAC_CTL1,
429                                 CS42L42_DACB_INV_SHIFT, true, false),
430         SOC_SINGLE("DAC HPF Switch", CS42L42_DAC_CTL2,
431                                 CS42L42_DAC_HPF_EN_SHIFT, true, false),
432         SOC_DOUBLE_R_TLV("Mixer Volume", CS42L42_MIXER_CHA_VOL,
433                          CS42L42_MIXER_CHB_VOL, CS42L42_MIXER_CH_VOL_SHIFT,
434                                 0x3f, 1, mixer_tlv)
435 };
436 
437 static int cs42l42_hp_adc_ev(struct snd_soc_dapm_widget *w,
438                              struct snd_kcontrol *kcontrol, int event)
439 {
440         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
441         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
442 
443         switch (event) {
444         case SND_SOC_DAPM_PRE_PMU:
445                 cs42l42->hp_adc_up_pending = true;
446                 break;
447         case SND_SOC_DAPM_POST_PMU:
448                 /* Only need one delay if HP and ADC are both powering-up */
449                 if (cs42l42->hp_adc_up_pending) {
450                         usleep_range(CS42L42_HP_ADC_EN_TIME_US,
451                                      CS42L42_HP_ADC_EN_TIME_US + 1000);
452                         cs42l42->hp_adc_up_pending = false;
453                 }
454                 break;
455         default:
456                 break;
457         }
458 
459         return 0;
460 }
461 
462 static const struct snd_soc_dapm_widget cs42l42_dapm_widgets[] = {
463         /* Playback Path */
464         SND_SOC_DAPM_OUTPUT("HP"),
465         SND_SOC_DAPM_DAC_E("DAC", NULL, CS42L42_PWR_CTL1, CS42L42_HP_PDN_SHIFT, 1,
466                            cs42l42_hp_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
467         SND_SOC_DAPM_MIXER("MIXER", CS42L42_PWR_CTL1, CS42L42_MIXER_PDN_SHIFT, 1, NULL, 0),
468         SND_SOC_DAPM_AIF_IN("SDIN1", NULL, 0, SND_SOC_NOPM, 0, 0),
469         SND_SOC_DAPM_AIF_IN("SDIN2", NULL, 1, SND_SOC_NOPM, 0, 0),
470 
471         /* Playback Requirements */
472         SND_SOC_DAPM_SUPPLY("ASP DAI0", CS42L42_PWR_CTL1, CS42L42_ASP_DAI_PDN_SHIFT, 1, NULL, 0),
473 
474         /* Capture Path */
475         SND_SOC_DAPM_INPUT("HS"),
476         SND_SOC_DAPM_ADC_E("ADC", NULL, CS42L42_PWR_CTL1, CS42L42_ADC_PDN_SHIFT, 1,
477                            cs42l42_hp_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
478         SND_SOC_DAPM_AIF_OUT("SDOUT1", NULL, 0, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH1_SHIFT, 0),
479         SND_SOC_DAPM_AIF_OUT("SDOUT2", NULL, 1, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH2_SHIFT, 0),
480 
481         /* Capture Requirements */
482         SND_SOC_DAPM_SUPPLY("ASP DAO0", CS42L42_PWR_CTL1, CS42L42_ASP_DAO_PDN_SHIFT, 1, NULL, 0),
483         SND_SOC_DAPM_SUPPLY("ASP TX EN", CS42L42_ASP_TX_SZ_EN, CS42L42_ASP_TX_EN_SHIFT, 0, NULL, 0),
484 
485         /* Playback/Capture Requirements */
486         SND_SOC_DAPM_SUPPLY("SCLK", CS42L42_ASP_CLK_CFG, CS42L42_ASP_SCLK_EN_SHIFT, 0, NULL, 0),
487 };
488 
489 static const struct snd_soc_dapm_route cs42l42_audio_map[] = {
490         /* Playback Path */
491         {"HP", NULL, "DAC"},
492         {"DAC", NULL, "MIXER"},
493         {"MIXER", NULL, "SDIN1"},
494         {"MIXER", NULL, "SDIN2"},
495         {"SDIN1", NULL, "Playback"},
496         {"SDIN2", NULL, "Playback"},
497 
498         /* Playback Requirements */
499         {"SDIN1", NULL, "ASP DAI0"},
500         {"SDIN2", NULL, "ASP DAI0"},
501         {"SDIN1", NULL, "SCLK"},
502         {"SDIN2", NULL, "SCLK"},
503 
504         /* Capture Path */
505         {"ADC", NULL, "HS"},
506         { "SDOUT1", NULL, "ADC" },
507         { "SDOUT2", NULL, "ADC" },
508         { "Capture", NULL, "SDOUT1" },
509         { "Capture", NULL, "SDOUT2" },
510 
511         /* Capture Requirements */
512         { "SDOUT1", NULL, "ASP DAO0" },
513         { "SDOUT2", NULL, "ASP DAO0" },
514         { "SDOUT1", NULL, "SCLK" },
515         { "SDOUT2", NULL, "SCLK" },
516         { "SDOUT1", NULL, "ASP TX EN" },
517         { "SDOUT2", NULL, "ASP TX EN" },
518 };
519 
520 static int cs42l42_set_jack(struct snd_soc_component *component, struct snd_soc_jack *jk, void *d)
521 {
522         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
523 
524         /* Prevent race with interrupt handler */
525         mutex_lock(&cs42l42->jack_detect_mutex);
526         cs42l42->jack = jk;
527 
528         if (jk) {
529                 switch (cs42l42->hs_type) {
530                 case CS42L42_PLUG_CTIA:
531                 case CS42L42_PLUG_OMTP:
532                         snd_soc_jack_report(jk, SND_JACK_HEADSET, SND_JACK_HEADSET);
533                         break;
534                 case CS42L42_PLUG_HEADPHONE:
535                         snd_soc_jack_report(jk, SND_JACK_HEADPHONE, SND_JACK_HEADPHONE);
536                         break;
537                 default:
538                         break;
539                 }
540         }
541         mutex_unlock(&cs42l42->jack_detect_mutex);
542 
543         return 0;
544 }
545 
546 static const struct snd_soc_component_driver soc_component_dev_cs42l42 = {
547         .set_jack               = cs42l42_set_jack,
548         .dapm_widgets           = cs42l42_dapm_widgets,
549         .num_dapm_widgets       = ARRAY_SIZE(cs42l42_dapm_widgets),
550         .dapm_routes            = cs42l42_audio_map,
551         .num_dapm_routes        = ARRAY_SIZE(cs42l42_audio_map),
552         .controls               = cs42l42_snd_controls,
553         .num_controls           = ARRAY_SIZE(cs42l42_snd_controls),
554         .idle_bias_on           = 1,
555         .endianness             = 1,
556         .non_legacy_dai_naming  = 1,
557 };
558 
559 /* Switch to SCLK. Atomic delay after the write to allow the switch to complete. */
560 static const struct reg_sequence cs42l42_to_sclk_seq[] = {
561         {
562                 .reg = CS42L42_OSC_SWITCH,
563                 .def = CS42L42_SCLK_PRESENT_MASK,
564                 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US,
565         },
566 };
567 
568 /* Switch to OSC. Atomic delay after the write to allow the switch to complete. */
569 static const struct reg_sequence cs42l42_to_osc_seq[] = {
570         {
571                 .reg = CS42L42_OSC_SWITCH,
572                 .def = 0,
573                 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US,
574         },
575 };
576 
577 struct cs42l42_pll_params {
578         u32 sclk;
579         u8 mclk_src_sel;
580         u8 sclk_prediv;
581         u8 pll_div_int;
582         u32 pll_div_frac;
583         u8 pll_mode;
584         u8 pll_divout;
585         u32 mclk_int;
586         u8 pll_cal_ratio;
587         u8 n;
588 };
589 
590 /*
591  * Common PLL Settings for given SCLK
592  * Table 4-5 from the Datasheet
593  */
594 static const struct cs42l42_pll_params pll_ratio_table[] = {
595         { 1411200,  1, 0x00, 0x80, 0x000000, 0x03, 0x10, 11289600, 128, 2},
596         { 1536000,  1, 0x00, 0x7D, 0x000000, 0x03, 0x10, 12000000, 125, 2},
597         { 2304000,  1, 0x00, 0x55, 0xC00000, 0x02, 0x10, 12288000,  85, 2},
598         { 2400000,  1, 0x00, 0x50, 0x000000, 0x03, 0x10, 12000000,  80, 2},
599         { 2822400,  1, 0x00, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1},
600         { 3000000,  1, 0x00, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1},
601         { 3072000,  1, 0x00, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1},
602         { 4000000,  1, 0x00, 0x30, 0x800000, 0x03, 0x10, 12000000,  96, 1},
603         { 4096000,  1, 0x00, 0x2E, 0xE00000, 0x03, 0x10, 12000000,  94, 1},
604         { 5644800,  1, 0x01, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1},
605         { 6000000,  1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1},
606         { 6144000,  1, 0x01, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1},
607         { 11289600, 0, 0, 0, 0, 0, 0, 11289600, 0, 1},
608         { 12000000, 0, 0, 0, 0, 0, 0, 12000000, 0, 1},
609         { 12288000, 0, 0, 0, 0, 0, 0, 12288000, 0, 1},
610         { 22579200, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1},
611         { 24000000, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1},
612         { 24576000, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 12288000, 128, 1}
613 };
614 
615 static int cs42l42_pll_config(struct snd_soc_component *component)
616 {
617         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
618         int i;
619         u32 clk;
620         u32 fsync;
621 
622         if (!cs42l42->sclk)
623                 clk = cs42l42->bclk;
624         else
625                 clk = cs42l42->sclk;
626 
627         /* Don't reconfigure if there is an audio stream running */
628         if (cs42l42->stream_use) {
629                 if (pll_ratio_table[cs42l42->pll_config].sclk == clk)
630                         return 0;
631                 else
632                         return -EBUSY;
633         }
634 
635         for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
636                 if (pll_ratio_table[i].sclk == clk) {
637                         cs42l42->pll_config = i;
638 
639                         /* Configure the internal sample rate */
640                         snd_soc_component_update_bits(component, CS42L42_MCLK_CTL,
641                                         CS42L42_INTERNAL_FS_MASK,
642                                         ((pll_ratio_table[i].mclk_int !=
643                                         12000000) &&
644                                         (pll_ratio_table[i].mclk_int !=
645                                         24000000)) <<
646                                         CS42L42_INTERNAL_FS_SHIFT);
647 
648                         /* Set up the LRCLK */
649                         fsync = clk / cs42l42->srate;
650                         if (((fsync * cs42l42->srate) != clk)
651                                 || ((fsync % 2) != 0)) {
652                                 dev_err(component->dev,
653                                         "Unsupported sclk %d/sample rate %d\n",
654                                         clk,
655                                         cs42l42->srate);
656                                 return -EINVAL;
657                         }
658                         /* Set the LRCLK period */
659                         snd_soc_component_update_bits(component,
660                                         CS42L42_FSYNC_P_LOWER,
661                                         CS42L42_FSYNC_PERIOD_MASK,
662                                         CS42L42_FRAC0_VAL(fsync - 1) <<
663                                         CS42L42_FSYNC_PERIOD_SHIFT);
664                         snd_soc_component_update_bits(component,
665                                         CS42L42_FSYNC_P_UPPER,
666                                         CS42L42_FSYNC_PERIOD_MASK,
667                                         CS42L42_FRAC1_VAL(fsync - 1) <<
668                                         CS42L42_FSYNC_PERIOD_SHIFT);
669                         /* Set the LRCLK to 50% duty cycle */
670                         fsync = fsync / 2;
671                         snd_soc_component_update_bits(component,
672                                         CS42L42_FSYNC_PW_LOWER,
673                                         CS42L42_FSYNC_PULSE_WIDTH_MASK,
674                                         CS42L42_FRAC0_VAL(fsync - 1) <<
675                                         CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
676                         snd_soc_component_update_bits(component,
677                                         CS42L42_FSYNC_PW_UPPER,
678                                         CS42L42_FSYNC_PULSE_WIDTH_MASK,
679                                         CS42L42_FRAC1_VAL(fsync - 1) <<
680                                         CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
681                         if (pll_ratio_table[i].mclk_src_sel == 0) {
682                                 /* Pass the clock straight through */
683                                 snd_soc_component_update_bits(component,
684                                         CS42L42_PLL_CTL1,
685                                         CS42L42_PLL_START_MASK, 0);
686                         } else {
687                                 /* Configure PLL per table 4-5 */
688                                 snd_soc_component_update_bits(component,
689                                         CS42L42_PLL_DIV_CFG1,
690                                         CS42L42_SCLK_PREDIV_MASK,
691                                         pll_ratio_table[i].sclk_prediv
692                                         << CS42L42_SCLK_PREDIV_SHIFT);
693                                 snd_soc_component_update_bits(component,
694                                         CS42L42_PLL_DIV_INT,
695                                         CS42L42_PLL_DIV_INT_MASK,
696                                         pll_ratio_table[i].pll_div_int
697                                         << CS42L42_PLL_DIV_INT_SHIFT);
698                                 snd_soc_component_update_bits(component,
699                                         CS42L42_PLL_DIV_FRAC0,
700                                         CS42L42_PLL_DIV_FRAC_MASK,
701                                         CS42L42_FRAC0_VAL(
702                                         pll_ratio_table[i].pll_div_frac)
703                                         << CS42L42_PLL_DIV_FRAC_SHIFT);
704                                 snd_soc_component_update_bits(component,
705                                         CS42L42_PLL_DIV_FRAC1,
706                                         CS42L42_PLL_DIV_FRAC_MASK,
707                                         CS42L42_FRAC1_VAL(
708                                         pll_ratio_table[i].pll_div_frac)
709                                         << CS42L42_PLL_DIV_FRAC_SHIFT);
710                                 snd_soc_component_update_bits(component,
711                                         CS42L42_PLL_DIV_FRAC2,
712                                         CS42L42_PLL_DIV_FRAC_MASK,
713                                         CS42L42_FRAC2_VAL(
714                                         pll_ratio_table[i].pll_div_frac)
715                                         << CS42L42_PLL_DIV_FRAC_SHIFT);
716                                 snd_soc_component_update_bits(component,
717                                         CS42L42_PLL_CTL4,
718                                         CS42L42_PLL_MODE_MASK,
719                                         pll_ratio_table[i].pll_mode
720                                         << CS42L42_PLL_MODE_SHIFT);
721                                 snd_soc_component_update_bits(component,
722                                         CS42L42_PLL_CTL3,
723                                         CS42L42_PLL_DIVOUT_MASK,
724                                         (pll_ratio_table[i].pll_divout * pll_ratio_table[i].n)
725                                         << CS42L42_PLL_DIVOUT_SHIFT);
726                                 if (pll_ratio_table[i].n != 1)
727                                         cs42l42->pll_divout = pll_ratio_table[i].pll_divout;
728                                 else
729                                         cs42l42->pll_divout = 0;
730                                 snd_soc_component_update_bits(component,
731                                         CS42L42_PLL_CAL_RATIO,
732                                         CS42L42_PLL_CAL_RATIO_MASK,
733                                         pll_ratio_table[i].pll_cal_ratio
734                                         << CS42L42_PLL_CAL_RATIO_SHIFT);
735                         }
736                         return 0;
737                 }
738         }
739 
740         return -EINVAL;
741 }
742 
743 static void cs42l42_src_config(struct snd_soc_component *component, unsigned int sample_rate)
744 {
745         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
746         unsigned int fs;
747 
748         /* Don't reconfigure if there is an audio stream running */
749         if (cs42l42->stream_use)
750                 return;
751 
752         /* SRC MCLK must be as close as possible to 125 * sample rate */
753         if (sample_rate <= 48000)
754                 fs = CS42L42_CLK_IASRC_SEL_6;
755         else
756                 fs = CS42L42_CLK_IASRC_SEL_12;
757 
758         /* Set the sample rates (96k or lower) */
759         snd_soc_component_update_bits(component,
760                                       CS42L42_FS_RATE_EN,
761                                       CS42L42_FS_EN_MASK,
762                                       (CS42L42_FS_EN_IASRC_96K |
763                                        CS42L42_FS_EN_OASRC_96K) <<
764                                       CS42L42_FS_EN_SHIFT);
765 
766         snd_soc_component_update_bits(component,
767                                       CS42L42_IN_ASRC_CLK,
768                                       CS42L42_CLK_IASRC_SEL_MASK,
769                                       fs << CS42L42_CLK_IASRC_SEL_SHIFT);
770         snd_soc_component_update_bits(component,
771                                       CS42L42_OUT_ASRC_CLK,
772                                       CS42L42_CLK_OASRC_SEL_MASK,
773                                       fs << CS42L42_CLK_OASRC_SEL_SHIFT);
774 }
775 
776 static int cs42l42_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
777 {
778         struct snd_soc_component *component = codec_dai->component;
779         u32 asp_cfg_val = 0;
780 
781         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
782         case SND_SOC_DAIFMT_CBS_CFM:
783                 asp_cfg_val |= CS42L42_ASP_MASTER_MODE <<
784                                 CS42L42_ASP_MODE_SHIFT;
785                 break;
786         case SND_SOC_DAIFMT_CBS_CFS:
787                 asp_cfg_val |= CS42L42_ASP_SLAVE_MODE <<
788                                 CS42L42_ASP_MODE_SHIFT;
789                 break;
790         default:
791                 return -EINVAL;
792         }
793 
794         /* interface format */
795         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
796         case SND_SOC_DAIFMT_I2S:
797                 /*
798                  * 5050 mode, frame starts on falling edge of LRCLK,
799                  * frame delayed by 1.0 SCLKs
800                  */
801                 snd_soc_component_update_bits(component,
802                                               CS42L42_ASP_FRM_CFG,
803                                               CS42L42_ASP_STP_MASK |
804                                               CS42L42_ASP_5050_MASK |
805                                               CS42L42_ASP_FSD_MASK,
806                                               CS42L42_ASP_5050_MASK |
807                                               (CS42L42_ASP_FSD_1_0 <<
808                                                 CS42L42_ASP_FSD_SHIFT));
809                 break;
810         default:
811                 return -EINVAL;
812         }
813 
814         /* Bitclock/frame inversion */
815         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
816         case SND_SOC_DAIFMT_NB_NF:
817                 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT;
818                 break;
819         case SND_SOC_DAIFMT_NB_IF:
820                 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT;
821                 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT;
822                 break;
823         case SND_SOC_DAIFMT_IB_NF:
824                 break;
825         case SND_SOC_DAIFMT_IB_IF:
826                 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT;
827                 break;
828         }
829 
830         snd_soc_component_update_bits(component, CS42L42_ASP_CLK_CFG, CS42L42_ASP_MODE_MASK |
831                                                                       CS42L42_ASP_SCPOL_MASK |
832                                                                       CS42L42_ASP_LCPOL_MASK,
833                                                                       asp_cfg_val);
834 
835         return 0;
836 }
837 
838 static int cs42l42_dai_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
839 {
840         struct snd_soc_component *component = dai->component;
841         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
842 
843         /*
844          * Sample rates < 44.1 kHz would produce an out-of-range SCLK with
845          * a standard I2S frame. If the machine driver sets SCLK it must be
846          * legal.
847          */
848         if (cs42l42->sclk)
849                 return 0;
850 
851         /* Machine driver has not set a SCLK, limit bottom end to 44.1 kHz */
852         return snd_pcm_hw_constraint_minmax(substream->runtime,
853                                             SNDRV_PCM_HW_PARAM_RATE,
854                                             44100, 96000);
855 }
856 
857 static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream,
858                                 struct snd_pcm_hw_params *params,
859                                 struct snd_soc_dai *dai)
860 {
861         struct snd_soc_component *component = dai->component;
862         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
863         unsigned int channels = params_channels(params);
864         unsigned int width = (params_width(params) / 8) - 1;
865         unsigned int val = 0;
866         int ret;
867 
868         cs42l42->srate = params_rate(params);
869         cs42l42->bclk = snd_soc_params_to_bclk(params);
870 
871         /* I2S frame always has 2 channels even for mono audio */
872         if (channels == 1)
873                 cs42l42->bclk *= 2;
874 
875         /*
876          * Assume 24-bit samples are in 32-bit slots, to prevent SCLK being
877          * more than assumed (which would result in overclocking).
878          */
879         if (params_width(params) == 24)
880                 cs42l42->bclk = (cs42l42->bclk / 3) * 4;
881 
882         switch (substream->stream) {
883         case SNDRV_PCM_STREAM_CAPTURE:
884                 /* channel 2 on high LRCLK */
885                 val = CS42L42_ASP_TX_CH2_AP_MASK |
886                       (width << CS42L42_ASP_TX_CH2_RES_SHIFT) |
887                       (width << CS42L42_ASP_TX_CH1_RES_SHIFT);
888 
889                 snd_soc_component_update_bits(component, CS42L42_ASP_TX_CH_AP_RES,
890                                 CS42L42_ASP_TX_CH1_AP_MASK | CS42L42_ASP_TX_CH2_AP_MASK |
891                                 CS42L42_ASP_TX_CH2_RES_MASK | CS42L42_ASP_TX_CH1_RES_MASK, val);
892                 break;
893         case SNDRV_PCM_STREAM_PLAYBACK:
894                 val |= width << CS42L42_ASP_RX_CH_RES_SHIFT;
895                 /* channel 1 on low LRCLK */
896                 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH1_AP_RES,
897                                                          CS42L42_ASP_RX_CH_AP_MASK |
898                                                          CS42L42_ASP_RX_CH_RES_MASK, val);
899                 /* Channel 2 on high LRCLK */
900                 val |= CS42L42_ASP_RX_CH_AP_HI << CS42L42_ASP_RX_CH_AP_SHIFT;
901                 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH2_AP_RES,
902                                                          CS42L42_ASP_RX_CH_AP_MASK |
903                                                          CS42L42_ASP_RX_CH_RES_MASK, val);
904 
905                 /* Channel B comes from the last active channel */
906                 snd_soc_component_update_bits(component, CS42L42_SP_RX_CH_SEL,
907                                               CS42L42_SP_RX_CHB_SEL_MASK,
908                                               (channels - 1) << CS42L42_SP_RX_CHB_SEL_SHIFT);
909 
910                 /* Both LRCLK slots must be enabled */
911                 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_EN,
912                                               CS42L42_ASP_RX0_CH_EN_MASK,
913                                               BIT(CS42L42_ASP_RX0_CH1_SHIFT) |
914                                               BIT(CS42L42_ASP_RX0_CH2_SHIFT));
915                 break;
916         default:
917                 break;
918         }
919 
920         ret = cs42l42_pll_config(component);
921         if (ret)
922                 return ret;
923 
924         cs42l42_src_config(component, params_rate(params));
925 
926         return 0;
927 }
928 
929 static int cs42l42_set_sysclk(struct snd_soc_dai *dai,
930                                 int clk_id, unsigned int freq, int dir)
931 {
932         struct snd_soc_component *component = dai->component;
933         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
934         int i;
935 
936         if (freq == 0) {
937                 cs42l42->sclk = 0;
938                 return 0;
939         }
940 
941         for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
942                 if (pll_ratio_table[i].sclk == freq) {
943                         cs42l42->sclk = freq;
944                         return 0;
945                 }
946         }
947 
948         dev_err(component->dev, "SCLK %u not supported\n", freq);
949 
950         return -EINVAL;
951 }
952 
953 static int cs42l42_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
954 {
955         struct snd_soc_component *component = dai->component;
956         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
957         unsigned int regval;
958         int ret;
959 
960         if (mute) {
961                 /* Mute the headphone */
962                 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
963                         snd_soc_component_update_bits(component, CS42L42_HP_CTL,
964                                                       CS42L42_HP_ANA_AMUTE_MASK |
965                                                       CS42L42_HP_ANA_BMUTE_MASK,
966                                                       CS42L42_HP_ANA_AMUTE_MASK |
967                                                       CS42L42_HP_ANA_BMUTE_MASK);
968 
969                 cs42l42->stream_use &= ~(1 << stream);
970                 if (!cs42l42->stream_use) {
971                         /*
972                          * Switch to the internal oscillator.
973                          * SCLK must remain running until after this clock switch.
974                          * Without a source of clock the I2C bus doesn't work.
975                          */
976                         regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_osc_seq,
977                                                ARRAY_SIZE(cs42l42_to_osc_seq));
978 
979                         /* Must disconnect PLL before stopping it */
980                         snd_soc_component_update_bits(component,
981                                                       CS42L42_MCLK_SRC_SEL,
982                                                       CS42L42_MCLK_SRC_SEL_MASK,
983                                                       0);
984                         usleep_range(100, 200);
985 
986                         snd_soc_component_update_bits(component, CS42L42_PLL_CTL1,
987                                                       CS42L42_PLL_START_MASK, 0);
988                 }
989         } else {
990                 if (!cs42l42->stream_use) {
991                         /* SCLK must be running before codec unmute */
992                         if (pll_ratio_table[cs42l42->pll_config].mclk_src_sel) {
993                                 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1,
994                                                               CS42L42_PLL_START_MASK, 1);
995 
996                                 if (cs42l42->pll_divout) {
997                                         usleep_range(CS42L42_PLL_DIVOUT_TIME_US,
998                                                      CS42L42_PLL_DIVOUT_TIME_US * 2);
999                                         snd_soc_component_update_bits(component, CS42L42_PLL_CTL3,
1000                                                                       CS42L42_PLL_DIVOUT_MASK,
1001                                                                       cs42l42->pll_divout <<
1002                                                                       CS42L42_PLL_DIVOUT_SHIFT);
1003                                 }
1004 
1005                                 ret = regmap_read_poll_timeout(cs42l42->regmap,
1006                                                                CS42L42_PLL_LOCK_STATUS,
1007                                                                regval,
1008                                                                (regval & 1),
1009                                                                CS42L42_PLL_LOCK_POLL_US,
1010                                                                CS42L42_PLL_LOCK_TIMEOUT_US);
1011                                 if (ret < 0)
1012                                         dev_warn(component->dev, "PLL failed to lock: %d\n", ret);
1013 
1014                                 /* PLL must be running to drive glitchless switch logic */
1015                                 snd_soc_component_update_bits(component,
1016                                                               CS42L42_MCLK_SRC_SEL,
1017                                                               CS42L42_MCLK_SRC_SEL_MASK,
1018                                                               CS42L42_MCLK_SRC_SEL_MASK);
1019                         }
1020 
1021                         /* Mark SCLK as present, turn off internal oscillator */
1022                         regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_sclk_seq,
1023                                                ARRAY_SIZE(cs42l42_to_sclk_seq));
1024                 }
1025                 cs42l42->stream_use |= 1 << stream;
1026 
1027                 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1028                         /* Un-mute the headphone */
1029                         snd_soc_component_update_bits(component, CS42L42_HP_CTL,
1030                                                       CS42L42_HP_ANA_AMUTE_MASK |
1031                                                       CS42L42_HP_ANA_BMUTE_MASK,
1032                                                       0);
1033                 }
1034         }
1035 
1036         return 0;
1037 }
1038 
1039 #define CS42L42_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1040                          SNDRV_PCM_FMTBIT_S24_LE |\
1041                          SNDRV_PCM_FMTBIT_S32_LE)
1042 
1043 static const struct snd_soc_dai_ops cs42l42_ops = {
1044         .startup        = cs42l42_dai_startup,
1045         .hw_params      = cs42l42_pcm_hw_params,
1046         .set_fmt        = cs42l42_set_dai_fmt,
1047         .set_sysclk     = cs42l42_set_sysclk,
1048         .mute_stream    = cs42l42_mute_stream,
1049 };
1050 
1051 static struct snd_soc_dai_driver cs42l42_dai = {
1052                 .name = "cs42l42",
1053                 .playback = {
1054                         .stream_name = "Playback",
1055                         .channels_min = 1,
1056                         .channels_max = 2,
1057                         .rates = SNDRV_PCM_RATE_8000_96000,
1058                         .formats = CS42L42_FORMATS,
1059                 },
1060                 .capture = {
1061                         .stream_name = "Capture",
1062                         .channels_min = 1,
1063                         .channels_max = 2,
1064                         .rates = SNDRV_PCM_RATE_8000_96000,
1065                         .formats = CS42L42_FORMATS,
1066                 },
1067                 .symmetric_rate = 1,
1068                 .symmetric_sample_bits = 1,
1069                 .ops = &cs42l42_ops,
1070 };
1071 
1072 static void cs42l42_manual_hs_type_detect(struct cs42l42_private *cs42l42)
1073 {
1074         unsigned int hs_det_status;
1075         unsigned int hs_det_comp1;
1076         unsigned int hs_det_comp2;
1077         unsigned int hs_det_sw;
1078 
1079         /* Set hs detect to manual, active mode */
1080         regmap_update_bits(cs42l42->regmap,
1081                 CS42L42_HSDET_CTL2,
1082                 CS42L42_HSDET_CTRL_MASK |
1083                 CS42L42_HSDET_SET_MASK |
1084                 CS42L42_HSBIAS_REF_MASK |
1085                 CS42L42_HSDET_AUTO_TIME_MASK,
1086                 (1 << CS42L42_HSDET_CTRL_SHIFT) |
1087                 (0 << CS42L42_HSDET_SET_SHIFT) |
1088                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1089                 (0 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1090 
1091         /* Configure HS DET comparator reference levels. */
1092         regmap_update_bits(cs42l42->regmap,
1093                                 CS42L42_HSDET_CTL1,
1094                                 CS42L42_HSDET_COMP1_LVL_MASK |
1095                                 CS42L42_HSDET_COMP2_LVL_MASK,
1096                                 (CS42L42_HSDET_COMP1_LVL_VAL << CS42L42_HSDET_COMP1_LVL_SHIFT) |
1097                                 (CS42L42_HSDET_COMP2_LVL_VAL << CS42L42_HSDET_COMP2_LVL_SHIFT));
1098 
1099         /* Open the SW_HSB_HS3 switch and close SW_HSB_HS4 for a Type 1 headset. */
1100         regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP1);
1101 
1102         msleep(100);
1103 
1104         regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status);
1105 
1106         hs_det_comp1 = (hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >>
1107                         CS42L42_HSDET_COMP1_OUT_SHIFT;
1108         hs_det_comp2 = (hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >>
1109                         CS42L42_HSDET_COMP2_OUT_SHIFT;
1110 
1111         /* Close the SW_HSB_HS3 switch for a Type 2 headset. */
1112         regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP2);
1113 
1114         msleep(100);
1115 
1116         regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status);
1117 
1118         hs_det_comp1 |= ((hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >>
1119                         CS42L42_HSDET_COMP1_OUT_SHIFT) << 1;
1120         hs_det_comp2 |= ((hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >>
1121                         CS42L42_HSDET_COMP2_OUT_SHIFT) << 1;
1122 
1123         /* Use Comparator 1 with 1.25V Threshold. */
1124         switch (hs_det_comp1) {
1125         case CS42L42_HSDET_COMP_TYPE1:
1126                 cs42l42->hs_type = CS42L42_PLUG_CTIA;
1127                 hs_det_sw = CS42L42_HSDET_SW_TYPE1;
1128                 break;
1129         case CS42L42_HSDET_COMP_TYPE2:
1130                 cs42l42->hs_type = CS42L42_PLUG_OMTP;
1131                 hs_det_sw = CS42L42_HSDET_SW_TYPE2;
1132                 break;
1133         default:
1134                 /* Fallback to Comparator 2 with 1.75V Threshold. */
1135                 switch (hs_det_comp2) {
1136                 case CS42L42_HSDET_COMP_TYPE1:
1137                         cs42l42->hs_type = CS42L42_PLUG_CTIA;
1138                         hs_det_sw = CS42L42_HSDET_SW_TYPE1;
1139                         break;
1140                 case CS42L42_HSDET_COMP_TYPE2:
1141                         cs42l42->hs_type = CS42L42_PLUG_OMTP;
1142                         hs_det_sw = CS42L42_HSDET_SW_TYPE2;
1143                         break;
1144                 case CS42L42_HSDET_COMP_TYPE3:
1145                         cs42l42->hs_type = CS42L42_PLUG_HEADPHONE;
1146                         hs_det_sw = CS42L42_HSDET_SW_TYPE3;
1147                         break;
1148                 default:
1149                         cs42l42->hs_type = CS42L42_PLUG_INVALID;
1150                         hs_det_sw = CS42L42_HSDET_SW_TYPE4;
1151                         break;
1152                 }
1153         }
1154 
1155         /* Set Switches */
1156         regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, hs_det_sw);
1157 
1158         /* Set HSDET mode to Manual—Disabled */
1159         regmap_update_bits(cs42l42->regmap,
1160                 CS42L42_HSDET_CTL2,
1161                 CS42L42_HSDET_CTRL_MASK |
1162                 CS42L42_HSDET_SET_MASK |
1163                 CS42L42_HSBIAS_REF_MASK |
1164                 CS42L42_HSDET_AUTO_TIME_MASK,
1165                 (0 << CS42L42_HSDET_CTRL_SHIFT) |
1166                 (0 << CS42L42_HSDET_SET_SHIFT) |
1167                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1168                 (0 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1169 
1170         /* Configure HS DET comparator reference levels. */
1171         regmap_update_bits(cs42l42->regmap,
1172                                 CS42L42_HSDET_CTL1,
1173                                 CS42L42_HSDET_COMP1_LVL_MASK |
1174                                 CS42L42_HSDET_COMP2_LVL_MASK,
1175                                 (CS42L42_HSDET_COMP1_LVL_DEFAULT << CS42L42_HSDET_COMP1_LVL_SHIFT) |
1176                                 (CS42L42_HSDET_COMP2_LVL_DEFAULT << CS42L42_HSDET_COMP2_LVL_SHIFT));
1177 }
1178 
1179 static void cs42l42_process_hs_type_detect(struct cs42l42_private *cs42l42)
1180 {
1181         unsigned int hs_det_status;
1182         unsigned int int_status;
1183 
1184         /* Read and save the hs detection result */
1185         regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status);
1186 
1187         /* Mask the auto detect interrupt */
1188         regmap_update_bits(cs42l42->regmap,
1189                 CS42L42_CODEC_INT_MASK,
1190                 CS42L42_PDN_DONE_MASK |
1191                 CS42L42_HSDET_AUTO_DONE_MASK,
1192                 (1 << CS42L42_PDN_DONE_SHIFT) |
1193                 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1194 
1195 
1196         cs42l42->hs_type = (hs_det_status & CS42L42_HSDET_TYPE_MASK) >>
1197                                 CS42L42_HSDET_TYPE_SHIFT;
1198 
1199         /* Set hs detect to automatic, disabled mode */
1200         regmap_update_bits(cs42l42->regmap,
1201                 CS42L42_HSDET_CTL2,
1202                 CS42L42_HSDET_CTRL_MASK |
1203                 CS42L42_HSDET_SET_MASK |
1204                 CS42L42_HSBIAS_REF_MASK |
1205                 CS42L42_HSDET_AUTO_TIME_MASK,
1206                 (2 << CS42L42_HSDET_CTRL_SHIFT) |
1207                 (2 << CS42L42_HSDET_SET_SHIFT) |
1208                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1209                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1210 
1211         /* Run Manual detection if auto detect has not found a headset.
1212          * We Re-Run with Manual Detection if the original detection was invalid or headphones,
1213          * to ensure that a headset mic is detected in all cases.
1214          */
1215         if (cs42l42->hs_type == CS42L42_PLUG_INVALID ||
1216                 cs42l42->hs_type == CS42L42_PLUG_HEADPHONE) {
1217                 dev_dbg(cs42l42->dev, "Running Manual Detection Fallback\n");
1218                 cs42l42_manual_hs_type_detect(cs42l42);
1219         }
1220 
1221         /* Set up button detection */
1222         if ((cs42l42->hs_type == CS42L42_PLUG_CTIA) ||
1223               (cs42l42->hs_type == CS42L42_PLUG_OMTP)) {
1224                 /* Set auto HS bias settings to default */
1225                 regmap_update_bits(cs42l42->regmap,
1226                         CS42L42_HSBIAS_SC_AUTOCTL,
1227                         CS42L42_HSBIAS_SENSE_EN_MASK |
1228                         CS42L42_AUTO_HSBIAS_HIZ_MASK |
1229                         CS42L42_TIP_SENSE_EN_MASK |
1230                         CS42L42_HSBIAS_SENSE_TRIP_MASK,
1231                         (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1232                         (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1233                         (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1234                         (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1235 
1236                 /* Set up hs detect level sensitivity */
1237                 regmap_update_bits(cs42l42->regmap,
1238                         CS42L42_MIC_DET_CTL1,
1239                         CS42L42_LATCH_TO_VP_MASK |
1240                         CS42L42_EVENT_STAT_SEL_MASK |
1241                         CS42L42_HS_DET_LEVEL_MASK,
1242                         (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1243                         (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1244                         (cs42l42->bias_thresholds[0] <<
1245                         CS42L42_HS_DET_LEVEL_SHIFT));
1246 
1247                 /* Set auto HS bias settings to default */
1248                 regmap_update_bits(cs42l42->regmap,
1249                         CS42L42_HSBIAS_SC_AUTOCTL,
1250                         CS42L42_HSBIAS_SENSE_EN_MASK |
1251                         CS42L42_AUTO_HSBIAS_HIZ_MASK |
1252                         CS42L42_TIP_SENSE_EN_MASK |
1253                         CS42L42_HSBIAS_SENSE_TRIP_MASK,
1254                         (cs42l42->hs_bias_sense_en << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1255                         (1 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1256                         (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1257                         (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1258 
1259                 /* Turn on level detect circuitry */
1260                 regmap_update_bits(cs42l42->regmap,
1261                         CS42L42_MISC_DET_CTL,
1262                         CS42L42_DETECT_MODE_MASK |
1263                         CS42L42_HSBIAS_CTL_MASK |
1264                         CS42L42_PDN_MIC_LVL_DET_MASK,
1265                         (0 << CS42L42_DETECT_MODE_SHIFT) |
1266                         (3 << CS42L42_HSBIAS_CTL_SHIFT) |
1267                         (0 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1268 
1269                 msleep(cs42l42->btn_det_init_dbnce);
1270 
1271                 /* Clear any button interrupts before unmasking them */
1272                 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2,
1273                             &int_status);
1274 
1275                 /* Unmask button detect interrupts */
1276                 regmap_update_bits(cs42l42->regmap,
1277                         CS42L42_DET_INT2_MASK,
1278                         CS42L42_M_DETECT_TF_MASK |
1279                         CS42L42_M_DETECT_FT_MASK |
1280                         CS42L42_M_HSBIAS_HIZ_MASK |
1281                         CS42L42_M_SHORT_RLS_MASK |
1282                         CS42L42_M_SHORT_DET_MASK,
1283                         (0 << CS42L42_M_DETECT_TF_SHIFT) |
1284                         (0 << CS42L42_M_DETECT_FT_SHIFT) |
1285                         (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1286                         (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1287                         (1 << CS42L42_M_SHORT_DET_SHIFT));
1288         } else {
1289                 /* Make sure button detect and HS bias circuits are off */
1290                 regmap_update_bits(cs42l42->regmap,
1291                         CS42L42_MISC_DET_CTL,
1292                         CS42L42_DETECT_MODE_MASK |
1293                         CS42L42_HSBIAS_CTL_MASK |
1294                         CS42L42_PDN_MIC_LVL_DET_MASK,
1295                         (0 << CS42L42_DETECT_MODE_SHIFT) |
1296                         (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1297                         (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1298         }
1299 
1300         regmap_update_bits(cs42l42->regmap,
1301                                 CS42L42_DAC_CTL2,
1302                                 CS42L42_HPOUT_PULLDOWN_MASK |
1303                                 CS42L42_HPOUT_LOAD_MASK |
1304                                 CS42L42_HPOUT_CLAMP_MASK |
1305                                 CS42L42_DAC_HPF_EN_MASK |
1306                                 CS42L42_DAC_MON_EN_MASK,
1307                                 (0 << CS42L42_HPOUT_PULLDOWN_SHIFT) |
1308                                 (0 << CS42L42_HPOUT_LOAD_SHIFT) |
1309                                 (0 << CS42L42_HPOUT_CLAMP_SHIFT) |
1310                                 (1 << CS42L42_DAC_HPF_EN_SHIFT) |
1311                                 (0 << CS42L42_DAC_MON_EN_SHIFT));
1312 
1313         /* Unmask tip sense interrupts */
1314         regmap_update_bits(cs42l42->regmap,
1315                 CS42L42_TSRS_PLUG_INT_MASK,
1316                 CS42L42_RS_PLUG_MASK |
1317                 CS42L42_RS_UNPLUG_MASK |
1318                 CS42L42_TS_PLUG_MASK |
1319                 CS42L42_TS_UNPLUG_MASK,
1320                 (1 << CS42L42_RS_PLUG_SHIFT) |
1321                 (1 << CS42L42_RS_UNPLUG_SHIFT) |
1322                 (0 << CS42L42_TS_PLUG_SHIFT) |
1323                 (0 << CS42L42_TS_UNPLUG_SHIFT));
1324 }
1325 
1326 static void cs42l42_init_hs_type_detect(struct cs42l42_private *cs42l42)
1327 {
1328         /* Mask tip sense interrupts */
1329         regmap_update_bits(cs42l42->regmap,
1330                                 CS42L42_TSRS_PLUG_INT_MASK,
1331                                 CS42L42_RS_PLUG_MASK |
1332                                 CS42L42_RS_UNPLUG_MASK |
1333                                 CS42L42_TS_PLUG_MASK |
1334                                 CS42L42_TS_UNPLUG_MASK,
1335                                 (1 << CS42L42_RS_PLUG_SHIFT) |
1336                                 (1 << CS42L42_RS_UNPLUG_SHIFT) |
1337                                 (1 << CS42L42_TS_PLUG_SHIFT) |
1338                                 (1 << CS42L42_TS_UNPLUG_SHIFT));
1339 
1340         /* Make sure button detect and HS bias circuits are off */
1341         regmap_update_bits(cs42l42->regmap,
1342                                 CS42L42_MISC_DET_CTL,
1343                                 CS42L42_DETECT_MODE_MASK |
1344                                 CS42L42_HSBIAS_CTL_MASK |
1345                                 CS42L42_PDN_MIC_LVL_DET_MASK,
1346                                 (0 << CS42L42_DETECT_MODE_SHIFT) |
1347                                 (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1348                                 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1349 
1350         /* Set auto HS bias settings to default */
1351         regmap_update_bits(cs42l42->regmap,
1352                                 CS42L42_HSBIAS_SC_AUTOCTL,
1353                                 CS42L42_HSBIAS_SENSE_EN_MASK |
1354                                 CS42L42_AUTO_HSBIAS_HIZ_MASK |
1355                                 CS42L42_TIP_SENSE_EN_MASK |
1356                                 CS42L42_HSBIAS_SENSE_TRIP_MASK,
1357                                 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1358                                 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1359                                 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1360                                 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1361 
1362         /* Set hs detect to manual, disabled mode */
1363         regmap_update_bits(cs42l42->regmap,
1364                                 CS42L42_HSDET_CTL2,
1365                                 CS42L42_HSDET_CTRL_MASK |
1366                                 CS42L42_HSDET_SET_MASK |
1367                                 CS42L42_HSBIAS_REF_MASK |
1368                                 CS42L42_HSDET_AUTO_TIME_MASK,
1369                                 (0 << CS42L42_HSDET_CTRL_SHIFT) |
1370                                 (2 << CS42L42_HSDET_SET_SHIFT) |
1371                                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1372                                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1373 
1374         regmap_update_bits(cs42l42->regmap,
1375                                 CS42L42_DAC_CTL2,
1376                                 CS42L42_HPOUT_PULLDOWN_MASK |
1377                                 CS42L42_HPOUT_LOAD_MASK |
1378                                 CS42L42_HPOUT_CLAMP_MASK |
1379                                 CS42L42_DAC_HPF_EN_MASK |
1380                                 CS42L42_DAC_MON_EN_MASK,
1381                                 (8 << CS42L42_HPOUT_PULLDOWN_SHIFT) |
1382                                 (0 << CS42L42_HPOUT_LOAD_SHIFT) |
1383                                 (1 << CS42L42_HPOUT_CLAMP_SHIFT) |
1384                                 (1 << CS42L42_DAC_HPF_EN_SHIFT) |
1385                                 (1 << CS42L42_DAC_MON_EN_SHIFT));
1386 
1387         /* Power up HS bias to 2.7V */
1388         regmap_update_bits(cs42l42->regmap,
1389                                 CS42L42_MISC_DET_CTL,
1390                                 CS42L42_DETECT_MODE_MASK |
1391                                 CS42L42_HSBIAS_CTL_MASK |
1392                                 CS42L42_PDN_MIC_LVL_DET_MASK,
1393                                 (0 << CS42L42_DETECT_MODE_SHIFT) |
1394                                 (3 << CS42L42_HSBIAS_CTL_SHIFT) |
1395                                 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1396 
1397         /* Wait for HS bias to ramp up */
1398         msleep(cs42l42->hs_bias_ramp_time);
1399 
1400         /* Unmask auto detect interrupt */
1401         regmap_update_bits(cs42l42->regmap,
1402                                 CS42L42_CODEC_INT_MASK,
1403                                 CS42L42_PDN_DONE_MASK |
1404                                 CS42L42_HSDET_AUTO_DONE_MASK,
1405                                 (1 << CS42L42_PDN_DONE_SHIFT) |
1406                                 (0 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1407 
1408         /* Set hs detect to automatic, enabled mode */
1409         regmap_update_bits(cs42l42->regmap,
1410                                 CS42L42_HSDET_CTL2,
1411                                 CS42L42_HSDET_CTRL_MASK |
1412                                 CS42L42_HSDET_SET_MASK |
1413                                 CS42L42_HSBIAS_REF_MASK |
1414                                 CS42L42_HSDET_AUTO_TIME_MASK,
1415                                 (3 << CS42L42_HSDET_CTRL_SHIFT) |
1416                                 (2 << CS42L42_HSDET_SET_SHIFT) |
1417                                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1418                                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1419 }
1420 
1421 static void cs42l42_cancel_hs_type_detect(struct cs42l42_private *cs42l42)
1422 {
1423         /* Mask button detect interrupts */
1424         regmap_update_bits(cs42l42->regmap,
1425                 CS42L42_DET_INT2_MASK,
1426                 CS42L42_M_DETECT_TF_MASK |
1427                 CS42L42_M_DETECT_FT_MASK |
1428                 CS42L42_M_HSBIAS_HIZ_MASK |
1429                 CS42L42_M_SHORT_RLS_MASK |
1430                 CS42L42_M_SHORT_DET_MASK,
1431                 (1 << CS42L42_M_DETECT_TF_SHIFT) |
1432                 (1 << CS42L42_M_DETECT_FT_SHIFT) |
1433                 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1434                 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1435                 (1 << CS42L42_M_SHORT_DET_SHIFT));
1436 
1437         /* Ground HS bias */
1438         regmap_update_bits(cs42l42->regmap,
1439                                 CS42L42_MISC_DET_CTL,
1440                                 CS42L42_DETECT_MODE_MASK |
1441                                 CS42L42_HSBIAS_CTL_MASK |
1442                                 CS42L42_PDN_MIC_LVL_DET_MASK,
1443                                 (0 << CS42L42_DETECT_MODE_SHIFT) |
1444                                 (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1445                                 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1446 
1447         /* Set auto HS bias settings to default */
1448         regmap_update_bits(cs42l42->regmap,
1449                                 CS42L42_HSBIAS_SC_AUTOCTL,
1450                                 CS42L42_HSBIAS_SENSE_EN_MASK |
1451                                 CS42L42_AUTO_HSBIAS_HIZ_MASK |
1452                                 CS42L42_TIP_SENSE_EN_MASK |
1453                                 CS42L42_HSBIAS_SENSE_TRIP_MASK,
1454                                 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1455                                 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1456                                 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1457                                 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1458 
1459         /* Set hs detect to manual, disabled mode */
1460         regmap_update_bits(cs42l42->regmap,
1461                                 CS42L42_HSDET_CTL2,
1462                                 CS42L42_HSDET_CTRL_MASK |
1463                                 CS42L42_HSDET_SET_MASK |
1464                                 CS42L42_HSBIAS_REF_MASK |
1465                                 CS42L42_HSDET_AUTO_TIME_MASK,
1466                                 (0 << CS42L42_HSDET_CTRL_SHIFT) |
1467                                 (2 << CS42L42_HSDET_SET_SHIFT) |
1468                                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1469                                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1470 }
1471 
1472 static int cs42l42_handle_button_press(struct cs42l42_private *cs42l42)
1473 {
1474         int bias_level;
1475         unsigned int detect_status;
1476 
1477         /* Mask button detect interrupts */
1478         regmap_update_bits(cs42l42->regmap,
1479                 CS42L42_DET_INT2_MASK,
1480                 CS42L42_M_DETECT_TF_MASK |
1481                 CS42L42_M_DETECT_FT_MASK |
1482                 CS42L42_M_HSBIAS_HIZ_MASK |
1483                 CS42L42_M_SHORT_RLS_MASK |
1484                 CS42L42_M_SHORT_DET_MASK,
1485                 (1 << CS42L42_M_DETECT_TF_SHIFT) |
1486                 (1 << CS42L42_M_DETECT_FT_SHIFT) |
1487                 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1488                 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1489                 (1 << CS42L42_M_SHORT_DET_SHIFT));
1490 
1491         usleep_range(cs42l42->btn_det_event_dbnce * 1000,
1492                      cs42l42->btn_det_event_dbnce * 2000);
1493 
1494         /* Test all 4 level detect biases */
1495         bias_level = 1;
1496         do {
1497                 /* Adjust button detect level sensitivity */
1498                 regmap_update_bits(cs42l42->regmap,
1499                         CS42L42_MIC_DET_CTL1,
1500                         CS42L42_LATCH_TO_VP_MASK |
1501                         CS42L42_EVENT_STAT_SEL_MASK |
1502                         CS42L42_HS_DET_LEVEL_MASK,
1503                         (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1504                         (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1505                         (cs42l42->bias_thresholds[bias_level] <<
1506                         CS42L42_HS_DET_LEVEL_SHIFT));
1507 
1508                 regmap_read(cs42l42->regmap, CS42L42_DET_STATUS2,
1509                                 &detect_status);
1510         } while ((detect_status & CS42L42_HS_TRUE_MASK) &&
1511                 (++bias_level < CS42L42_NUM_BIASES));
1512 
1513         switch (bias_level) {
1514         case 1: /* Function C button press */
1515                 bias_level = SND_JACK_BTN_2;
1516                 dev_dbg(cs42l42->dev, "Function C button press\n");
1517                 break;
1518         case 2: /* Function B button press */
1519                 bias_level = SND_JACK_BTN_1;
1520                 dev_dbg(cs42l42->dev, "Function B button press\n");
1521                 break;
1522         case 3: /* Function D button press */
1523                 bias_level = SND_JACK_BTN_3;
1524                 dev_dbg(cs42l42->dev, "Function D button press\n");
1525                 break;
1526         case 4: /* Function A button press */
1527                 bias_level = SND_JACK_BTN_0;
1528                 dev_dbg(cs42l42->dev, "Function A button press\n");
1529                 break;
1530         default:
1531                 bias_level = 0;
1532                 break;
1533         }
1534 
1535         /* Set button detect level sensitivity back to default */
1536         regmap_update_bits(cs42l42->regmap,
1537                 CS42L42_MIC_DET_CTL1,
1538                 CS42L42_LATCH_TO_VP_MASK |
1539                 CS42L42_EVENT_STAT_SEL_MASK |
1540                 CS42L42_HS_DET_LEVEL_MASK,
1541                 (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1542                 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1543                 (cs42l42->bias_thresholds[0] << CS42L42_HS_DET_LEVEL_SHIFT));
1544 
1545         /* Clear any button interrupts before unmasking them */
1546         regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2,
1547                     &detect_status);
1548 
1549         /* Unmask button detect interrupts */
1550         regmap_update_bits(cs42l42->regmap,
1551                 CS42L42_DET_INT2_MASK,
1552                 CS42L42_M_DETECT_TF_MASK |
1553                 CS42L42_M_DETECT_FT_MASK |
1554                 CS42L42_M_HSBIAS_HIZ_MASK |
1555                 CS42L42_M_SHORT_RLS_MASK |
1556                 CS42L42_M_SHORT_DET_MASK,
1557                 (0 << CS42L42_M_DETECT_TF_SHIFT) |
1558                 (0 << CS42L42_M_DETECT_FT_SHIFT) |
1559                 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1560                 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1561                 (1 << CS42L42_M_SHORT_DET_SHIFT));
1562 
1563         return bias_level;
1564 }
1565 
1566 struct cs42l42_irq_params {
1567         u16 status_addr;
1568         u16 mask_addr;
1569         u8 mask;
1570 };
1571 
1572 static const struct cs42l42_irq_params irq_params_table[] = {
1573         {CS42L42_ADC_OVFL_STATUS, CS42L42_ADC_OVFL_INT_MASK,
1574                 CS42L42_ADC_OVFL_VAL_MASK},
1575         {CS42L42_MIXER_STATUS, CS42L42_MIXER_INT_MASK,
1576                 CS42L42_MIXER_VAL_MASK},
1577         {CS42L42_SRC_STATUS, CS42L42_SRC_INT_MASK,
1578                 CS42L42_SRC_VAL_MASK},
1579         {CS42L42_ASP_RX_STATUS, CS42L42_ASP_RX_INT_MASK,
1580                 CS42L42_ASP_RX_VAL_MASK},
1581         {CS42L42_ASP_TX_STATUS, CS42L42_ASP_TX_INT_MASK,
1582                 CS42L42_ASP_TX_VAL_MASK},
1583         {CS42L42_CODEC_STATUS, CS42L42_CODEC_INT_MASK,
1584                 CS42L42_CODEC_VAL_MASK},
1585         {CS42L42_DET_INT_STATUS1, CS42L42_DET_INT1_MASK,
1586                 CS42L42_DET_INT_VAL1_MASK},
1587         {CS42L42_DET_INT_STATUS2, CS42L42_DET_INT2_MASK,
1588                 CS42L42_DET_INT_VAL2_MASK},
1589         {CS42L42_SRCPL_INT_STATUS, CS42L42_SRCPL_INT_MASK,
1590                 CS42L42_SRCPL_VAL_MASK},
1591         {CS42L42_VPMON_STATUS, CS42L42_VPMON_INT_MASK,
1592                 CS42L42_VPMON_VAL_MASK},
1593         {CS42L42_PLL_LOCK_STATUS, CS42L42_PLL_LOCK_INT_MASK,
1594                 CS42L42_PLL_LOCK_VAL_MASK},
1595         {CS42L42_TSRS_PLUG_STATUS, CS42L42_TSRS_PLUG_INT_MASK,
1596                 CS42L42_TSRS_PLUG_VAL_MASK}
1597 };
1598 
1599 static irqreturn_t cs42l42_irq_thread(int irq, void *data)
1600 {
1601         struct cs42l42_private *cs42l42 = (struct cs42l42_private *)data;
1602         unsigned int stickies[12];
1603         unsigned int masks[12];
1604         unsigned int current_plug_status;
1605         unsigned int current_button_status;
1606         unsigned int i;
1607         int report = 0;
1608 
1609 
1610         /* Read sticky registers to clear interurpt */
1611         for (i = 0; i < ARRAY_SIZE(stickies); i++) {
1612                 regmap_read(cs42l42->regmap, irq_params_table[i].status_addr,
1613                                 &(stickies[i]));
1614                 regmap_read(cs42l42->regmap, irq_params_table[i].mask_addr,
1615                                 &(masks[i]));
1616                 stickies[i] = stickies[i] & (~masks[i]) &
1617                                 irq_params_table[i].mask;
1618         }
1619 
1620         /* Read tip sense status before handling type detect */
1621         current_plug_status = (stickies[11] &
1622                 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >>
1623                 CS42L42_TS_PLUG_SHIFT;
1624 
1625         /* Read button sense status */
1626         current_button_status = stickies[7] &
1627                 (CS42L42_M_DETECT_TF_MASK |
1628                 CS42L42_M_DETECT_FT_MASK |
1629                 CS42L42_M_HSBIAS_HIZ_MASK);
1630 
1631         mutex_lock(&cs42l42->jack_detect_mutex);
1632 
1633         /*
1634          * Check auto-detect status. Don't assume a previous unplug event has
1635          * cleared the flags. If the jack is unplugged and plugged during
1636          * system suspend there won't have been an unplug event.
1637          */
1638         if ((~masks[5]) & irq_params_table[5].mask) {
1639                 if (stickies[5] & CS42L42_HSDET_AUTO_DONE_MASK) {
1640                         cs42l42_process_hs_type_detect(cs42l42);
1641                         switch (cs42l42->hs_type) {
1642                         case CS42L42_PLUG_CTIA:
1643                         case CS42L42_PLUG_OMTP:
1644                                 snd_soc_jack_report(cs42l42->jack, SND_JACK_HEADSET,
1645                                                     SND_JACK_HEADSET |
1646                                                     SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1647                                                     SND_JACK_BTN_2 | SND_JACK_BTN_3);
1648                                 break;
1649                         case CS42L42_PLUG_HEADPHONE:
1650                                 snd_soc_jack_report(cs42l42->jack, SND_JACK_HEADPHONE,
1651                                                     SND_JACK_HEADSET |
1652                                                     SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1653                                                     SND_JACK_BTN_2 | SND_JACK_BTN_3);
1654                                 break;
1655                         default:
1656                                 break;
1657                         }
1658                         dev_dbg(cs42l42->dev, "Auto detect done (%d)\n", cs42l42->hs_type);
1659                 }
1660         }
1661 
1662         /* Check tip sense status */
1663         if ((~masks[11]) & irq_params_table[11].mask) {
1664                 switch (current_plug_status) {
1665                 case CS42L42_TS_PLUG:
1666                         if (cs42l42->plug_state != CS42L42_TS_PLUG) {
1667                                 cs42l42->plug_state = CS42L42_TS_PLUG;
1668                                 cs42l42_init_hs_type_detect(cs42l42);
1669                         }
1670                         break;
1671 
1672                 case CS42L42_TS_UNPLUG:
1673                         if (cs42l42->plug_state != CS42L42_TS_UNPLUG) {
1674                                 cs42l42->plug_state = CS42L42_TS_UNPLUG;
1675                                 cs42l42_cancel_hs_type_detect(cs42l42);
1676 
1677                                 switch (cs42l42->hs_type) {
1678                                 case CS42L42_PLUG_CTIA:
1679                                 case CS42L42_PLUG_OMTP:
1680                                         snd_soc_jack_report(cs42l42->jack, 0, SND_JACK_HEADSET);
1681                                         break;
1682                                 case CS42L42_PLUG_HEADPHONE:
1683                                         snd_soc_jack_report(cs42l42->jack, 0, SND_JACK_HEADPHONE);
1684                                         break;
1685                                 default:
1686                                         break;
1687                                 }
1688                                 snd_soc_jack_report(cs42l42->jack, 0,
1689                                                     SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1690                                                     SND_JACK_BTN_2 | SND_JACK_BTN_3);
1691 
1692                                 dev_dbg(cs42l42->dev, "Unplug event\n");
1693                         }
1694                         break;
1695 
1696                 default:
1697                         if (cs42l42->plug_state != CS42L42_TS_TRANS)
1698                                 cs42l42->plug_state = CS42L42_TS_TRANS;
1699                 }
1700         }
1701 
1702         /* Check button detect status */
1703         if (cs42l42->plug_state == CS42L42_TS_PLUG && ((~masks[7]) & irq_params_table[7].mask)) {
1704                 if (!(current_button_status &
1705                         CS42L42_M_HSBIAS_HIZ_MASK)) {
1706 
1707                         if (current_button_status & CS42L42_M_DETECT_TF_MASK) {
1708                                 dev_dbg(cs42l42->dev, "Button released\n");
1709                                 report = 0;
1710                         } else if (current_button_status & CS42L42_M_DETECT_FT_MASK) {
1711                                 report = cs42l42_handle_button_press(cs42l42);
1712 
1713                         }
1714                         snd_soc_jack_report(cs42l42->jack, report, SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1715                                                                    SND_JACK_BTN_2 | SND_JACK_BTN_3);
1716                 }
1717         }
1718 
1719         mutex_unlock(&cs42l42->jack_detect_mutex);
1720 
1721         return IRQ_HANDLED;
1722 }
1723 
1724 static void cs42l42_set_interrupt_masks(struct cs42l42_private *cs42l42)
1725 {
1726         regmap_update_bits(cs42l42->regmap, CS42L42_ADC_OVFL_INT_MASK,
1727                         CS42L42_ADC_OVFL_MASK,
1728                         (1 << CS42L42_ADC_OVFL_SHIFT));
1729 
1730         regmap_update_bits(cs42l42->regmap, CS42L42_MIXER_INT_MASK,
1731                         CS42L42_MIX_CHB_OVFL_MASK |
1732                         CS42L42_MIX_CHA_OVFL_MASK |
1733                         CS42L42_EQ_OVFL_MASK |
1734                         CS42L42_EQ_BIQUAD_OVFL_MASK,
1735                         (1 << CS42L42_MIX_CHB_OVFL_SHIFT) |
1736                         (1 << CS42L42_MIX_CHA_OVFL_SHIFT) |
1737                         (1 << CS42L42_EQ_OVFL_SHIFT) |
1738                         (1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT));
1739 
1740         regmap_update_bits(cs42l42->regmap, CS42L42_SRC_INT_MASK,
1741                         CS42L42_SRC_ILK_MASK |
1742                         CS42L42_SRC_OLK_MASK |
1743                         CS42L42_SRC_IUNLK_MASK |
1744                         CS42L42_SRC_OUNLK_MASK,
1745                         (1 << CS42L42_SRC_ILK_SHIFT) |
1746                         (1 << CS42L42_SRC_OLK_SHIFT) |
1747                         (1 << CS42L42_SRC_IUNLK_SHIFT) |
1748                         (1 << CS42L42_SRC_OUNLK_SHIFT));
1749 
1750         regmap_update_bits(cs42l42->regmap, CS42L42_ASP_RX_INT_MASK,
1751                         CS42L42_ASPRX_NOLRCK_MASK |
1752                         CS42L42_ASPRX_EARLY_MASK |
1753                         CS42L42_ASPRX_LATE_MASK |
1754                         CS42L42_ASPRX_ERROR_MASK |
1755                         CS42L42_ASPRX_OVLD_MASK,
1756                         (1 << CS42L42_ASPRX_NOLRCK_SHIFT) |
1757                         (1 << CS42L42_ASPRX_EARLY_SHIFT) |
1758                         (1 << CS42L42_ASPRX_LATE_SHIFT) |
1759                         (1 << CS42L42_ASPRX_ERROR_SHIFT) |
1760                         (1 << CS42L42_ASPRX_OVLD_SHIFT));
1761 
1762         regmap_update_bits(cs42l42->regmap, CS42L42_ASP_TX_INT_MASK,
1763                         CS42L42_ASPTX_NOLRCK_MASK |
1764                         CS42L42_ASPTX_EARLY_MASK |
1765                         CS42L42_ASPTX_LATE_MASK |
1766                         CS42L42_ASPTX_SMERROR_MASK,
1767                         (1 << CS42L42_ASPTX_NOLRCK_SHIFT) |
1768                         (1 << CS42L42_ASPTX_EARLY_SHIFT) |
1769                         (1 << CS42L42_ASPTX_LATE_SHIFT) |
1770                         (1 << CS42L42_ASPTX_SMERROR_SHIFT));
1771 
1772         regmap_update_bits(cs42l42->regmap, CS42L42_CODEC_INT_MASK,
1773                         CS42L42_PDN_DONE_MASK |
1774                         CS42L42_HSDET_AUTO_DONE_MASK,
1775                         (1 << CS42L42_PDN_DONE_SHIFT) |
1776                         (1 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1777 
1778         regmap_update_bits(cs42l42->regmap, CS42L42_SRCPL_INT_MASK,
1779                         CS42L42_SRCPL_ADC_LK_MASK |
1780                         CS42L42_SRCPL_DAC_LK_MASK |
1781                         CS42L42_SRCPL_ADC_UNLK_MASK |
1782                         CS42L42_SRCPL_DAC_UNLK_MASK,
1783                         (1 << CS42L42_SRCPL_ADC_LK_SHIFT) |
1784                         (1 << CS42L42_SRCPL_DAC_LK_SHIFT) |
1785                         (1 << CS42L42_SRCPL_ADC_UNLK_SHIFT) |
1786                         (1 << CS42L42_SRCPL_DAC_UNLK_SHIFT));
1787 
1788         regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT1_MASK,
1789                         CS42L42_TIP_SENSE_UNPLUG_MASK |
1790                         CS42L42_TIP_SENSE_PLUG_MASK |
1791                         CS42L42_HSBIAS_SENSE_MASK,
1792                         (1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT) |
1793                         (1 << CS42L42_TIP_SENSE_PLUG_SHIFT) |
1794                         (1 << CS42L42_HSBIAS_SENSE_SHIFT));
1795 
1796         regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT2_MASK,
1797                         CS42L42_M_DETECT_TF_MASK |
1798                         CS42L42_M_DETECT_FT_MASK |
1799                         CS42L42_M_HSBIAS_HIZ_MASK |
1800                         CS42L42_M_SHORT_RLS_MASK |
1801                         CS42L42_M_SHORT_DET_MASK,
1802                         (1 << CS42L42_M_DETECT_TF_SHIFT) |
1803                         (1 << CS42L42_M_DETECT_FT_SHIFT) |
1804                         (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1805                         (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1806                         (1 << CS42L42_M_SHORT_DET_SHIFT));
1807 
1808         regmap_update_bits(cs42l42->regmap, CS42L42_VPMON_INT_MASK,
1809                         CS42L42_VPMON_MASK,
1810                         (1 << CS42L42_VPMON_SHIFT));
1811 
1812         regmap_update_bits(cs42l42->regmap, CS42L42_PLL_LOCK_INT_MASK,
1813                         CS42L42_PLL_LOCK_MASK,
1814                         (1 << CS42L42_PLL_LOCK_SHIFT));
1815 
1816         regmap_update_bits(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK,
1817                         CS42L42_RS_PLUG_MASK |
1818                         CS42L42_RS_UNPLUG_MASK |
1819                         CS42L42_TS_PLUG_MASK |
1820                         CS42L42_TS_UNPLUG_MASK,
1821                         (1 << CS42L42_RS_PLUG_SHIFT) |
1822                         (1 << CS42L42_RS_UNPLUG_SHIFT) |
1823                         (0 << CS42L42_TS_PLUG_SHIFT) |
1824                         (0 << CS42L42_TS_UNPLUG_SHIFT));
1825 }
1826 
1827 static void cs42l42_setup_hs_type_detect(struct cs42l42_private *cs42l42)
1828 {
1829         unsigned int reg;
1830 
1831         cs42l42->hs_type = CS42L42_PLUG_INVALID;
1832 
1833         /* Latch analog controls to VP power domain */
1834         regmap_update_bits(cs42l42->regmap, CS42L42_MIC_DET_CTL1,
1835                         CS42L42_LATCH_TO_VP_MASK |
1836                         CS42L42_EVENT_STAT_SEL_MASK |
1837                         CS42L42_HS_DET_LEVEL_MASK,
1838                         (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1839                         (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1840                         (cs42l42->bias_thresholds[0] <<
1841                         CS42L42_HS_DET_LEVEL_SHIFT));
1842 
1843         /* Remove ground noise-suppression clamps */
1844         regmap_update_bits(cs42l42->regmap,
1845                         CS42L42_HS_CLAMP_DISABLE,
1846                         CS42L42_HS_CLAMP_DISABLE_MASK,
1847                         (1 << CS42L42_HS_CLAMP_DISABLE_SHIFT));
1848 
1849         /* Enable the tip sense circuit */
1850         regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1851                            CS42L42_TS_INV_MASK, CS42L42_TS_INV_MASK);
1852 
1853         regmap_update_bits(cs42l42->regmap, CS42L42_TIPSENSE_CTL,
1854                         CS42L42_TIP_SENSE_CTRL_MASK |
1855                         CS42L42_TIP_SENSE_INV_MASK |
1856                         CS42L42_TIP_SENSE_DEBOUNCE_MASK,
1857                         (3 << CS42L42_TIP_SENSE_CTRL_SHIFT) |
1858                         (!cs42l42->ts_inv << CS42L42_TIP_SENSE_INV_SHIFT) |
1859                         (2 << CS42L42_TIP_SENSE_DEBOUNCE_SHIFT));
1860 
1861         /* Save the initial status of the tip sense */
1862         regmap_read(cs42l42->regmap,
1863                           CS42L42_TSRS_PLUG_STATUS,
1864                           &reg);
1865         cs42l42->plug_state = (((char) reg) &
1866                       (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >>
1867                       CS42L42_TS_PLUG_SHIFT;
1868 }
1869 
1870 static const unsigned int threshold_defaults[] = {
1871         CS42L42_HS_DET_LEVEL_15,
1872         CS42L42_HS_DET_LEVEL_8,
1873         CS42L42_HS_DET_LEVEL_4,
1874         CS42L42_HS_DET_LEVEL_1
1875 };
1876 
1877 static int cs42l42_handle_device_data(struct device *dev,
1878                                         struct cs42l42_private *cs42l42)
1879 {
1880         unsigned int val;
1881         u32 thresholds[CS42L42_NUM_BIASES];
1882         int ret;
1883         int i;
1884 
1885         ret = device_property_read_u32(dev, "cirrus,ts-inv", &val);
1886         if (!ret) {
1887                 switch (val) {
1888                 case CS42L42_TS_INV_EN:
1889                 case CS42L42_TS_INV_DIS:
1890                         cs42l42->ts_inv = val;
1891                         break;
1892                 default:
1893                         dev_err(dev,
1894                                 "Wrong cirrus,ts-inv DT value %d\n",
1895                                 val);
1896                         cs42l42->ts_inv = CS42L42_TS_INV_DIS;
1897                 }
1898         } else {
1899                 cs42l42->ts_inv = CS42L42_TS_INV_DIS;
1900         }
1901 
1902         ret = device_property_read_u32(dev, "cirrus,ts-dbnc-rise", &val);
1903         if (!ret) {
1904                 switch (val) {
1905                 case CS42L42_TS_DBNCE_0:
1906                 case CS42L42_TS_DBNCE_125:
1907                 case CS42L42_TS_DBNCE_250:
1908                 case CS42L42_TS_DBNCE_500:
1909                 case CS42L42_TS_DBNCE_750:
1910                 case CS42L42_TS_DBNCE_1000:
1911                 case CS42L42_TS_DBNCE_1250:
1912                 case CS42L42_TS_DBNCE_1500:
1913                         cs42l42->ts_dbnc_rise = val;
1914                         break;
1915                 default:
1916                         dev_err(dev,
1917                                 "Wrong cirrus,ts-dbnc-rise DT value %d\n",
1918                                 val);
1919                         cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000;
1920                 }
1921         } else {
1922                 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000;
1923         }
1924 
1925         regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1926                         CS42L42_TS_RISE_DBNCE_TIME_MASK,
1927                         (cs42l42->ts_dbnc_rise <<
1928                         CS42L42_TS_RISE_DBNCE_TIME_SHIFT));
1929 
1930         ret = device_property_read_u32(dev, "cirrus,ts-dbnc-fall", &val);
1931         if (!ret) {
1932                 switch (val) {
1933                 case CS42L42_TS_DBNCE_0:
1934                 case CS42L42_TS_DBNCE_125:
1935                 case CS42L42_TS_DBNCE_250:
1936                 case CS42L42_TS_DBNCE_500:
1937                 case CS42L42_TS_DBNCE_750:
1938                 case CS42L42_TS_DBNCE_1000:
1939                 case CS42L42_TS_DBNCE_1250:
1940                 case CS42L42_TS_DBNCE_1500:
1941                         cs42l42->ts_dbnc_fall = val;
1942                         break;
1943                 default:
1944                         dev_err(dev,
1945                                 "Wrong cirrus,ts-dbnc-fall DT value %d\n",
1946                                 val);
1947                         cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0;
1948                 }
1949         } else {
1950                 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0;
1951         }
1952 
1953         regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1954                         CS42L42_TS_FALL_DBNCE_TIME_MASK,
1955                         (cs42l42->ts_dbnc_fall <<
1956                         CS42L42_TS_FALL_DBNCE_TIME_SHIFT));
1957 
1958         ret = device_property_read_u32(dev, "cirrus,btn-det-init-dbnce", &val);
1959         if (!ret) {
1960                 if (val <= CS42L42_BTN_DET_INIT_DBNCE_MAX)
1961                         cs42l42->btn_det_init_dbnce = val;
1962                 else {
1963                         dev_err(dev,
1964                                 "Wrong cirrus,btn-det-init-dbnce DT value %d\n",
1965                                 val);
1966                         cs42l42->btn_det_init_dbnce =
1967                                 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT;
1968                 }
1969         } else {
1970                 cs42l42->btn_det_init_dbnce =
1971                         CS42L42_BTN_DET_INIT_DBNCE_DEFAULT;
1972         }
1973 
1974         ret = device_property_read_u32(dev, "cirrus,btn-det-event-dbnce", &val);
1975         if (!ret) {
1976                 if (val <= CS42L42_BTN_DET_EVENT_DBNCE_MAX)
1977                         cs42l42->btn_det_event_dbnce = val;
1978                 else {
1979                         dev_err(dev,
1980                                 "Wrong cirrus,btn-det-event-dbnce DT value %d\n", val);
1981                         cs42l42->btn_det_event_dbnce =
1982                                 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT;
1983                 }
1984         } else {
1985                 cs42l42->btn_det_event_dbnce =
1986                         CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT;
1987         }
1988 
1989         ret = device_property_read_u32_array(dev, "cirrus,bias-lvls",
1990                                              thresholds, ARRAY_SIZE(thresholds));
1991         if (!ret) {
1992                 for (i = 0; i < CS42L42_NUM_BIASES; i++) {
1993                         if (thresholds[i] <= CS42L42_HS_DET_LEVEL_MAX)
1994                                 cs42l42->bias_thresholds[i] = thresholds[i];
1995                         else {
1996                                 dev_err(dev,
1997                                         "Wrong cirrus,bias-lvls[%d] DT value %d\n", i,
1998                                         thresholds[i]);
1999                                 cs42l42->bias_thresholds[i] = threshold_defaults[i];
2000                         }
2001                 }
2002         } else {
2003                 for (i = 0; i < CS42L42_NUM_BIASES; i++)
2004                         cs42l42->bias_thresholds[i] = threshold_defaults[i];
2005         }
2006 
2007         ret = device_property_read_u32(dev, "cirrus,hs-bias-ramp-rate", &val);
2008         if (!ret) {
2009                 switch (val) {
2010                 case CS42L42_HSBIAS_RAMP_FAST_RISE_SLOW_FALL:
2011                         cs42l42->hs_bias_ramp_rate = val;
2012                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME0;
2013                         break;
2014                 case CS42L42_HSBIAS_RAMP_FAST:
2015                         cs42l42->hs_bias_ramp_rate = val;
2016                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME1;
2017                         break;
2018                 case CS42L42_HSBIAS_RAMP_SLOW:
2019                         cs42l42->hs_bias_ramp_rate = val;
2020                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
2021                         break;
2022                 case CS42L42_HSBIAS_RAMP_SLOWEST:
2023                         cs42l42->hs_bias_ramp_rate = val;
2024                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME3;
2025                         break;
2026                 default:
2027                         dev_err(dev,
2028                                 "Wrong cirrus,hs-bias-ramp-rate DT value %d\n",
2029                                 val);
2030                         cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW;
2031                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
2032                 }
2033         } else {
2034                 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW;
2035                 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
2036         }
2037 
2038         regmap_update_bits(cs42l42->regmap, CS42L42_HS_BIAS_CTL,
2039                         CS42L42_HSBIAS_RAMP_MASK,
2040                         (cs42l42->hs_bias_ramp_rate <<
2041                         CS42L42_HSBIAS_RAMP_SHIFT));
2042 
2043         if (device_property_read_bool(dev, "cirrus,hs-bias-sense-disable"))
2044                 cs42l42->hs_bias_sense_en = 0;
2045         else
2046                 cs42l42->hs_bias_sense_en = 1;
2047 
2048         return 0;
2049 }
2050 
2051 static int cs42l42_i2c_probe(struct i2c_client *i2c_client,
2052                                        const struct i2c_device_id *id)
2053 {
2054         struct cs42l42_private *cs42l42;
2055         int ret, i, devid;
2056         unsigned int reg;
2057 
2058         cs42l42 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42l42_private),
2059                                GFP_KERNEL);
2060         if (!cs42l42)
2061                 return -ENOMEM;
2062 
2063         cs42l42->dev = &i2c_client->dev;
2064         i2c_set_clientdata(i2c_client, cs42l42);
2065         mutex_init(&cs42l42->jack_detect_mutex);
2066 
2067         cs42l42->regmap = devm_regmap_init_i2c(i2c_client, &cs42l42_regmap);
2068         if (IS_ERR(cs42l42->regmap)) {
2069                 ret = PTR_ERR(cs42l42->regmap);
2070                 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
2071                 return ret;
2072         }
2073 
2074         for (i = 0; i < ARRAY_SIZE(cs42l42->supplies); i++)
2075                 cs42l42->supplies[i].supply = cs42l42_supply_names[i];
2076 
2077         ret = devm_regulator_bulk_get(&i2c_client->dev,
2078                                       ARRAY_SIZE(cs42l42->supplies),
2079                                       cs42l42->supplies);
2080         if (ret != 0) {
2081                 dev_err(&i2c_client->dev,
2082                         "Failed to request supplies: %d\n", ret);
2083                 return ret;
2084         }
2085 
2086         ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies),
2087                                     cs42l42->supplies);
2088         if (ret != 0) {
2089                 dev_err(&i2c_client->dev,
2090                         "Failed to enable supplies: %d\n", ret);
2091                 return ret;
2092         }
2093 
2094         /* Reset the Device */
2095         cs42l42->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev,
2096                 "reset", GPIOD_OUT_LOW);
2097         if (IS_ERR(cs42l42->reset_gpio)) {
2098                 ret = PTR_ERR(cs42l42->reset_gpio);
2099                 goto err_disable_noreset;
2100         }
2101 
2102         if (cs42l42->reset_gpio) {
2103                 dev_dbg(&i2c_client->dev, "Found reset GPIO\n");
2104                 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1);
2105         }
2106         usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2);
2107 
2108         /* Request IRQ if one was specified */
2109         if (i2c_client->irq) {
2110                 ret = request_threaded_irq(i2c_client->irq,
2111                                            NULL, cs42l42_irq_thread,
2112                                            IRQF_ONESHOT | IRQF_TRIGGER_LOW,
2113                                            "cs42l42", cs42l42);
2114                 if (ret == -EPROBE_DEFER) {
2115                         goto err_disable_noirq;
2116                 } else if (ret != 0) {
2117                         dev_err(&i2c_client->dev,
2118                                 "Failed to request IRQ: %d\n", ret);
2119                         goto err_disable_noirq;
2120                 }
2121         }
2122 
2123         /* initialize codec */
2124         devid = cirrus_read_device_id(cs42l42->regmap, CS42L42_DEVID_AB);
2125         if (devid < 0) {
2126                 ret = devid;
2127                 dev_err(&i2c_client->dev, "Failed to read device ID: %d\n", ret);
2128                 goto err_disable;
2129         }
2130 
2131         if (devid != CS42L42_CHIP_ID) {
2132                 ret = -ENODEV;
2133                 dev_err(&i2c_client->dev,
2134                         "CS42L42 Device ID (%X). Expected %X\n",
2135                         devid, CS42L42_CHIP_ID);
2136                 goto err_disable;
2137         }
2138 
2139         ret = regmap_read(cs42l42->regmap, CS42L42_REVID, &reg);
2140         if (ret < 0) {
2141                 dev_err(&i2c_client->dev, "Get Revision ID failed\n");
2142                 goto err_shutdown;
2143         }
2144 
2145         dev_info(&i2c_client->dev,
2146                  "Cirrus Logic CS42L42, Revision: %02X\n", reg & 0xFF);
2147 
2148         /* Power up the codec */
2149         regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL1,
2150                         CS42L42_ASP_DAO_PDN_MASK |
2151                         CS42L42_ASP_DAI_PDN_MASK |
2152                         CS42L42_MIXER_PDN_MASK |
2153                         CS42L42_EQ_PDN_MASK |
2154                         CS42L42_HP_PDN_MASK |
2155                         CS42L42_ADC_PDN_MASK |
2156                         CS42L42_PDN_ALL_MASK,
2157                         (1 << CS42L42_ASP_DAO_PDN_SHIFT) |
2158                         (1 << CS42L42_ASP_DAI_PDN_SHIFT) |
2159                         (1 << CS42L42_MIXER_PDN_SHIFT) |
2160                         (1 << CS42L42_EQ_PDN_SHIFT) |
2161                         (1 << CS42L42_HP_PDN_SHIFT) |
2162                         (1 << CS42L42_ADC_PDN_SHIFT) |
2163                         (0 << CS42L42_PDN_ALL_SHIFT));
2164 
2165         ret = cs42l42_handle_device_data(&i2c_client->dev, cs42l42);
2166         if (ret != 0)
2167                 goto err_shutdown;
2168 
2169         /* Setup headset detection */
2170         cs42l42_setup_hs_type_detect(cs42l42);
2171 
2172         /* Mask/Unmask Interrupts */
2173         cs42l42_set_interrupt_masks(cs42l42);
2174 
2175         /* Register codec for machine driver */
2176         ret = devm_snd_soc_register_component(&i2c_client->dev,
2177                         &soc_component_dev_cs42l42, &cs42l42_dai, 1);
2178         if (ret < 0)
2179                 goto err_shutdown;
2180 
2181         return 0;
2182 
2183 err_shutdown:
2184         regmap_write(cs42l42->regmap, CS42L42_CODEC_INT_MASK, 0xff);
2185         regmap_write(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 0xff);
2186         regmap_write(cs42l42->regmap, CS42L42_PWR_CTL1, 0xff);
2187 
2188 err_disable:
2189         if (i2c_client->irq)
2190                 free_irq(i2c_client->irq, cs42l42);
2191 
2192 err_disable_noirq:
2193         gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
2194 err_disable_noreset:
2195         regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies),
2196                                 cs42l42->supplies);
2197         return ret;
2198 }
2199 
2200 static int cs42l42_i2c_remove(struct i2c_client *i2c_client)
2201 {
2202         struct cs42l42_private *cs42l42 = i2c_get_clientdata(i2c_client);
2203 
2204         if (i2c_client->irq)
2205                 free_irq(i2c_client->irq, cs42l42);
2206 
2207         /*
2208          * The driver might not have control of reset and power supplies,
2209          * so ensure that the chip internals are powered down.
2210          */
2211         regmap_write(cs42l42->regmap, CS42L42_CODEC_INT_MASK, 0xff);
2212         regmap_write(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 0xff);
2213         regmap_write(cs42l42->regmap, CS42L42_PWR_CTL1, 0xff);
2214 
2215         gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
2216         regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), cs42l42->supplies);
2217 
2218         return 0;
2219 }
2220 
2221 #ifdef CONFIG_OF
2222 static const struct of_device_id cs42l42_of_match[] = {
2223         { .compatible = "cirrus,cs42l42", },
2224         {}
2225 };
2226 MODULE_DEVICE_TABLE(of, cs42l42_of_match);
2227 #endif
2228 
2229 #ifdef CONFIG_ACPI
2230 static const struct acpi_device_id cs42l42_acpi_match[] = {
2231         {"10134242", 0,},
2232         {}
2233 };
2234 MODULE_DEVICE_TABLE(acpi, cs42l42_acpi_match);
2235 #endif
2236 
2237 static const struct i2c_device_id cs42l42_id[] = {
2238         {"cs42l42", 0},
2239         {}
2240 };
2241 
2242 MODULE_DEVICE_TABLE(i2c, cs42l42_id);
2243 
2244 static struct i2c_driver cs42l42_i2c_driver = {
2245         .driver = {
2246                 .name = "cs42l42",
2247                 .of_match_table = of_match_ptr(cs42l42_of_match),
2248                 .acpi_match_table = ACPI_PTR(cs42l42_acpi_match),
2249                 },
2250         .id_table = cs42l42_id,
2251         .probe = cs42l42_i2c_probe,
2252         .remove = cs42l42_i2c_remove,
2253 };
2254 
2255 module_i2c_driver(cs42l42_i2c_driver);
2256 
2257 MODULE_DESCRIPTION("ASoC CS42L42 driver");
2258 MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <james.schulman@cirrus.com>");
2259 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
2260 MODULE_AUTHOR("Michael White, Cirrus Logic Inc, <michael.white@cirrus.com>");
2261 MODULE_AUTHOR("Lucas Tanure <tanureal@opensource.cirrus.com>");
2262 MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>");
2263 MODULE_AUTHOR("Vitaly Rodionov <vitalyr@opensource.cirrus.com>");
2264 MODULE_LICENSE("GPL");
2265 

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