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TOMOYO Linux Cross Reference
Linux/sound/soc/codecs/cs42l42.h

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  1 /*
  2  * cs42l42.h -- CS42L42 ALSA SoC audio driver header
  3  *
  4  * Copyright 2016 Cirrus Logic, Inc.
  5  *
  6  * Author: James Schulman <james.schulman@cirrus.com>
  7  * Author: Brian Austin <brian.austin@cirrus.com>
  8  * Author: Michael White <michael.white@cirrus.com>
  9  *
 10  * This program is free software; you can redistribute it and/or modify
 11  * it under the terms of the GNU General Public License version 2 as
 12  * published by the Free Software Foundation.
 13  *
 14  */
 15 
 16 #ifndef __CS42L42_H__
 17 #define __CS42L42_H__
 18 
 19 #define CS42L42_PAGE_REGISTER   0x00    /* Page Select Register */
 20 #define CS42L42_WIN_START       0x00
 21 #define CS42L42_WIN_LEN         0x100
 22 #define CS42L42_RANGE_MIN       0x00
 23 #define CS42L42_RANGE_MAX       0x7F
 24 
 25 #define CS42L42_PAGE_10         0x1000
 26 #define CS42L42_PAGE_11         0x1100
 27 #define CS42L42_PAGE_12         0x1200
 28 #define CS42L42_PAGE_13         0x1300
 29 #define CS42L42_PAGE_15         0x1500
 30 #define CS42L42_PAGE_19         0x1900
 31 #define CS42L42_PAGE_1B         0x1B00
 32 #define CS42L42_PAGE_1C         0x1C00
 33 #define CS42L42_PAGE_1D         0x1D00
 34 #define CS42L42_PAGE_1F         0x1F00
 35 #define CS42L42_PAGE_20         0x2000
 36 #define CS42L42_PAGE_21         0x2100
 37 #define CS42L42_PAGE_23         0x2300
 38 #define CS42L42_PAGE_24         0x2400
 39 #define CS42L42_PAGE_25         0x2500
 40 #define CS42L42_PAGE_26         0x2600
 41 #define CS42L42_PAGE_28         0x2800
 42 #define CS42L42_PAGE_29         0x2900
 43 #define CS42L42_PAGE_2A         0x2A00
 44 #define CS42L42_PAGE_30         0x3000
 45 
 46 #define CS42L42_CHIP_ID         0x42A42
 47 
 48 /* Page 0x10 Global Registers */
 49 #define CS42L42_DEVID_AB                (CS42L42_PAGE_10 + 0x01)
 50 #define CS42L42_DEVID_CD                (CS42L42_PAGE_10 + 0x02)
 51 #define CS42L42_DEVID_E                 (CS42L42_PAGE_10 + 0x03)
 52 #define CS42L42_FABID                   (CS42L42_PAGE_10 + 0x04)
 53 #define CS42L42_REVID                   (CS42L42_PAGE_10 + 0x05)
 54 #define CS42L42_FRZ_CTL                 (CS42L42_PAGE_10 + 0x06)
 55 
 56 #define CS42L42_SRC_CTL                 (CS42L42_PAGE_10 + 0x07)
 57 #define CS42L42_SRC_BYPASS_DAC_SHIFT    1
 58 #define CS42L42_SRC_BYPASS_DAC_MASK     (1 << CS42L42_SRC_BYPASS_DAC_SHIFT)
 59 
 60 #define CS42L42_MCLK_STATUS             (CS42L42_PAGE_10 + 0x08)
 61 
 62 #define CS42L42_MCLK_CTL                (CS42L42_PAGE_10 + 0x09)
 63 #define CS42L42_INTERNAL_FS_SHIFT       1
 64 #define CS42L42_INTERNAL_FS_MASK        (1 << CS42L42_INTERNAL_FS_SHIFT)
 65 
 66 #define CS42L42_SFTRAMP_RATE            (CS42L42_PAGE_10 + 0x0A)
 67 #define CS42L42_I2C_DEBOUNCE            (CS42L42_PAGE_10 + 0x0E)
 68 #define CS42L42_I2C_STRETCH             (CS42L42_PAGE_10 + 0x0F)
 69 #define CS42L42_I2C_TIMEOUT             (CS42L42_PAGE_10 + 0x10)
 70 
 71 /* Page 0x11 Power and Headset Detect Registers */
 72 #define CS42L42_PWR_CTL1                (CS42L42_PAGE_11 + 0x01)
 73 #define CS42L42_ASP_DAO_PDN_SHIFT       7
 74 #define CS42L42_ASP_DAO_PDN_MASK        (1 << CS42L42_ASP_DAO_PDN_SHIFT)
 75 #define CS42L42_ASP_DAI_PDN_SHIFT       6
 76 #define CS42L42_ASP_DAI_PDN_MASK        (1 << CS42L42_ASP_DAI_PDN_SHIFT)
 77 #define CS42L42_MIXER_PDN_SHIFT         5
 78 #define CS42L42_MIXER_PDN_MASK          (1 << CS42L42_MIXER_PDN_SHIFT)
 79 #define CS42L42_EQ_PDN_SHIFT            4
 80 #define CS42L42_EQ_PDN_MASK             (1 << CS42L42_EQ_PDN_SHIFT)
 81 #define CS42L42_HP_PDN_SHIFT            3
 82 #define CS42L42_HP_PDN_MASK             (1 << CS42L42_HP_PDN_SHIFT)
 83 #define CS42L42_ADC_PDN_SHIFT           2
 84 #define CS42L42_ADC_PDN_MASK            (1 << CS42L42_HP_PDN_SHIFT)
 85 #define CS42L42_PDN_ALL_SHIFT           0
 86 #define CS42L42_PDN_ALL_MASK            (1 << CS42L42_PDN_ALL_SHIFT)
 87 
 88 #define CS42L42_PWR_CTL2                (CS42L42_PAGE_11 + 0x02)
 89 #define CS42L42_ADC_SRC_PDNB_SHIFT      0
 90 #define CS42L42_ADC_SRC_PDNB_MASK       (1 << CS42L42_ADC_SRC_PDNB_SHIFT)
 91 #define CS42L42_DAC_SRC_PDNB_SHIFT      1
 92 #define CS42L42_DAC_SRC_PDNB_MASK       (1 << CS42L42_DAC_SRC_PDNB_SHIFT)
 93 #define CS42L42_ASP_DAI1_PDN_SHIFT      2
 94 #define CS42L42_ASP_DAI1_PDN_MASK       (1 << CS42L42_ASP_DAI1_PDN_SHIFT)
 95 #define CS42L42_SRC_PDN_OVERRIDE_SHIFT  3
 96 #define CS42L42_SRC_PDN_OVERRIDE_MASK   (1 << CS42L42_SRC_PDN_OVERRIDE_SHIFT)
 97 #define CS42L42_DISCHARGE_FILT_SHIFT    4
 98 #define CS42L42_DISCHARGE_FILT_MASK     (1 << CS42L42_DISCHARGE_FILT_SHIFT)
 99 
100 #define CS42L42_PWR_CTL3                        (CS42L42_PAGE_11 + 0x03)
101 #define CS42L42_RING_SENSE_PDNB_SHIFT           1
102 #define CS42L42_RING_SENSE_PDNB_MASK            (1 << \
103                                         CS42L42_RING_SENSE_PDNB_SHIFT)
104 #define CS42L42_VPMON_PDNB_SHIFT                2
105 #define CS42L42_VPMON_PDNB_MASK                 (1 << \
106                                         CS42L42_VPMON_PDNB_SHIFT)
107 #define CS42L42_SW_CLK_STP_STAT_SEL_SHIFT       5
108 #define CS42L42_SW_CLK_STP_STAT_SEL_MASK        (3 << \
109                                         CS42L42_SW_CLK_STP_STAT_SEL_SHIFT)
110 
111 #define CS42L42_RSENSE_CTL1                     (CS42L42_PAGE_11 + 0x04)
112 #define CS42L42_RS_TRIM_R_SHIFT                 0
113 #define CS42L42_RS_TRIM_R_MASK                  (1 << \
114                                         CS42L42_RS_TRIM_R_SHIFT)
115 #define CS42L42_RS_TRIM_T_SHIFT                 1
116 #define CS42L42_RS_TRIM_T_MASK                  (1 << \
117                                         CS42L42_RS_TRIM_T_SHIFT)
118 #define CS42L42_HPREF_RS_SHIFT                  2
119 #define CS42L42_HPREF_RS_MASK                   (1 << \
120                                         CS42L42_HPREF_RS_SHIFT)
121 #define CS42L42_HSBIAS_FILT_REF_RS_SHIFT        3
122 #define CS42L42_HSBIAS_FILT_REF_RS_MASK         (1 << \
123                                         CS42L42_HSBIAS_FILT_REF_RS_SHIFT)
124 #define CS42L42_RING_SENSE_PU_HIZ_SHIFT         6
125 #define CS42L42_RING_SENSE_PU_HIZ_MASK          (1 << \
126                                         CS42L42_RING_SENSE_PU_HIZ_SHIFT)
127 
128 #define CS42L42_RSENSE_CTL2             (CS42L42_PAGE_11 + 0x05)
129 #define CS42L42_TS_RS_GATE_SHIFT        7
130 #define CS42L42_TS_RS_GATE_MAS          (1 << CS42L42_TS_RS_GATE_SHIFT)
131 
132 #define CS42L42_OSC_SWITCH              (CS42L42_PAGE_11 + 0x07)
133 #define CS42L42_SCLK_PRESENT_SHIFT      0
134 #define CS42L42_SCLK_PRESENT_MASK       (1 << CS42L42_SCLK_PRESENT_SHIFT)
135 
136 #define CS42L42_OSC_SWITCH_STATUS       (CS42L42_PAGE_11 + 0x09)
137 #define CS42L42_OSC_SW_SEL_STAT_SHIFT   0
138 #define CS42L42_OSC_SW_SEL_STAT_MASK    (3 << CS42L42_OSC_SW_SEL_STAT_SHIFT)
139 #define CS42L42_OSC_PDNB_STAT_SHIFT     2
140 #define CS42L42_OSC_PDNB_STAT_MASK      (1 << CS42L42_OSC_SW_SEL_STAT_SHIFT)
141 
142 #define CS42L42_RSENSE_CTL3                     (CS42L42_PAGE_11 + 0x12)
143 #define CS42L42_RS_RISE_DBNCE_TIME_SHIFT        0
144 #define CS42L42_RS_RISE_DBNCE_TIME_MASK         (7 << \
145                                         CS42L42_RS_RISE_DBNCE_TIME_SHIFT)
146 #define CS42L42_RS_FALL_DBNCE_TIME_SHIFT        3
147 #define CS42L42_RS_FALL_DBNCE_TIME_MASK         (7 << \
148                                         CS42L42_RS_FALL_DBNCE_TIME_SHIFT)
149 #define CS42L42_RS_PU_EN_SHIFT                  6
150 #define CS42L42_RS_PU_EN_MASK                   (1 << \
151                                         CS42L42_RS_PU_EN_SHIFT)
152 #define CS42L42_RS_INV_SHIFT                    7
153 #define CS42L42_RS_INV_MASK                     (1 << \
154                                         CS42L42_RS_INV_SHIFT)
155 
156 #define CS42L42_TSENSE_CTL                      (CS42L42_PAGE_11 + 0x13)
157 #define CS42L42_TS_RISE_DBNCE_TIME_SHIFT        0
158 #define CS42L42_TS_RISE_DBNCE_TIME_MASK         (7 << \
159                                         CS42L42_TS_RISE_DBNCE_TIME_SHIFT)
160 #define CS42L42_TS_FALL_DBNCE_TIME_SHIFT        3
161 #define CS42L42_TS_FALL_DBNCE_TIME_MASK         (7 << \
162                                         CS42L42_TS_FALL_DBNCE_TIME_SHIFT)
163 #define CS42L42_TS_INV_SHIFT                    7
164 #define CS42L42_TS_INV_MASK                     (1 << \
165                                         CS42L42_TS_INV_SHIFT)
166 
167 #define CS42L42_TSRS_INT_DISABLE        (CS42L42_PAGE_11 + 0x14)
168 #define CS42L42_D_RS_PLUG_DBNC_SHIFT    0
169 #define CS42L42_D_RS_PLUG_DBNC_MASK     (1 << CS42L42_D_RS_PLUG_DBNC_SHIFT)
170 #define CS42L42_D_RS_UNPLUG_DBNC_SHIFT  1
171 #define CS42L42_D_RS_UNPLUG_DBNC_MASK   (1 << CS42L42_D_RS_UNPLUG_DBNC_SHIFT)
172 #define CS42L42_D_TS_PLUG_DBNC_SHIFT    2
173 #define CS42L42_D_TS_PLUG_DBNC_MASK     (1 << CS42L42_D_TS_PLUG_DBNC_SHIFT)
174 #define CS42L42_D_TS_UNPLUG_DBNC_SHIFT  3
175 #define CS42L42_D_TS_UNPLUG_DBNC_MASK   (1 << CS42L42_D_TS_UNPLUG_DBNC_SHIFT)
176 
177 #define CS42L42_TRSENSE_STATUS          (CS42L42_PAGE_11 + 0x15)
178 #define CS42L42_RS_PLUG_DBNC_SHIFT      0
179 #define CS42L42_RS_PLUG_DBNC_MASK       (1 << CS42L42_RS_PLUG_DBNC_SHIFT)
180 #define CS42L42_RS_UNPLUG_DBNC_SHIFT    1
181 #define CS42L42_RS_UNPLUG_DBNC_MASK     (1 << CS42L42_RS_UNPLUG_DBNC_SHIFT)
182 #define CS42L42_TS_PLUG_DBNC_SHIFT      2
183 #define CS42L42_TS_PLUG_DBNC_MASK       (1 << CS42L42_TS_PLUG_DBNC_SHIFT)
184 #define CS42L42_TS_UNPLUG_DBNC_SHIFT    3
185 #define CS42L42_TS_UNPLUG_DBNC_MASK     (1 << CS42L42_TS_UNPLUG_DBNC_SHIFT)
186 
187 #define CS42L42_HSDET_CTL1              (CS42L42_PAGE_11 + 0x1F)
188 #define CS42L42_HSDET_COMP1_LVL_SHIFT   0
189 #define CS42L42_HSDET_COMP1_LVL_MASK    (15 << CS42L42_HSDET_COMP1_LVL_SHIFT)
190 #define CS42L42_HSDET_COMP2_LVL_SHIFT   4
191 #define CS42L42_HSDET_COMP2_LVL_MASK    (15 << CS42L42_HSDET_COMP2_LVL_SHIFT)
192 
193 #define CS42L42_HSDET_CTL2              (CS42L42_PAGE_11 + 0x20)
194 #define CS42L42_HSDET_AUTO_TIME_SHIFT   0
195 #define CS42L42_HSDET_AUTO_TIME_MASK    (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)
196 #define CS42L42_HSBIAS_REF_SHIFT        3
197 #define CS42L42_HSBIAS_REF_MASK         (1 << CS42L42_HSBIAS_REF_SHIFT)
198 #define CS42L42_HSDET_SET_SHIFT         4
199 #define CS42L42_HSDET_SET_MASK          (3 << CS42L42_HSDET_SET_SHIFT)
200 #define CS42L42_HSDET_CTRL_SHIFT        6
201 #define CS42L42_HSDET_CTRL_MASK         (3 << CS42L42_HSDET_CTRL_SHIFT)
202 
203 #define CS42L42_HS_SWITCH_CTL           (CS42L42_PAGE_11 + 0x21)
204 #define CS42L42_SW_GNDHS_HS4_SHIFT      0
205 #define CS42L42_SW_GNDHS_HS4_MASK       (1 << CS42L42_SW_GNDHS_HS4_SHIFT)
206 #define CS42L42_SW_GNDHS_HS3_SHIFT      1
207 #define CS42L42_SW_GNDHS_HS3_MASK       (1 << CS42L42_SW_GNDHS_HS3_SHIFT)
208 #define CS42L42_SW_HSB_HS4_SHIFT        2
209 #define CS42L42_SW_HSB_HS4_MASK         (1 << CS42L42_SW_HSB_HS4_SHIFT)
210 #define CS42L42_SW_HSB_HS3_SHIFT        3
211 #define CS42L42_SW_HSB_HS3_MASK         (1 << CS42L42_SW_HSB_HS3_SHIFT)
212 #define CS42L42_SW_HSB_FILT_HS4_SHIFT   4
213 #define CS42L42_SW_HSB_FILT_HS4_MASK    (1 << CS42L42_SW_HSB_FILT_HS4_SHIFT)
214 #define CS42L42_SW_HSB_FILT_HS3_SHIFT   5
215 #define CS42L42_SW_HSB_FILT_HS3_MASK    (1 << CS42L42_SW_HSB_FILT_HS3_SHIFT)
216 #define CS42L42_SW_REF_HS4_SHIFT        6
217 #define CS42L42_SW_REF_HS4_MASK         (1 << CS42L42_SW_REF_HS4_SHIFT)
218 #define CS42L42_SW_REF_HS3_SHIFT        7
219 #define CS42L42_SW_REF_HS3_MASK         (1 << CS42L42_SW_REF_HS3_SHIFT)
220 
221 #define CS42L42_HS_DET_STATUS           (CS42L42_PAGE_11 + 0x24)
222 #define CS42L42_HSDET_TYPE_SHIFT        0
223 #define CS42L42_HSDET_TYPE_MASK         (3 << CS42L42_HSDET_TYPE_SHIFT)
224 #define CS42L42_HSDET_COMP1_OUT_SHIFT   6
225 #define CS42L42_HSDET_COMP1_OUT_MASK    (1 << CS42L42_HSDET_COMP1_OUT_SHIFT)
226 #define CS42L42_HSDET_COMP2_OUT_SHIFT   7
227 #define CS42L42_HSDET_COMP2_OUT_MASK    (1 << CS42L42_HSDET_COMP2_OUT_SHIFT)
228 #define CS42L42_PLUG_CTIA               0
229 #define CS42L42_PLUG_OMTP               1
230 #define CS42L42_PLUG_HEADPHONE          2
231 #define CS42L42_PLUG_INVALID            3
232 
233 #define CS42L42_HS_CLAMP_DISABLE        (CS42L42_PAGE_11 + 0x29)
234 #define CS42L42_HS_CLAMP_DISABLE_SHIFT  0
235 #define CS42L42_HS_CLAMP_DISABLE_MASK   (1 << CS42L42_HS_CLAMP_DISABLE_SHIFT)
236 
237 /* Page 0x12 Clocking Registers */
238 #define CS42L42_MCLK_SRC_SEL            (CS42L42_PAGE_12 + 0x01)
239 #define CS42L42_MCLKDIV_SHIFT           1
240 #define CS42L42_MCLKDIV_MASK            (1 << CS42L42_MCLKDIV_SHIFT)
241 #define CS42L42_MCLK_SRC_SEL_SHIFT      0
242 #define CS42L42_MCLK_SRC_SEL_MASK       (1 << CS42L42_MCLK_SRC_SEL_SHIFT)
243 
244 #define CS42L42_SPDIF_CLK_CFG           (CS42L42_PAGE_12 + 0x02)
245 #define CS42L42_FSYNC_PW_LOWER          (CS42L42_PAGE_12 + 0x03)
246 
247 #define CS42L42_FSYNC_PW_UPPER                  (CS42L42_PAGE_12 + 0x04)
248 #define CS42L42_FSYNC_PULSE_WIDTH_SHIFT         0
249 #define CS42L42_FSYNC_PULSE_WIDTH_MASK          (0xff << \
250                                         CS42L42_FSYNC_PULSE_WIDTH_SHIFT)
251 
252 #define CS42L42_FSYNC_P_LOWER           (CS42L42_PAGE_12 + 0x05)
253 
254 #define CS42L42_FSYNC_P_UPPER           (CS42L42_PAGE_12 + 0x06)
255 #define CS42L42_FSYNC_PERIOD_SHIFT      0
256 #define CS42L42_FSYNC_PERIOD_MASK       (0xff << CS42L42_FSYNC_PERIOD_SHIFT)
257 
258 #define CS42L42_ASP_CLK_CFG             (CS42L42_PAGE_12 + 0x07)
259 #define CS42L42_ASP_SCLK_EN_SHIFT       5
260 #define CS42L42_ASP_SCLK_EN_MASK        (1 << CS42L42_ASP_SCLK_EN_SHIFT)
261 #define CS42L42_ASP_MASTER_MODE         0x01
262 #define CS42L42_ASP_SLAVE_MODE          0x00
263 #define CS42L42_ASP_MODE_SHIFT          4
264 #define CS42L42_ASP_MODE_MASK           (1 << CS42L42_ASP_MODE_SHIFT)
265 #define CS42L42_ASP_SCPOL_IN_DAC_SHIFT  2
266 #define CS42L42_ASP_SCPOL_IN_DAC_MASK   (1 << CS42L42_ASP_SCPOL_IN_DAC_SHIFT)
267 #define CS42L42_ASP_LCPOL_IN_SHIFT      0
268 #define CS42L42_ASP_LCPOL_IN_MASK       (1 << CS42L42_ASP_LCPOL_IN_SHIFT)
269 #define CS42L42_ASP_POL_INV             1
270 
271 #define CS42L42_ASP_FRM_CFG             (CS42L42_PAGE_12 + 0x08)
272 #define CS42L42_ASP_STP_SHIFT           4
273 #define CS42L42_ASP_STP_MASK            (1 << CS42L42_ASP_STP_SHIFT)
274 #define CS42L42_ASP_5050_SHIFT          3
275 #define CS42L42_ASP_5050_MASK           (1 << CS42L42_ASP_5050_SHIFT)
276 #define CS42L42_ASP_FSD_SHIFT           0
277 #define CS42L42_ASP_FSD_MASK            (7 << CS42L42_ASP_FSD_SHIFT)
278 #define CS42L42_ASP_FSD_0_5             1
279 #define CS42L42_ASP_FSD_1_0             2
280 #define CS42L42_ASP_FSD_1_5             3
281 #define CS42L42_ASP_FSD_2_0             4
282 
283 #define CS42L42_FS_RATE_EN              (CS42L42_PAGE_12 + 0x09)
284 #define CS42L42_FS_EN_SHIFT             0
285 #define CS42L42_FS_EN_MASK              (0xf << CS42L42_FS_EN_SHIFT)
286 #define CS42L42_FS_EN_IASRC_96K         0x1
287 #define CS42L42_FS_EN_OASRC_96K         0x2
288 
289 #define CS42L42_IN_ASRC_CLK             (CS42L42_PAGE_12 + 0x0A)
290 #define CS42L42_CLK_IASRC_SEL_SHIFT     0
291 #define CS42L42_CLK_IASRC_SEL_MASK      (1 << CS42L42_CLK_IASRC_SEL_SHIFT)
292 #define CS42L42_CLK_IASRC_SEL_12        1
293 
294 #define CS42L42_OUT_ASRC_CLK            (CS42L42_PAGE_12 + 0x0B)
295 #define CS42L42_CLK_OASRC_SEL_SHIFT     0
296 #define CS42L42_CLK_OASRC_SEL_MASK      (1 << CS42L42_CLK_OASRC_SEL_SHIFT)
297 #define CS42L42_CLK_OASRC_SEL_12        1
298 
299 #define CS42L42_PLL_DIV_CFG1            (CS42L42_PAGE_12 + 0x0C)
300 #define CS42L42_SCLK_PREDIV_SHIFT       0
301 #define CS42L42_SCLK_PREDIV_MASK        (3 << CS42L42_SCLK_PREDIV_SHIFT)
302 
303 /* Page 0x13 Interrupt Registers */
304 /* Interrupts */
305 #define CS42L42_ADC_OVFL_STATUS         (CS42L42_PAGE_13 + 0x01)
306 #define CS42L42_MIXER_STATUS            (CS42L42_PAGE_13 + 0x02)
307 #define CS42L42_SRC_STATUS              (CS42L42_PAGE_13 + 0x03)
308 #define CS42L42_ASP_RX_STATUS           (CS42L42_PAGE_13 + 0x04)
309 #define CS42L42_ASP_TX_STATUS           (CS42L42_PAGE_13 + 0x05)
310 #define CS42L42_CODEC_STATUS            (CS42L42_PAGE_13 + 0x08)
311 #define CS42L42_DET_INT_STATUS1         (CS42L42_PAGE_13 + 0x09)
312 #define CS42L42_DET_INT_STATUS2         (CS42L42_PAGE_13 + 0x0A)
313 #define CS42L42_SRCPL_INT_STATUS        (CS42L42_PAGE_13 + 0x0B)
314 #define CS42L42_VPMON_STATUS            (CS42L42_PAGE_13 + 0x0D)
315 #define CS42L42_PLL_LOCK_STATUS         (CS42L42_PAGE_13 + 0x0E)
316 #define CS42L42_TSRS_PLUG_STATUS        (CS42L42_PAGE_13 + 0x0F)
317 /* Masks */
318 #define CS42L42_ADC_OVFL_INT_MASK       (CS42L42_PAGE_13 + 0x16)
319 #define CS42L42_ADC_OVFL_SHIFT          0
320 #define CS42L42_ADC_OVFL_MASK           (1 << CS42L42_ADC_OVFL_SHIFT)
321 #define CS42L42_ADC_OVFL_VAL_MASK       CS42L42_ADC_OVFL_MASK
322 
323 #define CS42L42_MIXER_INT_MASK          (CS42L42_PAGE_13 + 0x17)
324 #define CS42L42_MIX_CHB_OVFL_SHIFT      0
325 #define CS42L42_MIX_CHB_OVFL_MASK       (1 << CS42L42_MIX_CHB_OVFL_SHIFT)
326 #define CS42L42_MIX_CHA_OVFL_SHIFT      1
327 #define CS42L42_MIX_CHA_OVFL_MASK       (1 << CS42L42_MIX_CHA_OVFL_SHIFT)
328 #define CS42L42_EQ_OVFL_SHIFT           2
329 #define CS42L42_EQ_OVFL_MASK            (1 << CS42L42_EQ_OVFL_SHIFT)
330 #define CS42L42_EQ_BIQUAD_OVFL_SHIFT    3
331 #define CS42L42_EQ_BIQUAD_OVFL_MASK     (1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT)
332 #define CS42L42_MIXER_VAL_MASK          (CS42L42_MIX_CHB_OVFL_MASK | \
333                                         CS42L42_MIX_CHA_OVFL_MASK | \
334                                         CS42L42_EQ_OVFL_MASK | \
335                                         CS42L42_EQ_BIQUAD_OVFL_MASK)
336 
337 #define CS42L42_SRC_INT_MASK            (CS42L42_PAGE_13 + 0x18)
338 #define CS42L42_SRC_ILK_SHIFT           0
339 #define CS42L42_SRC_ILK_MASK            (1 << CS42L42_SRC_ILK_SHIFT)
340 #define CS42L42_SRC_OLK_SHIFT           1
341 #define CS42L42_SRC_OLK_MASK            (1 << CS42L42_SRC_OLK_SHIFT)
342 #define CS42L42_SRC_IUNLK_SHIFT         2
343 #define CS42L42_SRC_IUNLK_MASK          (1 << CS42L42_SRC_IUNLK_SHIFT)
344 #define CS42L42_SRC_OUNLK_SHIFT         3
345 #define CS42L42_SRC_OUNLK_MASK          (1 << CS42L42_SRC_OUNLK_SHIFT)
346 #define CS42L42_SRC_VAL_MASK            (CS42L42_SRC_ILK_MASK | \
347                                         CS42L42_SRC_OLK_MASK | \
348                                         CS42L42_SRC_IUNLK_MASK | \
349                                         CS42L42_SRC_OUNLK_MASK)
350 
351 #define CS42L42_ASP_RX_INT_MASK         (CS42L42_PAGE_13 + 0x19)
352 #define CS42L42_ASPRX_NOLRCK_SHIFT      0
353 #define CS42L42_ASPRX_NOLRCK_MASK       (1 << CS42L42_ASPRX_NOLRCK_SHIFT)
354 #define CS42L42_ASPRX_EARLY_SHIFT       1
355 #define CS42L42_ASPRX_EARLY_MASK        (1 << CS42L42_ASPRX_EARLY_SHIFT)
356 #define CS42L42_ASPRX_LATE_SHIFT        2
357 #define CS42L42_ASPRX_LATE_MASK         (1 << CS42L42_ASPRX_LATE_SHIFT)
358 #define CS42L42_ASPRX_ERROR_SHIFT       3
359 #define CS42L42_ASPRX_ERROR_MASK        (1 << CS42L42_ASPRX_ERROR_SHIFT)
360 #define CS42L42_ASPRX_OVLD_SHIFT        4
361 #define CS42L42_ASPRX_OVLD_MASK         (1 << CS42L42_ASPRX_OVLD_SHIFT)
362 #define CS42L42_ASP_RX_VAL_MASK         (CS42L42_ASPRX_NOLRCK_MASK | \
363                                         CS42L42_ASPRX_EARLY_MASK | \
364                                         CS42L42_ASPRX_LATE_MASK | \
365                                         CS42L42_ASPRX_ERROR_MASK | \
366                                         CS42L42_ASPRX_OVLD_MASK)
367 
368 #define CS42L42_ASP_TX_INT_MASK         (CS42L42_PAGE_13 + 0x1A)
369 #define CS42L42_ASPTX_NOLRCK_SHIFT      0
370 #define CS42L42_ASPTX_NOLRCK_MASK       (1 << CS42L42_ASPTX_NOLRCK_SHIFT)
371 #define CS42L42_ASPTX_EARLY_SHIFT       1
372 #define CS42L42_ASPTX_EARLY_MASK        (1 << CS42L42_ASPTX_EARLY_SHIFT)
373 #define CS42L42_ASPTX_LATE_SHIFT        2
374 #define CS42L42_ASPTX_LATE_MASK         (1 << CS42L42_ASPTX_LATE_SHIFT)
375 #define CS42L42_ASPTX_SMERROR_SHIFT     3
376 #define CS42L42_ASPTX_SMERROR_MASK      (1 << CS42L42_ASPTX_SMERROR_SHIFT)
377 #define CS42L42_ASP_TX_VAL_MASK         (CS42L42_ASPTX_NOLRCK_MASK | \
378                                         CS42L42_ASPTX_EARLY_MASK | \
379                                         CS42L42_ASPTX_LATE_MASK | \
380                                         CS42L42_ASPTX_SMERROR_MASK)
381 
382 #define CS42L42_CODEC_INT_MASK          (CS42L42_PAGE_13 + 0x1B)
383 #define CS42L42_PDN_DONE_SHIFT          0
384 #define CS42L42_PDN_DONE_MASK           (1 << CS42L42_PDN_DONE_SHIFT)
385 #define CS42L42_HSDET_AUTO_DONE_SHIFT   1
386 #define CS42L42_HSDET_AUTO_DONE_MASK    (1 << CS42L42_HSDET_AUTO_DONE_SHIFT)
387 #define CS42L42_CODEC_VAL_MASK          (CS42L42_PDN_DONE_MASK | \
388                                         CS42L42_HSDET_AUTO_DONE_MASK)
389 
390 #define CS42L42_SRCPL_INT_MASK          (CS42L42_PAGE_13 + 0x1C)
391 #define CS42L42_SRCPL_ADC_LK_SHIFT      0
392 #define CS42L42_SRCPL_ADC_LK_MASK       (1 << CS42L42_SRCPL_ADC_LK_SHIFT)
393 #define CS42L42_SRCPL_DAC_LK_SHIFT      2
394 #define CS42L42_SRCPL_DAC_LK_MASK       (1 << CS42L42_SRCPL_DAC_LK_SHIFT)
395 #define CS42L42_SRCPL_ADC_UNLK_SHIFT    5
396 #define CS42L42_SRCPL_ADC_UNLK_MASK     (1 << CS42L42_SRCPL_ADC_UNLK_SHIFT)
397 #define CS42L42_SRCPL_DAC_UNLK_SHIFT    6
398 #define CS42L42_SRCPL_DAC_UNLK_MASK     (1 << CS42L42_SRCPL_DAC_UNLK_SHIFT)
399 #define CS42L42_SRCPL_VAL_MASK          (CS42L42_SRCPL_ADC_LK_MASK | \
400                                         CS42L42_SRCPL_DAC_LK_MASK | \
401                                         CS42L42_SRCPL_ADC_UNLK_MASK | \
402                                         CS42L42_SRCPL_DAC_UNLK_MASK)
403 
404 #define CS42L42_VPMON_INT_MASK          (CS42L42_PAGE_13 + 0x1E)
405 #define CS42L42_VPMON_SHIFT             0
406 #define CS42L42_VPMON_MASK              (1 << CS42L42_VPMON_SHIFT)
407 #define CS42L42_VPMON_VAL_MASK          CS42L42_VPMON_MASK
408 
409 #define CS42L42_PLL_LOCK_INT_MASK       (CS42L42_PAGE_13 + 0x1F)
410 #define CS42L42_PLL_LOCK_SHIFT          0
411 #define CS42L42_PLL_LOCK_MASK           (1 << CS42L42_PLL_LOCK_SHIFT)
412 #define CS42L42_PLL_LOCK_VAL_MASK       CS42L42_PLL_LOCK_MASK
413 
414 #define CS42L42_TSRS_PLUG_INT_MASK      (CS42L42_PAGE_13 + 0x20)
415 #define CS42L42_RS_PLUG_SHIFT           0
416 #define CS42L42_RS_PLUG_MASK            (1 << CS42L42_RS_PLUG_SHIFT)
417 #define CS42L42_RS_UNPLUG_SHIFT         1
418 #define CS42L42_RS_UNPLUG_MASK          (1 << CS42L42_RS_UNPLUG_SHIFT)
419 #define CS42L42_TS_PLUG_SHIFT           2
420 #define CS42L42_TS_PLUG_MASK            (1 << CS42L42_TS_PLUG_SHIFT)
421 #define CS42L42_TS_UNPLUG_SHIFT         3
422 #define CS42L42_TS_UNPLUG_MASK          (1 << CS42L42_TS_UNPLUG_SHIFT)
423 #define CS42L42_TSRS_PLUG_VAL_MASK      (CS42L42_RS_PLUG_MASK | \
424                                         CS42L42_RS_UNPLUG_MASK | \
425                                         CS42L42_TS_PLUG_MASK | \
426                                         CS42L42_TS_UNPLUG_MASK)
427 #define CS42L42_TS_PLUG                 3
428 #define CS42L42_TS_UNPLUG               0
429 #define CS42L42_TS_TRANS                1
430 
431 /* Page 0x15 Fractional-N PLL Registers */
432 #define CS42L42_PLL_CTL1                (CS42L42_PAGE_15 + 0x01)
433 #define CS42L42_PLL_START_SHIFT         0
434 #define CS42L42_PLL_START_MASK          (1 << CS42L42_PLL_START_SHIFT)
435 
436 #define CS42L42_PLL_DIV_FRAC0           (CS42L42_PAGE_15 + 0x02)
437 #define CS42L42_PLL_DIV_FRAC_SHIFT      0
438 #define CS42L42_PLL_DIV_FRAC_MASK       (0xff << CS42L42_PLL_DIV_FRAC_SHIFT)
439 
440 #define CS42L42_PLL_DIV_FRAC1           (CS42L42_PAGE_15 + 0x03)
441 #define CS42L42_PLL_DIV_FRAC2           (CS42L42_PAGE_15 + 0x04)
442 
443 #define CS42L42_PLL_DIV_INT             (CS42L42_PAGE_15 + 0x05)
444 #define CS42L42_PLL_DIV_INT_SHIFT       0
445 #define CS42L42_PLL_DIV_INT_MASK        (0xff << CS42L42_PLL_DIV_INT_SHIFT)
446 
447 #define CS42L42_PLL_CTL3                (CS42L42_PAGE_15 + 0x08)
448 #define CS42L42_PLL_DIVOUT_SHIFT        0
449 #define CS42L42_PLL_DIVOUT_MASK         (0xff << CS42L42_PLL_DIVOUT_SHIFT)
450 
451 #define CS42L42_PLL_CAL_RATIO           (CS42L42_PAGE_15 + 0x0A)
452 #define CS42L42_PLL_CAL_RATIO_SHIFT     0
453 #define CS42L42_PLL_CAL_RATIO_MASK      (0xff << CS42L42_PLL_CAL_RATIO_SHIFT)
454 
455 #define CS42L42_PLL_CTL4                (CS42L42_PAGE_15 + 0x1B)
456 #define CS42L42_PLL_MODE_SHIFT          0
457 #define CS42L42_PLL_MODE_MASK           (3 << CS42L42_PLL_MODE_SHIFT)
458 
459 /* Page 0x19 HP Load Detect Registers */
460 #define CS42L42_LOAD_DET_RCSTAT         (CS42L42_PAGE_19 + 0x25)
461 #define CS42L42_RLA_STAT_SHIFT          0
462 #define CS42L42_RLA_STAT_MASK           (3 << CS42L42_RLA_STAT_SHIFT)
463 #define CS42L42_RLA_STAT_15_OHM         0
464 
465 #define CS42L42_LOAD_DET_DONE           (CS42L42_PAGE_19 + 0x26)
466 #define CS42L42_HPLOAD_DET_DONE_SHIFT   0
467 #define CS42L42_HPLOAD_DET_DONE_MASK    (1 << CS42L42_HPLOAD_DET_DONE_SHIFT)
468 
469 #define CS42L42_LOAD_DET_EN             (CS42L42_PAGE_19 + 0x27)
470 #define CS42L42_HP_LD_EN_SHIFT          0
471 #define CS42L42_HP_LD_EN_MASK           (1 << CS42L42_HP_LD_EN_SHIFT)
472 
473 /* Page 0x1B Headset Interface Registers */
474 #define CS42L42_HSBIAS_SC_AUTOCTL               (CS42L42_PAGE_1B + 0x70)
475 #define CS42L42_HSBIAS_SENSE_TRIP_SHIFT         0
476 #define CS42L42_HSBIAS_SENSE_TRIP_MASK          (7 << \
477                                         CS42L42_HSBIAS_SENSE_TRIP_SHIFT)
478 #define CS42L42_TIP_SENSE_EN_SHIFT              5
479 #define CS42L42_TIP_SENSE_EN_MASK               (1 << \
480                                         CS42L42_TIP_SENSE_EN_SHIFT)
481 #define CS42L42_AUTO_HSBIAS_HIZ_SHIFT           6
482 #define CS42L42_AUTO_HSBIAS_HIZ_MASK            (1 << \
483                                         CS42L42_AUTO_HSBIAS_HIZ_SHIFT)
484 #define CS42L42_HSBIAS_SENSE_EN_SHIFT           7
485 #define CS42L42_HSBIAS_SENSE_EN_MASK            (1 << \
486                                         CS42L42_HSBIAS_SENSE_EN_SHIFT)
487 
488 #define CS42L42_WAKE_CTL                (CS42L42_PAGE_1B + 0x71)
489 #define CS42L42_WAKEB_CLEAR_SHIFT       0
490 #define CS42L42_WAKEB_CLEAR_MASK        (1 << CS42L42_WAKEB_CLEAR_SHIFT)
491 #define CS42L42_WAKEB_MODE_SHIFT        5
492 #define CS42L42_WAKEB_MODE_MASK         (1 << CS42L42_WAKEB_MODE_SHIFT)
493 #define CS42L42_M_HP_WAKE_SHIFT         6
494 #define CS42L42_M_HP_WAKE_MASK          (1 << CS42L42_M_HP_WAKE_SHIFT)
495 #define CS42L42_M_MIC_WAKE_SHIFT        7
496 #define CS42L42_M_MIC_WAKE_MASK         (1 << CS42L42_M_MIC_WAKE_SHIFT)
497 
498 #define CS42L42_ADC_DISABLE_MUTE                (CS42L42_PAGE_1B + 0x72)
499 #define CS42L42_ADC_DISABLE_S0_MUTE_SHIFT       7
500 #define CS42L42_ADC_DISABLE_S0_MUTE_MASK        (1 << \
501                                         CS42L42_ADC_DISABLE_S0_MUTE_SHIFT)
502 
503 #define CS42L42_TIPSENSE_CTL                    (CS42L42_PAGE_1B + 0x73)
504 #define CS42L42_TIP_SENSE_DEBOUNCE_SHIFT        0
505 #define CS42L42_TIP_SENSE_DEBOUNCE_MASK         (3 << \
506                                         CS42L42_TIP_SENSE_DEBOUNCE_SHIFT)
507 #define CS42L42_TIP_SENSE_INV_SHIFT             5
508 #define CS42L42_TIP_SENSE_INV_MASK              (1 << \
509                                         CS42L42_TIP_SENSE_INV_SHIFT)
510 #define CS42L42_TIP_SENSE_CTRL_SHIFT            6
511 #define CS42L42_TIP_SENSE_CTRL_MASK             (3 << \
512                                         CS42L42_TIP_SENSE_CTRL_SHIFT)
513 
514 #define CS42L42_MISC_DET_CTL            (CS42L42_PAGE_1B + 0x74)
515 #define CS42L42_PDN_MIC_LVL_DET_SHIFT   0
516 #define CS42L42_PDN_MIC_LVL_DET_MASK    (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)
517 #define CS42L42_HSBIAS_CTL_SHIFT        1
518 #define CS42L42_HSBIAS_CTL_MASK         (3 << CS42L42_HSBIAS_CTL_SHIFT)
519 #define CS42L42_DETECT_MODE_SHIFT       3
520 #define CS42L42_DETECT_MODE_MASK        (3 << CS42L42_DETECT_MODE_SHIFT)
521 
522 #define CS42L42_MIC_DET_CTL1            (CS42L42_PAGE_1B + 0x75)
523 #define CS42L42_HS_DET_LEVEL_SHIFT      0
524 #define CS42L42_HS_DET_LEVEL_MASK       (0x3F << CS42L42_HS_DET_LEVEL_SHIFT)
525 #define CS42L42_EVENT_STAT_SEL_SHIFT    6
526 #define CS42L42_EVENT_STAT_SEL_MASK     (1 << CS42L42_EVENT_STAT_SEL_SHIFT)
527 #define CS42L42_LATCH_TO_VP_SHIFT       7
528 #define CS42L42_LATCH_TO_VP_MASK        (1 << CS42L42_LATCH_TO_VP_SHIFT)
529 
530 #define CS42L42_MIC_DET_CTL2            (CS42L42_PAGE_1B + 0x76)
531 #define CS42L42_DEBOUNCE_TIME_SHIFT     5
532 #define CS42L42_DEBOUNCE_TIME_MASK      (0x07 << CS42L42_DEBOUNCE_TIME_SHIFT)
533 
534 #define CS42L42_DET_STATUS1             (CS42L42_PAGE_1B + 0x77)
535 #define CS42L42_HSBIAS_HIZ_MODE_SHIFT   6
536 #define CS42L42_HSBIAS_HIZ_MODE_MASK    (1 << CS42L42_HSBIAS_HIZ_MODE_SHIFT)
537 #define CS42L42_TIP_SENSE_SHIFT         7
538 #define CS42L42_TIP_SENSE_MASK          (1 << CS42L42_TIP_SENSE_SHIFT)
539 
540 #define CS42L42_DET_STATUS2             (CS42L42_PAGE_1B + 0x78)
541 #define CS42L42_SHORT_TRUE_SHIFT        0
542 #define CS42L42_SHORT_TRUE_MASK         (1 << CS42L42_SHORT_TRUE_SHIFT)
543 #define CS42L42_HS_TRUE_SHIFT   1
544 #define CS42L42_HS_TRUE_MASK            (1 << CS42L42_HS_TRUE_SHIFT)
545 
546 #define CS42L42_DET_INT1_MASK           (CS42L42_PAGE_1B + 0x79)
547 #define CS42L42_TIP_SENSE_UNPLUG_SHIFT  5
548 #define CS42L42_TIP_SENSE_UNPLUG_MASK   (1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT)
549 #define CS42L42_TIP_SENSE_PLUG_SHIFT    6
550 #define CS42L42_TIP_SENSE_PLUG_MASK     (1 << CS42L42_TIP_SENSE_PLUG_SHIFT)
551 #define CS42L42_HSBIAS_SENSE_SHIFT      7
552 #define CS42L42_HSBIAS_SENSE_MASK       (1 << CS42L42_HSBIAS_SENSE_SHIFT)
553 #define CS42L42_DET_INT_VAL1_MASK       (CS42L42_TIP_SENSE_UNPLUG_MASK | \
554                                         CS42L42_TIP_SENSE_PLUG_MASK | \
555                                         CS42L42_HSBIAS_SENSE_MASK)
556 
557 #define CS42L42_DET_INT2_MASK           (CS42L42_PAGE_1B + 0x7A)
558 #define CS42L42_M_SHORT_DET_SHIFT       0
559 #define CS42L42_M_SHORT_DET_MASK        (1 << \
560                                         CS42L42_M_SHORT_DET_SHIFT)
561 #define CS42L42_M_SHORT_RLS_SHIFT       1
562 #define CS42L42_M_SHORT_RLS_MASK        (1 << \
563                                         CS42L42_M_SHORT_RLS_SHIFT)
564 #define CS42L42_M_HSBIAS_HIZ_SHIFT      2
565 #define CS42L42_M_HSBIAS_HIZ_MASK       (1 << \
566                                         CS42L42_M_HSBIAS_HIZ_SHIFT)
567 #define CS42L42_M_DETECT_FT_SHIFT       6
568 #define CS42L42_M_DETECT_FT_MASK        (1 << \
569                                         CS42L42_M_DETECT_FT_SHIFT)
570 #define CS42L42_M_DETECT_TF_SHIFT       7
571 #define CS42L42_M_DETECT_TF_MASK        (1 << \
572                                         CS42L42_M_DETECT_TF_SHIFT)
573 #define CS42L42_DET_INT_VAL2_MASK       (CS42L42_M_SHORT_DET_MASK | \
574                                         CS42L42_M_SHORT_RLS_MASK | \
575                                         CS42L42_M_HSBIAS_HIZ_MASK | \
576                                         CS42L42_M_DETECT_FT_MASK | \
577                                         CS42L42_M_DETECT_TF_MASK)
578 
579 /* Page 0x1C Headset Bias Registers */
580 #define CS42L42_HS_BIAS_CTL             (CS42L42_PAGE_1C + 0x03)
581 #define CS42L42_HSBIAS_RAMP_SHIFT       0
582 #define CS42L42_HSBIAS_RAMP_MASK        (3 << CS42L42_HSBIAS_RAMP_SHIFT)
583 #define CS42L42_HSBIAS_PD_SHIFT         4
584 #define CS42L42_HSBIAS_PD_MASK          (1 << CS42L42_HSBIAS_PD_SHIFT)
585 #define CS42L42_HSBIAS_CAPLESS_SHIFT    7
586 #define CS42L42_HSBIAS_CAPLESS_MASK     (1 << CS42L42_HSBIAS_CAPLESS_SHIFT)
587 
588 /* Page 0x1D ADC Registers */
589 #define CS42L42_ADC_CTL                 (CS42L42_PAGE_1D + 0x01)
590 #define CS42L42_ADC_NOTCH_DIS_SHIFT             5
591 #define CS42L42_ADC_FORCE_WEAK_VCM_SHIFT        4
592 #define CS42L42_ADC_INV_SHIFT                   2
593 #define CS42L42_ADC_DIG_BOOST_SHIFT             0
594 
595 #define CS42L42_ADC_VOLUME              (CS42L42_PAGE_1D + 0x03)
596 #define CS42L42_ADC_VOL_SHIFT           0
597 
598 #define CS42L42_ADC_WNF_HPF_CTL         (CS42L42_PAGE_1D + 0x04)
599 #define CS42L42_ADC_WNF_CF_SHIFT        4
600 #define CS42L42_ADC_WNF_EN_SHIFT        3
601 #define CS42L42_ADC_HPF_CF_SHIFT        1
602 #define CS42L42_ADC_HPF_EN_SHIFT        0
603 
604 /* Page 0x1F DAC Registers */
605 #define CS42L42_DAC_CTL1                (CS42L42_PAGE_1F + 0x01)
606 #define CS42L42_DACB_INV_SHIFT          1
607 #define CS42L42_DACA_INV_SHIFT          0
608 
609 #define CS42L42_DAC_CTL2                (CS42L42_PAGE_1F + 0x06)
610 #define CS42L42_HPOUT_PULLDOWN_SHIFT    4
611 #define CS42L42_HPOUT_PULLDOWN_MASK     (15 << CS42L42_HPOUT_PULLDOWN_SHIFT)
612 #define CS42L42_HPOUT_LOAD_SHIFT        3
613 #define CS42L42_HPOUT_LOAD_MASK         (1 << CS42L42_HPOUT_LOAD_SHIFT)
614 #define CS42L42_HPOUT_CLAMP_SHIFT       2
615 #define CS42L42_HPOUT_CLAMP_MASK        (1 << CS42L42_HPOUT_CLAMP_SHIFT)
616 #define CS42L42_DAC_HPF_EN_SHIFT        1
617 #define CS42L42_DAC_HPF_EN_MASK         (1 << CS42L42_DAC_HPF_EN_SHIFT)
618 #define CS42L42_DAC_MON_EN_SHIFT        0
619 #define CS42L42_DAC_MON_EN_MASK         (1 << CS42L42_DAC_MON_EN_SHIFT)
620 
621 /* Page 0x20 HP CTL Registers */
622 #define CS42L42_HP_CTL                  (CS42L42_PAGE_20 + 0x01)
623 #define CS42L42_HP_ANA_BMUTE_SHIFT      3
624 #define CS42L42_HP_ANA_BMUTE_MASK       (1 << CS42L42_HP_ANA_BMUTE_SHIFT)
625 #define CS42L42_HP_ANA_AMUTE_SHIFT      2
626 #define CS42L42_HP_ANA_AMUTE_MASK       (1 << CS42L42_HP_ANA_AMUTE_SHIFT)
627 #define CS42L42_HP_FULL_SCALE_VOL_SHIFT 1
628 #define CS42L42_HP_FULL_SCALE_VOL_MASK  (1 << CS42L42_HP_FULL_SCALE_VOL_SHIFT)
629 
630 /* Page 0x21 Class H Registers */
631 #define CS42L42_CLASSH_CTL              (CS42L42_PAGE_21 + 0x01)
632 
633 /* Page 0x23 Mixer Volume Registers */
634 #define CS42L42_MIXER_CHA_VOL           (CS42L42_PAGE_23 + 0x01)
635 #define CS42L42_MIXER_ADC_VOL           (CS42L42_PAGE_23 + 0x02)
636 
637 #define CS42L42_MIXER_CHB_VOL           (CS42L42_PAGE_23 + 0x03)
638 #define CS42L42_MIXER_CH_VOL_SHIFT      0
639 #define CS42L42_MIXER_CH_VOL_MASK       (0x3f << CS42L42_MIXER_CH_VOL_SHIFT)
640 
641 /* Page 0x24 EQ Registers */
642 #define CS42L42_EQ_COEF_IN0             (CS42L42_PAGE_24 + 0x01)
643 #define CS42L42_EQ_COEF_IN1             (CS42L42_PAGE_24 + 0x02)
644 #define CS42L42_EQ_COEF_IN2             (CS42L42_PAGE_24 + 0x03)
645 #define CS42L42_EQ_COEF_IN3             (CS42L42_PAGE_24 + 0x04)
646 #define CS42L42_EQ_COEF_RW              (CS42L42_PAGE_24 + 0x06)
647 #define CS42L42_EQ_COEF_OUT0            (CS42L42_PAGE_24 + 0x07)
648 #define CS42L42_EQ_COEF_OUT1            (CS42L42_PAGE_24 + 0x08)
649 #define CS42L42_EQ_COEF_OUT2            (CS42L42_PAGE_24 + 0x09)
650 #define CS42L42_EQ_COEF_OUT3            (CS42L42_PAGE_24 + 0x0A)
651 #define CS42L42_EQ_INIT_STAT            (CS42L42_PAGE_24 + 0x0B)
652 #define CS42L42_EQ_START_FILT           (CS42L42_PAGE_24 + 0x0C)
653 #define CS42L42_EQ_MUTE_CTL             (CS42L42_PAGE_24 + 0x0E)
654 
655 /* Page 0x25 Audio Port Registers */
656 #define CS42L42_SP_RX_CH_SEL            (CS42L42_PAGE_25 + 0x01)
657 
658 #define CS42L42_SP_RX_ISOC_CTL          (CS42L42_PAGE_25 + 0x02)
659 #define CS42L42_SP_RX_RSYNC_SHIFT       6
660 #define CS42L42_SP_RX_RSYNC_MASK        (1 << CS42L42_SP_RX_RSYNC_SHIFT)
661 #define CS42L42_SP_RX_NSB_POS_SHIFT     3
662 #define CS42L42_SP_RX_NSB_POS_MASK      (7 << CS42L42_SP_RX_NSB_POS_SHIFT)
663 #define CS42L42_SP_RX_NFS_NSBB_SHIFT    2
664 #define CS42L42_SP_RX_NFS_NSBB_MASK     (1 << CS42L42_SP_RX_NFS_NSBB_SHIFT)
665 #define CS42L42_SP_RX_ISOC_MODE_SHIFT   0
666 #define CS42L42_SP_RX_ISOC_MODE_MASK    (3 << CS42L42_SP_RX_ISOC_MODE_SHIFT)
667 
668 #define CS42L42_SP_RX_FS                (CS42L42_PAGE_25 + 0x03)
669 #define CS42l42_SPDIF_CH_SEL            (CS42L42_PAGE_25 + 0x04)
670 #define CS42L42_SP_TX_ISOC_CTL          (CS42L42_PAGE_25 + 0x05)
671 #define CS42L42_SP_TX_FS                (CS42L42_PAGE_25 + 0x06)
672 #define CS42L42_SPDIF_SW_CTL1           (CS42L42_PAGE_25 + 0x07)
673 
674 /* Page 0x26 SRC Registers */
675 #define CS42L42_SRC_SDIN_FS             (CS42L42_PAGE_26 + 0x01)
676 #define CS42L42_SRC_SDIN_FS_SHIFT       0
677 #define CS42L42_SRC_SDIN_FS_MASK        (0x1f << CS42L42_SRC_SDIN_FS_SHIFT)
678 
679 #define CS42L42_SRC_SDOUT_FS            (CS42L42_PAGE_26 + 0x09)
680 
681 /* Page 0x28 S/PDIF Registers */
682 #define CS42L42_SPDIF_CTL1              (CS42L42_PAGE_28 + 0x01)
683 #define CS42L42_SPDIF_CTL2              (CS42L42_PAGE_28 + 0x02)
684 #define CS42L42_SPDIF_CTL3              (CS42L42_PAGE_28 + 0x03)
685 #define CS42L42_SPDIF_CTL4              (CS42L42_PAGE_28 + 0x04)
686 
687 /* Page 0x29 Serial Port TX Registers */
688 #define CS42L42_ASP_TX_SZ_EN            (CS42L42_PAGE_29 + 0x01)
689 #define CS42L42_ASP_TX_CH_EN            (CS42L42_PAGE_29 + 0x02)
690 #define CS42L42_ASP_TX_CH_AP_RES        (CS42L42_PAGE_29 + 0x03)
691 #define CS42L42_ASP_TX_CH1_BIT_MSB      (CS42L42_PAGE_29 + 0x04)
692 #define CS42L42_ASP_TX_CH1_BIT_LSB      (CS42L42_PAGE_29 + 0x05)
693 #define CS42L42_ASP_TX_HIZ_DLY_CFG      (CS42L42_PAGE_29 + 0x06)
694 #define CS42L42_ASP_TX_CH2_BIT_MSB      (CS42L42_PAGE_29 + 0x0A)
695 #define CS42L42_ASP_TX_CH2_BIT_LSB      (CS42L42_PAGE_29 + 0x0B)
696 
697 /* Page 0x2A Serial Port RX Registers */
698 #define CS42L42_ASP_RX_DAI0_EN          (CS42L42_PAGE_2A + 0x01)
699 #define CS42L42_ASP_RX0_CH_EN_SHIFT     2
700 #define CS42L42_ASP_RX0_CH_EN_MASK      (0xf << CS42L42_ASP_RX0_CH_EN_SHIFT)
701 #define CS42L42_ASP_RX0_CH1_EN          1
702 #define CS42L42_ASP_RX0_CH2_EN          2
703 #define CS42L42_ASP_RX0_CH3_EN          4
704 #define CS42L42_ASP_RX0_CH4_EN          8
705 
706 #define CS42L42_ASP_RX_DAI0_CH1_AP_RES  (CS42L42_PAGE_2A + 0x02)
707 #define CS42L42_ASP_RX_DAI0_CH1_BIT_MSB (CS42L42_PAGE_2A + 0x03)
708 #define CS42L42_ASP_RX_DAI0_CH1_BIT_LSB (CS42L42_PAGE_2A + 0x04)
709 #define CS42L42_ASP_RX_DAI0_CH2_AP_RES  (CS42L42_PAGE_2A + 0x05)
710 #define CS42L42_ASP_RX_DAI0_CH2_BIT_MSB (CS42L42_PAGE_2A + 0x06)
711 #define CS42L42_ASP_RX_DAI0_CH2_BIT_LSB (CS42L42_PAGE_2A + 0x07)
712 #define CS42L42_ASP_RX_DAI0_CH3_AP_RES  (CS42L42_PAGE_2A + 0x08)
713 #define CS42L42_ASP_RX_DAI0_CH3_BIT_MSB (CS42L42_PAGE_2A + 0x09)
714 #define CS42L42_ASP_RX_DAI0_CH3_BIT_LSB (CS42L42_PAGE_2A + 0x0A)
715 #define CS42L42_ASP_RX_DAI0_CH4_AP_RES  (CS42L42_PAGE_2A + 0x0B)
716 #define CS42L42_ASP_RX_DAI0_CH4_BIT_MSB (CS42L42_PAGE_2A + 0x0C)
717 #define CS42L42_ASP_RX_DAI0_CH4_BIT_LSB (CS42L42_PAGE_2A + 0x0D)
718 #define CS42L42_ASP_RX_DAI1_CH1_AP_RES  (CS42L42_PAGE_2A + 0x0E)
719 #define CS42L42_ASP_RX_DAI1_CH1_BIT_MSB (CS42L42_PAGE_2A + 0x0F)
720 #define CS42L42_ASP_RX_DAI1_CH1_BIT_LSB (CS42L42_PAGE_2A + 0x10)
721 #define CS42L42_ASP_RX_DAI1_CH2_AP_RES  (CS42L42_PAGE_2A + 0x11)
722 #define CS42L42_ASP_RX_DAI1_CH2_BIT_MSB (CS42L42_PAGE_2A + 0x12)
723 #define CS42L42_ASP_RX_DAI1_CH2_BIT_LSB (CS42L42_PAGE_2A + 0x13)
724 
725 #define CS42L42_ASP_RX_CH_AP_SHIFT      6
726 #define CS42L42_ASP_RX_CH_AP_MASK       (1 << CS42L42_ASP_RX_CH_AP_SHIFT)
727 #define CS42L42_ASP_RX_CH_AP_LOW        0
728 #define CS42L42_ASP_RX_CH_AP_HI         1
729 #define CS42L42_ASP_RX_CH_RES_SHIFT     0
730 #define CS42L42_ASP_RX_CH_RES_MASK      (3 << CS42L42_ASP_RX_CH_RES_SHIFT)
731 #define CS42L42_ASP_RX_CH_RES_32        3
732 #define CS42L42_ASP_RX_CH_RES_16        1
733 #define CS42L42_ASP_RX_CH_BIT_ST_SHIFT  0
734 #define CS42L42_ASP_RX_CH_BIT_ST_MASK   (0xff << CS42L42_ASP_RX_CH_BIT_ST_SHIFT)
735 
736 /* Page 0x30 ID Registers */
737 #define CS42L42_SUB_REVID               (CS42L42_PAGE_30 + 0x14)
738 #define CS42L42_MAX_REGISTER            (CS42L42_PAGE_30 + 0x14)
739 
740 /* Defines for fracturing values spread across multiple registers */
741 #define CS42L42_FRAC0_VAL(val)  ((val) & 0x0000ff)
742 #define CS42L42_FRAC1_VAL(val)  (((val) & 0x00ff00) >> 8)
743 #define CS42L42_FRAC2_VAL(val)  (((val) & 0xff0000) >> 16)
744 
745 #define CS42L42_NUM_SUPPLIES    5
746 
747 static const char *const cs42l42_supply_names[CS42L42_NUM_SUPPLIES] = {
748         "VA",
749         "VP",
750         "VCP",
751         "VD_FILT",
752         "VL",
753 };
754 
755 struct  cs42l42_private {
756         struct regmap *regmap;
757         struct snd_soc_component *component;
758         struct regulator_bulk_data supplies[CS42L42_NUM_SUPPLIES];
759         struct gpio_desc *reset_gpio;
760         struct completion pdn_done;
761         u32 sclk;
762         u32 srate;
763         u32 swidth;
764         u8 plug_state;
765         u8 hs_type;
766         u8 ts_inv;
767         u8 ts_dbnc_rise;
768         u8 ts_dbnc_fall;
769         u8 btn_det_init_dbnce;
770         u8 btn_det_event_dbnce;
771         u8 bias_thresholds[CS42L42_NUM_BIASES];
772         u8 hs_bias_ramp_rate;
773         u8 hs_bias_ramp_time;
774 };
775 
776 #endif /* __CS42L42_H__ */
777 

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