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TOMOYO Linux Cross Reference
Linux/sound/soc/codecs/cs42l52.c

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  1 /*
  2  * cs42l52.c -- CS42L52 ALSA SoC audio driver
  3  *
  4  * Copyright 2012 CirrusLogic, Inc.
  5  *
  6  * Author: Georgi Vlaev <joe@nucleusys.com>
  7  * Author: Brian Austin <brian.austin@cirrus.com>
  8  *
  9  * This program is free software; you can redistribute it and/or modify
 10  * it under the terms of the GNU General Public License version 2 as
 11  * published by the Free Software Foundation.
 12  *
 13  */
 14 
 15 #include <linux/module.h>
 16 #include <linux/moduleparam.h>
 17 #include <linux/kernel.h>
 18 #include <linux/init.h>
 19 #include <linux/delay.h>
 20 #include <linux/pm.h>
 21 #include <linux/i2c.h>
 22 #include <linux/input.h>
 23 #include <linux/regmap.h>
 24 #include <linux/slab.h>
 25 #include <linux/workqueue.h>
 26 #include <linux/platform_device.h>
 27 #include <sound/core.h>
 28 #include <sound/pcm.h>
 29 #include <sound/pcm_params.h>
 30 #include <sound/soc.h>
 31 #include <sound/soc-dapm.h>
 32 #include <sound/initval.h>
 33 #include <sound/tlv.h>
 34 #include <sound/cs42l52.h>
 35 #include "cs42l52.h"
 36 
 37 struct sp_config {
 38         u8 spc, format, spfs;
 39         u32 srate;
 40 };
 41 
 42 struct  cs42l52_private {
 43         struct regmap *regmap;
 44         struct snd_soc_codec *codec;
 45         struct device *dev;
 46         struct sp_config config;
 47         struct cs42l52_platform_data pdata;
 48         u32 sysclk;
 49         u8 mclksel;
 50         u32 mclk;
 51         u8 flags;
 52 #if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
 53         struct input_dev *beep;
 54         struct work_struct beep_work;
 55         int beep_rate;
 56 #endif
 57 };
 58 
 59 static const struct reg_default cs42l52_reg_defaults[] = {
 60         { CS42L52_PWRCTL1, 0x9F },      /* r02 PWRCTL 1 */
 61         { CS42L52_PWRCTL2, 0x07 },      /* r03 PWRCTL 2 */
 62         { CS42L52_PWRCTL3, 0xFF },      /* r04 PWRCTL 3 */
 63         { CS42L52_CLK_CTL, 0xA0 },      /* r05 Clocking Ctl */
 64         { CS42L52_IFACE_CTL1, 0x00 },   /* r06 Interface Ctl 1 */
 65         { CS42L52_ADC_PGA_A, 0x80 },    /* r08 Input A Select */
 66         { CS42L52_ADC_PGA_B, 0x80 },    /* r09 Input B Select */
 67         { CS42L52_ANALOG_HPF_CTL, 0xA5 },       /* r0A Analog HPF Ctl */
 68         { CS42L52_ADC_HPF_FREQ, 0x00 }, /* r0B ADC HPF Corner Freq */
 69         { CS42L52_ADC_MISC_CTL, 0x00 }, /* r0C Misc. ADC Ctl */
 70         { CS42L52_PB_CTL1, 0x60 },      /* r0D Playback Ctl 1 */
 71         { CS42L52_MISC_CTL, 0x02 },     /* r0E Misc. Ctl */
 72         { CS42L52_PB_CTL2, 0x00 },      /* r0F Playback Ctl 2 */
 73         { CS42L52_MICA_CTL, 0x00 },     /* r10 MICA Amp Ctl */
 74         { CS42L52_MICB_CTL, 0x00 },     /* r11 MICB Amp Ctl */
 75         { CS42L52_PGAA_CTL, 0x00 },     /* r12 PGAA Vol, Misc. */
 76         { CS42L52_PGAB_CTL, 0x00 },     /* r13 PGAB Vol, Misc. */
 77         { CS42L52_PASSTHRUA_VOL, 0x00 },        /* r14 Bypass A Vol */
 78         { CS42L52_PASSTHRUB_VOL, 0x00 },        /* r15 Bypass B Vol */
 79         { CS42L52_ADCA_VOL, 0x00 },     /* r16 ADCA Volume */
 80         { CS42L52_ADCB_VOL, 0x00 },     /* r17 ADCB Volume */
 81         { CS42L52_ADCA_MIXER_VOL, 0x80 },       /* r18 ADCA Mixer Volume */
 82         { CS42L52_ADCB_MIXER_VOL, 0x80 },       /* r19 ADCB Mixer Volume */
 83         { CS42L52_PCMA_MIXER_VOL, 0x00 },       /* r1A PCMA Mixer Volume */
 84         { CS42L52_PCMB_MIXER_VOL, 0x00 },       /* r1B PCMB Mixer Volume */
 85         { CS42L52_BEEP_FREQ, 0x00 },    /* r1C Beep Freq on Time */
 86         { CS42L52_BEEP_VOL, 0x00 },     /* r1D Beep Volume off Time */
 87         { CS42L52_BEEP_TONE_CTL, 0x00 },        /* r1E Beep Tone Cfg. */
 88         { CS42L52_TONE_CTL, 0x00 },     /* r1F Tone Ctl */
 89         { CS42L52_MASTERA_VOL, 0x00 },  /* r20 Master A Volume */
 90         { CS42L52_MASTERB_VOL, 0x00 },  /* r21 Master B Volume */
 91         { CS42L52_HPA_VOL, 0x00 },      /* r22 Headphone A Volume */
 92         { CS42L52_HPB_VOL, 0x00 },      /* r23 Headphone B Volume */
 93         { CS42L52_SPKA_VOL, 0x00 },     /* r24 Speaker A Volume */
 94         { CS42L52_SPKB_VOL, 0x00 },     /* r25 Speaker B Volume */
 95         { CS42L52_ADC_PCM_MIXER, 0x00 },        /* r26 Channel Mixer and Swap */
 96         { CS42L52_LIMITER_CTL1, 0x00 }, /* r27 Limit Ctl 1 Thresholds */
 97         { CS42L52_LIMITER_CTL2, 0x7F }, /* r28 Limit Ctl 2 Release Rate */
 98         { CS42L52_LIMITER_AT_RATE, 0xC0 },      /* r29 Limiter Attack Rate */
 99         { CS42L52_ALC_CTL, 0x00 },      /* r2A ALC Ctl 1 Attack Rate */
100         { CS42L52_ALC_RATE, 0x3F },     /* r2B ALC Release Rate */
101         { CS42L52_ALC_THRESHOLD, 0x3f },        /* r2C ALC Thresholds */
102         { CS42L52_NOISE_GATE_CTL, 0x00 },       /* r2D Noise Gate Ctl */
103         { CS42L52_CLK_STATUS, 0x00 },   /* r2E Overflow and Clock Status */
104         { CS42L52_BATT_COMPEN, 0x00 },  /* r2F battery Compensation */
105         { CS42L52_BATT_LEVEL, 0x00 },   /* r30 VP Battery Level */
106         { CS42L52_SPK_STATUS, 0x00 },   /* r31 Speaker Status */
107         { CS42L52_TEM_CTL, 0x3B },      /* r32 Temp Ctl */
108         { CS42L52_THE_FOLDBACK, 0x00 }, /* r33 Foldback */
109 };
110 
111 static bool cs42l52_readable_register(struct device *dev, unsigned int reg)
112 {
113         switch (reg) {
114         case CS42L52_CHIP:
115         case CS42L52_PWRCTL1:
116         case CS42L52_PWRCTL2:
117         case CS42L52_PWRCTL3:
118         case CS42L52_CLK_CTL:
119         case CS42L52_IFACE_CTL1:
120         case CS42L52_IFACE_CTL2:
121         case CS42L52_ADC_PGA_A:
122         case CS42L52_ADC_PGA_B:
123         case CS42L52_ANALOG_HPF_CTL:
124         case CS42L52_ADC_HPF_FREQ:
125         case CS42L52_ADC_MISC_CTL:
126         case CS42L52_PB_CTL1:
127         case CS42L52_MISC_CTL:
128         case CS42L52_PB_CTL2:
129         case CS42L52_MICA_CTL:
130         case CS42L52_MICB_CTL:
131         case CS42L52_PGAA_CTL:
132         case CS42L52_PGAB_CTL:
133         case CS42L52_PASSTHRUA_VOL:
134         case CS42L52_PASSTHRUB_VOL:
135         case CS42L52_ADCA_VOL:
136         case CS42L52_ADCB_VOL:
137         case CS42L52_ADCA_MIXER_VOL:
138         case CS42L52_ADCB_MIXER_VOL:
139         case CS42L52_PCMA_MIXER_VOL:
140         case CS42L52_PCMB_MIXER_VOL:
141         case CS42L52_BEEP_FREQ:
142         case CS42L52_BEEP_VOL:
143         case CS42L52_BEEP_TONE_CTL:
144         case CS42L52_TONE_CTL:
145         case CS42L52_MASTERA_VOL:
146         case CS42L52_MASTERB_VOL:
147         case CS42L52_HPA_VOL:
148         case CS42L52_HPB_VOL:
149         case CS42L52_SPKA_VOL:
150         case CS42L52_SPKB_VOL:
151         case CS42L52_ADC_PCM_MIXER:
152         case CS42L52_LIMITER_CTL1:
153         case CS42L52_LIMITER_CTL2:
154         case CS42L52_LIMITER_AT_RATE:
155         case CS42L52_ALC_CTL:
156         case CS42L52_ALC_RATE:
157         case CS42L52_ALC_THRESHOLD:
158         case CS42L52_NOISE_GATE_CTL:
159         case CS42L52_CLK_STATUS:
160         case CS42L52_BATT_COMPEN:
161         case CS42L52_BATT_LEVEL:
162         case CS42L52_SPK_STATUS:
163         case CS42L52_TEM_CTL:
164         case CS42L52_THE_FOLDBACK:
165         case CS42L52_CHARGE_PUMP:
166                 return true;
167         default:
168                 return false;
169         }
170 }
171 
172 static bool cs42l52_volatile_register(struct device *dev, unsigned int reg)
173 {
174         switch (reg) {
175         case CS42L52_IFACE_CTL2:
176         case CS42L52_CLK_STATUS:
177         case CS42L52_BATT_LEVEL:
178         case CS42L52_SPK_STATUS:
179         case CS42L52_CHARGE_PUMP:
180                 return 1;
181         default:
182                 return 0;
183         }
184 }
185 
186 static DECLARE_TLV_DB_SCALE(hl_tlv, -10200, 50, 0);
187 
188 static DECLARE_TLV_DB_SCALE(hpd_tlv, -9600, 50, 1);
189 
190 static DECLARE_TLV_DB_SCALE(ipd_tlv, -9600, 100, 0);
191 
192 static DECLARE_TLV_DB_SCALE(mic_tlv, 1600, 100, 0);
193 
194 static DECLARE_TLV_DB_SCALE(pga_tlv, -600, 50, 0);
195 
196 static DECLARE_TLV_DB_SCALE(mix_tlv, -50, 50, 0);
197 
198 static DECLARE_TLV_DB_SCALE(beep_tlv, -56, 200, 0);
199 
200 static const unsigned int limiter_tlv[] = {
201         TLV_DB_RANGE_HEAD(2),
202         0, 2, TLV_DB_SCALE_ITEM(-3000, 600, 0),
203         3, 7, TLV_DB_SCALE_ITEM(-1200, 300, 0),
204 };
205 
206 static const char * const cs42l52_adca_text[] = {
207         "Input1A", "Input2A", "Input3A", "Input4A", "PGA Input Left"};
208 
209 static const char * const cs42l52_adcb_text[] = {
210         "Input1B", "Input2B", "Input3B", "Input4B", "PGA Input Right"};
211 
212 static const struct soc_enum adca_enum =
213         SOC_ENUM_SINGLE(CS42L52_ADC_PGA_A, 5,
214                 ARRAY_SIZE(cs42l52_adca_text), cs42l52_adca_text);
215 
216 static const struct soc_enum adcb_enum =
217         SOC_ENUM_SINGLE(CS42L52_ADC_PGA_B, 5,
218                 ARRAY_SIZE(cs42l52_adcb_text), cs42l52_adcb_text);
219 
220 static const struct snd_kcontrol_new adca_mux =
221         SOC_DAPM_ENUM("Left ADC Input Capture Mux", adca_enum);
222 
223 static const struct snd_kcontrol_new adcb_mux =
224         SOC_DAPM_ENUM("Right ADC Input Capture Mux", adcb_enum);
225 
226 static const char * const mic_bias_level_text[] = {
227         "0.5 +VA", "0.6 +VA", "0.7 +VA",
228         "0.8 +VA", "0.83 +VA", "0.91 +VA"
229 };
230 
231 static const struct soc_enum mic_bias_level_enum =
232         SOC_ENUM_SINGLE(CS42L52_IFACE_CTL2, 0,
233                         ARRAY_SIZE(mic_bias_level_text), mic_bias_level_text);
234 
235 static const char * const cs42l52_mic_text[] = { "Single", "Differential" };
236 
237 static const struct soc_enum mica_enum =
238         SOC_ENUM_SINGLE(CS42L52_MICA_CTL, 5,
239                         ARRAY_SIZE(cs42l52_mic_text), cs42l52_mic_text);
240 
241 static const struct soc_enum micb_enum =
242         SOC_ENUM_SINGLE(CS42L52_MICB_CTL, 5,
243                         ARRAY_SIZE(cs42l52_mic_text), cs42l52_mic_text);
244 
245 static const struct snd_kcontrol_new mica_mux =
246         SOC_DAPM_ENUM("Left Mic Input Capture Mux", mica_enum);
247 
248 static const struct snd_kcontrol_new micb_mux =
249         SOC_DAPM_ENUM("Right Mic Input Capture Mux", micb_enum);
250 
251 static const char * const digital_output_mux_text[] = {"ADC", "DSP"};
252 
253 static const struct soc_enum digital_output_mux_enum =
254         SOC_ENUM_SINGLE(CS42L52_ADC_MISC_CTL, 6,
255                         ARRAY_SIZE(digital_output_mux_text),
256                         digital_output_mux_text);
257 
258 static const struct snd_kcontrol_new digital_output_mux =
259         SOC_DAPM_ENUM("Digital Output Mux", digital_output_mux_enum);
260 
261 static const char * const hp_gain_num_text[] = {
262         "0.3959", "0.4571", "0.5111", "0.6047",
263         "0.7099", "0.8399", "1.000", "1.1430"
264 };
265 
266 static const struct soc_enum hp_gain_enum =
267         SOC_ENUM_SINGLE(CS42L52_PB_CTL1, 5,
268                 ARRAY_SIZE(hp_gain_num_text), hp_gain_num_text);
269 
270 static const char * const beep_pitch_text[] = {
271         "C4", "C5", "D5", "E5", "F5", "G5", "A5", "B5",
272         "C6", "D6", "E6", "F6", "G6", "A6", "B6", "C7"
273 };
274 
275 static const struct soc_enum beep_pitch_enum =
276         SOC_ENUM_SINGLE(CS42L52_BEEP_FREQ, 4,
277                         ARRAY_SIZE(beep_pitch_text), beep_pitch_text);
278 
279 static const char * const beep_ontime_text[] = {
280         "86 ms", "430 ms", "780 ms", "1.20 s", "1.50 s",
281         "1.80 s", "2.20 s", "2.50 s", "2.80 s", "3.20 s",
282         "3.50 s", "3.80 s", "4.20 s", "4.50 s", "4.80 s", "5.20 s"
283 };
284 
285 static const struct soc_enum beep_ontime_enum =
286         SOC_ENUM_SINGLE(CS42L52_BEEP_FREQ, 0,
287                         ARRAY_SIZE(beep_ontime_text), beep_ontime_text);
288 
289 static const char * const beep_offtime_text[] = {
290         "1.23 s", "2.58 s", "3.90 s", "5.20 s",
291         "6.60 s", "8.05 s", "9.35 s", "10.80 s"
292 };
293 
294 static const struct soc_enum beep_offtime_enum =
295         SOC_ENUM_SINGLE(CS42L52_BEEP_VOL, 5,
296                         ARRAY_SIZE(beep_offtime_text), beep_offtime_text);
297 
298 static const char * const beep_config_text[] = {
299         "Off", "Single", "Multiple", "Continuous"
300 };
301 
302 static const struct soc_enum beep_config_enum =
303         SOC_ENUM_SINGLE(CS42L52_BEEP_TONE_CTL, 6,
304                         ARRAY_SIZE(beep_config_text), beep_config_text);
305 
306 static const char * const beep_bass_text[] = {
307         "50 Hz", "100 Hz", "200 Hz", "250 Hz"
308 };
309 
310 static const struct soc_enum beep_bass_enum =
311         SOC_ENUM_SINGLE(CS42L52_BEEP_TONE_CTL, 1,
312                         ARRAY_SIZE(beep_bass_text), beep_bass_text);
313 
314 static const char * const beep_treble_text[] = {
315         "5 kHz", "7 kHz", "10 kHz", " 15 kHz"
316 };
317 
318 static const struct soc_enum beep_treble_enum =
319         SOC_ENUM_SINGLE(CS42L52_BEEP_TONE_CTL, 3,
320                         ARRAY_SIZE(beep_treble_text), beep_treble_text);
321 
322 static const char * const ng_threshold_text[] = {
323         "-34dB", "-37dB", "-40dB", "-43dB",
324         "-46dB", "-52dB", "-58dB", "-64dB"
325 };
326 
327 static const struct soc_enum ng_threshold_enum =
328         SOC_ENUM_SINGLE(CS42L52_NOISE_GATE_CTL, 2,
329                 ARRAY_SIZE(ng_threshold_text), ng_threshold_text);
330 
331 static const char * const cs42l52_ng_delay_text[] = {
332         "50ms", "100ms", "150ms", "200ms"};
333 
334 static const struct soc_enum ng_delay_enum =
335         SOC_ENUM_SINGLE(CS42L52_NOISE_GATE_CTL, 0,
336                 ARRAY_SIZE(cs42l52_ng_delay_text), cs42l52_ng_delay_text);
337 
338 static const char * const cs42l52_ng_type_text[] = {
339         "Apply Specific", "Apply All"
340 };
341 
342 static const struct soc_enum ng_type_enum =
343         SOC_ENUM_SINGLE(CS42L52_NOISE_GATE_CTL, 6,
344                 ARRAY_SIZE(cs42l52_ng_type_text), cs42l52_ng_type_text);
345 
346 static const char * const left_swap_text[] = {
347         "Left", "LR 2", "Right"};
348 
349 static const char * const right_swap_text[] = {
350         "Right", "LR 2", "Left"};
351 
352 static const unsigned int swap_values[] = { 0, 1, 3 };
353 
354 static const struct soc_enum adca_swap_enum =
355         SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 2, 3,
356                               ARRAY_SIZE(left_swap_text),
357                               left_swap_text,
358                               swap_values);
359 
360 static const struct snd_kcontrol_new adca_mixer =
361         SOC_DAPM_ENUM("Route", adca_swap_enum);
362 
363 static const struct soc_enum pcma_swap_enum =
364         SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 6, 3,
365                               ARRAY_SIZE(left_swap_text),
366                               left_swap_text,
367                               swap_values);
368 
369 static const struct snd_kcontrol_new pcma_mixer =
370         SOC_DAPM_ENUM("Route", pcma_swap_enum);
371 
372 static const struct soc_enum adcb_swap_enum =
373         SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 0, 3,
374                               ARRAY_SIZE(right_swap_text),
375                               right_swap_text,
376                               swap_values);
377 
378 static const struct snd_kcontrol_new adcb_mixer =
379         SOC_DAPM_ENUM("Route", adcb_swap_enum);
380 
381 static const struct soc_enum pcmb_swap_enum =
382         SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 4, 3,
383                               ARRAY_SIZE(right_swap_text),
384                               right_swap_text,
385                               swap_values);
386 
387 static const struct snd_kcontrol_new pcmb_mixer =
388         SOC_DAPM_ENUM("Route", pcmb_swap_enum);
389 
390 
391 static const struct snd_kcontrol_new passthrul_ctl =
392         SOC_DAPM_SINGLE("Switch", CS42L52_MISC_CTL, 6, 1, 0);
393 
394 static const struct snd_kcontrol_new passthrur_ctl =
395         SOC_DAPM_SINGLE("Switch", CS42L52_MISC_CTL, 7, 1, 0);
396 
397 static const struct snd_kcontrol_new spkl_ctl =
398         SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 0, 1, 1);
399 
400 static const struct snd_kcontrol_new spkr_ctl =
401         SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 2, 1, 1);
402 
403 static const struct snd_kcontrol_new hpl_ctl =
404         SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 4, 1, 1);
405 
406 static const struct snd_kcontrol_new hpr_ctl =
407         SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 6, 1, 1);
408 
409 static const struct snd_kcontrol_new cs42l52_snd_controls[] = {
410 
411         SOC_DOUBLE_R_SX_TLV("Master Volume", CS42L52_MASTERA_VOL,
412                               CS42L52_MASTERB_VOL, 0, 0x34, 0xE4, hl_tlv),
413 
414         SOC_DOUBLE_R_SX_TLV("Headphone Volume", CS42L52_HPA_VOL,
415                               CS42L52_HPB_VOL, 0, 0x34, 0xCC, hpd_tlv),
416 
417         SOC_ENUM("Headphone Analog Gain", hp_gain_enum),
418 
419         SOC_DOUBLE_R_SX_TLV("Speaker Volume", CS42L52_SPKA_VOL,
420                               CS42L52_SPKB_VOL, 0, 0x1, 0xff, hl_tlv),
421 
422         SOC_DOUBLE_R_SX_TLV("Bypass Volume", CS42L52_PASSTHRUA_VOL,
423                               CS42L52_PASSTHRUB_VOL, 6, 0x18, 0x90, pga_tlv),
424 
425         SOC_DOUBLE("Bypass Mute", CS42L52_MISC_CTL, 4, 5, 1, 0),
426 
427         SOC_DOUBLE_R_TLV("MIC Gain Volume", CS42L52_MICA_CTL,
428                               CS42L52_MICB_CTL, 0, 0x10, 0, mic_tlv),
429 
430         SOC_ENUM("MIC Bias Level", mic_bias_level_enum),
431 
432         SOC_DOUBLE_R_SX_TLV("ADC Volume", CS42L52_ADCA_VOL,
433                               CS42L52_ADCB_VOL, 7, 0x80, 0xA0, ipd_tlv),
434         SOC_DOUBLE_R_SX_TLV("ADC Mixer Volume",
435                              CS42L52_ADCA_MIXER_VOL, CS42L52_ADCB_MIXER_VOL,
436                                 6, 0x7f, 0x19, ipd_tlv),
437 
438         SOC_DOUBLE("ADC Switch", CS42L52_ADC_MISC_CTL, 0, 1, 1, 0),
439 
440         SOC_DOUBLE_R("ADC Mixer Switch", CS42L52_ADCA_MIXER_VOL,
441                      CS42L52_ADCB_MIXER_VOL, 7, 1, 1),
442 
443         SOC_DOUBLE_R_SX_TLV("PGA Volume", CS42L52_PGAA_CTL,
444                             CS42L52_PGAB_CTL, 0, 0x28, 0x30, pga_tlv),
445 
446         SOC_DOUBLE_R_SX_TLV("PCM Mixer Volume",
447                             CS42L52_PCMA_MIXER_VOL, CS42L52_PCMB_MIXER_VOL,
448                                 0, 0x7f, 0x19, mix_tlv),
449         SOC_DOUBLE_R("PCM Mixer Switch",
450                      CS42L52_PCMA_MIXER_VOL, CS42L52_PCMB_MIXER_VOL, 7, 1, 1),
451 
452         SOC_ENUM("Beep Config", beep_config_enum),
453         SOC_ENUM("Beep Pitch", beep_pitch_enum),
454         SOC_ENUM("Beep on Time", beep_ontime_enum),
455         SOC_ENUM("Beep off Time", beep_offtime_enum),
456         SOC_SINGLE_SX_TLV("Beep Volume", CS42L52_BEEP_VOL,
457                         0, 0x07, 0x1f, beep_tlv),
458         SOC_SINGLE("Beep Mixer Switch", CS42L52_BEEP_TONE_CTL, 5, 1, 1),
459         SOC_ENUM("Beep Treble Corner Freq", beep_treble_enum),
460         SOC_ENUM("Beep Bass Corner Freq", beep_bass_enum),
461 
462         SOC_SINGLE("Tone Control Switch", CS42L52_BEEP_TONE_CTL, 0, 1, 1),
463         SOC_SINGLE_TLV("Treble Gain Volume",
464                             CS42L52_TONE_CTL, 4, 15, 1, hl_tlv),
465         SOC_SINGLE_TLV("Bass Gain Volume",
466                             CS42L52_TONE_CTL, 0, 15, 1, hl_tlv),
467 
468         /* Limiter */
469         SOC_SINGLE_TLV("Limiter Max Threshold Volume",
470                        CS42L52_LIMITER_CTL1, 5, 7, 0, limiter_tlv),
471         SOC_SINGLE_TLV("Limiter Cushion Threshold Volume",
472                        CS42L52_LIMITER_CTL1, 2, 7, 0, limiter_tlv),
473         SOC_SINGLE_TLV("Limiter Release Rate Volume",
474                        CS42L52_LIMITER_CTL2, 0, 63, 0, limiter_tlv),
475         SOC_SINGLE_TLV("Limiter Attack Rate Volume",
476                        CS42L52_LIMITER_AT_RATE, 0, 63, 0, limiter_tlv),
477 
478         SOC_SINGLE("Limiter SR Switch", CS42L52_LIMITER_CTL1, 1, 1, 0),
479         SOC_SINGLE("Limiter ZC Switch", CS42L52_LIMITER_CTL1, 0, 1, 0),
480         SOC_SINGLE("Limiter Switch", CS42L52_LIMITER_CTL2, 7, 1, 0),
481 
482         /* ALC */
483         SOC_SINGLE_TLV("ALC Attack Rate Volume", CS42L52_ALC_CTL,
484                        0, 63, 0, limiter_tlv),
485         SOC_SINGLE_TLV("ALC Release Rate Volume", CS42L52_ALC_RATE,
486                        0, 63, 0, limiter_tlv),
487         SOC_SINGLE_TLV("ALC Max Threshold Volume", CS42L52_ALC_THRESHOLD,
488                        5, 7, 0, limiter_tlv),
489         SOC_SINGLE_TLV("ALC Min Threshold Volume", CS42L52_ALC_THRESHOLD,
490                        2, 7, 0, limiter_tlv),
491 
492         SOC_DOUBLE_R("ALC SR Capture Switch", CS42L52_PGAA_CTL,
493                      CS42L52_PGAB_CTL, 7, 1, 1),
494         SOC_DOUBLE_R("ALC ZC Capture Switch", CS42L52_PGAA_CTL,
495                      CS42L52_PGAB_CTL, 6, 1, 1),
496         SOC_DOUBLE("ALC Capture Switch", CS42L52_ALC_CTL, 6, 7, 1, 0),
497 
498         /* Noise gate */
499         SOC_ENUM("NG Type Switch", ng_type_enum),
500         SOC_SINGLE("NG Enable Switch", CS42L52_NOISE_GATE_CTL, 6, 1, 0),
501         SOC_SINGLE("NG Boost Switch", CS42L52_NOISE_GATE_CTL, 5, 1, 1),
502         SOC_ENUM("NG Threshold", ng_threshold_enum),
503         SOC_ENUM("NG Delay", ng_delay_enum),
504 
505         SOC_DOUBLE("HPF Switch", CS42L52_ANALOG_HPF_CTL, 5, 7, 1, 0),
506 
507         SOC_DOUBLE("Analog SR Switch", CS42L52_ANALOG_HPF_CTL, 1, 3, 1, 1),
508         SOC_DOUBLE("Analog ZC Switch", CS42L52_ANALOG_HPF_CTL, 0, 2, 1, 1),
509         SOC_SINGLE("Digital SR Switch", CS42L52_MISC_CTL, 1, 1, 0),
510         SOC_SINGLE("Digital ZC Switch", CS42L52_MISC_CTL, 0, 1, 0),
511         SOC_SINGLE("Deemphasis Switch", CS42L52_MISC_CTL, 2, 1, 0),
512 
513         SOC_SINGLE("Batt Compensation Switch", CS42L52_BATT_COMPEN, 7, 1, 0),
514         SOC_SINGLE("Batt VP Monitor Switch", CS42L52_BATT_COMPEN, 6, 1, 0),
515         SOC_SINGLE("Batt VP ref", CS42L52_BATT_COMPEN, 0, 0x0f, 0),
516 
517         SOC_SINGLE("PGA AIN1L Switch", CS42L52_ADC_PGA_A, 0, 1, 0),
518         SOC_SINGLE("PGA AIN1R Switch", CS42L52_ADC_PGA_B, 0, 1, 0),
519         SOC_SINGLE("PGA AIN2L Switch", CS42L52_ADC_PGA_A, 1, 1, 0),
520         SOC_SINGLE("PGA AIN2R Switch", CS42L52_ADC_PGA_B, 1, 1, 0),
521 
522         SOC_SINGLE("PGA AIN3L Switch", CS42L52_ADC_PGA_A, 2, 1, 0),
523         SOC_SINGLE("PGA AIN3R Switch", CS42L52_ADC_PGA_B, 2, 1, 0),
524 
525         SOC_SINGLE("PGA AIN4L Switch", CS42L52_ADC_PGA_A, 3, 1, 0),
526         SOC_SINGLE("PGA AIN4R Switch", CS42L52_ADC_PGA_B, 3, 1, 0),
527 
528         SOC_SINGLE("PGA MICA Switch", CS42L52_ADC_PGA_A, 4, 1, 0),
529         SOC_SINGLE("PGA MICB Switch", CS42L52_ADC_PGA_B, 4, 1, 0),
530 
531 };
532 
533 static const struct snd_soc_dapm_widget cs42l52_dapm_widgets[] = {
534 
535         SND_SOC_DAPM_INPUT("AIN1L"),
536         SND_SOC_DAPM_INPUT("AIN1R"),
537         SND_SOC_DAPM_INPUT("AIN2L"),
538         SND_SOC_DAPM_INPUT("AIN2R"),
539         SND_SOC_DAPM_INPUT("AIN3L"),
540         SND_SOC_DAPM_INPUT("AIN3R"),
541         SND_SOC_DAPM_INPUT("AIN4L"),
542         SND_SOC_DAPM_INPUT("AIN4R"),
543         SND_SOC_DAPM_INPUT("MICA"),
544         SND_SOC_DAPM_INPUT("MICB"),
545         SND_SOC_DAPM_SIGGEN("Beep"),
546 
547         SND_SOC_DAPM_AIF_OUT("AIFOUTL", NULL,  0,
548                         SND_SOC_NOPM, 0, 0),
549         SND_SOC_DAPM_AIF_OUT("AIFOUTR", NULL,  0,
550                         SND_SOC_NOPM, 0, 0),
551 
552         SND_SOC_DAPM_MUX("MICA Mux", SND_SOC_NOPM, 0, 0, &mica_mux),
553         SND_SOC_DAPM_MUX("MICB Mux", SND_SOC_NOPM, 0, 0, &micb_mux),
554 
555         SND_SOC_DAPM_ADC("ADC Left", NULL, CS42L52_PWRCTL1, 1, 1),
556         SND_SOC_DAPM_ADC("ADC Right", NULL, CS42L52_PWRCTL1, 2, 1),
557         SND_SOC_DAPM_PGA("PGA Left", CS42L52_PWRCTL1, 3, 1, NULL, 0),
558         SND_SOC_DAPM_PGA("PGA Right", CS42L52_PWRCTL1, 4, 1, NULL, 0),
559 
560         SND_SOC_DAPM_MUX("ADC Left Mux", SND_SOC_NOPM, 0, 0, &adca_mux),
561         SND_SOC_DAPM_MUX("ADC Right Mux", SND_SOC_NOPM, 0, 0, &adcb_mux),
562 
563         SND_SOC_DAPM_MUX("ADC Left Swap", SND_SOC_NOPM,
564                          0, 0, &adca_mixer),
565         SND_SOC_DAPM_MUX("ADC Right Swap", SND_SOC_NOPM,
566                          0, 0, &adcb_mixer),
567 
568         SND_SOC_DAPM_MUX("Output Mux", SND_SOC_NOPM,
569                          0, 0, &digital_output_mux),
570 
571         SND_SOC_DAPM_PGA("PGA MICA", CS42L52_PWRCTL2, 1, 1, NULL, 0),
572         SND_SOC_DAPM_PGA("PGA MICB", CS42L52_PWRCTL2, 2, 1, NULL, 0),
573 
574         SND_SOC_DAPM_SUPPLY("Mic Bias", CS42L52_PWRCTL2, 0, 1, NULL, 0),
575         SND_SOC_DAPM_SUPPLY("Charge Pump", CS42L52_PWRCTL1, 7, 1, NULL, 0),
576 
577         SND_SOC_DAPM_AIF_IN("AIFINL", NULL,  0,
578                         SND_SOC_NOPM, 0, 0),
579         SND_SOC_DAPM_AIF_IN("AIFINR", NULL,  0,
580                         SND_SOC_NOPM, 0, 0),
581 
582         SND_SOC_DAPM_DAC("DAC Left", NULL, SND_SOC_NOPM, 0, 0),
583         SND_SOC_DAPM_DAC("DAC Right", NULL, SND_SOC_NOPM, 0, 0),
584 
585         SND_SOC_DAPM_SWITCH("Bypass Left", CS42L52_MISC_CTL,
586                             6, 0, &passthrul_ctl),
587         SND_SOC_DAPM_SWITCH("Bypass Right", CS42L52_MISC_CTL,
588                             7, 0, &passthrur_ctl),
589 
590         SND_SOC_DAPM_MUX("PCM Left Swap", SND_SOC_NOPM,
591                          0, 0, &pcma_mixer),
592         SND_SOC_DAPM_MUX("PCM Right Swap", SND_SOC_NOPM,
593                          0, 0, &pcmb_mixer),
594 
595         SND_SOC_DAPM_SWITCH("HP Left Amp", SND_SOC_NOPM, 0, 0, &hpl_ctl),
596         SND_SOC_DAPM_SWITCH("HP Right Amp", SND_SOC_NOPM, 0, 0, &hpr_ctl),
597 
598         SND_SOC_DAPM_SWITCH("SPK Left Amp", SND_SOC_NOPM, 0, 0, &spkl_ctl),
599         SND_SOC_DAPM_SWITCH("SPK Right Amp", SND_SOC_NOPM, 0, 0, &spkr_ctl),
600 
601         SND_SOC_DAPM_OUTPUT("HPOUTA"),
602         SND_SOC_DAPM_OUTPUT("HPOUTB"),
603         SND_SOC_DAPM_OUTPUT("SPKOUTA"),
604         SND_SOC_DAPM_OUTPUT("SPKOUTB"),
605 
606 };
607 
608 static const struct snd_soc_dapm_route cs42l52_audio_map[] = {
609 
610         {"Capture", NULL, "AIFOUTL"},
611         {"Capture", NULL, "AIFOUTL"},
612 
613         {"AIFOUTL", NULL, "Output Mux"},
614         {"AIFOUTR", NULL, "Output Mux"},
615 
616         {"Output Mux", "ADC", "ADC Left"},
617         {"Output Mux", "ADC", "ADC Right"},
618 
619         {"ADC Left", NULL, "Charge Pump"},
620         {"ADC Right", NULL, "Charge Pump"},
621 
622         {"Charge Pump", NULL, "ADC Left Mux"},
623         {"Charge Pump", NULL, "ADC Right Mux"},
624 
625         {"ADC Left Mux", "Input1A", "AIN1L"},
626         {"ADC Right Mux", "Input1B", "AIN1R"},
627         {"ADC Left Mux", "Input2A", "AIN2L"},
628         {"ADC Right Mux", "Input2B", "AIN2R"},
629         {"ADC Left Mux", "Input3A", "AIN3L"},
630         {"ADC Right Mux", "Input3B", "AIN3R"},
631         {"ADC Left Mux", "Input4A", "AIN4L"},
632         {"ADC Right Mux", "Input4B", "AIN4R"},
633         {"ADC Left Mux", "PGA Input Left", "PGA Left"},
634         {"ADC Right Mux", "PGA Input Right" , "PGA Right"},
635 
636         {"PGA Left", "Switch", "AIN1L"},
637         {"PGA Right", "Switch", "AIN1R"},
638         {"PGA Left", "Switch", "AIN2L"},
639         {"PGA Right", "Switch", "AIN2R"},
640         {"PGA Left", "Switch", "AIN3L"},
641         {"PGA Right", "Switch", "AIN3R"},
642         {"PGA Left", "Switch", "AIN4L"},
643         {"PGA Right", "Switch", "AIN4R"},
644 
645         {"PGA Left", "Switch", "PGA MICA"},
646         {"PGA MICA", NULL, "MICA"},
647 
648         {"PGA Right", "Switch", "PGA MICB"},
649         {"PGA MICB", NULL, "MICB"},
650 
651         {"HPOUTA", NULL, "HP Left Amp"},
652         {"HPOUTB", NULL, "HP Right Amp"},
653         {"HP Left Amp", NULL, "Bypass Left"},
654         {"HP Right Amp", NULL, "Bypass Right"},
655         {"Bypass Left", "Switch", "PGA Left"},
656         {"Bypass Right", "Switch", "PGA Right"},
657         {"HP Left Amp", "Switch", "DAC Left"},
658         {"HP Right Amp", "Switch", "DAC Right"},
659 
660         {"SPKOUTA", NULL, "SPK Left Amp"},
661         {"SPKOUTB", NULL, "SPK Right Amp"},
662 
663         {"SPK Left Amp", NULL, "Beep"},
664         {"SPK Right Amp", NULL, "Beep"},
665         {"SPK Left Amp", "Switch", "Playback"},
666         {"SPK Right Amp", "Switch", "Playback"},
667 
668         {"DAC Left", NULL, "Beep"},
669         {"DAC Right", NULL, "Beep"},
670         {"DAC Left", NULL, "Playback"},
671         {"DAC Right", NULL, "Playback"},
672 
673         {"Output Mux", "DSP", "Playback"},
674         {"Output Mux", "DSP", "Playback"},
675 
676         {"AIFINL", NULL, "Playback"},
677         {"AIFINR", NULL, "Playback"},
678 
679 };
680 
681 struct cs42l52_clk_para {
682         u32 mclk;
683         u32 rate;
684         u8 speed;
685         u8 group;
686         u8 videoclk;
687         u8 ratio;
688         u8 mclkdiv2;
689 };
690 
691 static const struct cs42l52_clk_para clk_map_table[] = {
692         /*8k*/
693         {12288000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
694         {18432000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
695         {12000000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 0},
696         {24000000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 1},
697         {27000000, 8000, CLK_QS_MODE, CLK_32K, CLK_27M_MCLK, CLK_R_125, 0},
698 
699         /*11.025k*/
700         {11289600, 11025, CLK_QS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
701         {16934400, 11025, CLK_QS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
702 
703         /*16k*/
704         {12288000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
705         {18432000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
706         {12000000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 0},
707         {24000000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 1},
708         {27000000, 16000, CLK_HS_MODE, CLK_32K, CLK_27M_MCLK, CLK_R_125, 1},
709 
710         /*22.05k*/
711         {11289600, 22050, CLK_HS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
712         {16934400, 22050, CLK_HS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
713 
714         /* 32k */
715         {12288000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
716         {18432000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
717         {12000000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 0},
718         {24000000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 1},
719         {27000000, 32000, CLK_SS_MODE, CLK_32K, CLK_27M_MCLK, CLK_R_125, 0},
720 
721         /* 44.1k */
722         {11289600, 44100, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
723         {16934400, 44100, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
724 
725         /* 48k */
726         {12288000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
727         {18432000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
728         {12000000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 0},
729         {24000000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 1},
730         {27000000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_27M_MCLK, CLK_R_125, 1},
731 
732         /* 88.2k */
733         {11289600, 88200, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
734         {16934400, 88200, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
735 
736         /* 96k */
737         {12288000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
738         {18432000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
739         {12000000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 0},
740         {24000000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 1},
741 };
742 
743 static int cs42l52_get_clk(int mclk, int rate)
744 {
745         int i, ret = -EINVAL;
746         u_int mclk1, mclk2 = 0;
747 
748         for (i = 0; i < ARRAY_SIZE(clk_map_table); i++) {
749                 if (clk_map_table[i].rate == rate) {
750                         mclk1 = clk_map_table[i].mclk;
751                         if (abs(mclk - mclk1) < abs(mclk - mclk2)) {
752                                 mclk2 = mclk1;
753                                 ret = i;
754                         }
755                 }
756         }
757         return ret;
758 }
759 
760 static int cs42l52_set_sysclk(struct snd_soc_dai *codec_dai,
761                         int clk_id, unsigned int freq, int dir)
762 {
763         struct snd_soc_codec *codec = codec_dai->codec;
764         struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
765 
766         if ((freq >= CS42L52_MIN_CLK) && (freq <= CS42L52_MAX_CLK)) {
767                 cs42l52->sysclk = freq;
768         } else {
769                 dev_err(codec->dev, "Invalid freq parameter\n");
770                 return -EINVAL;
771         }
772         return 0;
773 }
774 
775 static int cs42l52_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
776 {
777         struct snd_soc_codec *codec = codec_dai->codec;
778         struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
779         u8 iface = 0;
780 
781         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
782         case SND_SOC_DAIFMT_CBM_CFM:
783                 iface = CS42L52_IFACE_CTL1_MASTER;
784                 break;
785         case SND_SOC_DAIFMT_CBS_CFS:
786                 iface = CS42L52_IFACE_CTL1_SLAVE;
787                 break;
788         default:
789                 return -EINVAL;
790         }
791 
792          /* interface format */
793         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
794         case SND_SOC_DAIFMT_I2S:
795                 iface |= CS42L52_IFACE_CTL1_ADC_FMT_I2S |
796                                 CS42L52_IFACE_CTL1_DAC_FMT_I2S;
797                 break;
798         case SND_SOC_DAIFMT_RIGHT_J:
799                 iface |= CS42L52_IFACE_CTL1_DAC_FMT_RIGHT_J;
800                 break;
801         case SND_SOC_DAIFMT_LEFT_J:
802                 iface |= CS42L52_IFACE_CTL1_ADC_FMT_LEFT_J |
803                                 CS42L52_IFACE_CTL1_DAC_FMT_LEFT_J;
804                 break;
805         case SND_SOC_DAIFMT_DSP_A:
806                 iface |= CS42L52_IFACE_CTL1_DSP_MODE_EN;
807                 break;
808         case SND_SOC_DAIFMT_DSP_B:
809                 break;
810         default:
811                 return -EINVAL;
812         }
813 
814         /* clock inversion */
815         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
816         case SND_SOC_DAIFMT_NB_NF:
817                 break;
818         case SND_SOC_DAIFMT_IB_IF:
819                 iface |= CS42L52_IFACE_CTL1_INV_SCLK;
820                 break;
821         case SND_SOC_DAIFMT_IB_NF:
822                 iface |= CS42L52_IFACE_CTL1_INV_SCLK;
823                 break;
824         case SND_SOC_DAIFMT_NB_IF:
825                 break;
826         default:
827                 return -EINVAL;
828         }
829         cs42l52->config.format = iface;
830         snd_soc_write(codec, CS42L52_IFACE_CTL1, cs42l52->config.format);
831 
832         return 0;
833 }
834 
835 static int cs42l52_digital_mute(struct snd_soc_dai *dai, int mute)
836 {
837         struct snd_soc_codec *codec = dai->codec;
838 
839         if (mute)
840                 snd_soc_update_bits(codec, CS42L52_PB_CTL1,
841                                     CS42L52_PB_CTL1_MUTE_MASK,
842                                 CS42L52_PB_CTL1_MUTE);
843         else
844                 snd_soc_update_bits(codec, CS42L52_PB_CTL1,
845                                     CS42L52_PB_CTL1_MUTE_MASK,
846                                 CS42L52_PB_CTL1_UNMUTE);
847 
848         return 0;
849 }
850 
851 static int cs42l52_pcm_hw_params(struct snd_pcm_substream *substream,
852                                      struct snd_pcm_hw_params *params,
853                                      struct snd_soc_dai *dai)
854 {
855         struct snd_soc_codec *codec = dai->codec;
856         struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
857         u32 clk = 0;
858         int index;
859 
860         index = cs42l52_get_clk(cs42l52->sysclk, params_rate(params));
861         if (index >= 0) {
862                 cs42l52->sysclk = clk_map_table[index].mclk;
863 
864                 clk |= (clk_map_table[index].speed << CLK_SPEED_SHIFT) |
865                 (clk_map_table[index].group << CLK_32K_SR_SHIFT) |
866                 (clk_map_table[index].videoclk << CLK_27M_MCLK_SHIFT) |
867                 (clk_map_table[index].ratio << CLK_RATIO_SHIFT) |
868                 clk_map_table[index].mclkdiv2;
869 
870                 snd_soc_write(codec, CS42L52_CLK_CTL, clk);
871         } else {
872                 dev_err(codec->dev, "can't get correct mclk\n");
873                 return -EINVAL;
874         }
875 
876         return 0;
877 }
878 
879 static int cs42l52_set_bias_level(struct snd_soc_codec *codec,
880                                         enum snd_soc_bias_level level)
881 {
882         struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
883 
884         switch (level) {
885         case SND_SOC_BIAS_ON:
886                 break;
887         case SND_SOC_BIAS_PREPARE:
888                 snd_soc_update_bits(codec, CS42L52_PWRCTL1,
889                                     CS42L52_PWRCTL1_PDN_CODEC, 0);
890                 break;
891         case SND_SOC_BIAS_STANDBY:
892                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
893                         regcache_cache_only(cs42l52->regmap, false);
894                         regcache_sync(cs42l52->regmap);
895                 }
896                 snd_soc_write(codec, CS42L52_PWRCTL1, CS42L52_PWRCTL1_PDN_ALL);
897                 break;
898         case SND_SOC_BIAS_OFF:
899                 snd_soc_write(codec, CS42L52_PWRCTL1, CS42L52_PWRCTL1_PDN_ALL);
900                 regcache_cache_only(cs42l52->regmap, true);
901                 break;
902         }
903         codec->dapm.bias_level = level;
904 
905         return 0;
906 }
907 
908 #define CS42L52_RATES (SNDRV_PCM_RATE_8000_96000)
909 
910 #define CS42L52_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE | \
911                         SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_U18_3LE | \
912                         SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_U20_3LE | \
913                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_U24_LE)
914 
915 static struct snd_soc_dai_ops cs42l52_ops = {
916         .hw_params      = cs42l52_pcm_hw_params,
917         .digital_mute   = cs42l52_digital_mute,
918         .set_fmt        = cs42l52_set_fmt,
919         .set_sysclk     = cs42l52_set_sysclk,
920 };
921 
922 static struct snd_soc_dai_driver cs42l52_dai = {
923                 .name = "cs42l52",
924                 .playback = {
925                         .stream_name = "Playback",
926                         .channels_min = 1,
927                         .channels_max = 2,
928                         .rates = CS42L52_RATES,
929                         .formats = CS42L52_FORMATS,
930                 },
931                 .capture = {
932                         .stream_name = "Capture",
933                         .channels_min = 1,
934                         .channels_max = 2,
935                         .rates = CS42L52_RATES,
936                         .formats = CS42L52_FORMATS,
937                 },
938                 .ops = &cs42l52_ops,
939 };
940 
941 static int cs42l52_suspend(struct snd_soc_codec *codec)
942 {
943         cs42l52_set_bias_level(codec, SND_SOC_BIAS_OFF);
944 
945         return 0;
946 }
947 
948 static int cs42l52_resume(struct snd_soc_codec *codec)
949 {
950         cs42l52_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
951 
952         return 0;
953 }
954 
955 #if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
956 static int beep_rates[] = {
957         261, 522, 585, 667, 706, 774, 889, 1000,
958         1043, 1200, 1333, 1412, 1600, 1714, 2000, 2182
959 };
960 
961 static void cs42l52_beep_work(struct work_struct *work)
962 {
963         struct cs42l52_private *cs42l52 =
964                 container_of(work, struct cs42l52_private, beep_work);
965         struct snd_soc_codec *codec = cs42l52->codec;
966         struct snd_soc_dapm_context *dapm = &codec->dapm;
967         int i;
968         int val = 0;
969         int best = 0;
970 
971         if (cs42l52->beep_rate) {
972                 for (i = 0; i < ARRAY_SIZE(beep_rates); i++) {
973                         if (abs(cs42l52->beep_rate - beep_rates[i]) <
974                             abs(cs42l52->beep_rate - beep_rates[best]))
975                                 best = i;
976                 }
977 
978                 dev_dbg(codec->dev, "Set beep rate %dHz for requested %dHz\n",
979                         beep_rates[best], cs42l52->beep_rate);
980 
981                 val = (best << CS42L52_BEEP_RATE_SHIFT);
982 
983                 snd_soc_dapm_enable_pin(dapm, "Beep");
984         } else {
985                 dev_dbg(codec->dev, "Disabling beep\n");
986                 snd_soc_dapm_disable_pin(dapm, "Beep");
987         }
988 
989         snd_soc_update_bits(codec, CS42L52_BEEP_FREQ,
990                             CS42L52_BEEP_RATE_MASK, val);
991 
992         snd_soc_dapm_sync(dapm);
993 }
994 
995 /* For usability define a way of injecting beep events for the device -
996  * many systems will not have a keyboard.
997  */
998 static int cs42l52_beep_event(struct input_dev *dev, unsigned int type,
999                              unsigned int code, int hz)
1000 {
1001         struct snd_soc_codec *codec = input_get_drvdata(dev);
1002         struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
1003 
1004         dev_dbg(codec->dev, "Beep event %x %x\n", code, hz);
1005 
1006         switch (code) {
1007         case SND_BELL:
1008                 if (hz)
1009                         hz = 261;
1010         case SND_TONE:
1011                 break;
1012         default:
1013                 return -1;
1014         }
1015 
1016         /* Kick the beep from a workqueue */
1017         cs42l52->beep_rate = hz;
1018         schedule_work(&cs42l52->beep_work);
1019         return 0;
1020 }
1021 
1022 static ssize_t cs42l52_beep_set(struct device *dev,
1023                                struct device_attribute *attr,
1024                                const char *buf, size_t count)
1025 {
1026         struct cs42l52_private *cs42l52 = dev_get_drvdata(dev);
1027         long int time;
1028         int ret;
1029 
1030         ret = kstrtol(buf, 10, &time);
1031         if (ret != 0)
1032                 return ret;
1033 
1034         input_event(cs42l52->beep, EV_SND, SND_TONE, time);
1035 
1036         return count;
1037 }
1038 
1039 static DEVICE_ATTR(beep, 0200, NULL, cs42l52_beep_set);
1040 
1041 static void cs42l52_init_beep(struct snd_soc_codec *codec)
1042 {
1043         struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
1044         int ret;
1045 
1046         cs42l52->beep = devm_input_allocate_device(codec->dev);
1047         if (!cs42l52->beep) {
1048                 dev_err(codec->dev, "Failed to allocate beep device\n");
1049                 return;
1050         }
1051 
1052         INIT_WORK(&cs42l52->beep_work, cs42l52_beep_work);
1053         cs42l52->beep_rate = 0;
1054 
1055         cs42l52->beep->name = "CS42L52 Beep Generator";
1056         cs42l52->beep->phys = dev_name(codec->dev);
1057         cs42l52->beep->id.bustype = BUS_I2C;
1058 
1059         cs42l52->beep->evbit[0] = BIT_MASK(EV_SND);
1060         cs42l52->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE);
1061         cs42l52->beep->event = cs42l52_beep_event;
1062         cs42l52->beep->dev.parent = codec->dev;
1063         input_set_drvdata(cs42l52->beep, codec);
1064 
1065         ret = input_register_device(cs42l52->beep);
1066         if (ret != 0) {
1067                 cs42l52->beep = NULL;
1068                 dev_err(codec->dev, "Failed to register beep device\n");
1069         }
1070 
1071         ret = device_create_file(codec->dev, &dev_attr_beep);
1072         if (ret != 0) {
1073                 dev_err(codec->dev, "Failed to create keyclick file: %d\n",
1074                         ret);
1075         }
1076 }
1077 
1078 static void cs42l52_free_beep(struct snd_soc_codec *codec)
1079 {
1080         struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
1081 
1082         device_remove_file(codec->dev, &dev_attr_beep);
1083         cancel_work_sync(&cs42l52->beep_work);
1084         cs42l52->beep = NULL;
1085 
1086         snd_soc_update_bits(codec, CS42L52_BEEP_TONE_CTL,
1087                             CS42L52_BEEP_EN_MASK, 0);
1088 }
1089 #else
1090 static void cs42l52_init_beep(struct snd_soc_codec *codec)
1091 {
1092 }
1093 
1094 static void cs42l52_free_beep(struct snd_soc_codec *codec)
1095 {
1096 }
1097 #endif
1098 
1099 static int cs42l52_probe(struct snd_soc_codec *codec)
1100 {
1101         struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
1102         int ret;
1103 
1104         codec->control_data = cs42l52->regmap;
1105         ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP);
1106         if (ret < 0) {
1107                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1108                 return ret;
1109         }
1110         regcache_cache_only(cs42l52->regmap, true);
1111 
1112         cs42l52_init_beep(codec);
1113 
1114         cs42l52_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1115 
1116         cs42l52->sysclk = CS42L52_DEFAULT_CLK;
1117         cs42l52->config.format = CS42L52_DEFAULT_FORMAT;
1118 
1119         /* Set Platform MICx CFG */
1120         snd_soc_update_bits(codec, CS42L52_MICA_CTL,
1121                             CS42L52_MIC_CTL_TYPE_MASK,
1122                                 cs42l52->pdata.mica_cfg <<
1123                                 CS42L52_MIC_CTL_TYPE_SHIFT);
1124 
1125         snd_soc_update_bits(codec, CS42L52_MICB_CTL,
1126                             CS42L52_MIC_CTL_TYPE_MASK,
1127                                 cs42l52->pdata.micb_cfg <<
1128                                 CS42L52_MIC_CTL_TYPE_SHIFT);
1129 
1130         /* if Single Ended, Get Mic_Select */
1131         if (cs42l52->pdata.mica_cfg)
1132                 snd_soc_update_bits(codec, CS42L52_MICA_CTL,
1133                                     CS42L52_MIC_CTL_MIC_SEL_MASK,
1134                                 cs42l52->pdata.mica_sel <<
1135                                 CS42L52_MIC_CTL_MIC_SEL_SHIFT);
1136         if (cs42l52->pdata.micb_cfg)
1137                 snd_soc_update_bits(codec, CS42L52_MICB_CTL,
1138                                     CS42L52_MIC_CTL_MIC_SEL_MASK,
1139                                 cs42l52->pdata.micb_sel <<
1140                                 CS42L52_MIC_CTL_MIC_SEL_SHIFT);
1141 
1142         /* Set Platform Charge Pump Freq */
1143         snd_soc_update_bits(codec, CS42L52_CHARGE_PUMP,
1144                             CS42L52_CHARGE_PUMP_MASK,
1145                                 cs42l52->pdata.chgfreq <<
1146                                 CS42L52_CHARGE_PUMP_SHIFT);
1147 
1148         /* Set Platform Bias Level */
1149         snd_soc_update_bits(codec, CS42L52_IFACE_CTL2,
1150                             CS42L52_IFACE_CTL2_BIAS_LVL,
1151                                 cs42l52->pdata.micbias_lvl);
1152 
1153         return ret;
1154 }
1155 
1156 static int cs42l52_remove(struct snd_soc_codec *codec)
1157 {
1158         cs42l52_free_beep(codec);
1159         cs42l52_set_bias_level(codec, SND_SOC_BIAS_OFF);
1160 
1161         return 0;
1162 }
1163 
1164 static struct snd_soc_codec_driver soc_codec_dev_cs42l52 = {
1165         .probe = cs42l52_probe,
1166         .remove = cs42l52_remove,
1167         .suspend = cs42l52_suspend,
1168         .resume = cs42l52_resume,
1169         .set_bias_level = cs42l52_set_bias_level,
1170 
1171         .dapm_widgets = cs42l52_dapm_widgets,
1172         .num_dapm_widgets = ARRAY_SIZE(cs42l52_dapm_widgets),
1173         .dapm_routes = cs42l52_audio_map,
1174         .num_dapm_routes = ARRAY_SIZE(cs42l52_audio_map),
1175 
1176         .controls = cs42l52_snd_controls,
1177         .num_controls = ARRAY_SIZE(cs42l52_snd_controls),
1178 };
1179 
1180 /* Current and threshold powerup sequence Pg37 */
1181 static const struct reg_default cs42l52_threshold_patch[] = {
1182 
1183         { 0x00, 0x99 },
1184         { 0x3E, 0xBA },
1185         { 0x47, 0x80 },
1186         { 0x32, 0xBB },
1187         { 0x32, 0x3B },
1188         { 0x00, 0x00 },
1189 
1190 };
1191 
1192 static struct regmap_config cs42l52_regmap = {
1193         .reg_bits = 8,
1194         .val_bits = 8,
1195 
1196         .max_register = CS42L52_MAX_REGISTER,
1197         .reg_defaults = cs42l52_reg_defaults,
1198         .num_reg_defaults = ARRAY_SIZE(cs42l52_reg_defaults),
1199         .readable_reg = cs42l52_readable_register,
1200         .volatile_reg = cs42l52_volatile_register,
1201         .cache_type = REGCACHE_RBTREE,
1202 };
1203 
1204 static int cs42l52_i2c_probe(struct i2c_client *i2c_client,
1205                              const struct i2c_device_id *id)
1206 {
1207         struct cs42l52_private *cs42l52;
1208         int ret;
1209         unsigned int devid = 0;
1210         unsigned int reg;
1211 
1212         cs42l52 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42l52_private),
1213                                GFP_KERNEL);
1214         if (cs42l52 == NULL)
1215                 return -ENOMEM;
1216         cs42l52->dev = &i2c_client->dev;
1217 
1218         cs42l52->regmap = devm_regmap_init_i2c(i2c_client, &cs42l52_regmap);
1219         if (IS_ERR(cs42l52->regmap)) {
1220                 ret = PTR_ERR(cs42l52->regmap);
1221                 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
1222                 return ret;
1223         }
1224 
1225         i2c_set_clientdata(i2c_client, cs42l52);
1226 
1227         if (dev_get_platdata(&i2c_client->dev))
1228                 memcpy(&cs42l52->pdata, dev_get_platdata(&i2c_client->dev),
1229                        sizeof(cs42l52->pdata));
1230 
1231         ret = regmap_register_patch(cs42l52->regmap, cs42l52_threshold_patch,
1232                                     ARRAY_SIZE(cs42l52_threshold_patch));
1233         if (ret != 0)
1234                 dev_warn(cs42l52->dev, "Failed to apply regmap patch: %d\n",
1235                          ret);
1236 
1237         ret = regmap_read(cs42l52->regmap, CS42L52_CHIP, &reg);
1238         devid = reg & CS42L52_CHIP_ID_MASK;
1239         if (devid != CS42L52_CHIP_ID) {
1240                 ret = -ENODEV;
1241                 dev_err(&i2c_client->dev,
1242                         "CS42L52 Device ID (%X). Expected %X\n",
1243                         devid, CS42L52_CHIP_ID);
1244                 return ret;
1245         }
1246 
1247         regcache_cache_only(cs42l52->regmap, true);
1248 
1249         ret =  snd_soc_register_codec(&i2c_client->dev,
1250                         &soc_codec_dev_cs42l52, &cs42l52_dai, 1);
1251         if (ret < 0)
1252                 return ret;
1253         return 0;
1254 }
1255 
1256 static int cs42l52_i2c_remove(struct i2c_client *client)
1257 {
1258         snd_soc_unregister_codec(&client->dev);
1259         return 0;
1260 }
1261 
1262 static const struct i2c_device_id cs42l52_id[] = {
1263         { "cs42l52", 0 },
1264         { }
1265 };
1266 MODULE_DEVICE_TABLE(i2c, cs42l52_id);
1267 
1268 static struct i2c_driver cs42l52_i2c_driver = {
1269         .driver = {
1270                 .name = "cs42l52",
1271                 .owner = THIS_MODULE,
1272         },
1273         .id_table = cs42l52_id,
1274         .probe =    cs42l52_i2c_probe,
1275         .remove =   cs42l52_i2c_remove,
1276 };
1277 
1278 module_i2c_driver(cs42l52_i2c_driver);
1279 
1280 MODULE_DESCRIPTION("ASoC CS42L52 driver");
1281 MODULE_AUTHOR("Georgi Vlaev, Nucleus Systems Ltd, <joe@nucleusys.com>");
1282 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
1283 MODULE_LICENSE("GPL");
1284 

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