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TOMOYO Linux Cross Reference
Linux/sound/soc/codecs/lm49453.c

Version: ~ [ linux-5.3-rc5 ] ~ [ linux-5.2.9 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.67 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.139 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.189 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.189 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.19.8 ] ~ [ linux-3.18.140 ] ~ [ linux-3.17.8 ] ~ [ linux-3.16.72 ] ~ [ linux-3.15.10 ] ~ [ linux-3.14.79 ] ~ [ linux-3.13.11 ] ~ [ linux-3.12.74 ] ~ [ linux-3.11.10 ] ~ [ linux-3.10.108 ] ~ [ linux-3.9.11 ] ~ [ linux-3.8.13 ] ~ [ linux-3.7.10 ] ~ [ linux-3.6.11 ] ~ [ linux-3.5.7 ] ~ [ linux-3.4.113 ] ~ [ linux-3.3.8 ] ~ [ linux-3.2.102 ] ~ [ linux-3.1.10 ] ~ [ linux-3.0.101 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.5 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  * lm49453.c  -  LM49453 ALSA Soc Audio driver
  3  *
  4  * Copyright (c) 2012 Texas Instruments, Inc
  5  *
  6  * This program is free software; you can redistribute it and/or modify
  7  * it under the terms of the GNU General Public License as published by
  8  * the Free Software Foundation; version 2 of the License.
  9  *
 10  * Initially based on sound/soc/codecs/wm8350.c
 11  */
 12 
 13 #include <linux/module.h>
 14 #include <linux/moduleparam.h>
 15 #include <linux/kernel.h>
 16 #include <linux/init.h>
 17 #include <linux/delay.h>
 18 #include <linux/pm.h>
 19 #include <linux/i2c.h>
 20 #include <linux/regmap.h>
 21 #include <linux/slab.h>
 22 #include <sound/core.h>
 23 #include <sound/pcm.h>
 24 #include <sound/pcm_params.h>
 25 #include <sound/soc.h>
 26 #include <sound/soc-dapm.h>
 27 #include <sound/tlv.h>
 28 #include <sound/jack.h>
 29 #include <sound/initval.h>
 30 #include <asm/div64.h>
 31 #include "lm49453.h"
 32 
 33 static struct reg_default lm49453_reg_defs[] = {
 34         { 0, 0x00 },
 35         { 1, 0x00 },
 36         { 2, 0x00 },
 37         { 3, 0x00 },
 38         { 4, 0x00 },
 39         { 5, 0x00 },
 40         { 6, 0x00 },
 41         { 7, 0x00 },
 42         { 8, 0x00 },
 43         { 9, 0x00 },
 44         { 10, 0x00 },
 45         { 11, 0x00 },
 46         { 12, 0x00 },
 47         { 13, 0x00 },
 48         { 14, 0x00 },
 49         { 15, 0x00 },
 50         { 16, 0x00 },
 51         { 17, 0x00 },
 52         { 18, 0x00 },
 53         { 19, 0x00 },
 54         { 20, 0x00 },
 55         { 21, 0x00 },
 56         { 22, 0x00 },
 57         { 23, 0x00 },
 58         { 32, 0x00 },
 59         { 33, 0x00 },
 60         { 35, 0x00 },
 61         { 36, 0x00 },
 62         { 37, 0x00 },
 63         { 46, 0x00 },
 64         { 48, 0x00 },
 65         { 49, 0x00 },
 66         { 51, 0x00 },
 67         { 56, 0x00 },
 68         { 58, 0x00 },
 69         { 59, 0x00 },
 70         { 60, 0x00 },
 71         { 61, 0x00 },
 72         { 62, 0x00 },
 73         { 63, 0x00 },
 74         { 64, 0x00 },
 75         { 65, 0x00 },
 76         { 66, 0x00 },
 77         { 67, 0x00 },
 78         { 68, 0x00 },
 79         { 69, 0x00 },
 80         { 70, 0x00 },
 81         { 71, 0x00 },
 82         { 72, 0x00 },
 83         { 73, 0x00 },
 84         { 74, 0x00 },
 85         { 75, 0x00 },
 86         { 76, 0x00 },
 87         { 77, 0x00 },
 88         { 78, 0x00 },
 89         { 79, 0x00 },
 90         { 80, 0x00 },
 91         { 81, 0x00 },
 92         { 82, 0x00 },
 93         { 83, 0x00 },
 94         { 85, 0x00 },
 95         { 85, 0x00 },
 96         { 86, 0x00 },
 97         { 87, 0x00 },
 98         { 88, 0x00 },
 99         { 89, 0x00 },
100         { 90, 0x00 },
101         { 91, 0x00 },
102         { 92, 0x00 },
103         { 93, 0x00 },
104         { 94, 0x00 },
105         { 95, 0x00 },
106         { 96, 0x01 },
107         { 97, 0x00 },
108         { 98, 0x00 },
109         { 99, 0x00 },
110         { 100, 0x00 },
111         { 101, 0x00 },
112         { 102, 0x00 },
113         { 103, 0x01 },
114         { 104, 0x01 },
115         { 105, 0x00 },
116         { 106, 0x01 },
117         { 107, 0x00 },
118         { 108, 0x00 },
119         { 109, 0x00 },
120         { 110, 0x00 },
121         { 111, 0x02 },
122         { 112, 0x02 },
123         { 113, 0x00 },
124         { 121, 0x80 },
125         { 122, 0xBB },
126         { 123, 0x80 },
127         { 124, 0xBB },
128         { 128, 0x00 },
129         { 130, 0x00 },
130         { 131, 0x00 },
131         { 132, 0x00 },
132         { 133, 0x0A },
133         { 134, 0x0A },
134         { 135, 0x0A },
135         { 136, 0x0F },
136         { 137, 0x00 },
137         { 138, 0x73 },
138         { 139, 0x33 },
139         { 140, 0x73 },
140         { 141, 0x33 },
141         { 142, 0x73 },
142         { 143, 0x33 },
143         { 144, 0x73 },
144         { 145, 0x33 },
145         { 146, 0x73 },
146         { 147, 0x33 },
147         { 148, 0x73 },
148         { 149, 0x33 },
149         { 150, 0x73 },
150         { 151, 0x33 },
151         { 152, 0x00 },
152         { 153, 0x00 },
153         { 154, 0x00 },
154         { 155, 0x00 },
155         { 176, 0x00 },
156         { 177, 0x00 },
157         { 178, 0x00 },
158         { 179, 0x00 },
159         { 180, 0x00 },
160         { 181, 0x00 },
161         { 182, 0x00 },
162         { 183, 0x00 },
163         { 184, 0x00 },
164         { 185, 0x00 },
165         { 186, 0x00 },
166         { 187, 0x00 },
167         { 188, 0x00 },
168         { 189, 0x00 },
169         { 208, 0x06 },
170         { 209, 0x00 },
171         { 210, 0x08 },
172         { 211, 0x54 },
173         { 212, 0x14 },
174         { 213, 0x0d },
175         { 214, 0x0d },
176         { 215, 0x14 },
177         { 216, 0x60 },
178         { 221, 0x00 },
179         { 222, 0x00 },
180         { 223, 0x00 },
181         { 224, 0x00 },
182         { 248, 0x00 },
183         { 249, 0x00 },
184         { 250, 0x00 },
185         { 255, 0x00 },
186 };
187 
188 /* codec private data */
189 struct lm49453_priv {
190         struct regmap *regmap;
191         int fs_rate;
192 };
193 
194 /* capture path controls */
195 
196 static const char *lm49453_mic2mode_text[] = {"Single Ended", "Differential"};
197 
198 static SOC_ENUM_SINGLE_DECL(lm49453_mic2mode_enum, LM49453_P0_MICR_REG, 5,
199                             lm49453_mic2mode_text);
200 
201 static const char *lm49453_dmic_cfg_text[] = {"DMICDAT1", "DMICDAT2"};
202 
203 static SOC_ENUM_SINGLE_DECL(lm49453_dmic12_cfg_enum,
204                             LM49453_P0_DIGITAL_MIC1_CONFIG_REG, 7,
205                             lm49453_dmic_cfg_text);
206 
207 static SOC_ENUM_SINGLE_DECL(lm49453_dmic34_cfg_enum,
208                             LM49453_P0_DIGITAL_MIC2_CONFIG_REG, 7,
209                             lm49453_dmic_cfg_text);
210 
211 /* MUX Controls */
212 static const char *lm49453_adcl_mux_text[] = { "MIC1", "Aux_L" };
213 
214 static const char *lm49453_adcr_mux_text[] = { "MIC2", "Aux_R" };
215 
216 static SOC_ENUM_SINGLE_DECL(lm49453_adcl_enum,
217                             LM49453_P0_ANALOG_MIXER_ADC_REG, 0,
218                             lm49453_adcl_mux_text);
219 
220 static SOC_ENUM_SINGLE_DECL(lm49453_adcr_enum,
221                             LM49453_P0_ANALOG_MIXER_ADC_REG, 1,
222                             lm49453_adcr_mux_text);
223 
224 static const struct snd_kcontrol_new lm49453_adcl_mux_control =
225         SOC_DAPM_ENUM("ADC Left Mux", lm49453_adcl_enum);
226 
227 static const struct snd_kcontrol_new lm49453_adcr_mux_control =
228         SOC_DAPM_ENUM("ADC Right Mux", lm49453_adcr_enum);
229 
230 static const struct snd_kcontrol_new lm49453_headset_left_mixer[] = {
231 SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHPL1_REG, 0, 1, 0),
232 SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHPL1_REG, 1, 1, 0),
233 SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHPL1_REG, 2, 1, 0),
234 SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHPL1_REG, 3, 1, 0),
235 SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHPL1_REG, 4, 1, 0),
236 SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHPL1_REG, 5, 1, 0),
237 SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHPL1_REG, 6, 1, 0),
238 SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHPL1_REG, 7, 1, 0),
239 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHPL2_REG, 0, 1, 0),
240 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHPL2_REG, 1, 1, 0),
241 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHPL2_REG, 2, 1, 0),
242 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHPL2_REG, 3, 1, 0),
243 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHPL2_REG, 4, 1, 0),
244 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHPL2_REG, 5, 1, 0),
245 SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHPL2_REG, 6, 1, 0),
246 SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHPL2_REG, 7, 1, 0),
247 SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 0, 0, 0),
248 };
249 
250 static const struct snd_kcontrol_new lm49453_headset_right_mixer[] = {
251 SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHPR1_REG, 0, 1, 0),
252 SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHPR1_REG, 1, 1, 0),
253 SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHPR1_REG, 2, 1, 0),
254 SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHPR1_REG, 3, 1, 0),
255 SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHPR1_REG, 4, 1, 0),
256 SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHPR1_REG, 5, 1, 0),
257 SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHPR1_REG, 6, 1, 0),
258 SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHPR1_REG, 7, 1, 0),
259 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHPR2_REG, 0, 1, 0),
260 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHPR2_REG, 1, 1, 0),
261 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHPR2_REG, 2, 1, 0),
262 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHPR2_REG, 3, 1, 0),
263 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHPR2_REG, 4, 1, 0),
264 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHPR2_REG, 5, 1, 0),
265 SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHPR2_REG, 6, 1, 0),
266 SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHPR2_REG, 7, 1, 0),
267 SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 1, 0, 0),
268 };
269 
270 static const struct snd_kcontrol_new lm49453_speaker_left_mixer[] = {
271 SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLSL1_REG, 0, 1, 0),
272 SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLSL1_REG, 1, 1, 0),
273 SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLSL1_REG, 2, 1, 0),
274 SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLSL1_REG, 3, 1, 0),
275 SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLSL1_REG, 4, 1, 0),
276 SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLSL1_REG, 5, 1, 0),
277 SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLSL1_REG, 6, 1, 0),
278 SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLSL1_REG, 7, 1, 0),
279 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLSL2_REG, 0, 1, 0),
280 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLSL2_REG, 1, 1, 0),
281 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLSL2_REG, 2, 1, 0),
282 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLSL2_REG, 3, 1, 0),
283 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLSL2_REG, 4, 1, 0),
284 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLSL2_REG, 5, 1, 0),
285 SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLSL2_REG, 6, 1, 0),
286 SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLSL2_REG, 7, 1, 0),
287 SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 2, 0, 0),
288 };
289 
290 static const struct snd_kcontrol_new lm49453_speaker_right_mixer[] = {
291 SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLSR1_REG, 0, 1, 0),
292 SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLSR1_REG, 1, 1, 0),
293 SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLSR1_REG, 2, 1, 0),
294 SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLSR1_REG, 3, 1, 0),
295 SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLSR1_REG, 4, 1, 0),
296 SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLSR1_REG, 5, 1, 0),
297 SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLSR1_REG, 6, 1, 0),
298 SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLSR1_REG, 7, 1, 0),
299 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLSR2_REG, 0, 1, 0),
300 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLSR2_REG, 1, 1, 0),
301 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLSR2_REG, 2, 1, 0),
302 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLSR2_REG, 3, 1, 0),
303 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLSR2_REG, 4, 1, 0),
304 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLSR2_REG, 5, 1, 0),
305 SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLSR2_REG, 6, 1, 0),
306 SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLSR2_REG, 7, 1, 0),
307 SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 3, 0, 0),
308 };
309 
310 static const struct snd_kcontrol_new lm49453_haptic_left_mixer[] = {
311 SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHAL1_REG, 0, 1, 0),
312 SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHAL1_REG, 1, 1, 0),
313 SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHAL1_REG, 2, 1, 0),
314 SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHAL1_REG, 3, 1, 0),
315 SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHAL1_REG, 4, 1, 0),
316 SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHAL1_REG, 5, 1, 0),
317 SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHAL1_REG, 6, 1, 0),
318 SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHAL1_REG, 7, 1, 0),
319 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHAL2_REG, 0, 1, 0),
320 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHAL2_REG, 1, 1, 0),
321 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHAL2_REG, 2, 1, 0),
322 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHAL2_REG, 3, 1, 0),
323 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHAL2_REG, 4, 1, 0),
324 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHAL2_REG, 5, 1, 0),
325 SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHAL2_REG, 6, 1, 0),
326 SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHAL2_REG, 7, 1, 0),
327 SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 4, 0, 0),
328 };
329 
330 static const struct snd_kcontrol_new lm49453_haptic_right_mixer[] = {
331 SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHAR1_REG, 0, 1, 0),
332 SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHAR1_REG, 1, 1, 0),
333 SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHAR1_REG, 2, 1, 0),
334 SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHAR1_REG, 3, 1, 0),
335 SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHAR1_REG, 4, 1, 0),
336 SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHAR1_REG, 5, 1, 0),
337 SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHAR1_REG, 6, 1, 0),
338 SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHAR1_REG, 7, 1, 0),
339 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHAR2_REG, 0, 1, 0),
340 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHAR2_REG, 1, 1, 0),
341 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHAR2_REG, 2, 1, 0),
342 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHAR2_REG, 3, 1, 0),
343 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHAR2_REG, 4, 1, 0),
344 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHAR2_REG, 5, 1, 0),
345 SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHAR2_REG, 6, 1, 0),
346 SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHAR2_REG, 7, 1, 0),
347 SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 5, 0, 0),
348 };
349 
350 static const struct snd_kcontrol_new lm49453_lineout_left_mixer[] = {
351 SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLOL1_REG, 0, 1, 0),
352 SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLOL1_REG, 1, 1, 0),
353 SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLOL1_REG, 2, 1, 0),
354 SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLOL1_REG, 3, 1, 0),
355 SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLOL1_REG, 4, 1, 0),
356 SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLOL1_REG, 5, 1, 0),
357 SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLOL1_REG, 6, 1, 0),
358 SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLOL1_REG, 7, 1, 0),
359 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLOL2_REG, 0, 1, 0),
360 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLOL2_REG, 1, 1, 0),
361 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLOL2_REG, 2, 1, 0),
362 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLOL2_REG, 3, 1, 0),
363 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLOL2_REG, 4, 1, 0),
364 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLOL2_REG, 5, 1, 0),
365 SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLOL2_REG, 6, 1, 0),
366 SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLOL2_REG, 7, 1, 0),
367 SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 6, 0, 0),
368 };
369 
370 static const struct snd_kcontrol_new lm49453_lineout_right_mixer[] = {
371 SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLOR1_REG, 0, 1, 0),
372 SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLOR1_REG, 1, 1, 0),
373 SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLOR1_REG, 2, 1, 0),
374 SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLOR1_REG, 3, 1, 0),
375 SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLOR1_REG, 4, 1, 0),
376 SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLOR1_REG, 5, 1, 0),
377 SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLOR1_REG, 6, 1, 0),
378 SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLOR1_REG, 7, 1, 0),
379 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLOR2_REG, 0, 1, 0),
380 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLOR2_REG, 1, 1, 0),
381 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLOR2_REG, 2, 1, 0),
382 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLOR2_REG, 3, 1, 0),
383 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLOR2_REG, 4, 1, 0),
384 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLOR2_REG, 5, 1, 0),
385 SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLOR2_REG, 6, 1, 0),
386 SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLOR2_REG, 7, 1, 0),
387 SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 7, 0, 0),
388 };
389 
390 static const struct snd_kcontrol_new lm49453_port1_tx1_mixer[] = {
391 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX1_REG, 0, 1, 0),
392 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX1_REG, 1, 1, 0),
393 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX1_REG, 2, 1, 0),
394 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX1_REG, 3, 1, 0),
395 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX1_REG, 4, 1, 0),
396 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX1_REG, 5, 1, 0),
397 SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_PORT1_TX1_REG, 6, 1, 0),
398 SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_PORT1_TX1_REG, 7, 1, 0),
399 };
400 
401 static const struct snd_kcontrol_new lm49453_port1_tx2_mixer[] = {
402 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX2_REG, 0, 1, 0),
403 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX2_REG, 1, 1, 0),
404 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX2_REG, 2, 1, 0),
405 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX2_REG, 3, 1, 0),
406 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX2_REG, 4, 1, 0),
407 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX2_REG, 5, 1, 0),
408 SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_PORT1_TX2_REG, 6, 1, 0),
409 SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_PORT1_TX2_REG, 7, 1, 0),
410 };
411 
412 static const struct snd_kcontrol_new lm49453_port1_tx3_mixer[] = {
413 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX3_REG, 0, 1, 0),
414 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX3_REG, 1, 1, 0),
415 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX3_REG, 2, 1, 0),
416 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX3_REG, 3, 1, 0),
417 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX3_REG, 4, 1, 0),
418 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX3_REG, 5, 1, 0),
419 SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_PORT1_TX3_REG, 6, 1, 0),
420 };
421 
422 static const struct snd_kcontrol_new lm49453_port1_tx4_mixer[] = {
423 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX4_REG, 0, 1, 0),
424 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX4_REG, 1, 1, 0),
425 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX4_REG, 2, 1, 0),
426 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX4_REG, 3, 1, 0),
427 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX4_REG, 4, 1, 0),
428 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX4_REG, 5, 1, 0),
429 SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_PORT1_TX4_REG, 6, 1, 0),
430 };
431 
432 static const struct snd_kcontrol_new lm49453_port1_tx5_mixer[] = {
433 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX5_REG, 0, 1, 0),
434 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX5_REG, 1, 1, 0),
435 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX5_REG, 2, 1, 0),
436 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX5_REG, 3, 1, 0),
437 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX5_REG, 4, 1, 0),
438 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX5_REG, 5, 1, 0),
439 SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_PORT1_TX5_REG, 6, 1, 0),
440 };
441 
442 static const struct snd_kcontrol_new lm49453_port1_tx6_mixer[] = {
443 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX6_REG, 0, 1, 0),
444 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX6_REG, 1, 1, 0),
445 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX6_REG, 2, 1, 0),
446 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX6_REG, 3, 1, 0),
447 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX6_REG, 4, 1, 0),
448 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX6_REG, 5, 1, 0),
449 SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_PORT1_TX6_REG, 6, 1, 0),
450 };
451 
452 static const struct snd_kcontrol_new lm49453_port1_tx7_mixer[] = {
453 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX7_REG, 0, 1, 0),
454 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX7_REG, 1, 1, 0),
455 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX7_REG, 2, 1, 0),
456 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX7_REG, 3, 1, 0),
457 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX7_REG, 4, 1, 0),
458 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX7_REG, 5, 1, 0),
459 SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_PORT1_TX7_REG, 6, 1, 0),
460 };
461 
462 static const struct snd_kcontrol_new lm49453_port1_tx8_mixer[] = {
463 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX8_REG, 0, 1, 0),
464 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX8_REG, 1, 1, 0),
465 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX8_REG, 2, 1, 0),
466 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX8_REG, 3, 1, 0),
467 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX8_REG, 4, 1, 0),
468 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX8_REG, 5, 1, 0),
469 SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_PORT1_TX8_REG, 6, 1, 0),
470 };
471 
472 static const struct snd_kcontrol_new lm49453_port2_tx1_mixer[] = {
473 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT2_TX1_REG, 0, 1, 0),
474 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT2_TX1_REG, 1, 1, 0),
475 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT2_TX1_REG, 2, 1, 0),
476 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT2_TX1_REG, 3, 1, 0),
477 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT2_TX1_REG, 4, 1, 0),
478 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT2_TX1_REG, 5, 1, 0),
479 SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_PORT2_TX1_REG, 6, 1, 0),
480 SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_PORT2_TX1_REG, 7, 1, 0),
481 };
482 
483 static const struct snd_kcontrol_new lm49453_port2_tx2_mixer[] = {
484 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT2_TX2_REG, 0, 1, 0),
485 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT2_TX2_REG, 1, 1, 0),
486 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT2_TX2_REG, 2, 1, 0),
487 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT2_TX2_REG, 3, 1, 0),
488 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT2_TX2_REG, 4, 1, 0),
489 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT2_TX2_REG, 5, 1, 0),
490 SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_PORT2_TX2_REG, 6, 1, 0),
491 SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_PORT2_TX2_REG, 7, 1, 0),
492 };
493 
494 /* TLV Declarations */
495 static const DECLARE_TLV_DB_SCALE(adc_dac_tlv, -7650, 150, 1);
496 static const DECLARE_TLV_DB_SCALE(mic_tlv, 0, 200, 1);
497 static const DECLARE_TLV_DB_SCALE(port_tlv, -1800, 600, 0);
498 static const DECLARE_TLV_DB_SCALE(stn_tlv, -7200, 150, 0);
499 
500 static const struct snd_kcontrol_new lm49453_sidetone_mixer_controls[] = {
501 /* Sidetone supports mono only */
502 SOC_DAPM_SINGLE_TLV("Sidetone ADCL Volume", LM49453_P0_STN_VOL_ADCL_REG,
503                      0, 0x3F, 0, stn_tlv),
504 SOC_DAPM_SINGLE_TLV("Sidetone ADCR Volume", LM49453_P0_STN_VOL_ADCR_REG,
505                      0, 0x3F, 0, stn_tlv),
506 SOC_DAPM_SINGLE_TLV("Sidetone DMIC1L Volume", LM49453_P0_STN_VOL_DMIC1L_REG,
507                      0, 0x3F, 0, stn_tlv),
508 SOC_DAPM_SINGLE_TLV("Sidetone DMIC1R Volume", LM49453_P0_STN_VOL_DMIC1R_REG,
509                      0, 0x3F, 0, stn_tlv),
510 SOC_DAPM_SINGLE_TLV("Sidetone DMIC2L Volume", LM49453_P0_STN_VOL_DMIC2L_REG,
511                      0, 0x3F, 0, stn_tlv),
512 SOC_DAPM_SINGLE_TLV("Sidetone DMIC2R Volume", LM49453_P0_STN_VOL_DMIC2R_REG,
513                      0, 0x3F, 0, stn_tlv),
514 };
515 
516 static const struct snd_kcontrol_new lm49453_snd_controls[] = {
517         /* mic1 and mic2 supports mono only */
518         SOC_SINGLE_TLV("Mic1 Volume", LM49453_P0_MICL_REG, 0, 15, 0, mic_tlv),
519         SOC_SINGLE_TLV("Mic2 Volume", LM49453_P0_MICR_REG, 0, 15, 0, mic_tlv),
520 
521         SOC_SINGLE_TLV("ADCL Volume", LM49453_P0_ADC_LEVELL_REG, 0, 63,
522                         0, adc_dac_tlv),
523         SOC_SINGLE_TLV("ADCR Volume", LM49453_P0_ADC_LEVELR_REG, 0, 63,
524                         0, adc_dac_tlv),
525 
526         SOC_DOUBLE_R_TLV("DMIC1 Volume", LM49453_P0_DMIC1_LEVELL_REG,
527                           LM49453_P0_DMIC1_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
528         SOC_DOUBLE_R_TLV("DMIC2 Volume", LM49453_P0_DMIC2_LEVELL_REG,
529                           LM49453_P0_DMIC2_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
530 
531         SOC_DAPM_ENUM("Mic2Mode", lm49453_mic2mode_enum),
532         SOC_DAPM_ENUM("DMIC12 SRC", lm49453_dmic12_cfg_enum),
533         SOC_DAPM_ENUM("DMIC34 SRC", lm49453_dmic34_cfg_enum),
534 
535         /* Capture path filter enable */
536         SOC_SINGLE("DMIC1 HPFilter Switch", LM49453_P0_ADC_FX_ENABLES_REG,
537                                             0, 1, 0),
538         SOC_SINGLE("DMIC2 HPFilter Switch", LM49453_P0_ADC_FX_ENABLES_REG,
539                                             1, 1, 0),
540         SOC_SINGLE("ADC HPFilter Switch", LM49453_P0_ADC_FX_ENABLES_REG,
541                                           2, 1, 0),
542 
543         SOC_DOUBLE_R_TLV("DAC HP Volume", LM49453_P0_DAC_HP_LEVELL_REG,
544                           LM49453_P0_DAC_HP_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
545         SOC_DOUBLE_R_TLV("DAC LO Volume", LM49453_P0_DAC_LO_LEVELL_REG,
546                           LM49453_P0_DAC_LO_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
547         SOC_DOUBLE_R_TLV("DAC LS Volume", LM49453_P0_DAC_LS_LEVELL_REG,
548                           LM49453_P0_DAC_LS_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
549         SOC_DOUBLE_R_TLV("DAC HA Volume", LM49453_P0_DAC_HA_LEVELL_REG,
550                           LM49453_P0_DAC_HA_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
551 
552         SOC_SINGLE_TLV("EP Volume", LM49453_P0_DAC_LS_LEVELL_REG,
553                         0, 63, 0, adc_dac_tlv),
554 
555         SOC_SINGLE_TLV("PORT1_1_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG,
556                         0, 3, 0, port_tlv),
557         SOC_SINGLE_TLV("PORT1_2_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG,
558                         2, 3, 0, port_tlv),
559         SOC_SINGLE_TLV("PORT1_3_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG,
560                         4, 3, 0, port_tlv),
561         SOC_SINGLE_TLV("PORT1_4_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG,
562                         6, 3, 0, port_tlv),
563         SOC_SINGLE_TLV("PORT1_5_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG,
564                         0, 3, 0, port_tlv),
565         SOC_SINGLE_TLV("PORT1_6_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG,
566                         2, 3, 0, port_tlv),
567         SOC_SINGLE_TLV("PORT1_7_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG,
568                         4, 3, 0, port_tlv),
569         SOC_SINGLE_TLV("PORT1_8_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG,
570                         6, 3, 0, port_tlv),
571 
572         SOC_SINGLE_TLV("PORT2_1_RX_LVL Volume", LM49453_P0_PORT2_RX_LVL_REG,
573                         0, 3, 0, port_tlv),
574         SOC_SINGLE_TLV("PORT2_2_RX_LVL Volume", LM49453_P0_PORT2_RX_LVL_REG,
575                         2, 3, 0, port_tlv),
576 
577         SOC_SINGLE("Port1 Playback Switch", LM49453_P0_AUDIO_PORT1_BASIC_REG,
578                     1, 1, 0),
579         SOC_SINGLE("Port2 Playback Switch", LM49453_P0_AUDIO_PORT2_BASIC_REG,
580                     1, 1, 0),
581         SOC_SINGLE("Port1 Capture Switch", LM49453_P0_AUDIO_PORT1_BASIC_REG,
582                     2, 1, 0),
583         SOC_SINGLE("Port2 Capture Switch", LM49453_P0_AUDIO_PORT2_BASIC_REG,
584                     2, 1, 0)
585 
586 };
587 
588 /* DAPM widgets */
589 static const struct snd_soc_dapm_widget lm49453_dapm_widgets[] = {
590 
591         /* All end points HP,EP, LS, Lineout and Haptic */
592         SND_SOC_DAPM_OUTPUT("HPOUTL"),
593         SND_SOC_DAPM_OUTPUT("HPOUTR"),
594         SND_SOC_DAPM_OUTPUT("EPOUT"),
595         SND_SOC_DAPM_OUTPUT("LSOUTL"),
596         SND_SOC_DAPM_OUTPUT("LSOUTR"),
597         SND_SOC_DAPM_OUTPUT("LOOUTR"),
598         SND_SOC_DAPM_OUTPUT("LOOUTL"),
599         SND_SOC_DAPM_OUTPUT("HAOUTL"),
600         SND_SOC_DAPM_OUTPUT("HAOUTR"),
601 
602         SND_SOC_DAPM_INPUT("AMIC1"),
603         SND_SOC_DAPM_INPUT("AMIC2"),
604         SND_SOC_DAPM_INPUT("DMIC1DAT"),
605         SND_SOC_DAPM_INPUT("DMIC2DAT"),
606         SND_SOC_DAPM_INPUT("AUXL"),
607         SND_SOC_DAPM_INPUT("AUXR"),
608 
609         SND_SOC_DAPM_PGA("PORT1_1_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
610         SND_SOC_DAPM_PGA("PORT1_2_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
611         SND_SOC_DAPM_PGA("PORT1_3_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
612         SND_SOC_DAPM_PGA("PORT1_4_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
613         SND_SOC_DAPM_PGA("PORT1_5_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
614         SND_SOC_DAPM_PGA("PORT1_6_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
615         SND_SOC_DAPM_PGA("PORT1_7_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
616         SND_SOC_DAPM_PGA("PORT1_8_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
617         SND_SOC_DAPM_PGA("PORT2_1_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
618         SND_SOC_DAPM_PGA("PORT2_2_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
619 
620         SND_SOC_DAPM_SUPPLY("AMIC1Bias", LM49453_P0_MICL_REG, 6, 0, NULL, 0),
621         SND_SOC_DAPM_SUPPLY("AMIC2Bias", LM49453_P0_MICR_REG, 6, 0, NULL, 0),
622 
623         /* playback path driver enables */
624         SND_SOC_DAPM_OUT_DRV("Headset Switch",
625                         LM49453_P0_PMC_SETUP_REG, 0, 0, NULL, 0),
626         SND_SOC_DAPM_OUT_DRV("Earpiece Switch",
627                         LM49453_P0_EP_REG, 0, 0, NULL, 0),
628         SND_SOC_DAPM_OUT_DRV("Speaker Left Switch",
629                         LM49453_P0_DIS_PKVL_FB_REG, 0, 1, NULL, 0),
630         SND_SOC_DAPM_OUT_DRV("Speaker Right Switch",
631                         LM49453_P0_DIS_PKVL_FB_REG, 1, 1, NULL, 0),
632         SND_SOC_DAPM_OUT_DRV("Haptic Left Switch",
633                         LM49453_P0_DIS_PKVL_FB_REG, 2, 1, NULL, 0),
634         SND_SOC_DAPM_OUT_DRV("Haptic Right Switch",
635                         LM49453_P0_DIS_PKVL_FB_REG, 3, 1, NULL, 0),
636 
637         /* DAC */
638         SND_SOC_DAPM_DAC("HPL DAC", "Headset", SND_SOC_NOPM, 0, 0),
639         SND_SOC_DAPM_DAC("HPR DAC", "Headset", SND_SOC_NOPM, 0, 0),
640         SND_SOC_DAPM_DAC("LSL DAC", "Speaker", SND_SOC_NOPM, 0, 0),
641         SND_SOC_DAPM_DAC("LSR DAC", "Speaker", SND_SOC_NOPM, 0, 0),
642         SND_SOC_DAPM_DAC("HAL DAC", "Haptic", SND_SOC_NOPM, 0, 0),
643         SND_SOC_DAPM_DAC("HAR DAC", "Haptic", SND_SOC_NOPM, 0, 0),
644         SND_SOC_DAPM_DAC("LOL DAC", "Lineout", SND_SOC_NOPM, 0, 0),
645         SND_SOC_DAPM_DAC("LOR DAC", "Lineout", SND_SOC_NOPM, 0, 0),
646 
647 
648         SND_SOC_DAPM_PGA("AUXL Input",
649                         LM49453_P0_ANALOG_MIXER_ADC_REG, 2, 0, NULL, 0),
650         SND_SOC_DAPM_PGA("AUXR Input",
651                         LM49453_P0_ANALOG_MIXER_ADC_REG, 3, 0, NULL, 0),
652 
653         SND_SOC_DAPM_PGA("Sidetone", SND_SOC_NOPM, 0, 0, NULL, 0),
654 
655         /* ADC */
656         SND_SOC_DAPM_ADC("DMIC1 Left", "Capture", SND_SOC_NOPM, 1, 0),
657         SND_SOC_DAPM_ADC("DMIC1 Right", "Capture", SND_SOC_NOPM, 1, 0),
658         SND_SOC_DAPM_ADC("DMIC2 Left", "Capture", SND_SOC_NOPM, 1, 0),
659         SND_SOC_DAPM_ADC("DMIC2 Right", "Capture", SND_SOC_NOPM, 1, 0),
660 
661         SND_SOC_DAPM_ADC("ADC Left", "Capture", SND_SOC_NOPM, 1, 0),
662         SND_SOC_DAPM_ADC("ADC Right", "Capture", SND_SOC_NOPM, 0, 0),
663 
664         SND_SOC_DAPM_MUX("ADCL Mux", SND_SOC_NOPM, 0, 0,
665                           &lm49453_adcl_mux_control),
666         SND_SOC_DAPM_MUX("ADCR Mux", SND_SOC_NOPM, 0, 0,
667                           &lm49453_adcr_mux_control),
668 
669         SND_SOC_DAPM_MUX("Mic1 Input",
670                         SND_SOC_NOPM, 0, 0, &lm49453_adcl_mux_control),
671 
672         SND_SOC_DAPM_MUX("Mic2 Input",
673                         SND_SOC_NOPM, 0, 0, &lm49453_adcr_mux_control),
674 
675         /* AIF */
676         SND_SOC_DAPM_AIF_IN("PORT1_SDI", NULL, 0,
677                             LM49453_P0_PULL_CONFIG1_REG, 2, 0),
678         SND_SOC_DAPM_AIF_IN("PORT2_SDI", NULL, 0,
679                             LM49453_P0_PULL_CONFIG1_REG, 6, 0),
680 
681         SND_SOC_DAPM_AIF_OUT("PORT1_SDO", NULL, 0,
682                              LM49453_P0_PULL_CONFIG1_REG, 3, 0),
683         SND_SOC_DAPM_AIF_OUT("PORT2_SDO", NULL, 0,
684                               LM49453_P0_PULL_CONFIG1_REG, 7, 0),
685 
686         /* Port1 TX controls */
687         SND_SOC_DAPM_OUT_DRV("P1_1_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
688         SND_SOC_DAPM_OUT_DRV("P1_2_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
689         SND_SOC_DAPM_OUT_DRV("P1_3_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
690         SND_SOC_DAPM_OUT_DRV("P1_4_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
691         SND_SOC_DAPM_OUT_DRV("P1_5_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
692         SND_SOC_DAPM_OUT_DRV("P1_6_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
693         SND_SOC_DAPM_OUT_DRV("P1_7_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
694         SND_SOC_DAPM_OUT_DRV("P1_8_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
695 
696         /* Port2 TX controls */
697         SND_SOC_DAPM_OUT_DRV("P2_1_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
698         SND_SOC_DAPM_OUT_DRV("P2_2_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
699 
700         /* Sidetone Mixer */
701         SND_SOC_DAPM_MIXER("Sidetone Mixer", SND_SOC_NOPM, 0, 0,
702                             lm49453_sidetone_mixer_controls,
703                             ARRAY_SIZE(lm49453_sidetone_mixer_controls)),
704 
705         /* DAC MIXERS */
706         SND_SOC_DAPM_MIXER("HPL Mixer", SND_SOC_NOPM, 0, 0,
707                             lm49453_headset_left_mixer,
708                             ARRAY_SIZE(lm49453_headset_left_mixer)),
709         SND_SOC_DAPM_MIXER("HPR Mixer", SND_SOC_NOPM, 0, 0,
710                             lm49453_headset_right_mixer,
711                             ARRAY_SIZE(lm49453_headset_right_mixer)),
712         SND_SOC_DAPM_MIXER("LOL Mixer", SND_SOC_NOPM, 0, 0,
713                             lm49453_lineout_left_mixer,
714                             ARRAY_SIZE(lm49453_lineout_left_mixer)),
715         SND_SOC_DAPM_MIXER("LOR Mixer", SND_SOC_NOPM, 0, 0,
716                             lm49453_lineout_right_mixer,
717                             ARRAY_SIZE(lm49453_lineout_right_mixer)),
718         SND_SOC_DAPM_MIXER("LSL Mixer", SND_SOC_NOPM, 0, 0,
719                             lm49453_speaker_left_mixer,
720                             ARRAY_SIZE(lm49453_speaker_left_mixer)),
721         SND_SOC_DAPM_MIXER("LSR Mixer", SND_SOC_NOPM, 0, 0,
722                             lm49453_speaker_right_mixer,
723                             ARRAY_SIZE(lm49453_speaker_right_mixer)),
724         SND_SOC_DAPM_MIXER("HAL Mixer", SND_SOC_NOPM, 0, 0,
725                             lm49453_haptic_left_mixer,
726                             ARRAY_SIZE(lm49453_haptic_left_mixer)),
727         SND_SOC_DAPM_MIXER("HAR Mixer", SND_SOC_NOPM, 0, 0,
728                             lm49453_haptic_right_mixer,
729                             ARRAY_SIZE(lm49453_haptic_right_mixer)),
730 
731         /* Capture Mixer */
732         SND_SOC_DAPM_MIXER("Port1_1 Mixer", SND_SOC_NOPM, 0, 0,
733                             lm49453_port1_tx1_mixer,
734                             ARRAY_SIZE(lm49453_port1_tx1_mixer)),
735         SND_SOC_DAPM_MIXER("Port1_2 Mixer", SND_SOC_NOPM, 0, 0,
736                             lm49453_port1_tx2_mixer,
737                             ARRAY_SIZE(lm49453_port1_tx2_mixer)),
738         SND_SOC_DAPM_MIXER("Port1_3 Mixer", SND_SOC_NOPM, 0, 0,
739                             lm49453_port1_tx3_mixer,
740                             ARRAY_SIZE(lm49453_port1_tx3_mixer)),
741         SND_SOC_DAPM_MIXER("Port1_4 Mixer", SND_SOC_NOPM, 0, 0,
742                             lm49453_port1_tx4_mixer,
743                             ARRAY_SIZE(lm49453_port1_tx4_mixer)),
744         SND_SOC_DAPM_MIXER("Port1_5 Mixer", SND_SOC_NOPM, 0, 0,
745                             lm49453_port1_tx5_mixer,
746                             ARRAY_SIZE(lm49453_port1_tx5_mixer)),
747         SND_SOC_DAPM_MIXER("Port1_6 Mixer", SND_SOC_NOPM, 0, 0,
748                             lm49453_port1_tx6_mixer,
749                             ARRAY_SIZE(lm49453_port1_tx6_mixer)),
750         SND_SOC_DAPM_MIXER("Port1_7 Mixer", SND_SOC_NOPM, 0, 0,
751                             lm49453_port1_tx7_mixer,
752                             ARRAY_SIZE(lm49453_port1_tx7_mixer)),
753         SND_SOC_DAPM_MIXER("Port1_8 Mixer", SND_SOC_NOPM, 0, 0,
754                             lm49453_port1_tx8_mixer,
755                             ARRAY_SIZE(lm49453_port1_tx8_mixer)),
756 
757         SND_SOC_DAPM_MIXER("Port2_1 Mixer", SND_SOC_NOPM, 0, 0,
758                             lm49453_port2_tx1_mixer,
759                             ARRAY_SIZE(lm49453_port2_tx1_mixer)),
760         SND_SOC_DAPM_MIXER("Port2_2 Mixer", SND_SOC_NOPM, 0, 0,
761                             lm49453_port2_tx2_mixer,
762                             ARRAY_SIZE(lm49453_port2_tx2_mixer)),
763 };
764 
765 static const struct snd_soc_dapm_route lm49453_audio_map[] = {
766         /* Port SDI mapping */
767         { "PORT1_1_RX", "Port1 Playback Switch", "PORT1_SDI" },
768         { "PORT1_2_RX", "Port1 Playback Switch", "PORT1_SDI" },
769         { "PORT1_3_RX", "Port1 Playback Switch", "PORT1_SDI" },
770         { "PORT1_4_RX", "Port1 Playback Switch", "PORT1_SDI" },
771         { "PORT1_5_RX", "Port1 Playback Switch", "PORT1_SDI" },
772         { "PORT1_6_RX", "Port1 Playback Switch", "PORT1_SDI" },
773         { "PORT1_7_RX", "Port1 Playback Switch", "PORT1_SDI" },
774         { "PORT1_8_RX", "Port1 Playback Switch", "PORT1_SDI" },
775 
776         { "PORT2_1_RX", "Port2 Playback Switch", "PORT2_SDI" },
777         { "PORT2_2_RX", "Port2 Playback Switch", "PORT2_SDI" },
778 
779         /* HP mapping */
780         { "HPL Mixer", "Port1_1 Switch", "PORT1_1_RX" },
781         { "HPL Mixer", "Port1_2 Switch", "PORT1_2_RX" },
782         { "HPL Mixer", "Port1_3 Switch", "PORT1_3_RX" },
783         { "HPL Mixer", "Port1_4 Switch", "PORT1_4_RX" },
784         { "HPL Mixer", "Port1_5 Switch", "PORT1_5_RX" },
785         { "HPL Mixer", "Port1_6 Switch", "PORT1_6_RX" },
786         { "HPL Mixer", "Port1_7 Switch", "PORT1_7_RX" },
787         { "HPL Mixer", "Port1_8 Switch", "PORT1_8_RX" },
788 
789         { "HPL Mixer", "Port2_1 Switch", "PORT2_1_RX" },
790         { "HPL Mixer", "Port2_2 Switch", "PORT2_2_RX" },
791 
792         { "HPL Mixer", "ADCL Switch", "ADC Left" },
793         { "HPL Mixer", "ADCR Switch", "ADC Right" },
794         { "HPL Mixer", "DMIC1L Switch", "DMIC1 Left" },
795         { "HPL Mixer", "DMIC1R Switch", "DMIC1 Right" },
796         { "HPL Mixer", "DMIC2L Switch", "DMIC2 Left" },
797         { "HPL Mixer", "DMIC2R Switch", "DMIC2 Right" },
798         { "HPL Mixer", "Sidetone Switch", "Sidetone" },
799 
800         { "HPL DAC", NULL, "HPL Mixer" },
801 
802         { "HPR Mixer", "Port1_1 Switch", "PORT1_1_RX" },
803         { "HPR Mixer", "Port1_2 Switch", "PORT1_2_RX" },
804         { "HPR Mixer", "Port1_3 Switch", "PORT1_3_RX" },
805         { "HPR Mixer", "Port1_4 Switch", "PORT1_4_RX" },
806         { "HPR Mixer", "Port1_5 Switch", "PORT1_5_RX" },
807         { "HPR Mixer", "Port1_6 Switch", "PORT1_6_RX" },
808         { "HPR Mixer", "Port1_7 Switch", "PORT1_7_RX" },
809         { "HPR Mixer", "Port1_8 Switch", "PORT1_8_RX" },
810 
811         /* Port 2 */
812         { "HPR Mixer", "Port2_1 Switch", "PORT2_1_RX" },
813         { "HPR Mixer", "Port2_2 Switch", "PORT2_2_RX" },
814 
815         { "HPR Mixer", "ADCL Switch", "ADC Left" },
816         { "HPR Mixer", "ADCR Switch", "ADC Right" },
817         { "HPR Mixer", "DMIC1L Switch", "DMIC1 Left" },
818         { "HPR Mixer", "DMIC1R Switch", "DMIC1 Right" },
819         { "HPR Mixer", "DMIC2L Switch", "DMIC2 Left" },
820         { "HPR Mixer", "DMIC2L Switch", "DMIC2 Right" },
821         { "HPR Mixer", "Sidetone Switch", "Sidetone" },
822 
823         { "HPR DAC", NULL, "HPR Mixer" },
824 
825         { "HPOUTL", "Headset Switch", "HPL DAC"},
826         { "HPOUTR", "Headset Switch", "HPR DAC"},
827 
828         /* EP map */
829         { "EPOUT", "Earpiece Switch", "HPL DAC" },
830 
831         /* Speaker map */
832         { "LSL Mixer", "Port1_1 Switch", "PORT1_1_RX" },
833         { "LSL Mixer", "Port1_2 Switch", "PORT1_2_RX" },
834         { "LSL Mixer", "Port1_3 Switch", "PORT1_3_RX" },
835         { "LSL Mixer", "Port1_4 Switch", "PORT1_4_RX" },
836         { "LSL Mixer", "Port1_5 Switch", "PORT1_5_RX" },
837         { "LSL Mixer", "Port1_6 Switch", "PORT1_6_RX" },
838         { "LSL Mixer", "Port1_7 Switch", "PORT1_7_RX" },
839         { "LSL Mixer", "Port1_8 Switch", "PORT1_8_RX" },
840 
841         /* Port 2 */
842         { "LSL Mixer", "Port2_1 Switch", "PORT2_1_RX" },
843         { "LSL Mixer", "Port2_2 Switch", "PORT2_2_RX" },
844 
845         { "LSL Mixer", "ADCL Switch", "ADC Left" },
846         { "LSL Mixer", "ADCR Switch", "ADC Right" },
847         { "LSL Mixer", "DMIC1L Switch", "DMIC1 Left" },
848         { "LSL Mixer", "DMIC1R Switch", "DMIC1 Right" },
849         { "LSL Mixer", "DMIC2L Switch", "DMIC2 Left" },
850         { "LSL Mixer", "DMIC2R Switch", "DMIC2 Right" },
851         { "LSL Mixer", "Sidetone Switch", "Sidetone" },
852 
853         { "LSL DAC", NULL, "LSL Mixer" },
854 
855         { "LSR Mixer", "Port1_1 Switch", "PORT1_1_RX" },
856         { "LSR Mixer", "Port1_2 Switch", "PORT1_2_RX" },
857         { "LSR Mixer", "Port1_3 Switch", "PORT1_3_RX" },
858         { "LSR Mixer", "Port1_4 Switch", "PORT1_4_RX" },
859         { "LSR Mixer", "Port1_5 Switch", "PORT1_5_RX" },
860         { "LSR Mixer", "Port1_6 Switch", "PORT1_6_RX" },
861         { "LSR Mixer", "Port1_7 Switch", "PORT1_7_RX" },
862         { "LSR Mixer", "Port1_8 Switch", "PORT1_8_RX" },
863 
864         /* Port 2 */
865         { "LSR Mixer", "Port2_1 Switch", "PORT2_1_RX" },
866         { "LSR Mixer", "Port2_2 Switch", "PORT2_2_RX" },
867 
868         { "LSR Mixer", "ADCL Switch", "ADC Left" },
869         { "LSR Mixer", "ADCR Switch", "ADC Right" },
870         { "LSR Mixer", "DMIC1L Switch", "DMIC1 Left" },
871         { "LSR Mixer", "DMIC1R Switch", "DMIC1 Right" },
872         { "LSR Mixer", "DMIC2L Switch", "DMIC2 Left" },
873         { "LSR Mixer", "DMIC2R Switch", "DMIC2 Right" },
874         { "LSR Mixer", "Sidetone Switch", "Sidetone" },
875 
876         { "LSR DAC", NULL, "LSR Mixer" },
877 
878         { "LSOUTL", "Speaker Left Switch", "LSL DAC"},
879         { "LSOUTR", "Speaker Left Switch", "LSR DAC"},
880 
881         /* Haptic map */
882         { "HAL Mixer", "Port1_1 Switch", "PORT1_1_RX" },
883         { "HAL Mixer", "Port1_2 Switch", "PORT1_2_RX" },
884         { "HAL Mixer", "Port1_3 Switch", "PORT1_3_RX" },
885         { "HAL Mixer", "Port1_4 Switch", "PORT1_4_RX" },
886         { "HAL Mixer", "Port1_5 Switch", "PORT1_5_RX" },
887         { "HAL Mixer", "Port1_6 Switch", "PORT1_6_RX" },
888         { "HAL Mixer", "Port1_7 Switch", "PORT1_7_RX" },
889         { "HAL Mixer", "Port1_8 Switch", "PORT1_8_RX" },
890 
891         /* Port 2 */
892         { "HAL Mixer", "Port2_1 Switch", "PORT2_1_RX" },
893         { "HAL Mixer", "Port2_2 Switch", "PORT2_2_RX" },
894 
895         { "HAL Mixer", "ADCL Switch", "ADC Left" },
896         { "HAL Mixer", "ADCR Switch", "ADC Right" },
897         { "HAL Mixer", "DMIC1L Switch", "DMIC1 Left" },
898         { "HAL Mixer", "DMIC1R Switch", "DMIC1 Right" },
899         { "HAL Mixer", "DMIC2L Switch", "DMIC2 Left" },
900         { "HAL Mixer", "DMIC2R Switch", "DMIC2 Right" },
901         { "HAL Mixer", "Sidetone Switch", "Sidetone" },
902 
903         { "HAL DAC", NULL, "HAL Mixer" },
904 
905         { "HAR Mixer", "Port1_1 Switch", "PORT1_1_RX" },
906         { "HAR Mixer", "Port1_2 Switch", "PORT1_2_RX" },
907         { "HAR Mixer", "Port1_3 Switch", "PORT1_3_RX" },
908         { "HAR Mixer", "Port1_4 Switch", "PORT1_4_RX" },
909         { "HAR Mixer", "Port1_5 Switch", "PORT1_5_RX" },
910         { "HAR Mixer", "Port1_6 Switch", "PORT1_6_RX" },
911         { "HAR Mixer", "Port1_7 Switch", "PORT1_7_RX" },
912         { "HAR Mixer", "Port1_8 Switch", "PORT1_8_RX" },
913 
914         /* Port 2 */
915         { "HAR Mixer", "Port2_1 Switch", "PORT2_1_RX" },
916         { "HAR Mixer", "Port2_2 Switch", "PORT2_2_RX" },
917 
918         { "HAR Mixer", "ADCL Switch", "ADC Left" },
919         { "HAR Mixer", "ADCR Switch", "ADC Right" },
920         { "HAR Mixer", "DMIC1L Switch", "DMIC1 Left" },
921         { "HAR Mixer", "DMIC1R Switch", "DMIC1 Right" },
922         { "HAR Mixer", "DMIC2L Switch", "DMIC2 Left" },
923         { "HAR Mixer", "DMIC2R Switch", "DMIC2 Right" },
924         { "HAR Mixer", "Sideton Switch", "Sidetone" },
925 
926         { "HAR DAC", NULL, "HAR Mixer" },
927 
928         { "HAOUTL", "Haptic Left Switch", "HAL DAC" },
929         { "HAOUTR", "Haptic Right Switch", "HAR DAC" },
930 
931         /* Lineout map */
932         { "LOL Mixer", "Port1_1 Switch", "PORT1_1_RX" },
933         { "LOL Mixer", "Port1_2 Switch", "PORT1_2_RX" },
934         { "LOL Mixer", "Port1_3 Switch", "PORT1_3_RX" },
935         { "LOL Mixer", "Port1_4 Switch", "PORT1_4_RX" },
936         { "LOL Mixer", "Port1_5 Switch", "PORT1_5_RX" },
937         { "LOL Mixer", "Port1_6 Switch", "PORT1_6_RX" },
938         { "LOL Mixer", "Port1_7 Switch", "PORT1_7_RX" },
939         { "LOL Mixer", "Port1_8 Switch", "PORT1_8_RX" },
940 
941         /* Port 2 */
942         { "LOL Mixer", "Port2_1 Switch", "PORT2_1_RX" },
943         { "LOL Mixer", "Port2_2 Switch", "PORT2_2_RX" },
944 
945         { "LOL Mixer", "ADCL Switch", "ADC Left" },
946         { "LOL Mixer", "ADCR Switch", "ADC Right" },
947         { "LOL Mixer", "DMIC1L Switch", "DMIC1 Left" },
948         { "LOL Mixer", "DMIC1R Switch", "DMIC1 Right" },
949         { "LOL Mixer", "DMIC2L Switch", "DMIC2 Left" },
950         { "LOL Mixer", "DMIC2R Switch", "DMIC2 Right" },
951         { "LOL Mixer", "Sidetone Switch", "Sidetone" },
952 
953         { "LOL DAC", NULL, "LOL Mixer" },
954 
955         { "LOR Mixer", "Port1_1 Switch", "PORT1_1_RX" },
956         { "LOR Mixer", "Port1_2 Switch", "PORT1_2_RX" },
957         { "LOR Mixer", "Port1_3 Switch", "PORT1_3_RX" },
958         { "LOR Mixer", "Port1_4 Switch", "PORT1_4_RX" },
959         { "LOR Mixer", "Port1_5 Switch", "PORT1_5_RX" },
960         { "LOR Mixer", "Port1_6 Switch", "PORT1_6_RX" },
961         { "LOR Mixer", "Port1_7 Switch", "PORT1_7_RX" },
962         { "LOR Mixer", "Port1_8 Switch", "PORT1_8_RX" },
963 
964         /* Port 2 */
965         { "LOR Mixer", "Port2_1 Switch", "PORT2_1_RX" },
966         { "LOR Mixer", "Port2_2 Switch", "PORT2_2_RX" },
967 
968         { "LOR Mixer", "ADCL Switch", "ADC Left" },
969         { "LOR Mixer", "ADCR Switch", "ADC Right" },
970         { "LOR Mixer", "DMIC1L Switch", "DMIC1 Left" },
971         { "LOR Mixer", "DMIC1R Switch", "DMIC1 Right" },
972         { "LOR Mixer", "DMIC2L Switch", "DMIC2 Left" },
973         { "LOR Mixer", "DMIC2R Switch", "DMIC2 Right" },
974         { "LOR Mixer", "Sidetone Switch", "Sidetone" },
975 
976         { "LOR DAC", NULL, "LOR Mixer" },
977 
978         { "LOOUTL", NULL, "LOL DAC" },
979         { "LOOUTR", NULL, "LOR DAC" },
980 
981         /* TX map */
982         /* Port1 mappings */
983         { "Port1_1 Mixer", "ADCL Switch", "ADC Left" },
984         { "Port1_1 Mixer", "ADCR Switch", "ADC Right" },
985         { "Port1_1 Mixer", "DMIC1L Switch", "DMIC1 Left" },
986         { "Port1_1 Mixer", "DMIC1R Switch", "DMIC1 Right" },
987         { "Port1_1 Mixer", "DMIC2L Switch", "DMIC2 Left" },
988         { "Port1_1 Mixer", "DMIC2R Switch", "DMIC2 Right" },
989 
990         { "Port1_2 Mixer", "ADCL Switch", "ADC Left" },
991         { "Port1_2 Mixer", "ADCR Switch", "ADC Right" },
992         { "Port1_2 Mixer", "DMIC1L Switch", "DMIC1 Left" },
993         { "Port1_2 Mixer", "DMIC1R Switch", "DMIC1 Right" },
994         { "Port1_2 Mixer", "DMIC2L Switch", "DMIC2 Left" },
995         { "Port1_2 Mixer", "DMIC2R Switch", "DMIC2 Right" },
996 
997         { "Port1_3 Mixer", "ADCL Switch", "ADC Left" },
998         { "Port1_3 Mixer", "ADCR Switch", "ADC Right" },
999         { "Port1_3 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1000         { "Port1_3 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1001         { "Port1_3 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1002         { "Port1_3 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1003 
1004         { "Port1_4 Mixer", "ADCL Switch", "ADC Left" },
1005         { "Port1_4 Mixer", "ADCR Switch", "ADC Right" },
1006         { "Port1_4 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1007         { "Port1_4 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1008         { "Port1_4 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1009         { "Port1_4 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1010 
1011         { "Port1_5 Mixer", "ADCL Switch", "ADC Left" },
1012         { "Port1_5 Mixer", "ADCR Switch", "ADC Right" },
1013         { "Port1_5 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1014         { "Port1_5 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1015         { "Port1_5 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1016         { "Port1_5 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1017 
1018         { "Port1_6 Mixer", "ADCL Switch", "ADC Left" },
1019         { "Port1_6 Mixer", "ADCR Switch", "ADC Right" },
1020         { "Port1_6 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1021         { "Port1_6 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1022         { "Port1_6 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1023         { "Port1_6 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1024 
1025         { "Port1_7 Mixer", "ADCL Switch", "ADC Left" },
1026         { "Port1_7 Mixer", "ADCR Switch", "ADC Right" },
1027         { "Port1_7 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1028         { "Port1_7 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1029         { "Port1_7 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1030         { "Port1_7 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1031 
1032         { "Port1_8 Mixer", "ADCL Switch", "ADC Left" },
1033         { "Port1_8 Mixer", "ADCR Switch", "ADC Right" },
1034         { "Port1_8 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1035         { "Port1_8 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1036         { "Port1_8 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1037         { "Port1_8 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1038 
1039         { "Port2_1 Mixer", "ADCL Switch", "ADC Left" },
1040         { "Port2_1 Mixer", "ADCR Switch", "ADC Right" },
1041         { "Port2_1 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1042         { "Port2_1 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1043         { "Port2_1 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1044         { "Port2_1 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1045 
1046         { "Port2_2 Mixer", "ADCL Switch", "ADC Left" },
1047         { "Port2_2 Mixer", "ADCR Switch", "ADC Right" },
1048         { "Port2_2 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1049         { "Port2_2 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1050         { "Port2_2 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1051         { "Port2_2 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1052 
1053         { "P1_1_TX", NULL, "Port1_1 Mixer" },
1054         { "P1_2_TX", NULL, "Port1_2 Mixer" },
1055         { "P1_3_TX", NULL, "Port1_3 Mixer" },
1056         { "P1_4_TX", NULL, "Port1_4 Mixer" },
1057         { "P1_5_TX", NULL, "Port1_5 Mixer" },
1058         { "P1_6_TX", NULL, "Port1_6 Mixer" },
1059         { "P1_7_TX", NULL, "Port1_7 Mixer" },
1060         { "P1_8_TX", NULL, "Port1_8 Mixer" },
1061 
1062         { "P2_1_TX", NULL, "Port2_1 Mixer" },
1063         { "P2_2_TX", NULL, "Port2_2 Mixer" },
1064 
1065         { "PORT1_SDO", "Port1 Capture Switch", "P1_1_TX"},
1066         { "PORT1_SDO", "Port1 Capture Switch", "P1_2_TX"},
1067         { "PORT1_SDO", "Port1 Capture Switch", "P1_3_TX"},
1068         { "PORT1_SDO", "Port1 Capture Switch", "P1_4_TX"},
1069         { "PORT1_SDO", "Port1 Capture Switch", "P1_5_TX"},
1070         { "PORT1_SDO", "Port1 Capture Switch", "P1_6_TX"},
1071         { "PORT1_SDO", "Port1 Capture Switch", "P1_7_TX"},
1072         { "PORT1_SDO", "Port1 Capture Switch", "P1_8_TX"},
1073 
1074         { "PORT2_SDO", "Port2 Capture Switch", "P2_1_TX"},
1075         { "PORT2_SDO", "Port2 Capture Switch", "P2_2_TX"},
1076 
1077         { "Mic1 Input", NULL, "AMIC1" },
1078         { "Mic2 Input", NULL, "AMIC2" },
1079 
1080         { "AUXL Input", NULL, "AUXL" },
1081         { "AUXR Input", NULL, "AUXR" },
1082 
1083         /* AUX connections */
1084         { "ADCL Mux", "Aux_L", "AUXL Input" },
1085         { "ADCL Mux", "MIC1", "Mic1 Input" },
1086 
1087         { "ADCR Mux", "Aux_R", "AUXR Input" },
1088         { "ADCR Mux", "MIC2", "Mic2 Input" },
1089 
1090         /* ADC connection */
1091         { "ADC Left", NULL, "ADCL Mux"},
1092         { "ADC Right", NULL, "ADCR Mux"},
1093 
1094         { "DMIC1 Left", NULL, "DMIC1DAT"},
1095         { "DMIC1 Right", NULL, "DMIC1DAT"},
1096         { "DMIC2 Left", NULL, "DMIC2DAT"},
1097         { "DMIC2 Right", NULL, "DMIC2DAT"},
1098 
1099         /* Sidetone map */
1100         { "Sidetone Mixer", NULL, "ADC Left" },
1101         { "Sidetone Mixer", NULL, "ADC Right" },
1102         { "Sidetone Mixer", NULL, "DMIC1 Left" },
1103         { "Sidetone Mixer", NULL, "DMIC1 Right" },
1104         { "Sidetone Mixer", NULL, "DMIC2 Left" },
1105         { "Sidetone Mixer", NULL, "DMIC2 Right" },
1106 
1107         { "Sidetone", "Sidetone Switch", "Sidetone Mixer" },
1108 };
1109 
1110 static int lm49453_hw_params(struct snd_pcm_substream *substream,
1111                              struct snd_pcm_hw_params *params,
1112                              struct snd_soc_dai *dai)
1113 {
1114         struct snd_soc_codec *codec = dai->codec;
1115         struct lm49453_priv *lm49453 = snd_soc_codec_get_drvdata(codec);
1116         u16 clk_div = 0;
1117 
1118         lm49453->fs_rate = params_rate(params);
1119 
1120         /* Setting DAC clock dividers based on substream sample rate. */
1121         switch (lm49453->fs_rate) {
1122         case 8000:
1123         case 16000:
1124         case 32000:
1125         case 24000:
1126         case 48000:
1127                 clk_div = 256;
1128                 break;
1129         case 11025:
1130         case 22050:
1131         case 44100:
1132                 clk_div = 216;
1133                 break;
1134         case 96000:
1135                 clk_div = 127;
1136                 break;
1137         default:
1138                 return -EINVAL;
1139         }
1140 
1141         snd_soc_write(codec, LM49453_P0_ADC_CLK_DIV_REG, clk_div);
1142         snd_soc_write(codec, LM49453_P0_DAC_HP_CLK_DIV_REG, clk_div);
1143 
1144         return 0;
1145 }
1146 
1147 static int lm49453_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
1148 {
1149         struct snd_soc_codec *codec = codec_dai->codec;
1150 
1151         u16 aif_val;
1152         int mode = 0;
1153         int clk_phase = 0;
1154         int clk_shift = 0;
1155 
1156         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1157         case SND_SOC_DAIFMT_CBS_CFS:
1158                 aif_val = 0;
1159                 break;
1160         case SND_SOC_DAIFMT_CBS_CFM:
1161                 aif_val = LM49453_AUDIO_PORT1_BASIC_SYNC_MS;
1162                 break;
1163         case SND_SOC_DAIFMT_CBM_CFS:
1164                 aif_val = LM49453_AUDIO_PORT1_BASIC_CLK_MS;
1165                 break;
1166         case SND_SOC_DAIFMT_CBM_CFM:
1167                 aif_val = LM49453_AUDIO_PORT1_BASIC_CLK_MS |
1168                           LM49453_AUDIO_PORT1_BASIC_SYNC_MS;
1169                 break;
1170         default:
1171                 return -EINVAL;
1172         }
1173 
1174 
1175         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1176         case SND_SOC_DAIFMT_I2S:
1177                 break;
1178         case SND_SOC_DAIFMT_DSP_A:
1179                 mode = 1;
1180                 clk_phase = (1 << 5);
1181                 clk_shift = 1;
1182                 break;
1183         case SND_SOC_DAIFMT_DSP_B:
1184                 mode = 1;
1185                 clk_phase = (1 << 5);
1186                 clk_shift = 0;
1187                 break;
1188         default:
1189                 return -EINVAL;
1190         }
1191 
1192         snd_soc_update_bits(codec, LM49453_P0_AUDIO_PORT1_BASIC_REG,
1193                             LM49453_AUDIO_PORT1_BASIC_FMT_MASK|BIT(0)|BIT(5),
1194                             (aif_val | mode | clk_phase));
1195 
1196         snd_soc_write(codec, LM49453_P0_AUDIO_PORT1_RX_MSB_REG, clk_shift);
1197 
1198         return 0;
1199 }
1200 
1201 static int lm49453_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
1202                                   unsigned int freq, int dir)
1203 {
1204         struct snd_soc_codec *codec = dai->codec;
1205         u16 pll_clk = 0;
1206 
1207         switch (freq) {
1208         case 12288000:
1209         case 26000000:
1210         case 19200000:
1211                 /* pll clk slection */
1212                 pll_clk = 0;
1213                 break;
1214         case 48000:
1215         case 32576:
1216                 /* fll clk slection */
1217                 pll_clk = BIT(4);
1218                 return 0;
1219         default:
1220                 return -EINVAL;
1221         }
1222 
1223         snd_soc_update_bits(codec, LM49453_P0_PMC_SETUP_REG, BIT(4), pll_clk);
1224 
1225         return 0;
1226 }
1227 
1228 static int lm49453_hp_mute(struct snd_soc_dai *dai, int mute)
1229 {
1230         snd_soc_update_bits(dai->codec, LM49453_P0_DAC_DSP_REG, BIT(1)|BIT(0),
1231                             (mute ? (BIT(1)|BIT(0)) : 0));
1232         return 0;
1233 }
1234 
1235 static int lm49453_lo_mute(struct snd_soc_dai *dai, int mute)
1236 {
1237         snd_soc_update_bits(dai->codec, LM49453_P0_DAC_DSP_REG, BIT(3)|BIT(2),
1238                             (mute ? (BIT(3)|BIT(2)) : 0));
1239         return 0;
1240 }
1241 
1242 static int lm49453_ls_mute(struct snd_soc_dai *dai, int mute)
1243 {
1244         snd_soc_update_bits(dai->codec, LM49453_P0_DAC_DSP_REG, BIT(5)|BIT(4),
1245                             (mute ? (BIT(5)|BIT(4)) : 0));
1246         return 0;
1247 }
1248 
1249 static int lm49453_ep_mute(struct snd_soc_dai *dai, int mute)
1250 {
1251         snd_soc_update_bits(dai->codec, LM49453_P0_DAC_DSP_REG, BIT(4),
1252                             (mute ? BIT(4) : 0));
1253         return 0;
1254 }
1255 
1256 static int lm49453_ha_mute(struct snd_soc_dai *dai, int mute)
1257 {
1258         snd_soc_update_bits(dai->codec, LM49453_P0_DAC_DSP_REG, BIT(7)|BIT(6),
1259                             (mute ? (BIT(7)|BIT(6)) : 0));
1260         return 0;
1261 }
1262 
1263 static int lm49453_set_bias_level(struct snd_soc_codec *codec,
1264                                   enum snd_soc_bias_level level)
1265 {
1266         struct lm49453_priv *lm49453 = snd_soc_codec_get_drvdata(codec);
1267 
1268         switch (level) {
1269         case SND_SOC_BIAS_ON:
1270         case SND_SOC_BIAS_PREPARE:
1271                 break;
1272 
1273         case SND_SOC_BIAS_STANDBY:
1274                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
1275                         regcache_sync(lm49453->regmap);
1276 
1277                 snd_soc_update_bits(codec, LM49453_P0_PMC_SETUP_REG,
1278                                     LM49453_PMC_SETUP_CHIP_EN, LM49453_CHIP_EN);
1279                 break;
1280 
1281         case SND_SOC_BIAS_OFF:
1282                 snd_soc_update_bits(codec, LM49453_P0_PMC_SETUP_REG,
1283                                     LM49453_PMC_SETUP_CHIP_EN, 0);
1284                 break;
1285         }
1286 
1287         codec->dapm.bias_level = level;
1288 
1289         return 0;
1290 }
1291 
1292 /* Formates supported by LM49453 driver. */
1293 #define LM49453_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1294                          SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1295 
1296 static struct snd_soc_dai_ops lm49453_headset_dai_ops = {
1297         .hw_params      = lm49453_hw_params,
1298         .set_sysclk     = lm49453_set_dai_sysclk,
1299         .set_fmt        = lm49453_set_dai_fmt,
1300         .digital_mute   = lm49453_hp_mute,
1301 };
1302 
1303 static struct snd_soc_dai_ops lm49453_speaker_dai_ops = {
1304         .hw_params      = lm49453_hw_params,
1305         .set_sysclk     = lm49453_set_dai_sysclk,
1306         .set_fmt        = lm49453_set_dai_fmt,
1307         .digital_mute   = lm49453_ls_mute,
1308 };
1309 
1310 static struct snd_soc_dai_ops lm49453_haptic_dai_ops = {
1311         .hw_params      = lm49453_hw_params,
1312         .set_sysclk     = lm49453_set_dai_sysclk,
1313         .set_fmt        = lm49453_set_dai_fmt,
1314         .digital_mute   = lm49453_ha_mute,
1315 };
1316 
1317 static struct snd_soc_dai_ops lm49453_ep_dai_ops = {
1318         .hw_params      = lm49453_hw_params,
1319         .set_sysclk     = lm49453_set_dai_sysclk,
1320         .set_fmt        = lm49453_set_dai_fmt,
1321         .digital_mute   = lm49453_ep_mute,
1322 };
1323 
1324 static struct snd_soc_dai_ops lm49453_lineout_dai_ops = {
1325         .hw_params      = lm49453_hw_params,
1326         .set_sysclk     = lm49453_set_dai_sysclk,
1327         .set_fmt        = lm49453_set_dai_fmt,
1328         .digital_mute   = lm49453_lo_mute,
1329 };
1330 
1331 /* LM49453 dai structure. */
1332 static struct snd_soc_dai_driver lm49453_dai[] = {
1333         {
1334                 .name = "LM49453 Headset",
1335                 .playback = {
1336                         .stream_name = "Headset",
1337                         .channels_min = 2,
1338                         .channels_max = 2,
1339                         .rates = SNDRV_PCM_RATE_8000_192000,
1340                         .formats = LM49453_FORMATS,
1341                 },
1342                 .capture = {
1343                         .stream_name = "Capture",
1344                         .channels_min = 1,
1345                         .channels_max = 5,
1346                         .rates = SNDRV_PCM_RATE_8000_192000,
1347                         .formats = LM49453_FORMATS,
1348                 },
1349                 .ops = &lm49453_headset_dai_ops,
1350                 .symmetric_rates = 1,
1351         },
1352         {
1353                 .name = "LM49453 Speaker",
1354                 .playback = {
1355                         .stream_name = "Speaker",
1356                         .channels_min = 2,
1357                         .channels_max = 2,
1358                         .rates = SNDRV_PCM_RATE_8000_192000,
1359                         .formats = LM49453_FORMATS,
1360                 },
1361                 .ops = &lm49453_speaker_dai_ops,
1362         },
1363         {
1364                 .name = "LM49453 Haptic",
1365                 .playback = {
1366                         .stream_name = "Haptic",
1367                         .channels_min = 2,
1368                         .channels_max = 2,
1369                         .rates = SNDRV_PCM_RATE_8000_192000,
1370                         .formats = LM49453_FORMATS,
1371                 },
1372                 .ops = &lm49453_haptic_dai_ops,
1373         },
1374         {
1375                 .name = "LM49453 Earpiece",
1376                 .playback = {
1377                         .stream_name = "Earpiece",
1378                         .channels_min = 1,
1379                         .channels_max = 1,
1380                         .rates = SNDRV_PCM_RATE_8000_192000,
1381                         .formats = LM49453_FORMATS,
1382                 },
1383                 .ops = &lm49453_ep_dai_ops,
1384         },
1385         {
1386                 .name = "LM49453 line out",
1387                 .playback = {
1388                         .stream_name = "Lineout",
1389                         .channels_min = 2,
1390                         .channels_max = 2,
1391                         .rates = SNDRV_PCM_RATE_8000_192000,
1392                         .formats = LM49453_FORMATS,
1393                 },
1394                 .ops = &lm49453_lineout_dai_ops,
1395         },
1396 };
1397 
1398 static struct snd_soc_codec_driver soc_codec_dev_lm49453 = {
1399         .set_bias_level = lm49453_set_bias_level,
1400         .controls = lm49453_snd_controls,
1401         .num_controls = ARRAY_SIZE(lm49453_snd_controls),
1402         .dapm_widgets = lm49453_dapm_widgets,
1403         .num_dapm_widgets = ARRAY_SIZE(lm49453_dapm_widgets),
1404         .dapm_routes = lm49453_audio_map,
1405         .num_dapm_routes = ARRAY_SIZE(lm49453_audio_map),
1406         .idle_bias_off = true,
1407 };
1408 
1409 static const struct regmap_config lm49453_regmap_config = {
1410         .reg_bits = 8,
1411         .val_bits = 8,
1412 
1413         .max_register = LM49453_MAX_REGISTER,
1414         .reg_defaults = lm49453_reg_defs,
1415         .num_reg_defaults = ARRAY_SIZE(lm49453_reg_defs),
1416         .cache_type = REGCACHE_RBTREE,
1417 };
1418 
1419 static int lm49453_i2c_probe(struct i2c_client *i2c,
1420                              const struct i2c_device_id *id)
1421 {
1422         struct lm49453_priv *lm49453;
1423         int ret = 0;
1424 
1425         lm49453 = devm_kzalloc(&i2c->dev, sizeof(struct lm49453_priv),
1426                                 GFP_KERNEL);
1427 
1428         if (lm49453 == NULL)
1429                 return -ENOMEM;
1430 
1431         i2c_set_clientdata(i2c, lm49453);
1432 
1433         lm49453->regmap = devm_regmap_init_i2c(i2c, &lm49453_regmap_config);
1434         if (IS_ERR(lm49453->regmap)) {
1435                 ret = PTR_ERR(lm49453->regmap);
1436                 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1437                         ret);
1438                 return ret;
1439         }
1440 
1441         ret =  snd_soc_register_codec(&i2c->dev,
1442                                       &soc_codec_dev_lm49453,
1443                                       lm49453_dai, ARRAY_SIZE(lm49453_dai));
1444         if (ret < 0)
1445                 dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
1446 
1447         return ret;
1448 }
1449 
1450 static int lm49453_i2c_remove(struct i2c_client *client)
1451 {
1452         snd_soc_unregister_codec(&client->dev);
1453         return 0;
1454 }
1455 
1456 static const struct i2c_device_id lm49453_i2c_id[] = {
1457         { "lm49453", 0 },
1458         { }
1459 };
1460 MODULE_DEVICE_TABLE(i2c, lm49453_i2c_id);
1461 
1462 static struct i2c_driver lm49453_i2c_driver = {
1463         .driver = {
1464                 .name = "lm49453",
1465                 .owner = THIS_MODULE,
1466         },
1467         .probe = lm49453_i2c_probe,
1468         .remove = lm49453_i2c_remove,
1469         .id_table = lm49453_i2c_id,
1470 };
1471 
1472 module_i2c_driver(lm49453_i2c_driver);
1473 
1474 MODULE_DESCRIPTION("ASoC LM49453 driver");
1475 MODULE_AUTHOR("M R Swami Reddy <MR.Swami.Reddy@ti.com>");
1476 MODULE_LICENSE("GPL v2");
1477 

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