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TOMOYO Linux Cross Reference
Linux/sound/soc/codecs/max98925.h

Version: ~ [ linux-5.12-rc1 ] ~ [ linux-5.11.2 ] ~ [ linux-5.10.19 ] ~ [ linux-5.9.16 ] ~ [ linux-5.8.18 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.101 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.177 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.222 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.258 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.258 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.18.140 ] ~ [ linux-3.16.85 ] ~ [ linux-3.14.79 ] ~ [ linux-3.12.74 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.5 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /* SPDX-License-Identifier: GPL-2.0-only */
  2 /*
  3  * max98925.h -- MAX98925 ALSA SoC Audio driver
  4  *
  5  * Copyright 2013-2015 Maxim Integrated Products
  6  */
  7 
  8 #ifndef _MAX98925_H
  9 #define _MAX98925_H
 10 
 11 #define MAX98925_VERSION        0x51
 12 #define MAX98925_VERSION1       0x80
 13 #define MAX98925_VBAT_DATA              0x00
 14 #define MAX98925_VBST_DATA              0x01
 15 #define MAX98925_LIVE_STATUS0           0x02
 16 #define MAX98925_LIVE_STATUS1           0x03
 17 #define MAX98925_LIVE_STATUS2           0x04
 18 #define MAX98925_STATE0                 0x05
 19 #define MAX98925_STATE1                 0x06
 20 #define MAX98925_STATE2                 0x07
 21 #define MAX98925_FLAG0                  0x08
 22 #define MAX98925_FLAG1                  0x09
 23 #define MAX98925_FLAG2                  0x0A
 24 #define MAX98925_IRQ_ENABLE0            0x0B
 25 #define MAX98925_IRQ_ENABLE1            0x0C
 26 #define MAX98925_IRQ_ENABLE2            0x0D
 27 #define MAX98925_IRQ_CLEAR0             0x0E
 28 #define MAX98925_IRQ_CLEAR1             0x0F
 29 #define MAX98925_IRQ_CLEAR2             0x10
 30 #define MAX98925_MAP0                   0x11
 31 #define MAX98925_MAP1                   0x12
 32 #define MAX98925_MAP2                   0x13
 33 #define MAX98925_MAP3                   0x14
 34 #define MAX98925_MAP4                   0x15
 35 #define MAX98925_MAP5                   0x16
 36 #define MAX98925_MAP6                   0x17
 37 #define MAX98925_MAP7                   0x18
 38 #define MAX98925_MAP8                   0x19
 39 #define MAX98925_DAI_CLK_MODE1          0x1A
 40 #define MAX98925_DAI_CLK_MODE2          0x1B
 41 #define MAX98925_DAI_CLK_DIV_M_MSBS     0x1C
 42 #define MAX98925_DAI_CLK_DIV_M_LSBS     0x1D
 43 #define MAX98925_DAI_CLK_DIV_N_MSBS     0x1E
 44 #define MAX98925_DAI_CLK_DIV_N_LSBS     0x1F
 45 #define MAX98925_FORMAT                 0x20
 46 #define MAX98925_TDM_SLOT_SELECT        0x21
 47 #define MAX98925_DOUT_CFG_VMON          0x22
 48 #define MAX98925_DOUT_CFG_IMON          0x23
 49 #define MAX98925_DOUT_CFG_VBAT          0x24
 50 #define MAX98925_DOUT_CFG_VBST          0x25
 51 #define MAX98925_DOUT_CFG_FLAG          0x26
 52 #define MAX98925_DOUT_HIZ_CFG1          0x27
 53 #define MAX98925_DOUT_HIZ_CFG2          0x28
 54 #define MAX98925_DOUT_HIZ_CFG3          0x29
 55 #define MAX98925_DOUT_HIZ_CFG4          0x2A
 56 #define MAX98925_DOUT_DRV_STRENGTH      0x2B
 57 #define MAX98925_FILTERS                0x2C
 58 #define MAX98925_GAIN                   0x2D
 59 #define MAX98925_GAIN_RAMPING           0x2E
 60 #define MAX98925_SPK_AMP                0x2F
 61 #define MAX98925_THRESHOLD              0x30
 62 #define MAX98925_ALC_ATTACK             0x31
 63 #define MAX98925_ALC_ATTEN_RLS          0x32
 64 #define MAX98925_ALC_HOLD_RLS           0x33
 65 #define MAX98925_ALC_CONFIGURATION      0x34
 66 #define MAX98925_BOOST_CONVERTER        0x35
 67 #define MAX98925_BLOCK_ENABLE           0x36
 68 #define MAX98925_CONFIGURATION          0x37
 69 #define MAX98925_GLOBAL_ENABLE          0x38
 70 #define MAX98925_BOOST_LIMITER          0x3A
 71 #define MAX98925_REV_VERSION            0xFF
 72 
 73 #define MAX98925_REG_CNT               (MAX98925_R03A_BOOST_LIMITER+1)
 74 
 75 /* MAX98925 Register Bit Fields */
 76 
 77 /* MAX98925_R002_LIVE_STATUS0 */
 78 #define M98925_THERMWARN_STATUS_MASK                    (1<<3)
 79 #define M98925_THERMWARN_STATUS_SHIFT                   3
 80 #define M98925_THERMWARN_STATUS_WIDTH                   1
 81 #define M98925_THERMSHDN_STATUS_MASK                    (1<<1)
 82 #define M98925_THERMSHDN_STATUS_SHIFT                   1
 83 #define M98925_THERMSHDN_STATUS_WIDTH                   1
 84 
 85 /* MAX98925_R003_LIVE_STATUS1 */
 86 #define M98925_SPKCURNT_STATUS_MASK                     (1<<5)
 87 #define M98925_SPKCURNT_STATUS_SHIFT                    5
 88 #define M98925_SPKCURNT_STATUS_WIDTH                    1
 89 #define M98925_WATCHFAIL_STATUS_MASK                    (1<<4)
 90 #define M98925_WATCHFAIL_STATUS_SHIFT                   4
 91 #define M98925_WATCHFAIL_STATUS_WIDTH                   1
 92 #define M98925_ALCINFH_STATUS_MASK                      (1<<3)
 93 #define M98925_ALCINFH_STATUS_SHIFT                     3
 94 #define M98925_ALCINFH_STATUS_WIDTH                     1
 95 #define M98925_ALCACT_STATUS_MASK                       (1<<2)
 96 #define M98925_ALCACT_STATUS_SHIFT                      2
 97 #define M98925_ALCACT_STATUS_WIDTH                      1
 98 #define M98925_ALCMUT_STATUS_MASK                       (1<<1)
 99 #define M98925_ALCMUT_STATUS_SHIFT                      1
100 #define M98925_ALCMUT_STATUS_WIDTH                      1
101 #define M98925_ACLP_STATUS_MASK                         (1<<0)
102 #define M98925_ACLP_STATUS_SHIFT                        0
103 #define M98925_ACLP_STATUS_WIDTH                        1
104 
105 /* MAX98925_R004_LIVE_STATUS2 */
106 #define M98925_SLOTOVRN_STATUS_MASK                     (1<<6)
107 #define M98925_SLOTOVRN_STATUS_SHIFT                    6
108 #define M98925_SLOTOVRN_STATUS_WIDTH                    1
109 #define M98925_INVALSLOT_STATUS_MASK                    (1<<5)
110 #define M98925_INVALSLOT_STATUS_SHIFT                   5
111 #define M98925_INVALSLOT_STATUS_WIDTH                   1
112 #define M98925_SLOTCNFLT_STATUS_MASK                    (1<<4)
113 #define M98925_SLOTCNFLT_STATUS_SHIFT                   4
114 #define M98925_SLOTCNFLT_STATUS_WIDTH                   1
115 #define M98925_VBSTOVFL_STATUS_MASK                     (1<<3)
116 #define M98925_VBSTOVFL_STATUS_SHIFT                    3
117 #define M98925_VBSTOVFL_STATUS_WIDTH                    1
118 #define M98925_VBATOVFL_STATUS_MASK                     (1<<2)
119 #define M98925_VBATOVFL_STATUS_SHIFT                    2
120 #define M98925_VBATOVFL_STATUS_WIDTH                    1
121 #define M98925_IMONOVFL_STATUS_MASK                     (1<<1)
122 #define M98925_IMONOVFL_STATUS_SHIFT                    1
123 #define M98925_IMONOVFL_STATUS_WIDTH                    1
124 #define M98925_VMONOVFL_STATUS_MASK                     (1<<0)
125 #define M98925_VMONOVFL_STATUS_SHIFT                    0
126 #define M98925_VMONOVFL_STATUS_WIDTH                    1
127 
128 /* MAX98925_R005_STATE0 */
129 #define M98925_THERMWARN_END_STATE_MASK                 (1<<3)
130 #define M98925_THERMWARN_END_STATE_SHIFT                3
131 #define M98925_THERMWARN_END_STATE_WIDTH                1
132 #define M98925_THERMWARN_BGN_STATE_MASK                 (1<<2)
133 #define M98925_THERMWARN_BGN_STATE_SHIFT                1
134 #define M98925_THERMWARN_BGN_STATE_WIDTH                1
135 #define M98925_THERMSHDN_END_STATE_MASK                 (1<<1)
136 #define M98925_THERMSHDN_END_STATE_SHIFT                1
137 #define M98925_THERMSHDN_END_STATE_WIDTH                1
138 #define M98925_THERMSHDN_BGN_STATE_MASK                 (1<<0)
139 #define M98925_THERMSHDN_BGN_STATE_SHIFT                0
140 #define M98925_THERMSHDN_BGN_STATE_WIDTH                1
141 
142 /* MAX98925_R006_STATE1 */
143 #define M98925_SPRCURNT_STATE_MASK                      (1<<5)
144 #define M98925_SPRCURNT_STATE_SHIFT                     5
145 #define M98925_SPRCURNT_STATE_WIDTH                     1
146 #define M98925_WATCHFAIL_STATE_MASK                     (1<<4)
147 #define M98925_WATCHFAIL_STATE_SHIFT                    4
148 #define M98925_WATCHFAIL_STATE_WIDTH                    1
149 #define M98925_ALCINFH_STATE_MASK                       (1<<3)
150 #define M98925_ALCINFH_STATE_SHIFT                      3
151 #define M98925_ALCINFH_STATE_WIDTH                      1
152 #define M98925_ALCACT_STATE_MASK                        (1<<2)
153 #define M98925_ALCACT_STATE_SHIFT                       2
154 #define M98925_ALCACT_STATE_WIDTH                       1
155 #define M98925_ALCMUT_STATE_MASK                        (1<<1)
156 #define M98925_ALCMUT_STATE_SHIFT                       1
157 #define M98925_ALCMUT_STATE_WIDTH                       1
158 #define M98925_ALCP_STATE_MASK                          (1<<0)
159 #define M98925_ALCP_STATE_SHIFT                         0
160 #define M98925_ALCP_STATE_WIDTH                         1
161 
162 /* MAX98925_R007_STATE2 */
163 #define M98925_SLOTOVRN_STATE_MASK                      (1<<6)
164 #define M98925_SLOTOVRN_STATE_SHIFT                     6
165 #define M98925_SLOTOVRN_STATE_WIDTH                     1
166 #define M98925_INVALSLOT_STATE_MASK                     (1<<5)
167 #define M98925_INVALSLOT_STATE_SHIFT                    5
168 #define M98925_INVALSLOT_STATE_WIDTH                    1
169 #define M98925_SLOTCNFLT_STATE_MASK                     (1<<4)
170 #define M98925_SLOTCNFLT_STATE_SHIFT                    4
171 #define M98925_SLOTCNFLT_STATE_WIDTH                    1
172 #define M98925_VBSTOVFL_STATE_MASK                      (1<<3)
173 #define M98925_VBSTOVFL_STATE_SHIFT                     3
174 #define M98925_VBSTOVFL_STATE_WIDTH                     1
175 #define M98925_VBATOVFL_STATE_MASK                      (1<<2)
176 #define M98925_VBATOVFL_STATE_SHIFT                     2
177 #define M98925_VBATOVFL_STATE_WIDTH                     1
178 #define M98925_IMONOVFL_STATE_MASK                      (1<<1)
179 #define M98925_IMONOVFL_STATE_SHIFT                     1
180 #define M98925_IMONOVFL_STATE_WIDTH                     1
181 #define M98925_VMONOVFL_STATE_MASK                      (1<<0)
182 #define M98925_VMONOVFL_STATE_SHIFT                     0
183 #define M98925_VMONOVFL_STATE_WIDTH                     1
184 
185 /* MAX98925_R008_FLAG0 */
186 #define M98925_THERMWARN_END_FLAG_MASK                  (1<<3)
187 #define M98925_THERMWARN_END_FLAG_SHIFT                 3
188 #define M98925_THERMWARN_END_FLAG_WIDTH                 1
189 #define M98925_THERMWARN_BGN_FLAG_MASK                  (1<<2)
190 #define M98925_THERMWARN_BGN_FLAG_SHIFT                 2
191 #define M98925_THERMWARN_BGN_FLAG_WIDTH                 1
192 #define M98925_THERMSHDN_END_FLAG_MASK                  (1<<1)
193 #define M98925_THERMSHDN_END_FLAG_SHIFT                 1
194 #define M98925_THERMSHDN_END_FLAG_WIDTH                 1
195 #define M98925_THERMSHDN_BGN_FLAG_MASK                  (1<<0)
196 #define M98925_THERMSHDN_BGN_FLAG_SHIFT                 0
197 #define M98925_THERMSHDN_BGN_FLAG_WIDTH                 1
198 
199 /* MAX98925_R009_FLAG1 */
200 #define M98925_SPKCURNT_FLAG_MASK                       (1<<5)
201 #define M98925_SPKCURNT_FLAG_SHIFT                      5
202 #define M98925_SPKCURNT_FLAG_WIDTH                      1
203 #define M98925_WATCHFAIL_FLAG_MASK                      (1<<4)
204 #define M98925_WATCHFAIL_FLAG_SHIFT                     4
205 #define M98925_WATCHFAIL_FLAG_WIDTH                     1
206 #define M98925_ALCINFH_FLAG_MASK                        (1<<3)
207 #define M98925_ALCINFH_FLAG_SHIFT                       3
208 #define M98925_ALCINFH_FLAG_WIDTH                       1
209 #define M98925_ALCACT_FLAG_MASK                         (1<<2)
210 #define M98925_ALCACT_FLAG_SHIFT                        2
211 #define M98925_ALCACT_FLAG_WIDTH                        1
212 #define M98925_ALCMUT_FLAG_MASK                         (1<<1)
213 #define M98925_ALCMUT_FLAG_SHIFT                        1
214 #define M98925_ALCMUT_FLAG_WIDTH                        1
215 #define M98925_ALCP_FLAG_MASK                           (1<<0)
216 #define M98925_ALCP_FLAG_SHIFT                          0
217 #define M98925_ALCP_FLAG_WIDTH                          1
218 
219 /* MAX98925_R00A_FLAG2 */
220 #define M98925_SLOTOVRN_FLAG_MASK                       (1<<6)
221 #define M98925_SLOTOVRN_FLAG_SHIFT                      6
222 #define M98925_SLOTOVRN_FLAG_WIDTH                      1
223 #define M98925_INVALSLOT_FLAG_MASK                      (1<<5)
224 #define M98925_INVALSLOT_FLAG_SHIFT                     5
225 #define M98925_INVALSLOT_FLAG_WIDTH                     1
226 #define M98925_SLOTCNFLT_FLAG_MASK                      (1<<4)
227 #define M98925_SLOTCNFLT_FLAG_SHIFT                     4
228 #define M98925_SLOTCNFLT_FLAG_WIDTH                     1
229 #define M98925_VBSTOVFL_FLAG_MASK                       (1<<3)
230 #define M98925_VBSTOVFL_FLAG_SHIFT                      3
231 #define M98925_VBSTOVFL_FLAG_WIDTH                      1
232 #define M98925_VBATOVFL_FLAG_MASK                       (1<<2)
233 #define M98925_VBATOVFL_FLAG_SHIFT                      2
234 #define M98925_VBATOVFL_FLAG_WIDTH                      1
235 #define M98925_IMONOVFL_FLAG_MASK                       (1<<1)
236 #define M98925_IMONOVFL_FLAG_SHIFT                      1
237 #define M98925_IMONOVFL_FLAG_WIDTH                      1
238 #define M98925_VMONOVFL_FLAG_MASK                       (1<<0)
239 #define M98925_VMONOVFL_FLAG_SHIFT                      0
240 #define M98925_VMONOVFL_FLAG_WIDTH                      1
241 
242 /* MAX98925_R00B_IRQ_ENABLE0 */
243 #define M98925_THERMWARN_END_EN_MASK                    (1<<3)
244 #define M98925_THERMWARN_END_EN_SHIFT                   3
245 #define M98925_THERMWARN_END_EN_WIDTH                   1
246 #define M98925_THERMWARN_BGN_EN_MASK                    (1<<2)
247 #define M98925_THERMWARN_BGN_EN_SHIFT                   2
248 #define M98925_THERMWARN_BGN_EN_WIDTH                   1
249 #define M98925_THERMSHDN_END_EN_MASK                    (1<<1)
250 #define M98925_THERMSHDN_END_EN_SHIFT                   1
251 #define M98925_THERMSHDN_END_EN_WIDTH                   1
252 #define M98925_THERMSHDN_BGN_EN_MASK                    (1<<0)
253 #define M98925_THERMSHDN_BGN_EN_SHIFT                   0
254 #define M98925_THERMSHDN_BGN_EN_WIDTH                   1
255 
256 /* MAX98925_R00C_IRQ_ENABLE1 */
257 #define M98925_SPKCURNT_EN_MASK                         (1<<5)
258 #define M98925_SPKCURNT_EN_SHIFT                        5
259 #define M98925_SPKCURNT_EN_WIDTH                        1
260 #define M98925_WATCHFAIL_EN_MASK                        (1<<4)
261 #define M98925_WATCHFAIL_EN_SHIFT                       4
262 #define M98925_WATCHFAIL_EN_WIDTH                       1
263 #define M98925_ALCINFH_EN_MASK                          (1<<3)
264 #define M98925_ALCINFH_EN_SHIFT                         3
265 #define M98925_ALCINFH_EN_WIDTH                         1
266 #define M98925_ALCACT_EN_MASK                           (1<<2)
267 #define M98925_ALCACT_EN_SHIFT                          2
268 #define M98925_ALCACT_EN_WIDTH                          1
269 #define M98925_ALCMUT_EN_MASK                           (1<<1)
270 #define M98925_ALCMUT_EN_SHIFT                          1
271 #define M98925_ALCMUT_EN_WIDTH                          1
272 #define M98925_ALCP_EN_MASK                                     (1<<0)
273 #define M98925_ALCP_EN_SHIFT                            0
274 #define M98925_ALCP_EN_WIDTH                            1
275 
276 /* MAX98925_R00D_IRQ_ENABLE2 */
277 #define M98925_SLOTOVRN_EN_MASK                                 (1<<6)
278 #define M98925_SLOTOVRN_EN_SHIFT                                6
279 #define M98925_SLOTOVRN_EN_WIDTH                                1
280 #define M98925_INVALSLOT_EN_MASK                                (1<<5)
281 #define M98925_INVALSLOT_EN_SHIFT                               5
282 #define M98925_INVALSLOT_EN_WIDTH                               1
283 #define M98925_SLOTCNFLT_EN_MASK                                (1<<4)
284 #define M98925_SLOTCNFLT_EN_SHIFT                               4
285 #define M98925_SLOTCNFLT_EN_WIDTH                               1
286 #define M98925_VBSTOVFL_EN_MASK                                 (1<<3)
287 #define M98925_VBSTOVFL_EN_SHIFT                                3
288 #define M98925_VBSTOVFL_EN_WIDTH                                1
289 #define M98925_VBATOVFL_EN_MASK                                 (1<<2)
290 #define M98925_VBATOVFL_EN_SHIFT                                2
291 #define M98925_VBATOVFL_EN_WIDTH                                1
292 #define M98925_IMONOVFL_EN_MASK                                 (1<<1)
293 #define M98925_IMONOVFL_EN_SHIFT                                1
294 #define M98925_IMONOVFL_EN_WIDTH                                1
295 #define M98925_VMONOVFL_EN_MASK                                 (1<<0)
296 #define M98925_VMONOVFL_EN_SHIFT                                0
297 #define M98925_VMONOVFL_EN_WIDTH                                1
298 
299 /* MAX98925_R00E_IRQ_CLEAR0 */
300 #define M98925_THERMWARN_END_CLR_MASK                   (1<<3)
301 #define M98925_THERMWARN_END_CLR_SHIFT                  3
302 #define M98925_THERMWARN_END_CLR_WIDTH                  1
303 #define M98925_THERMWARN_BGN_CLR_MASK                   (1<<2)
304 #define M98925_THERMWARN_BGN_CLR_SHIFT                  2
305 #define M98925_THERMWARN_BGN_CLR_WIDTH                  1
306 #define M98925_THERMSHDN_END_CLR_MASK                   (1<<1)
307 #define M98925_THERMSHDN_END_CLR_SHIFT                  1
308 #define M98925_THERMSHDN_END_CLR_WIDTH                  1
309 #define M98925_THERMSHDN_BGN_CLR_MASK                   (1<<0)
310 #define M98925_THERMSHDN_BGN_CLR_SHIFT                  0
311 #define M98925_THERMSHDN_BGN_CLR_WIDTH                  1
312 
313 /* MAX98925_R00F_IRQ_CLEAR1 */
314 #define M98925_SPKCURNT_CLR_MASK                                (1<<5)
315 #define M98925_SPKCURNT_CLR_SHIFT                               5
316 #define M98925_SPKCURNT_CLR_WIDTH                               1
317 #define M98925_WATCHFAIL_CLR_MASK                               (1<<4)
318 #define M98925_WATCHFAIL_CLR_SHIFT                              4
319 #define M98925_WATCHFAIL_CLR_WIDTH                              1
320 #define M98925_ALCINFH_CLR_MASK                                 (1<<3)
321 #define M98925_ALCINFH_CLR_SHIFT                                3
322 #define M98925_ALCINFH_CLR_WIDTH                                1
323 #define M98925_ALCACT_CLR_MASK                                  (1<<2)
324 #define M98925_ALCACT_CLR_SHIFT                                 2
325 #define M98925_ALCACT_CLR_WIDTH                                 1
326 #define M98925_ALCMUT_CLR_MASK                                  (1<<1)
327 #define M98925_ALCMUT_CLR_SHIFT                                 1
328 #define M98925_ALCMUT_CLR_WIDTH                                 1
329 #define M98925_ALCP_CLR_MASK                                    (1<<0)
330 #define M98925_ALCP_CLR_SHIFT                                   0
331 #define M98925_ALCP_CLR_WIDTH                                   1
332 
333 /* MAX98925_R010_IRQ_CLEAR2 */
334 #define M98925_SLOTOVRN_CLR_MASK                                (1<<6)
335 #define M98925_SLOTOVRN_CLR_SHIFT                               6
336 #define M98925_SLOTOVRN_CLR_WIDTH                               1
337 #define M98925_INVALSLOT_CLR_MASK                               (1<<5)
338 #define M98925_INVALSLOT_CLR_SHIFT                              5
339 #define M98925_INVALSLOT_CLR_WIDTH                              1
340 #define M98925_SLOTCNFLT_CLR_MASK                               (1<<4)
341 #define M98925_SLOTCNFLT_CLR_SHIFT                              4
342 #define M98925_SLOTCNFLT_CLR_WIDTH                              1
343 #define M98925_VBSTOVFL_CLR_MASK                                (1<<3)
344 #define M98925_VBSTOVFL_CLR_SHIFT                               3
345 #define M98925_VBSTOVFL_CLR_WIDTH                               1
346 #define M98925_VBATOVFL_CLR_MASK                                (1<<2)
347 #define M98925_VBATOVFL_CLR_SHIFT                               2
348 #define M98925_VBATOVFL_CLR_WIDTH                               1
349 #define M98925_IMONOVFL_CLR_MASK                                (1<<1)
350 #define M98925_IMONOVFL_CLR_SHIFT                               1
351 #define M98925_IMONOVFL_CLR_WIDTH                               1
352 #define M98925_VMONOVFL_CLR_MASK                                (1<<0)
353 #define M98925_VMONOVFL_CLR_SHIFT                               0
354 #define M98925_VMONOVFL_CLR_WIDTH                               1
355 
356 /* MAX98925_R011_MAP0 */
357 #define M98925_ER_THERMWARN_EN_MASK                             (1<<7)
358 #define M98925_ER_THERMWARN_EN_SHIFT                    7
359 #define M98925_ER_THERMWARN_EN_WIDTH                    1
360 #define M98925_ER_THERMWARN_MAP_MASK                    (0x07<<4)
361 #define M98925_ER_THERMWARN_MAP_SHIFT                   4
362 #define M98925_ER_THERMWARN_MAP_WIDTH                   3
363 
364 /* MAX98925_R012_MAP1 */
365 #define M98925_ER_ALCMUT_EN_MASK                                (1<<7)
366 #define M98925_ER_ALCMUT_EN_SHIFT                               7
367 #define M98925_ER_ALCMUT_EN_WIDTH                               1
368 #define M98925_ER_ALCMUT_MAP_MASK                               (0x07<<4)
369 #define M98925_ER_ALCMUT_MAP_SHIFT                              4
370 #define M98925_ER_ALCMUT_MAP_WIDTH                              3
371 #define M98925_ER_ALCP_EN_MASK                                  (1<<3)
372 #define M98925_ER_ALCP_EN_SHIFT                                 3
373 #define M98925_ER_ALCP_EN_WIDTH                                 1
374 #define M98925_ER_ALCP_MAP_MASK                                 (0x07<<0)
375 #define M98925_ER_ALCP_MAP_SHIFT                                0
376 #define M98925_ER_ALCP_MAP_WIDTH                                3
377 
378 /* MAX98925_R013_MAP2 */
379 #define M98925_ER_ALCINFH_EN_MASK                               (1<<7)
380 #define M98925_ER_ALCINFH_EN_SHIFT                              7
381 #define M98925_ER_ALCINFH_EN_WIDTH                              1
382 #define M98925_ER_ALCINFH_MAP_MASK                              (0x07<<4)
383 #define M98925_ER_ALCINFH_MAP_SHIFT                             4
384 #define M98925_ER_ALCINFH_MAP_WIDTH                             3
385 #define M98925_ER_ALCACT_EN_MASK                                (1<<3)
386 #define M98925_ER_ALCACT_EN_SHIFT                               3
387 #define M98925_ER_ALCACT_EN_WIDTH                               1
388 #define M98925_ER_ALCACT_MAP_MASK                               (0x07<<0)
389 #define M98925_ER_ALCACT_MAP_SHIFT                              0
390 #define M98925_ER_ALCACT_MAP_WIDTH                              3
391 
392 /* MAX98925_R014_MAP3 */
393 #define M98925_ER_SPKCURNT_EN_MASK                              (1<<7)
394 #define M98925_ER_SPKCURNT_EN_SHIFT                             7
395 #define M98925_ER_SPKCURNT_EN_WIDTH                             1
396 #define M98925_ER_SPKCURNT_MAP_MASK                             (0x07<<4)
397 #define M98925_ER_SPKCURNT_MAP_SHIFT                    4
398 #define M98925_ER_SPKCURNT_MAP_WIDTH                    3
399 
400 /* MAX98925_R015_MAP4 */
401 /* RESERVED */
402 
403 /* MAX98925_R016_MAP5 */
404 #define M98925_ER_IMONOVFL_EN_MASK                              (1<<7)
405 #define M98925_ER_IMONOVFL_EN_SHIFT                             7
406 #define M98925_ER_IMONOVFL_EN_WIDTH                             1
407 #define M98925_ER_IMONOVFL_MAP_MASK                             (0x07<<4)
408 #define M98925_ER_IMONOVFL_MAP_SHIFT                    4
409 #define M98925_ER_IMONOVFL_MAP_WIDTH                    3
410 #define M98925_ER_VMONOVFL_EN_MASK                              (1<<3)
411 #define M98925_ER_VMONOVFL_EN_SHIFT                             3
412 #define M98925_ER_VMONOVFL_EN_WIDTH                             1
413 #define M98925_ER_VMONOVFL_MAP_MASK                             (0x07<<0)
414 #define M98925_ER_VMONOVFL_MAP_SHIFT                    0
415 #define M98925_ER_VMONOVFL_MAP_WIDTH                    3
416 
417 /* MAX98925_R017_MAP6 */
418 #define M98925_ER_VBSTOVFL_EN_MASK                              (1<<7)
419 #define M98925_ER_VBSTOVFL_EN_SHIFT                             7
420 #define M98925_ER_VBSTOVFL_EN_WIDTH                             1
421 #define M98925_ER_VBSTOVFL_MAP_MASK                             (0x07<<4)
422 #define M98925_ER_VBSTOVFL_MAP_SHIFT                    4
423 #define M98925_ER_VBSTOVFL_MAP_WIDTH                    3
424 #define M98925_ER_VBATOVFL_EN_MASK                              (1<<3)
425 #define M98925_ER_VBATOVFL_EN_SHIFT                             3
426 #define M98925_ER_VBATOVFL_EN_WIDTH                             1
427 #define M98925_ER_VBATOVFL_MAP_MASK                             (0x07<<0)
428 #define M98925_ER_VBATOVFL_MAP_SHIFT                    0
429 #define M98925_ER_VBATOVFL_MAP_WIDTH                    3
430 
431 /* MAX98925_R018_MAP7 */
432 #define M98925_ER_INVALSLOT_EN_MASK                             (1<<7)
433 #define M98925_ER_INVALSLOT_EN_SHIFT                    7
434 #define M98925_ER_INVALSLOT_EN_WIDTH                    1
435 #define M98925_ER_INVALSLOT_MAP_MASK                    (0x07<<4)
436 #define M98925_ER_INVALSLOT_MAP_SHIFT                   4
437 #define M98925_ER_INVALSLOT_MAP_WIDTH                   3
438 #define M98925_ER_SLOTCNFLT_EN_MASK                             (1<<3)
439 #define M98925_ER_SLOTCNFLT_EN_SHIFT                    3
440 #define M98925_ER_SLOTCNFLT_EN_WIDTH                    1
441 #define M98925_ER_SLOTCNFLT_MAP_MASK                    (0x07<<0)
442 #define M98925_ER_SLOTCNFLT_MAP_SHIFT                   0
443 #define M98925_ER_SLOTCNFLT_MAP_WIDTH                   3
444 
445 /* MAX98925_R019_MAP8 */
446 #define M98925_ER_SLOTOVRN_EN_MASK      (1<<3)
447 #define M98925_ER_SLOTOVRN_EN_SHIFT     3
448 #define M98925_ER_SLOTOVRN_EN_WIDTH     1
449 #define M98925_ER_SLOTOVRN_MAP_MASK     (0x07<<0)
450 #define M98925_ER_SLOTOVRN_MAP_SHIFT    0
451 #define M98925_ER_SLOTOVRN_MAP_WIDTH    3
452 
453 /* MAX98925_R01A_DAI_CLK_MODE1 */
454 #define M98925_DAI_CLK_SOURCE_MASK      (1<<6)
455 #define M98925_DAI_CLK_SOURCE_SHIFT     6
456 #define M98925_DAI_CLK_SOURCE_WIDTH     1
457 #define M98925_MDLL_MULT_MASK           (0x0F<<0)
458 #define M98925_MDLL_MULT_SHIFT          0
459 #define M98925_MDLL_MULT_WIDTH          4
460 
461 #define M98925_MDLL_MULT_MCLKx8         6
462 #define M98925_MDLL_MULT_MCLKx16        8
463 
464 /* MAX98925_R01B_DAI_CLK_MODE2 */
465 #define M98925_DAI_SR_MASK                      (0x0F<<4)
466 #define M98925_DAI_SR_SHIFT                     4
467 #define M98925_DAI_SR_WIDTH                     4
468 #define M98925_DAI_MAS_MASK                     (1<<3)
469 #define M98925_DAI_MAS_SHIFT                    3
470 #define M98925_DAI_MAS_WIDTH                    1
471 #define M98925_DAI_BSEL_MASK                    (0x07<<0)
472 #define M98925_DAI_BSEL_SHIFT                   0
473 #define M98925_DAI_BSEL_WIDTH                   3
474 
475 #define M98925_DAI_BSEL_32 (0 << M98925_DAI_BSEL_SHIFT)
476 #define M98925_DAI_BSEL_48 (1 << M98925_DAI_BSEL_SHIFT)
477 #define M98925_DAI_BSEL_64 (2 << M98925_DAI_BSEL_SHIFT)
478 #define M98925_DAI_BSEL_256 (6 << M98925_DAI_BSEL_SHIFT)
479 
480 /* MAX98925_R01C_DAI_CLK_DIV_M_MSBS */
481 #define M98925_DAI_M_MSBS_MASK                                  (0xFF<<0)
482 #define M98925_DAI_M_MSBS_SHIFT                                 0
483 #define M98925_DAI_M_MSBS_WIDTH                                 8
484 
485 /* MAX98925_R01D_DAI_CLK_DIV_M_LSBS */
486 #define M98925_DAI_M_LSBS_MASK                                  (0xFF<<0)
487 #define M98925_DAI_M_LSBS_SHIFT                                 0
488 #define M98925_DAI_M_LSBS_WIDTH                                 8
489 
490 /* MAX98925_R01E_DAI_CLK_DIV_N_MSBS */
491 #define M98925_DAI_N_MSBS_MASK                                  (0x7F<<0)
492 #define M98925_DAI_N_MSBS_SHIFT                                 0
493 #define M98925_DAI_N_MSBS_WIDTH                                 7
494 
495 /* MAX98925_R01F_DAI_CLK_DIV_N_LSBS */
496 #define M98925_DAI_N_LSBS_MASK                                  (0xFF<<0)
497 #define M98925_DAI_N_LSBS_SHIFT                                 0
498 #define M98925_DAI_N_LSBS_WIDTH                                 8
499 
500 /* MAX98925_R020_FORMAT */
501 #define M98925_DAI_CHANSZ_MASK                                  (0x03<<6)
502 #define M98925_DAI_CHANSZ_SHIFT                                 6
503 #define M98925_DAI_CHANSZ_WIDTH                                 2
504 #define M98925_DAI_EXTBCLK_HIZ_MASK                             (1<<4)
505 #define M98925_DAI_EXTBCLK_HIZ_SHIFT                    4
506 #define M98925_DAI_EXTBCLK_HIZ_WIDTH                    1
507 #define M98925_DAI_WCI_MASK                                             (1<<3)
508 #define M98925_DAI_WCI_SHIFT                                    3
509 #define M98925_DAI_WCI_WIDTH                                    1
510 #define M98925_DAI_BCI_MASK                                             (1<<2)
511 #define M98925_DAI_BCI_SHIFT                                    2
512 #define M98925_DAI_BCI_WIDTH                                    1
513 #define M98925_DAI_DLY_MASK                                             (1<<1)
514 #define M98925_DAI_DLY_SHIFT                                    1
515 #define M98925_DAI_DLY_WIDTH                                    1
516 #define M98925_DAI_TDM_MASK                                             (1<<0)
517 #define M98925_DAI_TDM_SHIFT                                    0
518 #define M98925_DAI_TDM_WIDTH                                    1
519 
520 #define M98925_DAI_CHANSZ_16 (1 << M98925_DAI_CHANSZ_SHIFT)
521 #define M98925_DAI_CHANSZ_24 (2 << M98925_DAI_CHANSZ_SHIFT)
522 #define M98925_DAI_CHANSZ_32 (3 << M98925_DAI_CHANSZ_SHIFT)
523 
524 /* MAX98925_R021_TDM_SLOT_SELECT */
525 #define M98925_DAI_DO_EN_MASK                                   (1<<7)
526 #define M98925_DAI_DO_EN_SHIFT                                  7
527 #define M98925_DAI_DO_EN_WIDTH                                  1
528 #define M98925_DAI_DIN_EN_MASK                                  (1<<6)
529 #define M98925_DAI_DIN_EN_SHIFT                                 6
530 #define M98925_DAI_DIN_EN_WIDTH                                 1
531 #define M98925_DAI_INR_SOURCE_MASK                              (0x07<<3)
532 #define M98925_DAI_INR_SOURCE_SHIFT                             3
533 #define M98925_DAI_INR_SOURCE_WIDTH                             3
534 #define M98925_DAI_INL_SOURCE_MASK                              (0x07<<0)
535 #define M98925_DAI_INL_SOURCE_SHIFT                             0
536 #define M98925_DAI_INL_SOURCE_WIDTH                             3
537 
538 /* MAX98925_R022_DOUT_CFG_VMON */
539 #define M98925_DAI_VMON_EN_MASK                                 (1<<5)
540 #define M98925_DAI_VMON_EN_SHIFT                                5
541 #define M98925_DAI_VMON_EN_WIDTH                                1
542 #define M98925_DAI_VMON_SLOT_MASK                               (0x1F<<0)
543 #define M98925_DAI_VMON_SLOT_SHIFT                              0
544 #define M98925_DAI_VMON_SLOT_WIDTH                              5
545 
546 #define M98925_DAI_VMON_SLOT_00_01 (0 << M98925_DAI_VMON_SLOT_SHIFT)
547 #define M98925_DAI_VMON_SLOT_01_02 (1 << M98925_DAI_VMON_SLOT_SHIFT)
548 #define M98925_DAI_VMON_SLOT_02_03 (2 << M98925_DAI_VMON_SLOT_SHIFT)
549 #define M98925_DAI_VMON_SLOT_03_04 (3 << M98925_DAI_VMON_SLOT_SHIFT)
550 #define M98925_DAI_VMON_SLOT_04_05 (4 << M98925_DAI_VMON_SLOT_SHIFT)
551 #define M98925_DAI_VMON_SLOT_05_06 (5 << M98925_DAI_VMON_SLOT_SHIFT)
552 #define M98925_DAI_VMON_SLOT_06_07 (6 << M98925_DAI_VMON_SLOT_SHIFT)
553 #define M98925_DAI_VMON_SLOT_07_08 (7 << M98925_DAI_VMON_SLOT_SHIFT)
554 #define M98925_DAI_VMON_SLOT_08_09 (8 << M98925_DAI_VMON_SLOT_SHIFT)
555 #define M98925_DAI_VMON_SLOT_09_0A (9 << M98925_DAI_VMON_SLOT_SHIFT)
556 #define M98925_DAI_VMON_SLOT_0A_0B (10 << M98925_DAI_VMON_SLOT_SHIFT)
557 #define M98925_DAI_VMON_SLOT_0B_0C (11 << M98925_DAI_VMON_SLOT_SHIFT)
558 #define M98925_DAI_VMON_SLOT_0C_0D (12 << M98925_DAI_VMON_SLOT_SHIFT)
559 #define M98925_DAI_VMON_SLOT_0D_0E (13 << M98925_DAI_VMON_SLOT_SHIFT)
560 #define M98925_DAI_VMON_SLOT_0E_0F (14 << M98925_DAI_VMON_SLOT_SHIFT)
561 #define M98925_DAI_VMON_SLOT_0F_10 (15 << M98925_DAI_VMON_SLOT_SHIFT)
562 #define M98925_DAI_VMON_SLOT_10_11 (16 << M98925_DAI_VMON_SLOT_SHIFT)
563 #define M98925_DAI_VMON_SLOT_11_12 (17 << M98925_DAI_VMON_SLOT_SHIFT)
564 #define M98925_DAI_VMON_SLOT_12_13 (18 << M98925_DAI_VMON_SLOT_SHIFT)
565 #define M98925_DAI_VMON_SLOT_13_14 (19 << M98925_DAI_VMON_SLOT_SHIFT)
566 #define M98925_DAI_VMON_SLOT_14_15 (20 << M98925_DAI_VMON_SLOT_SHIFT)
567 #define M98925_DAI_VMON_SLOT_15_16 (21 << M98925_DAI_VMON_SLOT_SHIFT)
568 #define M98925_DAI_VMON_SLOT_16_17 (22 << M98925_DAI_VMON_SLOT_SHIFT)
569 #define M98925_DAI_VMON_SLOT_17_18 (23 << M98925_DAI_VMON_SLOT_SHIFT)
570 #define M98925_DAI_VMON_SLOT_18_19 (24 << M98925_DAI_VMON_SLOT_SHIFT)
571 #define M98925_DAI_VMON_SLOT_19_1A (25 << M98925_DAI_VMON_SLOT_SHIFT)
572 #define M98925_DAI_VMON_SLOT_1A_1B (26 << M98925_DAI_VMON_SLOT_SHIFT)
573 #define M98925_DAI_VMON_SLOT_1B_1C (27 << M98925_DAI_VMON_SLOT_SHIFT)
574 #define M98925_DAI_VMON_SLOT_1C_1D (28 << M98925_DAI_VMON_SLOT_SHIFT)
575 #define M98925_DAI_VMON_SLOT_1D_1E (29 << M98925_DAI_VMON_SLOT_SHIFT)
576 #define M98925_DAI_VMON_SLOT_1E_1F (30 << M98925_DAI_VMON_SLOT_SHIFT)
577 
578 /* MAX98925_R023_DOUT_CFG_IMON */
579 #define M98925_DAI_IMON_EN_MASK                                 (1<<5)
580 #define M98925_DAI_IMON_EN_SHIFT                                5
581 #define M98925_DAI_IMON_EN_WIDTH                                1
582 #define M98925_DAI_IMON_SLOT_MASK                               (0x1F<<0)
583 #define M98925_DAI_IMON_SLOT_SHIFT                              0
584 #define M98925_DAI_IMON_SLOT_WIDTH                              5
585 
586 #define M98925_DAI_IMON_SLOT_00_01 (0 << M98925_DAI_IMON_SLOT_SHIFT)
587 #define M98925_DAI_IMON_SLOT_01_02 (1 << M98925_DAI_IMON_SLOT_SHIFT)
588 #define M98925_DAI_IMON_SLOT_02_03 (2 << M98925_DAI_IMON_SLOT_SHIFT)
589 #define M98925_DAI_IMON_SLOT_03_04 (3 << M98925_DAI_IMON_SLOT_SHIFT)
590 #define M98925_DAI_IMON_SLOT_04_05 (4 << M98925_DAI_IMON_SLOT_SHIFT)
591 #define M98925_DAI_IMON_SLOT_05_06 (5 << M98925_DAI_IMON_SLOT_SHIFT)
592 #define M98925_DAI_IMON_SLOT_06_07 (6 << M98925_DAI_IMON_SLOT_SHIFT)
593 #define M98925_DAI_IMON_SLOT_07_08 (7 << M98925_DAI_IMON_SLOT_SHIFT)
594 #define M98925_DAI_IMON_SLOT_08_09 (8 << M98925_DAI_IMON_SLOT_SHIFT)
595 #define M98925_DAI_IMON_SLOT_09_0A (9 << M98925_DAI_IMON_SLOT_SHIFT)
596 #define M98925_DAI_IMON_SLOT_0A_0B (10 << M98925_DAI_IMON_SLOT_SHIFT)
597 #define M98925_DAI_IMON_SLOT_0B_0C (11 << M98925_DAI_IMON_SLOT_SHIFT)
598 #define M98925_DAI_IMON_SLOT_0C_0D (12 << M98925_DAI_IMON_SLOT_SHIFT)
599 #define M98925_DAI_IMON_SLOT_0D_0E (13 << M98925_DAI_IMON_SLOT_SHIFT)
600 #define M98925_DAI_IMON_SLOT_0E_0F (14 << M98925_DAI_IMON_SLOT_SHIFT)
601 #define M98925_DAI_IMON_SLOT_0F_10 (15 << M98925_DAI_IMON_SLOT_SHIFT)
602 #define M98925_DAI_IMON_SLOT_10_11 (16 << M98925_DAI_IMON_SLOT_SHIFT)
603 #define M98925_DAI_IMON_SLOT_11_12 (17 << M98925_DAI_IMON_SLOT_SHIFT)
604 #define M98925_DAI_IMON_SLOT_12_13 (18 << M98925_DAI_IMON_SLOT_SHIFT)
605 #define M98925_DAI_IMON_SLOT_13_14 (19 << M98925_DAI_IMON_SLOT_SHIFT)
606 #define M98925_DAI_IMON_SLOT_14_15 (20 << M98925_DAI_IMON_SLOT_SHIFT)
607 #define M98925_DAI_IMON_SLOT_15_16 (21 << M98925_DAI_IMON_SLOT_SHIFT)
608 #define M98925_DAI_IMON_SLOT_16_17 (22 << M98925_DAI_IMON_SLOT_SHIFT)
609 #define M98925_DAI_IMON_SLOT_17_18 (23 << M98925_DAI_IMON_SLOT_SHIFT)
610 #define M98925_DAI_IMON_SLOT_18_19 (24 << M98925_DAI_IMON_SLOT_SHIFT)
611 #define M98925_DAI_IMON_SLOT_19_1A (25 << M98925_DAI_IMON_SLOT_SHIFT)
612 #define M98925_DAI_IMON_SLOT_1A_1B (26 << M98925_DAI_IMON_SLOT_SHIFT)
613 #define M98925_DAI_IMON_SLOT_1B_1C (27 << M98925_DAI_IMON_SLOT_SHIFT)
614 #define M98925_DAI_IMON_SLOT_1C_1D (28 << M98925_DAI_IMON_SLOT_SHIFT)
615 #define M98925_DAI_IMON_SLOT_1D_1E (29 << M98925_DAI_IMON_SLOT_SHIFT)
616 #define M98925_DAI_IMON_SLOT_1E_1F (30 << M98925_DAI_IMON_SLOT_SHIFT)
617 
618 /* MAX98925_R024_DOUT_CFG_VBAT */
619 #define M98925_DAI_VBAT_EN_MASK                                 (1<<5)
620 #define M98925_DAI_VBAT_EN_SHIFT                                5
621 #define M98925_DAI_VBAT_EN_WIDTH                                1
622 #define M98925_DAI_VBAT_SLOT_MASK                               (0x1F<<0)
623 #define M98925_DAI_VBAT_SLOT_SHIFT                              0
624 #define M98925_DAI_VBAT_SLOT_WIDTH                              5
625 
626 /* MAX98925_R025_DOUT_CFG_VBST */
627 #define M98925_DAI_VBST_EN_MASK                                 (1<<5)
628 #define M98925_DAI_VBST_EN_SHIFT                                5
629 #define M98925_DAI_VBST_EN_WIDTH                                1
630 #define M98925_DAI_VBST_SLOT_MASK                               (0x1F<<0)
631 #define M98925_DAI_VBST_SLOT_SHIFT                              0
632 #define M98925_DAI_VBST_SLOT_WIDTH                              5
633 
634 /* MAX98925_R026_DOUT_CFG_FLAG */
635 #define M98925_DAI_FLAG_EN_MASK                                 (1<<5)
636 #define M98925_DAI_FLAG_EN_SHIFT                                5
637 #define M98925_DAI_FLAG_EN_WIDTH                                1
638 #define M98925_DAI_FLAG_SLOT_MASK                               (0x1F<<0)
639 #define M98925_DAI_FLAG_SLOT_SHIFT                              0
640 #define M98925_DAI_FLAG_SLOT_WIDTH                              5
641 
642 /* MAX98925_R027_DOUT_HIZ_CFG1 */
643 #define M98925_DAI_SLOT_HIZ_CFG1_MASK                   (0xFF<<0)
644 #define M98925_DAI_SLOT_HIZ_CFG1_SHIFT                  0
645 #define M98925_DAI_SLOT_HIZ_CFG1_WIDTH                  8
646 
647 /* MAX98925_R028_DOUT_HIZ_CFG2 */
648 #define M98925_DAI_SLOT_HIZ_CFG2_MASK                   (0xFF<<0)
649 #define M98925_DAI_SLOT_HIZ_CFG2_SHIFT                  0
650 #define M98925_DAI_SLOT_HIZ_CFG2_WIDTH                  8
651 
652 /* MAX98925_R029_DOUT_HIZ_CFG3 */
653 #define M98925_DAI_SLOT_HIZ_CFG3_MASK                   (0xFF<<0)
654 #define M98925_DAI_SLOT_HIZ_CFG3_SHIFT                  0
655 #define M98925_DAI_SLOT_HIZ_CFG3_WIDTH                  8
656 
657 /* MAX98925_R02A_DOUT_HIZ_CFG4 */
658 #define M98925_DAI_SLOT_HIZ_CFG4_MASK                   (0xFF<<0)
659 #define M98925_DAI_SLOT_HIZ_CFG4_SHIFT                  0
660 #define M98925_DAI_SLOT_HIZ_CFG4_WIDTH                  8
661 
662 /* MAX98925_R02B_DOUT_DRV_STRENGTH */
663 #define M98925_DAI_OUT_DRIVE_MASK                               (0x03<<0)
664 #define M98925_DAI_OUT_DRIVE_SHIFT                              0
665 #define M98925_DAI_OUT_DRIVE_WIDTH                              2
666 
667 /* MAX98925_R02C_FILTERS */
668 #define M98925_ADC_DITHER_EN_MASK                               (1<<7)
669 #define M98925_ADC_DITHER_EN_SHIFT                              7
670 #define M98925_ADC_DITHER_EN_WIDTH                              1
671 #define M98925_IV_DCB_EN_MASK                                   (1<<6)
672 #define M98925_IV_DCB_EN_SHIFT                                  6
673 #define M98925_IV_DCB_EN_WIDTH                                  1
674 #define M98925_DAC_DITHER_EN_MASK                               (1<<4)
675 #define M98925_DAC_DITHER_EN_SHIFT                              4
676 #define M98925_DAC_DITHER_EN_WIDTH                              1
677 #define M98925_DAC_FILTER_MODE_MASK                             (1<<3)
678 #define M98925_DAC_FILTER_MODE_SHIFT                    3
679 #define M98925_DAC_FILTER_MODE_WIDTH                    1
680 #define M98925_DAC_HPF_MASK                             (0x07<<0)
681 #define M98925_DAC_HPF_SHIFT                                    0
682 #define M98925_DAC_HPF_WIDTH                                    3
683 #define M98925_DAC_HPF_DISABLE          (0 << M98925_DAC_HPF_SHIFT)
684 #define M98925_DAC_HPF_DC_BLOCK         (1 << M98925_DAC_HPF_SHIFT)
685 #define M98925_DAC_HPF_EN_100           (2 << M98925_DAC_HPF_SHIFT)
686 #define M98925_DAC_HPF_EN_200           (3 << M98925_DAC_HPF_SHIFT)
687 #define M98925_DAC_HPF_EN_400           (4 << M98925_DAC_HPF_SHIFT)
688 #define M98925_DAC_HPF_EN_800           (5 << M98925_DAC_HPF_SHIFT)
689 
690 /* MAX98925_R02D_GAIN */
691 #define M98925_DAC_IN_SEL_MASK                                  (0x03<<5)
692 #define M98925_DAC_IN_SEL_SHIFT                                 5
693 #define M98925_DAC_IN_SEL_WIDTH                                 2
694 #define M98925_SPK_GAIN_MASK                                    (0x1F<<0)
695 #define M98925_SPK_GAIN_SHIFT                                   0
696 #define M98925_SPK_GAIN_WIDTH                                   5
697 
698 #define M98925_DAC_IN_SEL_LEFT_DAI (0 << M98925_DAC_IN_SEL_SHIFT)
699 #define M98925_DAC_IN_SEL_RIGHT_DAI (1 << M98925_DAC_IN_SEL_SHIFT)
700 #define M98925_DAC_IN_SEL_SUMMED_DAI (2 << M98925_DAC_IN_SEL_SHIFT)
701 #define M98925_DAC_IN_SEL_DIV2_SUMMED_DAI (3 << M98925_DAC_IN_SEL_SHIFT)
702 
703 /* MAX98925_R02E_GAIN_RAMPING */
704 #define M98925_SPK_RMP_EN_MASK          (1<<1)
705 #define M98925_SPK_RMP_EN_SHIFT         1
706 #define M98925_SPK_RMP_EN_WIDTH         1
707 #define M98925_SPK_ZCD_EN_MASK          (1<<0)
708 #define M98925_SPK_ZCD_EN_SHIFT         0
709 #define M98925_SPK_ZCD_EN_WIDTH         1
710 
711 /* MAX98925_R02F_SPK_AMP */
712 #define M98925_SPK_MODE_MASK            (1<<0)
713 #define M98925_SPK_MODE_SHIFT           0
714 #define M98925_SPK_MODE_WIDTH           1
715 
716 /* MAX98925_R030_THRESHOLD */
717 #define M98925_ALC_EN_MASK                      (1<<5)
718 #define M98925_ALC_EN_SHIFT                     5
719 #define M98925_ALC_EN_WIDTH                     1
720 #define M98925_ALC_TH_MASK                      (0x1F<<0)
721 #define M98925_ALC_TH_SHIFT                     0
722 #define M98925_ALC_TH_WIDTH                     5
723 
724 /* MAX98925_R031_ALC_ATTACK */
725 #define M98925_ALC_ATK_STEP_MASK        (0x0F<<4)
726 #define M98925_ALC_ATK_STEP_SHIFT       4
727 #define M98925_ALC_ATK_STEP_WIDTH       4
728 #define M98925_ALC_ATK_RATE_MASK        (0x7<<0)
729 #define M98925_ALC_ATK_RATE_SHIFT       0
730 #define M98925_ALC_ATK_RATE_WIDTH       3
731 
732 /* MAX98925_R032_ALC_ATTEN_RLS */
733 #define M98925_ALC_MAX_ATTEN_MASK       (0x0F<<4)
734 #define M98925_ALC_MAX_ATTEN_SHIFT      4
735 #define M98925_ALC_MAX_ATTEN_WIDTH      4
736 #define M98925_ALC_RLS_RATE_MASK        (0x7<<0)
737 #define M98925_ALC_RLS_RATE_SHIFT       0
738 #define M98925_ALC_RLS_RATE_WIDTH       3
739 
740 /* MAX98925_R033_ALC_HOLD_RLS */
741 #define M98925_ALC_RLS_TGR_MASK         (1<<0)
742 #define M98925_ALC_RLS_TGR_SHIFT        0
743 #define M98925_ALC_RLS_TGR_WIDTH        1
744 
745 /* MAX98925_R034_ALC_CONFIGURATION */
746 #define M98925_ALC_MUTE_EN_MASK         (1<<7)
747 #define M98925_ALC_MUTE_EN_SHIFT        7
748 #define M98925_ALC_MUTE_EN_WIDTH        1
749 #define M98925_ALC_MUTE_DLY_MASK        (0x07<<4)
750 #define M98925_ALC_MUTE_DLY_SHIFT       4
751 #define M98925_ALC_MUTE_DLY_WIDTH       3
752 #define M98925_ALC_RLS_DBT_MASK         (0x07<<0)
753 #define M98925_ALC_RLS_DBT_SHIFT        0
754 #define M98925_ALC_RLS_DBT_WIDTH        3
755 
756 /* MAX98925_R035_BOOST_CONVERTER */
757 #define M98925_BST_SYNC_MASK            (1<<7)
758 #define M98925_BST_SYNC_SHIFT           7
759 #define M98925_BST_SYNC_WIDTH           1
760 #define M98925_BST_PHASE_MASK           (0x03<<4)
761 #define M98925_BST_PHASE_SHIFT          4
762 #define M98925_BST_PHASE_WIDTH          2
763 #define M98925_BST_SKIP_MODE_MASK       (0x03<<0)
764 #define M98925_BST_SKIP_MODE_SHIFT      0
765 #define M98925_BST_SKIP_MODE_WIDTH      2
766 
767 /* MAX98925_R036_BLOCK_ENABLE */
768 #define M98925_BST_EN_MASK                      (1<<7)
769 #define M98925_BST_EN_SHIFT                     7
770 #define M98925_BST_EN_WIDTH                     1
771 #define M98925_WATCH_EN_MASK            (1<<6)
772 #define M98925_WATCH_EN_SHIFT           6
773 #define M98925_WATCH_EN_WIDTH           1
774 #define M98925_CLKMON_EN_MASK           (1<<5)
775 #define M98925_CLKMON_EN_SHIFT          5
776 #define M98925_CLKMON_EN_WIDTH          1
777 #define M98925_SPK_EN_MASK                      (1<<4)
778 #define M98925_SPK_EN_SHIFT                     4
779 #define M98925_SPK_EN_WIDTH                     1
780 #define M98925_ADC_VBST_EN_MASK         (1<<3)
781 #define M98925_ADC_VBST_EN_SHIFT        3
782 #define M98925_ADC_VBST_EN_WIDTH        1
783 #define M98925_ADC_VBAT_EN_MASK         (1<<2)
784 #define M98925_ADC_VBAT_EN_SHIFT        2
785 #define M98925_ADC_VBAT_EN_WIDTH        1
786 #define M98925_ADC_IMON_EN_MASK         (1<<1)
787 #define M98925_ADC_IMON_EN_SHIFT        1
788 #define M98925_ADC_IMON_EN_WIDTH        1
789 #define M98925_ADC_VMON_EN_MASK         (1<<0)
790 #define M98925_ADC_VMON_EN_SHIFT        0
791 #define M98925_ADC_VMON_EN_WIDTH        1
792 
793 /* MAX98925_R037_CONFIGURATION */
794 #define M98925_BST_VOUT_MASK            (0x0F<<4)
795 #define M98925_BST_VOUT_SHIFT           4
796 #define M98925_BST_VOUT_WIDTH           4
797 #define M98925_THERMWARN_LEVEL_MASK     (0x03<<2)
798 #define M98925_THERMWARN_LEVEL_SHIFT                    2
799 #define M98925_THERMWARN_LEVEL_WIDTH                    2
800 #define M98925_WATCH_TIME_MASK                  (0x03<<0)
801 #define M98925_WATCH_TIME_SHIFT                 0
802 #define M98925_WATCH_TIME_WIDTH                 2
803 
804 /* MAX98925_R038_GLOBAL_ENABLE */
805 #define M98925_EN_MASK                  (1<<7)
806 #define M98925_EN_SHIFT                 7
807 #define M98925_EN_WIDTH                 1
808 
809 /* MAX98925_R03A_BOOST_LIMITER */
810 #define M98925_BST_ILIM_MASK    (0x1F<<3)
811 #define M98925_BST_ILIM_SHIFT   3
812 #define M98925_BST_ILIM_WIDTH   5
813 
814 /* MAX98925_R0FF_VERSION */
815 #define M98925_REV_ID_MASK      (0xFF<<0)
816 #define M98925_REV_ID_SHIFT     0
817 #define M98925_REV_ID_WIDTH     8
818 
819 struct max98925_priv {
820         struct regmap *regmap;
821         struct snd_soc_component *component;
822         struct max98925_pdata *pdata;
823         unsigned int sysclk;
824         unsigned int v_slot;
825         unsigned int i_slot;
826         unsigned int spk_gain;
827         unsigned int ch_size;
828 };
829 #endif
830 

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